1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "efuse.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "util.h" 15 16 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 17 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 18 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 19 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 20 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 21 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 22 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 26 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 29 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 31 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 33 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 34 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 35 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 36 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 37 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 38 }; 39 40 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 41 u32 val, enum rtw89_mac_mem_sel sel) 42 { 43 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44 u32 addr = mac->mem_base_addrs[sel] + offset; 45 46 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 47 rtw89_write32(rtwdev, mac->indir_access_addr, val); 48 } 49 50 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 51 enum rtw89_mac_mem_sel sel) 52 { 53 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 54 u32 addr = mac->mem_base_addrs[sel] + offset; 55 56 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 57 return rtw89_read32(rtwdev, mac->indir_access_addr); 58 } 59 60 static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 61 enum rtw89_mac_hwmod_sel sel) 62 { 63 u32 val, r_val; 64 65 if (sel == RTW89_DMAC_SEL) { 66 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 67 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 69 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 70 val = B_AX_CMAC_EN; 71 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 72 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 73 val = B_AX_CMAC1_FEN; 74 } else { 75 return -EINVAL; 76 } 77 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 78 (val & r_val) != val) 79 return -EFAULT; 80 81 return 0; 82 } 83 84 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 85 { 86 u8 lte_ctrl; 87 int ret; 88 89 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 90 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 91 if (ret) 92 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 93 94 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 95 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 96 97 return ret; 98 } 99 100 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 101 { 102 u8 lte_ctrl; 103 int ret; 104 105 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 106 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 107 if (ret) 108 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 109 110 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 111 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 112 113 return ret; 114 } 115 116 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 117 { 118 u32 ctrl_reg, data_reg, ctrl_data; 119 u32 val; 120 int ret; 121 122 switch (ctrl->type) { 123 case DLE_CTRL_TYPE_WDE: 124 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 125 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 126 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 127 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 128 B_AX_WDE_DFI_ACTIVE; 129 break; 130 case DLE_CTRL_TYPE_PLE: 131 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 132 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 133 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 134 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 135 B_AX_PLE_DFI_ACTIVE; 136 break; 137 default: 138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 139 return -EINVAL; 140 } 141 142 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 143 144 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 145 1, 1000, false, rtwdev, ctrl_reg); 146 if (ret) { 147 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 148 ctrl_reg, ctrl_data); 149 return ret; 150 } 151 152 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 153 return 0; 154 } 155 156 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 157 struct rtw89_mac_dle_dfi_quota *quota) 158 { 159 struct rtw89_mac_dle_dfi_ctrl ctrl; 160 int ret; 161 162 ctrl.type = quota->dle_type; 163 ctrl.target = DLE_DFI_TYPE_QUOTA; 164 ctrl.addr = quota->qtaid; 165 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 166 if (ret) { 167 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 168 return ret; 169 } 170 171 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 172 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 173 return 0; 174 } 175 176 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 177 struct rtw89_mac_dle_dfi_qempty *qempty) 178 { 179 struct rtw89_mac_dle_dfi_ctrl ctrl; 180 u32 ret; 181 182 ctrl.type = qempty->dle_type; 183 ctrl.target = DLE_DFI_TYPE_QEMPTY; 184 ctrl.addr = qempty->grpsel; 185 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 186 if (ret) { 187 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 188 return ret; 189 } 190 191 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 192 return 0; 193 } 194 195 static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 196 { 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 209 } 210 211 static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 212 { 213 struct rtw89_mac_dle_dfi_qempty qempty; 214 struct rtw89_mac_dle_dfi_quota quota; 215 struct rtw89_mac_dle_dfi_ctrl ctrl; 216 u32 val, not_empty, i; 217 int ret; 218 219 qempty.dle_type = DLE_CTRL_TYPE_PLE; 220 qempty.grpsel = 0; 221 qempty.qempty = ~(u32)0; 222 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 223 if (ret) 224 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 225 else 226 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 227 228 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 229 if (!(not_empty & BIT(0))) 230 continue; 231 ctrl.type = DLE_CTRL_TYPE_PLE; 232 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 233 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 234 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 235 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 236 if (ret) 237 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 238 else 239 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 240 u32_get_bits(ctrl.out_data, 241 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 242 } 243 244 quota.dle_type = DLE_CTRL_TYPE_PLE; 245 quota.qtaid = 6; 246 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 247 if (ret) 248 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 249 else 250 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 251 quota.rsv_pgnum, quota.use_pgnum); 252 253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 255 u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 257 u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 258 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 259 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 260 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 261 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 262 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 263 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 264 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 265 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 266 rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 267 268 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 269 quota.dle_type = DLE_CTRL_TYPE_PLE; 270 quota.qtaid = 7; 271 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 272 if (ret) 273 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 274 else 275 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 276 quota.rsv_pgnum, quota.use_pgnum); 277 278 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 279 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 280 u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 281 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 282 u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 283 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 284 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 285 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 286 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 287 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 288 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 289 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 290 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 291 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 292 } 293 294 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 295 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 296 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 298 299 dump_err_status_dispatcher_ax(rtwdev); 300 } 301 302 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 303 enum mac_ax_err_info err) 304 { 305 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 306 u32 dbg, event; 307 308 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 309 event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 310 311 switch (event) { 312 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 313 rtw89_info(rtwdev, "quota lost!\n"); 314 mac->dump_qta_lost(rtwdev); 315 break; 316 default: 317 break; 318 } 319 } 320 321 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 322 { 323 const struct rtw89_chip_info *chip = rtwdev->chip; 324 u32 dmac_err; 325 int i, ret; 326 327 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 328 if (ret) { 329 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 330 return; 331 } 332 333 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 334 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 335 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 337 338 if (dmac_err) { 339 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 341 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 343 if (chip->chip_id == RTL8852C) { 344 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 345 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 346 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 347 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 348 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 349 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 350 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 351 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 352 } 353 } 354 355 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 356 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 357 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 358 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 359 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 360 if (chip->chip_id == RTL8852C) 361 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 363 else 364 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 365 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 366 } 367 368 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 369 if (chip->chip_id == RTL8852C) { 370 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 371 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 372 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 373 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 374 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 376 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 377 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 378 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 380 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 382 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 384 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 385 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 386 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 388 389 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 390 B_AX_DBG_SEL0, 0x8B); 391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 392 B_AX_DBG_SEL1, 0x8B); 393 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 394 B_AX_SEL_0XC0_MASK, 1); 395 for (i = 0; i < 0x10; i++) { 396 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 397 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 398 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 399 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 400 } 401 } else if (chip->chip_id == RTL8922A) { 402 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 403 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 404 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 405 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 406 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 407 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 408 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 409 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 410 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 411 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 412 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 413 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 414 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 415 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 416 } else { 417 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 419 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 421 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 422 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 423 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 424 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 425 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 426 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 427 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 429 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 430 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 431 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 432 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 433 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 434 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 435 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 436 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 437 } 438 } 439 440 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 441 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 442 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 443 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 444 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 445 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 446 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 447 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 448 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 449 } 450 451 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 452 if (chip->chip_id == RTL8922A) { 453 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 454 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 455 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 456 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 457 } else { 458 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 459 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 460 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 461 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 462 } 463 } 464 465 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 466 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 468 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 469 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 470 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 471 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 472 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 474 } 475 476 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 477 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 478 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 479 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 480 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 481 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 482 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 483 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 484 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 485 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 486 } else { 487 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 489 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 491 } 492 } 493 494 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 495 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 496 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 497 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 499 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 501 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 503 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 505 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 507 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 508 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 509 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 510 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 511 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 512 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 513 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 514 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 515 if (chip->chip_id == RTL8922A) { 516 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 517 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 518 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 519 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 520 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 521 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 522 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 523 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 524 } else { 525 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 526 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 527 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 528 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 529 if (chip->chip_id == RTL8852C) { 530 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 531 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 532 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 533 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 534 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 535 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 536 } else { 537 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 538 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 539 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 540 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 541 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 542 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 543 } 544 } 545 } 546 547 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 548 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 549 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 550 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 551 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 552 } 553 554 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 555 if (chip->chip_id == RTL8922A) { 556 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 557 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 558 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 559 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 560 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 561 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 562 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 563 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 564 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 565 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 566 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 567 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 568 } else { 569 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 570 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 571 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 572 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 573 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 574 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 575 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 576 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 577 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 578 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 579 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 580 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 581 } 582 } 583 584 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 585 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 586 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 587 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 588 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 589 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 590 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 591 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 592 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 593 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 594 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 595 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 596 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 597 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 598 } else { 599 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 600 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 601 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 602 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 603 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 604 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 605 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 606 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 607 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 608 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 609 } 610 if (chip->chip_id == RTL8922A) { 611 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 612 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 613 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 614 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 615 } 616 } 617 618 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 619 if (chip->chip_id == RTL8922A) { 620 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 621 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 622 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 623 rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 624 } else if (chip->chip_id == RTL8852C) { 625 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 626 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 627 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 628 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 629 } 630 } 631 632 if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 633 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 634 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 635 RTW89_MAC_MEM_AXIDMA)); 636 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 637 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 638 RTW89_MAC_MEM_AXIDMA)); 639 } 640 641 if (dmac_err & B_BE_MLO_ERR_INT) { 642 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 643 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 644 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 645 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 646 } 647 648 if (dmac_err & B_BE_PLRLS_ERR_INT) { 649 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 650 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 651 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 652 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 653 } 654 } 655 656 static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 657 u8 band) 658 { 659 const struct rtw89_chip_info *chip = rtwdev->chip; 660 u32 offset = 0; 661 u32 cmac_err; 662 int ret; 663 664 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 665 if (ret) { 666 if (band) 667 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 668 else 669 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 670 return; 671 } 672 673 if (band) 674 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 675 676 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 677 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 678 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 679 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 680 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 681 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 682 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 683 684 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 685 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 686 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 687 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 688 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 689 } 690 691 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 692 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 693 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 694 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 695 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 696 } 697 698 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 699 if (chip->chip_id == RTL8852C) { 700 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 701 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 702 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 703 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 704 } else { 705 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 706 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 707 } 708 } 709 710 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 711 if (chip->chip_id == RTL8852C) { 712 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 713 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 714 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 715 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 716 } else { 717 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 718 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 719 } 720 } 721 722 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 723 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 724 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 725 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 726 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 727 } 728 729 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 730 if (chip->chip_id == RTL8852C) { 731 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 732 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 733 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 734 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 735 } else { 736 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 737 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 738 } 739 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 740 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 741 } 742 743 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 744 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 745 } 746 747 static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 748 enum mac_ax_err_info err) 749 { 750 if (err != MAC_AX_ERR_L1_ERR_DMAC && 751 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 752 err != MAC_AX_ERR_L0_ERR_CMAC0 && 753 err != MAC_AX_ERR_L0_ERR_CMAC1 && 754 err != MAC_AX_ERR_RXI300) 755 return; 756 757 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 758 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 759 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 760 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 761 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 762 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 763 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 764 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 765 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 766 767 rtw89_mac_dump_dmac_err_status(rtwdev); 768 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 769 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 770 771 rtwdev->hci.ops->dump_err_status(rtwdev); 772 773 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 774 rtw89_mac_dump_l0_to_l1(rtwdev, err); 775 776 rtw89_info(rtwdev, "<---\n"); 777 } 778 779 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 780 { 781 struct rtw89_ser *ser = &rtwdev->ser; 782 u32 dmac_err, imr, isr; 783 int ret; 784 785 if (rtwdev->chip->chip_id == RTL8852C) { 786 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 787 if (ret) 788 return true; 789 790 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 791 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 792 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 793 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 794 795 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 796 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 797 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 798 return true; 799 } 800 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 801 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 802 return true; 803 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 804 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 805 return true; 806 } 807 } 808 809 return false; 810 } 811 812 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 813 { 814 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 815 u32 err, err_scnr; 816 int ret; 817 818 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 819 false, rtwdev, R_AX_HALT_C2H_CTRL); 820 if (ret) { 821 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 822 return ret; 823 } 824 825 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 826 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 827 828 err_scnr = RTW89_ERROR_SCENARIO(err); 829 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 830 err = MAC_AX_ERR_CPU_EXCEPTION; 831 else if (err_scnr == RTW89_WCPU_ASSERTION) 832 err = MAC_AX_ERR_ASSERTION; 833 else if (err_scnr == RTW89_RXI300_ERROR) 834 err = MAC_AX_ERR_RXI300; 835 836 if (rtw89_mac_suppress_log(rtwdev, err)) 837 return err; 838 839 rtw89_fw_st_dbg_dump(rtwdev); 840 mac->dump_err_status(rtwdev, err); 841 842 return err; 843 } 844 EXPORT_SYMBOL(rtw89_mac_get_err_status); 845 846 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 847 { 848 struct rtw89_ser *ser = &rtwdev->ser; 849 u32 halt; 850 int ret = 0; 851 852 if (err > MAC_AX_SET_ERR_MAX) { 853 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 854 return -EINVAL; 855 } 856 857 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 858 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 859 if (ret) { 860 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 861 return -EFAULT; 862 } 863 864 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 865 866 if (ser->prehandle_l1 && 867 (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 868 return 0; 869 870 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 871 872 return 0; 873 } 874 EXPORT_SYMBOL(rtw89_mac_set_err_status); 875 876 static int hfc_reset_param(struct rtw89_dev *rtwdev) 877 { 878 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 879 struct rtw89_hfc_param_ini param_ini = {NULL}; 880 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 881 882 switch (rtwdev->hci.type) { 883 case RTW89_HCI_TYPE_PCIE: 884 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 885 param->en = 0; 886 break; 887 default: 888 return -EINVAL; 889 } 890 891 if (param_ini.pub_cfg) 892 param->pub_cfg = *param_ini.pub_cfg; 893 894 if (param_ini.prec_cfg) 895 param->prec_cfg = *param_ini.prec_cfg; 896 897 if (param_ini.ch_cfg) 898 param->ch_cfg = param_ini.ch_cfg; 899 900 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 901 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 902 param->mode = param_ini.mode; 903 904 return 0; 905 } 906 907 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 908 { 909 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 910 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 911 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 912 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 913 914 if (ch >= RTW89_DMA_CH_NUM) 915 return -EINVAL; 916 917 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 918 ch_cfg[ch].max > pub_cfg->pub_max) 919 return -EINVAL; 920 if (ch_cfg[ch].grp >= grp_num) 921 return -EINVAL; 922 923 return 0; 924 } 925 926 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 927 { 928 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 929 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 930 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 931 932 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 933 if (rtwdev->chip->chip_id == RTL8852A) 934 return 0; 935 else 936 return -EFAULT; 937 } 938 939 return 0; 940 } 941 942 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 943 { 944 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 945 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 946 947 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 948 return -EFAULT; 949 950 return 0; 951 } 952 953 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 954 { 955 const struct rtw89_chip_info *chip = rtwdev->chip; 956 const struct rtw89_page_regs *regs = chip->page_regs; 957 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 958 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 959 int ret = 0; 960 u32 val = 0; 961 962 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 963 if (ret) 964 return ret; 965 966 ret = hfc_ch_cfg_chk(rtwdev, ch); 967 if (ret) 968 return ret; 969 970 if (ch > RTW89_DMA_B1HI) 971 return -EINVAL; 972 973 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 974 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 975 (cfg[ch].grp ? B_AX_GRP : 0); 976 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 977 978 return 0; 979 } 980 981 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 982 { 983 const struct rtw89_chip_info *chip = rtwdev->chip; 984 const struct rtw89_page_regs *regs = chip->page_regs; 985 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 986 struct rtw89_hfc_ch_info *info = param->ch_info; 987 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 988 u32 val; 989 u32 ret; 990 991 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 992 if (ret) 993 return ret; 994 995 if (ch > RTW89_DMA_H2C) 996 return -EINVAL; 997 998 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 999 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 1000 if (ch < RTW89_DMA_H2C) 1001 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1002 else 1003 info[ch].used = cfg[ch].min - info[ch].aval; 1004 1005 return 0; 1006 } 1007 1008 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1009 { 1010 const struct rtw89_chip_info *chip = rtwdev->chip; 1011 const struct rtw89_page_regs *regs = chip->page_regs; 1012 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1013 u32 val; 1014 int ret; 1015 1016 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1017 if (ret) 1018 return ret; 1019 1020 ret = hfc_pub_cfg_chk(rtwdev); 1021 if (ret) 1022 return ret; 1023 1024 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1025 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1026 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1027 1028 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1029 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1030 1031 return 0; 1032 } 1033 1034 static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1035 { 1036 const struct rtw89_chip_info *chip = rtwdev->chip; 1037 const struct rtw89_page_regs *regs = chip->page_regs; 1038 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1039 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1040 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1041 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1042 u32 val; 1043 1044 val = rtw89_read32(rtwdev, regs->pub_page_info1); 1045 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1046 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1047 val = rtw89_read32(rtwdev, regs->pub_page_info3); 1048 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1049 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1050 info->pub_aval = 1051 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1052 B_AX_PUB_AVAL_PG_MASK); 1053 info->wp_aval = 1054 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1055 B_AX_WP_AVAL_PG_MASK); 1056 1057 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1058 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1059 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1060 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1061 prec_cfg->ch011_full_cond = 1062 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1063 prec_cfg->h2c_full_cond = 1064 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1065 prec_cfg->wp_ch07_full_cond = 1066 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1067 prec_cfg->wp_ch811_full_cond = 1068 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1069 1070 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1071 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1072 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1073 1074 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1075 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1076 1077 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1078 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1079 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1080 1081 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1082 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1083 1084 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1085 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1086 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 1087 } 1088 1089 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 1090 { 1091 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1092 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1093 int ret; 1094 1095 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1096 if (ret) 1097 return ret; 1098 1099 mac->hfc_get_mix_info(rtwdev); 1100 1101 ret = hfc_pub_info_chk(rtwdev); 1102 if (param->en && ret) 1103 return ret; 1104 1105 return 0; 1106 } 1107 1108 static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1109 { 1110 const struct rtw89_chip_info *chip = rtwdev->chip; 1111 const struct rtw89_page_regs *regs = chip->page_regs; 1112 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1113 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1114 u32 val; 1115 1116 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1117 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1118 1119 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1120 B_AX_HCI_FC_CH12_FULL_COND_MASK, 1121 prec_cfg->h2c_full_cond); 1122 } 1123 1124 static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1125 { 1126 const struct rtw89_chip_info *chip = rtwdev->chip; 1127 const struct rtw89_page_regs *regs = chip->page_regs; 1128 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1129 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1130 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1131 u32 val; 1132 1133 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1134 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1135 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1136 1137 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1138 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1139 1140 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1141 B_AX_PREC_PAGE_WP_CH07_MASK) | 1142 u32_encode_bits(prec_cfg->wp_ch811_prec, 1143 B_AX_PREC_PAGE_WP_CH811_MASK); 1144 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1145 1146 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1147 param->mode, B_AX_HCI_FC_MODE_MASK); 1148 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1149 B_AX_HCI_FC_WD_FULL_COND_MASK); 1150 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1151 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1152 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1153 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1154 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1155 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1156 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1157 } 1158 1159 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1160 { 1161 const struct rtw89_chip_info *chip = rtwdev->chip; 1162 const struct rtw89_page_regs *regs = chip->page_regs; 1163 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1164 u32 val; 1165 1166 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1167 param->en = en; 1168 param->h2c_en = h2c_en; 1169 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1170 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1171 (val & ~B_AX_HCI_FC_CH12_EN); 1172 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1173 } 1174 1175 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1176 { 1177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1178 const struct rtw89_chip_info *chip = rtwdev->chip; 1179 u32 dma_ch_mask = chip->dma_ch_mask; 1180 u8 ch; 1181 u32 ret = 0; 1182 1183 if (reset) 1184 ret = hfc_reset_param(rtwdev); 1185 if (ret) 1186 return ret; 1187 1188 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1189 if (ret) 1190 return ret; 1191 1192 mac->hfc_func_en(rtwdev, false, false); 1193 1194 if (!en && h2c_en) { 1195 mac->hfc_h2c_cfg(rtwdev); 1196 mac->hfc_func_en(rtwdev, en, h2c_en); 1197 return ret; 1198 } 1199 1200 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1201 if (dma_ch_mask & BIT(ch)) 1202 continue; 1203 ret = hfc_ch_ctrl(rtwdev, ch); 1204 if (ret) 1205 return ret; 1206 } 1207 1208 ret = hfc_pub_ctrl(rtwdev); 1209 if (ret) 1210 return ret; 1211 1212 mac->hfc_mix_cfg(rtwdev); 1213 if (en || h2c_en) { 1214 mac->hfc_func_en(rtwdev, en, h2c_en); 1215 udelay(10); 1216 } 1217 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1218 if (dma_ch_mask & BIT(ch)) 1219 continue; 1220 ret = hfc_upd_ch_info(rtwdev, ch); 1221 if (ret) 1222 return ret; 1223 } 1224 ret = hfc_upd_mix_info(rtwdev); 1225 1226 return ret; 1227 } 1228 1229 #define PWR_POLL_CNT 2000 1230 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1231 const struct rtw89_pwr_cfg *cfg) 1232 { 1233 u8 val = 0; 1234 int ret; 1235 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1236 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1237 1238 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1239 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1240 1241 if (!ret) 1242 return 0; 1243 1244 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1245 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1246 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1247 1248 return -EBUSY; 1249 } 1250 1251 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1252 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1253 { 1254 const struct rtw89_pwr_cfg *cur_cfg; 1255 u32 addr; 1256 u8 val; 1257 1258 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1259 if (!(cur_cfg->intf_msk & intf_msk) || 1260 !(cur_cfg->cv_msk & cv_msk)) 1261 continue; 1262 1263 switch (cur_cfg->cmd) { 1264 case PWR_CMD_WRITE: 1265 addr = cur_cfg->addr; 1266 1267 if (cur_cfg->base == PWR_BASE_SDIO) 1268 addr |= SDIO_LOCAL_BASE_ADDR; 1269 1270 val = rtw89_read8(rtwdev, addr); 1271 val &= ~(cur_cfg->msk); 1272 val |= (cur_cfg->val & cur_cfg->msk); 1273 1274 rtw89_write8(rtwdev, addr, val); 1275 break; 1276 case PWR_CMD_POLL: 1277 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1278 return -EBUSY; 1279 break; 1280 case PWR_CMD_DELAY: 1281 if (cur_cfg->val == PWR_DELAY_US) 1282 udelay(cur_cfg->addr); 1283 else 1284 fsleep(cur_cfg->addr * 1000); 1285 break; 1286 default: 1287 return -EINVAL; 1288 } 1289 } 1290 1291 return 0; 1292 } 1293 1294 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1295 const struct rtw89_pwr_cfg * const *cfg_seq) 1296 { 1297 int ret; 1298 1299 for (; *cfg_seq; cfg_seq++) { 1300 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1301 PWR_INTF_MSK_PCIE, *cfg_seq); 1302 if (ret) 1303 return -EBUSY; 1304 } 1305 1306 return 0; 1307 } 1308 1309 static enum rtw89_rpwm_req_pwr_state 1310 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1311 { 1312 enum rtw89_rpwm_req_pwr_state state; 1313 1314 switch (rtwdev->ps_mode) { 1315 case RTW89_PS_MODE_RFOFF: 1316 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1317 break; 1318 case RTW89_PS_MODE_CLK_GATED: 1319 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1320 break; 1321 case RTW89_PS_MODE_PWR_GATED: 1322 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1323 break; 1324 default: 1325 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1326 break; 1327 } 1328 return state; 1329 } 1330 1331 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1332 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1333 bool notify_wake) 1334 { 1335 u16 request; 1336 1337 spin_lock_bh(&rtwdev->rpwm_lock); 1338 1339 request = rtw89_read16(rtwdev, R_AX_RPWM); 1340 request ^= request | PS_RPWM_TOGGLE; 1341 request |= req_pwr_state; 1342 1343 if (notify_wake) { 1344 request |= PS_RPWM_NOTIFY_WAKE; 1345 } else { 1346 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1347 RPWM_SEQ_NUM_MAX; 1348 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1349 rtwdev->mac.rpwm_seq_num); 1350 1351 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1352 request |= PS_RPWM_ACK; 1353 } 1354 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1355 1356 spin_unlock_bh(&rtwdev->rpwm_lock); 1357 } 1358 1359 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1360 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1361 { 1362 bool request_deep_mode; 1363 bool in_deep_mode; 1364 u8 rpwm_req_num; 1365 u8 cpwm_rsp_seq; 1366 u8 cpwm_seq; 1367 u8 cpwm_status; 1368 1369 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1370 request_deep_mode = true; 1371 else 1372 request_deep_mode = false; 1373 1374 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1375 in_deep_mode = true; 1376 else 1377 in_deep_mode = false; 1378 1379 if (request_deep_mode != in_deep_mode) 1380 return -EPERM; 1381 1382 if (request_deep_mode) 1383 return 0; 1384 1385 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1386 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1387 PS_CPWM_RSP_SEQ_NUM); 1388 1389 if (rpwm_req_num != cpwm_rsp_seq) 1390 return -EPERM; 1391 1392 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1393 CPWM_SEQ_NUM_MAX; 1394 1395 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1396 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1397 return -EPERM; 1398 1399 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1400 if (cpwm_status != req_pwr_state) 1401 return -EPERM; 1402 1403 return 0; 1404 } 1405 1406 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1407 { 1408 enum rtw89_rpwm_req_pwr_state state; 1409 unsigned long delay = enter ? 10 : 150; 1410 int ret; 1411 int i; 1412 1413 if (enter) 1414 state = rtw89_mac_get_req_pwr_state(rtwdev); 1415 else 1416 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1417 1418 for (i = 0; i < RPWM_TRY_CNT; i++) { 1419 rtw89_mac_send_rpwm(rtwdev, state, false); 1420 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1421 !ret, delay, 15000, false, 1422 rtwdev, state); 1423 if (!ret) 1424 break; 1425 1426 if (i == RPWM_TRY_CNT - 1) 1427 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1428 enter ? "entering" : "leaving"); 1429 else 1430 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1431 "%d time firmware failed to ack for %s ps mode\n", 1432 i + 1, enter ? "entering" : "leaving"); 1433 } 1434 } 1435 1436 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1437 { 1438 enum rtw89_rpwm_req_pwr_state state; 1439 1440 state = rtw89_mac_get_req_pwr_state(rtwdev); 1441 rtw89_mac_send_rpwm(rtwdev, state, true); 1442 } 1443 1444 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1445 { 1446 #define PWR_ACT 1 1447 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1448 const struct rtw89_chip_info *chip = rtwdev->chip; 1449 const struct rtw89_pwr_cfg * const *cfg_seq; 1450 int (*cfg_func)(struct rtw89_dev *rtwdev); 1451 int ret; 1452 u8 val; 1453 1454 if (on) { 1455 cfg_seq = chip->pwr_on_seq; 1456 cfg_func = chip->ops->pwr_on_func; 1457 } else { 1458 cfg_seq = chip->pwr_off_seq; 1459 cfg_func = chip->ops->pwr_off_func; 1460 } 1461 1462 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1463 __rtw89_leave_ps_mode(rtwdev); 1464 1465 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1466 if (on && val == PWR_ACT) { 1467 rtw89_err(rtwdev, "MAC has already powered on\n"); 1468 return -EBUSY; 1469 } 1470 1471 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1472 if (ret) 1473 return ret; 1474 1475 if (on) { 1476 if (!test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags)) 1477 mac->efuse_read_fw_secure(rtwdev); 1478 1479 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1480 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1481 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1482 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1483 } else { 1484 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1485 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1486 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1487 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1488 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1489 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1490 rtw89_set_entity_state(rtwdev, RTW89_PHY_0, false); 1491 rtw89_set_entity_state(rtwdev, RTW89_PHY_1, false); 1492 } 1493 1494 return 0; 1495 #undef PWR_ACT 1496 } 1497 1498 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1499 { 1500 rtw89_mac_power_switch(rtwdev, false); 1501 } 1502 1503 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1504 { 1505 u32 func_en = 0; 1506 u32 ck_en = 0; 1507 u32 c1pc_en = 0; 1508 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1509 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1510 1511 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1512 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1513 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1514 B_AX_CMAC_CRPRT; 1515 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1516 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1517 B_AX_RMAC_CKEN; 1518 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1519 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1520 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1521 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1522 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1523 1524 if (en) { 1525 if (mac_idx == RTW89_MAC_1) { 1526 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1527 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1528 B_AX_R_SYM_ISO_CMAC12PP); 1529 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1530 B_AX_CMAC1_FEN); 1531 } 1532 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1533 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1534 } else { 1535 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1536 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1537 if (mac_idx == RTW89_MAC_1) { 1538 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1539 B_AX_CMAC1_FEN); 1540 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1541 B_AX_R_SYM_ISO_CMAC12PP); 1542 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1543 } 1544 } 1545 1546 return 0; 1547 } 1548 1549 static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1550 { 1551 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1552 u32 val32; 1553 1554 if (chip_id == RTL8852C) 1555 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1556 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1557 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1558 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1559 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1560 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1561 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1562 else 1563 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1564 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1565 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1566 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1567 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1568 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1569 B_AX_DMAC_CRPRT); 1570 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1571 1572 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1573 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1574 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1575 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1576 if (chip_id == RTL8852BT) 1577 val32 |= B_AX_AXIDMA_CLK_EN; 1578 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1579 1580 return 0; 1581 } 1582 1583 static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1584 { 1585 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1586 1587 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 1588 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1589 B_AX_OCP_L1_MASK); 1590 1591 return 0; 1592 } 1593 1594 static int sys_init_ax(struct rtw89_dev *rtwdev) 1595 { 1596 int ret; 1597 1598 ret = dmac_func_en_ax(rtwdev); 1599 if (ret) 1600 return ret; 1601 1602 ret = cmac_func_en_ax(rtwdev, 0, true); 1603 if (ret) 1604 return ret; 1605 1606 ret = chip_func_en_ax(rtwdev); 1607 if (ret) 1608 return ret; 1609 1610 return ret; 1611 } 1612 1613 const struct rtw89_mac_size_set rtw89_mac_size = { 1614 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1615 .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0}, 1616 .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0}, 1617 /* PCIE 64 */ 1618 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1619 .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1620 /* DLFW */ 1621 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1622 .wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1623 /* PCIE 64 */ 1624 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1625 /* 8852B PCIE SCC */ 1626 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1627 /* DLFW */ 1628 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1629 /* 8852C DLFW */ 1630 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1631 /* 8852C PCIE SCC */ 1632 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1633 .wde_size23 = {RTW89_WDE_PG_64, 1022, 2,}, 1634 /* PCIE */ 1635 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1636 .ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,}, 1637 .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1638 /* DLFW */ 1639 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1640 /* PCIE 64 */ 1641 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1642 /* DLFW */ 1643 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1644 .ple_size9 = {RTW89_PLE_PG_128, 2288, 16,}, 1645 /* 8852C DLFW */ 1646 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1647 /* 8852C PCIE SCC */ 1648 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1649 /* PCIE 64 */ 1650 .wde_qt0 = {3792, 196, 0, 107,}, 1651 .wde_qt0_v1 = {3302, 6, 0, 20,}, 1652 /* DLFW */ 1653 .wde_qt4 = {0, 0, 0, 0,}, 1654 /* PCIE 64 */ 1655 .wde_qt6 = {448, 48, 0, 16,}, 1656 /* 8852B PCIE SCC */ 1657 .wde_qt7 = {446, 48, 0, 16,}, 1658 /* 8852C DLFW */ 1659 .wde_qt17 = {0, 0, 0, 0,}, 1660 /* 8852C PCIE SCC */ 1661 .wde_qt18 = {3228, 60, 0, 40,}, 1662 .wde_qt23 = {958, 48, 0, 16,}, 1663 .ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,}, 1664 .ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,}, 1665 /* PCIE SCC */ 1666 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1667 /* PCIE SCC */ 1668 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1669 .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1670 /* DLFW */ 1671 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1672 /* PCIE 64 */ 1673 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1674 /* DLFW 52C */ 1675 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1676 /* DLFW 52C */ 1677 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1678 /* 8852C PCIE SCC */ 1679 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1680 /* 8852C PCIE SCC */ 1681 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1682 .ple_qt57 = {147, 0, 16, 20, 13, 13, 178, 0, 32, 14, 8, 0,}, 1683 /* PCIE 64 */ 1684 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1685 .ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,}, 1686 /* 8852A PCIE WOW */ 1687 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1688 /* 8852B PCIE WOW */ 1689 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1690 /* 8852BT PCIE WOW */ 1691 .ple_qt_52bt_wow = {147, 0, 32, 20, 1860, 13, 1929, 0, 1879, 14, 24, 0,}, 1692 /* 8851B PCIE WOW */ 1693 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1694 .ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,}, 1695 .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1696 .rsvd0_size0 = {212992, 0,}, 1697 .rsvd1_size0 = {587776, 2048,}, 1698 }; 1699 EXPORT_SYMBOL(rtw89_mac_size); 1700 1701 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1702 enum rtw89_qta_mode mode) 1703 { 1704 struct rtw89_mac_info *mac = &rtwdev->mac; 1705 const struct rtw89_dle_mem *cfg; 1706 1707 cfg = &rtwdev->chip->dle_mem[mode]; 1708 if (!cfg) 1709 return NULL; 1710 1711 if (cfg->mode != mode) { 1712 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1713 return NULL; 1714 } 1715 1716 mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1717 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1718 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1719 mac->dle_info.qta_mode = mode; 1720 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1721 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1722 1723 return cfg; 1724 } 1725 1726 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1727 enum rtw89_mac_dle_rsvd_qt_type type, 1728 struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1729 { 1730 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1731 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1732 1733 switch (type) { 1734 case DLE_RSVD_QT_MPDU_INFO: 1735 cfg->pktid = dle_info->ple_free_pg; 1736 cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1737 break; 1738 case DLE_RSVD_QT_B0_CSI: 1739 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1740 cfg->pg_num = rsvd_qt->b0_csi; 1741 break; 1742 case DLE_RSVD_QT_B1_CSI: 1743 cfg->pktid = dle_info->ple_free_pg + 1744 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1745 cfg->pg_num = rsvd_qt->b1_csi; 1746 break; 1747 case DLE_RSVD_QT_B0_LMR: 1748 cfg->pktid = dle_info->ple_free_pg + 1749 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1750 cfg->pg_num = rsvd_qt->b0_lmr; 1751 break; 1752 case DLE_RSVD_QT_B1_LMR: 1753 cfg->pktid = dle_info->ple_free_pg + 1754 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1755 rsvd_qt->b0_lmr; 1756 cfg->pg_num = rsvd_qt->b1_lmr; 1757 break; 1758 case DLE_RSVD_QT_B0_FTM: 1759 cfg->pktid = dle_info->ple_free_pg + 1760 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1761 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1762 cfg->pg_num = rsvd_qt->b0_ftm; 1763 break; 1764 case DLE_RSVD_QT_B1_FTM: 1765 cfg->pktid = dle_info->ple_free_pg + 1766 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1767 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1768 cfg->pg_num = rsvd_qt->b1_ftm; 1769 break; 1770 default: 1771 return -EINVAL; 1772 } 1773 1774 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1775 1776 return 0; 1777 } 1778 1779 static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 1780 { 1781 struct rtw89_mac_dle_dfi_qempty qempty; 1782 u32 grpnum, qtmp, val32, msk32; 1783 int i, j, ret; 1784 1785 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 1786 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1787 1788 for (i = 0; i < grpnum; i++) { 1789 qempty.grpsel = i; 1790 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1791 if (ret) { 1792 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1793 return false; 1794 } 1795 qtmp = qempty.qempty; 1796 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1797 val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 1798 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1799 return false; 1800 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1801 } 1802 } 1803 1804 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 1805 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1806 if (ret) { 1807 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1808 return false; 1809 } 1810 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1811 if ((qempty.qempty & msk32) != msk32) 1812 return false; 1813 1814 if (rtwdev->dbcc_en) { 1815 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1816 if ((qempty.qempty & msk32) != msk32) 1817 return false; 1818 } 1819 1820 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1821 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1822 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1823 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1824 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1825 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1826 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1827 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1828 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1829 1830 return (val32 & msk32) == msk32; 1831 } 1832 1833 static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 1834 { 1835 const struct rtw89_dle_size *wde = cfg->wde_size; 1836 const struct rtw89_dle_size *ple = cfg->ple_size; 1837 u32 used; 1838 1839 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1840 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1841 1842 if (cfg->rsvd0_size && cfg->rsvd1_size) { 1843 used += cfg->rsvd0_size->size; 1844 used += cfg->rsvd1_size->size; 1845 } 1846 1847 return used; 1848 } 1849 1850 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1851 enum rtw89_qta_mode mode) 1852 { 1853 u32 size = rtwdev->chip->fifo_size; 1854 1855 if (mode == RTW89_QTA_SCC) 1856 size -= rtwdev->chip->dle_scc_rsvd_size; 1857 1858 return size; 1859 } 1860 1861 static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 1862 { 1863 if (enable) 1864 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1865 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1866 else 1867 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1868 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1869 } 1870 1871 static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 1872 { 1873 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1874 1875 if (enable) { 1876 if (rtwdev->chip->chip_id == RTL8851B) 1877 val |= B_AX_AXIDMA_CLK_EN; 1878 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1879 } else { 1880 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1881 } 1882 } 1883 1884 static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1885 { 1886 const struct rtw89_dle_size *size_cfg; 1887 u32 val; 1888 u8 bound = 0; 1889 1890 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1891 size_cfg = cfg->wde_size; 1892 1893 switch (size_cfg->pge_size) { 1894 default: 1895 case RTW89_WDE_PG_64: 1896 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1897 B_AX_WDE_PAGE_SEL_MASK); 1898 break; 1899 case RTW89_WDE_PG_128: 1900 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1901 B_AX_WDE_PAGE_SEL_MASK); 1902 break; 1903 case RTW89_WDE_PG_256: 1904 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1905 return -EINVAL; 1906 } 1907 1908 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1909 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1910 B_AX_WDE_FREE_PAGE_NUM_MASK); 1911 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1912 1913 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1914 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1915 * size_cfg->pge_size / DLE_BOUND_UNIT; 1916 size_cfg = cfg->ple_size; 1917 1918 switch (size_cfg->pge_size) { 1919 default: 1920 case RTW89_PLE_PG_64: 1921 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1922 return -EINVAL; 1923 case RTW89_PLE_PG_128: 1924 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1925 B_AX_PLE_PAGE_SEL_MASK); 1926 break; 1927 case RTW89_PLE_PG_256: 1928 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1929 B_AX_PLE_PAGE_SEL_MASK); 1930 break; 1931 } 1932 1933 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1934 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1935 B_AX_PLE_FREE_PAGE_NUM_MASK); 1936 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1937 1938 return 0; 1939 } 1940 1941 static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 1942 { 1943 u32 reg, mask; 1944 u32 ini; 1945 1946 if (wde_or_ple) { 1947 reg = R_AX_WDE_INI_STATUS; 1948 mask = WDE_MGN_INI_RDY; 1949 } else { 1950 reg = R_AX_PLE_INI_STATUS; 1951 mask = PLE_MGN_INI_RDY; 1952 } 1953 1954 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 1955 2000, false, rtwdev, reg); 1956 } 1957 1958 #define INVALID_QT_WCPU U16_MAX 1959 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1960 do { \ 1961 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1962 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1963 rtw89_write32(rtwdev, \ 1964 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1965 val); \ 1966 } while (0) 1967 #define SET_QUOTA(_x, _module, _idx) \ 1968 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1969 1970 static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 1971 const struct rtw89_wde_quota *min_cfg, 1972 const struct rtw89_wde_quota *max_cfg, 1973 u16 ext_wde_min_qt_wcpu) 1974 { 1975 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1976 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1977 u32 val; 1978 1979 SET_QUOTA(hif, WDE, 0); 1980 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1981 SET_QUOTA(pkt_in, WDE, 3); 1982 SET_QUOTA(cpu_io, WDE, 4); 1983 } 1984 1985 static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 1986 const struct rtw89_ple_quota *min_cfg, 1987 const struct rtw89_ple_quota *max_cfg) 1988 { 1989 u32 val; 1990 1991 SET_QUOTA(cma0_tx, PLE, 0); 1992 SET_QUOTA(cma1_tx, PLE, 1); 1993 SET_QUOTA(c2h, PLE, 2); 1994 SET_QUOTA(h2c, PLE, 3); 1995 SET_QUOTA(wcpu, PLE, 4); 1996 SET_QUOTA(mpdu_proc, PLE, 5); 1997 SET_QUOTA(cma0_dma, PLE, 6); 1998 SET_QUOTA(cma1_dma, PLE, 7); 1999 SET_QUOTA(bb_rpt, PLE, 8); 2000 SET_QUOTA(wd_rel, PLE, 9); 2001 SET_QUOTA(cpu_io, PLE, 10); 2002 if (rtwdev->chip->chip_id == RTL8852C) 2003 SET_QUOTA(tx_rpt, PLE, 11); 2004 } 2005 2006 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 2007 { 2008 const struct rtw89_ple_quota *min_cfg, *max_cfg; 2009 const struct rtw89_dle_mem *cfg; 2010 u32 val; 2011 2012 if (rtwdev->chip->chip_id == RTL8852C) 2013 return 0; 2014 2015 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 2016 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 2017 return -EINVAL; 2018 } 2019 2020 if (wow) 2021 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 2022 else 2023 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 2024 if (!cfg) { 2025 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2026 return -EINVAL; 2027 } 2028 2029 min_cfg = cfg->ple_min_qt; 2030 max_cfg = cfg->ple_max_qt; 2031 SET_QUOTA(cma0_dma, PLE, 6); 2032 SET_QUOTA(cma1_dma, PLE, 7); 2033 2034 return 0; 2035 } 2036 #undef SET_QUOTA 2037 2038 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 2039 { 2040 const struct rtw89_chip_info *chip = rtwdev->chip; 2041 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 2042 2043 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 2044 return; 2045 2046 /* 8852C enable B_AX_UC_MGNT_DEC by default */ 2047 if (chip->chip_id == RTL8852C) 2048 msk32 = B_AX_BMC_MGNT_DEC; 2049 2050 if (enable) 2051 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2052 else 2053 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2054 } 2055 2056 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2057 const struct rtw89_dle_mem *cfg, 2058 u16 ext_wde_min_qt_wcpu) 2059 { 2060 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2061 2062 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 2063 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2064 } 2065 2066 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2067 enum rtw89_qta_mode ext_mode) 2068 { 2069 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2070 const struct rtw89_dle_mem *cfg, *ext_cfg; 2071 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 2072 int ret; 2073 2074 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2075 if (ret) 2076 return ret; 2077 2078 cfg = get_dle_mem_cfg(rtwdev, mode); 2079 if (!cfg) { 2080 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2081 ret = -EINVAL; 2082 goto error; 2083 } 2084 2085 if (mode == RTW89_QTA_DLFW) { 2086 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2087 if (!ext_cfg) { 2088 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2089 ext_mode); 2090 ret = -EINVAL; 2091 goto error; 2092 } 2093 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2094 } 2095 2096 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2097 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2098 ret = -EINVAL; 2099 goto error; 2100 } 2101 2102 mac->dle_func_en(rtwdev, false); 2103 mac->dle_clk_en(rtwdev, true); 2104 2105 ret = mac->dle_mix_cfg(rtwdev, cfg); 2106 if (ret) { 2107 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2108 goto error; 2109 } 2110 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2111 2112 mac->dle_func_en(rtwdev, true); 2113 2114 ret = mac->chk_dle_rdy(rtwdev, true); 2115 if (ret) { 2116 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2117 return ret; 2118 } 2119 2120 ret = mac->chk_dle_rdy(rtwdev, false); 2121 if (ret) { 2122 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2123 return ret; 2124 } 2125 2126 return 0; 2127 error: 2128 mac->dle_func_en(rtwdev, false); 2129 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2130 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2131 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2132 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2133 2134 return ret; 2135 } 2136 2137 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2138 enum rtw89_qta_mode mode) 2139 { 2140 u32 reg, max_preld_size, min_rsvd_size; 2141 2142 max_preld_size = (mac_idx == RTW89_MAC_0 ? 2143 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2144 reg = mac_idx == RTW89_MAC_0 ? 2145 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2146 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2147 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2148 2149 min_rsvd_size = PRELD_AMSDU_SIZE; 2150 reg = mac_idx == RTW89_MAC_0 ? 2151 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2152 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2153 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2154 2155 return 0; 2156 } 2157 2158 static bool is_qta_poh(struct rtw89_dev *rtwdev) 2159 { 2160 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2161 } 2162 2163 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2164 enum rtw89_qta_mode mode) 2165 { 2166 const struct rtw89_chip_info *chip = rtwdev->chip; 2167 2168 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) || 2169 !is_qta_poh(rtwdev)) 2170 return 0; 2171 2172 return preload_init_set(rtwdev, mac_idx, mode); 2173 } 2174 2175 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2176 { 2177 u32 msk32; 2178 u32 val32; 2179 2180 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2181 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2182 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2183 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2184 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2185 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2186 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2187 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2188 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2189 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2190 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2191 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2192 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2193 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2194 2195 if ((val32 & msk32) == msk32) 2196 return true; 2197 2198 return false; 2199 } 2200 2201 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2202 { 2203 const struct rtw89_chip_info *chip = rtwdev->chip; 2204 2205 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 2206 return; 2207 2208 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2209 SS2F_PATH_WLCPU); 2210 } 2211 2212 static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2213 { 2214 u32 p_val; 2215 u8 val; 2216 int ret; 2217 2218 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2219 if (ret) 2220 return ret; 2221 2222 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2223 val |= B_AX_SS_EN; 2224 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2225 2226 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2227 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2228 if (ret) { 2229 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2230 return ret; 2231 } 2232 2233 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 2234 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2235 2236 _patch_ss2f_path(rtwdev); 2237 2238 return 0; 2239 } 2240 2241 static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2242 { 2243 int ret; 2244 2245 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2246 if (ret) 2247 return ret; 2248 2249 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2250 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2251 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2252 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2253 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2254 2255 return 0; 2256 } 2257 2258 static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2259 { 2260 const struct rtw89_chip_info *chip = rtwdev->chip; 2261 u32 val = 0; 2262 int ret; 2263 2264 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2265 if (ret) 2266 return ret; 2267 2268 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2269 /* init clock */ 2270 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2271 /* init TX encryption */ 2272 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2273 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2274 if (chip->chip_id == RTL8852C) 2275 val |= B_AX_UC_MGNT_DEC; 2276 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2277 chip->chip_id == RTL8851B) 2278 val &= ~B_AX_TX_PARTIAL_MODE; 2279 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2280 2281 /* init MIC ICV append */ 2282 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2283 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2284 2285 /* option init */ 2286 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2287 2288 if (chip->chip_id == RTL8852C) 2289 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2290 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2291 2292 return 0; 2293 } 2294 2295 static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2296 { 2297 int ret; 2298 2299 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2300 if (ret) { 2301 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2302 return ret; 2303 } 2304 2305 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2306 if (ret) { 2307 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2308 return ret; 2309 } 2310 2311 ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2312 if (ret) { 2313 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2314 return ret; 2315 } 2316 2317 ret = sta_sch_init_ax(rtwdev); 2318 if (ret) { 2319 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2320 return ret; 2321 } 2322 2323 ret = mpdu_proc_init_ax(rtwdev); 2324 if (ret) { 2325 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2326 return ret; 2327 } 2328 2329 ret = sec_eng_init_ax(rtwdev); 2330 if (ret) { 2331 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2332 return ret; 2333 } 2334 2335 return ret; 2336 } 2337 2338 static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2339 { 2340 u32 val, reg; 2341 u16 p_val; 2342 int ret; 2343 2344 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2345 if (ret) 2346 return ret; 2347 2348 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2349 2350 val = rtw89_read32(rtwdev, reg); 2351 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2352 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2353 rtw89_write32(rtwdev, reg, val); 2354 2355 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2356 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2357 if (ret) { 2358 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2359 return ret; 2360 } 2361 2362 return 0; 2363 } 2364 2365 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2366 { 2367 u32 ret; 2368 u32 reg; 2369 u32 val; 2370 2371 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2372 if (ret) 2373 return ret; 2374 2375 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2376 if (rtwdev->chip->chip_id == RTL8852C) 2377 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2378 SIFS_MACTXEN_T1_V1); 2379 else 2380 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2381 SIFS_MACTXEN_T1); 2382 2383 if (rtw89_is_rtl885xb(rtwdev)) { 2384 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2385 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2386 } 2387 2388 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2389 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2390 2391 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2392 if (rtwdev->chip->chip_id == RTL8852C) { 2393 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2394 B_AX_TX_PARTIAL_MODE); 2395 if (!val) 2396 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2397 SCH_PREBKF_24US); 2398 } else { 2399 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2400 SCH_PREBKF_24US); 2401 } 2402 2403 return 0; 2404 } 2405 2406 static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2407 enum rtw89_machdr_frame_type type, 2408 enum rtw89_mac_fwd_target fwd_target, 2409 u8 mac_idx) 2410 { 2411 u32 reg; 2412 u32 val; 2413 2414 switch (fwd_target) { 2415 case RTW89_FWD_DONT_CARE: 2416 val = RX_FLTR_FRAME_DROP; 2417 break; 2418 case RTW89_FWD_TO_HOST: 2419 val = RX_FLTR_FRAME_TO_HOST; 2420 break; 2421 case RTW89_FWD_TO_WLAN_CPU: 2422 val = RX_FLTR_FRAME_TO_WLCPU; 2423 break; 2424 default: 2425 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2426 return -EINVAL; 2427 } 2428 2429 switch (type) { 2430 case RTW89_MGNT: 2431 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2432 break; 2433 case RTW89_CTRL: 2434 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2435 break; 2436 case RTW89_DATA: 2437 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2438 break; 2439 default: 2440 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2441 return -EINVAL; 2442 } 2443 rtw89_write32(rtwdev, reg, val); 2444 2445 return 0; 2446 } 2447 2448 static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2449 { 2450 int ret, i; 2451 u32 mac_ftlr, plcp_ftlr; 2452 2453 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2454 if (ret) 2455 return ret; 2456 2457 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2458 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2459 mac_idx); 2460 if (ret) 2461 return ret; 2462 } 2463 mac_ftlr = rtwdev->hal.rx_fltr; 2464 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2465 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2466 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2467 B_AX_HE_SIGB_CRC_CHK; 2468 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2469 mac_ftlr); 2470 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2471 plcp_ftlr); 2472 2473 return 0; 2474 } 2475 2476 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2477 { 2478 u32 reg, val32; 2479 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2480 2481 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2482 B_AX_RSP_CHK_BASIC_NAV; 2483 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2484 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2485 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2486 2487 switch (rtwdev->chip->chip_id) { 2488 case RTL8852A: 2489 case RTL8852B: 2490 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2491 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2492 rtw89_write32(rtwdev, reg, val32); 2493 2494 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2495 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2496 rtw89_write32(rtwdev, reg, val32); 2497 break; 2498 default: 2499 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2500 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2501 rtw89_write32(rtwdev, reg, val32); 2502 2503 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2504 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2505 rtw89_write32(rtwdev, reg, val32); 2506 break; 2507 } 2508 } 2509 2510 static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2511 { 2512 u32 val, reg; 2513 int ret; 2514 2515 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2516 if (ret) 2517 return ret; 2518 2519 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2520 val = rtw89_read32(rtwdev, reg); 2521 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2522 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2523 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2524 B_AX_CTN_CHK_INTRA_NAV | 2525 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2526 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2527 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2528 B_AX_CTN_CHK_CCA_P20); 2529 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2530 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2531 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2532 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2533 B_AX_SIFS_CHK_EDCCA); 2534 2535 rtw89_write32(rtwdev, reg, val); 2536 2537 _patch_dis_resp_chk(rtwdev, mac_idx); 2538 2539 return 0; 2540 } 2541 2542 static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 2543 { 2544 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2545 B_AX_WMAC_TF_UP_NAV_EN | 2546 B_AX_WMAC_NAV_UPPER_EN); 2547 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2548 2549 return 0; 2550 } 2551 2552 static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2553 { 2554 u32 reg; 2555 int ret; 2556 2557 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2558 if (ret) 2559 return ret; 2560 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2561 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2562 2563 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx); 2564 rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN); 2565 2566 return 0; 2567 } 2568 2569 static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2570 { 2571 u32 reg; 2572 int ret; 2573 2574 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2575 if (ret) 2576 return ret; 2577 2578 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2579 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2580 2581 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2582 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2583 2584 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2585 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2586 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2587 2588 return 0; 2589 } 2590 2591 static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2592 { 2593 const struct rtw89_chip_info *chip = rtwdev->chip; 2594 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2595 u32 reg, val, sifs; 2596 int ret; 2597 2598 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2599 if (ret) 2600 return ret; 2601 2602 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2603 val = rtw89_read32(rtwdev, reg); 2604 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2605 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2606 2607 switch (rtwdev->chip->chip_id) { 2608 case RTL8852A: 2609 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2610 break; 2611 case RTL8851B: 2612 case RTL8852B: 2613 case RTL8852BT: 2614 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2615 break; 2616 default: 2617 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2618 break; 2619 } 2620 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2621 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2622 rtw89_write32(rtwdev, reg, val); 2623 2624 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2625 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2626 2627 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2628 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2629 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2630 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2631 2632 return 0; 2633 } 2634 2635 static void rst_bacam(struct rtw89_dev *rtwdev) 2636 { 2637 u32 val32; 2638 int ret; 2639 2640 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2641 S_AX_BACAM_RST_ALL); 2642 2643 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2644 1, 1000, false, 2645 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2646 if (ret) 2647 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2648 } 2649 2650 static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2651 { 2652 #define TRXCFG_RMAC_CCA_TO 32 2653 #define TRXCFG_RMAC_DATA_TO 15 2654 #define RX_MAX_LEN_UNIT 512 2655 #define PLD_RLS_MAX_PG 127 2656 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2657 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2658 int ret; 2659 u32 reg, rx_max_len, rx_qta; 2660 u16 val; 2661 2662 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2663 if (ret) 2664 return ret; 2665 2666 if (mac_idx == RTW89_MAC_0) 2667 rst_bacam(rtwdev); 2668 2669 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2670 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2671 2672 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2673 val = rtw89_read16(rtwdev, reg); 2674 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2675 B_AX_RX_DLK_DATA_TIME_MASK); 2676 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2677 B_AX_RX_DLK_CCA_TIME_MASK); 2678 if (chip_id == RTL8852BT) 2679 val |= B_AX_RX_DLK_RST_EN; 2680 rtw89_write16(rtwdev, reg, val); 2681 2682 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2683 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2684 2685 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2686 if (mac_idx == RTW89_MAC_0) 2687 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2688 else 2689 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2690 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2691 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2692 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2693 rx_max_len /= RX_MAX_LEN_UNIT; 2694 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2695 2696 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) { 2697 rtw89_write16_mask(rtwdev, 2698 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2699 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2700 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2701 BIT(12)); 2702 } 2703 2704 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2705 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2706 2707 return ret; 2708 } 2709 2710 static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2711 { 2712 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2713 u32 val, reg; 2714 int ret; 2715 2716 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2717 if (ret) 2718 return ret; 2719 2720 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2721 val = rtw89_read32(rtwdev, reg); 2722 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2723 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2724 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2725 rtw89_write32(rtwdev, reg, val); 2726 2727 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2728 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 2729 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2730 } 2731 2732 return 0; 2733 } 2734 2735 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2736 { 2737 const struct rtw89_dle_mem *cfg; 2738 2739 cfg = get_dle_mem_cfg(rtwdev, mode); 2740 if (!cfg) { 2741 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2742 return false; 2743 } 2744 2745 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2746 } 2747 2748 static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2749 { 2750 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2751 u32 val, reg; 2752 int ret; 2753 2754 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2755 if (ret) 2756 return ret; 2757 2758 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2759 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2760 val = rtw89_read32(rtwdev, reg); 2761 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2762 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2763 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2764 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2765 val |= B_AX_HW_CTS2SELF_EN; 2766 rtw89_write32(rtwdev, reg, val); 2767 2768 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2769 val = rtw89_read32(rtwdev, reg); 2770 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2771 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2772 rtw89_write32(rtwdev, reg, val); 2773 } 2774 2775 if (mac_idx == RTW89_MAC_0) { 2776 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2777 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2778 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2779 B_AX_PTCL_TRIGGER_SS_EN_0 | 2780 B_AX_PTCL_TRIGGER_SS_EN_1 | 2781 B_AX_PTCL_TRIGGER_SS_EN_UL); 2782 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2783 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2784 } else if (mac_idx == RTW89_MAC_1) { 2785 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2786 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2787 } 2788 2789 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2790 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_VHT_0, mac_idx); 2791 rtw89_write32_mask(rtwdev, reg, 2792 B_AX_AMPDU_MAX_LEN_VHT_MASK, 0x3FF80); 2793 } 2794 2795 return 0; 2796 } 2797 2798 static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2799 { 2800 u32 reg; 2801 int ret; 2802 2803 if (!rtw89_is_rtl885xb(rtwdev)) 2804 return 0; 2805 2806 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2807 if (ret) 2808 return ret; 2809 2810 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2811 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2812 2813 return 0; 2814 } 2815 2816 static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2817 { 2818 int ret; 2819 2820 ret = scheduler_init_ax(rtwdev, mac_idx); 2821 if (ret) { 2822 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2823 return ret; 2824 } 2825 2826 ret = addr_cam_init_ax(rtwdev, mac_idx); 2827 if (ret) { 2828 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2829 ret); 2830 return ret; 2831 } 2832 2833 ret = rx_fltr_init_ax(rtwdev, mac_idx); 2834 if (ret) { 2835 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2836 ret); 2837 return ret; 2838 } 2839 2840 ret = cca_ctrl_init_ax(rtwdev, mac_idx); 2841 if (ret) { 2842 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2843 ret); 2844 return ret; 2845 } 2846 2847 ret = nav_ctrl_init_ax(rtwdev); 2848 if (ret) { 2849 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2850 ret); 2851 return ret; 2852 } 2853 2854 ret = spatial_reuse_init_ax(rtwdev, mac_idx); 2855 if (ret) { 2856 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2857 mac_idx, ret); 2858 return ret; 2859 } 2860 2861 ret = tmac_init_ax(rtwdev, mac_idx); 2862 if (ret) { 2863 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2864 return ret; 2865 } 2866 2867 ret = trxptcl_init_ax(rtwdev, mac_idx); 2868 if (ret) { 2869 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2870 return ret; 2871 } 2872 2873 ret = rmac_init_ax(rtwdev, mac_idx); 2874 if (ret) { 2875 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2876 return ret; 2877 } 2878 2879 ret = cmac_com_init_ax(rtwdev, mac_idx); 2880 if (ret) { 2881 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2882 return ret; 2883 } 2884 2885 ret = ptcl_init_ax(rtwdev, mac_idx); 2886 if (ret) { 2887 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2888 return ret; 2889 } 2890 2891 ret = cmac_dma_init_ax(rtwdev, mac_idx); 2892 if (ret) { 2893 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2894 return ret; 2895 } 2896 2897 return ret; 2898 } 2899 2900 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2901 struct rtw89_mac_c2h_info *c2h_info, u8 part_num) 2902 { 2903 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2904 const struct rtw89_chip_info *chip = rtwdev->chip; 2905 struct rtw89_mac_h2c_info h2c_info = {}; 2906 enum rtw89_mac_c2h_type c2h_type; 2907 u8 content_len; 2908 u32 ret; 2909 2910 if (chip->chip_gen == RTW89_CHIP_AX) 2911 content_len = 0; 2912 else 2913 content_len = 2; 2914 2915 switch (part_num) { 2916 case 0: 2917 c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP; 2918 break; 2919 case 1: 2920 c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1; 2921 break; 2922 default: 2923 return -EINVAL; 2924 } 2925 2926 mac->cnv_efuse_state(rtwdev, false); 2927 2928 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2929 h2c_info.content_len = content_len; 2930 h2c_info.u.hdr.w0 = u32_encode_bits(part_num, RTW89_H2CREG_GET_FEATURE_PART_NUM); 2931 2932 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2933 if (ret) 2934 goto out; 2935 2936 if (c2h_info->id != c2h_type) 2937 ret = -EINVAL; 2938 2939 out: 2940 mac->cnv_efuse_state(rtwdev, true); 2941 2942 return ret; 2943 } 2944 2945 static int rtw89_mac_setup_phycap_part0(struct rtw89_dev *rtwdev) 2946 { 2947 const struct rtw89_chip_info *chip = rtwdev->chip; 2948 const struct rtw89_c2hreg_phycap *phycap; 2949 struct rtw89_efuse *efuse = &rtwdev->efuse; 2950 struct rtw89_mac_c2h_info c2h_info = {}; 2951 struct rtw89_hal *hal = &rtwdev->hal; 2952 u8 tx_nss; 2953 u8 rx_nss; 2954 u8 tx_ant; 2955 u8 rx_ant; 2956 int ret; 2957 2958 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 0); 2959 if (ret) 2960 return ret; 2961 2962 phycap = &c2h_info.u.phycap; 2963 2964 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 2965 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 2966 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 2967 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 2968 2969 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2970 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2971 2972 if (tx_ant == 1) 2973 hal->antenna_tx = RF_B; 2974 if (rx_ant == 1) 2975 hal->antenna_rx = RF_B; 2976 2977 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2978 hal->antenna_tx = RF_B; 2979 hal->tx_path_diversity = true; 2980 } 2981 2982 if (chip->rf_path_num == 1) { 2983 hal->antenna_tx = RF_A; 2984 hal->antenna_rx = RF_A; 2985 if ((efuse->rfe_type % 3) == 2) 2986 hal->ant_diversity = true; 2987 } 2988 2989 rtw89_debug(rtwdev, RTW89_DBG_FW, 2990 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2991 hal->tx_nss, tx_nss, chip->tx_nss, 2992 hal->rx_nss, rx_nss, chip->rx_nss); 2993 rtw89_debug(rtwdev, RTW89_DBG_FW, 2994 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2995 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2996 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2997 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2998 2999 return 0; 3000 } 3001 3002 static int rtw89_mac_setup_phycap_part1(struct rtw89_dev *rtwdev) 3003 { 3004 const struct rtw89_chip_variant *variant = rtwdev->variant; 3005 const struct rtw89_c2hreg_phycap *phycap; 3006 struct rtw89_mac_c2h_info c2h_info = {}; 3007 struct rtw89_hal *hal = &rtwdev->hal; 3008 u8 qam_raw, qam; 3009 int ret; 3010 3011 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 1); 3012 if (ret) 3013 return ret; 3014 3015 phycap = &c2h_info.u.phycap; 3016 3017 qam_raw = u32_get_bits(phycap->w2, RTW89_C2HREG_PHYCAP_P1_W2_QAM); 3018 3019 switch (qam_raw) { 3020 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_256: 3021 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024: 3022 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096: 3023 qam = qam_raw; 3024 break; 3025 default: 3026 qam = RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096; 3027 break; 3028 } 3029 3030 if ((variant && variant->no_mcs_12_13) || 3031 qam <= RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024) 3032 hal->no_mcs_12_13 = true; 3033 3034 rtw89_debug(rtwdev, RTW89_DBG_FW, "phycap qam=%d/%d no_mcs_12_13=%d\n", 3035 qam_raw, qam, hal->no_mcs_12_13); 3036 3037 return 0; 3038 } 3039 3040 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 3041 { 3042 const struct rtw89_chip_info *chip = rtwdev->chip; 3043 int ret; 3044 3045 ret = rtw89_mac_setup_phycap_part0(rtwdev); 3046 if (ret) 3047 return ret; 3048 3049 if (chip->chip_gen == RTW89_CHIP_AX || 3050 RTW89_CHK_FW_FEATURE(NO_PHYCAP_P1, &rtwdev->fw)) 3051 return 0; 3052 3053 return rtw89_mac_setup_phycap_part1(rtwdev); 3054 } 3055 3056 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 3057 u16 tx_en_u16, u16 mask_u16) 3058 { 3059 u32 ret; 3060 struct rtw89_mac_c2h_info c2h_info = {0}; 3061 struct rtw89_mac_h2c_info h2c_info = {0}; 3062 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 3063 3064 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 3065 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 3066 3067 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 3068 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 3069 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 3070 3071 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 3072 if (ret) 3073 return ret; 3074 3075 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 3076 return -EINVAL; 3077 3078 return 0; 3079 } 3080 3081 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 3082 u16 tx_en, u16 tx_en_mask) 3083 { 3084 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 3085 u16 val; 3086 int ret; 3087 3088 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3089 if (ret) 3090 return ret; 3091 3092 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3093 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 3094 tx_en, tx_en_mask); 3095 3096 val = rtw89_read16(rtwdev, reg); 3097 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3098 rtw89_write16(rtwdev, reg, val); 3099 3100 return 0; 3101 } 3102 3103 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3104 u32 tx_en, u32 tx_en_mask) 3105 { 3106 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 3107 u32 val; 3108 int ret; 3109 3110 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3111 if (ret) 3112 return ret; 3113 3114 val = rtw89_read32(rtwdev, reg); 3115 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3116 rtw89_write32(rtwdev, reg, val); 3117 3118 return 0; 3119 } 3120 3121 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3122 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3123 { 3124 int ret; 3125 3126 *tx_en = rtw89_read16(rtwdev, 3127 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3128 3129 switch (sel) { 3130 case RTW89_SCH_TX_SEL_ALL: 3131 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3132 B_AX_CTN_TXEN_ALL_MASK); 3133 if (ret) 3134 return ret; 3135 break; 3136 case RTW89_SCH_TX_SEL_HIQ: 3137 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3138 0, B_AX_CTN_TXEN_HGQ); 3139 if (ret) 3140 return ret; 3141 break; 3142 case RTW89_SCH_TX_SEL_MG0: 3143 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3144 0, B_AX_CTN_TXEN_MGQ); 3145 if (ret) 3146 return ret; 3147 break; 3148 case RTW89_SCH_TX_SEL_MACID: 3149 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3150 B_AX_CTN_TXEN_ALL_MASK); 3151 if (ret) 3152 return ret; 3153 break; 3154 default: 3155 return 0; 3156 } 3157 3158 return 0; 3159 } 3160 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3161 3162 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3163 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3164 { 3165 int ret; 3166 3167 *tx_en = rtw89_read32(rtwdev, 3168 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3169 3170 switch (sel) { 3171 case RTW89_SCH_TX_SEL_ALL: 3172 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3173 B_AX_CTN_TXEN_ALL_MASK_V1); 3174 if (ret) 3175 return ret; 3176 break; 3177 case RTW89_SCH_TX_SEL_HIQ: 3178 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3179 0, B_AX_CTN_TXEN_HGQ); 3180 if (ret) 3181 return ret; 3182 break; 3183 case RTW89_SCH_TX_SEL_MG0: 3184 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3185 0, B_AX_CTN_TXEN_MGQ); 3186 if (ret) 3187 return ret; 3188 break; 3189 case RTW89_SCH_TX_SEL_MACID: 3190 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3191 B_AX_CTN_TXEN_ALL_MASK_V1); 3192 if (ret) 3193 return ret; 3194 break; 3195 default: 3196 return 0; 3197 } 3198 3199 return 0; 3200 } 3201 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3202 3203 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3204 { 3205 int ret; 3206 3207 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3208 if (ret) 3209 return ret; 3210 3211 return 0; 3212 } 3213 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3214 3215 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3216 { 3217 int ret; 3218 3219 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3220 B_AX_CTN_TXEN_ALL_MASK_V1); 3221 if (ret) 3222 return ret; 3223 3224 return 0; 3225 } 3226 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3227 3228 static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3229 { 3230 u32 val, reg; 3231 int ret; 3232 3233 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3234 val = buf_len; 3235 val |= B_AX_WD_BUF_REQ_EXEC; 3236 rtw89_write32(rtwdev, reg, val); 3237 3238 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3239 3240 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3241 1, 2000, false, rtwdev, reg); 3242 if (ret) 3243 return ret; 3244 3245 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3246 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3247 return -ENOENT; 3248 3249 return 0; 3250 } 3251 3252 static int set_cpuio_ax(struct rtw89_dev *rtwdev, 3253 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3254 { 3255 u32 val, cmd_type, reg; 3256 int ret; 3257 3258 cmd_type = ctrl_para->cmd_type; 3259 3260 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3261 val = 0; 3262 val = u32_replace_bits(val, ctrl_para->start_pktid, 3263 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3264 val = u32_replace_bits(val, ctrl_para->end_pktid, 3265 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3266 rtw89_write32(rtwdev, reg, val); 3267 3268 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3269 val = 0; 3270 val = u32_replace_bits(val, ctrl_para->src_pid, 3271 B_AX_CPUQ_OP_SRC_PID_MASK); 3272 val = u32_replace_bits(val, ctrl_para->src_qid, 3273 B_AX_CPUQ_OP_SRC_QID_MASK); 3274 val = u32_replace_bits(val, ctrl_para->dst_pid, 3275 B_AX_CPUQ_OP_DST_PID_MASK); 3276 val = u32_replace_bits(val, ctrl_para->dst_qid, 3277 B_AX_CPUQ_OP_DST_QID_MASK); 3278 rtw89_write32(rtwdev, reg, val); 3279 3280 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3281 val = 0; 3282 val = u32_replace_bits(val, cmd_type, 3283 B_AX_CPUQ_OP_CMD_TYPE_MASK); 3284 val = u32_replace_bits(val, ctrl_para->macid, 3285 B_AX_CPUQ_OP_MACID_MASK); 3286 val = u32_replace_bits(val, ctrl_para->pkt_num, 3287 B_AX_CPUQ_OP_PKTNUM_MASK); 3288 val |= B_AX_WD_CPUQ_OP_EXEC; 3289 rtw89_write32(rtwdev, reg, val); 3290 3291 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3292 3293 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3294 1, 2000, false, rtwdev, reg); 3295 if (ret) 3296 return ret; 3297 3298 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3299 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3300 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3301 3302 return 0; 3303 } 3304 3305 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 3306 bool band1_en) 3307 { 3308 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3309 const struct rtw89_dle_mem *cfg; 3310 3311 cfg = get_dle_mem_cfg(rtwdev, mode); 3312 if (!cfg) { 3313 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3314 return -EINVAL; 3315 } 3316 3317 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3318 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3319 return -EINVAL; 3320 } 3321 3322 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3323 3324 return mac->dle_quota_change(rtwdev, band1_en); 3325 } 3326 3327 static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en) 3328 { 3329 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3330 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3331 u16 pkt_id; 3332 int ret; 3333 3334 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3335 if (ret) { 3336 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3337 return ret; 3338 } 3339 3340 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3341 ctrl_para.start_pktid = pkt_id; 3342 ctrl_para.end_pktid = pkt_id; 3343 ctrl_para.pkt_num = 0; 3344 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3345 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3346 ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3347 if (ret) { 3348 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3349 return -EFAULT; 3350 } 3351 3352 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3353 if (ret) { 3354 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3355 return ret; 3356 } 3357 3358 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3359 ctrl_para.start_pktid = pkt_id; 3360 ctrl_para.end_pktid = pkt_id; 3361 ctrl_para.pkt_num = 0; 3362 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3363 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3364 ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3365 if (ret) { 3366 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3367 return -EFAULT; 3368 } 3369 3370 return 0; 3371 } 3372 3373 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3374 { 3375 int ret; 3376 u32 reg; 3377 u8 val; 3378 3379 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3380 if (ret) 3381 return ret; 3382 3383 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3384 3385 ret = read_poll_timeout(rtw89_read8, val, 3386 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3387 SW_CVR_DUR_US, 3388 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3389 false, rtwdev, reg); 3390 if (ret) 3391 return ret; 3392 3393 return 0; 3394 } 3395 3396 static int band1_enable_ax(struct rtw89_dev *rtwdev) 3397 { 3398 int ret, i; 3399 u32 sleep_bak[4] = {0}; 3400 u32 pause_bak[4] = {0}; 3401 u32 tx_en; 3402 3403 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3404 if (ret) { 3405 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3406 return ret; 3407 } 3408 3409 for (i = 0; i < 4; i++) { 3410 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3411 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3412 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3413 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3414 } 3415 3416 ret = band_idle_ck_b(rtwdev, 0); 3417 if (ret) { 3418 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3419 return ret; 3420 } 3421 3422 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 3423 if (ret) { 3424 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3425 return ret; 3426 } 3427 3428 for (i = 0; i < 4; i++) { 3429 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3430 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3431 } 3432 3433 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3434 if (ret) { 3435 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3436 return ret; 3437 } 3438 3439 ret = cmac_func_en_ax(rtwdev, 1, true); 3440 if (ret) { 3441 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3442 return ret; 3443 } 3444 3445 ret = cmac_init_ax(rtwdev, 1); 3446 if (ret) { 3447 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3448 return ret; 3449 } 3450 3451 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3452 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3453 3454 return 0; 3455 } 3456 3457 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3458 { 3459 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3460 3461 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3462 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3463 } 3464 3465 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3466 { 3467 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3468 3469 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3470 } 3471 3472 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3473 { 3474 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3475 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3476 3477 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3478 B_AX_TX_GET_ERRPKTID_INT_EN | 3479 B_AX_TX_NXT_ERRPKTID_INT_EN | 3480 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3481 B_AX_TX_OFFSET_ERR_INT_EN | 3482 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3483 if (chip_id == RTL8852C) 3484 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3485 B_AX_TX_ETH_TYPE_ERR_EN | 3486 B_AX_TX_LLC_PRE_ERR_EN | 3487 B_AX_TX_NW_TYPE_ERR_EN | 3488 B_AX_TX_KSRCH_ERR_EN); 3489 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3490 imr->mpdu_tx_imr_set); 3491 3492 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3493 B_AX_GETPKTID_ERR_INT_EN | 3494 B_AX_MHDRLEN_ERR_INT_EN | 3495 B_AX_RPT_ERR_INT_EN); 3496 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3497 imr->mpdu_rx_imr_set); 3498 } 3499 3500 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3501 { 3502 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3503 3504 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3505 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3506 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3507 B_AX_PLE_B_PKTID_ERR_INT_EN); 3508 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3509 imr->sta_sch_imr_set); 3510 } 3511 3512 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3513 { 3514 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3515 3516 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3517 imr->txpktctl_imr_b0_clr); 3518 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3519 imr->txpktctl_imr_b0_set); 3520 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3521 imr->txpktctl_imr_b1_clr); 3522 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3523 imr->txpktctl_imr_b1_set); 3524 } 3525 3526 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3527 { 3528 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3529 3530 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3531 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3532 } 3533 3534 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3535 { 3536 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3537 3538 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3539 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3540 } 3541 3542 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3543 { 3544 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3545 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3546 } 3547 3548 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3549 { 3550 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3551 3552 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3553 imr->host_disp_imr_clr); 3554 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3555 imr->host_disp_imr_set); 3556 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3557 imr->cpu_disp_imr_clr); 3558 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3559 imr->cpu_disp_imr_set); 3560 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3561 imr->other_disp_imr_clr); 3562 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3563 imr->other_disp_imr_set); 3564 } 3565 3566 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3567 { 3568 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3569 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3570 } 3571 3572 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3573 { 3574 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3575 3576 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3577 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3578 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3579 B_AX_BBRPT_CHINFO_IMR_CLR); 3580 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3581 imr->bbrpt_err_imr_set); 3582 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3583 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3584 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3585 } 3586 3587 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3588 { 3589 u32 reg; 3590 3591 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3592 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3593 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3594 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3595 } 3596 3597 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3598 { 3599 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3600 u32 reg; 3601 3602 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3603 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3604 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3605 } 3606 3607 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3608 { 3609 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3610 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3611 u32 reg; 3612 3613 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3614 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3615 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3616 3617 if (chip_id == RTL8852C) { 3618 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3619 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3620 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3621 } 3622 } 3623 3624 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3625 { 3626 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3627 u32 reg; 3628 3629 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3630 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3631 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3632 } 3633 3634 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3635 { 3636 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3637 u32 reg; 3638 3639 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3640 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3641 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3642 } 3643 3644 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3645 { 3646 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3647 u32 reg; 3648 3649 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3650 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3651 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3652 } 3653 3654 static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3655 enum rtw89_mac_hwmod_sel sel) 3656 { 3657 int ret; 3658 3659 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3660 if (ret) { 3661 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3662 sel, mac_idx); 3663 return ret; 3664 } 3665 3666 if (sel == RTW89_DMAC_SEL) { 3667 rtw89_wdrls_imr_enable(rtwdev); 3668 rtw89_wsec_imr_enable(rtwdev); 3669 rtw89_mpdu_trx_imr_enable(rtwdev); 3670 rtw89_sta_sch_imr_enable(rtwdev); 3671 rtw89_txpktctl_imr_enable(rtwdev); 3672 rtw89_wde_imr_enable(rtwdev); 3673 rtw89_ple_imr_enable(rtwdev); 3674 rtw89_pktin_imr_enable(rtwdev); 3675 rtw89_dispatcher_imr_enable(rtwdev); 3676 rtw89_cpuio_imr_enable(rtwdev); 3677 rtw89_bbrpt_imr_enable(rtwdev); 3678 } else if (sel == RTW89_CMAC_SEL) { 3679 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3680 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3681 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3682 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3683 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3684 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3685 } else { 3686 return -EINVAL; 3687 } 3688 3689 return 0; 3690 } 3691 3692 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 3693 { 3694 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3695 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3696 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3697 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3698 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta) 3699 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3700 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3701 } 3702 3703 static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3704 { 3705 int ret = 0; 3706 3707 if (enable) { 3708 ret = band1_enable_ax(rtwdev); 3709 if (ret) { 3710 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3711 return ret; 3712 } 3713 3714 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3715 if (ret) { 3716 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3717 return ret; 3718 } 3719 } else { 3720 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3721 return -EINVAL; 3722 } 3723 3724 return 0; 3725 } 3726 3727 static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 3728 { 3729 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3730 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3731 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3732 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3733 B_AX_RLSRPT0_FLTR_MAP_MASK); 3734 } else { 3735 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3736 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3737 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3738 B_AX_RLSRPT0_FLTR_MAP_MASK); 3739 } 3740 3741 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3742 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3743 3744 return 0; 3745 } 3746 3747 static int trx_init_ax(struct rtw89_dev *rtwdev) 3748 { 3749 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3750 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3751 int ret; 3752 3753 ret = dmac_init_ax(rtwdev, 0); 3754 if (ret) { 3755 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3756 return ret; 3757 } 3758 3759 ret = cmac_init_ax(rtwdev, 0); 3760 if (ret) { 3761 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3762 return ret; 3763 } 3764 3765 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 3766 ret = dbcc_enable_ax(rtwdev, true); 3767 if (ret) { 3768 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3769 return ret; 3770 } 3771 } 3772 3773 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3774 if (ret) { 3775 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3776 return ret; 3777 } 3778 3779 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3780 if (ret) { 3781 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3782 return ret; 3783 } 3784 3785 err_imr_ctrl_ax(rtwdev, true); 3786 3787 ret = set_host_rpr_ax(rtwdev); 3788 if (ret) { 3789 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3790 return ret; 3791 } 3792 3793 if (chip_id == RTL8852C) 3794 rtw89_write32_clr(rtwdev, R_AX_RSP_CHK_SIG, 3795 B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN); 3796 3797 return 0; 3798 } 3799 3800 static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev) 3801 { 3802 #define BACAM_1024BMP_OCC_ENTRY 4 3803 #define BACAM_MAX_RU_SUPPORT_B0_STA 1 3804 #define BACAM_MAX_RU_SUPPORT_B1_STA 1 3805 const struct rtw89_chip_info *chip = rtwdev->chip; 3806 u8 users, offset; 3807 3808 if (chip->bacam_ver != RTW89_BACAM_V1) 3809 return 0; 3810 3811 offset = 0; 3812 users = BACAM_MAX_RU_SUPPORT_B0_STA; 3813 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0); 3814 3815 offset += users * BACAM_1024BMP_OCC_ENTRY; 3816 users = BACAM_MAX_RU_SUPPORT_B1_STA; 3817 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1); 3818 3819 return 0; 3820 } 3821 3822 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3823 { 3824 u32 val32; 3825 3826 if (rtw89_is_rtl885xb(rtwdev)) { 3827 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3828 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3829 return; 3830 } 3831 3832 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3833 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3834 3835 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3836 val32 |= B_AX_FS_WDT_INT; 3837 val32 &= ~B_AX_FS_WDT_INT_MSK; 3838 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3839 } 3840 3841 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3842 { 3843 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3844 3845 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3846 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3847 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3848 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3849 3850 rtw89_disable_fw_watchdog(rtwdev); 3851 3852 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3853 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3854 } 3855 3856 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3857 bool dlfw, bool include_bb) 3858 { 3859 u32 val; 3860 int ret; 3861 3862 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3863 return -EFAULT; 3864 3865 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3866 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3867 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3868 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3869 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3870 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3871 3872 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3873 3874 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3875 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3876 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3877 B_AX_WCPU_FWDL_STS_MASK); 3878 3879 if (dlfw) 3880 val |= B_AX_WCPU_FWDL_EN; 3881 3882 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3883 3884 if (rtw89_is_rtl885xb(rtwdev)) 3885 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3886 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3887 3888 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3889 boot_reason); 3890 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3891 3892 if (!dlfw) { 3893 mdelay(5); 3894 3895 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 3896 if (ret) 3897 return ret; 3898 } 3899 3900 return 0; 3901 } 3902 3903 static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 3904 { 3905 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3906 u32 val; 3907 3908 if (chip_id == RTL8852C) 3909 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3910 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3911 else 3912 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3913 B_AX_PKT_BUF_EN; 3914 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3915 } 3916 3917 static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 3918 { 3919 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3920 u32 val; 3921 3922 if (chip_id == RTL8851B || chip_id == RTL8852BT) 3923 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3924 else 3925 val = B_AX_DISPATCHER_CLK_EN; 3926 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3927 3928 if (chip_id != RTL8852C) 3929 return; 3930 3931 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3932 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3933 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3934 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3935 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3936 3937 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3938 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3939 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3940 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3941 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3942 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3943 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3944 } 3945 3946 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3947 { 3948 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3949 int ret; 3950 3951 mac->hci_func_en(rtwdev); 3952 mac->dmac_func_pre_en(rtwdev); 3953 3954 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3955 if (ret) { 3956 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3957 return ret; 3958 } 3959 3960 ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 3961 if (ret) { 3962 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3963 return ret; 3964 } 3965 3966 return ret; 3967 } 3968 3969 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3970 { 3971 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3972 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3973 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3974 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3975 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3976 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3977 3978 return 0; 3979 } 3980 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3981 3982 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3983 { 3984 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3985 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3986 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3987 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3988 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3989 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3990 3991 return 0; 3992 } 3993 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3994 3995 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 3996 { 3997 int ret; 3998 3999 ret = rtw89_mac_power_switch(rtwdev, true); 4000 if (ret) { 4001 rtw89_mac_power_switch(rtwdev, false); 4002 ret = rtw89_mac_power_switch(rtwdev, true); 4003 if (ret) 4004 return ret; 4005 } 4006 4007 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 4008 4009 if (include_bb) { 4010 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0); 4011 if (rtwdev->dbcc_en) 4012 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1); 4013 } 4014 4015 ret = rtw89_mac_dmac_pre_init(rtwdev); 4016 if (ret) 4017 return ret; 4018 4019 if (rtwdev->hci.ops->mac_pre_init) { 4020 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 4021 if (ret) 4022 return ret; 4023 } 4024 4025 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 4026 if (ret) 4027 return ret; 4028 4029 return 0; 4030 } 4031 4032 int rtw89_mac_init(struct rtw89_dev *rtwdev) 4033 { 4034 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4035 const struct rtw89_chip_info *chip = rtwdev->chip; 4036 bool include_bb = !!chip->bbmcu_nr; 4037 int ret; 4038 4039 ret = rtw89_mac_partial_init(rtwdev, include_bb); 4040 if (ret) 4041 goto fail; 4042 4043 ret = rtw89_chip_enable_bb_rf(rtwdev); 4044 if (ret) 4045 goto fail; 4046 4047 ret = mac->sys_init(rtwdev); 4048 if (ret) 4049 goto fail; 4050 4051 ret = mac->trx_init(rtwdev); 4052 if (ret) 4053 goto fail; 4054 4055 ret = rtw89_mac_feat_init(rtwdev); 4056 if (ret) 4057 goto fail; 4058 4059 if (rtwdev->hci.ops->mac_post_init) { 4060 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 4061 if (ret) 4062 goto fail; 4063 } 4064 4065 rtw89_fw_send_all_early_h2c(rtwdev); 4066 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 4067 4068 return ret; 4069 fail: 4070 rtw89_mac_power_switch(rtwdev, false); 4071 4072 return ret; 4073 } 4074 4075 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4076 { 4077 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4078 u8 i; 4079 4080 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4081 return; 4082 4083 for (i = 0; i < 4; i++) { 4084 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4085 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 4086 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 4087 } 4088 } 4089 4090 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4091 { 4092 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4093 4094 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4095 return; 4096 4097 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4098 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 4099 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 4100 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 4101 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 4102 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 4103 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 4104 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 4105 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 4106 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 4107 } 4108 4109 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 4110 { 4111 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 4112 u8 grp = macid >> 5; 4113 int ret; 4114 4115 /* If this is called by change_interface() in the case of P2P, it could 4116 * be power-off, so ignore this operation. 4117 */ 4118 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 4119 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4120 return 0; 4121 4122 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4123 if (ret) 4124 return ret; 4125 4126 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 4127 4128 return 0; 4129 } 4130 4131 static const struct rtw89_port_reg rtw89_port_base_ax = { 4132 .port_cfg = R_AX_PORT_CFG_P0, 4133 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 4134 .bcn_area = R_AX_BCN_AREA_P0, 4135 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 4136 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 4137 .tbtt_agg = R_AX_TBTT_AGG_P0, 4138 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 4139 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 4140 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 4141 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 4142 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 4143 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 4144 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 4145 .tsftr_l = R_AX_TSFTR_LOW_P0, 4146 .tsftr_h = R_AX_TSFTR_HIGH_P0, 4147 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 4148 .bss_color = R_AX_PTCL_BSS_COLOR_0, 4149 .mbssid = R_AX_MBSSID_CTRL, 4150 .mbssid_drop = R_AX_MBSSID_DROP_0, 4151 .tsf_sync = R_AX_PORT0_TSF_SYNC, 4152 .ptcl_dbg = R_AX_PTCL_DBG, 4153 .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4154 .bcn_drop_all = R_AX_BCN_DROP_ALL0, 4155 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 4156 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 4157 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4158 }; 4159 4160 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 4161 struct rtw89_vif_link *rtwvif_link, u8 type) 4162 { 4163 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4164 const struct rtw89_port_reg *p = mac->port_base; 4165 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif_link->port); 4166 u32 reg_info, reg_ctrl; 4167 u32 val; 4168 int ret; 4169 4170 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif_link->mac_idx); 4171 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif_link->mac_idx); 4172 4173 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 4174 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 4175 fsleep(100); 4176 4177 ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 4178 true, rtwdev, reg_info, mask); 4179 if (ret) 4180 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 4181 } 4182 4183 static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, 4184 struct rtw89_vif_link *rtwvif_link) 4185 { 4186 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4187 const struct rtw89_port_reg *p = mac->port_base; 4188 4189 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4190 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 4191 1); 4192 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 4193 0); 4194 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 4195 0); 4196 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 2); 4197 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4198 B_AX_TBTTERLY_MASK, 1); 4199 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, 4200 B_AX_BCN_SPACE_MASK, 1); 4201 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4202 4203 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM0); 4204 if (rtwvif_link->port == RTW89_PORT_0) 4205 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM1); 4206 4207 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4208 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TBTT_PROHIB_EN); 4209 fsleep(2000); 4210 } 4211 4212 #define BCN_INTERVAL 100 4213 #define BCN_ERLY_DEF 160 4214 #define BCN_SETUP_DEF 2 4215 #define BCN_HOLD_DEF 200 4216 #define BCN_MASK_DEF 0 4217 #define TBTT_ERLY_DEF 5 4218 #define BCN_SET_UNIT 32 4219 #define BCN_ERLY_SET_DLY (10 * 2) 4220 4221 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4222 struct rtw89_vif_link *rtwvif_link) 4223 { 4224 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4225 const struct rtw89_port_reg *p = mac->port_base; 4226 const struct rtw89_chip_info *chip = rtwdev->chip; 4227 struct ieee80211_bss_conf *bss_conf; 4228 bool need_backup = false; 4229 u32 backup_val; 4230 u16 beacon_int; 4231 4232 if (!rtw89_read32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN)) 4233 return; 4234 4235 if (chip->chip_id == RTL8852A && rtwvif_link->port != RTW89_PORT_0) { 4236 need_backup = true; 4237 backup_val = rtw89_read32_port(rtwdev, rtwvif_link, p->tbtt_prohib); 4238 } 4239 4240 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4241 rtw89_mac_bcn_drop(rtwdev, rtwvif_link); 4242 4243 if (chip->chip_id == RTL8852A) { 4244 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->tbtt_prohib, 4245 B_AX_TBTT_SETUP_MASK); 4246 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4247 B_AX_TBTT_HOLD_MASK, 1); 4248 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->tbtt_early, 4249 B_AX_TBTTERLY_MASK); 4250 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->bcn_early, 4251 B_AX_BCNERLY_MASK); 4252 } 4253 4254 rcu_read_lock(); 4255 4256 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4257 beacon_int = bss_conf->beacon_int; 4258 4259 rcu_read_unlock(); 4260 4261 msleep(beacon_int + 1); 4262 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN | 4263 B_AX_BRK_SETUP); 4264 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSFTR_RST); 4265 rtw89_write32_port(rtwdev, rtwvif_link, p->bcn_cnt_tmr, 0); 4266 4267 if (need_backup) 4268 rtw89_write32_port(rtwdev, rtwvif_link, p->tbtt_prohib, backup_val); 4269 } 4270 4271 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4272 struct rtw89_vif_link *rtwvif_link, bool en) 4273 { 4274 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4275 const struct rtw89_port_reg *p = mac->port_base; 4276 4277 if (en) 4278 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4279 B_AX_TXBCN_RPT_EN); 4280 else 4281 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4282 B_AX_TXBCN_RPT_EN); 4283 } 4284 4285 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4286 struct rtw89_vif_link *rtwvif_link, bool en) 4287 { 4288 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4289 const struct rtw89_port_reg *p = mac->port_base; 4290 4291 if (en) 4292 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4293 B_AX_RXBCN_RPT_EN); 4294 else 4295 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4296 B_AX_RXBCN_RPT_EN); 4297 } 4298 4299 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4300 struct rtw89_vif_link *rtwvif_link) 4301 { 4302 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4303 const struct rtw89_port_reg *p = mac->port_base; 4304 4305 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_NET_TYPE_MASK, 4306 rtwvif_link->net_type); 4307 } 4308 4309 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4310 struct rtw89_vif_link *rtwvif_link) 4311 { 4312 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4313 const struct rtw89_port_reg *p = mac->port_base; 4314 bool en = rtwvif_link->net_type != RTW89_NET_TYPE_NO_LINK; 4315 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4316 4317 if (en) 4318 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bits); 4319 else 4320 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bits); 4321 } 4322 4323 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4324 struct rtw89_vif_link *rtwvif_link) 4325 { 4326 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4327 const struct rtw89_port_reg *p = mac->port_base; 4328 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4329 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4330 u32 bit = B_AX_RX_BSSID_FIT_EN; 4331 4332 if (en) 4333 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bit); 4334 else 4335 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bit); 4336 } 4337 4338 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4339 struct rtw89_vif_link *rtwvif_link, bool en) 4340 { 4341 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4342 const struct rtw89_port_reg *p = mac->port_base; 4343 4344 if (en) 4345 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4346 else 4347 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4348 } 4349 4350 static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev, 4351 struct rtw89_vif_link *rtwvif_link) 4352 { 4353 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4354 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4355 4356 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif_link, en); 4357 } 4358 4359 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4360 struct rtw89_vif_link *rtwvif_link, bool en) 4361 { 4362 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4363 const struct rtw89_port_reg *p = mac->port_base; 4364 4365 if (en) 4366 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4367 else 4368 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4369 } 4370 4371 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4372 struct rtw89_vif_link *rtwvif_link) 4373 { 4374 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || 4375 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4376 4377 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4378 } 4379 4380 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4381 { 4382 struct rtw89_vif_link *rtwvif_link; 4383 struct rtw89_vif *rtwvif; 4384 unsigned int link_id; 4385 4386 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4387 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4388 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4389 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4390 } 4391 4392 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4393 struct rtw89_vif_link *rtwvif_link) 4394 { 4395 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4396 const struct rtw89_port_reg *p = mac->port_base; 4397 struct ieee80211_bss_conf *bss_conf; 4398 u16 bcn_int; 4399 4400 rcu_read_lock(); 4401 4402 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4403 if (bss_conf->beacon_int) 4404 bcn_int = bss_conf->beacon_int; 4405 else 4406 bcn_int = BCN_INTERVAL; 4407 4408 rcu_read_unlock(); 4409 4410 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, B_AX_BCN_SPACE_MASK, 4411 bcn_int); 4412 } 4413 4414 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4415 struct rtw89_vif_link *rtwvif_link) 4416 { 4417 u8 win = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 4418 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4419 const struct rtw89_port_reg *p = mac->port_base; 4420 u8 port = rtwvif_link->port; 4421 u32 reg; 4422 4423 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif_link->mac_idx); 4424 rtw89_write8(rtwdev, reg, win); 4425 } 4426 4427 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4428 struct rtw89_vif_link *rtwvif_link) 4429 { 4430 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4431 const struct rtw89_port_reg *p = mac->port_base; 4432 struct ieee80211_bss_conf *bss_conf; 4433 u8 dtim_period; 4434 u32 addr; 4435 4436 rcu_read_lock(); 4437 4438 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4439 dtim_period = bss_conf->dtim_period; 4440 4441 rcu_read_unlock(); 4442 4443 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif_link->mac_idx); 4444 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4445 4446 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4447 dtim_period); 4448 } 4449 4450 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4451 struct rtw89_vif_link *rtwvif_link) 4452 { 4453 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4454 const struct rtw89_port_reg *p = mac->port_base; 4455 4456 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4457 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4458 } 4459 4460 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4461 struct rtw89_vif_link *rtwvif_link) 4462 { 4463 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4464 const struct rtw89_port_reg *p = mac->port_base; 4465 4466 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4467 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4468 } 4469 4470 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4471 struct rtw89_vif_link *rtwvif_link) 4472 { 4473 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4474 const struct rtw89_port_reg *p = mac->port_base; 4475 4476 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, 4477 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4478 } 4479 4480 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4481 struct rtw89_vif_link *rtwvif_link) 4482 { 4483 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4484 const struct rtw89_port_reg *p = mac->port_base; 4485 4486 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4487 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4488 } 4489 4490 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4491 struct rtw89_vif_link *rtwvif_link) 4492 { 4493 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4494 const struct rtw89_port_reg *p = mac->port_base; 4495 static const u32 masks[RTW89_PORT_NUM] = { 4496 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4497 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4498 B_AX_BSS_COLOB_AX_PORT_4_MASK, 4499 }; 4500 struct ieee80211_bss_conf *bss_conf; 4501 u8 port = rtwvif_link->port; 4502 u32 reg_base; 4503 u32 reg; 4504 u8 bss_color; 4505 4506 rcu_read_lock(); 4507 4508 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4509 bss_color = bss_conf->he_bss_color.color; 4510 4511 rcu_read_unlock(); 4512 4513 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4514 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif_link->mac_idx); 4515 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4516 } 4517 4518 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4519 struct rtw89_vif_link *rtwvif_link) 4520 { 4521 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4522 const struct rtw89_port_reg *p = mac->port_base; 4523 u8 port = rtwvif_link->port; 4524 u32 reg; 4525 4526 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4527 return; 4528 4529 if (port == 0) { 4530 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif_link->mac_idx); 4531 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4532 } 4533 } 4534 4535 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4536 struct rtw89_vif_link *rtwvif_link) 4537 { 4538 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4539 const struct rtw89_port_reg *p = mac->port_base; 4540 u8 port = rtwvif_link->port; 4541 u32 reg; 4542 u32 val; 4543 4544 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif_link->mac_idx); 4545 val = rtw89_read32(rtwdev, reg); 4546 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4547 if (port == 0) 4548 val &= ~BIT(0); 4549 rtw89_write32(rtwdev, reg, val); 4550 } 4551 4552 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4553 struct rtw89_vif_link *rtwvif_link, bool enable) 4554 { 4555 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4556 const struct rtw89_port_reg *p = mac->port_base; 4557 4558 if (enable) 4559 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4560 B_AX_PORT_FUNC_EN); 4561 else 4562 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4563 B_AX_PORT_FUNC_EN); 4564 } 4565 4566 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4567 struct rtw89_vif_link *rtwvif_link) 4568 { 4569 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4570 const struct rtw89_port_reg *p = mac->port_base; 4571 4572 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 4573 BCN_ERLY_DEF); 4574 } 4575 4576 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 4577 struct rtw89_vif_link *rtwvif_link) 4578 { 4579 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4580 const struct rtw89_port_reg *p = mac->port_base; 4581 u16 val; 4582 4583 if (rtwdev->chip->chip_id != RTL8852C) 4584 return; 4585 4586 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4587 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION) 4588 return; 4589 4590 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4591 B_AX_TBTT_SHIFT_OFST_SIGN; 4592 4593 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_shift, 4594 B_AX_TBTT_SHIFT_OFST_MASK, val); 4595 } 4596 4597 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4598 struct rtw89_vif_link *rtwvif_link, 4599 struct rtw89_vif_link *rtwvif_src, 4600 u16 offset_tu) 4601 { 4602 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4603 const struct rtw89_port_reg *p = mac->port_base; 4604 u32 val, reg; 4605 4606 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4607 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif_link->port * 4, 4608 rtwvif_link->mac_idx); 4609 4610 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4611 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4612 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4613 } 4614 4615 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4616 struct rtw89_vif_link *rtwvif_link, 4617 struct rtw89_vif_link *rtwvif_src, 4618 u8 offset, int *n_offset) 4619 { 4620 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif_link == rtwvif_src) 4621 return; 4622 4623 /* adjust offset randomly to avoid beacon conflict */ 4624 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4625 rtw89_mac_port_tsf_sync(rtwdev, rtwvif_link, rtwvif_src, 4626 (*n_offset) * offset); 4627 4628 (*n_offset)++; 4629 } 4630 4631 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4632 { 4633 struct rtw89_vif_link *src = NULL, *tmp; 4634 u8 offset = 100, vif_aps = 0; 4635 struct rtw89_vif *rtwvif; 4636 unsigned int link_id; 4637 int n_offset = 1; 4638 4639 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4640 rtw89_vif_for_each_link(rtwvif, tmp, link_id) { 4641 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4642 src = tmp; 4643 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4644 vif_aps++; 4645 } 4646 } 4647 4648 if (vif_aps == 0) 4649 return; 4650 4651 offset /= (vif_aps + 1); 4652 4653 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4654 rtw89_vif_for_each_link(rtwvif, tmp, link_id) 4655 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, 4656 &n_offset); 4657 } 4658 4659 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4660 { 4661 int ret; 4662 4663 ret = rtw89_mac_port_update(rtwdev, rtwvif_link); 4664 if (ret) 4665 return ret; 4666 4667 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4668 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4669 4670 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif_link->mac_id, false); 4671 if (ret) 4672 return ret; 4673 4674 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_CREATE); 4675 if (ret) 4676 return ret; 4677 4678 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, NULL, true); 4679 if (ret) 4680 return ret; 4681 4682 ret = rtw89_cam_init(rtwdev, rtwvif_link); 4683 if (ret) 4684 return ret; 4685 4686 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL); 4687 if (ret) 4688 return ret; 4689 4690 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, NULL); 4691 if (ret) 4692 return ret; 4693 4694 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, NULL); 4695 if (ret) 4696 return ret; 4697 4698 return 0; 4699 } 4700 4701 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4702 { 4703 int ret; 4704 4705 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_REMOVE); 4706 if (ret) 4707 return ret; 4708 4709 rtw89_cam_deinit(rtwdev, rtwvif_link); 4710 4711 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL); 4712 if (ret) 4713 return ret; 4714 4715 return 0; 4716 } 4717 4718 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4719 { 4720 u8 port = rtwvif_link->port; 4721 4722 if (port >= RTW89_PORT_NUM) 4723 return -EINVAL; 4724 4725 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 4726 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif_link, false); 4727 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif_link, false); 4728 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif_link); 4729 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif_link); 4730 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif_link); 4731 rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif_link); 4732 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif_link); 4733 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif_link); 4734 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif_link); 4735 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif_link); 4736 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif_link); 4737 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif_link); 4738 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif_link); 4739 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif_link); 4740 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif_link); 4741 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif_link); 4742 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif_link); 4743 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif_link); 4744 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif_link, true); 4745 rtw89_mac_port_tsf_resync_all(rtwdev); 4746 fsleep(BCN_ERLY_SET_DLY); 4747 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif_link); 4748 4749 return 0; 4750 } 4751 4752 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4753 u64 *tsf) 4754 { 4755 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4756 const struct rtw89_port_reg *p = mac->port_base; 4757 u32 tsf_low, tsf_high; 4758 int ret; 4759 4760 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif_link->mac_idx, RTW89_CMAC_SEL); 4761 if (ret) 4762 return ret; 4763 4764 tsf_low = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_l); 4765 tsf_high = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_h); 4766 *tsf = (u64)tsf_high << 32 | tsf_low; 4767 4768 return 0; 4769 } 4770 4771 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4772 struct cfg80211_bss *bss, 4773 void *data) 4774 { 4775 const struct cfg80211_bss_ies *ies; 4776 const struct element *elem; 4777 bool *tolerated = data; 4778 4779 rcu_read_lock(); 4780 ies = rcu_dereference(bss->ies); 4781 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4782 ies->len); 4783 4784 if (!elem || elem->datalen < 10 || 4785 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4786 *tolerated = false; 4787 rcu_read_unlock(); 4788 } 4789 4790 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4791 struct rtw89_vif_link *rtwvif_link) 4792 { 4793 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4794 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4795 struct ieee80211_hw *hw = rtwdev->hw; 4796 struct ieee80211_bss_conf *bss_conf; 4797 struct cfg80211_chan_def oper; 4798 bool tolerated = true; 4799 u32 reg; 4800 4801 rcu_read_lock(); 4802 4803 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4804 if (!bss_conf->he_support || vif->type != NL80211_IFTYPE_STATION) { 4805 rcu_read_unlock(); 4806 return; 4807 } 4808 4809 oper = bss_conf->chanreq.oper; 4810 if (!(oper.chan->flags & IEEE80211_CHAN_RADAR)) { 4811 rcu_read_unlock(); 4812 return; 4813 } 4814 4815 rcu_read_unlock(); 4816 4817 cfg80211_bss_iter(hw->wiphy, &oper, 4818 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4819 &tolerated); 4820 4821 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr, 4822 rtwvif_link->mac_idx); 4823 if (tolerated) 4824 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4825 else 4826 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4827 } 4828 4829 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4830 { 4831 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 4832 } 4833 4834 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4835 { 4836 return rtw89_mac_vif_init(rtwdev, rtwvif_link); 4837 } 4838 4839 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4840 { 4841 return rtw89_mac_vif_deinit(rtwdev, rtwvif_link); 4842 } 4843 4844 static void 4845 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4846 { 4847 } 4848 4849 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4850 { 4851 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4852 4853 return band == op->band_type && channel == op->primary_channel; 4854 } 4855 4856 static void 4857 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4858 u32 len) 4859 { 4860 const struct rtw89_c2h_scanofld *c2h = 4861 (const struct rtw89_c2h_scanofld *)skb->data; 4862 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 4863 struct rtw89_vif *rtwvif; 4864 struct rtw89_chan new; 4865 u32 last_chan = rtwdev->scan_info.last_chan_idx, report_tsf; 4866 u16 actual_period, expect_period; 4867 u8 reason, status, tx_fail, band; 4868 u8 mac_idx, sw_def, fw_def; 4869 u8 ver = U8_MAX; 4870 u16 chan; 4871 int ret; 4872 4873 if (!rtwvif_link) 4874 return; 4875 4876 rtwvif = rtwvif_link->rtwvif; 4877 4878 if (RTW89_CHK_FW_FEATURE(CH_INFO_BE_V0, &rtwdev->fw)) 4879 ver = 0; 4880 4881 tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL); 4882 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 4883 chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH); 4884 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 4885 band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND); 4886 actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD); 4887 mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX); 4888 4889 4890 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4891 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4892 4893 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4894 sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF); 4895 fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF); 4896 report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF); 4897 if (ver == 0) { 4898 expect_period = 4899 le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD); 4900 } else { 4901 actual_period = le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_PERIOD_V1); 4902 expect_period = 4903 le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1); 4904 } 4905 4906 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4907 "sw_def: %d, fw_def: %d, tsf: %x, expect: %d\n", 4908 sw_def, fw_def, report_tsf, expect_period); 4909 } 4910 4911 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4912 "mac_idx[%d] band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4913 mac_idx, band, chan, reason, status, tx_fail, actual_period); 4914 4915 switch (reason) { 4916 case RTW89_SCAN_LEAVE_OP_NOTIFY: 4917 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4918 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4919 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, false); 4920 ieee80211_stop_queues(rtwdev->hw); 4921 } 4922 return; 4923 case RTW89_SCAN_END_SCAN_NOTIFY: 4924 if (rtwdev->scan_info.abort) 4925 return; 4926 4927 if (rtwvif_link && rtwvif->scan_req && 4928 last_chan < rtwvif->scan_req->n_channels) { 4929 ret = rtw89_hw_scan_offload(rtwdev, rtwvif_link, true); 4930 if (ret) { 4931 rtw89_hw_scan_abort(rtwdev, rtwvif_link); 4932 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4933 } 4934 } else { 4935 rtw89_hw_scan_complete(rtwdev, rtwvif_link, false); 4936 } 4937 break; 4938 case RTW89_SCAN_ENTER_OP_NOTIFY: 4939 case RTW89_SCAN_ENTER_CH_NOTIFY: 4940 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4941 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, 4942 &rtwdev->scan_info.op_chan); 4943 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, true); 4944 ieee80211_wake_queues(rtwdev->hw); 4945 } else { 4946 rtw89_chan_create(&new, chan, chan, band, 4947 RTW89_CHANNEL_WIDTH_20); 4948 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, 4949 &new); 4950 } 4951 break; 4952 default: 4953 return; 4954 } 4955 } 4956 4957 static void 4958 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4959 struct sk_buff *skb) 4960 { 4961 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4962 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 4963 enum nl80211_cqm_rssi_threshold_event nl_event; 4964 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4965 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4966 u8 type, event, mac_id; 4967 s8 sig; 4968 4969 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4970 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4971 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4972 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4973 4974 if (mac_id != rtwvif_link->mac_id) 4975 return; 4976 4977 rtw89_debug(rtwdev, RTW89_DBG_FW, 4978 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4979 mac_id, type, sig, event); 4980 4981 switch (type) { 4982 case RTW89_BCN_FLTR_BEACON_LOSS: 4983 if (!rtwdev->scanning && !rtwvif->offchan) 4984 ieee80211_connection_loss(vif); 4985 else 4986 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 4987 return; 4988 case RTW89_BCN_FLTR_NOTIFY: 4989 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4990 break; 4991 case RTW89_BCN_FLTR_RSSI: 4992 if (event == RTW89_BCN_FLTR_RSSI_LOW) 4993 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4994 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4995 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4996 else 4997 return; 4998 break; 4999 default: 5000 return; 5001 } 5002 5003 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 5004 } 5005 5006 static void 5007 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5008 u32 len) 5009 { 5010 struct rtw89_vif_link *rtwvif_link; 5011 struct rtw89_vif *rtwvif; 5012 unsigned int link_id; 5013 5014 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5015 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 5016 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif_link, c2h); 5017 } 5018 5019 static void 5020 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5021 { 5022 /* N.B. This will run in interrupt context. */ 5023 5024 rtw89_debug(rtwdev, RTW89_DBG_FW, 5025 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 5026 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 5027 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 5028 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 5029 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 5030 } 5031 5032 static void 5033 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5034 { 5035 /* N.B. This will run in interrupt context. */ 5036 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5037 struct rtw89_wait_info *ps_wait = &rtwdev->mac.ps_wait; 5038 const struct rtw89_c2h_done_ack *c2h = 5039 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 5040 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 5041 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 5042 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 5043 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 5044 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 5045 struct rtw89_completion_data data = {}; 5046 unsigned int cond; 5047 5048 rtw89_debug(rtwdev, RTW89_DBG_FW, 5049 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 5050 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 5051 5052 if (h2c_cat != H2C_CAT_MAC) 5053 return; 5054 5055 switch (h2c_class) { 5056 default: 5057 return; 5058 case H2C_CL_MAC_PS: 5059 switch (h2c_func) { 5060 default: 5061 return; 5062 case H2C_FUNC_IPS_CFG: 5063 cond = RTW89_PS_WAIT_COND_IPS_CFG; 5064 break; 5065 } 5066 5067 data.err = !!h2c_return; 5068 rtw89_complete_cond(ps_wait, cond, &data); 5069 return; 5070 case H2C_CL_MAC_FW_OFLD: 5071 switch (h2c_func) { 5072 default: 5073 return; 5074 case H2C_FUNC_ADD_SCANOFLD_CH: 5075 cond = RTW89_SCANOFLD_WAIT_COND_ADD_CH; 5076 break; 5077 case H2C_FUNC_SCANOFLD: 5078 cond = RTW89_SCANOFLD_WAIT_COND_START; 5079 break; 5080 case H2C_FUNC_SCANOFLD_BE: 5081 cond = RTW89_SCANOFLD_BE_WAIT_COND_START; 5082 break; 5083 } 5084 5085 data.err = !!h2c_return; 5086 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5087 return; 5088 } 5089 } 5090 5091 static void 5092 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5093 { 5094 rtw89_fw_log_dump(rtwdev, c2h->data, len); 5095 } 5096 5097 static void 5098 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5099 { 5100 } 5101 5102 static void 5103 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 5104 u32 len) 5105 { 5106 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 5107 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 5108 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 5109 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 5110 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 5111 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 5112 struct rtw89_completion_data data = {}; 5113 unsigned int cond; 5114 5115 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 5116 pkt_id, pkt_op, pkt_len); 5117 5118 data.err = !pkt_len; 5119 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 5120 5121 rtw89_complete_cond(wait, cond, &data); 5122 } 5123 5124 static void 5125 rtw89_mac_c2h_tx_duty_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5126 { 5127 struct rtw89_c2h_tx_duty_rpt *c2h = 5128 (struct rtw89_c2h_tx_duty_rpt *)skb_c2h->data; 5129 u8 err; 5130 5131 err = le32_get_bits(c2h->w2, RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR); 5132 5133 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "C2H TX duty rpt with err=%d\n", err); 5134 } 5135 5136 static void 5137 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5138 u32 len) 5139 { 5140 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 5141 } 5142 5143 static void 5144 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5145 { 5146 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 5147 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 5148 5149 switch (func) { 5150 case H2C_FUNC_ADD_MCC: 5151 case H2C_FUNC_START_MCC: 5152 case H2C_FUNC_STOP_MCC: 5153 case H2C_FUNC_DEL_MCC_GROUP: 5154 case H2C_FUNC_RESET_MCC_GROUP: 5155 case H2C_FUNC_MCC_REQ_TSF: 5156 case H2C_FUNC_MCC_MACID_BITMAP: 5157 case H2C_FUNC_MCC_SYNC: 5158 case H2C_FUNC_MCC_SET_DURATION: 5159 break; 5160 default: 5161 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5162 "invalid MCC C2H RCV ACK: func %d\n", func); 5163 return; 5164 } 5165 5166 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5167 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 5168 } 5169 5170 static void 5171 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5172 { 5173 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 5174 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 5175 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 5176 struct rtw89_completion_data data = {}; 5177 unsigned int cond; 5178 bool next = false; 5179 5180 switch (func) { 5181 case H2C_FUNC_MCC_REQ_TSF: 5182 next = true; 5183 break; 5184 case H2C_FUNC_MCC_MACID_BITMAP: 5185 case H2C_FUNC_MCC_SYNC: 5186 case H2C_FUNC_MCC_SET_DURATION: 5187 break; 5188 case H2C_FUNC_ADD_MCC: 5189 case H2C_FUNC_START_MCC: 5190 case H2C_FUNC_STOP_MCC: 5191 case H2C_FUNC_DEL_MCC_GROUP: 5192 case H2C_FUNC_RESET_MCC_GROUP: 5193 default: 5194 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5195 "invalid MCC C2H REQ ACK: func %d\n", func); 5196 return; 5197 } 5198 5199 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5200 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 5201 group, func, retcode); 5202 5203 if (!retcode && next) 5204 return; 5205 5206 data.err = !!retcode; 5207 cond = RTW89_MCC_WAIT_COND(group, func); 5208 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5209 } 5210 5211 static void 5212 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5213 { 5214 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 5215 struct rtw89_completion_data data = {}; 5216 struct rtw89_mac_mcc_tsf_rpt *rpt; 5217 unsigned int cond; 5218 5219 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 5220 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 5221 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 5222 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 5223 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 5224 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 5225 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 5226 5227 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5228 #if defined(__linux__) 5229 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 5230 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5231 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5232 #elif defined(__FreeBSD__) 5233 "MCC C2H TSF RPT: macid %d> %ju, macid %d> %ju\n", 5234 rpt->macid_x, (uintmax_t)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5235 rpt->macid_y, (uintmax_t)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5236 #endif 5237 5238 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 5239 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5240 } 5241 5242 static void 5243 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5244 { 5245 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 5246 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 5247 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 5248 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 5249 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 5250 struct rtw89_completion_data data = {}; 5251 unsigned int cond; 5252 bool rsp = true; 5253 bool err; 5254 u8 func; 5255 5256 switch (status) { 5257 case RTW89_MAC_MCC_ADD_ROLE_OK: 5258 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 5259 func = H2C_FUNC_ADD_MCC; 5260 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 5261 break; 5262 case RTW89_MAC_MCC_START_GROUP_OK: 5263 case RTW89_MAC_MCC_START_GROUP_FAIL: 5264 func = H2C_FUNC_START_MCC; 5265 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 5266 break; 5267 case RTW89_MAC_MCC_STOP_GROUP_OK: 5268 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 5269 func = H2C_FUNC_STOP_MCC; 5270 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 5271 break; 5272 case RTW89_MAC_MCC_DEL_GROUP_OK: 5273 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 5274 func = H2C_FUNC_DEL_MCC_GROUP; 5275 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 5276 break; 5277 case RTW89_MAC_MCC_RESET_GROUP_OK: 5278 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 5279 func = H2C_FUNC_RESET_MCC_GROUP; 5280 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 5281 break; 5282 case RTW89_MAC_MCC_SWITCH_CH_OK: 5283 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 5284 case RTW89_MAC_MCC_TXNULL0_OK: 5285 case RTW89_MAC_MCC_TXNULL0_FAIL: 5286 case RTW89_MAC_MCC_TXNULL1_OK: 5287 case RTW89_MAC_MCC_TXNULL1_FAIL: 5288 case RTW89_MAC_MCC_SWITCH_EARLY: 5289 case RTW89_MAC_MCC_TBTT: 5290 case RTW89_MAC_MCC_DURATION_START: 5291 case RTW89_MAC_MCC_DURATION_END: 5292 rsp = false; 5293 break; 5294 default: 5295 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5296 "invalid MCC C2H STS RPT: status %d\n", status); 5297 return; 5298 } 5299 5300 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5301 #if defined(__linux__) 5302 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5303 group, macid, status, (u64)tsf_high << 32 | tsf_low); 5304 #elif defined(__FreeBSD__) 5305 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %ju\n", 5306 group, macid, status, (uintmax_t)tsf_high << 32 | tsf_low); 5307 #endif 5308 5309 if (!rsp) 5310 return; 5311 5312 data.err = err; 5313 cond = RTW89_MCC_WAIT_COND(group, func); 5314 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5315 } 5316 5317 static void 5318 rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5319 { 5320 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5321 const struct rtw89_c2h_mrc_tsf_rpt *c2h_rpt; 5322 struct rtw89_completion_data data = {}; 5323 struct rtw89_mac_mrc_tsf_rpt *rpt; 5324 unsigned int i; 5325 5326 c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data; 5327 rpt = (struct rtw89_mac_mrc_tsf_rpt *)data.buf; 5328 rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM, 5329 le32_get_bits(c2h_rpt->w2, 5330 RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM)); 5331 5332 for (i = 0; i < rpt->num; i++) { 5333 u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high); 5334 u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low); 5335 5336 rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low; 5337 5338 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5339 #if defined(__linux__) 5340 "MRC C2H TSF RPT: index %u> %llu\n", 5341 i, rpt->tsfs[i]); 5342 #elif defined(__FreeBSD__) 5343 "MRC C2H TSF RPT: index %u> %ju\n", 5344 i, (uintmax_t)rpt->tsfs[i]); 5345 #endif 5346 } 5347 5348 rtw89_complete_cond(wait, RTW89_MRC_WAIT_COND_REQ_TSF, &data); 5349 } 5350 5351 static void 5352 rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5353 { 5354 struct rtw89_wow_param *rtw_wow = &rtwdev->wow; 5355 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt; 5356 struct rtw89_wait_info *wait = &rtw_wow->wait; 5357 const struct rtw89_c2h_wow_aoac_report *c2h = 5358 (const struct rtw89_c2h_wow_aoac_report *)skb->data; 5359 struct rtw89_completion_data data = {}; 5360 5361 aoac_rpt->rpt_ver = c2h->rpt_ver; 5362 aoac_rpt->sec_type = c2h->sec_type; 5363 aoac_rpt->key_idx = c2h->key_idx; 5364 aoac_rpt->pattern_idx = c2h->pattern_idx; 5365 aoac_rpt->rekey_ok = u8_get_bits(c2h->rekey_ok, 5366 RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX); 5367 memcpy(aoac_rpt->ptk_tx_iv, c2h->ptk_tx_iv, sizeof(aoac_rpt->ptk_tx_iv)); 5368 memcpy(aoac_rpt->eapol_key_replay_count, c2h->eapol_key_replay_count, 5369 sizeof(aoac_rpt->eapol_key_replay_count)); 5370 memcpy(aoac_rpt->gtk, c2h->gtk, sizeof(aoac_rpt->gtk)); 5371 memcpy(aoac_rpt->ptk_rx_iv, c2h->ptk_rx_iv, sizeof(aoac_rpt->ptk_rx_iv)); 5372 memcpy(aoac_rpt->gtk_rx_iv, c2h->gtk_rx_iv, sizeof(aoac_rpt->gtk_rx_iv)); 5373 aoac_rpt->igtk_key_id = le64_to_cpu(c2h->igtk_key_id); 5374 aoac_rpt->igtk_ipn = le64_to_cpu(c2h->igtk_ipn); 5375 memcpy(aoac_rpt->igtk, c2h->igtk, sizeof(aoac_rpt->igtk)); 5376 5377 rtw89_complete_cond(wait, RTW89_WOW_WAIT_COND_AOAC, &data); 5378 } 5379 5380 static void 5381 rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5382 { 5383 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5384 const struct rtw89_c2h_mrc_status_rpt *c2h_rpt; 5385 struct rtw89_completion_data data = {}; 5386 enum rtw89_mac_mrc_status status; 5387 unsigned int cond; 5388 bool next = false; 5389 u32 tsf_high; 5390 u32 tsf_low; 5391 u8 sch_idx; 5392 u8 func; 5393 5394 c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data; 5395 sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX); 5396 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS); 5397 tsf_high = le32_to_cpu(c2h_rpt->tsf_high); 5398 tsf_low = le32_to_cpu(c2h_rpt->tsf_low); 5399 5400 switch (status) { 5401 case RTW89_MAC_MRC_START_SCH_OK: 5402 func = H2C_FUNC_START_MRC; 5403 break; 5404 case RTW89_MAC_MRC_STOP_SCH_OK: 5405 /* H2C_FUNC_DEL_MRC without STOP_ONLY, so wait for DEL_SCH_OK */ 5406 func = H2C_FUNC_DEL_MRC; 5407 next = true; 5408 break; 5409 case RTW89_MAC_MRC_DEL_SCH_OK: 5410 func = H2C_FUNC_DEL_MRC; 5411 break; 5412 case RTW89_MAC_MRC_EMPTY_SCH_FAIL: 5413 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5414 "MRC C2H STS RPT: empty sch fail\n"); 5415 return; 5416 case RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL: 5417 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5418 "MRC C2H STS RPT: role not exist fail\n"); 5419 return; 5420 case RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL: 5421 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5422 "MRC C2H STS RPT: data not found fail\n"); 5423 return; 5424 case RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL: 5425 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5426 "MRC C2H STS RPT: get next slot fail\n"); 5427 return; 5428 case RTW89_MAC_MRC_ALT_ROLE_FAIL: 5429 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5430 "MRC C2H STS RPT: alt role fail\n"); 5431 return; 5432 case RTW89_MAC_MRC_ADD_PSTIMER_FAIL: 5433 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5434 "MRC C2H STS RPT: add ps timer fail\n"); 5435 return; 5436 case RTW89_MAC_MRC_MALLOC_FAIL: 5437 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5438 "MRC C2H STS RPT: malloc fail\n"); 5439 return; 5440 case RTW89_MAC_MRC_SWITCH_CH_FAIL: 5441 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5442 "MRC C2H STS RPT: switch ch fail\n"); 5443 return; 5444 case RTW89_MAC_MRC_TXNULL0_FAIL: 5445 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5446 "MRC C2H STS RPT: tx null-0 fail\n"); 5447 return; 5448 case RTW89_MAC_MRC_PORT_FUNC_EN_FAIL: 5449 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5450 "MRC C2H STS RPT: port func en fail\n"); 5451 return; 5452 default: 5453 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5454 "invalid MRC C2H STS RPT: status %d\n", status); 5455 return; 5456 } 5457 5458 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5459 #if defined(__linux__) 5460 "MRC C2H STS RPT: sch_idx %d, status %d, tsf %llu\n", 5461 sch_idx, status, (u64)tsf_high << 32 | tsf_low); 5462 #elif defined(__FreeBSD__) 5463 "MRC C2H STS RPT: sch_idx %d, status %d, tsf %ju\n", 5464 sch_idx, status, (uintmax_t)tsf_high << 32 | tsf_low); 5465 #endif 5466 5467 if (next) 5468 return; 5469 5470 cond = RTW89_MRC_WAIT_COND(sch_idx, func); 5471 rtw89_complete_cond(wait, cond, &data); 5472 } 5473 5474 static void 5475 rtw89_mac_c2h_pwr_int_notify(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5476 { 5477 const struct rtw89_c2h_pwr_int_notify *c2h; 5478 struct rtw89_sta_link *rtwsta_link; 5479 struct ieee80211_sta *sta; 5480 struct rtw89_sta *rtwsta; 5481 u16 macid; 5482 bool ps; 5483 5484 c2h = (const struct rtw89_c2h_pwr_int_notify *)skb->data; 5485 macid = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_MACID); 5486 ps = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS); 5487 5488 rcu_read_lock(); 5489 5490 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 5491 if (unlikely(!rtwsta_link)) 5492 goto out; 5493 5494 rtwsta = rtwsta_link->rtwsta; 5495 if (ps) 5496 set_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags); 5497 else 5498 clear_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags); 5499 5500 sta = rtwsta_to_sta(rtwsta); 5501 ieee80211_sta_ps_transition(sta, ps); 5502 5503 out: 5504 rcu_read_unlock(); 5505 } 5506 5507 static 5508 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 5509 struct sk_buff *c2h, u32 len) = { 5510 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5511 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 5512 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5513 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 5514 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 5515 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5516 [RTW89_MAC_C2H_FUNC_TX_DUTY_RPT] = rtw89_mac_c2h_tx_duty_rpt, 5517 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 5518 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 5519 }; 5520 5521 static 5522 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 5523 struct sk_buff *c2h, u32 len) = { 5524 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 5525 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5526 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5527 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5528 }; 5529 5530 static 5531 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 5532 struct sk_buff *c2h, u32 len) = { 5533 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 5534 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 5535 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 5536 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 5537 }; 5538 5539 static 5540 void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev, 5541 struct sk_buff *c2h, u32 len) = { 5542 [RTW89_MAC_C2H_FUNC_MRC_TSF_RPT] = rtw89_mac_c2h_mrc_tsf_rpt, 5543 [RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT] = rtw89_mac_c2h_mrc_status_rpt, 5544 }; 5545 5546 static 5547 void (* const rtw89_mac_c2h_wow_handler[])(struct rtw89_dev *rtwdev, 5548 struct sk_buff *c2h, u32 len) = { 5549 [RTW89_MAC_C2H_FUNC_AOAC_REPORT] = rtw89_mac_c2h_wow_aoac_rpt, 5550 }; 5551 5552 static 5553 void (* const rtw89_mac_c2h_ap_handler[])(struct rtw89_dev *rtwdev, 5554 struct sk_buff *c2h, u32 len) = { 5555 [RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY] = rtw89_mac_c2h_pwr_int_notify, 5556 }; 5557 5558 static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev, 5559 struct sk_buff *skb) 5560 { 5561 const struct rtw89_c2h_scanofld *c2h = 5562 (const struct rtw89_c2h_scanofld *)skb->data; 5563 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5564 struct rtw89_completion_data data = {}; 5565 unsigned int cond; 5566 u8 status, reason; 5567 5568 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5569 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5570 data.err = status != RTW89_SCAN_STATUS_SUCCESS; 5571 5572 if (reason == RTW89_SCAN_END_SCAN_NOTIFY) { 5573 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 5574 cond = RTW89_SCANOFLD_BE_WAIT_COND_STOP; 5575 else 5576 cond = RTW89_SCANOFLD_WAIT_COND_STOP; 5577 5578 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5579 } 5580 } 5581 5582 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5583 u8 class, u8 func) 5584 { 5585 switch (class) { 5586 default: 5587 return false; 5588 case RTW89_MAC_C2H_CLASS_INFO: 5589 switch (func) { 5590 default: 5591 return false; 5592 case RTW89_MAC_C2H_FUNC_REC_ACK: 5593 case RTW89_MAC_C2H_FUNC_DONE_ACK: 5594 return true; 5595 } 5596 case RTW89_MAC_C2H_CLASS_OFLD: 5597 switch (func) { 5598 default: 5599 return false; 5600 case RTW89_MAC_C2H_FUNC_SCANOFLD_RSP: 5601 rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h); 5602 return false; 5603 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 5604 return true; 5605 } 5606 case RTW89_MAC_C2H_CLASS_MCC: 5607 return true; 5608 case RTW89_MAC_C2H_CLASS_MRC: 5609 return true; 5610 case RTW89_MAC_C2H_CLASS_WOW: 5611 return true; 5612 case RTW89_MAC_C2H_CLASS_AP: 5613 switch (func) { 5614 default: 5615 return false; 5616 case RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY: 5617 return true; 5618 } 5619 } 5620 } 5621 5622 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5623 u32 len, u8 class, u8 func) 5624 { 5625 void (*handler)(struct rtw89_dev *rtwdev, 5626 struct sk_buff *c2h, u32 len) = NULL; 5627 5628 switch (class) { 5629 case RTW89_MAC_C2H_CLASS_INFO: 5630 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 5631 handler = rtw89_mac_c2h_info_handler[func]; 5632 break; 5633 case RTW89_MAC_C2H_CLASS_OFLD: 5634 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 5635 handler = rtw89_mac_c2h_ofld_handler[func]; 5636 break; 5637 case RTW89_MAC_C2H_CLASS_MCC: 5638 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 5639 handler = rtw89_mac_c2h_mcc_handler[func]; 5640 break; 5641 case RTW89_MAC_C2H_CLASS_MRC: 5642 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MRC) 5643 handler = rtw89_mac_c2h_mrc_handler[func]; 5644 break; 5645 case RTW89_MAC_C2H_CLASS_WOW: 5646 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_WOW) 5647 handler = rtw89_mac_c2h_wow_handler[func]; 5648 break; 5649 case RTW89_MAC_C2H_CLASS_AP: 5650 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_AP) 5651 handler = rtw89_mac_c2h_ap_handler[func]; 5652 break; 5653 case RTW89_MAC_C2H_CLASS_FWDBG: 5654 return; 5655 default: 5656 rtw89_info(rtwdev, "MAC c2h class %d not support\n", class); 5657 return; 5658 } 5659 if (!handler) { 5660 rtw89_info(rtwdev, "MAC c2h class %d func %d not support\n", class, 5661 func); 5662 return; 5663 } 5664 handler(rtwdev, skb, len); 5665 } 5666 5667 static 5668 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 5669 enum rtw89_phy_idx phy_idx, 5670 u32 reg_base, u32 *cr) 5671 { 5672 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; 5673 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 5674 5675 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 5676 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 5677 addr); 5678 goto error; 5679 } 5680 5681 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 5682 if (mode == RTW89_QTA_SCC) { 5683 rtw89_err(rtwdev, 5684 "[TXPWR] addr=0x%x but hw not enable\n", 5685 addr); 5686 goto error; 5687 } 5688 5689 *cr = addr; 5690 return true; 5691 5692 error: 5693 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 5694 addr, phy_idx); 5695 5696 return false; 5697 } 5698 5699 static 5700 int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 5701 { 5702 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 5703 int ret; 5704 5705 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5706 if (ret) 5707 return ret; 5708 5709 if (!enable) { 5710 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 5711 return 0; 5712 } 5713 5714 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 5715 B_AX_APP_MAC_INFO_RPT | 5716 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 5717 B_AX_PPDU_STAT_RPT_CRC32); 5718 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 5719 RTW89_PRPT_DEST_HOST); 5720 5721 return 0; 5722 } 5723 5724 static 5725 void __rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 5726 { 5727 #define MAC_AX_TIME_TH_SH 5 5728 #define MAC_AX_LEN_TH_SH 4 5729 #define MAC_AX_TIME_TH_MAX 255 5730 #define MAC_AX_LEN_TH_MAX 255 5731 #define MAC_AX_TIME_TH_DEF 88 5732 #define MAC_AX_LEN_TH_DEF 4080 5733 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5734 struct ieee80211_hw *hw = rtwdev->hw; 5735 u32 rts_threshold = hw->wiphy->rts_threshold; 5736 u32 time_th, len_th; 5737 u32 reg; 5738 5739 if (rts_threshold == (u32)-1) { 5740 time_th = MAC_AX_TIME_TH_DEF; 5741 len_th = MAC_AX_LEN_TH_DEF; 5742 } else { 5743 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 5744 len_th = rts_threshold; 5745 } 5746 5747 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 5748 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 5749 5750 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 5751 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 5752 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 5753 } 5754 5755 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev) 5756 { 5757 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 5758 if (rtwdev->dbcc_en) 5759 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_1); 5760 } 5761 5762 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 5763 { 5764 bool empty; 5765 int ret; 5766 5767 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5768 return; 5769 5770 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 5771 10000, 200000, false, rtwdev); 5772 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 5773 rtw89_info(rtwdev, "timed out to flush queues\n"); 5774 } 5775 5776 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 5777 { 5778 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 5779 u8 val; 5780 u16 val16; 5781 u32 val32; 5782 int ret; 5783 5784 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 5785 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5786 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 5787 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 5788 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 5789 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 5790 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5791 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 5792 5793 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 5794 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 5795 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 5796 5797 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 5798 if (ret) { 5799 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 5800 return ret; 5801 } 5802 val32 = val32 & B_AX_WL_RX_CTRL; 5803 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 5804 if (ret) { 5805 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 5806 return ret; 5807 } 5808 5809 switch (coex->pta_mode) { 5810 case RTW89_MAC_AX_COEX_RTK_MODE: 5811 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5812 val &= ~B_AX_BTMODE_MASK; 5813 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 5814 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5815 5816 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 5817 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 5818 5819 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 5820 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 5821 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 5822 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 5823 break; 5824 case RTW89_MAC_AX_COEX_CSR_MODE: 5825 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5826 val &= ~B_AX_BTMODE_MASK; 5827 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 5828 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5829 5830 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 5831 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 5832 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 5833 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 5834 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 5835 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 5836 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 5837 val16 |= B_AX_ENHANCED_BT; 5838 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 5839 5840 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 5841 break; 5842 default: 5843 return -EINVAL; 5844 } 5845 5846 switch (coex->direction) { 5847 case RTW89_MAC_AX_COEX_INNER: 5848 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5849 val = (val & ~BIT(2)) | BIT(1); 5850 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5851 break; 5852 case RTW89_MAC_AX_COEX_OUTPUT: 5853 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5854 val = val | BIT(1) | BIT(0); 5855 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5856 break; 5857 case RTW89_MAC_AX_COEX_INPUT: 5858 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5859 val = val & ~(BIT(2) | BIT(1)); 5860 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5861 break; 5862 default: 5863 return -EINVAL; 5864 } 5865 5866 return 0; 5867 } 5868 EXPORT_SYMBOL(rtw89_mac_coex_init); 5869 5870 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 5871 const struct rtw89_mac_ax_coex *coex) 5872 { 5873 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 5874 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 5875 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 5876 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 5877 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 5878 5879 switch (coex->pta_mode) { 5880 case RTW89_MAC_AX_COEX_RTK_MODE: 5881 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5882 MAC_AX_RTK_MODE); 5883 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 5884 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 5885 break; 5886 case RTW89_MAC_AX_COEX_CSR_MODE: 5887 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5888 MAC_AX_CSR_MODE); 5889 break; 5890 default: 5891 return -EINVAL; 5892 } 5893 5894 return 0; 5895 } 5896 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 5897 5898 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5899 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5900 { 5901 u32 val = 0, ret; 5902 5903 if (gnt_cfg->band[0].gnt_bt) 5904 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 5905 5906 if (gnt_cfg->band[0].gnt_bt_sw_en) 5907 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 5908 5909 if (gnt_cfg->band[0].gnt_wl) 5910 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 5911 5912 if (gnt_cfg->band[0].gnt_wl_sw_en) 5913 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 5914 5915 if (gnt_cfg->band[1].gnt_bt) 5916 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 5917 5918 if (gnt_cfg->band[1].gnt_bt_sw_en) 5919 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 5920 5921 if (gnt_cfg->band[1].gnt_wl) 5922 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 5923 5924 if (gnt_cfg->band[1].gnt_wl_sw_en) 5925 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 5926 5927 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 5928 if (ret) { 5929 rtw89_err(rtwdev, "Write LTE fail!\n"); 5930 return ret; 5931 } 5932 5933 return 0; 5934 } 5935 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 5936 5937 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 5938 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5939 { 5940 u32 val = 0; 5941 5942 if (gnt_cfg->band[0].gnt_bt) 5943 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 5944 B_AX_GNT_BT_TX_VAL; 5945 else 5946 val |= B_AX_WL_ACT_VAL; 5947 5948 if (gnt_cfg->band[0].gnt_bt_sw_en) 5949 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5950 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5951 5952 if (gnt_cfg->band[0].gnt_wl) 5953 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 5954 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5955 5956 if (gnt_cfg->band[0].gnt_wl_sw_en) 5957 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5958 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5959 5960 if (gnt_cfg->band[1].gnt_bt) 5961 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 5962 B_AX_GNT_BT_TX_VAL; 5963 else 5964 val |= B_AX_WL_ACT_VAL; 5965 5966 if (gnt_cfg->band[1].gnt_bt_sw_en) 5967 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5968 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5969 5970 if (gnt_cfg->band[1].gnt_wl) 5971 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 5972 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5973 5974 if (gnt_cfg->band[1].gnt_wl_sw_en) 5975 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5976 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5977 5978 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 5979 5980 return 0; 5981 } 5982 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 5983 5984 static 5985 int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 5986 { 5987 u32 reg; 5988 u16 val; 5989 int ret; 5990 5991 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 5992 if (ret) 5993 return ret; 5994 5995 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 5996 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 5997 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 5998 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 5999 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 6000 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 6001 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 6002 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 6003 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 6004 B_AX_PLT_EN; 6005 rtw89_write16(rtwdev, reg, val); 6006 6007 return 0; 6008 } 6009 6010 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 6011 { 6012 u32 fw_sb; 6013 6014 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 6015 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 6016 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 6017 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6018 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 6019 else 6020 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 6021 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 6022 val = B_AX_TOGGLE | 6023 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 6024 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 6025 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 6026 fsleep(1000); /* avoid BT FW loss information */ 6027 } 6028 6029 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 6030 { 6031 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 6032 } 6033 6034 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6035 { 6036 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 6037 6038 val = wl ? val | BIT(2) : val & ~BIT(2); 6039 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 6040 6041 return 0; 6042 } 6043 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 6044 6045 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 6046 { 6047 struct rtw89_btc *btc = &rtwdev->btc; 6048 struct rtw89_btc_dm *dm = &btc->dm; 6049 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 6050 int i; 6051 6052 if (wl) 6053 return 0; 6054 6055 for (i = 0; i < RTW89_PHY_MAX; i++) { 6056 g[i].gnt_bt_sw_en = 1; 6057 g[i].gnt_bt = 1; 6058 g[i].gnt_wl_sw_en = 1; 6059 g[i].gnt_wl = 0; 6060 } 6061 6062 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 6063 } 6064 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 6065 6066 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 6067 { 6068 const struct rtw89_chip_info *chip = rtwdev->chip; 6069 u8 val = 0; 6070 6071 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) 6072 return false; 6073 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 6074 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 6075 B_AX_LTE_MUX_CTRL_PATH >> 24); 6076 6077 return !!val; 6078 } 6079 6080 static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band) 6081 { 6082 u32 reg; 6083 u16 cnt; 6084 6085 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 6086 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 6087 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 6088 6089 return cnt; 6090 } 6091 6092 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 6093 bool keep) 6094 { 6095 u32 reg; 6096 6097 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 6098 return; 6099 6100 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 6101 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6102 if (keep) { 6103 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6104 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6105 BFRP_RX_STANDBY_TIMER_KEEP); 6106 } else { 6107 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6108 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6109 BFRP_RX_STANDBY_TIMER_RELEASE); 6110 } 6111 } 6112 6113 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 6114 { 6115 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6116 u32 reg; 6117 u32 mask = mac->bfee_ctrl.mask; 6118 6119 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 6120 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 6121 if (en) { 6122 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6123 rtw89_write32_set(rtwdev, reg, mask); 6124 } else { 6125 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6126 rtw89_write32_clr(rtwdev, reg, mask); 6127 } 6128 } 6129 6130 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 6131 { 6132 u32 reg; 6133 u32 val32; 6134 int ret; 6135 6136 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6137 if (ret) 6138 return ret; 6139 6140 /* AP mode set tx gid to 63 */ 6141 /* STA mode set tx gid to 0(default) */ 6142 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 6143 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 6144 6145 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 6146 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 6147 6148 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6149 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 6150 rtw89_write32(rtwdev, reg, val32); 6151 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 6152 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 6153 6154 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6155 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 6156 B_AX_BFMEE_USE_NSTS | 6157 B_AX_BFMEE_CSI_GID_SEL | 6158 B_AX_BFMEE_CSI_FORCE_RETE_EN); 6159 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 6160 rtw89_write32(rtwdev, reg, 6161 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 6162 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 6163 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 6164 6165 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 6166 rtw89_write32_set(rtwdev, reg, 6167 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 6168 6169 return 0; 6170 } 6171 6172 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 6173 struct rtw89_vif_link *rtwvif_link, 6174 struct rtw89_sta_link *rtwsta_link) 6175 { 6176 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 6177 struct ieee80211_link_sta *link_sta; 6178 u8 mac_idx = rtwvif_link->mac_idx; 6179 u8 port_sel = rtwvif_link->port; 6180 u8 sound_dim = 3, t; 6181 u8 *phy_cap; 6182 u32 reg; 6183 u16 val; 6184 int ret; 6185 6186 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6187 if (ret) 6188 return ret; 6189 6190 rcu_read_lock(); 6191 6192 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6193 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info; 6194 6195 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6196 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 6197 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 6198 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 6199 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 6200 phy_cap[5]); 6201 sound_dim = min(sound_dim, t); 6202 } 6203 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6204 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 6205 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 6206 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 6207 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 6208 link_sta->vht_cap.cap); 6209 sound_dim = min(sound_dim, t); 6210 } 6211 nc = min(nc, sound_dim); 6212 nr = min(nr, sound_dim); 6213 6214 rcu_read_unlock(); 6215 6216 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6217 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6218 6219 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 6220 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 6221 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 6222 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 6223 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 6224 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 6225 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 6226 6227 if (port_sel == 0) 6228 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6229 else 6230 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 6231 6232 rtw89_write16(rtwdev, reg, val); 6233 6234 return 0; 6235 } 6236 6237 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 6238 struct rtw89_vif_link *rtwvif_link, 6239 struct rtw89_sta_link *rtwsta_link) 6240 { 6241 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 6242 struct ieee80211_link_sta *link_sta; 6243 u8 mac_idx = rtwvif_link->mac_idx; 6244 u32 reg; 6245 int ret; 6246 6247 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6248 if (ret) 6249 return ret; 6250 6251 rcu_read_lock(); 6252 6253 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6254 6255 if (link_sta->he_cap.has_he) { 6256 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 6257 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 6258 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 6259 } 6260 if (link_sta->vht_cap.vht_supported) { 6261 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 6262 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 6263 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 6264 } 6265 if (link_sta->ht_cap.ht_supported) { 6266 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 6267 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 6268 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 6269 } 6270 6271 rcu_read_unlock(); 6272 6273 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6274 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6275 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 6276 rtw89_write32(rtwdev, 6277 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 6278 rrsc); 6279 6280 return 0; 6281 } 6282 6283 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 6284 struct rtw89_vif_link *rtwvif_link, 6285 struct rtw89_sta_link *rtwsta_link) 6286 { 6287 struct ieee80211_link_sta *link_sta; 6288 bool has_beamformer_cap; 6289 6290 rcu_read_lock(); 6291 6292 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6293 has_beamformer_cap = rtw89_sta_has_beamformer_cap(link_sta); 6294 6295 rcu_read_unlock(); 6296 6297 if (has_beamformer_cap) { 6298 rtw89_debug(rtwdev, RTW89_DBG_BF, 6299 "initialize bfee for new association\n"); 6300 rtw89_mac_init_bfee_ax(rtwdev, rtwvif_link->mac_idx); 6301 rtw89_mac_set_csi_para_reg_ax(rtwdev, rtwvif_link, rtwsta_link); 6302 rtw89_mac_csi_rrsc_ax(rtwdev, rtwvif_link, rtwsta_link); 6303 } 6304 } 6305 6306 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, 6307 struct rtw89_vif_link *rtwvif_link, 6308 struct rtw89_sta_link *rtwsta_link) 6309 { 6310 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, false); 6311 } 6312 6313 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6314 struct ieee80211_bss_conf *conf) 6315 { 6316 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 6317 struct rtw89_vif_link *rtwvif_link; 6318 u8 mac_idx; 6319 __le32 *p; 6320 6321 rtwvif_link = rtwvif->links[conf->link_id]; 6322 if (unlikely(!rtwvif_link)) { 6323 rtw89_err(rtwdev, 6324 "%s: rtwvif link (link_id %u) is not active\n", 6325 __func__, conf->link_id); 6326 return; 6327 } 6328 6329 mac_idx = rtwvif_link->mac_idx; 6330 6331 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 6332 6333 p = (__le32 *)conf->mu_group.membership; 6334 rtw89_write32(rtwdev, 6335 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 6336 le32_to_cpu(p[0])); 6337 rtw89_write32(rtwdev, 6338 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 6339 le32_to_cpu(p[1])); 6340 6341 p = (__le32 *)conf->mu_group.position; 6342 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 6343 le32_to_cpu(p[0])); 6344 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 6345 le32_to_cpu(p[1])); 6346 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 6347 le32_to_cpu(p[2])); 6348 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 6349 le32_to_cpu(p[3])); 6350 } 6351 6352 struct rtw89_mac_bf_monitor_iter_data { 6353 struct rtw89_dev *rtwdev; 6354 struct rtw89_sta_link *down_rtwsta_link; 6355 int count; 6356 }; 6357 6358 static 6359 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 6360 { 6361 struct rtw89_mac_bf_monitor_iter_data *iter_data = 6362 (struct rtw89_mac_bf_monitor_iter_data *)data; 6363 struct rtw89_sta_link *down_rtwsta_link = iter_data->down_rtwsta_link; 6364 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6365 struct ieee80211_link_sta *link_sta; 6366 struct rtw89_sta_link *rtwsta_link; 6367 bool has_beamformer_cap = false; 6368 int *count = &iter_data->count; 6369 unsigned int link_id; 6370 6371 rcu_read_lock(); 6372 6373 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6374 if (rtwsta_link == down_rtwsta_link) 6375 continue; 6376 6377 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 6378 if (rtw89_sta_has_beamformer_cap(link_sta)) { 6379 has_beamformer_cap = true; 6380 break; 6381 } 6382 } 6383 6384 if (has_beamformer_cap) 6385 (*count)++; 6386 6387 rcu_read_unlock(); 6388 } 6389 6390 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 6391 struct rtw89_sta_link *rtwsta_link, 6392 bool disconnect) 6393 { 6394 struct rtw89_mac_bf_monitor_iter_data data; 6395 6396 data.rtwdev = rtwdev; 6397 data.down_rtwsta_link = disconnect ? rtwsta_link : NULL; 6398 data.count = 0; 6399 ieee80211_iterate_stations_atomic(rtwdev->hw, 6400 rtw89_mac_bf_monitor_calc_iter, 6401 &data); 6402 6403 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 6404 if (data.count) 6405 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6406 else 6407 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6408 } 6409 6410 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 6411 { 6412 struct rtw89_traffic_stats *stats = &rtwdev->stats; 6413 struct rtw89_vif_link *rtwvif_link; 6414 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 6415 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6416 struct rtw89_vif *rtwvif; 6417 bool keep_timer = true; 6418 unsigned int link_id; 6419 bool old_keep_timer; 6420 6421 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6422 6423 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 6424 keep_timer = false; 6425 6426 if (keep_timer != old_keep_timer) { 6427 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6428 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6429 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif_link->mac_idx, 6430 keep_timer); 6431 } 6432 6433 if (en == old) 6434 return; 6435 6436 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6437 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6438 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, en); 6439 } 6440 6441 static int 6442 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6443 u32 tx_time) 6444 { 6445 #define MAC_AX_DFLT_TX_TIME 5280 6446 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6447 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 6448 u32 reg; 6449 int ret = 0; 6450 6451 if (rtwsta_link->cctl_tx_time) { 6452 rtwsta_link->ampdu_max_time = (max_tx_time - 512) >> 9; 6453 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6454 } else { 6455 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6456 if (ret) { 6457 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 6458 return ret; 6459 } 6460 6461 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6462 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 6463 max_tx_time >> 5); 6464 } 6465 6466 return ret; 6467 } 6468 6469 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6470 bool resume, u32 tx_time) 6471 { 6472 int ret = 0; 6473 6474 if (!resume) { 6475 rtwsta_link->cctl_tx_time = true; 6476 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6477 } else { 6478 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6479 rtwsta_link->cctl_tx_time = false; 6480 } 6481 6482 return ret; 6483 } 6484 6485 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6486 u32 *tx_time) 6487 { 6488 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6489 u32 reg; 6490 int ret = 0; 6491 6492 if (rtwsta_link->cctl_tx_time) { 6493 *tx_time = (rtwsta_link->ampdu_max_time + 1) << 9; 6494 } else { 6495 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6496 if (ret) { 6497 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 6498 return ret; 6499 } 6500 6501 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6502 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 6503 } 6504 6505 return ret; 6506 } 6507 6508 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 6509 struct rtw89_sta_link *rtwsta_link, 6510 bool resume, u8 tx_retry) 6511 { 6512 int ret = 0; 6513 6514 rtwsta_link->data_tx_cnt_lmt = tx_retry; 6515 6516 if (!resume) { 6517 rtwsta_link->cctl_tx_retry_limit = true; 6518 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6519 } else { 6520 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6521 rtwsta_link->cctl_tx_retry_limit = false; 6522 } 6523 6524 return ret; 6525 } 6526 6527 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 6528 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry) 6529 { 6530 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6531 u32 reg; 6532 int ret = 0; 6533 6534 if (rtwsta_link->cctl_tx_retry_limit) { 6535 *tx_retry = rtwsta_link->data_tx_cnt_lmt; 6536 } else { 6537 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6538 if (ret) { 6539 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 6540 return ret; 6541 } 6542 6543 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx); 6544 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 6545 } 6546 6547 return ret; 6548 } 6549 6550 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 6551 struct rtw89_vif_link *rtwvif_link, bool en) 6552 { 6553 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6554 u8 mac_idx = rtwvif_link->mac_idx; 6555 u16 set = mac->muedca_ctrl.mask; 6556 u32 reg; 6557 u32 ret; 6558 6559 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6560 if (ret) 6561 return ret; 6562 6563 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 6564 if (en) 6565 rtw89_write16_set(rtwdev, reg, set); 6566 else 6567 rtw89_write16_clr(rtwdev, reg, set); 6568 6569 return 0; 6570 } 6571 6572 static 6573 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 6574 { 6575 u32 val32; 6576 int ret; 6577 6578 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6579 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 6580 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 6581 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 6582 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6583 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6584 6585 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6586 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6587 if (ret) { 6588 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 6589 offset, val, mask); 6590 return ret; 6591 } 6592 6593 return 0; 6594 } 6595 6596 static 6597 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 6598 { 6599 u32 val32; 6600 int ret; 6601 6602 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6603 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 6604 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 6605 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 6606 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6607 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6608 6609 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6610 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6611 if (ret) { 6612 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 6613 return ret; 6614 } 6615 6616 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 6617 6618 return 0; 6619 } 6620 6621 static 6622 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, 6623 struct rtw89_vif_link *rtwvif_link, 6624 struct rtw89_sta_link *rtwsta_link) 6625 { 6626 static const enum rtw89_pkt_drop_sel sels[] = { 6627 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 6628 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 6629 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 6630 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 6631 }; 6632 struct rtw89_pkt_drop_params params = {0}; 6633 int i; 6634 6635 params.mac_band = rtwvif_link->mac_idx; 6636 params.macid = rtwsta_link->mac_id; 6637 params.port = rtwvif_link->port; 6638 params.mbssid = 0; 6639 params.tf_trs = rtwvif_link->trigger; 6640 6641 for (i = 0; i < ARRAY_SIZE(sels); i++) { 6642 params.sel = sels[i]; 6643 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6644 } 6645 } 6646 6647 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 6648 { 6649 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6650 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6651 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6652 struct rtw89_vif_link *rtwvif_link; 6653 struct rtw89_sta_link *rtwsta_link; 6654 struct rtw89_vif *target = data; 6655 unsigned int link_id; 6656 6657 if (rtwvif != target) 6658 return; 6659 6660 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6661 rtwvif_link = rtwsta_link->rtwvif_link; 6662 rtw89_mac_pkt_drop_sta(rtwdev, rtwvif_link, rtwsta_link); 6663 } 6664 } 6665 6666 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 6667 { 6668 ieee80211_iterate_stations_atomic(rtwdev->hw, 6669 rtw89_mac_pkt_drop_vif_iter, 6670 rtwvif); 6671 } 6672 6673 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 6674 enum rtw89_mac_idx band) 6675 { 6676 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6677 struct rtw89_pkt_drop_params params = {0}; 6678 bool empty; 6679 int i, ret = 0, try_cnt = 3; 6680 6681 params.mac_band = band; 6682 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 6683 6684 for (i = 0; i < try_cnt; i++) { 6685 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 6686 50000, false, rtwdev); 6687 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 6688 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6689 else 6690 return 0; 6691 } 6692 return ret; 6693 } 6694 6695 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) 6696 { 6697 struct rtw89_mac_h2c_info h2c_info = {}; 6698 struct rtw89_mac_c2h_info c2h_info = {}; 6699 u32 ret; 6700 6701 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 6702 return 0; 6703 6704 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL; 6705 h2c_info.content_len = sizeof(h2c_info.u.hdr); 6706 h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN); 6707 6708 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 6709 if (ret) 6710 return ret; 6711 6712 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK) 6713 ret = -EINVAL; 6714 6715 return ret; 6716 } 6717 6718 static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow) 6719 { 6720 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6721 const struct rtw89_chip_info *chip = rtwdev->chip; 6722 int ret; 6723 6724 if (enable_wow) { 6725 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); 6726 if (ret) { 6727 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6728 return ret; 6729 } 6730 6731 rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6732 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6733 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); 6734 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 6735 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); 6736 rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); 6737 rtw89_write32(rtwdev, R_AX_TF_FWD, 0); 6738 rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); 6739 6740 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 6741 return 0; 6742 6743 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 6744 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); 6745 else 6746 rtw89_write32_set(rtwdev, R_AX_DBG_WOW, 6747 B_AX_DBG_WOW_CPU_IO_RX_EN); 6748 } else { 6749 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); 6750 if (ret) { 6751 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6752 return ret; 6753 } 6754 6755 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6756 rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6757 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 6758 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 6759 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 6760 } 6761 6762 return 0; 6763 } 6764 6765 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 6766 { 6767 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 6768 6769 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 6770 } 6771 6772 static 6773 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 6774 bool h2c_or_fwdl) 6775 { 6776 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 6777 u8 val; 6778 6779 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 6780 1, FWDL_WAIT_CNT, false, 6781 rtwdev, R_AX_WCPU_FW_CTRL); 6782 } 6783 6784 static 6785 void rtw89_fwdl_secure_idmem_share_mode_ax(struct rtw89_dev *rtwdev, u8 mode) 6786 { 6787 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 6788 6789 if (!sec->secure_boot) 6790 return; 6791 6792 rtw89_write32_mask(rtwdev, R_AX_WCPU_FW_CTRL, 6793 B_AX_IDMEM_SHARE_MODE_RECORD_MASK, mode); 6794 rtw89_write32_set(rtwdev, R_AX_WCPU_FW_CTRL, 6795 B_AX_IDMEM_SHARE_MODE_RECORD_VALID); 6796 } 6797 6798 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 6799 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 6800 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 6801 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 6802 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 6803 .rx_fltr = R_AX_RX_FLTR_OPT, 6804 .port_base = &rtw89_port_base_ax, 6805 .agg_len_ht = R_AX_AGG_LEN_HT_0, 6806 .ps_status = R_AX_PPWRBIT_SETTING, 6807 6808 .muedca_ctrl = { 6809 .addr = R_AX_MUEDCA_EN, 6810 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 6811 }, 6812 .bfee_ctrl = { 6813 .addr = R_AX_BFMEE_RESP_OPTION, 6814 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 6815 B_AX_BFMEE_HE_NDPA_EN, 6816 }, 6817 .narrow_bw_ru_dis = { 6818 .addr = R_AX_RXTRIG_TEST_USER_2, 6819 .mask = B_AX_RXTRIG_RU26_DIS, 6820 }, 6821 .wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,}, 6822 6823 .check_mac_en = rtw89_mac_check_mac_en_ax, 6824 .sys_init = sys_init_ax, 6825 .trx_init = trx_init_ax, 6826 .hci_func_en = rtw89_mac_hci_func_en_ax, 6827 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 6828 .dle_func_en = dle_func_en_ax, 6829 .dle_clk_en = dle_clk_en_ax, 6830 .bf_assoc = rtw89_mac_bf_assoc_ax, 6831 6832 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 6833 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax, 6834 .cfg_phy_rpt = NULL, 6835 6836 .dle_mix_cfg = dle_mix_cfg_ax, 6837 .chk_dle_rdy = chk_dle_rdy_ax, 6838 .dle_buf_req = dle_buf_req_ax, 6839 .hfc_func_en = hfc_func_en_ax, 6840 .hfc_h2c_cfg = hfc_h2c_cfg_ax, 6841 .hfc_mix_cfg = hfc_mix_cfg_ax, 6842 .hfc_get_mix_info = hfc_get_mix_info_ax, 6843 .wde_quota_cfg = wde_quota_cfg_ax, 6844 .ple_quota_cfg = ple_quota_cfg_ax, 6845 .set_cpuio = set_cpuio_ax, 6846 .dle_quota_change = dle_quota_change_ax, 6847 6848 .disable_cpu = rtw89_mac_disable_cpu_ax, 6849 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 6850 .fwdl_get_status = rtw89_fw_get_rdy_ax, 6851 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 6852 .fwdl_secure_idmem_share_mode = rtw89_fwdl_secure_idmem_share_mode_ax, 6853 .parse_efuse_map = rtw89_parse_efuse_map_ax, 6854 .parse_phycap_map = rtw89_parse_phycap_map_ax, 6855 .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 6856 .efuse_read_fw_secure = rtw89_efuse_read_fw_secure_ax, 6857 6858 .cfg_plt = rtw89_mac_cfg_plt_ax, 6859 .get_plt_cnt = rtw89_mac_get_plt_cnt_ax, 6860 6861 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 6862 6863 .write_xtal_si = rtw89_mac_write_xtal_si_ax, 6864 .read_xtal_si = rtw89_mac_read_xtal_si_ax, 6865 6866 .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 6867 .dump_err_status = rtw89_mac_dump_err_status_ax, 6868 6869 .is_txq_empty = mac_is_txq_empty_ax, 6870 6871 .add_chan_list = rtw89_hw_scan_add_chan_list_ax, 6872 .add_chan_list_pno = rtw89_pno_scan_add_chan_list_ax, 6873 .scan_offload = rtw89_fw_h2c_scan_offload_ax, 6874 6875 .wow_config_mac = rtw89_wow_config_mac_ax, 6876 }; 6877 EXPORT_SYMBOL(rtw89_mac_gen_ax); 6878