1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "debug.h"
6 #include "efuse.h"
7 #include "fw.h"
8 #include "mac.h"
9 #include "reg.h"
10
11 static const u32 rtw89_mac_mem_base_addrs_be[RTW89_MAC_MEM_NUM] = {
12 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR_BE,
13 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR_BE,
14 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR_BE,
15 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR_BE,
16 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR_BE,
17 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR_BE,
18 [RTW89_MAC_MEM_SECURITY_CAM] = SEC_CAM_BASE_ADDR_BE,
19 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR_BE,
20 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR_BE,
21 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR_BE,
22 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR_BE,
23 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR_BE,
24 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR_BE,
25 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR_BE,
26 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR_BE,
27 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR_BE,
28 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR_BE,
29 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR_BE,
30 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR_BE,
31 [RTW89_MAC_MEM_WD_PAGE] = WD_PAGE_BASE_ADDR_BE,
32 [RTW89_MAC_MEM_MLD_TBL] = MLD_TBL_BASE_ADDR_BE,
33 };
34
35 static const struct rtw89_port_reg rtw89_port_base_be = {
36 .port_cfg = R_BE_PORT_CFG_P0,
37 .tbtt_prohib = R_BE_TBTT_PROHIB_P0,
38 .bcn_area = R_BE_BCN_AREA_P0,
39 .bcn_early = R_BE_BCNERLYINT_CFG_P0,
40 .tbtt_early = R_BE_TBTTERLYINT_CFG_P0,
41 .tbtt_agg = R_BE_TBTT_AGG_P0,
42 .bcn_space = R_BE_BCN_SPACE_CFG_P0,
43 .bcn_forcetx = R_BE_BCN_FORCETX_P0,
44 .bcn_err_cnt = R_BE_BCN_ERR_CNT_P0,
45 .bcn_err_flag = R_BE_BCN_ERR_FLAG_P0,
46 .dtim_ctrl = R_BE_DTIM_CTRL_P0,
47 .tbtt_shift = R_BE_TBTT_SHIFT_P0,
48 .bcn_cnt_tmr = R_BE_BCN_CNT_TMR_P0,
49 .tsftr_l = R_BE_TSFTR_LOW_P0,
50 .tsftr_h = R_BE_TSFTR_HIGH_P0,
51 .md_tsft = R_BE_WMTX_MOREDATA_TSFT_STMP_CTL,
52 .bss_color = R_BE_PTCL_BSS_COLOR_0,
53 .mbssid = R_BE_MBSSID_CTRL,
54 .mbssid_drop = R_BE_MBSSID_DROP_0,
55 .tsf_sync = R_BE_PORT_0_TSF_SYNC,
56 .ptcl_dbg = R_BE_PTCL_DBG,
57 .ptcl_dbg_info = R_BE_PTCL_DBG_INFO,
58 .bcn_drop_all = R_BE_BCN_DROP_ALL0,
59 .bcn_psr_rpt = R_BE_BCN_PSR_RPT_P0,
60 .hiq_win = {R_BE_P0MB_HGQ_WINDOW_CFG_0, R_BE_PORT_HGQ_WINDOW_CFG,
61 R_BE_PORT_HGQ_WINDOW_CFG + 1, R_BE_PORT_HGQ_WINDOW_CFG + 2,
62 R_BE_PORT_HGQ_WINDOW_CFG + 3},
63 };
64
65 static const struct rtw89_mac_mu_gid_addr rtw89_mac_mu_gid_addr_be = {
66 .position_en = {R_BE_GID_POSITION_EN0, R_BE_GID_POSITION_EN1},
67 .position = {R_BE_GID_POSITION0, R_BE_GID_POSITION1,
68 R_BE_GID_POSITION2, R_BE_GID_POSITION3},
69 };
70
rtw89_mac_check_mac_en_be(struct rtw89_dev * rtwdev,u8 mac_idx,enum rtw89_mac_hwmod_sel sel)71 static int rtw89_mac_check_mac_en_be(struct rtw89_dev *rtwdev, u8 mac_idx,
72 enum rtw89_mac_hwmod_sel sel)
73 {
74 if (sel == RTW89_DMAC_SEL &&
75 test_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags))
76 return 0;
77 if (sel == RTW89_CMAC_SEL && mac_idx == RTW89_MAC_0 &&
78 test_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags))
79 return 0;
80 if (sel == RTW89_CMAC_SEL && mac_idx == RTW89_MAC_1 &&
81 test_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags))
82 return 0;
83
84 return -EFAULT;
85 }
86
is_qta_poh(struct rtw89_dev * rtwdev)87 static bool is_qta_poh(struct rtw89_dev *rtwdev)
88 {
89 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE;
90 }
91
hfc_get_mix_info_be(struct rtw89_dev * rtwdev)92 static void hfc_get_mix_info_be(struct rtw89_dev *rtwdev)
93 {
94 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
95 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
96 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
97 struct rtw89_hfc_pub_info *info = ¶m->pub_info;
98 const struct rtw89_chip_info *chip = rtwdev->chip;
99 u32 val;
100
101 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO1);
102 info->g0_used = u32_get_bits(val, B_BE_G0_USE_PG_MASK);
103 info->g1_used = u32_get_bits(val, B_BE_G1_USE_PG_MASK);
104
105 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO3);
106 info->g0_aval = u32_get_bits(val, B_BE_G0_AVAL_PG_MASK);
107 info->g1_aval = u32_get_bits(val, B_BE_G1_AVAL_PG_MASK);
108 info->pub_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO2),
109 B_BE_PUB_AVAL_PG_MASK);
110 info->wp_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_WP_PAGE_INFO1),
111 B_BE_WP_AVAL_PG_MASK);
112
113 val = rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL);
114 param->en = !!(val & B_BE_HCI_FC_EN);
115 param->h2c_en = !!(val & B_BE_HCI_FC_CH12_EN);
116 param->mode = u32_get_bits(val, B_BE_HCI_FC_MODE_MASK);
117 prec_cfg->ch011_full_cond = u32_get_bits(val, B_BE_HCI_FC_WD_FULL_COND_MASK);
118 prec_cfg->h2c_full_cond = u32_get_bits(val, B_BE_HCI_FC_CH12_FULL_COND_MASK);
119 prec_cfg->wp_ch07_full_cond =
120 u32_get_bits(val, B_BE_HCI_FC_WP_CH07_FULL_COND_MASK);
121 prec_cfg->wp_ch811_full_cond =
122 u32_get_bits(val, B_BE_HCI_FC_WP_CH811_FULL_COND_MASK);
123
124 val = rtw89_read32(rtwdev, R_BE_CH_PAGE_CTRL);
125 prec_cfg->ch011_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH011_V1_MASK);
126 if (chip->chip_id == RTL8922D)
127 prec_cfg->ch011_full_page = u32_get_bits(val, B_BE_FULL_WD_PG_MASK);
128 prec_cfg->h2c_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH12_V1_MASK);
129
130 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_CTRL2);
131 pub_cfg->pub_max = u32_get_bits(val, B_BE_PUBPG_ALL_MASK);
132
133 val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL1);
134 if (chip->chip_id == RTL8922D) {
135 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_V1_MASK);
136 prec_cfg->wp_ch07_full_page = u32_get_bits(val, B_BE_FULL_PAGE_WP_CH07_MASK);
137 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_V1_MASK);
138 prec_cfg->wp_ch811_full_page = u32_get_bits(val, B_BE_FULL_PAGE_WP_CH811_MASK);
139 } else {
140 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_MASK);
141 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_MASK);
142 }
143
144 val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL2);
145 pub_cfg->wp_thrd = u32_get_bits(val, B_BE_WP_THRD_MASK);
146
147 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_CTRL1);
148 pub_cfg->grp0 = u32_get_bits(val, B_BE_PUBPG_G0_MASK);
149 pub_cfg->grp1 = u32_get_bits(val, B_BE_PUBPG_G1_MASK);
150 }
151
hfc_h2c_cfg_be(struct rtw89_dev * rtwdev)152 static void hfc_h2c_cfg_be(struct rtw89_dev *rtwdev)
153 {
154 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
155 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
156 u32 val;
157
158 val = u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK);
159 rtw89_write32(rtwdev, R_BE_CH_PAGE_CTRL, val);
160 }
161
hfc_mix_cfg_be(struct rtw89_dev * rtwdev)162 static void hfc_mix_cfg_be(struct rtw89_dev *rtwdev)
163 {
164 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
165 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
166 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
167 const struct rtw89_chip_info *chip = rtwdev->chip;
168 u32 val;
169
170 val = u32_encode_bits(prec_cfg->ch011_prec, B_BE_PREC_PAGE_CH011_V1_MASK) |
171 u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK);
172 if (chip->chip_id == RTL8922D)
173 val = u32_replace_bits(val, prec_cfg->ch011_full_page, B_BE_FULL_WD_PG_MASK);
174 rtw89_write32(rtwdev, R_BE_CH_PAGE_CTRL, val);
175
176 val = u32_encode_bits(pub_cfg->pub_max, B_BE_PUBPG_ALL_MASK);
177 rtw89_write32(rtwdev, R_BE_PUB_PAGE_CTRL2, val);
178
179 if (chip->chip_id == RTL8922D)
180 val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_V1_MASK) |
181 u32_encode_bits(prec_cfg->wp_ch07_full_page, B_BE_FULL_PAGE_WP_CH07_MASK) |
182 u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_V1_MASK) |
183 u32_encode_bits(prec_cfg->wp_ch811_full_page, B_BE_FULL_PAGE_WP_CH811_MASK);
184 else
185 val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_MASK) |
186 u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_MASK);
187 rtw89_write32(rtwdev, R_BE_WP_PAGE_CTRL1, val);
188
189 val = u32_replace_bits(rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL),
190 param->mode, B_BE_HCI_FC_MODE_MASK);
191 val = u32_replace_bits(val, prec_cfg->ch011_full_cond,
192 B_BE_HCI_FC_WD_FULL_COND_MASK);
193 val = u32_replace_bits(val, prec_cfg->h2c_full_cond,
194 B_BE_HCI_FC_CH12_FULL_COND_MASK);
195 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond,
196 B_BE_HCI_FC_WP_CH07_FULL_COND_MASK);
197 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond,
198 B_BE_HCI_FC_WP_CH811_FULL_COND_MASK);
199 rtw89_write32(rtwdev, R_BE_HCI_FC_CTRL, val);
200 }
201
hfc_func_en_be(struct rtw89_dev * rtwdev,bool en,bool h2c_en)202 static void hfc_func_en_be(struct rtw89_dev *rtwdev, bool en, bool h2c_en)
203 {
204 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
205 u32 val;
206
207 val = rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL);
208 param->en = en;
209 param->h2c_en = h2c_en;
210 val = en ? (val | B_BE_HCI_FC_EN) : (val & ~B_BE_HCI_FC_EN);
211 val = h2c_en ? (val | B_BE_HCI_FC_CH12_EN) :
212 (val & ~B_BE_HCI_FC_CH12_EN);
213 rtw89_write32(rtwdev, R_BE_HCI_FC_CTRL, val);
214 }
215
dle_func_en_be(struct rtw89_dev * rtwdev,bool enable)216 static void dle_func_en_be(struct rtw89_dev *rtwdev, bool enable)
217 {
218 if (enable)
219 rtw89_write32_set(rtwdev, R_BE_DMAC_FUNC_EN,
220 B_BE_DLE_WDE_EN | B_BE_DLE_PLE_EN);
221 else
222 rtw89_write32_clr(rtwdev, R_BE_DMAC_FUNC_EN,
223 B_BE_DLE_WDE_EN | B_BE_DLE_PLE_EN);
224 }
225
dle_clk_en_be(struct rtw89_dev * rtwdev,bool enable)226 static void dle_clk_en_be(struct rtw89_dev *rtwdev, bool enable)
227 {
228 if (rtwdev->chip->chip_id != RTL8922A)
229 return;
230
231 if (enable)
232 rtw89_write32_set(rtwdev, R_BE_DMAC_CLK_EN,
233 B_BE_DLE_WDE_CLK_EN | B_BE_DLE_PLE_CLK_EN);
234 else
235 rtw89_write32_clr(rtwdev, R_BE_DMAC_CLK_EN,
236 B_BE_DLE_WDE_CLK_EN | B_BE_DLE_PLE_CLK_EN);
237 }
238
dle_mix_cfg_be(struct rtw89_dev * rtwdev,const struct rtw89_dle_mem * cfg)239 static int dle_mix_cfg_be(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg)
240 {
241 const struct rtw89_dle_size *wde_size_cfg, *ple_size_cfg;
242 u32 bound;
243 u32 val;
244
245 wde_size_cfg = cfg->wde_size;
246 ple_size_cfg = cfg->ple_size;
247
248 val = rtw89_read32(rtwdev, R_BE_WDE_PKTBUF_CFG);
249
250 switch (wde_size_cfg->pge_size) {
251 default:
252 case RTW89_WDE_PG_64:
253 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64,
254 B_BE_WDE_PAGE_SEL_MASK);
255 break;
256 case RTW89_WDE_PG_128:
257 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128,
258 B_BE_WDE_PAGE_SEL_MASK);
259 break;
260 case RTW89_WDE_PG_256:
261 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n");
262 return -EINVAL;
263 }
264
265 bound = wde_size_cfg->srt_ofst / DLE_BOUND_UNIT;
266 val = u32_replace_bits(val, bound, B_BE_WDE_START_BOUND_MASK);
267 val = u32_replace_bits(val, wde_size_cfg->lnk_pge_num,
268 B_BE_WDE_FREE_PAGE_NUM_MASK);
269 rtw89_write32(rtwdev, R_BE_WDE_PKTBUF_CFG, val);
270
271 val = rtw89_read32(rtwdev, R_BE_PLE_PKTBUF_CFG);
272
273 switch (ple_size_cfg->pge_size) {
274 default:
275 case RTW89_PLE_PG_64:
276 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n");
277 return -EINVAL;
278 case RTW89_PLE_PG_128:
279 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128,
280 B_BE_PLE_PAGE_SEL_MASK);
281 break;
282 case RTW89_PLE_PG_256:
283 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256,
284 B_BE_PLE_PAGE_SEL_MASK);
285 break;
286 }
287
288 bound = ple_size_cfg->srt_ofst / DLE_BOUND_UNIT;
289 val = u32_replace_bits(val, bound, B_BE_PLE_START_BOUND_MASK);
290 val = u32_replace_bits(val, ple_size_cfg->lnk_pge_num,
291 B_BE_PLE_FREE_PAGE_NUM_MASK);
292 rtw89_write32(rtwdev, R_BE_PLE_PKTBUF_CFG, val);
293
294 return 0;
295 }
296
chk_dle_rdy_be(struct rtw89_dev * rtwdev,bool wde_or_ple)297 static int chk_dle_rdy_be(struct rtw89_dev *rtwdev, bool wde_or_ple)
298 {
299 u32 reg, mask;
300 u32 ini;
301
302 if (wde_or_ple) {
303 reg = R_AX_WDE_INI_STATUS;
304 mask = WDE_MGN_INI_RDY;
305 } else {
306 reg = R_AX_PLE_INI_STATUS;
307 mask = PLE_MGN_INI_RDY;
308 }
309
310 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1,
311 2000, false, rtwdev, reg);
312 }
313
314 #define INVALID_QT_WCPU U16_MAX
315 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \
316 do { \
317 val = u32_encode_bits(_min_x, B_BE_ ## _module ## _Q ## _idx ## _MIN_SIZE_MASK) | \
318 u32_encode_bits(_max_x, B_BE_ ## _module ## _Q ## _idx ## _MAX_SIZE_MASK); \
319 rtw89_write32(rtwdev, \
320 R_BE_ ## _module ## _QTA ## _idx ## _CFG, \
321 val); \
322 } while (0)
323 #define SET_QUOTA(_x, _module, _idx) \
324 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx)
325
wde_quota_cfg_be(struct rtw89_dev * rtwdev,const struct rtw89_wde_quota * min_cfg,const struct rtw89_wde_quota * max_cfg,u16 ext_wde_min_qt_wcpu)326 static void wde_quota_cfg_be(struct rtw89_dev *rtwdev,
327 const struct rtw89_wde_quota *min_cfg,
328 const struct rtw89_wde_quota *max_cfg,
329 u16 ext_wde_min_qt_wcpu)
330 {
331 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ?
332 ext_wde_min_qt_wcpu : min_cfg->wcpu;
333 u16 max_qt_wcpu = max(max_cfg->wcpu, min_qt_wcpu);
334 u32 val;
335
336 SET_QUOTA(hif, WDE, 0);
337 SET_QUOTA_VAL(min_qt_wcpu, max_qt_wcpu, WDE, 1);
338 SET_QUOTA_VAL(0, 0, WDE, 2);
339 SET_QUOTA(pkt_in, WDE, 3);
340 SET_QUOTA(cpu_io, WDE, 4);
341 }
342
ple_quota_cfg_be(struct rtw89_dev * rtwdev,const struct rtw89_ple_quota * min_cfg,const struct rtw89_ple_quota * max_cfg)343 static void ple_quota_cfg_be(struct rtw89_dev *rtwdev,
344 const struct rtw89_ple_quota *min_cfg,
345 const struct rtw89_ple_quota *max_cfg)
346 {
347 u32 val;
348
349 SET_QUOTA(cma0_tx, PLE, 0);
350 SET_QUOTA(cma1_tx, PLE, 1);
351 SET_QUOTA(c2h, PLE, 2);
352 SET_QUOTA(h2c, PLE, 3);
353 SET_QUOTA(wcpu, PLE, 4);
354 SET_QUOTA(mpdu_proc, PLE, 5);
355 SET_QUOTA(cma0_dma, PLE, 6);
356 SET_QUOTA(cma1_dma, PLE, 7);
357 SET_QUOTA(bb_rpt, PLE, 8);
358 SET_QUOTA(wd_rel, PLE, 9);
359 SET_QUOTA(cpu_io, PLE, 10);
360 SET_QUOTA(tx_rpt, PLE, 11);
361 SET_QUOTA(h2d, PLE, 12);
362
363 if (rtwdev->chip->chip_id == RTL8922A)
364 return;
365
366 SET_QUOTA(snrpt, PLE, 13);
367 }
368
rtw89_mac_hci_func_en_be(struct rtw89_dev * rtwdev)369 static void rtw89_mac_hci_func_en_be(struct rtw89_dev *rtwdev)
370 {
371 rtw89_write32_set(rtwdev, R_BE_HCI_FUNC_EN, B_BE_HCI_TXDMA_EN |
372 B_BE_HCI_RXDMA_EN);
373 }
374
rtw89_mac_dmac_func_pre_en_be(struct rtw89_dev * rtwdev)375 static void rtw89_mac_dmac_func_pre_en_be(struct rtw89_dev *rtwdev)
376 {
377 const struct rtw89_chip_info *chip = rtwdev->chip;
378 u32 mask;
379 u32 val;
380
381 val = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1);
382
383 switch (rtwdev->hci.type) {
384 case RTW89_HCI_TYPE_PCIE:
385 val = u32_replace_bits(val, S_BE_DMA_MOD_PCIE_NO_DATA_CPU,
386 B_BE_DMA_MODE_MASK);
387 break;
388 case RTW89_HCI_TYPE_USB:
389 val = u32_replace_bits(val, S_BE_DMA_MOD_USB, B_BE_DMA_MODE_MASK);
390 val = (val & ~B_BE_STOP_AXI_MST) | B_BE_TXDMA_EN | B_BE_RXDMA_EN;
391 break;
392 case RTW89_HCI_TYPE_SDIO:
393 val = u32_replace_bits(val, S_BE_DMA_MOD_SDIO, B_BE_DMA_MODE_MASK);
394 val = (val & ~B_BE_STOP_AXI_MST) | B_BE_TXDMA_EN | B_BE_RXDMA_EN;
395 break;
396 default:
397 return;
398 }
399
400 rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val);
401
402 if (chip->chip_id == RTL8922A)
403 mask = B_BE_TX_STOP1_MASK;
404 else
405 mask = B_BE_TX_STOP1_MASK_V1;
406
407 rtw89_write32_clr(rtwdev, R_BE_HAXI_DMA_STOP1, mask);
408
409 rtw89_write32_set(rtwdev, R_BE_DMAC_TABLE_CTRL, B_BE_DMAC_ADDR_MODE);
410 }
411
412 static
rtw89_mac_write_xtal_si_be(struct rtw89_dev * rtwdev,u8 offset,u8 val,u8 mask)413 int rtw89_mac_write_xtal_si_be(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
414 {
415 u32 val32;
416 int ret;
417
418 val32 = u32_encode_bits(offset, B_BE_WL_XTAL_SI_ADDR_MASK) |
419 u32_encode_bits(val, B_BE_WL_XTAL_SI_DATA_MASK) |
420 u32_encode_bits(mask, B_BE_WL_XTAL_SI_BITMASK_MASK) |
421 u32_encode_bits(XTAL_SI_NORMAL_WRITE, B_BE_WL_XTAL_SI_MODE_MASK) |
422 u32_encode_bits(0, B_BE_WL_XTAL_SI_CHIPID_MASK) |
423 B_BE_WL_XTAL_SI_CMD_POLL;
424 rtw89_write32(rtwdev, R_BE_WLAN_XTAL_SI_CTRL, val32);
425
426 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_WL_XTAL_SI_CMD_POLL),
427 50, 50000, false, rtwdev, R_BE_WLAN_XTAL_SI_CTRL);
428 if (ret) {
429 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n",
430 offset, val, mask);
431 return ret;
432 }
433
434 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags) &&
435 (u32_get_bits(val32, B_BE_WL_XTAL_SI_ADDR_MASK) != offset ||
436 u32_get_bits(val32, B_BE_WL_XTAL_SI_DATA_MASK) != val))
437 rtw89_warn(rtwdev, "xtal si write: offset=%x val=%x poll=%x\n",
438 offset, val, val32);
439
440 return 0;
441 }
442
443 static
rtw89_mac_read_xtal_si_be(struct rtw89_dev * rtwdev,u8 offset,u8 * val)444 int rtw89_mac_read_xtal_si_be(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
445 {
446 u32 val32;
447 int ret;
448
449 val32 = u32_encode_bits(offset, B_BE_WL_XTAL_SI_ADDR_MASK) |
450 u32_encode_bits(0x0, B_BE_WL_XTAL_SI_DATA_MASK) |
451 u32_encode_bits(0x0, B_BE_WL_XTAL_SI_BITMASK_MASK) |
452 u32_encode_bits(XTAL_SI_NORMAL_READ, B_BE_WL_XTAL_SI_MODE_MASK) |
453 u32_encode_bits(0, B_BE_WL_XTAL_SI_CHIPID_MASK) |
454 B_BE_WL_XTAL_SI_CMD_POLL;
455 rtw89_write32(rtwdev, R_BE_WLAN_XTAL_SI_CTRL, val32);
456
457 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_WL_XTAL_SI_CMD_POLL),
458 50, 50000, false, rtwdev, R_BE_WLAN_XTAL_SI_CTRL);
459 if (ret) {
460 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset);
461 return ret;
462 }
463
464 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags) &&
465 u32_get_bits(val32, B_BE_WL_XTAL_SI_ADDR_MASK) != offset)
466 rtw89_warn(rtwdev, "xtal si read: offset=%x poll=%x\n",
467 offset, val32);
468
469 *val = u32_get_bits(val32, B_BE_WL_XTAL_SI_DATA_MASK);
470
471 return 0;
472 }
473
rtw89_mac_reset_pwr_state_be(struct rtw89_dev * rtwdev)474 static int rtw89_mac_reset_pwr_state_be(struct rtw89_dev *rtwdev)
475 {
476 u32 val32;
477 int ret;
478
479 val32 = rtw89_read32(rtwdev, R_BE_SYSON_FSM_MON);
480 val32 &= WLAN_FSM_MASK;
481 val32 |= WLAN_FSM_SET;
482 rtw89_write32(rtwdev, R_BE_SYSON_FSM_MON, val32);
483
484 ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == WLAN_FSM_IDLE,
485 1000, 2000000, false,
486 rtwdev, R_BE_SYSON_FSM_MON, WLAN_FSM_STATE_MASK);
487 if (ret) {
488 rtw89_err(rtwdev, "[ERR]Polling WLAN PMC timeout= %X\n", val32);
489 return ret;
490 }
491
492 val32 = rtw89_read32_mask(rtwdev, R_BE_IC_PWR_STATE, B_BE_WLMAC_PWR_STE_MASK);
493 if (val32 == MAC_AX_MAC_OFF) {
494 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
495
496 ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
497 1000, 2000000, false,
498 rtwdev, R_BE_HCI_OPT_CTRL,
499 B_BE_HAXIDMA_IO_ST | B_BE_HAXIDMA_BACKUP_RESTORE_ST);
500 if (ret) {
501 rtw89_err(rtwdev, "[ERR]Polling HAXI IO timeout= %X\n", val32);
502 return ret;
503 }
504
505 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
506
507 ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
508 1000, 2000000, false,
509 rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_ST);
510 if (ret) {
511 rtw89_err(rtwdev, "[ERR]Polling WLAN IO timeout= %X\n", val32);
512 return ret;
513 }
514
515 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
516 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
517 } else if (val32 == MAC_AX_MAC_ON) {
518 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
519
520 ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
521 1000, 2000000, false,
522 rtwdev, R_BE_HCI_OPT_CTRL,
523 B_BE_HAXIDMA_IO_ST | B_BE_HAXIDMA_BACKUP_RESTORE_ST);
524 if (ret) {
525 rtw89_err(rtwdev, "[ERR]Polling HAXI IO timeout= %X\n", val32);
526 return ret;
527 }
528
529 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
530
531 ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
532 1000, 2000000, false,
533 rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_ST);
534 if (ret) {
535 rtw89_err(rtwdev, "[ERR]Polling WLAN IO timeout= %X\n", val32);
536 return ret;
537 }
538
539 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
540 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
541
542 ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == MAC_AX_MAC_OFF,
543 1000, 2000000, false,
544 rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
545 if (ret) {
546 rtw89_err(rtwdev, "[ERR]Polling MAC state timeout= %X\n", val32);
547 return ret;
548 }
549
550 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
551 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
552 } else if (val32 == MAC_AX_MAC_LPS) {
553 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
554
555 ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
556 1000, 2000000, false,
557 rtwdev, R_BE_HCI_OPT_CTRL,
558 B_BE_HAXIDMA_IO_ST | B_BE_HAXIDMA_BACKUP_RESTORE_ST);
559 if (ret) {
560 rtw89_err(rtwdev, "[ERR]Polling HAXI IO timeout= %X\n", val32);
561 return ret;
562 }
563
564 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
565
566 ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
567 1000, 2000000, false,
568 rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_ST);
569 if (ret) {
570 rtw89_err(rtwdev, "[ERR]Polling WLAN IO timeout= %X\n", val32);
571 return ret;
572 }
573
574 rtw89_write32_set(rtwdev, R_BE_WLLPS_CTRL, B_BE_FORCE_LEAVE_LPS);
575
576 ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == MAC_AX_MAC_ON,
577 1000, 2000000, false,
578 rtwdev, R_BE_IC_PWR_STATE, B_BE_WLMAC_PWR_STE_MASK);
579 if (ret) {
580 rtw89_err(rtwdev, "[ERR]Polling MAC STS timeout= %X\n", val32);
581 return ret;
582 }
583
584 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
585 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
586
587 ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == MAC_AX_MAC_OFF,
588 1000, 2000000, false,
589 rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
590 if (ret) {
591 rtw89_err(rtwdev, "[ERR]Polling MAC state timeout= %X\n", val32);
592 return ret;
593 }
594
595 rtw89_write32_clr(rtwdev, R_BE_WLLPS_CTRL, B_BE_FORCE_LEAVE_LPS);
596 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
597 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
598 }
599
600 return 0;
601 }
602
rtw89_mac_disable_cpu_be(struct rtw89_dev * rtwdev)603 static void rtw89_mac_disable_cpu_be(struct rtw89_dev *rtwdev)
604 {
605 u32 val32;
606
607 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
608
609 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
610 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_HOLD_AFTER_RESET);
611 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
612
613 val32 = rtw89_read32(rtwdev, R_BE_WCPU_FW_CTRL);
614 val32 &= B_BE_RUN_ENV_MASK;
615 rtw89_write32(rtwdev, R_BE_WCPU_FW_CTRL, val32);
616
617 if (rtwdev->chip->chip_id == RTL8922A)
618 rtw89_write32_set(rtwdev, R_BE_DCPU_PLATFORM_ENABLE, B_BE_DCPU_PLATFORM_EN);
619
620 rtw89_write32(rtwdev, R_BE_UDM0, 0);
621 rtw89_write32(rtwdev, R_BE_HALT_C2H, 0);
622 rtw89_write32(rtwdev, R_BE_UDM2, 0);
623 }
624
rtw89_mac_fwdl_preconfig_be(struct rtw89_dev * rtwdev)625 static void rtw89_mac_fwdl_preconfig_be(struct rtw89_dev *rtwdev)
626 {
627 rtw89_write32_clr(rtwdev, R_BE_FW_AUTO_CAL_DELAY, B_BE_WCPU_FW_DELAY_COUNT_VALID);
628 rtw89_write32_mask(rtwdev, R_BE_FW_AUTO_CAL_DELAY, B_BE_WCPU_FW_DELAY_COUNT_MASK, 0);
629 }
630
set_cpu_en(struct rtw89_dev * rtwdev,bool include_bb)631 static void set_cpu_en(struct rtw89_dev *rtwdev, bool include_bb)
632 {
633 u32 set = B_BE_WLANCPU_FWDL_EN;
634
635 if (include_bb)
636 set |= B_BE_BBMCU0_FWDL_EN;
637
638 rtw89_write32_set(rtwdev, R_BE_WCPU_FW_CTRL, set);
639 }
640
wcpu_on(struct rtw89_dev * rtwdev,u8 boot_reason,bool dlfw)641 static int wcpu_on(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw)
642 {
643 const struct rtw89_chip_info *chip = rtwdev->chip;
644 struct rtw89_hal *hal = &rtwdev->hal;
645 u32 val32;
646 int ret;
647
648 val32 = rtw89_read32(rtwdev, R_BE_HALT_C2H);
649 if (val32) {
650 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n");
651 rtw89_warn(rtwdev, "[SER] %s: R_BE_HALT_C2H = 0x%x\n", __func__, val32);
652 }
653 val32 = rtw89_read32(rtwdev, R_BE_UDM1);
654 if (val32) {
655 rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
656 "[SER] AON L2 Debug register not empty before Boot.\n");
657 rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
658 "[SER] %s: R_BE_UDM1 = 0x%x\n", __func__, val32);
659 }
660 val32 = rtw89_read32(rtwdev, R_BE_UDM2);
661 if (val32) {
662 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n");
663 rtw89_warn(rtwdev, "[SER] %s: R_BE_UDM2 = 0x%x\n", __func__, val32);
664 }
665
666 rtw89_write32(rtwdev, R_BE_UDM1, 0);
667 rtw89_write32(rtwdev, R_BE_UDM2, 0);
668 rtw89_write32(rtwdev, R_BE_BOOT_DBG, 0x0);
669 rtw89_write32(rtwdev, R_BE_HALT_H2C, 0);
670 rtw89_write32(rtwdev, R_BE_HALT_C2H, 0);
671 rtw89_write32(rtwdev, R_BE_HALT_H2C_CTRL, 0);
672 rtw89_write32(rtwdev, R_BE_HALT_C2H_CTRL, 0);
673
674 val32 = rtw89_read32(rtwdev, R_BE_HISR0);
675 rtw89_write32(rtwdev, R_BE_HISR0, B_BE_HALT_C2H_INT);
676 rtw89_debug(rtwdev, RTW89_DBG_SER, "HISR0=0x%x\n", val32);
677
678 rtw89_write32_set(rtwdev, R_BE_SYS_CLK_CTRL, B_BE_CPU_CLK_EN);
679 rtw89_write32_clr(rtwdev, R_BE_SYS_CFG5,
680 B_BE_WDT_WAKE_PCIE_EN | B_BE_WDT_WAKE_USB_EN);
681 rtw89_write32_clr(rtwdev, R_BE_WCPU_FW_CTRL,
682 B_BE_WDT_PLT_RST_EN | B_BE_WCPU_ROM_CUT_GET);
683 rtw89_write32(rtwdev, R_BE_SECURE_BOOT_MALLOC_INFO, 0);
684 rtw89_write32_clr(rtwdev, R_BE_GPIO_MUXCFG, B_BE_BOOT_MODE);
685
686 if (chip->chip_id != RTL8922A)
687 rtw89_write32_set(rtwdev, R_BE_WCPU_FW_CTRL, B_BE_HOST_EXIST);
688
689 rtw89_write32_mask(rtwdev, R_BE_WCPU_FW_CTRL,
690 B_BE_WCPU_ROM_CUT_VAL_MASK, hal->cv + 1);
691 rtw89_write16_mask(rtwdev, R_BE_BOOT_REASON, B_BE_BOOT_REASON_MASK, boot_reason);
692 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
693 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_HOLD_AFTER_RESET);
694 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
695
696 if (!dlfw) {
697 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE);
698 if (ret)
699 return ret;
700 }
701
702 return 0;
703 }
704
rtw89_mac_fwdl_enable_wcpu_be(struct rtw89_dev * rtwdev,u8 boot_reason,bool dlfw,bool include_bb)705 static int rtw89_mac_fwdl_enable_wcpu_be(struct rtw89_dev *rtwdev,
706 u8 boot_reason, bool dlfw,
707 bool include_bb)
708 {
709 set_cpu_en(rtwdev, include_bb);
710
711 return wcpu_on(rtwdev, boot_reason, dlfw);
712 }
713
714 static const u8 fwdl_status_map[] = {
715 [0] = RTW89_FWDL_INITIAL_STATE,
716 [1] = RTW89_FWDL_FWDL_ONGOING,
717 [4] = RTW89_FWDL_CHECKSUM_FAIL,
718 [5] = RTW89_FWDL_SECURITY_FAIL,
719 [6] = RTW89_FWDL_SECURITY_FAIL,
720 [7] = RTW89_FWDL_CV_NOT_MATCH,
721 [8] = RTW89_FWDL_RSVD0,
722 [2] = RTW89_FWDL_WCPU_FWDL_RDY,
723 [3] = RTW89_FWDL_WCPU_FW_INIT_RDY,
724 [9] = RTW89_FWDL_RSVD0,
725 };
726
fwdl_get_status_be(struct rtw89_dev * rtwdev,enum rtw89_fwdl_check_type type)727 static u8 fwdl_get_status_be(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type)
728 {
729 bool check_pass = false;
730 u32 val32;
731 u8 st;
732
733 val32 = rtw89_read32(rtwdev, R_BE_WCPU_FW_CTRL);
734
735 switch (type) {
736 case RTW89_FWDL_CHECK_WCPU_FWDL_DONE:
737 check_pass = !(val32 & B_BE_WLANCPU_FWDL_EN);
738 break;
739 case RTW89_FWDL_CHECK_DCPU_FWDL_DONE:
740 check_pass = !(val32 & B_BE_DATACPU_FWDL_EN);
741 break;
742 case RTW89_FWDL_CHECK_BB0_FWDL_DONE:
743 check_pass = !(val32 & B_BE_BBMCU0_FWDL_EN);
744 break;
745 case RTW89_FWDL_CHECK_BB1_FWDL_DONE:
746 check_pass = !(val32 & B_BE_BBMCU1_FWDL_EN);
747 break;
748 default:
749 break;
750 }
751
752 if (check_pass)
753 return RTW89_FWDL_WCPU_FW_INIT_RDY;
754
755 st = u32_get_bits(val32, B_BE_WCPU_FWDL_STATUS_MASK);
756 if (st < ARRAY_SIZE(fwdl_status_map))
757 return fwdl_status_map[st];
758
759 return st;
760 }
761
rtw89_fwdl_check_path_ready_be(struct rtw89_dev * rtwdev,bool h2c_or_fwdl)762 static int rtw89_fwdl_check_path_ready_be(struct rtw89_dev *rtwdev,
763 bool h2c_or_fwdl)
764 {
765 u32 check = h2c_or_fwdl ? B_BE_H2C_PATH_RDY : B_BE_DLFW_PATH_RDY;
766 u32 val;
767
768 return read_poll_timeout_atomic(rtw89_read32, val, val & check,
769 1, 1000000, false,
770 rtwdev, R_BE_WCPU_FW_CTRL);
771 }
772
dmac_func_en_be(struct rtw89_dev * rtwdev)773 static int dmac_func_en_be(struct rtw89_dev *rtwdev)
774 {
775 const struct rtw89_chip_info *chip = rtwdev->chip;
776
777 if (chip->chip_id == RTL8922A)
778 return 0;
779
780 rtw89_write32_set(rtwdev, R_BE_DMAC_FUNC_EN,
781 B_BE_MAC_FUNC_EN | B_BE_DMAC_FUNC_EN |
782 B_BE_MPDU_PROC_EN | B_BE_WD_RLS_EN |
783 B_BE_DLE_WDE_EN | B_BE_TXPKT_CTRL_EN |
784 B_BE_STA_SCH_EN | B_BE_DLE_PLE_EN |
785 B_BE_PKT_BUF_EN | B_BE_DMAC_TBL_EN |
786 B_BE_PKT_IN_EN | B_BE_DLE_CPUIO_EN |
787 B_BE_DISPATCHER_EN | B_BE_BBRPT_EN |
788 B_BE_MAC_SEC_EN | B_BE_H_AXIDMA_EN |
789 B_BE_DMAC_MLO_EN | B_BE_PLRLS_EN |
790 B_BE_P_AXIDMA_EN | B_BE_DLE_DATACPUIO_EN);
791
792 return 0;
793 }
794
cmac_share_func_en_be(struct rtw89_dev * rtwdev)795 static int cmac_share_func_en_be(struct rtw89_dev *rtwdev)
796 {
797 const struct rtw89_chip_info *chip = rtwdev->chip;
798
799 if (chip->chip_id == RTL8922A)
800 return 0;
801
802 rtw89_write32_set(rtwdev, R_BE_CMAC_SHARE_FUNC_EN,
803 B_BE_CMAC_SHARE_EN | B_BE_RESPBA_EN |
804 B_BE_ADDRSRCH_EN | B_BE_BTCOEX_EN);
805
806 return 0;
807 }
808
cmac_pwr_en_be(struct rtw89_dev * rtwdev,u8 mac_idx,bool en)809 static int cmac_pwr_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
810 {
811 if (mac_idx > RTW89_MAC_1)
812 return -EINVAL;
813
814 if (mac_idx == RTW89_MAC_0) {
815 if (en == test_bit(RTW89_FLAG_CMAC0_PWR, rtwdev->flags))
816 return 0;
817
818 if (en) {
819 rtw89_write32_set(rtwdev, R_BE_AFE_CTRL1,
820 B_BE_R_SYM_WLCMAC0_ALL_EN);
821 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
822 B_BE_R_SYM_ISO_CMAC02PP);
823 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
824 B_BE_CMAC0_FEN);
825
826 set_bit(RTW89_FLAG_CMAC0_PWR, rtwdev->flags);
827 } else {
828 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
829 B_BE_CMAC0_FEN);
830 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
831 B_BE_R_SYM_ISO_CMAC02PP);
832 rtw89_write32_clr(rtwdev, R_BE_AFE_CTRL1,
833 B_BE_R_SYM_WLCMAC0_ALL_EN);
834
835 clear_bit(RTW89_FLAG_CMAC0_PWR, rtwdev->flags);
836 }
837 } else {
838 if (en == test_bit(RTW89_FLAG_CMAC1_PWR, rtwdev->flags))
839 return 0;
840
841 if (en) {
842 rtw89_write32_set(rtwdev, R_BE_AFE_CTRL1,
843 B_BE_R_SYM_WLCMAC1_ALL_EN);
844 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
845 B_BE_R_SYM_ISO_CMAC12PP);
846 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
847 B_BE_CMAC1_FEN);
848
849 set_bit(RTW89_FLAG_CMAC1_PWR, rtwdev->flags);
850 } else {
851 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
852 B_BE_CMAC1_FEN);
853 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
854 B_BE_R_SYM_ISO_CMAC12PP);
855 rtw89_write32_clr(rtwdev, R_BE_AFE_CTRL1,
856 B_BE_R_SYM_WLCMAC1_ALL_EN);
857
858 clear_bit(RTW89_FLAG_CMAC1_PWR, rtwdev->flags);
859 }
860 }
861
862 return 0;
863 }
864
cmac_func_en_be(struct rtw89_dev * rtwdev,u8 mac_idx,bool en)865 static int cmac_func_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
866 {
867 enum rtw89_flags pwr_flag, func_flag;
868 u32 reg;
869
870 if (mac_idx > RTW89_MAC_1)
871 return -EINVAL;
872
873 if (mac_idx == RTW89_MAC_0) {
874 pwr_flag = RTW89_FLAG_CMAC0_PWR;
875 func_flag = RTW89_FLAG_CMAC0_FUNC;
876 } else {
877 pwr_flag = RTW89_FLAG_CMAC1_PWR;
878 func_flag = RTW89_FLAG_CMAC1_FUNC;
879 }
880
881 if (!test_bit(pwr_flag, rtwdev->flags)) {
882 rtw89_warn(rtwdev, "CMAC %u power cut did not release\n", mac_idx);
883 return 0;
884 }
885
886 if (en) {
887 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx);
888 rtw89_write32_set(rtwdev, reg, B_BE_CK_EN_SET);
889
890 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx);
891 rtw89_write32_set(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET);
892
893 set_bit(func_flag, rtwdev->flags);
894 } else {
895 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx);
896 rtw89_write32_clr(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET);
897
898 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx);
899 rtw89_write32_clr(rtwdev, reg, B_BE_CK_EN_SET);
900
901 clear_bit(func_flag, rtwdev->flags);
902 }
903
904 return 0;
905 }
906
chip_func_en_be(struct rtw89_dev * rtwdev)907 static int chip_func_en_be(struct rtw89_dev *rtwdev)
908 {
909 return 0;
910 }
911
sys_init_be(struct rtw89_dev * rtwdev)912 static int sys_init_be(struct rtw89_dev *rtwdev)
913 {
914 int ret;
915
916 ret = dmac_func_en_be(rtwdev);
917 if (ret)
918 return ret;
919
920 ret = cmac_share_func_en_be(rtwdev);
921 if (ret)
922 return ret;
923
924 ret = cmac_pwr_en_be(rtwdev, RTW89_MAC_0, true);
925 if (ret)
926 return ret;
927
928 ret = cmac_func_en_be(rtwdev, RTW89_MAC_0, true);
929 if (ret)
930 return ret;
931
932 return chip_func_en_be(rtwdev);
933 }
934
mac_func_en_be(struct rtw89_dev * rtwdev)935 static int mac_func_en_be(struct rtw89_dev *rtwdev)
936 {
937 u32 val;
938 int ret;
939
940 ret = dmac_func_en_be(rtwdev);
941 if (ret)
942 return ret;
943
944 ret = cmac_share_func_en_be(rtwdev);
945 if (ret)
946 return ret;
947
948 val = rtw89_read32(rtwdev, R_BE_FEN_RST_ENABLE);
949 if (val & B_BE_CMAC0_FEN) {
950 ret = cmac_pwr_en_be(rtwdev, RTW89_MAC_0, true);
951 if (ret)
952 return ret;
953
954 ret = cmac_func_en_be(rtwdev, RTW89_MAC_0, true);
955 if (ret)
956 return ret;
957 }
958
959 if (val & B_BE_CMAC1_FEN) {
960 ret = cmac_pwr_en_be(rtwdev, RTW89_MAC_1, true);
961 if (ret)
962 return ret;
963
964 ret = cmac_func_en_be(rtwdev, RTW89_MAC_1, true);
965 if (ret)
966 return ret;
967 }
968
969 return 0;
970 }
971
sta_sch_init_be(struct rtw89_dev * rtwdev)972 static int sta_sch_init_be(struct rtw89_dev *rtwdev)
973 {
974 u32 p_val;
975 int ret;
976
977 if (rtwdev->chip->chip_id == RTL8922D) {
978 rtw89_write32_set(rtwdev, R_BE_SS_LITE_TXL_MACID, B_BE_RPT_OTHER_BAND_EN);
979 return 0;
980 }
981
982 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
983 if (ret)
984 return ret;
985
986 rtw89_write8_set(rtwdev, R_BE_SS_CTRL, B_BE_SS_EN);
987
988 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_BE_SS_INIT_DONE,
989 1, TRXCFG_WAIT_CNT, false, rtwdev, R_BE_SS_CTRL);
990 if (ret) {
991 rtw89_err(rtwdev, "[ERR]STA scheduler init\n");
992 return ret;
993 }
994
995 rtw89_write32_set(rtwdev, R_BE_SS_CTRL, B_BE_WARM_INIT);
996 rtw89_write32_clr(rtwdev, R_BE_SS_CTRL, B_BE_BAND_TRIG_EN | B_BE_BAND1_TRIG_EN);
997
998 return 0;
999 }
1000
mpdu_proc_init_be(struct rtw89_dev * rtwdev)1001 static int mpdu_proc_init_be(struct rtw89_dev *rtwdev)
1002 {
1003 u32 val32;
1004 int ret;
1005
1006 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1007 if (ret)
1008 return ret;
1009
1010 rtw89_io_pack(rtwdev);
1011
1012 rtw89_write32_set(rtwdev, R_BE_MPDU_PROC, B_BE_APPEND_FCS);
1013 rtw89_write32(rtwdev, R_BE_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL |
1014 B_BE_CA_CHK_ADDRCAM_EN);
1015
1016 val32 = rtw89_read32(rtwdev, R_BE_HDR_SHCUT_SETTING);
1017 val32 |= (B_BE_TX_HW_SEQ_EN | B_BE_TX_HW_ACK_POLICY_EN | B_BE_TX_MAC_MPDU_PROC_EN);
1018 val32 &= ~B_BE_TX_ADDR_MLD_TO_LIK;
1019 rtw89_write32_set(rtwdev, R_BE_HDR_SHCUT_SETTING, val32);
1020
1021 rtw89_write32(rtwdev, R_BE_RX_HDRTRNS, TRXCFG_MPDU_PROC_RX_HDR_CONV |
1022 B_BE_HC_ADDR_HIT_EN);
1023
1024 val32 = rtw89_read32(rtwdev, R_BE_DISP_FWD_WLAN_0);
1025 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_DATA_MASK);
1026 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_MNG_MASK);
1027 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_CTL_MASK);
1028 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_1_MASK);
1029 rtw89_write32(rtwdev, R_BE_DISP_FWD_WLAN_0, val32);
1030
1031 rtw89_io_unpack(rtwdev);
1032
1033 return 0;
1034 }
1035
sec_eng_init_be(struct rtw89_dev * rtwdev)1036 static int sec_eng_init_be(struct rtw89_dev *rtwdev)
1037 {
1038 u32 val32;
1039 int ret;
1040
1041 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1042 if (ret)
1043 return ret;
1044
1045 rtw89_io_pack(rtwdev);
1046
1047 val32 = rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL);
1048 val32 |= B_BE_CLK_EN_CGCMP | B_BE_CLK_EN_WAPI | B_BE_CLK_EN_WEP_TKIP |
1049 B_BE_SEC_TX_ENC | B_BE_SEC_RX_DEC |
1050 B_BE_MC_DEC | B_BE_BC_DEC |
1051 B_BE_BMC_MGNT_DEC | B_BE_UC_MGNT_DEC |
1052 B_BE_SEC_PRE_ENQUE_TX;
1053 rtw89_write32(rtwdev, R_BE_SEC_ENG_CTRL, val32);
1054
1055 rtw89_write32_set(rtwdev, R_BE_SEC_MPDU_PROC, B_BE_APPEND_ICV | B_BE_APPEND_MIC);
1056
1057 rtw89_io_unpack(rtwdev);
1058
1059 return 0;
1060 }
1061
txpktctrl_init_be(struct rtw89_dev * rtwdev)1062 static int txpktctrl_init_be(struct rtw89_dev *rtwdev)
1063 {
1064 struct rtw89_mac_info *mac = &rtwdev->mac;
1065 struct rtw89_mac_dle_rsvd_qt_cfg qt_cfg;
1066 const struct rtw89_dle_input *dle_input;
1067 u32 mpdu_info_b1_ofst;
1068 u32 val32;
1069 int ret;
1070
1071 ret = rtw89_mac_get_dle_rsvd_qt_cfg(rtwdev, DLE_RSVD_QT_MPDU_INFO, &qt_cfg);
1072 if (ret) {
1073 rtw89_err(rtwdev, "get dle rsvd qt %d cfg fail %d\n",
1074 DLE_RSVD_QT_MPDU_INFO, ret);
1075 return ret;
1076 }
1077
1078 dle_input = mac->dle_info.dle_input;
1079 if (dle_input)
1080 mpdu_info_b1_ofst = DIV_ROUND_UP(dle_input->mpdu_info_tbl_b0,
1081 BIT(MPDU_INFO_TBL_FACTOR));
1082 else
1083 mpdu_info_b1_ofst = MPDU_INFO_B1_OFST;
1084
1085 val32 = rtw89_read32(rtwdev, R_BE_TXPKTCTL_MPDUINFO_CFG);
1086 val32 = u32_replace_bits(val32, qt_cfg.pktid, B_BE_MPDUINFO_PKTID_MASK);
1087 val32 = u32_replace_bits(val32, mpdu_info_b1_ofst, B_BE_MPDUINFO_B1_BADDR_MASK);
1088 val32 |= B_BE_MPDUINFO_FEN;
1089 rtw89_write32(rtwdev, R_BE_TXPKTCTL_MPDUINFO_CFG, val32);
1090
1091 return 0;
1092 }
1093
mlo_init_be(struct rtw89_dev * rtwdev)1094 static int mlo_init_be(struct rtw89_dev *rtwdev)
1095 {
1096 const struct rtw89_chip_info *chip = rtwdev->chip;
1097 u32 val32;
1098 u32 reg;
1099 int ret;
1100
1101 rtw89_io_pack(rtwdev);
1102
1103 val32 = rtw89_read32(rtwdev, R_BE_MLO_INIT_CTL);
1104 val32 |= B_BE_MLO_TABLE_REINIT;
1105 rtw89_write32(rtwdev, R_BE_MLO_INIT_CTL, val32);
1106 val32 &= ~B_BE_MLO_TABLE_REINIT;
1107 rtw89_write32(rtwdev, R_BE_MLO_INIT_CTL, val32);
1108
1109 rtw89_io_unpack(rtwdev);
1110
1111 ret = read_poll_timeout_atomic(rtw89_read32, val32,
1112 val32 & B_BE_MLO_TABLE_INIT_DONE,
1113 1, 1000, false, rtwdev, R_BE_MLO_INIT_CTL);
1114 if (ret)
1115 rtw89_err(rtwdev, "[MLO]%s: MLO init polling timeout\n", __func__);
1116
1117 if (chip->chip_id == RTL8922A)
1118 reg = R_BE_SS_CTRL;
1119 else
1120 reg = R_BE_SS_CTRL_V1;
1121
1122 rtw89_io_pack(rtwdev);
1123
1124 rtw89_write32_set(rtwdev, reg, B_BE_MLO_HW_CHGLINK_EN);
1125 rtw89_write32_set(rtwdev, R_BE_CMAC_SHARE_ACQCHK_CFG_0, B_BE_R_MACID_ACQ_CHK_EN);
1126
1127 rtw89_io_unpack(rtwdev);
1128
1129 return ret;
1130 }
1131
dmac_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1132 static int dmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1133 {
1134 int ret;
1135
1136 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID);
1137 if (ret) {
1138 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret);
1139 return ret;
1140 }
1141
1142 ret = rtw89_mac_preload_init(rtwdev, mac_idx, rtwdev->mac.qta_mode);
1143 if (ret) {
1144 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret);
1145 return ret;
1146 }
1147
1148 ret = rtw89_mac_hfc_init(rtwdev, true, true, true);
1149 if (ret) {
1150 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret);
1151 return ret;
1152 }
1153
1154 ret = sta_sch_init_be(rtwdev);
1155 if (ret) {
1156 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret);
1157 return ret;
1158 }
1159
1160 ret = mpdu_proc_init_be(rtwdev);
1161 if (ret) {
1162 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret);
1163 return ret;
1164 }
1165
1166 ret = sec_eng_init_be(rtwdev);
1167 if (ret) {
1168 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret);
1169 return ret;
1170 }
1171
1172 ret = txpktctrl_init_be(rtwdev);
1173 if (ret) {
1174 rtw89_err(rtwdev, "[ERR]TX pkt ctrl init %d\n", ret);
1175 return ret;
1176 }
1177
1178 ret = mlo_init_be(rtwdev);
1179 if (ret) {
1180 rtw89_err(rtwdev, "[ERR]MLO init %d\n", ret);
1181 return ret;
1182 }
1183
1184 return ret;
1185 }
1186
scheduler_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1187 static int scheduler_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1188 {
1189 const struct rtw89_chip_info *chip = rtwdev->chip;
1190 u32 val32;
1191 u32 reg;
1192 int ret;
1193
1194 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1195 if (ret)
1196 return ret;
1197
1198 rtw89_io_pack(rtwdev);
1199
1200 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MISC_1, mac_idx);
1201 rtw89_write32_set(rtwdev, reg, B_BE_EN_TX_FINISH_PRD_RESP);
1202
1203 if (chip->chip_id == RTL8922D) {
1204 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SCH_EXT_CTRL, mac_idx);
1205 rtw89_write32_set(rtwdev, reg, B_BE_CWCNT_PLUS_MODE);
1206 }
1207
1208 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_HE_CTN_CHK_CCA_NAV, mac_idx);
1209 val32 = B_BE_HE_CTN_CHK_CCA_P20 | B_BE_HE_CTN_CHK_EDCCA_P20 |
1210 B_BE_HE_CTN_CHK_CCA_BITMAP | B_BE_HE_CTN_CHK_EDCCA_BITMAP |
1211 B_BE_HE_CTN_CHK_NO_GNT_WL | B_BE_HE_CTN_CHK_BASIC_NAV |
1212 B_BE_HE_CTN_CHK_INTRA_NAV | B_BE_HE_CTN_CHK_TX_NAV;
1213 rtw89_write32(rtwdev, reg, val32);
1214
1215 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_HE_SIFS_CHK_CCA_NAV, mac_idx);
1216 val32 = B_BE_HE_SIFS_CHK_EDCCA_P20 | B_BE_HE_SIFS_CHK_EDCCA_BITMAP |
1217 B_BE_HE_SIFS_CHK_NO_GNT_WL;
1218 rtw89_write32(rtwdev, reg, val32);
1219
1220 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_CHK_CCA_NAV, mac_idx);
1221 val32 = B_BE_TB_CHK_EDCCA_BITMAP | B_BE_TB_CHK_NO_GNT_WL | B_BE_TB_CHK_BASIC_NAV;
1222 rtw89_write32(rtwdev, reg, val32);
1223
1224 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CCA_CFG_0, mac_idx);
1225 rtw89_write32_clr(rtwdev, reg, B_BE_NO_GNT_WL_EN);
1226
1227 if (is_qta_poh(rtwdev)) {
1228 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PREBKF_CFG_0, mac_idx);
1229 rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_MASK,
1230 SCH_PREBKF_24US);
1231
1232 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_CFG_0, mac_idx);
1233 rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_NONAC_MASK,
1234 SCH_PREBKF_24US);
1235 }
1236
1237 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_EDCA_BCNQ_PARAM, mac_idx);
1238 rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_CW_MASK, 0x32);
1239 rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_AIFS_MASK, BCN_IFS_25US);
1240
1241 if (chip->chip_id == RTL8922D) {
1242 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SCH_EDCA_RST_CFG, mac_idx);
1243 rtw89_write32_set(rtwdev, reg, B_BE_TX_NAV_RST_EDCA_EN);
1244 }
1245
1246 rtw89_io_unpack(rtwdev);
1247
1248 return 0;
1249 }
1250
addr_cam_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1251 static int addr_cam_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1252 {
1253 u32 val32;
1254 u16 val16;
1255 u32 reg;
1256 int ret;
1257
1258 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1259 if (ret)
1260 return ret;
1261
1262 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_ADDR_CAM_CTRL, mac_idx);
1263 val32 = rtw89_read32(rtwdev, reg);
1264 val32 = u32_replace_bits(val32, ADDR_CAM_SERCH_RANGE, B_BE_ADDR_CAM_RANGE_MASK);
1265 val32 |= B_BE_ADDR_CAM_EN;
1266 if (mac_idx == RTW89_MAC_0)
1267 val32 |= B_BE_ADDR_CAM_CLR;
1268 rtw89_write32(rtwdev, reg, val32);
1269
1270 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_ADDR_CAM_CTRL, mac_idx);
1271 ret = read_poll_timeout_atomic(rtw89_read16, val16, !(val16 & B_BE_ADDR_CAM_CLR),
1272 1, TRXCFG_WAIT_CNT, false, rtwdev, reg);
1273 if (ret)
1274 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n");
1275
1276 return ret;
1277 }
1278
rtw89_mac_typ_fltr_opt_be(struct rtw89_dev * rtwdev,enum rtw89_machdr_frame_type type,enum rtw89_mac_fwd_target fwd_target,u8 mac_idx)1279 static int rtw89_mac_typ_fltr_opt_be(struct rtw89_dev *rtwdev,
1280 enum rtw89_machdr_frame_type type,
1281 enum rtw89_mac_fwd_target fwd_target,
1282 u8 mac_idx)
1283 {
1284 u32 reg;
1285 u32 val;
1286
1287 switch (fwd_target) {
1288 case RTW89_FWD_DONT_CARE:
1289 val = RX_FLTR_FRAME_DROP_BE;
1290 break;
1291 case RTW89_FWD_TO_HOST:
1292 case RTW89_FWD_TO_WLAN_CPU:
1293 val = RX_FLTR_FRAME_ACCEPT_BE;
1294 break;
1295 default:
1296 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n");
1297 return -EINVAL;
1298 }
1299
1300 switch (type) {
1301 case RTW89_MGNT:
1302 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MGNT_FLTR, mac_idx);
1303 break;
1304 case RTW89_CTRL:
1305 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTRL_FLTR, mac_idx);
1306 break;
1307 case RTW89_DATA:
1308 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DATA_FLTR, mac_idx);
1309 break;
1310 default:
1311 rtw89_err(rtwdev, "[ERR]set rx filter type err\n");
1312 return -EINVAL;
1313 }
1314 rtw89_write32(rtwdev, reg, val);
1315
1316 return 0;
1317 }
1318
rx_fltr_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1319 static int rx_fltr_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1320 {
1321 u32 reg;
1322 u32 val;
1323
1324 rtw89_io_pack(rtwdev);
1325
1326 rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_MGNT, RTW89_FWD_TO_HOST, mac_idx);
1327 rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_CTRL, RTW89_FWD_TO_HOST, mac_idx);
1328 rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_DATA, RTW89_FWD_TO_HOST, mac_idx);
1329
1330 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_FLTR_OPT, mac_idx);
1331 rtw89_write32(rtwdev, reg, rtwdev->hal.rx_fltr);
1332
1333 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx);
1334 val = B_BE_HE_SIGB_CRC_CHK | B_BE_VHT_MU_SIGB_CRC_CHK |
1335 B_BE_VHT_SU_SIGB_CRC_CHK | B_BE_SIGA_CRC_CHK |
1336 B_BE_LSIG_PARITY_CHK_EN | B_BE_CCK_SIG_CHK | B_BE_CCK_CRC_CHK;
1337 rtw89_write16(rtwdev, reg, val);
1338
1339 rtw89_io_unpack(rtwdev);
1340
1341 return 0;
1342 }
1343
cca_ctrl_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1344 static int cca_ctrl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1345 {
1346 return 0;
1347 }
1348
nav_ctrl_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1349 static int nav_ctrl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1350 {
1351 u32 val32;
1352 u32 reg;
1353
1354 rtw89_io_pack(rtwdev);
1355
1356 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_NAV_CTL, mac_idx);
1357
1358 val32 = rtw89_read32(rtwdev, reg);
1359 val32 &= ~B_BE_WMAC_PLCP_UP_NAV_EN;
1360 val32 |= B_BE_WMAC_TF_UP_NAV_EN | B_BE_WMAC_NAV_UPPER_EN;
1361 val32 = u32_replace_bits(val32, NAV_25MS, B_BE_WMAC_NAV_UPPER_MASK);
1362
1363 rtw89_write32(rtwdev, reg, val32);
1364
1365 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SPECIAL_TX_SETTING, mac_idx);
1366 rtw89_write32_clr(rtwdev, reg, B_BE_BMC_NAV_PROTECT);
1367
1368 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_0, mac_idx);
1369 rtw89_write32_set(rtwdev, reg, B_BE_WMAC_MBA_DUR_FORCE);
1370
1371 rtw89_io_unpack(rtwdev);
1372
1373 return 0;
1374 }
1375
spatial_reuse_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1376 static int spatial_reuse_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1377 {
1378 u32 reg;
1379 int ret;
1380
1381 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1382 if (ret)
1383 return ret;
1384
1385 rtw89_io_pack(rtwdev);
1386
1387 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_SR_CTRL, mac_idx);
1388 rtw89_write8_clr(rtwdev, reg, B_BE_SR_EN | B_BE_SR_CTRL_PLCP_EN);
1389
1390 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BSSID_SRC_CTRL, mac_idx);
1391 rtw89_write8_set(rtwdev, reg, B_BE_PLCP_SRC_EN);
1392
1393 rtw89_io_unpack(rtwdev);
1394
1395 return 0;
1396 }
1397
tmac_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1398 static int tmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1399 {
1400 const struct rtw89_chip_info *chip = rtwdev->chip;
1401 struct rtw89_hal *hal = &rtwdev->hal;
1402 u32 reg;
1403
1404 rtw89_io_pack(rtwdev);
1405
1406 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_PPDU_CTRL, mac_idx);
1407 rtw89_write32_clr(rtwdev, reg, B_BE_QOSNULL_UPD_MUEDCA_EN);
1408
1409 if (chip->chip_id == RTL8922A) {
1410 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMTX_TCR_BE_4, mac_idx);
1411 rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK, 0x12);
1412 rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK, 0xe);
1413 }
1414
1415 if (chip->chip_id == RTL8922D && hal->cid != RTL8922D_CID7090) {
1416 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_COMMON_PHYINTF_CTRL_0, mac_idx);
1417 rtw89_write32_clr(rtwdev, reg, CLEAR_DTOP_DIS);
1418 }
1419
1420 rtw89_io_unpack(rtwdev);
1421
1422 return 0;
1423 }
1424
trxptcl_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1425 static int trxptcl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1426 {
1427 const struct rtw89_chip_info *chip = rtwdev->chip;
1428 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs;
1429 struct rtw89_hal *hal = &rtwdev->hal;
1430 u32 val32;
1431 u32 reg;
1432 int ret;
1433
1434 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1435 if (ret)
1436 return ret;
1437
1438 rtw89_io_pack(rtwdev);
1439
1440 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MAC_LOOPBACK, mac_idx);
1441 val32 = rtw89_read32(rtwdev, reg);
1442 val32 = u32_replace_bits(val32, S_BE_MACLBK_PLCP_DLY_DEF,
1443 B_BE_MACLBK_PLCP_DLY_MASK);
1444 val32 &= ~B_BE_MACLBK_EN;
1445 rtw89_write32(rtwdev, reg, val32);
1446
1447 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx);
1448 rtw89_write32_set(rtwdev, reg, B_BE_PHYINTF_EN);
1449
1450 if (chip->chip_id == RTL8922D) {
1451 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_PLCP_EXT_OPTION_2, mac_idx);
1452 rtw89_write32_set(rtwdev, reg, B_BE_PLCP_PHASE_B_CRC_CHK_EN |
1453 B_BE_PLCP_PHASE_A_CRC_CHK_EN);
1454 }
1455
1456 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_0, mac_idx);
1457 val32 = rtw89_read32(rtwdev, reg);
1458 val32 = u32_replace_bits(val32, WMAC_SPEC_SIFS_CCK,
1459 B_BE_WMAC_SPEC_SIFS_CCK_MASK);
1460 val32 = u32_replace_bits(val32, WMAC_SPEC_SIFS_OFDM_1115E,
1461 B_BE_WMAC_SPEC_SIFS_OFDM_MASK);
1462 rtw89_write32(rtwdev, reg, val32);
1463
1464 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_LEGACY, mac_idx);
1465 rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA);
1466
1467 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_HE, mac_idx);
1468 rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_RESP_HE_CHK_EDCCA);
1469
1470 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC, mac_idx);
1471 rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA);
1472
1473 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RXTRIG_TEST_USER_2, mac_idx);
1474 rtw89_write32_set(rtwdev, reg, B_BE_RXTRIG_FCSCHK_EN);
1475
1476 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_1, mac_idx);
1477 val32 = rtw89_read32(rtwdev, reg);
1478 val32 &= B_BE_FTM_RRSR_RATE_EN_MASK | B_BE_WMAC_RESP_DOPPLEB_BE_EN |
1479 B_BE_WMAC_RESP_DCM_EN | B_BE_WMAC_RESP_REF_RATE_MASK;
1480 rtw89_write32(rtwdev, reg, val32);
1481 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);
1482
1483 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR1, mac_idx);
1484 val32 = rtw89_read32(rtwdev, reg);
1485 val32 &= B_BE_RRSR_RATE_EN_MASK | B_BE_RRSR_CCK_MASK | B_BE_RSC_MASK;
1486 rtw89_write32(rtwdev, reg, val32);
1487
1488 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR0, mac_idx);
1489 val32 = rtw89_read32(rtwdev, reg);
1490 val32 &= B_BE_RRSR_OFDM_MASK | B_BE_RRSR_HT_MASK | B_BE_RRSR_VHT_MASK |
1491 B_BE_RRSR_HE_MASK;
1492 rtw89_write32(rtwdev, reg, val32);
1493
1494 if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV) {
1495 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR1, mac_idx);
1496 rtw89_write32_mask(rtwdev, reg, B_BE_RSC_MASK, 1);
1497 }
1498
1499 rtw89_io_unpack(rtwdev);
1500
1501 return 0;
1502 }
1503
rst_bacam_be(struct rtw89_dev * rtwdev)1504 static int rst_bacam_be(struct rtw89_dev *rtwdev)
1505 {
1506 u32 val;
1507 int ret;
1508
1509 rtw89_write32_mask(rtwdev, R_BE_RESPBA_CAM_CTRL, B_BE_BACAM_RST_MASK,
1510 S_BE_BACAM_RST_ALL);
1511
1512 ret = read_poll_timeout_atomic(rtw89_read32_mask, val, val == S_BE_BACAM_RST_DONE,
1513 1, 1000, false,
1514 rtwdev, R_BE_RESPBA_CAM_CTRL, B_BE_BACAM_RST_MASK);
1515 if (ret)
1516 rtw89_err(rtwdev, "[ERR]bacam rst timeout\n");
1517
1518 return ret;
1519 }
1520
1521 #define PLD_RLS_MAX_PG 127
1522 #define RX_MAX_LEN_UNIT 512
1523 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT)
1524
rmac_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1525 static int rmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1526 {
1527 const struct rtw89_chip_info *chip = rtwdev->chip;
1528 u32 rx_min_qta, rx_max_len, rx_max_pg;
1529 u16 val16;
1530 u32 reg;
1531 int ret;
1532
1533 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1534 if (ret)
1535 return ret;
1536
1537 if (mac_idx == RTW89_MAC_0) {
1538 ret = rst_bacam_be(rtwdev);
1539 if (ret)
1540 return ret;
1541 }
1542
1543 rtw89_io_pack(rtwdev);
1544
1545 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DLK_PROTECT_CTL, mac_idx);
1546 val16 = rtw89_read16(rtwdev, reg);
1547 val16 = u16_replace_bits(val16, TRXCFG_RMAC_DATA_TO, B_BE_RX_DLK_DATA_TIME_MASK);
1548 val16 = u16_replace_bits(val16, TRXCFG_RMAC_CCA_TO, B_BE_RX_DLK_CCA_TIME_MASK);
1549 val16 |= B_BE_RX_DLK_RST_EN;
1550 rtw89_write16(rtwdev, reg, val16);
1551
1552 if (mac_idx == RTW89_MAC_0)
1553 rx_min_qta = rtwdev->mac.dle_info.c0_rx_qta;
1554 else
1555 rx_min_qta = rtwdev->mac.dle_info.c1_rx_qta;
1556 rx_max_pg = min_t(u32, rx_min_qta, PLD_RLS_MAX_PG);
1557 rx_max_len = rx_max_pg * rtwdev->mac.dle_info.ple_pg_size;
1558 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN);
1559 rx_max_len /= RX_MAX_LEN_UNIT;
1560
1561 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_FLTR_OPT, mac_idx);
1562 rtw89_write32_mask(rtwdev, reg, B_BE_RX_MPDU_MAX_LEN_MASK, rx_max_len);
1563
1564 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx);
1565 rtw89_write8_clr(rtwdev, reg, B_BE_VHT_SU_SIGB_CRC_CHK);
1566
1567 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RCR, mac_idx);
1568 rtw89_write16_set(rtwdev, reg, B_BE_BUSY_CHKSN);
1569
1570 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_PLCP_EXT_OPTION_1, mac_idx);
1571 rtw89_write16_set(rtwdev, reg, B_BE_PLCP_SU_PSDU_LEN_SRC);
1572
1573 if (chip->chip_id == RTL8922D) {
1574 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BSR_UPD_CTRL, mac_idx);
1575 rtw89_write32_set(rtwdev, reg, B_BE_QSIZE_RULE);
1576
1577 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RXGCK_CTRL, mac_idx);
1578 rtw89_write16_mask(rtwdev, reg, B_BE_RXGCK_GCK_RATE_LIMIT_MASK, RX_GCK_LEGACY);
1579
1580 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx);
1581 rtw89_write32_set(rtwdev, reg, B_BE_DIS_CHK_MIN_LEN);
1582 }
1583
1584 rtw89_io_unpack(rtwdev);
1585
1586 return 0;
1587 }
1588
resp_pktctl_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1589 static int resp_pktctl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1590 {
1591 struct rtw89_mac_dle_rsvd_qt_cfg qt_cfg;
1592 enum rtw89_mac_dle_rsvd_qt_type type;
1593 u32 reg;
1594 int ret;
1595
1596 if (mac_idx == RTW89_MAC_1)
1597 type = DLE_RSVD_QT_B1_CSI;
1598 else
1599 type = DLE_RSVD_QT_B0_CSI;
1600
1601 ret = rtw89_mac_get_dle_rsvd_qt_cfg(rtwdev, type, &qt_cfg);
1602 if (ret) {
1603 rtw89_err(rtwdev, "get dle rsvd qt %d cfg fail %d\n", type, ret);
1604 return ret;
1605 }
1606
1607 rtw89_io_pack(rtwdev);
1608
1609 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RESP_CSI_RESERVED_PAGE, mac_idx);
1610 rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_START_PAGE_MASK, qt_cfg.pktid);
1611 rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_PAGE_NUM_MASK, qt_cfg.pg_num + 1);
1612
1613 rtw89_io_unpack(rtwdev);
1614
1615 return 0;
1616 }
1617
cmac_com_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1618 static int cmac_com_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1619 {
1620 u32 val32;
1621 int ret;
1622
1623 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1624 if (ret)
1625 return ret;
1626
1627 if (mac_idx == RTW89_MAC_0) {
1628 val32 = rtw89_read32(rtwdev, R_BE_TX_SUB_BAND_VALUE);
1629 val32 = u32_replace_bits(val32, S_BE_TXSB_20M_8, B_BE_TXSB_20M_MASK);
1630 val32 = u32_replace_bits(val32, S_BE_TXSB_40M_4, B_BE_TXSB_40M_MASK);
1631 val32 = u32_replace_bits(val32, S_BE_TXSB_80M_2, B_BE_TXSB_80M_MASK);
1632 val32 = u32_replace_bits(val32, S_BE_TXSB_160M_1, B_BE_TXSB_160M_MASK);
1633 rtw89_write32(rtwdev, R_BE_TX_SUB_BAND_VALUE, val32);
1634 } else {
1635 val32 = rtw89_read32(rtwdev, R_BE_TX_SUB_BAND_VALUE_C1);
1636 val32 = u32_replace_bits(val32, S_BE_TXSB_20M_2, B_BE_TXSB_20M_MASK);
1637 val32 = u32_replace_bits(val32, S_BE_TXSB_40M_1, B_BE_TXSB_40M_MASK);
1638 val32 = u32_replace_bits(val32, S_BE_TXSB_80M_0, B_BE_TXSB_80M_MASK);
1639 val32 = u32_replace_bits(val32, S_BE_TXSB_160M_0, B_BE_TXSB_160M_MASK);
1640 rtw89_write32(rtwdev, R_BE_TX_SUB_BAND_VALUE_C1, val32);
1641 }
1642
1643 return 0;
1644 }
1645
ptcl_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1646 static int ptcl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1647 {
1648 const struct rtw89_chip_info *chip = rtwdev->chip;
1649 u32 val32;
1650 u8 val8;
1651 u32 reg;
1652 int ret;
1653
1654 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1655 if (ret)
1656 return ret;
1657
1658 rtw89_io_pack(rtwdev);
1659
1660 if (is_qta_poh(rtwdev)) {
1661 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SIFS_SETTING, mac_idx);
1662 val32 = rtw89_read32(rtwdev, reg);
1663 val32 = u32_replace_bits(val32, S_AX_CTS2S_TH_1K,
1664 B_BE_HW_CTS2SELF_PKT_LEN_TH_MASK);
1665 if (chip->chip_id == RTL8922A)
1666 val32 = u32_replace_bits(val32, S_AX_CTS2S_TH_SEC_256B,
1667 B_BE_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK);
1668 val32 |= B_BE_HW_CTS2SELF_EN;
1669 rtw89_write32(rtwdev, reg, val32);
1670
1671 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_FSM_MON, mac_idx);
1672 val32 = rtw89_read32(rtwdev, reg);
1673 val32 = u32_replace_bits(val32, S_AX_PTCL_TO_2MS,
1674 B_BE_PTCL_TX_ARB_TO_THR_MASK);
1675 val32 &= ~B_BE_PTCL_TX_ARB_TO_MODE;
1676 rtw89_write32(rtwdev, reg, val32);
1677 }
1678
1679 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_COMMON_SETTING_0, mac_idx);
1680 val8 = rtw89_read8(rtwdev, reg);
1681 val8 |= B_BE_CMAC_TX_MODE_0 | B_BE_CMAC_TX_MODE_1;
1682 val8 &= ~(B_BE_PTCL_TRIGGER_SS_EN_0 |
1683 B_BE_PTCL_TRIGGER_SS_EN_1 |
1684 B_BE_PTCL_TRIGGER_SS_EN_UL);
1685 rtw89_write8(rtwdev, reg, val8);
1686
1687 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AMPDU_AGG_LIMIT, mac_idx);
1688 if (chip->chip_id == RTL8922A)
1689 val32 = AMPDU_MAX_TIME;
1690 else
1691 val32 = AMPDU_MAX_TIME_V1;
1692 rtw89_write32_mask(rtwdev, reg, B_BE_AMPDU_MAX_TIME_MASK, val32);
1693
1694 if (chip->chip_id == RTL8922D) {
1695 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AGG_BK_0, mac_idx);
1696 rtw89_write32_clr(rtwdev, reg, B_BE_WDBK_CFG | B_BE_EN_RTY_BK |
1697 B_BE_EN_RTY_BK_COD);
1698
1699 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AMPDU_AGG_LIMIT, mac_idx);
1700 rtw89_write32_mask(rtwdev, reg, B_BE_MAX_AGG_NUM_MASK,
1701 MAX_TX_AMPDU_NUM_V1 - 1);
1702 }
1703
1704 if (rtw89_mac_chk_preload_allow(rtwdev)) {
1705 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AGG_BK_0, mac_idx);
1706 rtw89_write32_set(rtwdev, reg, B_BE_PRELD_MGQ0_EN |
1707 B_BE_PRELD_HIQ_P4_EN |
1708 B_BE_PRELD_HIQ_P3_EN |
1709 B_BE_PRELD_HIQ_P2_EN |
1710 B_BE_PRELD_HIQ_P1_EN |
1711 B_BE_PRELD_HIQ_P0MB15_EN |
1712 B_BE_PRELD_HIQ_P0MB14_EN |
1713 B_BE_PRELD_HIQ_P0MB13_EN |
1714 B_BE_PRELD_HIQ_P0MB12_EN |
1715 B_BE_PRELD_HIQ_P0MB11_EN |
1716 B_BE_PRELD_HIQ_P0MB10_EN |
1717 B_BE_PRELD_HIQ_P0MB9_EN |
1718 B_BE_PRELD_HIQ_P0MB8_EN |
1719 B_BE_PRELD_HIQ_P0MB7_EN |
1720 B_BE_PRELD_HIQ_P0MB6_EN |
1721 B_BE_PRELD_HIQ_P0MB5_EN |
1722 B_BE_PRELD_HIQ_P0MB4_EN |
1723 B_BE_PRELD_HIQ_P0MB3_EN |
1724 B_BE_PRELD_HIQ_P0MB2_EN |
1725 B_BE_PRELD_HIQ_P0MB1_EN |
1726 B_BE_PRELD_HIQ_P0_EN);
1727 }
1728
1729 rtw89_io_unpack(rtwdev);
1730
1731 return 0;
1732 }
1733
cmac_dma_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1734 static int cmac_dma_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1735 {
1736 u32 val32;
1737 u32 reg;
1738 int ret;
1739
1740 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1741 if (ret)
1742 return ret;
1743
1744 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_CTRL_1, mac_idx);
1745
1746 val32 = rtw89_read32(rtwdev, reg);
1747 val32 = u32_replace_bits(val32, WLCPU_RXCH2_QID,
1748 B_BE_RXDMA_TXRPT_QUEUE_ID_SW_MASK);
1749 val32 = u32_replace_bits(val32, WLCPU_RXCH2_QID,
1750 B_BE_RXDMA_F2PCMDRPT_QUEUE_ID_SW_MASK);
1751 rtw89_write32(rtwdev, reg, val32);
1752
1753 return 0;
1754 }
1755
cmac_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1756 static int cmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1757 {
1758 int ret;
1759
1760 ret = scheduler_init_be(rtwdev, mac_idx);
1761 if (ret) {
1762 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret);
1763 return ret;
1764 }
1765
1766 ret = addr_cam_init_be(rtwdev, mac_idx);
1767 if (ret) {
1768 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx,
1769 ret);
1770 return ret;
1771 }
1772
1773 ret = rx_fltr_init_be(rtwdev, mac_idx);
1774 if (ret) {
1775 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx,
1776 ret);
1777 return ret;
1778 }
1779
1780 ret = cca_ctrl_init_be(rtwdev, mac_idx);
1781 if (ret) {
1782 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx,
1783 ret);
1784 return ret;
1785 }
1786
1787 ret = nav_ctrl_init_be(rtwdev, mac_idx);
1788 if (ret) {
1789 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx,
1790 ret);
1791 return ret;
1792 }
1793
1794 ret = spatial_reuse_init_be(rtwdev, mac_idx);
1795 if (ret) {
1796 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n",
1797 mac_idx, ret);
1798 return ret;
1799 }
1800
1801 ret = tmac_init_be(rtwdev, mac_idx);
1802 if (ret) {
1803 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret);
1804 return ret;
1805 }
1806
1807 ret = trxptcl_init_be(rtwdev, mac_idx);
1808 if (ret) {
1809 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret);
1810 return ret;
1811 }
1812
1813 ret = rmac_init_be(rtwdev, mac_idx);
1814 if (ret) {
1815 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret);
1816 return ret;
1817 }
1818
1819 ret = resp_pktctl_init_be(rtwdev, mac_idx);
1820 if (ret) {
1821 rtw89_err(rtwdev, "[ERR]CMAC%d resp pktctl init %d\n", mac_idx, ret);
1822 return ret;
1823 }
1824
1825 ret = cmac_com_init_be(rtwdev, mac_idx);
1826 if (ret) {
1827 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret);
1828 return ret;
1829 }
1830
1831 ret = ptcl_init_be(rtwdev, mac_idx);
1832 if (ret) {
1833 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret);
1834 return ret;
1835 }
1836
1837 ret = cmac_dma_init_be(rtwdev, mac_idx);
1838 if (ret) {
1839 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret);
1840 return ret;
1841 }
1842
1843 return ret;
1844 }
1845
tx_idle_poll_band_be(struct rtw89_dev * rtwdev,u8 mac_idx)1846 static int tx_idle_poll_band_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1847 {
1848 u32 reg;
1849 u8 val8;
1850 int ret;
1851
1852 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1853 if (ret)
1854 return ret;
1855
1856 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_TX_CTN_SEL, mac_idx);
1857
1858 ret = read_poll_timeout_atomic(rtw89_read8, val8, !(val8 & B_BE_PTCL_BUSY),
1859 30, 66000, false, rtwdev, reg);
1860
1861 return ret;
1862 }
1863
dle_buf_req_be(struct rtw89_dev * rtwdev,u16 buf_len,bool wd,u16 * pkt_id)1864 static int dle_buf_req_be(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id)
1865 {
1866 u32 val, reg;
1867 int ret;
1868
1869 reg = wd ? R_BE_WD_BUF_REQ : R_BE_PL_BUF_REQ;
1870 val = buf_len;
1871 val |= B_BE_WD_BUF_REQ_EXEC;
1872 rtw89_write32(rtwdev, reg, val);
1873
1874 reg = wd ? R_BE_WD_BUF_STATUS : R_BE_PL_BUF_STATUS;
1875
1876 ret = read_poll_timeout(rtw89_read32, val, val & B_BE_WD_BUF_STAT_DONE,
1877 1, 2000, false, rtwdev, reg);
1878 if (ret)
1879 return ret;
1880
1881 *pkt_id = u32_get_bits(val, B_BE_WD_BUF_STAT_PKTID_MASK);
1882 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID)
1883 return -ENOENT;
1884
1885 return 0;
1886 }
1887
set_cpuio_be(struct rtw89_dev * rtwdev,struct rtw89_cpuio_ctrl * ctrl_para,bool wd)1888 static int set_cpuio_be(struct rtw89_dev *rtwdev,
1889 struct rtw89_cpuio_ctrl *ctrl_para, bool wd)
1890 {
1891 u32 val_op0, val_op1, val_op2, val_op3;
1892 u32 val, cmd_type, reg;
1893 int ret;
1894
1895 cmd_type = ctrl_para->cmd_type;
1896
1897 reg = wd ? R_BE_WD_CPUQ_OP_3 : R_BE_PL_CPUQ_OP_3;
1898 val_op3 = u32_replace_bits(0, ctrl_para->start_pktid,
1899 B_BE_WD_CPUQ_OP_STRT_PKTID_MASK);
1900 val_op3 = u32_replace_bits(val_op3, ctrl_para->end_pktid,
1901 B_BE_WD_CPUQ_OP_END_PKTID_MASK);
1902 rtw89_write32(rtwdev, reg, val_op3);
1903
1904 reg = wd ? R_BE_WD_CPUQ_OP_1 : R_BE_PL_CPUQ_OP_1;
1905 val_op1 = u32_replace_bits(0, ctrl_para->src_pid,
1906 B_BE_WD_CPUQ_OP_SRC_PID_MASK);
1907 val_op1 = u32_replace_bits(val_op1, ctrl_para->src_qid,
1908 B_BE_WD_CPUQ_OP_SRC_QID_MASK);
1909 val_op1 = u32_replace_bits(val_op1, ctrl_para->macid,
1910 B_BE_WD_CPUQ_OP_SRC_MACID_MASK);
1911 rtw89_write32(rtwdev, reg, val_op1);
1912
1913 reg = wd ? R_BE_WD_CPUQ_OP_2 : R_BE_PL_CPUQ_OP_2;
1914 val_op2 = u32_replace_bits(0, ctrl_para->dst_pid,
1915 B_BE_WD_CPUQ_OP_DST_PID_MASK);
1916 val_op2 = u32_replace_bits(val_op2, ctrl_para->dst_qid,
1917 B_BE_WD_CPUQ_OP_DST_QID_MASK);
1918 val_op2 = u32_replace_bits(val_op2, ctrl_para->macid,
1919 B_BE_WD_CPUQ_OP_DST_MACID_MASK);
1920 rtw89_write32(rtwdev, reg, val_op2);
1921
1922 reg = wd ? R_BE_WD_CPUQ_OP_0 : R_BE_PL_CPUQ_OP_0;
1923 val_op0 = u32_replace_bits(0, cmd_type,
1924 B_BE_WD_CPUQ_OP_CMD_TYPE_MASK);
1925 val_op0 = u32_replace_bits(val_op0, ctrl_para->pkt_num,
1926 B_BE_WD_CPUQ_OP_PKTNUM_MASK);
1927 val_op0 |= B_BE_WD_CPUQ_OP_EXEC;
1928 rtw89_write32(rtwdev, reg, val_op0);
1929
1930 reg = wd ? R_BE_WD_CPUQ_OP_STATUS : R_BE_PL_CPUQ_OP_STATUS;
1931
1932 ret = read_poll_timeout(rtw89_read32, val, val & B_BE_WD_CPUQ_OP_STAT_DONE,
1933 1, 2000, false, rtwdev, reg);
1934 if (ret) {
1935 rtw89_err(rtwdev, "[ERR]set cpuio wd timeout\n");
1936 rtw89_err(rtwdev, "[ERR]op_0=0x%X, op_1=0x%X, op_2=0x%X\n",
1937 val_op0, val_op1, val_op2);
1938 return ret;
1939 }
1940
1941 if (cmd_type == CPUIO_OP_CMD_GET_NEXT_PID ||
1942 cmd_type == CPUIO_OP_CMD_GET_1ST_PID)
1943 ctrl_para->pktid = u32_get_bits(val, B_BE_WD_CPUQ_OP_PKTID_MASK);
1944
1945 return 0;
1946 }
1947
dle_upd_qta_aval_page_be(struct rtw89_dev * rtwdev,enum rtw89_mac_dle_ctrl_type type,enum rtw89_mac_dle_ple_quota_id quota_id)1948 static int dle_upd_qta_aval_page_be(struct rtw89_dev *rtwdev,
1949 enum rtw89_mac_dle_ctrl_type type,
1950 enum rtw89_mac_dle_ple_quota_id quota_id)
1951 {
1952 u32 val;
1953
1954 if (type == DLE_CTRL_TYPE_WDE) {
1955 rtw89_write32_mask(rtwdev, R_BE_WDE_BUFMGN_CTL,
1956 B_BE_WDE_AVAL_UPD_QTAID_MASK, quota_id);
1957 rtw89_write32_set(rtwdev, R_BE_WDE_BUFMGN_CTL, B_BE_WDE_AVAL_UPD_REQ);
1958
1959 return read_poll_timeout(rtw89_read32, val,
1960 !(val & B_BE_WDE_AVAL_UPD_REQ),
1961 1, 2000, false, rtwdev, R_BE_WDE_BUFMGN_CTL);
1962 } else if (type == DLE_CTRL_TYPE_PLE) {
1963 rtw89_write32_mask(rtwdev, R_BE_PLE_BUFMGN_CTL,
1964 B_BE_PLE_AVAL_UPD_QTAID_MASK, quota_id);
1965 rtw89_write32_set(rtwdev, R_BE_PLE_BUFMGN_CTL, B_BE_PLE_AVAL_UPD_REQ);
1966
1967 return read_poll_timeout(rtw89_read32, val,
1968 !(val & B_BE_PLE_AVAL_UPD_REQ),
1969 1, 2000, false, rtwdev, R_BE_PLE_BUFMGN_CTL);
1970 }
1971
1972 rtw89_warn(rtwdev, "%s wrong type %d\n", __func__, type);
1973 return -EINVAL;
1974 }
1975
dle_quota_change_be(struct rtw89_dev * rtwdev,bool band1_en)1976 static int dle_quota_change_be(struct rtw89_dev *rtwdev, bool band1_en)
1977 {
1978 int ret;
1979
1980 if (band1_en) {
1981 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
1982 PLE_QTAID_B0_TXPL);
1983 if (ret) {
1984 rtw89_err(rtwdev, "update PLE B0 TX avail page fail %d\n", ret);
1985 return ret;
1986 }
1987
1988 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
1989 PLE_QTAID_CMAC0_RX);
1990 if (ret) {
1991 rtw89_err(rtwdev, "update PLE CMAC0 RX avail page fail %d\n", ret);
1992 return ret;
1993 }
1994 } else {
1995 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
1996 PLE_QTAID_B1_TXPL);
1997 if (ret) {
1998 rtw89_err(rtwdev, "update PLE B1 TX avail page fail %d\n", ret);
1999 return ret;
2000 }
2001
2002 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
2003 PLE_QTAID_CMAC1_RX);
2004 if (ret) {
2005 rtw89_err(rtwdev, "update PLE CMAC1 RX avail page fail %d\n", ret);
2006 return ret;
2007 }
2008 }
2009
2010 return 0;
2011 }
2012
preload_init_be(struct rtw89_dev * rtwdev,u8 mac_idx,enum rtw89_qta_mode mode)2013 static int preload_init_be(struct rtw89_dev *rtwdev, u8 mac_idx,
2014 enum rtw89_qta_mode mode)
2015 {
2016 const struct rtw89_chip_info *chip = rtwdev->chip;
2017 u32 max_preld_size, min_rsvd_size;
2018 u8 preld_acq, preld_miscq;
2019 u32 val32;
2020 u32 reg;
2021
2022 if (!(chip->chip_id == RTL8922A || rtw89_mac_chk_preload_allow(rtwdev)))
2023 return 0;
2024
2025 rtw89_io_pack(rtwdev);
2026
2027 max_preld_size = mac_idx == RTW89_MAC_0 ?
2028 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM;
2029 if (chip->chip_id == RTL8922D)
2030 max_preld_size = PRELD_B01_ENT_NUM_8922D;
2031 max_preld_size *= PRELD_AMSDU_SIZE;
2032 min_rsvd_size = PRELD_NEXT_MIN_SIZE;
2033
2034 reg = mac_idx == RTW89_MAC_0 ? R_BE_TXPKTCTL_B0_PRELD_CFG1 :
2035 R_BE_TXPKTCTL_B1_PRELD_CFG1;
2036 val32 = rtw89_read32(rtwdev, reg);
2037 val32 = u32_replace_bits(val32, PRELD_NEXT_WND, B_BE_B0_PRELD_NXT_TXENDWIN_MASK);
2038 val32 = u32_replace_bits(val32, min_rsvd_size, B_BE_B0_PRELD_NXT_RSVMINSZ_MASK);
2039 rtw89_write32(rtwdev, reg, val32);
2040
2041 reg = mac_idx == RTW89_MAC_0 ? R_BE_TXPKTCTL_B0_PRELD_CFG0 :
2042 R_BE_TXPKTCTL_B1_PRELD_CFG0;
2043 if (chip->chip_id == RTL8922D) {
2044 preld_acq = PRELD_ACQ_ENT_NUM_8922D;
2045 preld_miscq = PRELD_MISCQ_ENT_NUM_8922D;
2046 } else {
2047 preld_acq = mac_idx == RTW89_MAC_0 ? PRELD_B0_ACQ_ENT_NUM_8922A :
2048 PRELD_B1_ACQ_ENT_NUM_8922A;
2049 preld_miscq = PRELD_MISCQ_ENT_NUM_8922A;
2050 }
2051
2052 val32 = rtw89_read32(rtwdev, reg);
2053 val32 = u32_replace_bits(val32, preld_acq, B_BE_B0_PRELD_CAM_G0ENTNUM_MASK);
2054 val32 = u32_replace_bits(val32, preld_miscq, B_BE_B0_PRELD_CAM_G1ENTNUM_MASK);
2055 val32 = u32_replace_bits(val32, max_preld_size, B_BE_B0_PRELD_USEMAXSZ_MASK);
2056 val32 |= B_BE_B0_PRELD_FEN;
2057 rtw89_write32(rtwdev, reg, val32);
2058
2059 rtw89_io_unpack(rtwdev);
2060
2061 return 0;
2062 }
2063
clr_aon_intr_be(struct rtw89_dev * rtwdev)2064 static void clr_aon_intr_be(struct rtw89_dev *rtwdev)
2065 {
2066 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE)
2067 return;
2068
2069 rtw89_write32_clr(rtwdev, R_BE_FWS0IMR, B_BE_FS_GPIOA_INT_EN);
2070 rtw89_write32_set(rtwdev, R_BE_FWS0ISR, B_BE_FS_GPIOA_INT);
2071 }
2072
dbcc_bb_ctrl_be(struct rtw89_dev * rtwdev,bool bb1_en)2073 static int dbcc_bb_ctrl_be(struct rtw89_dev *rtwdev, bool bb1_en)
2074 {
2075 u32 set = B_BE_FEN_BB1PLAT_RSTB | B_BE_FEN_BB1_IP_RSTN;
2076
2077 if (bb1_en)
2078 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, set);
2079 else
2080 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE, set);
2081
2082 return 0;
2083 }
2084
enable_imr_be(struct rtw89_dev * rtwdev,u8 mac_idx,enum rtw89_mac_hwmod_sel sel)2085 static int enable_imr_be(struct rtw89_dev *rtwdev, u8 mac_idx,
2086 enum rtw89_mac_hwmod_sel sel)
2087 {
2088 const struct rtw89_chip_info *chip = rtwdev->chip;
2089 const struct rtw89_imr_table *table;
2090 const struct rtw89_reg_imr *reg;
2091 u32 addr;
2092 u32 val;
2093 int i;
2094
2095 if (sel == RTW89_DMAC_SEL)
2096 table = chip->imr_dmac_table;
2097 else if (sel == RTW89_CMAC_SEL)
2098 table = chip->imr_cmac_table;
2099 else
2100 return -EINVAL;
2101
2102 if (chip->chip_id == RTL8922D)
2103 rtw89_write32_mask(rtwdev, R_BE_NO_RX_ERR_CFG,
2104 B_BE_NO_RX_ERR_TO_MASK, 0);
2105
2106 for (i = 0; i < table->n_regs; i++) {
2107 reg = &table->regs[i];
2108 addr = rtw89_mac_reg_by_idx(rtwdev, reg->addr, mac_idx);
2109
2110 val = rtw89_read32(rtwdev, addr);
2111 val &= ~reg->clr;
2112 val |= reg->set;
2113 rtw89_write32(rtwdev, addr, val);
2114 }
2115
2116 return 0;
2117 }
2118
err_imr_ctrl_be(struct rtw89_dev * rtwdev,bool en)2119 static void err_imr_ctrl_be(struct rtw89_dev *rtwdev, bool en)
2120 {
2121 u32 v32_dmac = en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS;
2122 u32 v32_cmac0 = en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS;
2123 u32 v32_cmac1 = en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS;
2124
2125 v32_dmac &= ~B_BE_DMAC_NOTX_ERR_INT_EN;
2126
2127 rtw89_write32(rtwdev, R_BE_DMAC_ERR_IMR, v32_dmac);
2128 rtw89_write32(rtwdev, R_BE_CMAC_ERR_IMR, v32_cmac0);
2129
2130 if (rtwdev->dbcc_en)
2131 rtw89_write32(rtwdev, R_BE_CMAC_ERR_IMR_C1, v32_cmac1);
2132 }
2133
band1_enable_be(struct rtw89_dev * rtwdev)2134 static int band1_enable_be(struct rtw89_dev *rtwdev)
2135 {
2136 int ret;
2137
2138 ret = tx_idle_poll_band_be(rtwdev, RTW89_MAC_0);
2139 if (ret) {
2140 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret);
2141 return ret;
2142 }
2143
2144 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true);
2145 if (ret) {
2146 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);
2147 return ret;
2148 }
2149
2150 ret = preload_init_be(rtwdev, RTW89_MAC_1, rtwdev->mac.qta_mode);
2151 if (ret) {
2152 rtw89_err(rtwdev, "[ERR]preload init B1 %d\n", ret);
2153 return ret;
2154 }
2155
2156 ret = cmac_pwr_en_be(rtwdev, RTW89_MAC_1, true);
2157 if (ret) {
2158 rtw89_err(rtwdev, "[ERR]CMAC%d pwr en %d\n", RTW89_MAC_1, ret);
2159 return ret;
2160 }
2161
2162 ret = cmac_func_en_be(rtwdev, RTW89_MAC_1, true);
2163 if (ret) {
2164 rtw89_err(rtwdev, "[ERR]CMAC%d func en %d\n", RTW89_MAC_1, ret);
2165 return ret;
2166 }
2167
2168 ret = cmac_init_be(rtwdev, RTW89_MAC_1);
2169 if (ret) {
2170 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", RTW89_MAC_1, ret);
2171 return ret;
2172 }
2173
2174 ret = dbcc_bb_ctrl_be(rtwdev, true);
2175 if (ret) {
2176 rtw89_err(rtwdev, "[ERR]enable bb 1 %d\n", ret);
2177 return ret;
2178 }
2179
2180 ret = enable_imr_be(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL);
2181 if (ret) {
2182 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret);
2183 return ret;
2184 }
2185
2186 return 0;
2187 }
2188
band1_disable_be(struct rtw89_dev * rtwdev)2189 static int band1_disable_be(struct rtw89_dev *rtwdev)
2190 {
2191 int ret;
2192
2193 ret = dbcc_bb_ctrl_be(rtwdev, false);
2194 if (ret) {
2195 rtw89_err(rtwdev, "[ERR]disable bb 1 %d\n", ret);
2196 return ret;
2197 }
2198
2199 ret = cmac_func_en_be(rtwdev, RTW89_MAC_1, false);
2200 if (ret) {
2201 rtw89_err(rtwdev, "[ERR]CMAC%d func dis %d\n", RTW89_MAC_1, ret);
2202 return ret;
2203 }
2204
2205 ret = cmac_pwr_en_be(rtwdev, RTW89_MAC_1, false);
2206 if (ret) {
2207 rtw89_err(rtwdev, "[ERR]CMAC%d pwr dis %d\n", RTW89_MAC_1, ret);
2208 return ret;
2209 }
2210
2211 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, false);
2212 if (ret) {
2213 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);
2214 return ret;
2215 }
2216
2217 return 0;
2218 }
2219
dbcc_enable_be(struct rtw89_dev * rtwdev,bool enable)2220 static int dbcc_enable_be(struct rtw89_dev *rtwdev, bool enable)
2221 {
2222 int ret;
2223
2224 if (enable) {
2225 ret = band1_enable_be(rtwdev);
2226 if (ret) {
2227 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret);
2228 return ret;
2229 }
2230
2231 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) {
2232 ret = rtw89_fw_h2c_notify_dbcc(rtwdev, true);
2233 if (ret) {
2234 rtw89_err(rtwdev, "%s:[ERR] notify dbcc1 fail %d\n",
2235 __func__, ret);
2236 return ret;
2237 }
2238 }
2239 } else {
2240 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) {
2241 ret = rtw89_fw_h2c_notify_dbcc(rtwdev, false);
2242 if (ret) {
2243 rtw89_err(rtwdev, "%s:[ERR] notify dbcc1 fail %d\n",
2244 __func__, ret);
2245 return ret;
2246 }
2247 }
2248
2249 ret = band1_disable_be(rtwdev);
2250 if (ret) {
2251 rtw89_err(rtwdev, "[ERR] band1_disable %d\n", ret);
2252 return ret;
2253 }
2254 }
2255
2256 return 0;
2257 }
2258
set_host_rpr_be(struct rtw89_dev * rtwdev)2259 static int set_host_rpr_be(struct rtw89_dev *rtwdev)
2260 {
2261 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2262 u32 val32;
2263 u32 mode;
2264 u32 fltr;
2265 u32 qid;
2266 bool poh;
2267
2268 poh = is_qta_poh(rtwdev);
2269
2270 if (poh) {
2271 mode = RTW89_RPR_MODE_POH;
2272 qid = WDRLS_DEST_QID_POH;
2273 } else {
2274 mode = RTW89_RPR_MODE_STF;
2275 fltr = 0;
2276 qid = WDRLS_DEST_QID_STF;
2277 }
2278
2279 if (chip_id == RTL8922A) {
2280 fltr = S_BE_WDRLS_FLTR_TXOK | S_BE_WDRLS_FLTR_RTYLMT |
2281 S_BE_WDRLS_FLTR_LIFTIM | S_BE_WDRLS_FLTR_MACID;
2282 } else {
2283 fltr = S_BE_WDRLS_FLTR_TXOK_V1 | S_BE_WDRLS_FLTR_RTYLMT_V1 |
2284 S_BE_WDRLS_FLTR_LIFTIM_V1 | S_BE_WDRLS_FLTR_MACID_V1;
2285 }
2286
2287 rtw89_write32_mask(rtwdev, R_BE_WDRLS_CFG, B_BE_WDRLS_MODE_MASK, mode);
2288 rtw89_write32_mask(rtwdev, R_BE_RLSRPT0_CFG0, B_BE_RLSRPT0_QID_MASK, qid);
2289
2290 val32 = rtw89_read32(rtwdev, R_BE_RLSRPT0_CFG1);
2291 if (chip_id == RTL8922A)
2292 val32 = u32_replace_bits(val32, fltr, B_BE_RLSRPT0_FLTR_MAP_MASK);
2293 else
2294 val32 = u32_replace_bits(val32, fltr, B_BE_RLSRPT0_FLTR_MAP_V1_MASK);
2295 val32 = u32_replace_bits(val32, 30, B_BE_RLSRPT0_AGGNUM_MASK);
2296 val32 = u32_replace_bits(val32, 255, B_BE_RLSRPT0_TO_MASK);
2297 rtw89_write32(rtwdev, R_BE_RLSRPT0_CFG1, val32);
2298
2299 return 0;
2300 }
2301
trx_init_be(struct rtw89_dev * rtwdev)2302 static int trx_init_be(struct rtw89_dev *rtwdev)
2303 {
2304 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2305 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode;
2306 int ret;
2307
2308 ret = dmac_init_be(rtwdev, 0);
2309 if (ret) {
2310 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret);
2311 return ret;
2312 }
2313
2314 ret = cmac_init_be(rtwdev, 0);
2315 if (ret) {
2316 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret);
2317 return ret;
2318 }
2319
2320 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) {
2321 ret = dbcc_enable_be(rtwdev, true);
2322 if (ret) {
2323 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret);
2324 return ret;
2325 }
2326 }
2327
2328 ret = enable_imr_be(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
2329 if (ret) {
2330 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret);
2331 return ret;
2332 }
2333
2334 ret = enable_imr_be(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
2335 if (ret) {
2336 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret);
2337 return ret;
2338 }
2339
2340 err_imr_ctrl_be(rtwdev, true);
2341
2342 ret = set_host_rpr_be(rtwdev);
2343 if (ret) {
2344 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret);
2345 return ret;
2346 }
2347
2348 if (chip_id == RTL8922A)
2349 rtw89_write32_clr(rtwdev, R_BE_RSP_CHK_SIG,
2350 B_BE_RSP_STATIC_RTS_CHK_SERV_BW_EN);
2351
2352 return 0;
2353 }
2354
rtw89_mac_cfg_gnt_v2(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)2355 int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev,
2356 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
2357 {
2358 u32 val = 0;
2359
2360 if (gnt_cfg->band[0].gnt_bt)
2361 val |= B_BE_GNT_BT_BB0_VAL | B_BE_GNT_BT_RX_BB0_VAL |
2362 B_BE_GNT_BT_TX_BB0_VAL;
2363
2364 if (gnt_cfg->band[0].gnt_bt_sw_en)
2365 val |= B_BE_GNT_BT_BB0_SWCTRL | B_BE_GNT_BT_RX_BB0_SWCTRL |
2366 B_BE_GNT_BT_TX_BB0_SWCTRL;
2367
2368 if (gnt_cfg->band[0].gnt_wl)
2369 val |= B_BE_GNT_WL_BB0_VAL | B_BE_GNT_WL_RX_VAL |
2370 B_BE_GNT_WL_TX_VAL | B_BE_GNT_WL_BB_PWR_VAL;
2371
2372 if (gnt_cfg->band[0].gnt_wl_sw_en)
2373 val |= B_BE_GNT_WL_BB0_SWCTRL | B_BE_GNT_WL_RX_SWCTRL |
2374 B_BE_GNT_WL_TX_SWCTRL | B_BE_GNT_WL_BB_PWR_SWCTRL;
2375
2376 if (gnt_cfg->band[1].gnt_bt)
2377 val |= B_BE_GNT_BT_BB1_VAL | B_BE_GNT_BT_RX_BB1_VAL |
2378 B_BE_GNT_BT_TX_BB1_VAL;
2379
2380 if (gnt_cfg->band[1].gnt_bt_sw_en)
2381 val |= B_BE_GNT_BT_BB1_SWCTRL | B_BE_GNT_BT_RX_BB1_SWCTRL |
2382 B_BE_GNT_BT_TX_BB1_SWCTRL;
2383
2384 if (gnt_cfg->band[1].gnt_wl)
2385 val |= B_BE_GNT_WL_BB1_VAL | B_BE_GNT_WL_RX_VAL |
2386 B_BE_GNT_WL_TX_VAL | B_BE_GNT_WL_BB_PWR_VAL;
2387
2388 if (gnt_cfg->band[1].gnt_wl_sw_en)
2389 val |= B_BE_GNT_WL_BB1_SWCTRL | B_BE_GNT_WL_RX_SWCTRL |
2390 B_BE_GNT_WL_TX_SWCTRL | B_BE_GNT_WL_BB_PWR_SWCTRL;
2391
2392 if (gnt_cfg->bt[0].wlan_act_en)
2393 val |= B_BE_WL_ACT_SWCTRL;
2394 if (gnt_cfg->bt[0].wlan_act)
2395 val |= B_BE_WL_ACT_VAL;
2396 if (gnt_cfg->bt[1].wlan_act_en)
2397 val |= B_BE_WL_ACT2_SWCTRL;
2398 if (gnt_cfg->bt[1].wlan_act)
2399 val |= B_BE_WL_ACT2_VAL;
2400
2401 rtw89_write32(rtwdev, R_BE_GNT_SW_CTRL, val);
2402
2403 return 0;
2404 }
2405 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v2);
2406
rtw89_mac_cfg_gnt_v3(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)2407 int rtw89_mac_cfg_gnt_v3(struct rtw89_dev *rtwdev,
2408 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
2409 {
2410 u32 val = 0;
2411
2412 if (gnt_cfg->band[0].gnt_bt)
2413 val |= B_BE_PTA_GNT_BT0_BB_VAL | B_BE_PTA_GNT_BT0_RX_BB0_VAL |
2414 B_BE_PTA_GNT_BT0_TX_BB0_VAL;
2415
2416 if (gnt_cfg->band[0].gnt_bt_sw_en)
2417 val |= B_BE_PTA_GNT_BT0_BB_SWCTRL | B_BE_PTA_GNT_BT0_RX_BB0_SWCTRL |
2418 B_BE_PTA_GNT_BT0_TX_BB0_SWCTRL;
2419
2420 if (gnt_cfg->band[0].gnt_wl)
2421 val |= B_BE_PTA_GNT_WL_BB0_VAL;
2422
2423 if (gnt_cfg->band[0].gnt_wl_sw_en)
2424 val |= B_BE_PTA_GNT_WL_BB0_SWCTRL;
2425
2426 if (gnt_cfg->band[1].gnt_bt)
2427 val |= B_BE_PTA_GNT_BT0_BB_VAL | B_BE_PTA_GNT_BT0_RX_BB1_VAL |
2428 B_BE_PTA_GNT_BT0_TX_BB1_VAL;
2429
2430 if (gnt_cfg->band[1].gnt_bt_sw_en)
2431 val |= B_BE_PTA_GNT_BT0_BB_SWCTRL | B_BE_PTA_GNT_BT0_RX_BB1_SWCTRL |
2432 B_BE_PTA_GNT_BT0_TX_BB1_SWCTRL;
2433
2434 if (gnt_cfg->band[1].gnt_wl)
2435 val |= B_BE_PTA_GNT_WL_BB1_VAL;
2436
2437 if (gnt_cfg->band[1].gnt_wl_sw_en)
2438 val |= B_BE_PTA_GNT_WL_BB1_SWCTRL;
2439
2440 if (gnt_cfg->bt[0].wlan_act_en)
2441 val |= B_BE_PTA_WL_ACT0_SWCTRL | B_BE_PTA_WL_ACT_RX_BT0_SWCTRL |
2442 B_BE_PTA_WL_ACT_TX_BT0_SWCTRL;
2443 if (gnt_cfg->bt[0].wlan_act)
2444 val |= B_BE_PTA_WL_ACT0_VAL | B_BE_PTA_WL_ACT_RX_BT0_VAL |
2445 B_BE_PTA_WL_ACT_TX_BT0_VAL;
2446 if (gnt_cfg->bt[1].wlan_act_en)
2447 val |= B_BE_PTA_WL_ACT1_SWCTRL | B_BE_PTA_WL_ACT_RX_BT1_SWCTRL |
2448 B_BE_PTA_WL_ACT_TX_BT1_SWCTRL;
2449 if (gnt_cfg->bt[1].wlan_act)
2450 val |= B_BE_PTA_WL_ACT1_VAL | B_BE_PTA_WL_ACT_RX_BT1_VAL |
2451 B_BE_PTA_WL_ACT_TX_BT1_VAL;
2452
2453 rtw89_write32(rtwdev, R_BE_PTA_GNT_SW_CTRL, val);
2454
2455 return 0;
2456 }
2457 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v3);
2458
rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev * rtwdev,bool wl)2459 int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl)
2460 {
2461 const struct rtw89_chip_info *chip = rtwdev->chip;
2462 struct rtw89_mac_ax_coex_gnt gnt = {};
2463 int i;
2464
2465 if (wl)
2466 return 0;
2467
2468 for (i = 0; i < RTW89_PHY_NUM; i++) {
2469 gnt.band[i].gnt_bt_sw_en = 1;
2470 gnt.band[i].gnt_bt = 1;
2471 gnt.band[i].gnt_wl_sw_en = 1;
2472 gnt.band[i].gnt_wl = 0;
2473 gnt.bt[i].wlan_act = 1;
2474 gnt.bt[i].wlan_act_en = 0;
2475 }
2476
2477 if (chip->chip_id == RTL8922A)
2478 return rtw89_mac_cfg_gnt_v2(rtwdev, &gnt);
2479 else
2480 return rtw89_mac_cfg_gnt_v3(rtwdev, &gnt);
2481
2482 }
2483 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v2);
2484
2485 static
rtw89_mac_cfg_plt_be(struct rtw89_dev * rtwdev,struct rtw89_mac_ax_plt * plt)2486 int rtw89_mac_cfg_plt_be(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
2487 {
2488 u32 reg;
2489 u16 val;
2490 int ret;
2491
2492 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL);
2493 if (ret)
2494 return ret;
2495
2496 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, plt->band);
2497 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_TX_PLT_GNT_LTE_RX : 0) |
2498 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_TX_PLT_GNT_BT_TX : 0) |
2499 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_TX_PLT_GNT_BT_RX : 0) |
2500 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_TX_PLT_GNT_WL : 0) |
2501 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_RX_PLT_GNT_LTE_RX : 0) |
2502 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_RX_PLT_GNT_BT_TX : 0) |
2503 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_RX_PLT_GNT_BT_RX : 0) |
2504 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_RX_PLT_GNT_WL : 0) |
2505 B_BE_PLT_EN;
2506 rtw89_write16(rtwdev, reg, val);
2507
2508 return 0;
2509 }
2510
rtw89_mac_get_plt_cnt_be(struct rtw89_dev * rtwdev,u8 band)2511 static u16 rtw89_mac_get_plt_cnt_be(struct rtw89_dev *rtwdev, u8 band)
2512 {
2513 u32 reg;
2514 u16 cnt;
2515
2516 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, band);
2517 cnt = rtw89_read32_mask(rtwdev, reg, B_BE_BT_PLT_PKT_CNT_MASK);
2518 rtw89_write16_set(rtwdev, reg, B_BE_BT_PLT_RST);
2519
2520 return cnt;
2521 }
2522
rtw89_set_hw_sch_tx_en_v2(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en,u32 tx_en_mask)2523 static int rtw89_set_hw_sch_tx_en_v2(struct rtw89_dev *rtwdev, u8 mac_idx,
2524 u32 tx_en, u32 tx_en_mask)
2525 {
2526 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_DRV_TXEN, mac_idx);
2527 u32 val;
2528 int ret;
2529
2530 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2531 if (ret)
2532 return ret;
2533
2534 val = rtw89_read32(rtwdev, reg);
2535 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask);
2536 rtw89_write32(rtwdev, reg, val);
2537
2538 return 0;
2539 }
2540
rtw89_mac_stop_sch_tx_v2(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)2541 int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx,
2542 u32 *tx_en, enum rtw89_sch_tx_sel sel)
2543 {
2544 int ret;
2545
2546 *tx_en = rtw89_read32(rtwdev,
2547 rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_DRV_TXEN, mac_idx));
2548
2549 switch (sel) {
2550 case RTW89_SCH_TX_SEL_ALL:
2551 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, 0,
2552 B_BE_CTN_TXEN_ALL_MASK);
2553 if (ret)
2554 return ret;
2555 break;
2556 case RTW89_SCH_TX_SEL_HIQ:
2557 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx,
2558 0, B_BE_CTN_TXEN_HGQ);
2559 if (ret)
2560 return ret;
2561 break;
2562 case RTW89_SCH_TX_SEL_MG0:
2563 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx,
2564 0, B_BE_CTN_TXEN_MGQ);
2565 if (ret)
2566 return ret;
2567 break;
2568 case RTW89_SCH_TX_SEL_MACID:
2569 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, 0,
2570 B_BE_CTN_TXEN_ALL_MASK);
2571 if (ret)
2572 return ret;
2573 break;
2574 default:
2575 return 0;
2576 }
2577
2578 return 0;
2579 }
2580 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v2);
2581
rtw89_mac_resume_sch_tx_v2(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)2582 int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
2583 {
2584 int ret;
2585
2586 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, tx_en,
2587 B_BE_CTN_TXEN_ALL_MASK);
2588 if (ret)
2589 return ret;
2590
2591 return 0;
2592 }
2593 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v2);
2594
rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)2595 void rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
2596 {
2597 u32 reg, val;
2598
2599 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RCR, mac_idx);
2600 val = enable ? MAC_AX_PHY_RPT_SIZE_8 : MAC_AX_PHY_RPT_SIZE_0;
2601 rtw89_write32_mask(rtwdev, reg, B_BE_PHY_RPT_SZ_MASK, val);
2602 rtw89_write32_mask(rtwdev, reg, B_BE_HDR_CNV_SZ_MASK, MAC_AX_HDR_CNV_SIZE_0);
2603
2604 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DRV_INFO_OPTION, mac_idx);
2605 rtw89_write32_mask(rtwdev, reg, B_BE_DRV_INFO_PHYRPT_EN, enable);
2606 }
2607 EXPORT_SYMBOL(rtw89_mac_cfg_phy_rpt_be);
2608
2609 static
rtw89_mac_set_edcca_mode_be(struct rtw89_dev * rtwdev,u8 mac_idx,bool normal)2610 void rtw89_mac_set_edcca_mode_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool normal)
2611 {
2612 u16 resp_ack, resp_rts, resp_rts_punc, resp_normal, resp_normal_punc;
2613
2614 if (rtwdev->chip->chip_id == RTL8922A)
2615 return;
2616
2617 resp_ack = RESP_ACK_CFG_BE;
2618 resp_rts = RESP_RTS_CFG_BE;
2619 resp_rts_punc = RESP_RTS_PUNC_CFG_BE;
2620 resp_normal = RESP_NORMAL_CFG_BE;
2621 resp_normal_punc = RESP_NORMAL_PUNC_CFG_BE;
2622
2623 if (normal) {
2624 rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_LEGACY,
2625 resp_ack, mac_idx);
2626 rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_HE,
2627 resp_ack, mac_idx);
2628 rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC,
2629 resp_ack, mac_idx);
2630 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY,
2631 resp_rts, mac_idx);
2632 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY_PUNC,
2633 resp_rts_punc, mac_idx);
2634 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY,
2635 resp_normal, mac_idx);
2636 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY_PUNC,
2637 resp_normal_punc, mac_idx);
2638 rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_LEGACY,
2639 resp_normal, mac_idx);
2640 rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_HE,
2641 resp_normal_punc, mac_idx);
2642 rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_EHT_LEG_PUNC,
2643 resp_normal_punc, mac_idx);
2644 } else {
2645 rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_LEGACY,
2646 resp_normal, mac_idx);
2647 rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_HE,
2648 resp_normal_punc, mac_idx);
2649 rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC,
2650 resp_normal_punc, mac_idx);
2651 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY,
2652 resp_rts, mac_idx);
2653 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY_PUNC,
2654 resp_rts_punc, mac_idx);
2655 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY,
2656 resp_normal, mac_idx);
2657 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY_PUNC,
2658 resp_normal_punc, mac_idx);
2659 rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_LEGACY,
2660 resp_normal, mac_idx);
2661 rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_HE,
2662 resp_normal_punc, mac_idx);
2663 rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_EHT_LEG_PUNC,
2664 resp_normal_punc, mac_idx);
2665 }
2666 }
2667
2668 static
rtw89_mac_set_vcore_cfg_be(struct rtw89_dev * rtwdev,u8 vlv)2669 void rtw89_mac_set_vcore_cfg_be(struct rtw89_dev *rtwdev, u8 vlv)
2670 {
2671 struct rtw89_hal *hal = &rtwdev->hal;
2672 u32 val32;
2673 u8 target;
2674 u8 vpwm;
2675 int i;
2676
2677 if (rtwdev->chip->chip_id != RTL8922D)
2678 return;
2679
2680 target = clamp(hal->thermal_prot_vmax - vlv,
2681 hal->thermal_prot_vmin, hal->thermal_prot_vmax);
2682
2683 val32 = rtw89_read32(rtwdev, R_BE_SPS_DIG_ON_CTRL0);
2684 vpwm = u32_get_bits(val32, B_BE_PWMTUNE_MASK);
2685 val32 &= ~B_BE_PWMTUNE_MASK;
2686
2687 if (vpwm == target)
2688 return;
2689
2690 for (i = 0; i < RTW89_THERMAL_PROT_VLV_MAX; i++) {
2691 if (vpwm > target)
2692 vpwm--;
2693 else
2694 vpwm++;
2695
2696 rtw89_write32(rtwdev, R_BE_SPS_DIG_ON_CTRL0, val32 | vpwm);
2697
2698 if (vpwm == target)
2699 break;
2700
2701 mdelay(50);
2702 }
2703 }
2704
2705 static
rtw89_mac_cfg_ppdu_status_be(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)2706 int rtw89_mac_cfg_ppdu_status_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
2707 {
2708 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PPDU_STAT, mac_idx);
2709 int ret;
2710
2711 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2712 if (ret)
2713 return ret;
2714
2715 if (!enable) {
2716 rtw89_write32_clr(rtwdev, reg, B_BE_PPDU_STAT_RPT_EN);
2717 return 0;
2718 }
2719
2720 rtw89_write32_mask(rtwdev, R_BE_HW_PPDU_STATUS, B_BE_FWD_PPDU_STAT_MASK, 3);
2721 rtw89_write32(rtwdev, reg, B_BE_PPDU_STAT_RPT_EN |
2722 B_BE_APP_RX_CNT_RPT | B_BE_APP_PLCP_HDR_RPT |
2723 B_BE_PPDU_STAT_RPT_CRC32 | B_BE_PPDU_STAT_RPT_DMA);
2724
2725 return 0;
2726 }
2727
rtw89_mac_get_txpwr_cr_be(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * cr)2728 static bool rtw89_mac_get_txpwr_cr_be(struct rtw89_dev *rtwdev,
2729 enum rtw89_phy_idx phy_idx,
2730 u32 reg_base, u32 *cr)
2731 {
2732 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode;
2733 int ret;
2734
2735 ret = rtw89_mac_check_mac_en(rtwdev, (enum rtw89_mac_idx)phy_idx,
2736 RTW89_CMAC_SEL);
2737 if (ret) {
2738 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags))
2739 return false;
2740
2741 rtw89_err(rtwdev, "[TXPWR] check mac enable failed\n");
2742 return false;
2743 }
2744
2745 if (reg_base < R_BE_PWR_MODULE || reg_base > R_BE_CMAC_FUNC_EN_C1) {
2746 rtw89_err(rtwdev, "[TXPWR] reg_base=0x%x exceed txpwr cr\n",
2747 reg_base);
2748 return false;
2749 }
2750
2751 *cr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx);
2752
2753 if (*cr >= CMAC1_START_ADDR_BE && *cr <= CMAC1_END_ADDR_BE) {
2754 if (mode == RTW89_QTA_SCC) {
2755 rtw89_err(rtwdev,
2756 "[TXPWR] addr=0x%x but hw not enable\n",
2757 *cr);
2758 return false;
2759 }
2760 }
2761
2762 return true;
2763 }
2764
rtw89_mac_init_bfee_be(struct rtw89_dev * rtwdev,u8 mac_idx)2765 static int rtw89_mac_init_bfee_be(struct rtw89_dev *rtwdev, u8 mac_idx)
2766 {
2767 u32 reg;
2768 u32 val;
2769 int ret;
2770
2771 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2772 if (ret)
2773 return ret;
2774
2775 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true);
2776
2777 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
2778 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL |
2779 B_BE_BFMEE_USE_NSTS |
2780 B_BE_BFMEE_CSI_GID_SEL |
2781 B_BE_BFMEE_CSI_FORCE_RETE_EN);
2782 rtw89_write32_mask(rtwdev, reg, B_BE_BFMEE_CSI_RSC_MASK, CSI_RX_BW_CFG);
2783
2784 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CSIRPT_OPTION, mac_idx);
2785 rtw89_write32_set(rtwdev, reg, B_BE_CSIPRT_VHTSU_AID_EN |
2786 B_BE_CSIPRT_HESU_AID_EN |
2787 B_BE_CSIPRT_EHTSU_AID_EN);
2788
2789 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RRSC, mac_idx);
2790 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP_BE);
2791
2792 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_1, mac_idx);
2793 rtw89_write32_mask(rtwdev, reg, B_BE_BFMEE_BE_CSI_RRSC_BITMAP_MASK,
2794 CSI_RRSC_BITMAP_CFG);
2795
2796 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RATE, mac_idx);
2797 val = u32_encode_bits(CSI_INIT_RATE_HT, B_BE_BFMEE_HT_CSI_RATE_MASK) |
2798 u32_encode_bits(CSI_INIT_RATE_VHT, B_BE_BFMEE_VHT_CSI_RATE_MASK) |
2799 u32_encode_bits(CSI_INIT_RATE_HE, B_BE_BFMEE_HE_CSI_RATE_MASK) |
2800 u32_encode_bits(CSI_INIT_RATE_EHT, B_BE_BFMEE_EHT_CSI_RATE_MASK);
2801
2802 rtw89_write32(rtwdev, reg, val);
2803
2804 return 0;
2805 }
2806
rtw89_mac_set_csi_para_reg_be(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)2807 static int rtw89_mac_set_csi_para_reg_be(struct rtw89_dev *rtwdev,
2808 struct rtw89_vif_link *rtwvif_link,
2809 struct rtw89_sta_link *rtwsta_link)
2810 {
2811 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1;
2812 struct ieee80211_link_sta *link_sta;
2813 u8 mac_idx = rtwvif_link->mac_idx;
2814 u8 port_sel = rtwvif_link->port;
2815 u8 sound_dim = 3, t;
2816 u8 *phy_cap;
2817 u32 reg;
2818 u16 val;
2819 int ret;
2820
2821 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2822 if (ret)
2823 return ret;
2824
2825 rcu_read_lock();
2826
2827 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
2828 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info;
2829
2830 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
2831 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) {
2832 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD);
2833 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ);
2834 t = u8_get_bits(phy_cap[5],
2835 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK);
2836 sound_dim = min(sound_dim, t);
2837 }
2838
2839 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
2840 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {
2841 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC);
2842 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK);
2843 t = u32_get_bits(link_sta->vht_cap.cap,
2844 IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK);
2845 sound_dim = min(sound_dim, t);
2846 }
2847
2848 /* Disable stbc_en in VHT 160MHz to avoid IOT issues with certain APs */
2849 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ)
2850 stbc_en = 0;
2851
2852 nc = min(nc, sound_dim);
2853 nr = min(nr, sound_dim);
2854
2855 rcu_read_unlock();
2856
2857 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
2858 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL);
2859
2860 val = u16_encode_bits(nc, B_BE_BFMEE_CSIINFO0_NC_MASK) |
2861 u16_encode_bits(nr, B_BE_BFMEE_CSIINFO0_NR_MASK) |
2862 u16_encode_bits(ng, B_BE_BFMEE_CSIINFO0_NG_MASK) |
2863 u16_encode_bits(cb, B_BE_BFMEE_CSIINFO0_CB_MASK) |
2864 u16_encode_bits(cs, B_BE_BFMEE_CSIINFO0_CS_MASK) |
2865 u16_encode_bits(ldpc_en, B_BE_BFMEE_CSIINFO0_LDPC_EN) |
2866 u16_encode_bits(stbc_en, B_BE_BFMEE_CSIINFO0_STBC_EN);
2867
2868 if (port_sel == 0)
2869 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0,
2870 mac_idx);
2871 else
2872 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_1,
2873 mac_idx);
2874
2875 rtw89_write16(rtwdev, reg, val);
2876
2877 return 0;
2878 }
2879
rtw89_mac_csi_rrsc_be(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)2880 static int rtw89_mac_csi_rrsc_be(struct rtw89_dev *rtwdev,
2881 struct rtw89_vif_link *rtwvif_link,
2882 struct rtw89_sta_link *rtwsta_link)
2883 {
2884 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M);
2885 struct ieee80211_link_sta *link_sta;
2886 u8 mac_idx = rtwvif_link->mac_idx;
2887 int ret;
2888 u32 reg;
2889
2890 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2891 if (ret)
2892 return ret;
2893
2894 rcu_read_lock();
2895
2896 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
2897
2898 if (link_sta->he_cap.has_he) {
2899 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) |
2900 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) |
2901 BIT(RTW89_MAC_BF_RRSC_HE_MSC5));
2902 }
2903 if (link_sta->vht_cap.vht_supported) {
2904 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) |
2905 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) |
2906 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5));
2907 }
2908 if (link_sta->ht_cap.ht_supported) {
2909 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) |
2910 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) |
2911 BIT(RTW89_MAC_BF_RRSC_HT_MSC5));
2912 }
2913
2914 rcu_read_unlock();
2915
2916 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
2917 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL);
2918 rtw89_write32_clr(rtwdev, reg, B_BE_BFMEE_CSI_FORCE_RETE_EN);
2919
2920 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RRSC, mac_idx);
2921 rtw89_write32(rtwdev, reg, rrsc);
2922
2923 return 0;
2924 }
2925
rtw89_mac_bf_assoc_be(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)2926 static void rtw89_mac_bf_assoc_be(struct rtw89_dev *rtwdev,
2927 struct rtw89_vif_link *rtwvif_link,
2928 struct rtw89_sta_link *rtwsta_link)
2929 {
2930 struct ieee80211_link_sta *link_sta;
2931 bool has_beamformer_cap;
2932
2933 rcu_read_lock();
2934
2935 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
2936 has_beamformer_cap = rtw89_sta_has_beamformer_cap(link_sta);
2937
2938 rcu_read_unlock();
2939
2940 if (has_beamformer_cap) {
2941 rtw89_debug(rtwdev, RTW89_DBG_BF,
2942 "initialize bfee for new association\n");
2943 rtw89_mac_init_bfee_be(rtwdev, rtwvif_link->mac_idx);
2944 rtw89_mac_set_csi_para_reg_be(rtwdev, rtwvif_link, rtwsta_link);
2945 rtw89_mac_csi_rrsc_be(rtwdev, rtwvif_link, rtwsta_link);
2946 }
2947 }
2948
dump_err_status_dispatcher_be(struct rtw89_dev * rtwdev)2949 static void dump_err_status_dispatcher_be(struct rtw89_dev *rtwdev)
2950 {
2951 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x ",
2952 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR));
2953 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n",
2954 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1));
2955 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x ",
2956 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR));
2957 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n",
2958 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2));
2959 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x ",
2960 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR));
2961 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n",
2962 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0));
2963 }
2964
rtw89_mac_dump_qta_lost_be(struct rtw89_dev * rtwdev)2965 static void rtw89_mac_dump_qta_lost_be(struct rtw89_dev *rtwdev)
2966 {
2967 struct rtw89_mac_dle_dfi_qempty qempty;
2968 struct rtw89_mac_dle_dfi_quota quota;
2969 struct rtw89_mac_dle_dfi_ctrl ctrl;
2970 u32 val, not_empty, i;
2971 int ret;
2972
2973 qempty.dle_type = DLE_CTRL_TYPE_PLE;
2974 qempty.grpsel = 0;
2975 qempty.qempty = ~(u32)0;
2976 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty);
2977 if (ret)
2978 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
2979 else
2980 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty);
2981
2982 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) {
2983 if (!(not_empty & BIT(0)))
2984 continue;
2985 ctrl.type = DLE_CTRL_TYPE_PLE;
2986 ctrl.target = DLE_DFI_TYPE_QLNKTBL;
2987 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) |
2988 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK);
2989 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl);
2990 if (ret)
2991 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
2992 else
2993 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i,
2994 u32_get_bits(ctrl.out_data,
2995 QLNKTBL_DATA_SEL1_PKT_CNT_MASK));
2996 }
2997
2998 quota.dle_type = DLE_CTRL_TYPE_PLE;
2999 quota.qtaid = 6;
3000 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a);
3001 if (ret)
3002 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
3003 else
3004 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n",
3005 quota.rsv_pgnum, quota.use_pgnum);
3006
3007 val = rtw89_read32(rtwdev, R_BE_PLE_QTA6_CFG);
3008 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n",
3009 u32_get_bits(val, B_BE_PLE_Q6_MIN_SIZE_MASK));
3010 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n",
3011 u32_get_bits(val, B_BE_PLE_Q6_MAX_SIZE_MASK));
3012 val = rtw89_read32(rtwdev, R_BE_RX_FLTR_OPT);
3013 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_BE_RX_MPDU_MAX_LEN=0x%x\n",
3014 u32_get_bits(val, B_BE_RX_MPDU_MAX_LEN_MASK));
3015 rtw89_info(rtwdev, "R_BE_RSP_CHK_SIG=0x%08x\n",
3016 rtw89_read32(rtwdev, R_BE_RSP_CHK_SIG));
3017 rtw89_info(rtwdev, "R_BE_TRXPTCL_RESP_0=0x%08x\n",
3018 rtw89_read32(rtwdev, R_BE_TRXPTCL_RESP_0));
3019
3020 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) {
3021 quota.dle_type = DLE_CTRL_TYPE_PLE;
3022 quota.qtaid = 7;
3023 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a);
3024 if (ret)
3025 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
3026 else
3027 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n",
3028 quota.rsv_pgnum, quota.use_pgnum);
3029
3030 val = rtw89_read32(rtwdev, R_BE_PLE_QTA7_CFG);
3031 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n",
3032 u32_get_bits(val, B_BE_PLE_Q7_MIN_SIZE_MASK));
3033 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n",
3034 u32_get_bits(val, B_BE_PLE_Q7_MAX_SIZE_MASK));
3035 val = rtw89_read32(rtwdev, R_BE_RX_FLTR_OPT_C1);
3036 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_BE_RX_MPDU_MAX_LEN=0x%x\n",
3037 u32_get_bits(val, B_BE_RX_MPDU_MAX_LEN_MASK));
3038 rtw89_info(rtwdev, "R_BE_RSP_CHK_SIG_C1=0x%08x\n",
3039 rtw89_read32(rtwdev, R_BE_RSP_CHK_SIG_C1));
3040 rtw89_info(rtwdev, "R_BE_TRXPTCL_RESP_0_C1=0x%08x\n",
3041 rtw89_read32(rtwdev, R_BE_TRXPTCL_RESP_0_C1));
3042 }
3043
3044 rtw89_info(rtwdev, "R_BE_DLE_EMPTY0=0x%08x\n",
3045 rtw89_read32(rtwdev, R_BE_DLE_EMPTY0));
3046 rtw89_info(rtwdev, "R_BE_DLE_EMPTY1=0x%08x\n",
3047 rtw89_read32(rtwdev, R_BE_DLE_EMPTY1));
3048
3049 dump_err_status_dispatcher_be(rtwdev);
3050 }
3051
rtw89_wow_config_mac_be(struct rtw89_dev * rtwdev,bool enable_wow)3052 static int rtw89_wow_config_mac_be(struct rtw89_dev *rtwdev, bool enable_wow)
3053 {
3054 if (enable_wow) {
3055 rtw89_write32_set(rtwdev, R_BE_RX_STOP, B_BE_HOST_RX_STOP);
3056 rtw89_write32_clr(rtwdev, R_BE_RX_FLTR_OPT, B_BE_SNIFFER_MODE);
3057 rtw89_mac_cpu_io_rx(rtwdev, enable_wow);
3058 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
3059 rtw89_write32(rtwdev, R_BE_FWD_ERR, 0);
3060 rtw89_write32(rtwdev, R_BE_FWD_ACTN0, 0);
3061 rtw89_write32(rtwdev, R_BE_FWD_ACTN1, 0);
3062 rtw89_write32(rtwdev, R_BE_FWD_ACTN2, 0);
3063 rtw89_write32(rtwdev, R_BE_FWD_TF0, 0);
3064 rtw89_write32(rtwdev, R_BE_FWD_TF1, 0);
3065 rtw89_write32(rtwdev, R_BE_FWD_ERR, 0);
3066 rtw89_write32(rtwdev, R_BE_HW_PPDU_STATUS, 0);
3067 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY);
3068 } else {
3069 rtw89_mac_cpu_io_rx(rtwdev, enable_wow);
3070 rtw89_write32_clr(rtwdev, R_BE_RX_STOP, B_BE_HOST_RX_STOP);
3071 rtw89_write32_set(rtwdev, R_BE_RX_FLTR_OPT, R_BE_RX_FLTR_OPT);
3072 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
3073 }
3074
3075 return 0;
3076 }
3077
rtw89_mac_dump_cmac_err_status_be(struct rtw89_dev * rtwdev,u8 band)3078 static void rtw89_mac_dump_cmac_err_status_be(struct rtw89_dev *rtwdev,
3079 u8 band)
3080 {
3081 u32 offset = 0;
3082 u32 cmac_err;
3083 int ret;
3084
3085 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL);
3086 if (ret) {
3087 rtw89_info(rtwdev, "[CMAC] : CMAC%d not enabled\n", band);
3088 return;
3089 }
3090
3091 if (band)
3092 offset = RTW89_MAC_BE_BAND_REG_OFFSET;
3093
3094 cmac_err = rtw89_read32(rtwdev, R_BE_CMAC_ERR_ISR + offset);
3095 rtw89_info(rtwdev, "R_BE_CMAC_ERR_ISR [%d]=0x%08x\n", band,
3096 rtw89_read32(rtwdev, R_BE_CMAC_ERR_ISR + offset));
3097 rtw89_info(rtwdev, "R_BE_CMAC_FUNC_EN [%d]=0x%08x\n", band,
3098 rtw89_read32(rtwdev, R_BE_CMAC_FUNC_EN + offset));
3099 rtw89_info(rtwdev, "R_BE_CK_EN [%d]=0x%08x\n", band,
3100 rtw89_read32(rtwdev, R_BE_CK_EN + offset));
3101
3102 if (cmac_err & B_BE_SCHEDULE_TOP_ERR_IND) {
3103 rtw89_info(rtwdev, "R_BE_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band,
3104 rtw89_read32(rtwdev, R_BE_SCHEDULE_ERR_IMR + offset));
3105 rtw89_info(rtwdev, "R_BE_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band,
3106 rtw89_read32(rtwdev, R_BE_SCHEDULE_ERR_ISR + offset));
3107 }
3108
3109 if (cmac_err & B_BE_PTCL_TOP_ERR_IND) {
3110 rtw89_info(rtwdev, "R_BE_PTCL_IMR0 [%d]=0x%08x\n", band,
3111 rtw89_read32(rtwdev, R_BE_PTCL_IMR0 + offset));
3112 rtw89_info(rtwdev, "R_BE_PTCL_ISR0 [%d]=0x%08x\n", band,
3113 rtw89_read32(rtwdev, R_BE_PTCL_ISR0 + offset));
3114 rtw89_info(rtwdev, "R_BE_PTCL_IMR1 [%d]=0x%08x\n", band,
3115 rtw89_read32(rtwdev, R_BE_PTCL_IMR1 + offset));
3116 rtw89_info(rtwdev, "R_BE_PTCL_ISR1 [%d]=0x%08x\n", band,
3117 rtw89_read32(rtwdev, R_BE_PTCL_ISR1 + offset));
3118 }
3119
3120 if (cmac_err & B_BE_DMA_TOP_ERR_IND) {
3121 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG_IMR [%d]=0x%08x\n", band,
3122 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG_IMR + offset));
3123 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG [%d]=0x%08x\n", band,
3124 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG + offset));
3125 rtw89_info(rtwdev, "R_BE_TX_ERROR_FLAG_IMR [%d]=0x%08x\n", band,
3126 rtw89_read32(rtwdev, R_BE_TX_ERROR_FLAG_IMR + offset));
3127 rtw89_info(rtwdev, "R_BE_TX_ERROR_FLAG [%d]=0x%08x\n", band,
3128 rtw89_read32(rtwdev, R_BE_TX_ERROR_FLAG + offset));
3129 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG_IMR_1 [%d]=0x%08x\n", band,
3130 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG_IMR_1 + offset));
3131 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG_1 [%d]=0x%08x\n", band,
3132 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG_1 + offset));
3133 }
3134
3135 if (cmac_err & B_BE_PHYINTF_ERR_IND) {
3136 rtw89_info(rtwdev, "R_BE_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
3137 rtw89_read32(rtwdev, R_BE_PHYINFO_ERR_IMR_V1 + offset));
3138 rtw89_info(rtwdev, "R_BE_PHYINFO_ERR_ISR [%d]=0x%08x\n", band,
3139 rtw89_read32(rtwdev, R_BE_PHYINFO_ERR_ISR + offset));
3140 }
3141
3142 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
3143 rtw89_info(rtwdev, "R_BE_TXPWR_ERR_FLAG [%d]=0x%08x\n", band,
3144 rtw89_read32(rtwdev, R_BE_TXPWR_ERR_FLAG + offset));
3145 rtw89_info(rtwdev, "R_BE_TXPWR_ERR_IMR [%d]=0x%08x\n", band,
3146 rtw89_read32(rtwdev, R_BE_TXPWR_ERR_IMR + offset));
3147 }
3148
3149 if (cmac_err & (B_BE_WMAC_RX_ERR_IND | B_BE_WMAC_TX_ERR_IND |
3150 B_BE_WMAC_RX_IDLETO_IDCT | B_BE_PTCL_TX_IDLETO_IDCT)) {
3151 rtw89_info(rtwdev, "R_BE_DBGSEL_TRXPTCL [%d]=0x%08x\n", band,
3152 rtw89_read32(rtwdev, R_BE_DBGSEL_TRXPTCL + offset));
3153 rtw89_info(rtwdev, "R_BE_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band,
3154 rtw89_read32(rtwdev, R_BE_TRXPTCL_ERROR_INDICA_MASK + offset));
3155 rtw89_info(rtwdev, "R_BE_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band,
3156 rtw89_read32(rtwdev, R_BE_TRXPTCL_ERROR_INDICA + offset));
3157 rtw89_info(rtwdev, "R_BE_RX_ERR_IMR [%d]=0x%08x\n", band,
3158 rtw89_read32(rtwdev, R_BE_RX_ERR_IMR + offset));
3159 rtw89_info(rtwdev, "R_BE_RX_ERR_ISR [%d]=0x%08x\n", band,
3160 rtw89_read32(rtwdev, R_BE_RX_ERR_ISR + offset));
3161 }
3162
3163 rtw89_info(rtwdev, "R_BE_CMAC_ERR_IMR [%d]=0x%08x\n", band,
3164 rtw89_read32(rtwdev, R_BE_CMAC_ERR_IMR + offset));
3165 }
3166
rtw89_mac_dump_err_status_be(struct rtw89_dev * rtwdev,enum mac_ax_err_info err)3167 static void rtw89_mac_dump_err_status_be(struct rtw89_dev *rtwdev,
3168 enum mac_ax_err_info err)
3169 {
3170 if (err != MAC_AX_ERR_L1_ERR_DMAC &&
3171 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 &&
3172 err != MAC_AX_ERR_L0_ERR_CMAC0 &&
3173 err != MAC_AX_ERR_L0_ERR_CMAC1 &&
3174 err != MAC_AX_ERR_RXI300)
3175 return;
3176
3177 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
3178 rtw89_info(rtwdev, "R_BE_SER_DBG_INFO=0x%08x\n",
3179 rtw89_read32(rtwdev, R_BE_SER_DBG_INFO));
3180 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT=0x%08x\n",
3181 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT));
3182 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT1=0x%08x\n",
3183 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT1));
3184 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT2=0x%08x\n",
3185 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT2));
3186 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT3=0x%08x\n",
3187 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT3));
3188 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) {
3189 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT_C1=0x%08x\n",
3190 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT_C1));
3191 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT1_C1=0x%08x\n",
3192 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT1_C1));
3193 }
3194 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_0=0x%08x\n",
3195 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_0));
3196 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_1=0x%08x\n",
3197 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_1));
3198 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_2=0x%08x\n",
3199 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_2));
3200 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_3=0x%08x\n",
3201 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_3));
3202 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_4=0x%08x\n",
3203 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_4));
3204 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_5=0x%08x\n",
3205 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_5));
3206 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_6=0x%08x\n",
3207 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_6));
3208 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_7=0x%08x\n",
3209 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_7));
3210
3211 rtw89_mac_dump_dmac_err_status(rtwdev);
3212 rtw89_mac_dump_cmac_err_status_be(rtwdev, RTW89_MAC_0);
3213 rtw89_mac_dump_cmac_err_status_be(rtwdev, RTW89_MAC_1);
3214
3215 rtwdev->hci.ops->dump_err_status(rtwdev);
3216
3217 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1)
3218 rtw89_mac_dump_l0_to_l1(rtwdev, err);
3219
3220 rtw89_info(rtwdev, "<---\n");
3221 }
3222
mac_is_txq_empty_be(struct rtw89_dev * rtwdev)3223 static bool mac_is_txq_empty_be(struct rtw89_dev *rtwdev)
3224 {
3225 struct rtw89_mac_dle_dfi_qempty qempty;
3226 u32 val32, msk32;
3227 u32 grpnum;
3228 int ret;
3229 int i;
3230
3231 grpnum = rtwdev->chip->wde_qempty_acq_grpnum;
3232 qempty.dle_type = DLE_CTRL_TYPE_WDE;
3233
3234 for (i = 0; i < grpnum; i++) {
3235 qempty.grpsel = i;
3236 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty);
3237 if (ret) {
3238 rtw89_warn(rtwdev,
3239 "%s: failed to dle dfi acq empty: %d\n",
3240 __func__, ret);
3241 return false;
3242 }
3243
3244 /* Each acq group contains 32 queues (8 macid * 4 acq),
3245 * but here, we can simply check if all bits are set.
3246 */
3247 if (qempty.qempty != MASKDWORD)
3248 return false;
3249 }
3250
3251 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel;
3252 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty);
3253 if (ret) {
3254 rtw89_warn(rtwdev, "%s: failed to dle dfi mgq empty: %d\n",
3255 __func__, ret);
3256 return false;
3257 }
3258
3259 msk32 = B_CMAC0_MGQ_NORMAL_BE | B_CMAC1_MGQ_NORMAL_BE;
3260 if ((qempty.qempty & msk32) != msk32)
3261 return false;
3262
3263 msk32 = B_BE_WDE_EMPTY_QUE_OTHERS;
3264 val32 = rtw89_read32(rtwdev, R_BE_DLE_EMPTY0);
3265 return (val32 & msk32) == msk32;
3266 }
3267
3268 const struct rtw89_mac_gen_def rtw89_mac_gen_be = {
3269 .band1_offset = RTW89_MAC_BE_BAND_REG_OFFSET,
3270 .filter_model_addr = R_BE_FILTER_MODEL_ADDR,
3271 .indir_access_addr = R_BE_INDIR_ACCESS_ENTRY,
3272 .mem_base_addrs = rtw89_mac_mem_base_addrs_be,
3273 .mem_page_size = MAC_MEM_DUMP_PAGE_SIZE_BE,
3274 .rx_fltr = R_BE_RX_FLTR_OPT,
3275 .default_rx_fltr = DEFAULT_BE_RX_FLTR,
3276 .port_base = &rtw89_port_base_be,
3277 .agg_len_ht = R_BE_AGG_LEN_HT_0,
3278 .ps_status = R_BE_WMTX_POWER_BE_BIT_CTL,
3279 .mu_gid = &rtw89_mac_mu_gid_addr_be,
3280 .boot_dbg = R_BE_BOOT_DBG,
3281
3282 .muedca_ctrl = {
3283 .addr = R_BE_MUEDCA_EN,
3284 .mask = B_BE_MUEDCA_EN_0 | B_BE_SET_MUEDCATIMER_TF_0,
3285 },
3286 .bfee_ctrl = {
3287 .addr = R_BE_BFMEE_RESP_OPTION,
3288 .mask = B_BE_BFMEE_HT_NDPA_EN | B_BE_BFMEE_VHT_NDPA_EN |
3289 B_BE_BFMEE_HE_NDPA_EN | B_BE_BFMEE_EHT_NDPA_EN,
3290 },
3291 .narrow_bw_ru_dis = {
3292 .addr = R_BE_RXTRIG_TEST_USER_2,
3293 .mask = B_BE_RXTRIG_RU26_DIS,
3294 },
3295 .wow_ctrl = {.addr = R_BE_WOW_CTRL, .mask = B_BE_WOW_WOWEN,},
3296 .agg_limit = {.addr = R_BE_AMPDU_AGG_LIMIT, .mask = B_BE_AMPDU_MAX_TIME_MASK,},
3297 .ra_agg_limit = {.addr = R_BE_AMPDU_AGG_LIMIT,
3298 .mask = B_BE_RA_TRY_RATE_AGG_LMT_MASK,},
3299 .txcnt_limit = {.addr = R_BE_TXCNT, .mask = B_BE_L_TXCNT_LMT_MASK,},
3300
3301 .check_mac_en = rtw89_mac_check_mac_en_be,
3302 .sys_init = sys_init_be,
3303 .trx_init = trx_init_be,
3304 .preload_init = preload_init_be,
3305 .clr_aon_intr = clr_aon_intr_be,
3306 .err_imr_ctrl = err_imr_ctrl_be,
3307 .mac_func_en = mac_func_en_be,
3308 .hci_func_en = rtw89_mac_hci_func_en_be,
3309 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_be,
3310 .dle_func_en = dle_func_en_be,
3311 .dle_clk_en = dle_clk_en_be,
3312 .bf_assoc = rtw89_mac_bf_assoc_be,
3313
3314 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_be,
3315 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_be,
3316 .cfg_phy_rpt = rtw89_mac_cfg_phy_rpt_be,
3317 .set_edcca_mode = rtw89_mac_set_edcca_mode_be,
3318 .set_vcore_cfg = rtw89_mac_set_vcore_cfg_be,
3319
3320 .dle_mix_cfg = dle_mix_cfg_be,
3321 .chk_dle_rdy = chk_dle_rdy_be,
3322 .dle_buf_req = dle_buf_req_be,
3323 .hfc_func_en = hfc_func_en_be,
3324 .hfc_h2c_cfg = hfc_h2c_cfg_be,
3325 .hfc_mix_cfg = hfc_mix_cfg_be,
3326 .hfc_get_mix_info = hfc_get_mix_info_be,
3327 .wde_quota_cfg = wde_quota_cfg_be,
3328 .ple_quota_cfg = ple_quota_cfg_be,
3329 .set_cpuio = set_cpuio_be,
3330 .dle_quota_change = dle_quota_change_be,
3331
3332 .reset_pwr_state = rtw89_mac_reset_pwr_state_be,
3333 .disable_cpu = rtw89_mac_disable_cpu_be,
3334 .fwdl_preconfig = rtw89_mac_fwdl_preconfig_be,
3335 .fwdl_enable_wcpu = rtw89_mac_fwdl_enable_wcpu_be,
3336 .fwdl_get_status = fwdl_get_status_be,
3337 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_be,
3338 .fwdl_secure_idmem_share_mode = NULL,
3339 .parse_efuse_map = rtw89_parse_efuse_map_be,
3340 .parse_phycap_map = rtw89_parse_phycap_map_be,
3341 .cnv_efuse_state = rtw89_cnv_efuse_state_be,
3342 .efuse_read_fw_secure = rtw89_efuse_read_fw_secure_be,
3343 .efuse_read_ecv = rtw89_efuse_read_ecv_be,
3344 .efuse_read_thermal_k = rtw89_efuse_read_thermal_k_be,
3345 .efuse_read_pwr_data = rtw89_efuse_read_pwr_data_be,
3346
3347 .cfg_plt = rtw89_mac_cfg_plt_be,
3348 .get_plt_cnt = rtw89_mac_get_plt_cnt_be,
3349
3350 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_be,
3351
3352 .write_xtal_si = rtw89_mac_write_xtal_si_be,
3353 .read_xtal_si = rtw89_mac_read_xtal_si_be,
3354
3355 .dump_qta_lost = rtw89_mac_dump_qta_lost_be,
3356 .dump_err_status = rtw89_mac_dump_err_status_be,
3357
3358 .is_txq_empty = mac_is_txq_empty_be,
3359
3360 .prep_chan_list = rtw89_hw_scan_prep_chan_list_be,
3361 .free_chan_list = rtw89_hw_scan_free_chan_list_be,
3362 .add_chan_list = rtw89_hw_scan_add_chan_list_be,
3363 .add_chan_list_pno = rtw89_pno_scan_add_chan_list_be,
3364 .scan_offload = rtw89_fw_h2c_scan_offload_be,
3365
3366 .wow_config_mac = rtw89_wow_config_mac_be,
3367 };
3368 EXPORT_SYMBOL(rtw89_mac_gen_be);
3369