1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4 #include <linux/ip.h>
5 #include <linux/udp.h>
6
7 #include "cam.h"
8 #include "chan.h"
9 #include "coex.h"
10 #include "core.h"
11 #include "efuse.h"
12 #include "fw.h"
13 #include "mac.h"
14 #include "phy.h"
15 #include "ps.h"
16 #include "reg.h"
17 #include "sar.h"
18 #include "ser.h"
19 #include "txrx.h"
20 #include "util.h"
21 #include "wow.h"
22
23 static bool rtw89_disable_ps_mode;
24 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644);
25 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode");
26
27 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \
28 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, }
29 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \
30 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ)
31 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \
32 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ)
33 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \
34 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ)
35 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \
36 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ)
37
38 static struct ieee80211_channel rtw89_channels_2ghz[] = {
39 RTW89_DEF_CHAN_2G(2412, 1),
40 RTW89_DEF_CHAN_2G(2417, 2),
41 RTW89_DEF_CHAN_2G(2422, 3),
42 RTW89_DEF_CHAN_2G(2427, 4),
43 RTW89_DEF_CHAN_2G(2432, 5),
44 RTW89_DEF_CHAN_2G(2437, 6),
45 RTW89_DEF_CHAN_2G(2442, 7),
46 RTW89_DEF_CHAN_2G(2447, 8),
47 RTW89_DEF_CHAN_2G(2452, 9),
48 RTW89_DEF_CHAN_2G(2457, 10),
49 RTW89_DEF_CHAN_2G(2462, 11),
50 RTW89_DEF_CHAN_2G(2467, 12),
51 RTW89_DEF_CHAN_2G(2472, 13),
52 RTW89_DEF_CHAN_2G(2484, 14),
53 };
54
55 static struct ieee80211_channel rtw89_channels_5ghz[] = {
56 RTW89_DEF_CHAN_5G(5180, 36),
57 RTW89_DEF_CHAN_5G(5200, 40),
58 RTW89_DEF_CHAN_5G(5220, 44),
59 RTW89_DEF_CHAN_5G(5240, 48),
60 RTW89_DEF_CHAN_5G(5260, 52),
61 RTW89_DEF_CHAN_5G(5280, 56),
62 RTW89_DEF_CHAN_5G(5300, 60),
63 RTW89_DEF_CHAN_5G(5320, 64),
64 RTW89_DEF_CHAN_5G(5500, 100),
65 RTW89_DEF_CHAN_5G(5520, 104),
66 RTW89_DEF_CHAN_5G(5540, 108),
67 RTW89_DEF_CHAN_5G(5560, 112),
68 RTW89_DEF_CHAN_5G(5580, 116),
69 RTW89_DEF_CHAN_5G(5600, 120),
70 RTW89_DEF_CHAN_5G(5620, 124),
71 RTW89_DEF_CHAN_5G(5640, 128),
72 RTW89_DEF_CHAN_5G(5660, 132),
73 RTW89_DEF_CHAN_5G(5680, 136),
74 RTW89_DEF_CHAN_5G(5700, 140),
75 RTW89_DEF_CHAN_5G(5720, 144),
76 RTW89_DEF_CHAN_5G(5745, 149),
77 RTW89_DEF_CHAN_5G(5765, 153),
78 RTW89_DEF_CHAN_5G(5785, 157),
79 RTW89_DEF_CHAN_5G(5805, 161),
80 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165),
81 RTW89_DEF_CHAN_5G(5845, 169),
82 RTW89_DEF_CHAN_5G(5865, 173),
83 RTW89_DEF_CHAN_5G(5885, 177),
84 };
85
86 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM ==
87 ARRAY_SIZE(rtw89_channels_5ghz));
88
89 static struct ieee80211_channel rtw89_channels_6ghz[] = {
90 RTW89_DEF_CHAN_6G(5955, 1),
91 RTW89_DEF_CHAN_6G(5975, 5),
92 RTW89_DEF_CHAN_6G(5995, 9),
93 RTW89_DEF_CHAN_6G(6015, 13),
94 RTW89_DEF_CHAN_6G(6035, 17),
95 RTW89_DEF_CHAN_6G(6055, 21),
96 RTW89_DEF_CHAN_6G(6075, 25),
97 RTW89_DEF_CHAN_6G(6095, 29),
98 RTW89_DEF_CHAN_6G(6115, 33),
99 RTW89_DEF_CHAN_6G(6135, 37),
100 RTW89_DEF_CHAN_6G(6155, 41),
101 RTW89_DEF_CHAN_6G(6175, 45),
102 RTW89_DEF_CHAN_6G(6195, 49),
103 RTW89_DEF_CHAN_6G(6215, 53),
104 RTW89_DEF_CHAN_6G(6235, 57),
105 RTW89_DEF_CHAN_6G(6255, 61),
106 RTW89_DEF_CHAN_6G(6275, 65),
107 RTW89_DEF_CHAN_6G(6295, 69),
108 RTW89_DEF_CHAN_6G(6315, 73),
109 RTW89_DEF_CHAN_6G(6335, 77),
110 RTW89_DEF_CHAN_6G(6355, 81),
111 RTW89_DEF_CHAN_6G(6375, 85),
112 RTW89_DEF_CHAN_6G(6395, 89),
113 RTW89_DEF_CHAN_6G(6415, 93),
114 RTW89_DEF_CHAN_6G(6435, 97),
115 RTW89_DEF_CHAN_6G(6455, 101),
116 RTW89_DEF_CHAN_6G(6475, 105),
117 RTW89_DEF_CHAN_6G(6495, 109),
118 RTW89_DEF_CHAN_6G(6515, 113),
119 RTW89_DEF_CHAN_6G(6535, 117),
120 RTW89_DEF_CHAN_6G(6555, 121),
121 RTW89_DEF_CHAN_6G(6575, 125),
122 RTW89_DEF_CHAN_6G(6595, 129),
123 RTW89_DEF_CHAN_6G(6615, 133),
124 RTW89_DEF_CHAN_6G(6635, 137),
125 RTW89_DEF_CHAN_6G(6655, 141),
126 RTW89_DEF_CHAN_6G(6675, 145),
127 RTW89_DEF_CHAN_6G(6695, 149),
128 RTW89_DEF_CHAN_6G(6715, 153),
129 RTW89_DEF_CHAN_6G(6735, 157),
130 RTW89_DEF_CHAN_6G(6755, 161),
131 RTW89_DEF_CHAN_6G(6775, 165),
132 RTW89_DEF_CHAN_6G(6795, 169),
133 RTW89_DEF_CHAN_6G(6815, 173),
134 RTW89_DEF_CHAN_6G(6835, 177),
135 RTW89_DEF_CHAN_6G(6855, 181),
136 RTW89_DEF_CHAN_6G(6875, 185),
137 RTW89_DEF_CHAN_6G(6895, 189),
138 RTW89_DEF_CHAN_6G(6915, 193),
139 RTW89_DEF_CHAN_6G(6935, 197),
140 RTW89_DEF_CHAN_6G(6955, 201),
141 RTW89_DEF_CHAN_6G(6975, 205),
142 RTW89_DEF_CHAN_6G(6995, 209),
143 RTW89_DEF_CHAN_6G(7015, 213),
144 RTW89_DEF_CHAN_6G(7035, 217),
145 RTW89_DEF_CHAN_6G(7055, 221),
146 RTW89_DEF_CHAN_6G(7075, 225),
147 RTW89_DEF_CHAN_6G(7095, 229),
148 RTW89_DEF_CHAN_6G(7115, 233),
149 };
150
151 static struct ieee80211_rate rtw89_bitrates[] = {
152 { .bitrate = 10, .hw_value = 0x00, },
153 { .bitrate = 20, .hw_value = 0x01, },
154 { .bitrate = 55, .hw_value = 0x02, },
155 { .bitrate = 110, .hw_value = 0x03, },
156 { .bitrate = 60, .hw_value = 0x04, },
157 { .bitrate = 90, .hw_value = 0x05, },
158 { .bitrate = 120, .hw_value = 0x06, },
159 { .bitrate = 180, .hw_value = 0x07, },
160 { .bitrate = 240, .hw_value = 0x08, },
161 { .bitrate = 360, .hw_value = 0x09, },
162 { .bitrate = 480, .hw_value = 0x0a, },
163 { .bitrate = 540, .hw_value = 0x0b, },
164 };
165
166 static const struct ieee80211_iface_limit rtw89_iface_limits[] = {
167 {
168 .max = 1,
169 .types = BIT(NL80211_IFTYPE_STATION),
170 },
171 {
172 .max = 1,
173 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
174 BIT(NL80211_IFTYPE_P2P_GO) |
175 BIT(NL80211_IFTYPE_AP),
176 },
177 };
178
179 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = {
180 {
181 .max = 1,
182 .types = BIT(NL80211_IFTYPE_STATION),
183 },
184 {
185 .max = 1,
186 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
187 BIT(NL80211_IFTYPE_P2P_GO),
188 },
189 };
190
191 static const struct ieee80211_iface_combination rtw89_iface_combs[] = {
192 {
193 .limits = rtw89_iface_limits,
194 .n_limits = ARRAY_SIZE(rtw89_iface_limits),
195 .max_interfaces = RTW89_MAX_INTERFACE_NUM,
196 .num_different_channels = 1,
197 },
198 {
199 .limits = rtw89_iface_limits_mcc,
200 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc),
201 .max_interfaces = RTW89_MAX_INTERFACE_NUM,
202 .num_different_channels = 2,
203 },
204 };
205
rtw89_ra_report_to_bitrate(struct rtw89_dev * rtwdev,u8 rpt_rate,u16 * bitrate)206 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate)
207 {
208 struct ieee80211_rate rate;
209
210 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) {
211 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate);
212 return false;
213 }
214
215 rate = rtw89_bitrates[rpt_rate];
216 *bitrate = rate.bitrate;
217
218 return true;
219 }
220
221 static const struct ieee80211_supported_band rtw89_sband_2ghz = {
222 .band = NL80211_BAND_2GHZ,
223 .channels = rtw89_channels_2ghz,
224 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz),
225 .bitrates = rtw89_bitrates,
226 .n_bitrates = ARRAY_SIZE(rtw89_bitrates),
227 .ht_cap = {0},
228 .vht_cap = {0},
229 };
230
231 static const struct ieee80211_supported_band rtw89_sband_5ghz = {
232 .band = NL80211_BAND_5GHZ,
233 .channels = rtw89_channels_5ghz,
234 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz),
235
236 /* 5G has no CCK rates, 1M/2M/5.5M/11M */
237 .bitrates = rtw89_bitrates + 4,
238 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
239 .ht_cap = {0},
240 .vht_cap = {0},
241 };
242
243 static const struct ieee80211_supported_band rtw89_sband_6ghz = {
244 .band = NL80211_BAND_6GHZ,
245 .channels = rtw89_channels_6ghz,
246 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz),
247
248 /* 6G has no CCK rates, 1M/2M/5.5M/11M */
249 .bitrates = rtw89_bitrates + 4,
250 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
251 };
252
rtw89_traffic_stats_accu(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats,struct sk_buff * skb,bool tx)253 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev,
254 struct rtw89_traffic_stats *stats,
255 struct sk_buff *skb, bool tx)
256 {
257 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
258
259 if (tx && ieee80211_is_assoc_req(hdr->frame_control))
260 rtw89_wow_parse_akm(rtwdev, skb);
261
262 if (!ieee80211_is_data(hdr->frame_control))
263 return;
264
265 if (is_broadcast_ether_addr(hdr->addr1) ||
266 is_multicast_ether_addr(hdr->addr1))
267 return;
268
269 if (tx) {
270 stats->tx_cnt++;
271 stats->tx_unicast += skb->len;
272 } else {
273 stats->rx_cnt++;
274 stats->rx_unicast += skb->len;
275 }
276 }
277
rtw89_get_default_chandef(struct cfg80211_chan_def * chandef)278 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef)
279 {
280 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0],
281 NL80211_CHAN_NO_HT);
282 }
283
rtw89_get_channel_params(const struct cfg80211_chan_def * chandef,struct rtw89_chan * chan)284 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
285 struct rtw89_chan *chan)
286 {
287 struct ieee80211_channel *channel = chandef->chan;
288 enum nl80211_chan_width width = chandef->width;
289 u32 primary_freq, center_freq;
290 u8 center_chan;
291 u8 bandwidth = RTW89_CHANNEL_WIDTH_20;
292 u32 offset;
293 u8 band;
294
295 center_chan = channel->hw_value;
296 primary_freq = channel->center_freq;
297 center_freq = chandef->center_freq1;
298
299 switch (width) {
300 case NL80211_CHAN_WIDTH_20_NOHT:
301 case NL80211_CHAN_WIDTH_20:
302 bandwidth = RTW89_CHANNEL_WIDTH_20;
303 break;
304 case NL80211_CHAN_WIDTH_40:
305 bandwidth = RTW89_CHANNEL_WIDTH_40;
306 if (primary_freq > center_freq) {
307 center_chan -= 2;
308 } else {
309 center_chan += 2;
310 }
311 break;
312 case NL80211_CHAN_WIDTH_80:
313 case NL80211_CHAN_WIDTH_160:
314 bandwidth = nl_to_rtw89_bandwidth(width);
315 if (primary_freq > center_freq) {
316 offset = (primary_freq - center_freq - 10) / 20;
317 center_chan -= 2 + offset * 4;
318 } else {
319 offset = (center_freq - primary_freq - 10) / 20;
320 center_chan += 2 + offset * 4;
321 }
322 break;
323 default:
324 center_chan = 0;
325 break;
326 }
327
328 switch (channel->band) {
329 default:
330 case NL80211_BAND_2GHZ:
331 band = RTW89_BAND_2G;
332 break;
333 case NL80211_BAND_5GHZ:
334 band = RTW89_BAND_5G;
335 break;
336 case NL80211_BAND_6GHZ:
337 band = RTW89_BAND_6G;
338 break;
339 }
340
341 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth);
342 }
343
__rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)344 static void __rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev,
345 const struct rtw89_chan *chan,
346 enum rtw89_phy_idx phy_idx)
347 {
348 const struct rtw89_chip_info *chip = rtwdev->chip;
349 bool entity_active;
350
351 entity_active = rtw89_get_entity_state(rtwdev, phy_idx);
352 if (!entity_active)
353 return;
354
355 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
356 }
357
rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev)358 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev)
359 {
360 const struct rtw89_chan *chan;
361
362 chan = rtw89_mgnt_chan_get(rtwdev, 0);
363 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_0);
364
365 if (!rtwdev->support_mlo)
366 return;
367
368 chan = rtw89_mgnt_chan_get(rtwdev, 1);
369 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_1);
370 }
371
__rtw89_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)372 static void __rtw89_set_channel(struct rtw89_dev *rtwdev,
373 const struct rtw89_chan *chan,
374 enum rtw89_mac_idx mac_idx,
375 enum rtw89_phy_idx phy_idx)
376 {
377 const struct rtw89_chip_info *chip = rtwdev->chip;
378 const struct rtw89_chan_rcd *chan_rcd;
379 struct rtw89_channel_help_params bak;
380 bool entity_active;
381
382 entity_active = rtw89_get_entity_state(rtwdev, phy_idx);
383
384 chan_rcd = rtw89_chan_rcd_get_by_chan(chan);
385
386 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx);
387
388 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx);
389
390 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
391
392 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx);
393
394 if (!entity_active || chan_rcd->band_changed) {
395 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type);
396 rtw89_chip_rfk_band_changed(rtwdev, phy_idx, chan);
397 }
398
399 rtw89_set_entity_state(rtwdev, phy_idx, true);
400 }
401
rtw89_set_channel(struct rtw89_dev * rtwdev)402 int rtw89_set_channel(struct rtw89_dev *rtwdev)
403 {
404 const struct rtw89_chan *chan;
405 enum rtw89_entity_mode mode;
406
407 mode = rtw89_entity_recalc(rtwdev);
408 if (mode < 0 || mode >= NUM_OF_RTW89_ENTITY_MODE) {
409 WARN(1, "Invalid ent mode: %d\n", mode);
410 return -EINVAL;
411 }
412
413 chan = rtw89_mgnt_chan_get(rtwdev, 0);
414 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_0, RTW89_PHY_0);
415
416 if (!rtwdev->support_mlo)
417 return 0;
418
419 chan = rtw89_mgnt_chan_get(rtwdev, 1);
420 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_1, RTW89_PHY_1);
421
422 return 0;
423 }
424
425 static enum rtw89_core_tx_type
rtw89_core_get_tx_type(struct rtw89_dev * rtwdev,struct sk_buff * skb)426 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev,
427 struct sk_buff *skb)
428 {
429 struct ieee80211_hdr *hdr = (void *)skb->data;
430 __le16 fc = hdr->frame_control;
431
432 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc))
433 return RTW89_CORE_TX_TYPE_MGMT;
434
435 return RTW89_CORE_TX_TYPE_DATA;
436 }
437
438 static void
rtw89_core_tx_update_ampdu_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)439 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev,
440 struct rtw89_core_tx_request *tx_req,
441 enum btc_pkt_type pkt_type)
442 {
443 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
444 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
445 struct ieee80211_link_sta *link_sta;
446 struct sk_buff *skb = tx_req->skb;
447 struct rtw89_sta *rtwsta;
448 u8 ampdu_num;
449 u8 tid;
450
451 if (pkt_type == PACKET_EAPOL) {
452 desc_info->bk = true;
453 return;
454 }
455
456 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU))
457 return;
458
459 if (!rtwsta_link) {
460 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n");
461 return;
462 }
463
464 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
465 rtwsta = rtwsta_link->rtwsta;
466
467 rcu_read_lock();
468
469 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
470 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ?
471 rtwsta->ampdu_params[tid].agg_num :
472 4 << link_sta->ht_cap.ampdu_factor) - 1);
473
474 desc_info->agg_en = true;
475 desc_info->ampdu_density = link_sta->ht_cap.ampdu_density;
476 desc_info->ampdu_num = ampdu_num;
477
478 rcu_read_unlock();
479 }
480
481 static void
rtw89_core_tx_update_sec_key(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)482 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev,
483 struct rtw89_core_tx_request *tx_req)
484 {
485 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
486 const struct rtw89_chip_info *chip = rtwdev->chip;
487 const struct rtw89_sec_cam_entry *sec_cam;
488 struct ieee80211_tx_info *info;
489 struct ieee80211_key_conf *key;
490 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
491 struct sk_buff *skb = tx_req->skb;
492 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE;
493 u8 sec_cam_idx;
494 u64 pn64;
495
496 info = IEEE80211_SKB_CB(skb);
497 key = info->control.hw_key;
498 sec_cam_idx = key->hw_key_idx;
499 sec_cam = cam_info->sec_entries[sec_cam_idx];
500 if (!sec_cam) {
501 rtw89_warn(rtwdev, "sec cam entry is empty\n");
502 return;
503 }
504
505 switch (key->cipher) {
506 case WLAN_CIPHER_SUITE_WEP40:
507 sec_type = RTW89_SEC_KEY_TYPE_WEP40;
508 break;
509 case WLAN_CIPHER_SUITE_WEP104:
510 sec_type = RTW89_SEC_KEY_TYPE_WEP104;
511 break;
512 case WLAN_CIPHER_SUITE_TKIP:
513 sec_type = RTW89_SEC_KEY_TYPE_TKIP;
514 break;
515 case WLAN_CIPHER_SUITE_CCMP:
516 sec_type = RTW89_SEC_KEY_TYPE_CCMP128;
517 break;
518 case WLAN_CIPHER_SUITE_CCMP_256:
519 sec_type = RTW89_SEC_KEY_TYPE_CCMP256;
520 break;
521 case WLAN_CIPHER_SUITE_GCMP:
522 sec_type = RTW89_SEC_KEY_TYPE_GCMP128;
523 break;
524 case WLAN_CIPHER_SUITE_GCMP_256:
525 sec_type = RTW89_SEC_KEY_TYPE_GCMP256;
526 break;
527 default:
528 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher);
529 return;
530 }
531
532 desc_info->sec_en = true;
533 desc_info->sec_keyid = key->keyidx;
534 desc_info->sec_type = sec_type;
535 desc_info->sec_cam_idx = sec_cam->sec_cam_idx;
536
537 if (!chip->hw_sec_hdr)
538 return;
539
540 pn64 = atomic64_inc_return(&key->tx_pn);
541 desc_info->sec_seq[0] = pn64;
542 desc_info->sec_seq[1] = pn64 >> 8;
543 desc_info->sec_seq[2] = pn64 >> 16;
544 desc_info->sec_seq[3] = pn64 >> 24;
545 desc_info->sec_seq[4] = pn64 >> 32;
546 desc_info->sec_seq[5] = pn64 >> 40;
547 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */
548 }
549
rtw89_core_get_mgmt_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,const struct rtw89_chan * chan)550 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev,
551 struct rtw89_core_tx_request *tx_req,
552 const struct rtw89_chan *chan)
553 {
554 struct sk_buff *skb = tx_req->skb;
555 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
556 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
557 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
558 struct ieee80211_vif *vif = tx_info->control.vif;
559 struct ieee80211_bss_conf *bss_conf;
560 u16 lowest_rate;
561 u16 rate;
562
563 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE ||
564 (vif && vif->p2p))
565 lowest_rate = RTW89_HW_RATE_OFDM6;
566 else if (chan->band_type == RTW89_BAND_2G)
567 lowest_rate = RTW89_HW_RATE_CCK1;
568 else
569 lowest_rate = RTW89_HW_RATE_OFDM6;
570
571 if (!rtwvif_link)
572 return lowest_rate;
573
574 rcu_read_lock();
575
576 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
577 if (!bss_conf->basic_rates || !rtwsta_link) {
578 rate = lowest_rate;
579 goto out;
580 }
581
582 rate = __ffs(bss_conf->basic_rates) + lowest_rate;
583
584 out:
585 rcu_read_unlock();
586
587 return rate;
588 }
589
rtw89_core_tx_get_mac_id(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)590 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev,
591 struct rtw89_core_tx_request *tx_req)
592 {
593 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
594 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
595
596 if (!rtwsta_link)
597 return rtwvif_link->mac_id;
598
599 return rtwsta_link->mac_id;
600 }
601
rtw89_core_tx_update_llc_hdr(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,struct sk_buff * skb)602 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev,
603 struct rtw89_tx_desc_info *desc_info,
604 struct sk_buff *skb)
605 {
606 struct ieee80211_hdr *hdr = (void *)skb->data;
607 __le16 fc = hdr->frame_control;
608
609 desc_info->hdr_llc_len = ieee80211_hdrlen(fc);
610 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */
611 }
612
613 static void
rtw89_core_tx_update_mgmt_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)614 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev,
615 struct rtw89_core_tx_request *tx_req)
616 {
617 const struct rtw89_chip_info *chip = rtwdev->chip;
618 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
619 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
620 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
621 rtwvif_link->chanctx_idx);
622 struct sk_buff *skb = tx_req->skb;
623 u8 qsel, ch_dma;
624
625 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT;
626 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
627
628 desc_info->qsel = qsel;
629 desc_info->ch_dma = ch_dma;
630 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
631 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
632 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL;
633 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE;
634
635 /* fixed data rate for mgmt frames */
636 desc_info->en_wd_info = true;
637 desc_info->use_rate = true;
638 desc_info->dis_data_fb = true;
639 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan);
640
641 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) {
642 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
643 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
644 }
645
646 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
647 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n",
648 desc_info->data_rate, chan->channel, chan->band_type,
649 chan->band_width);
650 }
651
652 static void
rtw89_core_tx_update_h2c_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)653 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev,
654 struct rtw89_core_tx_request *tx_req)
655 {
656 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
657
658 desc_info->is_bmc = false;
659 desc_info->wd_page = false;
660 desc_info->ch_dma = RTW89_DMA_H2C;
661 }
662
rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev * rtwdev,__le32 * htc,const struct rtw89_chan * chan)663 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc,
664 const struct rtw89_chan *chan)
665 {
666 static const u8 rtw89_bandwidth_to_om[] = {
667 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20,
668 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40,
669 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80,
670 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
671 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
672 };
673 const struct rtw89_chip_info *chip = rtwdev->chip;
674 struct rtw89_hal *hal = &rtwdev->hal;
675 u8 om_bandwidth;
676
677 if (!chip->dis_2g_40m_ul_ofdma ||
678 chan->band_type != RTW89_BAND_2G ||
679 chan->band_width != RTW89_CHANNEL_WIDTH_40)
680 return;
681
682 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ?
683 rtw89_bandwidth_to_om[chan->band_width] : 0;
684 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
685 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) |
686 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) |
687 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) |
688 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) |
689 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) |
690 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) |
691 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) |
692 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS);
693 }
694
695 static bool
__rtw89_core_tx_check_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)696 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev,
697 struct rtw89_core_tx_request *tx_req,
698 enum btc_pkt_type pkt_type)
699 {
700 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
701 struct sk_buff *skb = tx_req->skb;
702 struct ieee80211_hdr *hdr = (void *)skb->data;
703 struct ieee80211_link_sta *link_sta;
704 __le16 fc = hdr->frame_control;
705
706 /* AP IOT issue with EAPoL, ARP and DHCP */
707 if (pkt_type < PACKET_MAX)
708 return false;
709
710 if (!rtwsta_link)
711 return false;
712
713 rcu_read_lock();
714
715 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
716 if (!link_sta->he_cap.has_he) {
717 rcu_read_unlock();
718 return false;
719 }
720
721 rcu_read_unlock();
722
723 if (!ieee80211_is_data_qos(fc))
724 return false;
725
726 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN)
727 return false;
728
729 if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy)
730 return false;
731
732 return true;
733 }
734
735 static void
__rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)736 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev,
737 struct rtw89_core_tx_request *tx_req)
738 {
739 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
740 struct sk_buff *skb = tx_req->skb;
741 struct ieee80211_hdr *hdr = (void *)skb->data;
742 __le16 fc = hdr->frame_control;
743 void *data;
744 __le32 *htc;
745 u8 *qc;
746 int hdr_len;
747
748 hdr_len = ieee80211_has_a4(fc) ? 32 : 26;
749 data = skb_push(skb, IEEE80211_HT_CTL_LEN);
750 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len);
751
752 hdr = data;
753 htc = data + hdr_len;
754 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER);
755 *htc = rtwsta_link->htc_template ? rtwsta_link->htc_template :
756 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
757 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID);
758
759 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN;
760 qc[0] |= IEEE80211_QOS_CTL_EOSP;
761 }
762
763 static void
rtw89_core_tx_update_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)764 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev,
765 struct rtw89_core_tx_request *tx_req,
766 enum btc_pkt_type pkt_type)
767 {
768 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
769 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
770
771 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type))
772 goto desc_bk;
773
774 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req);
775
776 desc_info->pkt_size += IEEE80211_HT_CTL_LEN;
777 desc_info->a_ctrl_bsr = true;
778
779 desc_bk:
780 if (!rtwvif_link || rtwvif_link->last_a_ctrl == desc_info->a_ctrl_bsr)
781 return;
782
783 rtwvif_link->last_a_ctrl = desc_info->a_ctrl_bsr;
784 desc_info->bk = true;
785 }
786
rtw89_core_get_data_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)787 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev,
788 struct rtw89_core_tx_request *tx_req)
789 {
790 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
791 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
792 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
793 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern;
794 enum rtw89_chanctx_idx idx = rtwvif_link->chanctx_idx;
795 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx);
796 struct ieee80211_link_sta *link_sta;
797 u16 lowest_rate;
798 u16 rate;
799
800 if (rate_pattern->enable)
801 return rate_pattern->rate;
802
803 if (vif->p2p)
804 lowest_rate = RTW89_HW_RATE_OFDM6;
805 else if (chan->band_type == RTW89_BAND_2G)
806 lowest_rate = RTW89_HW_RATE_CCK1;
807 else
808 lowest_rate = RTW89_HW_RATE_OFDM6;
809
810 if (!rtwsta_link)
811 return lowest_rate;
812
813 rcu_read_lock();
814
815 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
816 if (!link_sta->supp_rates[chan->band_type]) {
817 rate = lowest_rate;
818 goto out;
819 }
820
821 rate = __ffs(link_sta->supp_rates[chan->band_type]) + lowest_rate;
822
823 out:
824 rcu_read_unlock();
825
826 return rate;
827 }
828
829 static void
rtw89_core_tx_update_data_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)830 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev,
831 struct rtw89_core_tx_request *tx_req)
832 {
833 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
834 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
835 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
836 struct sk_buff *skb = tx_req->skb;
837 u8 tid, tid_indicate;
838 u8 qsel, ch_dma;
839
840 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
841 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid);
842 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid);
843 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
844
845 desc_info->ch_dma = ch_dma;
846 desc_info->tid_indicate = tid_indicate;
847 desc_info->qsel = qsel;
848 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
849 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
850 desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false;
851 desc_info->stbc = rtwsta_link ? rtwsta_link->ra.stbc_cap : false;
852 desc_info->ldpc = rtwsta_link ? rtwsta_link->ra.ldpc_cap : false;
853
854 /* enable wd_info for AMPDU */
855 desc_info->en_wd_info = true;
856
857 if (IEEE80211_SKB_CB(skb)->control.hw_key)
858 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
859
860 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req);
861 }
862
863 static enum btc_pkt_type
rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)864 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev,
865 struct rtw89_core_tx_request *tx_req)
866 {
867 struct sk_buff *skb = tx_req->skb;
868 struct udphdr *udphdr;
869
870 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) {
871 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work);
872 return PACKET_EAPOL;
873 }
874
875 if (skb->protocol == htons(ETH_P_ARP)) {
876 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work);
877 return PACKET_ARP;
878 }
879
880 if (skb->protocol == htons(ETH_P_IP) &&
881 ip_hdr(skb)->protocol == IPPROTO_UDP) {
882 udphdr = udp_hdr(skb);
883 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) ||
884 (udphdr->source == htons(68) && udphdr->dest == htons(67))) &&
885 skb->len > 282) {
886 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work);
887 return PACKET_DHCP;
888 }
889 }
890
891 if (skb->protocol == htons(ETH_P_IP) &&
892 ip_hdr(skb)->protocol == IPPROTO_ICMP) {
893 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work);
894 return PACKET_ICMP;
895 }
896
897 return PACKET_MAX;
898 }
899
900 static void
rtw89_core_tx_wake(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)901 rtw89_core_tx_wake(struct rtw89_dev *rtwdev,
902 struct rtw89_core_tx_request *tx_req)
903 {
904 const struct rtw89_chip_info *chip = rtwdev->chip;
905
906 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw))
907 return;
908
909 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags))
910 return;
911
912 if (chip->chip_id != RTL8852C &&
913 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT)
914 return;
915
916 rtw89_mac_notify_wake(rtwdev);
917 }
918
919 static void
rtw89_core_tx_update_desc_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)920 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev,
921 struct rtw89_core_tx_request *tx_req)
922 {
923 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
924 struct sk_buff *skb = tx_req->skb;
925 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
926 struct ieee80211_hdr *hdr = (void *)skb->data;
927 struct rtw89_addr_cam_entry *addr_cam;
928 enum rtw89_core_tx_type tx_type;
929 enum btc_pkt_type pkt_type;
930 bool upd_wlan_hdr = false;
931 bool is_bmc;
932 u16 seq;
933
934 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
935 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) {
936 tx_type = rtw89_core_get_tx_type(rtwdev, skb);
937 tx_req->tx_type = tx_type;
938
939 addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link,
940 tx_req->rtwsta_link);
941 if (addr_cam->valid)
942 upd_wlan_hdr = true;
943 }
944 is_bmc = (is_broadcast_ether_addr(hdr->addr1) ||
945 is_multicast_ether_addr(hdr->addr1));
946
947 desc_info->seq = seq;
948 desc_info->pkt_size = skb->len;
949 desc_info->is_bmc = is_bmc;
950 desc_info->wd_page = true;
951 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM;
952 desc_info->upd_wlan_hdr = upd_wlan_hdr;
953
954 switch (tx_req->tx_type) {
955 case RTW89_CORE_TX_TYPE_MGMT:
956 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req);
957 break;
958 case RTW89_CORE_TX_TYPE_DATA:
959 rtw89_core_tx_update_data_info(rtwdev, tx_req);
960 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req);
961 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type);
962 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type);
963 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
964 break;
965 case RTW89_CORE_TX_TYPE_FWCMD:
966 rtw89_core_tx_update_h2c_info(rtwdev, tx_req);
967 break;
968 }
969 }
970
rtw89_core_tx_kick_off(struct rtw89_dev * rtwdev,u8 qsel)971 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel)
972 {
973 u8 ch_dma;
974
975 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
976
977 rtw89_hci_tx_kick_off(rtwdev, ch_dma);
978 }
979
rtw89_core_tx_kick_off_and_wait(struct rtw89_dev * rtwdev,struct sk_buff * skb,int qsel,unsigned int timeout)980 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
981 int qsel, unsigned int timeout)
982 {
983 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
984 struct rtw89_tx_wait_info *wait;
985 unsigned long time_left;
986 int ret = 0;
987
988 wait = kzalloc(sizeof(*wait), GFP_KERNEL);
989 if (!wait) {
990 rtw89_core_tx_kick_off(rtwdev, qsel);
991 return 0;
992 }
993
994 init_completion(&wait->completion);
995 rcu_assign_pointer(skb_data->wait, wait);
996
997 rtw89_core_tx_kick_off(rtwdev, qsel);
998 time_left = wait_for_completion_timeout(&wait->completion,
999 msecs_to_jiffies(timeout));
1000 if (time_left == 0)
1001 ret = -ETIMEDOUT;
1002 else if (!wait->tx_done)
1003 ret = -EAGAIN;
1004
1005 rcu_assign_pointer(skb_data->wait, NULL);
1006 kfree_rcu(wait, rcu_head);
1007
1008 return ret;
1009 }
1010
rtw89_h2c_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb,bool fwdl)1011 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
1012 struct sk_buff *skb, bool fwdl)
1013 {
1014 struct rtw89_core_tx_request tx_req = {0};
1015 u32 cnt;
1016 int ret;
1017
1018 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) {
1019 rtw89_debug(rtwdev, RTW89_DBG_FW,
1020 "ignore h2c due to power is off with firmware state=%d\n",
1021 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags));
1022 dev_kfree_skb(skb);
1023 return 0;
1024 }
1025
1026 tx_req.skb = skb;
1027 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD;
1028 if (fwdl)
1029 tx_req.desc_info.fw_dl = true;
1030
1031 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1032
1033 if (!fwdl)
1034 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len);
1035
1036 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12);
1037 if (cnt == 0) {
1038 rtw89_err(rtwdev, "no tx fwcmd resource\n");
1039 return -ENOSPC;
1040 }
1041
1042 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1043 if (ret) {
1044 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1045 return ret;
1046 }
1047 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12);
1048
1049 return 0;
1050 }
1051
rtw89_core_tx_write(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct sk_buff * skb,int * qsel)1052 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1053 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel)
1054 {
1055 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
1056 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
1057 struct rtw89_core_tx_request tx_req = {0};
1058 struct rtw89_sta_link *rtwsta_link = NULL;
1059 struct rtw89_vif_link *rtwvif_link;
1060 int ret;
1061
1062 /* By default, driver writes tx via the link on HW-0. And then,
1063 * according to links' status, HW can change tx to another link.
1064 */
1065
1066 if (rtwsta) {
1067 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
1068 if (unlikely(!rtwsta_link)) {
1069 rtw89_err(rtwdev, "tx: find no sta link on HW-0\n");
1070 return -ENOLINK;
1071 }
1072 }
1073
1074 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, 0);
1075 if (unlikely(!rtwvif_link)) {
1076 rtw89_err(rtwdev, "tx: find no vif link on HW-0\n");
1077 return -ENOLINK;
1078 }
1079
1080 tx_req.skb = skb;
1081 tx_req.rtwvif_link = rtwvif_link;
1082 tx_req.rtwsta_link = rtwsta_link;
1083
1084 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true);
1085 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true);
1086 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1087 rtw89_core_tx_wake(rtwdev, &tx_req);
1088
1089 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1090 if (ret) {
1091 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1092 return ret;
1093 }
1094
1095 if (qsel)
1096 *qsel = tx_req.desc_info.qsel;
1097
1098 return 0;
1099 }
1100
rtw89_build_txwd_body0(struct rtw89_tx_desc_info * desc_info)1101 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info)
1102 {
1103 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) |
1104 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1105 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1106 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1107 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1108 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) |
1109 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) |
1110 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode);
1111
1112 return cpu_to_le32(dword);
1113 }
1114
rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info * desc_info)1115 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info)
1116 {
1117 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1118 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1119 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1120 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1121 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1122 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl);
1123
1124 return cpu_to_le32(dword);
1125 }
1126
rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info * desc_info)1127 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info)
1128 {
1129 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1130 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1131 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type);
1132
1133 return cpu_to_le32(dword);
1134 }
1135
rtw89_build_txwd_body2(struct rtw89_tx_desc_info * desc_info)1136 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info)
1137 {
1138 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) |
1139 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) |
1140 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) |
1141 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id);
1142
1143 return cpu_to_le32(dword);
1144 }
1145
rtw89_build_txwd_body3(struct rtw89_tx_desc_info * desc_info)1146 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info)
1147 {
1148 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) |
1149 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) |
1150 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk);
1151
1152 return cpu_to_le32(dword);
1153 }
1154
rtw89_build_txwd_body4(struct rtw89_tx_desc_info * desc_info)1155 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info)
1156 {
1157 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1158 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1159
1160 return cpu_to_le32(dword);
1161 }
1162
rtw89_build_txwd_body5(struct rtw89_tx_desc_info * desc_info)1163 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info)
1164 {
1165 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1166 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1167 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1168 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1169
1170 return cpu_to_le32(dword);
1171 }
1172
rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info * desc_info)1173 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info)
1174 {
1175 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) |
1176 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate);
1177
1178 return cpu_to_le32(dword);
1179 }
1180
rtw89_build_txwd_info0(struct rtw89_tx_desc_info * desc_info)1181 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info)
1182 {
1183 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) |
1184 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) |
1185 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1186 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1187 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1188 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port);
1189
1190 return cpu_to_le32(dword);
1191 }
1192
rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info * desc_info)1193 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info)
1194 {
1195 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1196 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1197 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1198 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) |
1199 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) |
1200 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0);
1201
1202 return cpu_to_le32(dword);
1203 }
1204
rtw89_build_txwd_info1(struct rtw89_tx_desc_info * desc_info)1205 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info)
1206 {
1207 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) |
1208 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1209 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE,
1210 desc_info->data_retry_lowest_rate);
1211
1212 return cpu_to_le32(dword);
1213 }
1214
rtw89_build_txwd_info2(struct rtw89_tx_desc_info * desc_info)1215 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info)
1216 {
1217 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1218 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) |
1219 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) |
1220 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1221
1222 return cpu_to_le32(dword);
1223 }
1224
rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info * desc_info)1225 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info)
1226 {
1227 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1228 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1229 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1230
1231 return cpu_to_le32(dword);
1232 }
1233
rtw89_build_txwd_info4(struct rtw89_tx_desc_info * desc_info)1234 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info)
1235 {
1236 bool rts_en = !desc_info->is_bmc;
1237 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) |
1238 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1);
1239
1240 return cpu_to_le32(dword);
1241 }
1242
rtw89_core_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1243 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
1244 struct rtw89_tx_desc_info *desc_info,
1245 void *txdesc)
1246 {
1247 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc;
1248 struct rtw89_txwd_info *txwd_info;
1249
1250 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info);
1251 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1252 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1253
1254 if (!desc_info->en_wd_info)
1255 return;
1256
1257 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1258 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info);
1259 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1260 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info);
1261 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1262
1263 }
1264 EXPORT_SYMBOL(rtw89_core_fill_txdesc);
1265
rtw89_core_fill_txdesc_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1266 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
1267 struct rtw89_tx_desc_info *desc_info,
1268 void *txdesc)
1269 {
1270 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc;
1271 struct rtw89_txwd_info *txwd_info;
1272
1273 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info);
1274 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info);
1275 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1276 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1277 if (desc_info->sec_en) {
1278 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info);
1279 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info);
1280 }
1281 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info);
1282
1283 if (!desc_info->en_wd_info)
1284 return;
1285
1286 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1287 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info);
1288 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1289 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info);
1290 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1291 }
1292 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1);
1293
rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info * desc_info)1294 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info)
1295 {
1296 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1297 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) |
1298 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) |
1299 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1300 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page);
1301
1302 return cpu_to_le32(dword);
1303 }
1304
rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info * desc_info)1305 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info)
1306 {
1307 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1308 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1309 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type);
1310
1311 return cpu_to_le32(dword);
1312 }
1313
rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info * desc_info)1314 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info)
1315 {
1316 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) |
1317 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) |
1318 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) |
1319 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) |
1320 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) |
1321 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id);
1322
1323 return cpu_to_le32(dword);
1324 }
1325
rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info * desc_info)1326 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info)
1327 {
1328 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq);
1329
1330 return cpu_to_le32(dword);
1331 }
1332
rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info * desc_info)1333 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info)
1334 {
1335 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1336 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1337
1338 return cpu_to_le32(dword);
1339 }
1340
rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info * desc_info)1341 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info)
1342 {
1343 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1344 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1345 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1346 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1347
1348 return cpu_to_le32(dword);
1349 }
1350
rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info * desc_info)1351 static __le32 rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info *desc_info)
1352 {
1353 u32 dword = FIELD_PREP(BE_TXD_BODY6_UPD_WLAN_HDR, desc_info->upd_wlan_hdr);
1354
1355 return cpu_to_le32(dword);
1356 }
1357
rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info * desc_info)1358 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info)
1359 {
1360 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) |
1361 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) |
1362 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) |
1363 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate);
1364
1365 return cpu_to_le32(dword);
1366 }
1367
rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info * desc_info)1368 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info)
1369 {
1370 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) |
1371 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) |
1372 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1373 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port);
1374
1375 return cpu_to_le32(dword);
1376 }
1377
rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info * desc_info)1378 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info)
1379 {
1380 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) |
1381 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1382 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE,
1383 desc_info->data_retry_lowest_rate);
1384
1385 return cpu_to_le32(dword);
1386 }
1387
rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info * desc_info)1388 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info)
1389 {
1390 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1391 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1392 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1393
1394 return cpu_to_le32(dword);
1395 }
1396
rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info * desc_info)1397 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info)
1398 {
1399 bool rts_en = !desc_info->is_bmc;
1400 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) |
1401 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1);
1402
1403 return cpu_to_le32(dword);
1404 }
1405
rtw89_core_fill_txdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1406 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
1407 struct rtw89_tx_desc_info *desc_info,
1408 void *txdesc)
1409 {
1410 struct rtw89_txwd_body_v2 *txwd_body = txdesc;
1411 struct rtw89_txwd_info_v2 *txwd_info;
1412
1413 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info);
1414 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info);
1415 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info);
1416 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info);
1417 if (desc_info->sec_en) {
1418 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info);
1419 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info);
1420 }
1421 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info);
1422 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info);
1423
1424 if (!desc_info->en_wd_info)
1425 return;
1426
1427 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1);
1428 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info);
1429 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info);
1430 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info);
1431 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info);
1432 }
1433 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2);
1434
rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info * desc_info)1435 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info)
1436 {
1437 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1438 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1439 RTW89_CORE_RX_TYPE_FWDL :
1440 RTW89_CORE_RX_TYPE_H2C);
1441
1442 return cpu_to_le32(dword);
1443 }
1444
rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1445 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
1446 struct rtw89_tx_desc_info *desc_info,
1447 void *txdesc)
1448 {
1449 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc;
1450
1451 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info);
1452 }
1453 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1);
1454
rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info * desc_info)1455 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info)
1456 {
1457 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1458 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1459 RTW89_CORE_RX_TYPE_FWDL :
1460 RTW89_CORE_RX_TYPE_H2C);
1461
1462 return cpu_to_le32(dword);
1463 }
1464
rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1465 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
1466 struct rtw89_tx_desc_info *desc_info,
1467 void *txdesc)
1468 {
1469 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc;
1470
1471 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info);
1472 }
1473 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2);
1474
rtw89_core_rx_process_mac_ppdu(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_rx_phy_ppdu * phy_ppdu)1475 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev,
1476 struct sk_buff *skb,
1477 struct rtw89_rx_phy_ppdu *phy_ppdu)
1478 {
1479 const struct rtw89_chip_info *chip = rtwdev->chip;
1480 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data;
1481 const struct rtw89_rxinfo_user *user;
1482 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
1483 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE;
1484 bool rx_cnt_valid = false;
1485 bool invalid = false;
1486 u8 plcp_size = 0;
1487 u8 *phy_sts;
1488 u8 usr_num;
1489 int i;
1490
1491 if (chip_gen == RTW89_CHIP_BE) {
1492 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1);
1493 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1;
1494 }
1495
1496 if (invalid)
1497 return -EINVAL;
1498
1499 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD);
1500 if (chip_gen == RTW89_CHIP_BE) {
1501 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3;
1502 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1);
1503 } else {
1504 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3;
1505 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM);
1506 }
1507 if (usr_num > chip->ppdu_max_usr) {
1508 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n",
1509 usr_num);
1510 return -EINVAL;
1511 }
1512
1513 for (i = 0; i < usr_num; i++) {
1514 user = &rxinfo->user[i];
1515 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID))
1516 continue;
1517 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set
1518 * by hardware, so update mac_id by rxinfo_user[].mac_id.
1519 */
1520 if (chip_gen == RTW89_CHIP_BE)
1521 phy_ppdu->mac_id =
1522 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID);
1523 phy_ppdu->has_data =
1524 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA);
1525 phy_ppdu->has_bcn =
1526 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN);
1527 break;
1528 }
1529
1530 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE;
1531 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE;
1532 /* 8-byte alignment */
1533 if (usr_num & BIT(0))
1534 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE;
1535 if (rx_cnt_valid)
1536 phy_sts += rx_cnt_size;
1537 phy_sts += plcp_size;
1538
1539 if (phy_sts > skb->data + skb->len)
1540 return -EINVAL;
1541
1542 phy_ppdu->buf = phy_sts;
1543 phy_ppdu->len = skb->data + skb->len - phy_sts;
1544
1545 return 0;
1546 }
1547
rtw89_get_data_rate_nss(struct rtw89_dev * rtwdev,u16 data_rate)1548 static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate)
1549 {
1550 u8 data_rate_mode;
1551
1552 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
1553 switch (data_rate_mode) {
1554 case DATA_RATE_MODE_NON_HT:
1555 return 1;
1556 case DATA_RATE_MODE_HT:
1557 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1;
1558 case DATA_RATE_MODE_VHT:
1559 case DATA_RATE_MODE_HE:
1560 case DATA_RATE_MODE_EHT:
1561 return rtw89_get_data_nss(rtwdev, data_rate) + 1;
1562 default:
1563 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
1564 return 0;
1565 }
1566 }
1567
rtw89_core_rx_process_phy_ppdu_iter(void * data,struct ieee80211_sta * sta)1568 static void rtw89_core_rx_process_phy_ppdu_iter(void *data,
1569 struct ieee80211_sta *sta)
1570 {
1571 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data;
1572 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
1573 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
1574 struct rtw89_hal *hal = &rtwdev->hal;
1575 struct rtw89_sta_link *rtwsta_link;
1576 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
1577 u8 ant_pos = U8_MAX;
1578 u8 evm_pos = 0;
1579 int i;
1580
1581 /* FIXME: For single link, taking link on HW-0 here is okay. But, when
1582 * enabling multiple active links, we should determine the right link.
1583 */
1584 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
1585 if (unlikely(!rtwsta_link))
1586 return;
1587
1588 if (rtwsta_link->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self)
1589 return;
1590
1591 if (hal->ant_diversity && hal->antenna_rx) {
1592 ant_pos = __ffs(hal->antenna_rx);
1593 evm_pos = ant_pos;
1594 }
1595
1596 ewma_rssi_add(&rtwsta_link->avg_rssi, phy_ppdu->rssi_avg);
1597
1598 if (ant_pos < ant_num) {
1599 ewma_rssi_add(&rtwsta_link->rssi[ant_pos], phy_ppdu->rssi[0]);
1600 } else {
1601 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
1602 ewma_rssi_add(&rtwsta_link->rssi[i], phy_ppdu->rssi[i]);
1603 }
1604
1605 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) {
1606 ewma_snr_add(&rtwsta_link->avg_snr, phy_ppdu->ofdm.avg_snr);
1607 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) {
1608 ewma_evm_add(&rtwsta_link->evm_1ss, phy_ppdu->ofdm.evm_min);
1609 } else {
1610 ewma_evm_add(&rtwsta_link->evm_min[evm_pos],
1611 phy_ppdu->ofdm.evm_min);
1612 ewma_evm_add(&rtwsta_link->evm_max[evm_pos],
1613 phy_ppdu->ofdm.evm_max);
1614 }
1615 }
1616 }
1617
1618 #define VAR_LEN 0xff
1619 #define VAR_LEN_UNIT 8
rtw89_core_get_phy_status_ie_len(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr)1620 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev,
1621 const struct rtw89_phy_sts_iehdr *iehdr)
1622 {
1623 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = {
1624 [RTW89_CHIP_AX] = {
1625 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
1626 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN,
1627 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
1628 },
1629 [RTW89_CHIP_BE] = {
1630 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
1631 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN,
1632 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
1633 },
1634 };
1635 const u8 *physts_ie_len_tab;
1636 u16 ie_len;
1637 u8 ie;
1638
1639 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen];
1640
1641 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
1642 if (physts_ie_len_tab[ie] != VAR_LEN)
1643 ie_len = physts_ie_len_tab[ie];
1644 else
1645 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT;
1646
1647 return ie_len;
1648 }
1649
rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1650 static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev,
1651 const struct rtw89_phy_sts_iehdr *iehdr,
1652 struct rtw89_rx_phy_ppdu *phy_ppdu)
1653 {
1654 const struct rtw89_phy_sts_ie01_v2 *ie;
1655 u8 *rpl_fd = phy_ppdu->rpl_fd;
1656
1657 ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr;
1658 rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A);
1659 rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B);
1660 rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C);
1661 rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D);
1662
1663 phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX);
1664 }
1665
rtw89_core_parse_phy_status_ie01(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1666 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev,
1667 const struct rtw89_phy_sts_iehdr *iehdr,
1668 struct rtw89_rx_phy_ppdu *phy_ppdu)
1669 {
1670 const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr;
1671 s16 cfo;
1672 u32 t;
1673
1674 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX);
1675
1676 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
1677 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC);
1678 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC);
1679 }
1680
1681 if (!phy_ppdu->hdr_2_en)
1682 phy_ppdu->rx_path_en =
1683 le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN);
1684
1685 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6)
1686 return;
1687
1688 if (!phy_ppdu->to_self)
1689 return;
1690
1691 phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD);
1692 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR);
1693 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX);
1694 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN);
1695 phy_ppdu->ofdm.has = true;
1696
1697 /* sign conversion for S(12,2) */
1698 if (rtwdev->chip->cfo_src_fd) {
1699 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO);
1700 cfo = sign_extend32(t, 11);
1701 } else {
1702 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO);
1703 cfo = sign_extend32(t, 11);
1704 }
1705
1706 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu);
1707
1708 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
1709 rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu);
1710 }
1711
rtw89_core_parse_phy_status_ie00(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1712 static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev,
1713 const struct rtw89_phy_sts_iehdr *iehdr,
1714 struct rtw89_rx_phy_ppdu *phy_ppdu)
1715 {
1716 const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr;
1717 u16 tmp_rpl;
1718
1719 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL);
1720 phy_ppdu->rpl_avg = tmp_rpl >> 1;
1721 }
1722
rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1723 static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev,
1724 const struct rtw89_phy_sts_iehdr *iehdr,
1725 struct rtw89_rx_phy_ppdu *phy_ppdu)
1726 {
1727 const struct rtw89_phy_sts_ie00_v2 *ie;
1728 u8 *rpl_path = phy_ppdu->rpl_path;
1729 u16 tmp_rpl[RF_PATH_MAX];
1730 u8 i;
1731
1732 ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr;
1733 tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A);
1734 tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B);
1735 tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C);
1736 tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D);
1737
1738 for (i = 0; i < RF_PATH_MAX; i++)
1739 rpl_path[i] = tmp_rpl[i] >> 1;
1740 }
1741
rtw89_core_process_phy_status_ie(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1742 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev,
1743 const struct rtw89_phy_sts_iehdr *iehdr,
1744 struct rtw89_rx_phy_ppdu *phy_ppdu)
1745 {
1746 u8 ie;
1747
1748 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
1749
1750 switch (ie) {
1751 case RTW89_PHYSTS_IE00_CMN_CCK:
1752 rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu);
1753 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
1754 rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu);
1755 break;
1756 case RTW89_PHYSTS_IE01_CMN_OFDM:
1757 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu);
1758 break;
1759 default:
1760 break;
1761 }
1762
1763 return 0;
1764 }
1765
rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu * phy_ppdu)1766 static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu)
1767 {
1768 const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN;
1769
1770 phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN);
1771 }
1772
rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu * phy_ppdu)1773 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu)
1774 {
1775 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
1776 u8 *rssi = phy_ppdu->rssi;
1777
1778 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP);
1779 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG);
1780 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A);
1781 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B);
1782 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C);
1783 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D);
1784
1785 phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN);
1786 if (phy_ppdu->hdr_2_en)
1787 rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu);
1788 }
1789
rtw89_core_rx_process_phy_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1790 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev,
1791 struct rtw89_rx_phy_ppdu *phy_ppdu)
1792 {
1793 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
1794 u32 len_from_header;
1795 bool physts_valid;
1796
1797 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID);
1798 if (!physts_valid)
1799 return -EINVAL;
1800
1801 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3;
1802
1803 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
1804 len_from_header += PHY_STS_HDR_LEN;
1805
1806 if (len_from_header != phy_ppdu->len) {
1807 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n");
1808 return -EINVAL;
1809 }
1810 rtw89_core_update_phy_ppdu(phy_ppdu);
1811
1812 return 0;
1813 }
1814
rtw89_core_rx_parse_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1815 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev,
1816 struct rtw89_rx_phy_ppdu *phy_ppdu)
1817 {
1818 u16 ie_len;
1819 void *pos, *end;
1820
1821 /* mark invalid reports and bypass them */
1822 if (phy_ppdu->ie < RTW89_CCK_PKT)
1823 return -EINVAL;
1824
1825 pos = phy_ppdu->buf + PHY_STS_HDR_LEN;
1826 end = phy_ppdu->buf + phy_ppdu->len;
1827 while (pos < end) {
1828 const struct rtw89_phy_sts_iehdr *iehdr = pos;
1829
1830 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr);
1831 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu);
1832 pos += ie_len;
1833 if (pos > end || ie_len == 0) {
1834 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
1835 "phy status parse failed\n");
1836 return -EINVAL;
1837 }
1838 }
1839
1840 rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu);
1841 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu);
1842
1843 return 0;
1844 }
1845
rtw89_core_rx_process_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1846 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev,
1847 struct rtw89_rx_phy_ppdu *phy_ppdu)
1848 {
1849 int ret;
1850
1851 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu);
1852 if (ret)
1853 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n");
1854 else
1855 phy_ppdu->valid = true;
1856
1857 ieee80211_iterate_stations_atomic(rtwdev->hw,
1858 rtw89_core_rx_process_phy_ppdu_iter,
1859 phy_ppdu);
1860 }
1861
rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status)1862 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev,
1863 u8 desc_info_gi,
1864 bool rx_status)
1865 {
1866 switch (desc_info_gi) {
1867 case RTW89_GILTF_SGI_4XHE08:
1868 case RTW89_GILTF_2XHE08:
1869 case RTW89_GILTF_1XHE08:
1870 return NL80211_RATE_INFO_HE_GI_0_8;
1871 case RTW89_GILTF_2XHE16:
1872 case RTW89_GILTF_1XHE16:
1873 return NL80211_RATE_INFO_HE_GI_1_6;
1874 case RTW89_GILTF_LGI_4XHE32:
1875 return NL80211_RATE_INFO_HE_GI_3_2;
1876 default:
1877 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi);
1878 if (rx_status)
1879 return NL80211_RATE_INFO_HE_GI_3_2;
1880 return U8_MAX;
1881 }
1882 }
1883
rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status)1884 static u8 rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev *rtwdev,
1885 u8 desc_info_gi,
1886 bool rx_status)
1887 {
1888 switch (desc_info_gi) {
1889 case RTW89_GILTF_SGI_4XHE08:
1890 case RTW89_GILTF_2XHE08:
1891 case RTW89_GILTF_1XHE08:
1892 return NL80211_RATE_INFO_EHT_GI_0_8;
1893 case RTW89_GILTF_2XHE16:
1894 case RTW89_GILTF_1XHE16:
1895 return NL80211_RATE_INFO_EHT_GI_1_6;
1896 case RTW89_GILTF_LGI_4XHE32:
1897 return NL80211_RATE_INFO_EHT_GI_3_2;
1898 default:
1899 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi);
1900 if (rx_status)
1901 return NL80211_RATE_INFO_EHT_GI_3_2;
1902 return U8_MAX;
1903 }
1904 }
1905
rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status,bool eht)1906 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev,
1907 u8 desc_info_gi,
1908 bool rx_status, bool eht)
1909 {
1910 return eht ? rtw89_rxdesc_to_nl_eht_gi(rtwdev, desc_info_gi, rx_status) :
1911 rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info_gi, rx_status);
1912 }
1913
1914 static
rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status * status,u8 gi_ltf,bool eht)1915 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf,
1916 bool eht)
1917 {
1918 if (eht)
1919 return status->eht.gi == gi_ltf;
1920
1921 return status->he_gi == gi_ltf;
1922 }
1923
rtw89_core_rx_ppdu_match(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * status)1924 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev,
1925 struct rtw89_rx_desc_info *desc_info,
1926 struct ieee80211_rx_status *status)
1927 {
1928 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
1929 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf;
1930 bool eht = false;
1931 u16 data_rate;
1932 bool ret;
1933
1934 data_rate = desc_info->data_rate;
1935 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
1936 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
1937 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
1938 /* rate_idx is still hardware value here */
1939 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
1940 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
1941 } else if (data_rate_mode == DATA_RATE_MODE_VHT ||
1942 data_rate_mode == DATA_RATE_MODE_HE ||
1943 data_rate_mode == DATA_RATE_MODE_EHT) {
1944 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
1945 } else {
1946 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
1947 }
1948
1949 eht = data_rate_mode == DATA_RATE_MODE_EHT;
1950 bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
1951 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht);
1952 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt &&
1953 status->rate_idx == rate_idx &&
1954 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) &&
1955 status->bw == bw;
1956
1957 return ret;
1958 }
1959
1960 struct rtw89_vif_rx_stats_iter_data {
1961 struct rtw89_dev *rtwdev;
1962 struct rtw89_rx_phy_ppdu *phy_ppdu;
1963 struct rtw89_rx_desc_info *desc_info;
1964 struct sk_buff *skb;
1965 const u8 *bssid;
1966 };
1967
rtw89_stats_trigger_frame(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct ieee80211_bss_conf * bss_conf,struct sk_buff * skb)1968 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev,
1969 struct rtw89_vif_link *rtwvif_link,
1970 struct ieee80211_bss_conf *bss_conf,
1971 struct sk_buff *skb)
1972 {
1973 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data;
1974 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
1975 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
1976 u8 *pos, *end, type, tf_bw;
1977 u16 aid, tf_rua;
1978
1979 if (!ether_addr_equal(bss_conf->bssid, tf->ta) ||
1980 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION ||
1981 rtwvif_link->net_type == RTW89_NET_TYPE_NO_LINK)
1982 return;
1983
1984 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK);
1985 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR)
1986 return;
1987
1988 end = (u8 *)tf + skb->len;
1989 pos = tf->variable;
1990
1991 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) {
1992 aid = RTW89_GET_TF_USER_INFO_AID12(pos);
1993 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos);
1994 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK);
1995 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
1996 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n",
1997 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos),
1998 tf_rua, tf_bw);
1999
2000 if (aid == RTW89_TF_PAD)
2001 break;
2002
2003 if (aid == vif->cfg.aid) {
2004 enum nl80211_he_ru_alloc rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1);
2005
2006 rtwvif->stats.rx_tf_acc++;
2007 rtwdev->stats.rx_tf_acc++;
2008 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ &&
2009 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106)
2010 rtwvif_link->pwr_diff_en = true;
2011 break;
2012 }
2013
2014 pos += RTW89_TF_BASIC_USER_INFO_SZ;
2015 }
2016 }
2017
rtw89_cancel_6ghz_probe_work(struct work_struct * work)2018 static void rtw89_cancel_6ghz_probe_work(struct work_struct *work)
2019 {
2020 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
2021 cancel_6ghz_probe_work);
2022 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
2023 struct rtw89_pktofld_info *info;
2024
2025 mutex_lock(&rtwdev->mutex);
2026
2027 if (!rtwdev->scanning)
2028 goto out;
2029
2030 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
2031 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload))
2032 continue;
2033
2034 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
2035
2036 /* Don't delete/free info from pkt_list at this moment. Let it
2037 * be deleted/freed in rtw89_release_pkt_list() after scanning,
2038 * since if during scanning, pkt_list is accessed in bottom half.
2039 */
2040 }
2041
2042 out:
2043 mutex_unlock(&rtwdev->mutex);
2044 }
2045
rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb)2046 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev,
2047 struct sk_buff *skb)
2048 {
2049 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
2050 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
2051 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
2052 struct rtw89_pktofld_info *info;
2053 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie;
2054 bool queue_work = false;
2055
2056 if (rx_status->band != NL80211_BAND_6GHZ)
2057 return;
2058
2059 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len);
2060
2061 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
2062 if (ether_addr_equal(info->bssid, mgmt->bssid)) {
2063 info->cancel = true;
2064 queue_work = true;
2065 continue;
2066 }
2067
2068 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0)
2069 continue;
2070
2071 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) {
2072 info->cancel = true;
2073 queue_work = true;
2074 }
2075 }
2076
2077 if (queue_work)
2078 ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work);
2079 }
2080
rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link * rtwvif_link,struct ieee80211_hdr * hdr,size_t len)2081 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link *rtwvif_link,
2082 struct ieee80211_hdr *hdr, size_t len)
2083 {
2084 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr;
2085
2086 if (len < offsetof(typeof(*mgmt), u.beacon.variable))
2087 return;
2088
2089 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp));
2090 }
2091
rtw89_vif_rx_stats_iter(void * data,u8 * mac,struct ieee80211_vif * vif)2092 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac,
2093 struct ieee80211_vif *vif)
2094 {
2095 struct rtw89_vif_rx_stats_iter_data *iter_data = data;
2096 struct rtw89_dev *rtwdev = iter_data->rtwdev;
2097 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
2098 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat;
2099 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
2100 struct sk_buff *skb = iter_data->skb;
2101 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2102 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu;
2103 struct ieee80211_bss_conf *bss_conf;
2104 struct rtw89_vif_link *rtwvif_link;
2105 const u8 *bssid = iter_data->bssid;
2106
2107 if (rtwdev->scanning &&
2108 (ieee80211_is_beacon(hdr->frame_control) ||
2109 ieee80211_is_probe_resp(hdr->frame_control)))
2110 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb);
2111
2112 rcu_read_lock();
2113
2114 /* FIXME: For single link, taking link on HW-0 here is okay. But, when
2115 * enabling multiple active links, we should determine the right link.
2116 */
2117 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, 0);
2118 if (unlikely(!rtwvif_link))
2119 goto out;
2120
2121 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
2122 if (!bss_conf->bssid)
2123 goto out;
2124
2125 if (ieee80211_is_trigger(hdr->frame_control)) {
2126 rtw89_stats_trigger_frame(rtwdev, rtwvif_link, bss_conf, skb);
2127 goto out;
2128 }
2129
2130 if (!ether_addr_equal(bss_conf->bssid, bssid))
2131 goto out;
2132
2133 if (ieee80211_is_beacon(hdr->frame_control)) {
2134 if (vif->type == NL80211_IFTYPE_STATION &&
2135 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) {
2136 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len);
2137 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu);
2138 }
2139 pkt_stat->beacon_nr++;
2140
2141 if (phy_ppdu)
2142 ewma_rssi_add(&rtwdev->phystat.bcn_rssi, phy_ppdu->rssi_avg);
2143 }
2144
2145 if (!ether_addr_equal(bss_conf->addr, hdr->addr1))
2146 goto out;
2147
2148 if (desc_info->data_rate < RTW89_HW_RATE_NR)
2149 pkt_stat->rx_rate_cnt[desc_info->data_rate]++;
2150
2151 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false);
2152
2153 out:
2154 rcu_read_unlock();
2155 }
2156
rtw89_core_rx_stats(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2157 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev,
2158 struct rtw89_rx_phy_ppdu *phy_ppdu,
2159 struct rtw89_rx_desc_info *desc_info,
2160 struct sk_buff *skb)
2161 {
2162 struct rtw89_vif_rx_stats_iter_data iter_data;
2163
2164 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false);
2165
2166 iter_data.rtwdev = rtwdev;
2167 iter_data.phy_ppdu = phy_ppdu;
2168 iter_data.desc_info = desc_info;
2169 iter_data.skb = skb;
2170 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data);
2171 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data);
2172 }
2173
rtw89_correct_cck_chan(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * status)2174 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev,
2175 struct ieee80211_rx_status *status)
2176 {
2177 const struct rtw89_chan_rcd *rcd =
2178 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0);
2179 u16 chan = rcd->prev_primary_channel;
2180 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type);
2181
2182 if (status->band != NL80211_BAND_2GHZ &&
2183 status->encoding == RX_ENC_LEGACY &&
2184 status->rate_idx < RTW89_HW_RATE_OFDM6) {
2185 status->freq = ieee80211_channel_to_frequency(chan, band);
2186 status->band = band;
2187 }
2188 }
2189
rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status * rx_status)2190 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status)
2191 {
2192 if (rx_status->band == NL80211_BAND_2GHZ ||
2193 rx_status->encoding != RX_ENC_LEGACY)
2194 return;
2195
2196 /* Some control frames' freq(ACKs in this case) are reported wrong due
2197 * to FW notify timing, set to lowest rate to prevent overflow.
2198 */
2199 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) {
2200 rx_status->rate_idx = 0;
2201 return;
2202 }
2203
2204 /* No 4 CCK rates for non-2G */
2205 rx_status->rate_idx -= 4;
2206 }
2207
2208 static
rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * rx_status,struct rtw89_rx_phy_ppdu * phy_ppdu)2209 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev,
2210 struct ieee80211_rx_status *rx_status,
2211 struct rtw89_rx_phy_ppdu *phy_ppdu)
2212 {
2213 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
2214 return;
2215
2216 if (!phy_ppdu)
2217 return;
2218
2219 if (phy_ppdu->ldpc)
2220 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
2221 if (phy_ppdu->stbc)
2222 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK);
2223 }
2224
2225 static const u8 rx_status_bw_to_radiotap_eht_usig[] = {
2226 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ,
2227 [RATE_INFO_BW_5] = U8_MAX,
2228 [RATE_INFO_BW_10] = U8_MAX,
2229 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ,
2230 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ,
2231 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ,
2232 [RATE_INFO_BW_HE_RU] = U8_MAX,
2233 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1,
2234 [RATE_INFO_BW_EHT_RU] = U8_MAX,
2235 };
2236
rtw89_core_update_radiotap_eht(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)2237 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev,
2238 struct sk_buff *skb,
2239 struct ieee80211_rx_status *rx_status)
2240 {
2241 struct ieee80211_radiotap_eht_usig *usig;
2242 struct ieee80211_radiotap_eht *eht;
2243 struct ieee80211_radiotap_tlv *tlv;
2244 int eht_len = struct_size(eht, user_info, 1);
2245 int usig_len = sizeof(*usig);
2246 int len;
2247 u8 bw;
2248
2249 len = sizeof(*tlv) + ALIGN(eht_len, 4) +
2250 sizeof(*tlv) + ALIGN(usig_len, 4);
2251
2252 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END;
2253 skb_reset_mac_header(skb);
2254
2255 /* EHT */
2256 tlv = skb_push(skb, len);
2257 memset(tlv, 0, len);
2258 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT);
2259 tlv->len = cpu_to_le16(eht_len);
2260
2261 eht = (struct ieee80211_radiotap_eht *)tlv->data;
2262 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI);
2263 eht->data[0] =
2264 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI);
2265
2266 eht->user_info[0] =
2267 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN |
2268 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O |
2269 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN);
2270 eht->user_info[0] |=
2271 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) |
2272 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O);
2273 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC)
2274 eht->user_info[0] |=
2275 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING);
2276
2277 /* U-SIG */
2278 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4);
2279 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG);
2280 tlv->len = cpu_to_le16(usig_len);
2281
2282 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig))
2283 return;
2284
2285 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw];
2286 if (bw == U8_MAX)
2287 return;
2288
2289 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data;
2290 usig->common =
2291 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) |
2292 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW);
2293 }
2294
rtw89_core_update_radiotap(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)2295 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev,
2296 struct sk_buff *skb,
2297 struct ieee80211_rx_status *rx_status)
2298 {
2299 static const struct ieee80211_radiotap_he known_he = {
2300 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2301 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN |
2302 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN |
2303 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2304 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2305 };
2306 struct ieee80211_radiotap_he *he;
2307
2308 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
2309 return;
2310
2311 if (rx_status->encoding == RX_ENC_HE) {
2312 rx_status->flag |= RX_FLAG_RADIOTAP_HE;
2313 he = skb_push(skb, sizeof(*he));
2314 *he = known_he;
2315 } else if (rx_status->encoding == RX_ENC_EHT) {
2316 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status);
2317 }
2318 }
2319
rtw89_core_rx_to_mac80211(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb_ppdu,struct ieee80211_rx_status * rx_status)2320 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev,
2321 struct rtw89_rx_phy_ppdu *phy_ppdu,
2322 struct rtw89_rx_desc_info *desc_info,
2323 struct sk_buff *skb_ppdu,
2324 struct ieee80211_rx_status *rx_status)
2325 {
2326 struct napi_struct *napi = &rtwdev->napi;
2327
2328 /* In low power mode, napi isn't scheduled. Receive it to netif. */
2329 if (unlikely(!napi_is_scheduled(napi)))
2330 napi = NULL;
2331
2332 rtw89_core_hw_to_sband_rate(rx_status);
2333 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu);
2334 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu);
2335 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status);
2336 /* In low power mode, it does RX in thread context. */
2337 local_bh_disable();
2338 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi);
2339 local_bh_enable();
2340 rtwdev->napi_budget_countdown--;
2341 }
2342
rtw89_core_rx_pending_skb(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2343 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev,
2344 struct rtw89_rx_phy_ppdu *phy_ppdu,
2345 struct rtw89_rx_desc_info *desc_info,
2346 struct sk_buff *skb)
2347 {
2348 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2349 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band];
2350 struct sk_buff *skb_ppdu = NULL, *tmp;
2351 struct ieee80211_rx_status *rx_status;
2352
2353 if (curr > RTW89_MAX_PPDU_CNT)
2354 return;
2355
2356 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) {
2357 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]);
2358 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
2359 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status))
2360 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status);
2361 rtw89_correct_cck_chan(rtwdev, rx_status);
2362 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status);
2363 }
2364 }
2365
rtw89_core_rx_process_ppdu_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2366 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev,
2367 struct rtw89_rx_desc_info *desc_info,
2368 struct sk_buff *skb)
2369 {
2370 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false,
2371 .len = skb->len,
2372 .to_self = desc_info->addr1_match,
2373 .rate = desc_info->data_rate,
2374 .mac_id = desc_info->mac_id};
2375 int ret;
2376
2377 if (desc_info->mac_info_valid) {
2378 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu);
2379 if (ret)
2380 goto out;
2381 }
2382
2383 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu);
2384 if (ret)
2385 goto out;
2386
2387 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu);
2388
2389 out:
2390 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb);
2391 dev_kfree_skb_any(skb);
2392 }
2393
rtw89_core_rx_process_report(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2394 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev,
2395 struct rtw89_rx_desc_info *desc_info,
2396 struct sk_buff *skb)
2397 {
2398 switch (desc_info->pkt_type) {
2399 case RTW89_CORE_RX_TYPE_C2H:
2400 rtw89_fw_c2h_irqsafe(rtwdev, skb);
2401 break;
2402 case RTW89_CORE_RX_TYPE_PPDU_STAT:
2403 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb);
2404 break;
2405 default:
2406 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n",
2407 desc_info->pkt_type);
2408 dev_kfree_skb_any(skb);
2409 break;
2410 }
2411 }
2412
rtw89_core_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)2413 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
2414 struct rtw89_rx_desc_info *desc_info,
2415 u8 *data, u32 data_offset)
2416 {
2417 const struct rtw89_chip_info *chip = rtwdev->chip;
2418 struct rtw89_rxdesc_short *rxd_s;
2419 struct rtw89_rxdesc_long *rxd_l;
2420 u8 shift_len, drv_info_len;
2421
2422 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset);
2423 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK);
2424 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK);
2425 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD);
2426 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK);
2427 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD);
2428 if (chip->chip_id == RTL8852C)
2429 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK);
2430 else
2431 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK);
2432 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK);
2433 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK);
2434 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK);
2435 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN);
2436 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK);
2437 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK);
2438 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK);
2439 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR);
2440 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR);
2441 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC);
2442 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC);
2443 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH);
2444
2445 shift_len = desc_info->shift << 1; /* 2-byte unit */
2446 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
2447 desc_info->offset = data_offset + shift_len + drv_info_len;
2448 if (desc_info->long_rxdesc)
2449 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long);
2450 else
2451 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short);
2452 desc_info->ready = true;
2453
2454 if (!desc_info->long_rxdesc)
2455 return;
2456
2457 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset);
2458 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK);
2459 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD);
2460 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK);
2461 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK);
2462 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK);
2463 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK);
2464 }
2465 EXPORT_SYMBOL(rtw89_core_query_rxdesc);
2466
rtw89_core_query_rxdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)2467 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
2468 struct rtw89_rx_desc_info *desc_info,
2469 u8 *data, u32 data_offset)
2470 {
2471 struct rtw89_rxdesc_short_v2 *rxd_s;
2472 struct rtw89_rxdesc_long_v2 *rxd_l;
2473 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len;
2474
2475 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset);
2476
2477 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK);
2478 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK);
2479 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK);
2480 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK);
2481 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK);
2482 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD);
2483 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK);
2484 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT)
2485 desc_info->mac_info_valid = true;
2486
2487 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK);
2488 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK);
2489 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
2490
2491 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
2492 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
2493 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
2494 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC);
2495 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH);
2496
2497 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK);
2498 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK);
2499 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK);
2500 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK);
2501 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK);
2502
2503 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5);
2504
2505 shift_len = desc_info->shift << 1; /* 2-byte unit */
2506 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
2507 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */
2508 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */
2509 desc_info->offset = data_offset + shift_len + drv_info_len +
2510 phy_rtp_len + hdr_cnv_len;
2511
2512 if (desc_info->long_rxdesc)
2513 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2);
2514 else
2515 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2);
2516 desc_info->ready = true;
2517
2518 if (!desc_info->long_rxdesc)
2519 return;
2520
2521 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset);
2522
2523 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN);
2524 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK);
2525 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK);
2526 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK);
2527
2528 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK);
2529 }
2530 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2);
2531
2532 struct rtw89_core_iter_rx_status {
2533 struct rtw89_dev *rtwdev;
2534 struct ieee80211_rx_status *rx_status;
2535 struct rtw89_rx_desc_info *desc_info;
2536 u8 mac_id;
2537 };
2538
2539 static
rtw89_core_stats_sta_rx_status_iter(void * data,struct ieee80211_sta * sta)2540 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta)
2541 {
2542 struct rtw89_core_iter_rx_status *iter_data =
2543 (struct rtw89_core_iter_rx_status *)data;
2544 struct ieee80211_rx_status *rx_status = iter_data->rx_status;
2545 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
2546 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
2547 struct rtw89_sta_link *rtwsta_link;
2548 u8 mac_id = iter_data->mac_id;
2549
2550 /* FIXME: For single link, taking link on HW-0 here is okay. But, when
2551 * enabling multiple active links, we should determine the right link.
2552 */
2553 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
2554 if (unlikely(!rtwsta_link))
2555 return;
2556
2557 if (mac_id != rtwsta_link->mac_id)
2558 return;
2559
2560 rtwsta_link->rx_status = *rx_status;
2561 rtwsta_link->rx_hw_rate = desc_info->data_rate;
2562 }
2563
rtw89_core_stats_sta_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)2564 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev,
2565 struct rtw89_rx_desc_info *desc_info,
2566 struct ieee80211_rx_status *rx_status)
2567 {
2568 struct rtw89_core_iter_rx_status iter_data;
2569
2570 if (!desc_info->addr1_match || !desc_info->long_rxdesc)
2571 return;
2572
2573 if (desc_info->frame_type != RTW89_RX_TYPE_DATA)
2574 return;
2575
2576 iter_data.rtwdev = rtwdev;
2577 iter_data.rx_status = rx_status;
2578 iter_data.desc_info = desc_info;
2579 iter_data.mac_id = desc_info->mac_id;
2580 ieee80211_iterate_stations_atomic(rtwdev->hw,
2581 rtw89_core_stats_sta_rx_status_iter,
2582 &iter_data);
2583 }
2584
rtw89_core_update_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)2585 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev,
2586 struct rtw89_rx_desc_info *desc_info,
2587 struct ieee80211_rx_status *rx_status)
2588 {
2589 const struct cfg80211_chan_def *chandef =
2590 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0);
2591 u16 data_rate;
2592 u8 data_rate_mode;
2593 bool eht = false;
2594 u8 gi;
2595
2596 /* currently using single PHY */
2597 rx_status->freq = chandef->chan->center_freq;
2598 rx_status->band = chandef->chan->band;
2599
2600 if (rtwdev->scanning &&
2601 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) {
2602 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev);
2603 u8 chan = cur->primary_channel;
2604 u8 band = cur->band_type;
2605 enum nl80211_band nl_band;
2606
2607 nl_band = rtw89_hw_to_nl80211_band(band);
2608 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band);
2609 rx_status->band = nl_band;
2610 }
2611
2612 if (desc_info->icv_err || desc_info->crc32_err)
2613 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2614
2615 if (desc_info->hw_dec &&
2616 !(desc_info->sw_dec || desc_info->icv_err))
2617 rx_status->flag |= RX_FLAG_DECRYPTED;
2618
2619 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
2620
2621 data_rate = desc_info->data_rate;
2622 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
2623 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
2624 rx_status->encoding = RX_ENC_LEGACY;
2625 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
2626 /* convert rate_idx after we get the correct band */
2627 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
2628 rx_status->encoding = RX_ENC_HT;
2629 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
2630 if (desc_info->gi_ltf)
2631 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2632 } else if (data_rate_mode == DATA_RATE_MODE_VHT) {
2633 rx_status->encoding = RX_ENC_VHT;
2634 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2635 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
2636 if (desc_info->gi_ltf)
2637 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2638 } else if (data_rate_mode == DATA_RATE_MODE_HE) {
2639 rx_status->encoding = RX_ENC_HE;
2640 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2641 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
2642 } else if (data_rate_mode == DATA_RATE_MODE_EHT) {
2643 rx_status->encoding = RX_ENC_EHT;
2644 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2645 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
2646 eht = true;
2647 } else {
2648 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
2649 }
2650
2651 /* he_gi is used to match ppdu, so we always fill it. */
2652 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht);
2653 if (eht)
2654 rx_status->eht.gi = gi;
2655 else
2656 rx_status->he_gi = gi;
2657 rx_status->flag |= RX_FLAG_MACTIME_START;
2658 rx_status->mactime = desc_info->free_run_cnt;
2659
2660 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status);
2661 }
2662
rtw89_update_ps_mode(struct rtw89_dev * rtwdev)2663 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev)
2664 {
2665 const struct rtw89_chip_info *chip = rtwdev->chip;
2666
2667 /* FIXME: Fix __rtw89_enter_ps_mode() to consider MLO cases. */
2668 if (rtwdev->support_mlo)
2669 return RTW89_PS_MODE_NONE;
2670
2671 if (rtw89_disable_ps_mode || !chip->ps_mode_supported ||
2672 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw))
2673 return RTW89_PS_MODE_NONE;
2674
2675 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) &&
2676 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw))
2677 return RTW89_PS_MODE_PWR_GATED;
2678
2679 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED))
2680 return RTW89_PS_MODE_CLK_GATED;
2681
2682 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF))
2683 return RTW89_PS_MODE_RFOFF;
2684
2685 return RTW89_PS_MODE_NONE;
2686 }
2687
rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info)2688 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev,
2689 struct rtw89_rx_desc_info *desc_info)
2690 {
2691 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
2692 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2693 struct ieee80211_rx_status *rx_status;
2694 struct sk_buff *skb_ppdu, *tmp;
2695
2696 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) {
2697 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]);
2698 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
2699 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status);
2700 }
2701 }
2702
rtw89_core_rx(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2703 void rtw89_core_rx(struct rtw89_dev *rtwdev,
2704 struct rtw89_rx_desc_info *desc_info,
2705 struct sk_buff *skb)
2706 {
2707 struct ieee80211_rx_status *rx_status;
2708 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
2709 u8 ppdu_cnt = desc_info->ppdu_cnt;
2710 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2711
2712 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) {
2713 rtw89_core_rx_process_report(rtwdev, desc_info, skb);
2714 return;
2715 }
2716
2717 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) {
2718 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info);
2719 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt;
2720 }
2721
2722 rx_status = IEEE80211_SKB_RXCB(skb);
2723 memset(rx_status, 0, sizeof(*rx_status));
2724 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status);
2725 if (desc_info->long_rxdesc &&
2726 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP)
2727 skb_queue_tail(&ppdu_sts->rx_queue[band], skb);
2728 else
2729 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status);
2730 }
2731 EXPORT_SYMBOL(rtw89_core_rx);
2732
rtw89_core_napi_start(struct rtw89_dev * rtwdev)2733 void rtw89_core_napi_start(struct rtw89_dev *rtwdev)
2734 {
2735 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
2736 return;
2737
2738 napi_enable(&rtwdev->napi);
2739 }
2740 EXPORT_SYMBOL(rtw89_core_napi_start);
2741
rtw89_core_napi_stop(struct rtw89_dev * rtwdev)2742 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev)
2743 {
2744 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
2745 return;
2746
2747 napi_synchronize(&rtwdev->napi);
2748 napi_disable(&rtwdev->napi);
2749 }
2750 EXPORT_SYMBOL(rtw89_core_napi_stop);
2751
rtw89_core_napi_init(struct rtw89_dev * rtwdev)2752 int rtw89_core_napi_init(struct rtw89_dev *rtwdev)
2753 {
2754 rtwdev->netdev = alloc_netdev_dummy(0);
2755 if (!rtwdev->netdev)
2756 return -ENOMEM;
2757
2758 netif_napi_add(rtwdev->netdev, &rtwdev->napi,
2759 rtwdev->hci.ops->napi_poll);
2760 return 0;
2761 }
2762 EXPORT_SYMBOL(rtw89_core_napi_init);
2763
rtw89_core_napi_deinit(struct rtw89_dev * rtwdev)2764 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev)
2765 {
2766 rtw89_core_napi_stop(rtwdev);
2767 netif_napi_del(&rtwdev->napi);
2768 free_netdev(rtwdev->netdev);
2769 }
2770 EXPORT_SYMBOL(rtw89_core_napi_deinit);
2771
rtw89_core_ba_work(struct work_struct * work)2772 static void rtw89_core_ba_work(struct work_struct *work)
2773 {
2774 struct rtw89_dev *rtwdev =
2775 container_of(work, struct rtw89_dev, ba_work);
2776 struct rtw89_txq *rtwtxq, *tmp;
2777 int ret;
2778
2779 spin_lock_bh(&rtwdev->ba_lock);
2780 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
2781 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2782 struct ieee80211_sta *sta = txq->sta;
2783 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
2784 u8 tid = txq->tid;
2785
2786 if (!sta) {
2787 rtw89_warn(rtwdev, "cannot start BA without sta\n");
2788 goto skip_ba_work;
2789 }
2790
2791 if (rtwsta->disassoc) {
2792 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2793 "cannot start BA with disassoc sta\n");
2794 goto skip_ba_work;
2795 }
2796
2797 ret = ieee80211_start_tx_ba_session(sta, tid, 0);
2798 if (ret) {
2799 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2800 "failed to setup BA session for %pM:%2d: %d\n",
2801 sta->addr, tid, ret);
2802 if (ret == -EINVAL)
2803 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags);
2804 }
2805 skip_ba_work:
2806 list_del_init(&rtwtxq->list);
2807 }
2808 spin_unlock_bh(&rtwdev->ba_lock);
2809 }
2810
rtw89_core_free_sta_pending_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2811 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
2812 struct ieee80211_sta *sta)
2813 {
2814 struct rtw89_txq *rtwtxq, *tmp;
2815
2816 spin_lock_bh(&rtwdev->ba_lock);
2817 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
2818 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2819
2820 if (sta == txq->sta)
2821 list_del_init(&rtwtxq->list);
2822 }
2823 spin_unlock_bh(&rtwdev->ba_lock);
2824 }
2825
rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2826 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
2827 struct ieee80211_sta *sta)
2828 {
2829 struct rtw89_txq *rtwtxq, *tmp;
2830
2831 spin_lock_bh(&rtwdev->ba_lock);
2832 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
2833 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2834
2835 if (sta == txq->sta) {
2836 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
2837 list_del_init(&rtwtxq->list);
2838 }
2839 }
2840 spin_unlock_bh(&rtwdev->ba_lock);
2841 }
2842
rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2843 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev,
2844 struct ieee80211_sta *sta)
2845 {
2846 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
2847 struct sk_buff *skb, *tmp;
2848
2849 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) {
2850 skb_unlink(skb, &rtwsta->roc_queue);
2851 dev_kfree_skb_any(skb);
2852 }
2853 }
2854
rtw89_core_stop_tx_ba_session(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq)2855 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev,
2856 struct rtw89_txq *rtwtxq)
2857 {
2858 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2859 struct ieee80211_sta *sta = txq->sta;
2860 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
2861
2862 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc))
2863 return;
2864
2865 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) ||
2866 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
2867 return;
2868
2869 spin_lock_bh(&rtwdev->ba_lock);
2870 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
2871 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list);
2872 spin_unlock_bh(&rtwdev->ba_lock);
2873
2874 ieee80211_stop_tx_ba_session(sta, txq->tid);
2875 cancel_delayed_work(&rtwdev->forbid_ba_work);
2876 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work,
2877 RTW89_FORBID_BA_TIMER);
2878 }
2879
rtw89_core_txq_check_agg(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,struct sk_buff * skb)2880 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev,
2881 struct rtw89_txq *rtwtxq,
2882 struct sk_buff *skb)
2883 {
2884 struct ieee80211_hw *hw = rtwdev->hw;
2885 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2886 struct ieee80211_sta *sta = txq->sta;
2887 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
2888
2889 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
2890 return;
2891
2892 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
2893 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq);
2894 return;
2895 }
2896
2897 if (unlikely(!sta))
2898 return;
2899
2900 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags)))
2901 return;
2902
2903 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) {
2904 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU;
2905 return;
2906 }
2907
2908 spin_lock_bh(&rtwdev->ba_lock);
2909 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) {
2910 list_add_tail(&rtwtxq->list, &rtwdev->ba_list);
2911 ieee80211_queue_work(hw, &rtwdev->ba_work);
2912 }
2913 spin_unlock_bh(&rtwdev->ba_lock);
2914 }
2915
rtw89_core_txq_push(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,unsigned long frame_cnt,unsigned long byte_cnt)2916 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev,
2917 struct rtw89_txq *rtwtxq,
2918 unsigned long frame_cnt,
2919 unsigned long byte_cnt)
2920 {
2921 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2922 struct ieee80211_vif *vif = txq->vif;
2923 struct ieee80211_sta *sta = txq->sta;
2924 struct sk_buff *skb;
2925 unsigned long i;
2926 int ret;
2927
2928 rcu_read_lock();
2929 for (i = 0; i < frame_cnt; i++) {
2930 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq);
2931 if (!skb) {
2932 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n");
2933 goto out;
2934 }
2935 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb);
2936 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL);
2937 if (ret) {
2938 rtw89_err(rtwdev, "failed to push txq: %d\n", ret);
2939 ieee80211_free_txskb(rtwdev->hw, skb);
2940 break;
2941 }
2942 }
2943 out:
2944 rcu_read_unlock();
2945 }
2946
rtw89_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 tid)2947 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid)
2948 {
2949 u8 qsel, ch_dma;
2950
2951 qsel = rtw89_core_get_qsel(rtwdev, tid);
2952 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
2953
2954 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma);
2955 }
2956
rtw89_core_txq_agg_wait(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq,unsigned long * frame_cnt,bool * sched_txq,bool * reinvoke)2957 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev,
2958 struct ieee80211_txq *txq,
2959 unsigned long *frame_cnt,
2960 bool *sched_txq, bool *reinvoke)
2961 {
2962 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv;
2963 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(txq->sta);
2964 struct rtw89_sta_link *rtwsta_link;
2965
2966 if (!rtwsta)
2967 return false;
2968
2969 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
2970 if (unlikely(!rtwsta_link)) {
2971 rtw89_err(rtwdev, "agg wait: find no link on HW-0\n");
2972 return false;
2973 }
2974
2975 if (rtwsta_link->max_agg_wait <= 0)
2976 return false;
2977
2978 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID)
2979 return false;
2980
2981 if (*frame_cnt > 1) {
2982 *frame_cnt -= 1;
2983 *sched_txq = true;
2984 *reinvoke = true;
2985 rtwtxq->wait_cnt = 1;
2986 return false;
2987 }
2988
2989 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta_link->max_agg_wait) {
2990 *reinvoke = true;
2991 rtwtxq->wait_cnt++;
2992 return true;
2993 }
2994
2995 rtwtxq->wait_cnt = 0;
2996 return false;
2997 }
2998
rtw89_core_txq_schedule(struct rtw89_dev * rtwdev,u8 ac,bool * reinvoke)2999 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke)
3000 {
3001 struct ieee80211_hw *hw = rtwdev->hw;
3002 struct ieee80211_txq *txq;
3003 struct rtw89_vif *rtwvif;
3004 struct rtw89_txq *rtwtxq;
3005 unsigned long frame_cnt;
3006 unsigned long byte_cnt;
3007 u32 tx_resource;
3008 bool sched_txq;
3009
3010 ieee80211_txq_schedule_start(hw, ac);
3011 while ((txq = ieee80211_next_txq(hw, ac))) {
3012 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
3013 rtwvif = vif_to_rtwvif(txq->vif);
3014
3015 if (rtwvif->offchan) {
3016 ieee80211_return_txq(hw, txq, true);
3017 continue;
3018 }
3019 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid);
3020 sched_txq = false;
3021
3022 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt);
3023 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) {
3024 ieee80211_return_txq(hw, txq, true);
3025 continue;
3026 }
3027 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource);
3028 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt);
3029 ieee80211_return_txq(hw, txq, sched_txq);
3030 if (frame_cnt != 0)
3031 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid));
3032
3033 /* bound of tx_resource could get stuck due to burst traffic */
3034 if (frame_cnt == tx_resource)
3035 *reinvoke = true;
3036 }
3037 ieee80211_txq_schedule_end(hw, ac);
3038 }
3039
rtw89_ips_work(struct work_struct * work)3040 static void rtw89_ips_work(struct work_struct *work)
3041 {
3042 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
3043 ips_work);
3044 mutex_lock(&rtwdev->mutex);
3045 rtw89_enter_ips_by_hwflags(rtwdev);
3046 mutex_unlock(&rtwdev->mutex);
3047 }
3048
rtw89_core_txq_work(struct work_struct * w)3049 static void rtw89_core_txq_work(struct work_struct *w)
3050 {
3051 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work);
3052 bool reinvoke = false;
3053 u8 ac;
3054
3055 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
3056 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke);
3057
3058 if (reinvoke) {
3059 /* reinvoke to process the last frame */
3060 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1);
3061 }
3062 }
3063
rtw89_core_txq_reinvoke_work(struct work_struct * w)3064 static void rtw89_core_txq_reinvoke_work(struct work_struct *w)
3065 {
3066 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
3067 txq_reinvoke_work.work);
3068
3069 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
3070 }
3071
rtw89_forbid_ba_work(struct work_struct * w)3072 static void rtw89_forbid_ba_work(struct work_struct *w)
3073 {
3074 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
3075 forbid_ba_work.work);
3076 struct rtw89_txq *rtwtxq, *tmp;
3077
3078 spin_lock_bh(&rtwdev->ba_lock);
3079 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
3080 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
3081 list_del_init(&rtwtxq->list);
3082 }
3083 spin_unlock_bh(&rtwdev->ba_lock);
3084 }
3085
rtw89_core_sta_pending_tx_iter(void * data,struct ieee80211_sta * sta)3086 static void rtw89_core_sta_pending_tx_iter(void *data,
3087 struct ieee80211_sta *sta)
3088 {
3089 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
3090 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
3091 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
3092 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3093 struct rtw89_vif_link *target = data;
3094 struct rtw89_vif_link *rtwvif_link;
3095 struct sk_buff *skb, *tmp;
3096 unsigned int link_id;
3097 int qsel, ret;
3098
3099 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
3100 if (rtwvif_link->chanctx_idx == target->chanctx_idx)
3101 goto bottom;
3102
3103 return;
3104
3105 bottom:
3106 if (skb_queue_len(&rtwsta->roc_queue) == 0)
3107 return;
3108
3109 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) {
3110 skb_unlink(skb, &rtwsta->roc_queue);
3111
3112 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
3113 if (ret) {
3114 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret);
3115 dev_kfree_skb_any(skb);
3116 } else {
3117 rtw89_core_tx_kick_off(rtwdev, qsel);
3118 }
3119 }
3120 }
3121
rtw89_core_handle_sta_pending_tx(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)3122 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev,
3123 struct rtw89_vif_link *rtwvif_link)
3124 {
3125 ieee80211_iterate_stations_atomic(rtwdev->hw,
3126 rtw89_core_sta_pending_tx_iter,
3127 rtwvif_link);
3128 }
3129
rtw89_core_send_nullfunc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool qos,bool ps)3130 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev,
3131 struct rtw89_vif_link *rtwvif_link, bool qos, bool ps)
3132 {
3133 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3134 struct ieee80211_sta *sta;
3135 struct ieee80211_hdr *hdr;
3136 struct sk_buff *skb;
3137 int ret, qsel;
3138
3139 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
3140 return 0;
3141
3142 rcu_read_lock();
3143 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr);
3144 if (!sta) {
3145 ret = -EINVAL;
3146 goto out;
3147 }
3148
3149 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, qos);
3150 if (!skb) {
3151 ret = -ENOMEM;
3152 goto out;
3153 }
3154
3155 hdr = (struct ieee80211_hdr *)skb->data;
3156 if (ps)
3157 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
3158
3159 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
3160 if (ret) {
3161 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret);
3162 dev_kfree_skb_any(skb);
3163 goto out;
3164 }
3165
3166 rcu_read_unlock();
3167
3168 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel,
3169 RTW89_ROC_TX_TIMEOUT);
3170 out:
3171 rcu_read_unlock();
3172
3173 return ret;
3174 }
3175
rtw89_roc_start(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3176 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3177 {
3178 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3179 struct ieee80211_hw *hw = rtwdev->hw;
3180 struct rtw89_roc *roc = &rtwvif->roc;
3181 struct rtw89_vif_link *rtwvif_link;
3182 struct cfg80211_chan_def roc_chan;
3183 struct rtw89_vif *tmp_vif;
3184 u32 reg;
3185 int ret;
3186
3187 lockdep_assert_held(&rtwdev->mutex);
3188
3189 rtw89_leave_ips_by_hwflags(rtwdev);
3190 rtw89_leave_lps(rtwdev);
3191
3192 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, RTW89_ROC_BY_LINK_INDEX);
3193 if (unlikely(!rtwvif_link)) {
3194 rtw89_err(rtwdev, "roc start: find no link on HW-%u\n",
3195 RTW89_ROC_BY_LINK_INDEX);
3196 return;
3197 }
3198
3199 rtw89_chanctx_pause(rtwdev, RTW89_CHANCTX_PAUSE_REASON_ROC);
3200
3201 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, true);
3202 if (ret)
3203 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
3204 "roc send null-1 failed: %d\n", ret);
3205
3206 rtw89_for_each_rtwvif(rtwdev, tmp_vif) {
3207 struct rtw89_vif_link *tmp_link;
3208 unsigned int link_id;
3209
3210 rtw89_vif_for_each_link(tmp_vif, tmp_link, link_id) {
3211 if (tmp_link->chanctx_idx == rtwvif_link->chanctx_idx) {
3212 tmp_vif->offchan = true;
3213 break;
3214 }
3215 }
3216 }
3217
3218 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT);
3219 rtw89_config_roc_chandef(rtwdev, rtwvif_link->chanctx_idx, &roc_chan);
3220 rtw89_set_channel(rtwdev);
3221
3222 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
3223 rtw89_write32_clr(rtwdev, reg, B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH);
3224
3225 ieee80211_ready_on_channel(hw);
3226 cancel_delayed_work(&rtwvif->roc.roc_work);
3227 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work,
3228 msecs_to_jiffies(rtwvif->roc.duration));
3229 }
3230
rtw89_roc_end(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3231 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3232 {
3233 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3234 struct ieee80211_hw *hw = rtwdev->hw;
3235 struct rtw89_roc *roc = &rtwvif->roc;
3236 struct rtw89_vif_link *rtwvif_link;
3237 struct rtw89_vif *tmp_vif;
3238 u32 reg;
3239 int ret;
3240
3241 lockdep_assert_held(&rtwdev->mutex);
3242
3243 ieee80211_remain_on_channel_expired(hw);
3244
3245 rtw89_leave_ips_by_hwflags(rtwdev);
3246 rtw89_leave_lps(rtwdev);
3247
3248 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, RTW89_ROC_BY_LINK_INDEX);
3249 if (unlikely(!rtwvif_link)) {
3250 rtw89_err(rtwdev, "roc end: find no link on HW-%u\n",
3251 RTW89_ROC_BY_LINK_INDEX);
3252 return;
3253 }
3254
3255 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
3256 rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr);
3257
3258 roc->state = RTW89_ROC_IDLE;
3259 rtw89_config_roc_chandef(rtwdev, rtwvif_link->chanctx_idx, NULL);
3260 rtw89_chanctx_proceed(rtwdev);
3261 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, false);
3262 if (ret)
3263 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
3264 "roc send null-0 failed: %d\n", ret);
3265
3266 rtw89_for_each_rtwvif(rtwdev, tmp_vif)
3267 tmp_vif->offchan = false;
3268
3269 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif_link);
3270 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
3271
3272 if (hw->conf.flags & IEEE80211_CONF_IDLE)
3273 ieee80211_queue_delayed_work(hw, &roc->roc_work,
3274 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT));
3275 }
3276
rtw89_roc_work(struct work_struct * work)3277 void rtw89_roc_work(struct work_struct *work)
3278 {
3279 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif,
3280 roc.roc_work.work);
3281 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
3282 struct rtw89_roc *roc = &rtwvif->roc;
3283
3284 mutex_lock(&rtwdev->mutex);
3285
3286 switch (roc->state) {
3287 case RTW89_ROC_IDLE:
3288 rtw89_enter_ips_by_hwflags(rtwdev);
3289 break;
3290 case RTW89_ROC_MGMT:
3291 case RTW89_ROC_NORMAL:
3292 rtw89_roc_end(rtwdev, rtwvif);
3293 break;
3294 default:
3295 break;
3296 }
3297
3298 mutex_unlock(&rtwdev->mutex);
3299 }
3300
rtw89_get_traffic_level(struct rtw89_dev * rtwdev,u32 throughput,u64 cnt)3301 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev,
3302 u32 throughput, u64 cnt)
3303 {
3304 if (cnt < 100)
3305 return RTW89_TFC_IDLE;
3306 if (throughput > 50)
3307 return RTW89_TFC_HIGH;
3308 if (throughput > 10)
3309 return RTW89_TFC_MID;
3310 if (throughput > 2)
3311 return RTW89_TFC_LOW;
3312 return RTW89_TFC_ULTRA_LOW;
3313 }
3314
rtw89_traffic_stats_calc(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)3315 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev,
3316 struct rtw89_traffic_stats *stats)
3317 {
3318 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv;
3319 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv;
3320
3321 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT);
3322 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT);
3323
3324 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw);
3325 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw);
3326
3327 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
3328 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
3329 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput,
3330 stats->tx_cnt);
3331 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput,
3332 stats->rx_cnt);
3333 stats->tx_avg_len = stats->tx_cnt ?
3334 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0;
3335 stats->rx_avg_len = stats->rx_cnt ?
3336 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0;
3337
3338 stats->tx_unicast = 0;
3339 stats->rx_unicast = 0;
3340 stats->tx_cnt = 0;
3341 stats->rx_cnt = 0;
3342 stats->rx_tf_periodic = stats->rx_tf_acc;
3343 stats->rx_tf_acc = 0;
3344
3345 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv)
3346 return true;
3347
3348 return false;
3349 }
3350
rtw89_traffic_stats_track(struct rtw89_dev * rtwdev)3351 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev)
3352 {
3353 struct rtw89_vif_link *rtwvif_link;
3354 struct rtw89_vif *rtwvif;
3355 unsigned int link_id;
3356 bool tfc_changed;
3357
3358 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats);
3359
3360 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
3361 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats);
3362
3363 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
3364 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif_link);
3365 }
3366
3367 return tfc_changed;
3368 }
3369
rtw89_vif_enter_lps(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)3370 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev,
3371 struct rtw89_vif_link *rtwvif_link)
3372 {
3373 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION &&
3374 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT)
3375 return;
3376
3377 rtw89_enter_lps(rtwdev, rtwvif_link, true);
3378 }
3379
rtw89_enter_lps_track(struct rtw89_dev * rtwdev)3380 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev)
3381 {
3382 struct rtw89_vif_link *rtwvif_link;
3383 struct rtw89_vif *rtwvif;
3384 unsigned int link_id;
3385
3386 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
3387 if (rtwvif->tdls_peer)
3388 continue;
3389 if (rtwvif->offchan)
3390 continue;
3391
3392 if (rtwvif->stats.tx_tfc_lv != RTW89_TFC_IDLE ||
3393 rtwvif->stats.rx_tfc_lv != RTW89_TFC_IDLE)
3394 continue;
3395
3396 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
3397 rtw89_vif_enter_lps(rtwdev, rtwvif_link);
3398 }
3399 }
3400
rtw89_core_rfk_track(struct rtw89_dev * rtwdev)3401 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev)
3402 {
3403 enum rtw89_entity_mode mode;
3404
3405 mode = rtw89_get_entity_mode(rtwdev);
3406 if (mode == RTW89_ENTITY_MODE_MCC)
3407 return;
3408
3409 rtw89_chip_rfk_track(rtwdev);
3410 }
3411
rtw89_core_update_p2p_ps(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct ieee80211_bss_conf * bss_conf)3412 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev,
3413 struct rtw89_vif_link *rtwvif_link,
3414 struct ieee80211_bss_conf *bss_conf)
3415 {
3416 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev);
3417
3418 if (mode == RTW89_ENTITY_MODE_MCC)
3419 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE);
3420 else
3421 rtw89_process_p2p_ps(rtwdev, rtwvif_link, bss_conf);
3422 }
3423
rtw89_traffic_stats_init(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)3424 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
3425 struct rtw89_traffic_stats *stats)
3426 {
3427 stats->tx_unicast = 0;
3428 stats->rx_unicast = 0;
3429 stats->tx_cnt = 0;
3430 stats->rx_cnt = 0;
3431 ewma_tp_init(&stats->tx_ewma_tp);
3432 ewma_tp_init(&stats->rx_ewma_tp);
3433 }
3434
rtw89_track_work(struct work_struct * work)3435 static void rtw89_track_work(struct work_struct *work)
3436 {
3437 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
3438 track_work.work);
3439 bool tfc_changed;
3440
3441 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags))
3442 return;
3443
3444 mutex_lock(&rtwdev->mutex);
3445
3446 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
3447 goto out;
3448
3449 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
3450 RTW89_TRACK_WORK_PERIOD);
3451
3452 tfc_changed = rtw89_traffic_stats_track(rtwdev);
3453 if (rtwdev->scanning)
3454 goto out;
3455
3456 rtw89_leave_lps(rtwdev);
3457
3458 if (tfc_changed) {
3459 rtw89_hci_recalc_int_mit(rtwdev);
3460 rtw89_btc_ntfy_wl_sta(rtwdev);
3461 }
3462 rtw89_mac_bf_monitor_track(rtwdev);
3463 rtw89_phy_stat_track(rtwdev);
3464 rtw89_phy_env_monitor_track(rtwdev);
3465 rtw89_phy_dig(rtwdev);
3466 rtw89_core_rfk_track(rtwdev);
3467 rtw89_phy_ra_update(rtwdev);
3468 rtw89_phy_cfo_track(rtwdev);
3469 rtw89_phy_tx_path_div_track(rtwdev);
3470 rtw89_phy_antdiv_track(rtwdev);
3471 rtw89_phy_ul_tb_ctrl_track(rtwdev);
3472 rtw89_phy_edcca_track(rtwdev);
3473 rtw89_tas_track(rtwdev);
3474 rtw89_chanctx_track(rtwdev);
3475 rtw89_core_rfkill_poll(rtwdev, false);
3476
3477 if (rtwdev->lps_enabled && !rtwdev->btc.lps)
3478 rtw89_enter_lps_track(rtwdev);
3479
3480 out:
3481 mutex_unlock(&rtwdev->mutex);
3482 }
3483
rtw89_core_acquire_bit_map(unsigned long * addr,unsigned long size)3484 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size)
3485 {
3486 unsigned long bit;
3487
3488 bit = find_first_zero_bit(addr, size);
3489 if (bit < size)
3490 set_bit(bit, addr);
3491
3492 return bit;
3493 }
3494
rtw89_core_release_bit_map(unsigned long * addr,u8 bit)3495 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit)
3496 {
3497 clear_bit(bit, addr);
3498 }
3499
rtw89_core_release_all_bits_map(unsigned long * addr,unsigned int nbits)3500 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits)
3501 {
3502 bitmap_zero(addr, nbits);
3503 }
3504
rtw89_core_acquire_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u8 tid,u8 * cam_idx)3505 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
3506 struct rtw89_sta_link *rtwsta_link, u8 tid,
3507 u8 *cam_idx)
3508 {
3509 const struct rtw89_chip_info *chip = rtwdev->chip;
3510 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
3511 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
3512 u8 idx;
3513 int i;
3514
3515 lockdep_assert_held(&rtwdev->mutex);
3516
3517 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num);
3518 if (idx == chip->bacam_num) {
3519 /* allocate a static BA CAM to tid=0/5, so replace the existing
3520 * one if BA CAM is full. Hardware will process the original tid
3521 * automatically.
3522 */
3523 if (tid != 0 && tid != 5)
3524 return -ENOSPC;
3525
3526 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) {
3527 tmp = &cam_info->ba_cam_entry[i];
3528 if (tmp->tid == 0 || tmp->tid == 5)
3529 continue;
3530
3531 idx = i;
3532 entry = tmp;
3533 list_del(&entry->list);
3534 break;
3535 }
3536
3537 if (!entry)
3538 return -ENOSPC;
3539 } else {
3540 entry = &cam_info->ba_cam_entry[idx];
3541 }
3542
3543 entry->tid = tid;
3544 list_add_tail(&entry->list, &rtwsta_link->ba_cam_list);
3545
3546 *cam_idx = idx;
3547
3548 return 0;
3549 }
3550
rtw89_core_release_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u8 tid,u8 * cam_idx)3551 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
3552 struct rtw89_sta_link *rtwsta_link, u8 tid,
3553 u8 *cam_idx)
3554 {
3555 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
3556 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
3557 u8 idx;
3558
3559 lockdep_assert_held(&rtwdev->mutex);
3560
3561 list_for_each_entry_safe(entry, tmp, &rtwsta_link->ba_cam_list, list) {
3562 if (entry->tid != tid)
3563 continue;
3564
3565 idx = entry - cam_info->ba_cam_entry;
3566 list_del(&entry->list);
3567
3568 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx);
3569 *cam_idx = idx;
3570 return 0;
3571 }
3572
3573 return -ENOENT;
3574 }
3575
3576 #define RTW89_TYPE_MAPPING(_type) \
3577 case NL80211_IFTYPE_ ## _type: \
3578 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_ ## _type; \
3579 break
rtw89_vif_type_mapping(struct rtw89_vif_link * rtwvif_link,bool assoc)3580 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc)
3581 {
3582 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3583 const struct ieee80211_bss_conf *bss_conf;
3584
3585 switch (vif->type) {
3586 case NL80211_IFTYPE_STATION:
3587 if (vif->p2p)
3588 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT;
3589 else
3590 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_STATION;
3591 break;
3592 case NL80211_IFTYPE_AP:
3593 if (vif->p2p)
3594 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_GO;
3595 else
3596 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_AP;
3597 break;
3598 RTW89_TYPE_MAPPING(ADHOC);
3599 RTW89_TYPE_MAPPING(MONITOR);
3600 RTW89_TYPE_MAPPING(MESH_POINT);
3601 default:
3602 WARN_ON(1);
3603 break;
3604 }
3605
3606 switch (vif->type) {
3607 case NL80211_IFTYPE_AP:
3608 case NL80211_IFTYPE_MESH_POINT:
3609 rtwvif_link->net_type = RTW89_NET_TYPE_AP_MODE;
3610 rtwvif_link->self_role = RTW89_SELF_ROLE_AP;
3611 break;
3612 case NL80211_IFTYPE_ADHOC:
3613 rtwvif_link->net_type = RTW89_NET_TYPE_AD_HOC;
3614 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT;
3615 break;
3616 case NL80211_IFTYPE_STATION:
3617 if (assoc) {
3618 rtwvif_link->net_type = RTW89_NET_TYPE_INFRA;
3619
3620 rcu_read_lock();
3621 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
3622 rtwvif_link->trigger = bss_conf->he_support;
3623 rcu_read_unlock();
3624 } else {
3625 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK;
3626 rtwvif_link->trigger = false;
3627 }
3628 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT;
3629 rtwvif_link->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL;
3630 break;
3631 case NL80211_IFTYPE_MONITOR:
3632 break;
3633 default:
3634 WARN_ON(1);
3635 break;
3636 }
3637 }
3638
rtw89_core_sta_link_add(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3639 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev,
3640 struct rtw89_vif_link *rtwvif_link,
3641 struct rtw89_sta_link *rtwsta_link)
3642 {
3643 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3644 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
3645 struct rtw89_hal *hal = &rtwdev->hal;
3646 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
3647 int i;
3648 int ret;
3649
3650 rtwsta_link->prev_rssi = 0;
3651 INIT_LIST_HEAD(&rtwsta_link->ba_cam_list);
3652 ewma_rssi_init(&rtwsta_link->avg_rssi);
3653 ewma_snr_init(&rtwsta_link->avg_snr);
3654 ewma_evm_init(&rtwsta_link->evm_1ss);
3655 for (i = 0; i < ant_num; i++) {
3656 ewma_rssi_init(&rtwsta_link->rssi[i]);
3657 ewma_evm_init(&rtwsta_link->evm_min[i]);
3658 ewma_evm_init(&rtwsta_link->evm_max[i]);
3659 }
3660
3661 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3662 /* must do rtw89_reg_6ghz_recalc() before rfk channel */
3663 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, true);
3664 if (ret)
3665 return ret;
3666
3667 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
3668 BTC_ROLE_MSTS_STA_CONN_START);
3669 rtw89_chip_rfk_channel(rtwdev, rtwvif_link);
3670 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3671 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta_link->mac_id, false);
3672 if (ret) {
3673 rtw89_warn(rtwdev, "failed to send h2c macid pause\n");
3674 return ret;
3675 }
3676
3677 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link,
3678 RTW89_ROLE_CREATE);
3679 if (ret) {
3680 rtw89_warn(rtwdev, "failed to send h2c role info\n");
3681 return ret;
3682 }
3683
3684 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3685 if (ret)
3686 return ret;
3687
3688 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3689 if (ret)
3690 return ret;
3691 }
3692
3693 return 0;
3694 }
3695
rtw89_core_sta_link_disassoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3696 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev,
3697 struct rtw89_vif_link *rtwvif_link,
3698 struct rtw89_sta_link *rtwsta_link)
3699 {
3700 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3701
3702 if (vif->type == NL80211_IFTYPE_STATION)
3703 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false);
3704
3705 return 0;
3706 }
3707
rtw89_core_sta_link_disconnect(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3708 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev,
3709 struct rtw89_vif_link *rtwvif_link,
3710 struct rtw89_sta_link *rtwsta_link)
3711 {
3712 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3713 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
3714 int ret;
3715
3716 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, true);
3717 rtw89_mac_bf_disassoc(rtwdev, rtwvif_link, rtwsta_link);
3718
3719 if (vif->type == NL80211_IFTYPE_AP || sta->tdls)
3720 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam);
3721 if (sta->tdls)
3722 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam);
3723
3724 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3725 rtw89_vif_type_mapping(rtwvif_link, false);
3726 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif_link, true);
3727 }
3728
3729 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3730 if (ret) {
3731 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
3732 return ret;
3733 }
3734
3735 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, true);
3736 if (ret) {
3737 rtw89_warn(rtwdev, "failed to send h2c join info\n");
3738 return ret;
3739 }
3740
3741 /* update cam aid mac_id net_type */
3742 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL);
3743 if (ret) {
3744 rtw89_warn(rtwdev, "failed to send h2c cam\n");
3745 return ret;
3746 }
3747
3748 return ret;
3749 }
3750
rtw89_core_sta_link_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3751 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev,
3752 struct rtw89_vif_link *rtwvif_link,
3753 struct rtw89_sta_link *rtwsta_link)
3754 {
3755 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3756 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
3757 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link,
3758 rtwsta_link);
3759 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
3760 rtwvif_link->chanctx_idx);
3761 int ret;
3762
3763 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3764 if (sta->tdls) {
3765 struct ieee80211_link_sta *link_sta;
3766
3767 rcu_read_lock();
3768
3769 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
3770 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif_link, bssid_cam,
3771 link_sta->addr);
3772 if (ret) {
3773 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n");
3774 rcu_read_unlock();
3775 return ret;
3776 }
3777
3778 rcu_read_unlock();
3779 }
3780
3781 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta_link->addr_cam, bssid_cam);
3782 if (ret) {
3783 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n");
3784 return ret;
3785 }
3786 }
3787
3788 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3789 if (ret) {
3790 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
3791 return ret;
3792 }
3793
3794 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, false);
3795 if (ret) {
3796 rtw89_warn(rtwdev, "failed to send h2c join info\n");
3797 return ret;
3798 }
3799
3800 /* update cam aid mac_id net_type */
3801 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL);
3802 if (ret) {
3803 rtw89_warn(rtwdev, "failed to send h2c cam\n");
3804 return ret;
3805 }
3806
3807 rtw89_phy_ra_assoc(rtwdev, rtwsta_link);
3808 rtw89_mac_bf_assoc(rtwdev, rtwvif_link, rtwsta_link);
3809 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, false);
3810
3811 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3812 struct ieee80211_bss_conf *bss_conf;
3813
3814 rcu_read_lock();
3815
3816 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
3817 if (bss_conf->he_support &&
3818 !(bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE))
3819 rtwsta_link->er_cap = true;
3820
3821 rcu_read_unlock();
3822
3823 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
3824 BTC_ROLE_MSTS_STA_CONN_END);
3825 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan);
3826 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link);
3827
3828 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id);
3829 if (ret) {
3830 rtw89_warn(rtwdev, "failed to send h2c general packet\n");
3831 return ret;
3832 }
3833
3834 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true);
3835 }
3836
3837 return ret;
3838 }
3839
rtw89_core_sta_link_remove(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3840 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev,
3841 struct rtw89_vif_link *rtwvif_link,
3842 struct rtw89_sta_link *rtwsta_link)
3843 {
3844 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3845 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
3846 int ret;
3847
3848 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3849 rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, false);
3850 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
3851 BTC_ROLE_MSTS_STA_DIS_CONN);
3852 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3853 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link,
3854 RTW89_ROLE_REMOVE);
3855 if (ret) {
3856 rtw89_warn(rtwdev, "failed to send h2c role info\n");
3857 return ret;
3858 }
3859 }
3860
3861 return 0;
3862 }
3863
_rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_cfg * tid_conf)3864 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
3865 struct ieee80211_sta *sta,
3866 struct cfg80211_tid_cfg *tid_conf)
3867 {
3868 struct ieee80211_txq *txq;
3869 struct rtw89_txq *rtwtxq;
3870 u32 mask = tid_conf->mask;
3871 u8 tids = tid_conf->tids;
3872 int tids_nbit = BITS_PER_BYTE;
3873 int i;
3874
3875 for (i = 0; i < tids_nbit; i++, tids >>= 1) {
3876 if (!tids)
3877 break;
3878
3879 if (!(tids & BIT(0)))
3880 continue;
3881
3882 txq = sta->txq[i];
3883 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
3884
3885 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) {
3886 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) {
3887 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
3888 } else {
3889 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags))
3890 ieee80211_stop_tx_ba_session(sta, txq->tid);
3891 spin_lock_bh(&rtwdev->ba_lock);
3892 list_del_init(&rtwtxq->list);
3893 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
3894 spin_unlock_bh(&rtwdev->ba_lock);
3895 }
3896 }
3897
3898 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) {
3899 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE)
3900 sta->max_amsdu_subframes = 0;
3901 else
3902 sta->max_amsdu_subframes = 1;
3903 }
3904 }
3905 }
3906
rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_config * tid_config)3907 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
3908 struct ieee80211_sta *sta,
3909 struct cfg80211_tid_config *tid_config)
3910 {
3911 int i;
3912
3913 for (i = 0; i < tid_config->n_tid_conf; i++)
3914 _rtw89_core_set_tid_config(rtwdev, sta,
3915 &tid_config->tid_conf[i]);
3916 }
3917
rtw89_init_ht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_ht_cap * ht_cap)3918 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev,
3919 struct ieee80211_sta_ht_cap *ht_cap)
3920 {
3921 static const __le16 highest[RF_PATH_MAX] = {
3922 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600),
3923 };
3924 struct rtw89_hal *hal = &rtwdev->hal;
3925 u8 nss = hal->rx_nss;
3926 int i;
3927
3928 ht_cap->ht_supported = true;
3929 ht_cap->cap = 0;
3930 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
3931 IEEE80211_HT_CAP_MAX_AMSDU |
3932 IEEE80211_HT_CAP_TX_STBC |
3933 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
3934 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
3935 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
3936 IEEE80211_HT_CAP_DSSSCCK40 |
3937 IEEE80211_HT_CAP_SGI_40;
3938 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
3939 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
3940 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
3941 for (i = 0; i < nss; i++)
3942 ht_cap->mcs.rx_mask[i] = 0xFF;
3943 ht_cap->mcs.rx_mask[4] = 0x01;
3944 ht_cap->mcs.rx_highest = highest[nss - 1];
3945 }
3946
rtw89_init_vht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_vht_cap * vht_cap)3947 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev,
3948 struct ieee80211_sta_vht_cap *vht_cap)
3949 {
3950 static const __le16 highest_bw80[RF_PATH_MAX] = {
3951 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733),
3952 };
3953 static const __le16 highest_bw160[RF_PATH_MAX] = {
3954 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467),
3955 };
3956 const struct rtw89_chip_info *chip = rtwdev->chip;
3957 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ?
3958 highest_bw160 : highest_bw80;
3959 struct rtw89_hal *hal = &rtwdev->hal;
3960 u16 tx_mcs_map = 0, rx_mcs_map = 0;
3961 u8 sts_cap = 3;
3962 int i;
3963
3964 for (i = 0; i < 8; i++) {
3965 if (i < hal->tx_nss)
3966 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
3967 else
3968 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
3969 if (i < hal->rx_nss)
3970 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
3971 else
3972 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
3973 }
3974
3975 vht_cap->vht_supported = true;
3976 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
3977 IEEE80211_VHT_CAP_SHORT_GI_80 |
3978 IEEE80211_VHT_CAP_RXSTBC_1 |
3979 IEEE80211_VHT_CAP_HTC_VHT |
3980 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
3981 0;
3982 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
3983 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
3984 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
3985 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
3986 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT;
3987 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
3988 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
3989 IEEE80211_VHT_CAP_SHORT_GI_160;
3990 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map);
3991 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map);
3992 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1];
3993 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1];
3994
3995 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW))
3996 vht_cap->vht_mcs.tx_highest |=
3997 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
3998 }
3999
rtw89_init_he_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)4000 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev,
4001 enum nl80211_band band,
4002 enum nl80211_iftype iftype,
4003 struct ieee80211_sband_iftype_data *iftype_data)
4004 {
4005 const struct rtw89_chip_info *chip = rtwdev->chip;
4006 struct rtw89_hal *hal = &rtwdev->hal;
4007 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) ||
4008 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV);
4009 struct ieee80211_sta_he_cap *he_cap;
4010 int nss = hal->rx_nss;
4011 u8 *mac_cap_info;
4012 u8 *phy_cap_info;
4013 u16 mcs_map = 0;
4014 int i;
4015
4016 for (i = 0; i < 8; i++) {
4017 if (i < nss)
4018 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2);
4019 else
4020 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2);
4021 }
4022
4023 he_cap = &iftype_data->he_cap;
4024 mac_cap_info = he_cap->he_cap_elem.mac_cap_info;
4025 phy_cap_info = he_cap->he_cap_elem.phy_cap_info;
4026
4027 he_cap->has_he = true;
4028 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE;
4029 if (iftype == NL80211_IFTYPE_STATION)
4030 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
4031 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK |
4032 IEEE80211_HE_MAC_CAP2_BSR;
4033 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2;
4034 if (iftype == NL80211_IFTYPE_AP)
4035 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL;
4036 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS |
4037 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
4038 if (iftype == NL80211_IFTYPE_STATION)
4039 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX;
4040 if (band == NL80211_BAND_2GHZ) {
4041 phy_cap_info[0] =
4042 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
4043 } else {
4044 phy_cap_info[0] =
4045 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G;
4046 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
4047 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
4048 }
4049 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
4050 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD |
4051 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
4052 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
4053 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
4054 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ |
4055 IEEE80211_HE_PHY_CAP2_DOPPLER_TX;
4056 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM;
4057 if (iftype == NL80211_IFTYPE_STATION)
4058 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM |
4059 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2;
4060 if (iftype == NL80211_IFTYPE_AP)
4061 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU;
4062 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
4063 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4;
4064 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
4065 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
4066 phy_cap_info[5] = no_ng16 ? 0 :
4067 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK |
4068 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK;
4069 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
4070 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU |
4071 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
4072 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE;
4073 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
4074 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
4075 IEEE80211_HE_PHY_CAP7_MAX_NC_1;
4076 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
4077 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI |
4078 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996;
4079 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
4080 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
4081 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;
4082 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
4083 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
4084 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
4085 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
4086 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
4087 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
4088 if (iftype == NL80211_IFTYPE_STATION)
4089 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
4090 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map);
4091 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map);
4092 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) {
4093 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map);
4094 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map);
4095 }
4096
4097 if (band == NL80211_BAND_6GHZ) {
4098 __le16 capa;
4099
4100 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE,
4101 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
4102 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
4103 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
4104 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
4105 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
4106 iftype_data->he_6ghz_capa.capa = capa;
4107 }
4108 }
4109
rtw89_init_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)4110 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev,
4111 enum nl80211_band band,
4112 enum nl80211_iftype iftype,
4113 struct ieee80211_sband_iftype_data *iftype_data)
4114 {
4115 const struct rtw89_chip_info *chip = rtwdev->chip;
4116 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem;
4117 struct ieee80211_eht_mcs_nss_supp *eht_nss;
4118 struct ieee80211_sta_eht_cap *eht_cap;
4119 struct rtw89_hal *hal = &rtwdev->hal;
4120 bool support_320mhz = false;
4121 int sts = 8;
4122 u8 val;
4123
4124 if (chip->chip_gen == RTW89_CHIP_AX)
4125 return;
4126
4127 if (band == NL80211_BAND_6GHZ &&
4128 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320))
4129 support_320mhz = true;
4130
4131 eht_cap = &iftype_data->eht_cap;
4132 eht_cap_elem = &eht_cap->eht_cap_elem;
4133 eht_nss = &eht_cap->eht_mcs_nss_supp;
4134
4135 eht_cap->has_eht = true;
4136
4137 eht_cap_elem->mac_cap_info[0] =
4138 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991,
4139 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
4140 eht_cap_elem->mac_cap_info[1] = 0;
4141
4142 eht_cap_elem->phy_cap_info[0] =
4143 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
4144 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE;
4145 if (support_320mhz)
4146 eht_cap_elem->phy_cap_info[0] |=
4147 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
4148
4149 eht_cap_elem->phy_cap_info[0] |=
4150 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)),
4151 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK);
4152 eht_cap_elem->phy_cap_info[1] =
4153 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)),
4154 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) |
4155 u8_encode_bits(sts - 1,
4156 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK);
4157 if (support_320mhz)
4158 eht_cap_elem->phy_cap_info[1] |=
4159 u8_encode_bits(sts - 1,
4160 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK);
4161
4162 eht_cap_elem->phy_cap_info[2] = 0;
4163
4164 eht_cap_elem->phy_cap_info[3] =
4165 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
4166 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
4167 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
4168 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK;
4169
4170 eht_cap_elem->phy_cap_info[4] =
4171 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP |
4172 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK);
4173
4174 eht_cap_elem->phy_cap_info[5] =
4175 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US,
4176 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK);
4177
4178 eht_cap_elem->phy_cap_info[6] = 0;
4179 eht_cap_elem->phy_cap_info[7] = 0;
4180 eht_cap_elem->phy_cap_info[8] = 0;
4181
4182 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) |
4183 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX);
4184 eht_nss->bw._80.rx_tx_mcs9_max_nss = val;
4185 eht_nss->bw._80.rx_tx_mcs11_max_nss = val;
4186 eht_nss->bw._80.rx_tx_mcs13_max_nss = val;
4187 eht_nss->bw._160.rx_tx_mcs9_max_nss = val;
4188 eht_nss->bw._160.rx_tx_mcs11_max_nss = val;
4189 eht_nss->bw._160.rx_tx_mcs13_max_nss = val;
4190 if (support_320mhz) {
4191 eht_nss->bw._320.rx_tx_mcs9_max_nss = val;
4192 eht_nss->bw._320.rx_tx_mcs11_max_nss = val;
4193 eht_nss->bw._320.rx_tx_mcs13_max_nss = val;
4194 }
4195 }
4196
4197 #define RTW89_SBAND_IFTYPES_NR 2
4198
rtw89_init_he_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,struct ieee80211_supported_band * sband)4199 static void rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev,
4200 enum nl80211_band band,
4201 struct ieee80211_supported_band *sband)
4202 {
4203 struct ieee80211_sband_iftype_data *iftype_data;
4204 enum nl80211_iftype iftype;
4205 int idx = 0;
4206
4207 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL);
4208 if (!iftype_data)
4209 return;
4210
4211 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) {
4212 switch (iftype) {
4213 case NL80211_IFTYPE_STATION:
4214 case NL80211_IFTYPE_AP:
4215 break;
4216 default:
4217 continue;
4218 }
4219
4220 if (idx >= RTW89_SBAND_IFTYPES_NR) {
4221 rtw89_warn(rtwdev, "run out of iftype_data\n");
4222 break;
4223 }
4224
4225 iftype_data[idx].types_mask = BIT(iftype);
4226
4227 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]);
4228 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]);
4229
4230 idx++;
4231 }
4232
4233 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx);
4234 }
4235
rtw89_core_set_supported_band(struct rtw89_dev * rtwdev)4236 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev)
4237 {
4238 struct ieee80211_hw *hw = rtwdev->hw;
4239 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL;
4240 struct ieee80211_supported_band *sband_6ghz = NULL;
4241 u32 size = sizeof(struct ieee80211_supported_band);
4242 u8 support_bands = rtwdev->chip->support_bands;
4243
4244 if (support_bands & BIT(NL80211_BAND_2GHZ)) {
4245 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL);
4246 if (!sband_2ghz)
4247 goto err;
4248 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap);
4249 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz);
4250 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz;
4251 }
4252
4253 if (support_bands & BIT(NL80211_BAND_5GHZ)) {
4254 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL);
4255 if (!sband_5ghz)
4256 goto err;
4257 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap);
4258 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap);
4259 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz);
4260 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz;
4261 }
4262
4263 if (support_bands & BIT(NL80211_BAND_6GHZ)) {
4264 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL);
4265 if (!sband_6ghz)
4266 goto err;
4267 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz);
4268 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz;
4269 }
4270
4271 return 0;
4272
4273 err:
4274 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
4275 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL;
4276 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL;
4277 if (sband_2ghz)
4278 kfree((__force void *)sband_2ghz->iftype_data);
4279 if (sband_5ghz)
4280 kfree((__force void *)sband_5ghz->iftype_data);
4281 if (sband_6ghz)
4282 kfree((__force void *)sband_6ghz->iftype_data);
4283 kfree(sband_2ghz);
4284 kfree(sband_5ghz);
4285 kfree(sband_6ghz);
4286 return -ENOMEM;
4287 }
4288
rtw89_core_clr_supported_band(struct rtw89_dev * rtwdev)4289 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev)
4290 {
4291 struct ieee80211_hw *hw = rtwdev->hw;
4292
4293 if (hw->wiphy->bands[NL80211_BAND_2GHZ])
4294 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data);
4295 if (hw->wiphy->bands[NL80211_BAND_5GHZ])
4296 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data);
4297 if (hw->wiphy->bands[NL80211_BAND_6GHZ])
4298 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data);
4299 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
4300 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
4301 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]);
4302 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
4303 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL;
4304 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL;
4305 }
4306
rtw89_core_ppdu_sts_init(struct rtw89_dev * rtwdev)4307 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev)
4308 {
4309 int i;
4310
4311 for (i = 0; i < RTW89_PHY_MAX; i++)
4312 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]);
4313 for (i = 0; i < RTW89_PHY_MAX; i++)
4314 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX;
4315 }
4316
rtw89_core_update_beacon_work(struct work_struct * work)4317 void rtw89_core_update_beacon_work(struct work_struct *work)
4318 {
4319 struct rtw89_dev *rtwdev;
4320 struct rtw89_vif_link *rtwvif_link = container_of(work, struct rtw89_vif_link,
4321 update_beacon_work);
4322
4323 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE)
4324 return;
4325
4326 rtwdev = rtwvif_link->rtwvif->rtwdev;
4327
4328 mutex_lock(&rtwdev->mutex);
4329 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link);
4330 mutex_unlock(&rtwdev->mutex);
4331 }
4332
rtw89_wait_for_cond(struct rtw89_wait_info * wait,unsigned int cond)4333 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond)
4334 {
4335 struct completion *cmpl = &wait->completion;
4336 unsigned long time_left;
4337 unsigned int cur;
4338
4339 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond);
4340 if (cur != RTW89_WAIT_COND_IDLE)
4341 return -EBUSY;
4342
4343 time_left = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT);
4344 if (time_left == 0) {
4345 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
4346 return -ETIMEDOUT;
4347 }
4348
4349 if (wait->data.err)
4350 return -EFAULT;
4351
4352 return 0;
4353 }
4354
rtw89_complete_cond(struct rtw89_wait_info * wait,unsigned int cond,const struct rtw89_completion_data * data)4355 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
4356 const struct rtw89_completion_data *data)
4357 {
4358 unsigned int cur;
4359
4360 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE);
4361 if (cur != cond)
4362 return;
4363
4364 wait->data = *data;
4365 complete(&wait->completion);
4366 }
4367
rtw89_core_ntfy_btc_event(struct rtw89_dev * rtwdev,enum rtw89_btc_hmsg event)4368 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event)
4369 {
4370 u16 bt_req_len;
4371
4372 switch (event) {
4373 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT:
4374 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0);
4375 rtw89_debug(rtwdev, RTW89_DBG_BTC,
4376 "coex updates BT req len to %d TU\n", bt_req_len);
4377 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE);
4378 break;
4379 default:
4380 if (event < NUM_OF_RTW89_BTC_HMSG)
4381 rtw89_debug(rtwdev, RTW89_DBG_BTC,
4382 "unhandled BTC HMSG event: %d\n", event);
4383 else
4384 rtw89_warn(rtwdev,
4385 "unrecognized BTC HMSG event: %d\n", event);
4386 break;
4387 }
4388 }
4389
rtw89_check_quirks(struct rtw89_dev * rtwdev,const struct dmi_system_id * quirks)4390 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks)
4391 {
4392 const struct dmi_system_id *match;
4393 enum rtw89_quirks quirk;
4394
4395 if (!quirks)
4396 return;
4397
4398 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) {
4399 quirk = (uintptr_t)match->driver_data;
4400 if (quirk >= NUM_OF_RTW89_QUIRKS)
4401 continue;
4402
4403 set_bit(quirk, rtwdev->quirks);
4404 }
4405 }
4406 EXPORT_SYMBOL(rtw89_check_quirks);
4407
rtw89_core_start(struct rtw89_dev * rtwdev)4408 int rtw89_core_start(struct rtw89_dev *rtwdev)
4409 {
4410 int ret;
4411
4412 ret = rtw89_mac_init(rtwdev);
4413 if (ret) {
4414 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret);
4415 return ret;
4416 }
4417
4418 rtw89_btc_ntfy_poweron(rtwdev);
4419
4420 /* efuse process */
4421
4422 /* pre-config BB/RF, BB reset/RFC reset */
4423 ret = rtw89_chip_reset_bb_rf(rtwdev);
4424 if (ret)
4425 return ret;
4426
4427 rtw89_phy_init_bb_reg(rtwdev);
4428 rtw89_chip_bb_postinit(rtwdev);
4429 rtw89_phy_init_rf_reg(rtwdev, false);
4430
4431 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL);
4432
4433 rtw89_phy_dm_init(rtwdev);
4434
4435 rtw89_mac_cfg_ppdu_status_bands(rtwdev, true);
4436 rtw89_mac_update_rts_threshold(rtwdev);
4437
4438 rtw89_tas_reset(rtwdev);
4439
4440 ret = rtw89_hci_start(rtwdev);
4441 if (ret) {
4442 rtw89_err(rtwdev, "failed to start hci\n");
4443 return ret;
4444 }
4445
4446 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
4447 RTW89_TRACK_WORK_PERIOD);
4448
4449 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
4450
4451 rtw89_chip_rfk_init_late(rtwdev);
4452 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON);
4453 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable);
4454 rtw89_fw_h2c_init_ba_cam(rtwdev);
4455
4456 return 0;
4457 }
4458
rtw89_core_stop(struct rtw89_dev * rtwdev)4459 void rtw89_core_stop(struct rtw89_dev *rtwdev)
4460 {
4461 struct rtw89_btc *btc = &rtwdev->btc;
4462
4463 /* Prvent to stop twice; enter_ips and ops_stop */
4464 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
4465 return;
4466
4467 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF);
4468
4469 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
4470
4471 mutex_unlock(&rtwdev->mutex);
4472
4473 cancel_work_sync(&rtwdev->c2h_work);
4474 cancel_work_sync(&rtwdev->cancel_6ghz_probe_work);
4475 cancel_work_sync(&btc->eapol_notify_work);
4476 cancel_work_sync(&btc->arp_notify_work);
4477 cancel_work_sync(&btc->dhcp_notify_work);
4478 cancel_work_sync(&btc->icmp_notify_work);
4479 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work);
4480 cancel_delayed_work_sync(&rtwdev->track_work);
4481 cancel_delayed_work_sync(&rtwdev->chanctx_work);
4482 cancel_delayed_work_sync(&rtwdev->coex_act1_work);
4483 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work);
4484 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work);
4485 cancel_delayed_work_sync(&rtwdev->cfo_track_work);
4486 cancel_delayed_work_sync(&rtwdev->forbid_ba_work);
4487 cancel_delayed_work_sync(&rtwdev->antdiv_work);
4488
4489 mutex_lock(&rtwdev->mutex);
4490
4491 rtw89_btc_ntfy_poweroff(rtwdev);
4492 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
4493 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
4494 rtw89_hci_stop(rtwdev);
4495 rtw89_hci_deinit(rtwdev);
4496 rtw89_mac_pwr_off(rtwdev);
4497 rtw89_hci_reset(rtwdev);
4498 }
4499
rtw89_acquire_mac_id(struct rtw89_dev * rtwdev)4500 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev)
4501 {
4502 const struct rtw89_chip_info *chip = rtwdev->chip;
4503 u8 mac_id_num;
4504 u8 mac_id;
4505
4506 if (rtwdev->support_mlo)
4507 mac_id_num = chip->support_macid_num / chip->support_link_num;
4508 else
4509 mac_id_num = chip->support_macid_num;
4510
4511 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num);
4512 if (mac_id == mac_id_num)
4513 return RTW89_MAX_MAC_ID_NUM;
4514
4515 set_bit(mac_id, rtwdev->mac_id_map);
4516 return mac_id;
4517 }
4518
rtw89_release_mac_id(struct rtw89_dev * rtwdev,u8 mac_id)4519 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id)
4520 {
4521 clear_bit(mac_id, rtwdev->mac_id_map);
4522 }
4523
rtw89_init_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u8 mac_id,u8 port)4524 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4525 u8 mac_id, u8 port)
4526 {
4527 const struct rtw89_chip_info *chip = rtwdev->chip;
4528 u8 support_link_num = chip->support_link_num;
4529 u8 support_mld_num = 0;
4530 unsigned int link_id;
4531 u8 index;
4532
4533 bitmap_zero(rtwvif->links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
4534 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++)
4535 rtwvif->links[link_id] = NULL;
4536
4537 rtwvif->rtwdev = rtwdev;
4538
4539 if (rtwdev->support_mlo) {
4540 rtwvif->links_inst_valid_num = support_link_num;
4541 support_mld_num = chip->support_macid_num / support_link_num;
4542 } else {
4543 rtwvif->links_inst_valid_num = 1;
4544 }
4545
4546 for (index = 0; index < rtwvif->links_inst_valid_num; index++) {
4547 struct rtw89_vif_link *inst = &rtwvif->links_inst[index];
4548
4549 inst->rtwvif = rtwvif;
4550 inst->mac_id = mac_id + index * support_mld_num;
4551 inst->mac_idx = RTW89_MAC_0 + index;
4552 inst->phy_idx = RTW89_PHY_0 + index;
4553
4554 /* multi-link use the same port id on different HW bands */
4555 inst->port = port;
4556 }
4557 }
4558
rtw89_init_sta(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta,u8 mac_id)4559 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4560 struct rtw89_sta *rtwsta, u8 mac_id)
4561 {
4562 const struct rtw89_chip_info *chip = rtwdev->chip;
4563 u8 support_link_num = chip->support_link_num;
4564 u8 support_mld_num = 0;
4565 unsigned int link_id;
4566 u8 index;
4567
4568 bitmap_zero(rtwsta->links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
4569 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++)
4570 rtwsta->links[link_id] = NULL;
4571
4572 rtwsta->rtwdev = rtwdev;
4573 rtwsta->rtwvif = rtwvif;
4574
4575 if (rtwdev->support_mlo) {
4576 rtwsta->links_inst_valid_num = support_link_num;
4577 support_mld_num = chip->support_macid_num / support_link_num;
4578 } else {
4579 rtwsta->links_inst_valid_num = 1;
4580 }
4581
4582 for (index = 0; index < rtwsta->links_inst_valid_num; index++) {
4583 struct rtw89_sta_link *inst = &rtwsta->links_inst[index];
4584
4585 inst->rtwvif_link = &rtwvif->links_inst[index];
4586
4587 inst->rtwsta = rtwsta;
4588 inst->mac_id = mac_id + index * support_mld_num;
4589 }
4590 }
4591
rtw89_vif_set_link(struct rtw89_vif * rtwvif,unsigned int link_id)4592 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif,
4593 unsigned int link_id)
4594 {
4595 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id];
4596 u8 index;
4597 int ret;
4598
4599 if (rtwvif_link)
4600 return rtwvif_link;
4601
4602 index = find_first_zero_bit(rtwvif->links_inst_map,
4603 rtwvif->links_inst_valid_num);
4604 if (index == rtwvif->links_inst_valid_num) {
4605 ret = -EBUSY;
4606 goto err;
4607 }
4608
4609 rtwvif_link = &rtwvif->links_inst[index];
4610 rtwvif_link->link_id = link_id;
4611
4612 set_bit(index, rtwvif->links_inst_map);
4613 rtwvif->links[link_id] = rtwvif_link;
4614 return rtwvif_link;
4615
4616 err:
4617 rtw89_err(rtwvif->rtwdev, "vif (link_id %u) failed to set link: %d\n",
4618 link_id, ret);
4619 return NULL;
4620 }
4621
rtw89_vif_unset_link(struct rtw89_vif * rtwvif,unsigned int link_id)4622 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id)
4623 {
4624 struct rtw89_vif_link **container = &rtwvif->links[link_id];
4625 struct rtw89_vif_link *link = *container;
4626 u8 index;
4627
4628 if (!link)
4629 return;
4630
4631 index = rtw89_vif_link_inst_get_index(link);
4632 clear_bit(index, rtwvif->links_inst_map);
4633 *container = NULL;
4634 }
4635
rtw89_sta_set_link(struct rtw89_sta * rtwsta,unsigned int link_id)4636 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta,
4637 unsigned int link_id)
4638 {
4639 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
4640 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id];
4641 struct rtw89_sta_link *rtwsta_link = rtwsta->links[link_id];
4642 u8 index;
4643 int ret;
4644
4645 if (rtwsta_link)
4646 return rtwsta_link;
4647
4648 if (!rtwvif_link) {
4649 ret = -ENOLINK;
4650 goto err;
4651 }
4652
4653 index = rtw89_vif_link_inst_get_index(rtwvif_link);
4654 if (test_bit(index, rtwsta->links_inst_map)) {
4655 ret = -EBUSY;
4656 goto err;
4657 }
4658
4659 rtwsta_link = &rtwsta->links_inst[index];
4660 rtwsta_link->link_id = link_id;
4661
4662 set_bit(index, rtwsta->links_inst_map);
4663 rtwsta->links[link_id] = rtwsta_link;
4664 return rtwsta_link;
4665
4666 err:
4667 rtw89_err(rtwsta->rtwdev, "sta (link_id %u) failed to set link: %d\n",
4668 link_id, ret);
4669 return NULL;
4670 }
4671
rtw89_sta_unset_link(struct rtw89_sta * rtwsta,unsigned int link_id)4672 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id)
4673 {
4674 struct rtw89_sta_link **container = &rtwsta->links[link_id];
4675 struct rtw89_sta_link *link = *container;
4676 u8 index;
4677
4678 if (!link)
4679 return;
4680
4681 index = rtw89_sta_link_inst_get_index(link);
4682 clear_bit(index, rtwsta->links_inst_map);
4683 *container = NULL;
4684 }
4685
rtw89_core_init(struct rtw89_dev * rtwdev)4686 int rtw89_core_init(struct rtw89_dev *rtwdev)
4687 {
4688 struct rtw89_btc *btc = &rtwdev->btc;
4689 u8 band;
4690
4691 INIT_LIST_HEAD(&rtwdev->ba_list);
4692 INIT_LIST_HEAD(&rtwdev->forbid_ba_list);
4693 INIT_LIST_HEAD(&rtwdev->rtwvifs_list);
4694 INIT_LIST_HEAD(&rtwdev->early_h2c_list);
4695 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) {
4696 if (!(rtwdev->chip->support_bands & BIT(band)))
4697 continue;
4698 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]);
4699 }
4700 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work);
4701 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work);
4702 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work);
4703 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work);
4704 INIT_DELAYED_WORK(&rtwdev->chanctx_work, rtw89_chanctx_work);
4705 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work);
4706 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work);
4707 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work);
4708 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work);
4709 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work);
4710 INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work);
4711 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
4712 if (!rtwdev->txq_wq)
4713 return -ENOMEM;
4714 spin_lock_init(&rtwdev->ba_lock);
4715 spin_lock_init(&rtwdev->rpwm_lock);
4716 mutex_init(&rtwdev->mutex);
4717 mutex_init(&rtwdev->rf_mutex);
4718 rtwdev->total_sta_assoc = 0;
4719
4720 rtw89_init_wait(&rtwdev->mcc.wait);
4721 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait);
4722 rtw89_init_wait(&rtwdev->wow.wait);
4723 rtw89_init_wait(&rtwdev->mac.ps_wait);
4724
4725 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work);
4726 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work);
4727 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work);
4728 INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work);
4729
4730 skb_queue_head_init(&rtwdev->c2h_queue);
4731 rtw89_core_ppdu_sts_init(rtwdev);
4732 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats);
4733
4734 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR;
4735 rtwdev->dbcc_en = false;
4736 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT;
4737 rtwdev->mac.qta_mode = RTW89_QTA_SCC;
4738
4739 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
4740 rtwdev->dbcc_en = true;
4741 rtwdev->mac.qta_mode = RTW89_QTA_DBCC;
4742 rtwdev->mlo_dbcc_mode = MLO_2_PLUS_0_1RF;
4743 }
4744
4745 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work);
4746 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work);
4747 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work);
4748 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work);
4749
4750 init_completion(&rtwdev->fw.req.completion);
4751 init_completion(&rtwdev->rfk_wait.completion);
4752
4753 schedule_work(&rtwdev->load_firmware_work);
4754
4755 rtw89_ser_init(rtwdev);
4756 rtw89_entity_init(rtwdev);
4757 rtw89_tas_init(rtwdev);
4758
4759 return 0;
4760 }
4761 EXPORT_SYMBOL(rtw89_core_init);
4762
rtw89_core_deinit(struct rtw89_dev * rtwdev)4763 void rtw89_core_deinit(struct rtw89_dev *rtwdev)
4764 {
4765 rtw89_ser_deinit(rtwdev);
4766 rtw89_unload_firmware(rtwdev);
4767 rtw89_fw_free_all_early_h2c(rtwdev);
4768
4769 destroy_workqueue(rtwdev->txq_wq);
4770 mutex_destroy(&rtwdev->rf_mutex);
4771 mutex_destroy(&rtwdev->mutex);
4772 }
4773 EXPORT_SYMBOL(rtw89_core_deinit);
4774
rtw89_core_scan_start(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,const u8 * mac_addr,bool hw_scan)4775 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4776 const u8 *mac_addr, bool hw_scan)
4777 {
4778 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
4779 rtwvif_link->chanctx_idx);
4780
4781 rtwdev->scanning = true;
4782 rtw89_leave_lps(rtwdev);
4783 if (hw_scan)
4784 rtw89_leave_ips_by_hwflags(rtwdev);
4785
4786 ether_addr_copy(rtwvif_link->mac_addr, mac_addr);
4787 rtw89_btc_ntfy_scan_start(rtwdev, rtwvif_link->phy_idx, chan->band_type);
4788 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, true);
4789 rtw89_hci_recalc_int_mit(rtwdev);
4790 rtw89_phy_config_edcca(rtwdev, true);
4791
4792 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr);
4793 }
4794
rtw89_core_scan_complete(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool hw_scan)4795 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
4796 struct rtw89_vif_link *rtwvif_link, bool hw_scan)
4797 {
4798 struct ieee80211_bss_conf *bss_conf;
4799
4800 if (!rtwvif_link)
4801 return;
4802
4803 rcu_read_lock();
4804
4805 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
4806 ether_addr_copy(rtwvif_link->mac_addr, bss_conf->addr);
4807
4808 rcu_read_unlock();
4809
4810 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL);
4811
4812 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false);
4813 rtw89_btc_ntfy_scan_finish(rtwdev, rtwvif_link->phy_idx);
4814 rtw89_phy_config_edcca(rtwdev, false);
4815
4816 rtwdev->scanning = false;
4817 rtwdev->dig.bypass_dig = true;
4818 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
4819 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
4820 }
4821
rtw89_read_chip_ver(struct rtw89_dev * rtwdev)4822 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
4823 {
4824 const struct rtw89_chip_info *chip = rtwdev->chip;
4825 int ret;
4826 u8 val;
4827 u8 cv;
4828
4829 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK);
4830 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) {
4831 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD)
4832 cv = CHIP_CAV;
4833 else
4834 cv = CHIP_CBV;
4835 }
4836
4837 rtwdev->hal.cv = cv;
4838
4839 if (rtw89_is_rtl885xb(rtwdev)) {
4840 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val);
4841 if (ret)
4842 return;
4843
4844 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK);
4845 }
4846 }
4847
rtw89_core_setup_phycap(struct rtw89_dev * rtwdev)4848 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev)
4849 {
4850 const struct rtw89_chip_info *chip = rtwdev->chip;
4851
4852 rtwdev->hal.support_cckpd =
4853 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) &&
4854 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV);
4855 rtwdev->hal.support_igi =
4856 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV;
4857
4858 if (test_bit(RTW89_QUIRK_THERMAL_PROT_120C, rtwdev->quirks))
4859 rtwdev->hal.thermal_prot_th = chip->thermal_th[1];
4860 else if (test_bit(RTW89_QUIRK_THERMAL_PROT_110C, rtwdev->quirks))
4861 rtwdev->hal.thermal_prot_th = chip->thermal_th[0];
4862 else
4863 rtwdev->hal.thermal_prot_th = 0;
4864 }
4865
rtw89_core_setup_rfe_parms(struct rtw89_dev * rtwdev)4866 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev)
4867 {
4868 const struct rtw89_chip_info *chip = rtwdev->chip;
4869 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf;
4870 struct rtw89_efuse *efuse = &rtwdev->efuse;
4871 const struct rtw89_rfe_parms *sel;
4872 u8 rfe_type = efuse->rfe_type;
4873
4874 if (!conf) {
4875 sel = chip->dflt_parms;
4876 goto out;
4877 }
4878
4879 while (conf->rfe_parms) {
4880 if (rfe_type == conf->rfe_type) {
4881 sel = conf->rfe_parms;
4882 goto out;
4883 }
4884 conf++;
4885 }
4886
4887 sel = chip->dflt_parms;
4888
4889 out:
4890 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel);
4891 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl);
4892 }
4893
rtw89_chip_efuse_info_setup(struct rtw89_dev * rtwdev)4894 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev)
4895 {
4896 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4897 int ret;
4898
4899 ret = rtw89_mac_partial_init(rtwdev, false);
4900 if (ret)
4901 return ret;
4902
4903 ret = mac->parse_efuse_map(rtwdev);
4904 if (ret)
4905 return ret;
4906
4907 ret = mac->parse_phycap_map(rtwdev);
4908 if (ret)
4909 return ret;
4910
4911 ret = rtw89_mac_setup_phycap(rtwdev);
4912 if (ret)
4913 return ret;
4914
4915 rtw89_core_setup_phycap(rtwdev);
4916
4917 rtw89_hci_mac_pre_deinit(rtwdev);
4918
4919 rtw89_mac_pwr_off(rtwdev);
4920
4921 return 0;
4922 }
4923
rtw89_chip_board_info_setup(struct rtw89_dev * rtwdev)4924 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev)
4925 {
4926 rtw89_chip_fem_setup(rtwdev);
4927
4928 return 0;
4929 }
4930
rtw89_chip_has_rfkill(struct rtw89_dev * rtwdev)4931 static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev)
4932 {
4933 return !!rtwdev->chip->rfkill_init;
4934 }
4935
rtw89_core_rfkill_init(struct rtw89_dev * rtwdev)4936 static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev)
4937 {
4938 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init;
4939
4940 rtw89_write16_mask(rtwdev, regs->pinmux.addr,
4941 regs->pinmux.mask, regs->pinmux.data);
4942 rtw89_write16_mask(rtwdev, regs->mode.addr,
4943 regs->mode.mask, regs->mode.data);
4944 }
4945
rtw89_core_rfkill_get(struct rtw89_dev * rtwdev)4946 static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev)
4947 {
4948 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get;
4949
4950 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask);
4951 }
4952
rtw89_rfkill_polling_init(struct rtw89_dev * rtwdev)4953 static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev)
4954 {
4955 if (!rtw89_chip_has_rfkill(rtwdev))
4956 return;
4957
4958 rtw89_core_rfkill_init(rtwdev);
4959 rtw89_core_rfkill_poll(rtwdev, true);
4960 wiphy_rfkill_start_polling(rtwdev->hw->wiphy);
4961 }
4962
rtw89_rfkill_polling_deinit(struct rtw89_dev * rtwdev)4963 static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev)
4964 {
4965 if (!rtw89_chip_has_rfkill(rtwdev))
4966 return;
4967
4968 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy);
4969 }
4970
rtw89_core_rfkill_poll(struct rtw89_dev * rtwdev,bool force)4971 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force)
4972 {
4973 bool prev, blocked;
4974
4975 if (!rtw89_chip_has_rfkill(rtwdev))
4976 return;
4977
4978 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
4979 blocked = rtw89_core_rfkill_get(rtwdev);
4980
4981 if (!force && prev == blocked)
4982 return;
4983
4984 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n",
4985 blocked ? "disable" : "enable");
4986
4987 if (blocked)
4988 set_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
4989 else
4990 clear_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
4991
4992 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked);
4993 }
4994
rtw89_chip_info_setup(struct rtw89_dev * rtwdev)4995 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev)
4996 {
4997 int ret;
4998
4999 rtw89_read_chip_ver(rtwdev);
5000
5001 ret = rtw89_wait_firmware_completion(rtwdev);
5002 if (ret) {
5003 rtw89_err(rtwdev, "failed to wait firmware completion\n");
5004 return ret;
5005 }
5006
5007 ret = rtw89_fw_recognize(rtwdev);
5008 if (ret) {
5009 rtw89_err(rtwdev, "failed to recognize firmware\n");
5010 return ret;
5011 }
5012
5013 ret = rtw89_chip_efuse_info_setup(rtwdev);
5014 if (ret)
5015 return ret;
5016
5017 ret = rtw89_fw_recognize_elements(rtwdev);
5018 if (ret) {
5019 rtw89_err(rtwdev, "failed to recognize firmware elements\n");
5020 return ret;
5021 }
5022
5023 ret = rtw89_chip_board_info_setup(rtwdev);
5024 if (ret)
5025 return ret;
5026
5027 rtw89_core_setup_rfe_parms(rtwdev);
5028 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev);
5029
5030 return 0;
5031 }
5032 EXPORT_SYMBOL(rtw89_chip_info_setup);
5033
rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)5034 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
5035 struct rtw89_vif_link *rtwvif_link)
5036 {
5037 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5038 const struct rtw89_chip_info *chip = rtwdev->chip;
5039 struct ieee80211_bss_conf *bss_conf;
5040
5041 rcu_read_lock();
5042
5043 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
5044 if (!bss_conf->he_support || !vif->cfg.assoc) {
5045 rcu_read_unlock();
5046 return;
5047 }
5048
5049 rcu_read_unlock();
5050
5051 if (chip->ops->set_txpwr_ul_tb_offset)
5052 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif_link->mac_idx);
5053 }
5054
rtw89_core_register_hw(struct rtw89_dev * rtwdev)5055 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev)
5056 {
5057 const struct rtw89_chip_info *chip = rtwdev->chip;
5058 u8 n = rtwdev->support_mlo ? chip->support_link_num : 1;
5059 struct ieee80211_hw *hw = rtwdev->hw;
5060 struct rtw89_efuse *efuse = &rtwdev->efuse;
5061 struct rtw89_hal *hal = &rtwdev->hal;
5062 int ret;
5063 int tx_headroom = IEEE80211_HT_CTL_LEN;
5064
5065 hw->vif_data_size = struct_size_t(struct rtw89_vif, links_inst, n);
5066 hw->sta_data_size = struct_size_t(struct rtw89_sta, links_inst, n);
5067 hw->txq_data_size = sizeof(struct rtw89_txq);
5068 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg);
5069
5070 SET_IEEE80211_PERM_ADDR(hw, efuse->addr);
5071
5072 hw->extra_tx_headroom = tx_headroom;
5073 hw->queues = IEEE80211_NUM_ACS;
5074 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM;
5075 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM;
5076 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL;
5077
5078 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC |
5079 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
5080 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC;
5081
5082 ieee80211_hw_set(hw, SIGNAL_DBM);
5083 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
5084 ieee80211_hw_set(hw, MFP_CAPABLE);
5085 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
5086 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
5087 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
5088 ieee80211_hw_set(hw, TX_AMSDU);
5089 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
5090 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
5091 ieee80211_hw_set(hw, SUPPORTS_PS);
5092 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
5093 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
5094 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
5095 ieee80211_hw_set(hw, WANT_MONITOR_VIF);
5096
5097 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
5098 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
5099
5100 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw))
5101 ieee80211_hw_set(hw, CONNECTION_MONITOR);
5102
5103 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
5104 BIT(NL80211_IFTYPE_AP) |
5105 BIT(NL80211_IFTYPE_P2P_CLIENT) |
5106 BIT(NL80211_IFTYPE_P2P_GO);
5107
5108 if (hal->ant_diversity) {
5109 hw->wiphy->available_antennas_tx = 0x3;
5110 hw->wiphy->available_antennas_rx = 0x3;
5111 } else {
5112 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1;
5113 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1;
5114 }
5115
5116 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
5117 WIPHY_FLAG_TDLS_EXTERNAL_SETUP |
5118 WIPHY_FLAG_AP_UAPSD |
5119 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK;
5120
5121 if (!chip->support_rnr)
5122 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ;
5123
5124 if (chip->chip_gen == RTW89_CHIP_BE)
5125 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT;
5126
5127 if (rtwdev->support_mlo)
5128 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO;
5129
5130 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
5131
5132 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
5133 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN;
5134
5135 #ifdef CONFIG_PM
5136 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
5137 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
5138 #endif
5139
5140 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
5141 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
5142 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
5143 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
5144 hw->wiphy->max_remain_on_channel_duration = 1000;
5145
5146 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
5147 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
5148 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
5149
5150 ret = rtw89_core_set_supported_band(rtwdev);
5151 if (ret) {
5152 rtw89_err(rtwdev, "failed to set supported band\n");
5153 return ret;
5154 }
5155
5156 ret = rtw89_regd_setup(rtwdev);
5157 if (ret) {
5158 rtw89_err(rtwdev, "failed to set up regd\n");
5159 goto err_free_supported_band;
5160 }
5161
5162 hw->wiphy->sar_capa = &rtw89_sar_capa;
5163
5164 ret = ieee80211_register_hw(hw);
5165 if (ret) {
5166 rtw89_err(rtwdev, "failed to register hw\n");
5167 goto err_free_supported_band;
5168 }
5169
5170 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier);
5171 if (ret) {
5172 rtw89_err(rtwdev, "failed to init regd\n");
5173 goto err_unregister_hw;
5174 }
5175
5176 rtw89_rfkill_polling_init(rtwdev);
5177
5178 return 0;
5179
5180 err_unregister_hw:
5181 ieee80211_unregister_hw(hw);
5182 err_free_supported_band:
5183 rtw89_core_clr_supported_band(rtwdev);
5184
5185 return ret;
5186 }
5187
rtw89_core_unregister_hw(struct rtw89_dev * rtwdev)5188 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev)
5189 {
5190 struct ieee80211_hw *hw = rtwdev->hw;
5191
5192 rtw89_rfkill_polling_deinit(rtwdev);
5193 ieee80211_unregister_hw(hw);
5194 rtw89_core_clr_supported_band(rtwdev);
5195 }
5196
rtw89_core_register(struct rtw89_dev * rtwdev)5197 int rtw89_core_register(struct rtw89_dev *rtwdev)
5198 {
5199 int ret;
5200
5201 ret = rtw89_core_register_hw(rtwdev);
5202 if (ret) {
5203 rtw89_err(rtwdev, "failed to register core hw\n");
5204 return ret;
5205 }
5206
5207 rtw89_debugfs_init(rtwdev);
5208
5209 return 0;
5210 }
5211 EXPORT_SYMBOL(rtw89_core_register);
5212
rtw89_core_unregister(struct rtw89_dev * rtwdev)5213 void rtw89_core_unregister(struct rtw89_dev *rtwdev)
5214 {
5215 rtw89_core_unregister_hw(rtwdev);
5216
5217 rtw89_debugfs_deinit(rtwdev);
5218 }
5219 EXPORT_SYMBOL(rtw89_core_unregister);
5220
rtw89_alloc_ieee80211_hw(struct device * device,u32 bus_data_size,const struct rtw89_chip_info * chip)5221 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
5222 u32 bus_data_size,
5223 const struct rtw89_chip_info *chip)
5224 {
5225 struct rtw89_fw_info early_fw = {};
5226 const struct firmware *firmware;
5227 struct ieee80211_hw *hw;
5228 struct rtw89_dev *rtwdev;
5229 struct ieee80211_ops *ops;
5230 u32 driver_data_size;
5231 int fw_format = -1;
5232 bool support_mlo;
5233 bool no_chanctx;
5234
5235 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format);
5236
5237 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL);
5238 if (!ops)
5239 goto err;
5240
5241 no_chanctx = chip->support_chanctx_num == 0 ||
5242 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) ||
5243 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw);
5244
5245 if (no_chanctx) {
5246 ops->add_chanctx = ieee80211_emulate_add_chanctx;
5247 ops->remove_chanctx = ieee80211_emulate_remove_chanctx;
5248 ops->change_chanctx = ieee80211_emulate_change_chanctx;
5249 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx;
5250 ops->assign_vif_chanctx = NULL;
5251 ops->unassign_vif_chanctx = NULL;
5252 ops->remain_on_channel = NULL;
5253 ops->cancel_remain_on_channel = NULL;
5254 }
5255
5256 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size;
5257 hw = ieee80211_alloc_hw(driver_data_size, ops);
5258 if (!hw)
5259 goto err;
5260
5261 /* TODO: When driver MLO arch. is done, determine whether to support MLO
5262 * according to the following conditions.
5263 * 1. run with chanctx_ops
5264 * 2. chip->support_link_num != 0
5265 * 3. FW feature supports AP_LINK_PS
5266 */
5267 support_mlo = false;
5268
5269 hw->wiphy->iface_combinations = rtw89_iface_combs;
5270
5271 if (no_chanctx || chip->support_chanctx_num == 1)
5272 hw->wiphy->n_iface_combinations = 1;
5273 else
5274 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs);
5275
5276 rtwdev = hw->priv;
5277 rtwdev->hw = hw;
5278 rtwdev->dev = device;
5279 rtwdev->ops = ops;
5280 rtwdev->chip = chip;
5281 rtwdev->fw.req.firmware = firmware;
5282 rtwdev->fw.fw_format = fw_format;
5283 rtwdev->support_mlo = support_mlo;
5284
5285 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s chanctx\n",
5286 no_chanctx ? "without" : "with");
5287 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s MLO cap\n",
5288 support_mlo ? "with" : "without");
5289
5290 return rtwdev;
5291
5292 err:
5293 kfree(ops);
5294 release_firmware(firmware);
5295 return NULL;
5296 }
5297 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw);
5298
rtw89_free_ieee80211_hw(struct rtw89_dev * rtwdev)5299 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev)
5300 {
5301 kfree(rtwdev->ops);
5302 kfree(rtwdev->rfe_data);
5303 release_firmware(rtwdev->fw.req.firmware);
5304 ieee80211_free_hw(rtwdev->hw);
5305 }
5306 EXPORT_SYMBOL(rtw89_free_ieee80211_hw);
5307
5308 MODULE_AUTHOR("Realtek Corporation");
5309 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module");
5310 MODULE_LICENSE("Dual BSD/GPL");
5311