1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #if defined(__FreeBSD__)
6 #define LINUXKPI_PARAM_PREFIX rtw89_
7 #endif
8
9 #include <linux/ip.h>
10 #include <linux/udp.h>
11
12 #include "cam.h"
13 #include "chan.h"
14 #include "coex.h"
15 #include "core.h"
16 #include "efuse.h"
17 #include "fw.h"
18 #include "mac.h"
19 #include "phy.h"
20 #include "ps.h"
21 #include "reg.h"
22 #include "sar.h"
23 #include "ser.h"
24 #include "txrx.h"
25 #include "util.h"
26 #include "wow.h"
27
28 static bool rtw89_disable_ps_mode;
29 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644);
30 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode");
31
32 #if defined(__FreeBSD__)
33 static bool rtw_ht_support = false;
34 module_param_named(support_ht, rtw_ht_support, bool, 0644);
35 MODULE_PARM_DESC(support_ht, "Set to Y to enable HT support");
36
37 static bool rtw_vht_support = false;
38 module_param_named(support_vht, rtw_vht_support, bool, 0644);
39 MODULE_PARM_DESC(support_vht, "Set to Y to enable VHT support");
40
41 static bool rtw_eht_support = false;
42 module_param_named(support_eht, rtw_eht_support, bool, 0644);
43 MODULE_PARM_DESC(support_eht, "Set to Y to enable EHT support");
44 #endif
45
46
47 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \
48 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, }
49 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \
50 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ)
51 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \
52 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ)
53 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \
54 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ)
55 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \
56 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ)
57
58 static struct ieee80211_channel rtw89_channels_2ghz[] = {
59 RTW89_DEF_CHAN_2G(2412, 1),
60 RTW89_DEF_CHAN_2G(2417, 2),
61 RTW89_DEF_CHAN_2G(2422, 3),
62 RTW89_DEF_CHAN_2G(2427, 4),
63 RTW89_DEF_CHAN_2G(2432, 5),
64 RTW89_DEF_CHAN_2G(2437, 6),
65 RTW89_DEF_CHAN_2G(2442, 7),
66 RTW89_DEF_CHAN_2G(2447, 8),
67 RTW89_DEF_CHAN_2G(2452, 9),
68 RTW89_DEF_CHAN_2G(2457, 10),
69 RTW89_DEF_CHAN_2G(2462, 11),
70 RTW89_DEF_CHAN_2G(2467, 12),
71 RTW89_DEF_CHAN_2G(2472, 13),
72 RTW89_DEF_CHAN_2G(2484, 14),
73 };
74
75 static struct ieee80211_channel rtw89_channels_5ghz[] = {
76 RTW89_DEF_CHAN_5G(5180, 36),
77 RTW89_DEF_CHAN_5G(5200, 40),
78 RTW89_DEF_CHAN_5G(5220, 44),
79 RTW89_DEF_CHAN_5G(5240, 48),
80 RTW89_DEF_CHAN_5G(5260, 52),
81 RTW89_DEF_CHAN_5G(5280, 56),
82 RTW89_DEF_CHAN_5G(5300, 60),
83 RTW89_DEF_CHAN_5G(5320, 64),
84 RTW89_DEF_CHAN_5G(5500, 100),
85 RTW89_DEF_CHAN_5G(5520, 104),
86 RTW89_DEF_CHAN_5G(5540, 108),
87 RTW89_DEF_CHAN_5G(5560, 112),
88 RTW89_DEF_CHAN_5G(5580, 116),
89 RTW89_DEF_CHAN_5G(5600, 120),
90 RTW89_DEF_CHAN_5G(5620, 124),
91 RTW89_DEF_CHAN_5G(5640, 128),
92 RTW89_DEF_CHAN_5G(5660, 132),
93 RTW89_DEF_CHAN_5G(5680, 136),
94 RTW89_DEF_CHAN_5G(5700, 140),
95 RTW89_DEF_CHAN_5G(5720, 144),
96 RTW89_DEF_CHAN_5G(5745, 149),
97 RTW89_DEF_CHAN_5G(5765, 153),
98 RTW89_DEF_CHAN_5G(5785, 157),
99 RTW89_DEF_CHAN_5G(5805, 161),
100 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165),
101 RTW89_DEF_CHAN_5G(5845, 169),
102 RTW89_DEF_CHAN_5G(5865, 173),
103 RTW89_DEF_CHAN_5G(5885, 177),
104 };
105
106 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM ==
107 ARRAY_SIZE(rtw89_channels_5ghz));
108
109 static struct ieee80211_channel rtw89_channels_6ghz[] = {
110 RTW89_DEF_CHAN_6G(5955, 1),
111 RTW89_DEF_CHAN_6G(5975, 5),
112 RTW89_DEF_CHAN_6G(5995, 9),
113 RTW89_DEF_CHAN_6G(6015, 13),
114 RTW89_DEF_CHAN_6G(6035, 17),
115 RTW89_DEF_CHAN_6G(6055, 21),
116 RTW89_DEF_CHAN_6G(6075, 25),
117 RTW89_DEF_CHAN_6G(6095, 29),
118 RTW89_DEF_CHAN_6G(6115, 33),
119 RTW89_DEF_CHAN_6G(6135, 37),
120 RTW89_DEF_CHAN_6G(6155, 41),
121 RTW89_DEF_CHAN_6G(6175, 45),
122 RTW89_DEF_CHAN_6G(6195, 49),
123 RTW89_DEF_CHAN_6G(6215, 53),
124 RTW89_DEF_CHAN_6G(6235, 57),
125 RTW89_DEF_CHAN_6G(6255, 61),
126 RTW89_DEF_CHAN_6G(6275, 65),
127 RTW89_DEF_CHAN_6G(6295, 69),
128 RTW89_DEF_CHAN_6G(6315, 73),
129 RTW89_DEF_CHAN_6G(6335, 77),
130 RTW89_DEF_CHAN_6G(6355, 81),
131 RTW89_DEF_CHAN_6G(6375, 85),
132 RTW89_DEF_CHAN_6G(6395, 89),
133 RTW89_DEF_CHAN_6G(6415, 93),
134 RTW89_DEF_CHAN_6G(6435, 97),
135 RTW89_DEF_CHAN_6G(6455, 101),
136 RTW89_DEF_CHAN_6G(6475, 105),
137 RTW89_DEF_CHAN_6G(6495, 109),
138 RTW89_DEF_CHAN_6G(6515, 113),
139 RTW89_DEF_CHAN_6G(6535, 117),
140 RTW89_DEF_CHAN_6G(6555, 121),
141 RTW89_DEF_CHAN_6G(6575, 125),
142 RTW89_DEF_CHAN_6G(6595, 129),
143 RTW89_DEF_CHAN_6G(6615, 133),
144 RTW89_DEF_CHAN_6G(6635, 137),
145 RTW89_DEF_CHAN_6G(6655, 141),
146 RTW89_DEF_CHAN_6G(6675, 145),
147 RTW89_DEF_CHAN_6G(6695, 149),
148 RTW89_DEF_CHAN_6G(6715, 153),
149 RTW89_DEF_CHAN_6G(6735, 157),
150 RTW89_DEF_CHAN_6G(6755, 161),
151 RTW89_DEF_CHAN_6G(6775, 165),
152 RTW89_DEF_CHAN_6G(6795, 169),
153 RTW89_DEF_CHAN_6G(6815, 173),
154 RTW89_DEF_CHAN_6G(6835, 177),
155 RTW89_DEF_CHAN_6G(6855, 181),
156 RTW89_DEF_CHAN_6G(6875, 185),
157 RTW89_DEF_CHAN_6G(6895, 189),
158 RTW89_DEF_CHAN_6G(6915, 193),
159 RTW89_DEF_CHAN_6G(6935, 197),
160 RTW89_DEF_CHAN_6G(6955, 201),
161 RTW89_DEF_CHAN_6G(6975, 205),
162 RTW89_DEF_CHAN_6G(6995, 209),
163 RTW89_DEF_CHAN_6G(7015, 213),
164 RTW89_DEF_CHAN_6G(7035, 217),
165 RTW89_DEF_CHAN_6G(7055, 221),
166 RTW89_DEF_CHAN_6G(7075, 225),
167 RTW89_DEF_CHAN_6G(7095, 229),
168 RTW89_DEF_CHAN_6G(7115, 233),
169 };
170
171 static struct ieee80211_rate rtw89_bitrates[] = {
172 { .bitrate = 10, .hw_value = 0x00, },
173 { .bitrate = 20, .hw_value = 0x01, },
174 { .bitrate = 55, .hw_value = 0x02, },
175 { .bitrate = 110, .hw_value = 0x03, },
176 { .bitrate = 60, .hw_value = 0x04, },
177 { .bitrate = 90, .hw_value = 0x05, },
178 { .bitrate = 120, .hw_value = 0x06, },
179 { .bitrate = 180, .hw_value = 0x07, },
180 { .bitrate = 240, .hw_value = 0x08, },
181 { .bitrate = 360, .hw_value = 0x09, },
182 { .bitrate = 480, .hw_value = 0x0a, },
183 { .bitrate = 540, .hw_value = 0x0b, },
184 };
185
186 static const struct ieee80211_iface_limit rtw89_iface_limits[] = {
187 {
188 .max = 1,
189 .types = BIT(NL80211_IFTYPE_STATION),
190 },
191 {
192 .max = 1,
193 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
194 BIT(NL80211_IFTYPE_P2P_GO) |
195 BIT(NL80211_IFTYPE_AP),
196 },
197 };
198
199 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = {
200 {
201 .max = 1,
202 .types = BIT(NL80211_IFTYPE_STATION),
203 },
204 {
205 .max = 1,
206 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
207 BIT(NL80211_IFTYPE_P2P_GO),
208 },
209 };
210
211 static const struct ieee80211_iface_combination rtw89_iface_combs[] = {
212 {
213 .limits = rtw89_iface_limits,
214 .n_limits = ARRAY_SIZE(rtw89_iface_limits),
215 .max_interfaces = 2,
216 .num_different_channels = 1,
217 },
218 {
219 .limits = rtw89_iface_limits_mcc,
220 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc),
221 .max_interfaces = 2,
222 .num_different_channels = 2,
223 },
224 };
225
rtw89_ra_report_to_bitrate(struct rtw89_dev * rtwdev,u8 rpt_rate,u16 * bitrate)226 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate)
227 {
228 struct ieee80211_rate rate;
229
230 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) {
231 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate);
232 return false;
233 }
234
235 rate = rtw89_bitrates[rpt_rate];
236 *bitrate = rate.bitrate;
237
238 return true;
239 }
240
241 static const struct ieee80211_supported_band rtw89_sband_2ghz = {
242 .band = NL80211_BAND_2GHZ,
243 .channels = rtw89_channels_2ghz,
244 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz),
245 .bitrates = rtw89_bitrates,
246 .n_bitrates = ARRAY_SIZE(rtw89_bitrates),
247 .ht_cap = {0},
248 .vht_cap = {0},
249 };
250
251 static const struct ieee80211_supported_band rtw89_sband_5ghz = {
252 .band = NL80211_BAND_5GHZ,
253 .channels = rtw89_channels_5ghz,
254 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz),
255
256 /* 5G has no CCK rates, 1M/2M/5.5M/11M */
257 .bitrates = rtw89_bitrates + 4,
258 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
259 .ht_cap = {0},
260 .vht_cap = {0},
261 };
262
263 static const struct ieee80211_supported_band rtw89_sband_6ghz = {
264 .band = NL80211_BAND_6GHZ,
265 .channels = rtw89_channels_6ghz,
266 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz),
267
268 /* 6G has no CCK rates, 1M/2M/5.5M/11M */
269 .bitrates = rtw89_bitrates + 4,
270 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
271 };
272
rtw89_traffic_stats_accu(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats,struct sk_buff * skb,bool tx)273 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev,
274 struct rtw89_traffic_stats *stats,
275 struct sk_buff *skb, bool tx)
276 {
277 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
278
279 if (tx && ieee80211_is_assoc_req(hdr->frame_control))
280 rtw89_wow_parse_akm(rtwdev, skb);
281
282 if (!ieee80211_is_data(hdr->frame_control))
283 return;
284
285 if (is_broadcast_ether_addr(hdr->addr1) ||
286 is_multicast_ether_addr(hdr->addr1))
287 return;
288
289 if (tx) {
290 stats->tx_cnt++;
291 stats->tx_unicast += skb->len;
292 } else {
293 stats->rx_cnt++;
294 stats->rx_unicast += skb->len;
295 }
296 }
297
rtw89_get_default_chandef(struct cfg80211_chan_def * chandef)298 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef)
299 {
300 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0],
301 NL80211_CHAN_NO_HT);
302 }
303
rtw89_get_channel_params(const struct cfg80211_chan_def * chandef,struct rtw89_chan * chan)304 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
305 struct rtw89_chan *chan)
306 {
307 struct ieee80211_channel *channel = chandef->chan;
308 enum nl80211_chan_width width = chandef->width;
309 u32 primary_freq, center_freq;
310 u8 center_chan;
311 u8 bandwidth = RTW89_CHANNEL_WIDTH_20;
312 u32 offset;
313 u8 band;
314
315 center_chan = channel->hw_value;
316 primary_freq = channel->center_freq;
317 center_freq = chandef->center_freq1;
318
319 switch (width) {
320 case NL80211_CHAN_WIDTH_20_NOHT:
321 case NL80211_CHAN_WIDTH_20:
322 bandwidth = RTW89_CHANNEL_WIDTH_20;
323 break;
324 case NL80211_CHAN_WIDTH_40:
325 bandwidth = RTW89_CHANNEL_WIDTH_40;
326 if (primary_freq > center_freq) {
327 center_chan -= 2;
328 } else {
329 center_chan += 2;
330 }
331 break;
332 case NL80211_CHAN_WIDTH_80:
333 case NL80211_CHAN_WIDTH_160:
334 bandwidth = nl_to_rtw89_bandwidth(width);
335 if (primary_freq > center_freq) {
336 offset = (primary_freq - center_freq - 10) / 20;
337 center_chan -= 2 + offset * 4;
338 } else {
339 offset = (center_freq - primary_freq - 10) / 20;
340 center_chan += 2 + offset * 4;
341 }
342 break;
343 default:
344 center_chan = 0;
345 break;
346 }
347
348 switch (channel->band) {
349 default:
350 case NL80211_BAND_2GHZ:
351 band = RTW89_BAND_2G;
352 break;
353 case NL80211_BAND_5GHZ:
354 band = RTW89_BAND_5G;
355 break;
356 case NL80211_BAND_6GHZ:
357 band = RTW89_BAND_6G;
358 break;
359 }
360
361 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth);
362 }
363
rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev)364 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev)
365 {
366 struct rtw89_hal *hal = &rtwdev->hal;
367 const struct rtw89_chip_info *chip = rtwdev->chip;
368 const struct rtw89_chan *chan;
369 enum rtw89_sub_entity_idx sub_entity_idx;
370 enum rtw89_sub_entity_idx roc_idx;
371 enum rtw89_phy_idx phy_idx;
372 enum rtw89_entity_mode mode;
373 bool entity_active;
374
375 entity_active = rtw89_get_entity_state(rtwdev);
376 if (!entity_active)
377 return;
378
379 mode = rtw89_get_entity_mode(rtwdev);
380 switch (mode) {
381 case RTW89_ENTITY_MODE_SCC:
382 case RTW89_ENTITY_MODE_MCC:
383 sub_entity_idx = RTW89_SUB_ENTITY_0;
384 break;
385 case RTW89_ENTITY_MODE_MCC_PREPARE:
386 sub_entity_idx = RTW89_SUB_ENTITY_1;
387 break;
388 default:
389 WARN(1, "Invalid ent mode: %d\n", mode);
390 return;
391 }
392
393 roc_idx = atomic_read(&hal->roc_entity_idx);
394 if (roc_idx != RTW89_SUB_ENTITY_IDLE)
395 sub_entity_idx = roc_idx;
396
397 phy_idx = RTW89_PHY_0;
398 chan = rtw89_chan_get(rtwdev, sub_entity_idx);
399 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
400 }
401
rtw89_set_channel(struct rtw89_dev * rtwdev)402 int rtw89_set_channel(struct rtw89_dev *rtwdev)
403 {
404 struct rtw89_hal *hal = &rtwdev->hal;
405 const struct rtw89_chip_info *chip = rtwdev->chip;
406 const struct rtw89_chan_rcd *chan_rcd;
407 const struct rtw89_chan *chan;
408 enum rtw89_sub_entity_idx sub_entity_idx;
409 enum rtw89_sub_entity_idx roc_idx;
410 enum rtw89_mac_idx mac_idx;
411 enum rtw89_phy_idx phy_idx;
412 struct rtw89_channel_help_params bak;
413 enum rtw89_entity_mode mode;
414 bool entity_active;
415
416 entity_active = rtw89_get_entity_state(rtwdev);
417
418 mode = rtw89_entity_recalc(rtwdev);
419 switch (mode) {
420 case RTW89_ENTITY_MODE_SCC:
421 case RTW89_ENTITY_MODE_MCC:
422 sub_entity_idx = RTW89_SUB_ENTITY_0;
423 break;
424 case RTW89_ENTITY_MODE_MCC_PREPARE:
425 sub_entity_idx = RTW89_SUB_ENTITY_1;
426 break;
427 default:
428 WARN(1, "Invalid ent mode: %d\n", mode);
429 return -EINVAL;
430 }
431
432 roc_idx = atomic_read(&hal->roc_entity_idx);
433 if (roc_idx != RTW89_SUB_ENTITY_IDLE)
434 sub_entity_idx = roc_idx;
435
436 mac_idx = RTW89_MAC_0;
437 phy_idx = RTW89_PHY_0;
438
439 chan = rtw89_chan_get(rtwdev, sub_entity_idx);
440 chan_rcd = rtw89_chan_rcd_get(rtwdev, sub_entity_idx);
441
442 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx);
443
444 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx);
445
446 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
447
448 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx);
449
450 if (!entity_active || chan_rcd->band_changed) {
451 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type);
452 rtw89_chip_rfk_band_changed(rtwdev, phy_idx);
453 }
454
455 rtw89_set_entity_state(rtwdev, true);
456 return 0;
457 }
458
rtw89_get_channel(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_chan * chan)459 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
460 struct rtw89_chan *chan)
461 {
462 const struct cfg80211_chan_def *chandef;
463
464 chandef = rtw89_chandef_get(rtwdev, rtwvif->sub_entity_idx);
465 rtw89_get_channel_params(chandef, chan);
466 }
467
468 static enum rtw89_core_tx_type
rtw89_core_get_tx_type(struct rtw89_dev * rtwdev,struct sk_buff * skb)469 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev,
470 struct sk_buff *skb)
471 {
472 struct ieee80211_hdr *hdr = (void *)skb->data;
473 __le16 fc = hdr->frame_control;
474
475 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc))
476 return RTW89_CORE_TX_TYPE_MGMT;
477
478 return RTW89_CORE_TX_TYPE_DATA;
479 }
480
481 static void
rtw89_core_tx_update_ampdu_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)482 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev,
483 struct rtw89_core_tx_request *tx_req,
484 enum btc_pkt_type pkt_type)
485 {
486 struct ieee80211_sta *sta = tx_req->sta;
487 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
488 struct sk_buff *skb = tx_req->skb;
489 struct rtw89_sta *rtwsta;
490 u8 ampdu_num;
491 u8 tid;
492
493 if (pkt_type == PACKET_EAPOL) {
494 desc_info->bk = true;
495 return;
496 }
497
498 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU))
499 return;
500
501 if (!sta) {
502 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n");
503 return;
504 }
505
506 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
507 rtwsta = (struct rtw89_sta *)sta->drv_priv;
508
509 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ?
510 rtwsta->ampdu_params[tid].agg_num :
511 4 << sta->deflink.ht_cap.ampdu_factor) - 1);
512
513 desc_info->agg_en = true;
514 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density;
515 desc_info->ampdu_num = ampdu_num;
516 }
517
518 static void
rtw89_core_tx_update_sec_key(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)519 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev,
520 struct rtw89_core_tx_request *tx_req)
521 {
522 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
523 const struct rtw89_chip_info *chip = rtwdev->chip;
524 const struct rtw89_sec_cam_entry *sec_cam;
525 struct ieee80211_tx_info *info;
526 struct ieee80211_key_conf *key;
527 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
528 struct sk_buff *skb = tx_req->skb;
529 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE;
530 u8 sec_cam_idx;
531 u64 pn64;
532
533 info = IEEE80211_SKB_CB(skb);
534 key = info->control.hw_key;
535 sec_cam_idx = key->hw_key_idx;
536 sec_cam = cam_info->sec_entries[sec_cam_idx];
537 if (!sec_cam) {
538 rtw89_warn(rtwdev, "sec cam entry is empty\n");
539 return;
540 }
541
542 switch (key->cipher) {
543 case WLAN_CIPHER_SUITE_WEP40:
544 sec_type = RTW89_SEC_KEY_TYPE_WEP40;
545 break;
546 case WLAN_CIPHER_SUITE_WEP104:
547 sec_type = RTW89_SEC_KEY_TYPE_WEP104;
548 break;
549 case WLAN_CIPHER_SUITE_TKIP:
550 sec_type = RTW89_SEC_KEY_TYPE_TKIP;
551 break;
552 case WLAN_CIPHER_SUITE_CCMP:
553 sec_type = RTW89_SEC_KEY_TYPE_CCMP128;
554 break;
555 case WLAN_CIPHER_SUITE_CCMP_256:
556 sec_type = RTW89_SEC_KEY_TYPE_CCMP256;
557 break;
558 case WLAN_CIPHER_SUITE_GCMP:
559 sec_type = RTW89_SEC_KEY_TYPE_GCMP128;
560 break;
561 case WLAN_CIPHER_SUITE_GCMP_256:
562 sec_type = RTW89_SEC_KEY_TYPE_GCMP256;
563 break;
564 default:
565 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher);
566 return;
567 }
568
569 desc_info->sec_en = true;
570 desc_info->sec_keyid = key->keyidx;
571 desc_info->sec_type = sec_type;
572 desc_info->sec_cam_idx = sec_cam->sec_cam_idx;
573
574 if (!chip->hw_sec_hdr)
575 return;
576
577 pn64 = atomic64_inc_return(&key->tx_pn);
578 desc_info->sec_seq[0] = pn64;
579 desc_info->sec_seq[1] = pn64 >> 8;
580 desc_info->sec_seq[2] = pn64 >> 16;
581 desc_info->sec_seq[3] = pn64 >> 24;
582 desc_info->sec_seq[4] = pn64 >> 32;
583 desc_info->sec_seq[5] = pn64 >> 40;
584 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */
585 }
586
rtw89_core_get_mgmt_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,const struct rtw89_chan * chan)587 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev,
588 struct rtw89_core_tx_request *tx_req,
589 const struct rtw89_chan *chan)
590 {
591 struct sk_buff *skb = tx_req->skb;
592 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
593 struct ieee80211_vif *vif = tx_info->control.vif;
594 u16 lowest_rate;
595
596 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE ||
597 (vif && vif->p2p))
598 lowest_rate = RTW89_HW_RATE_OFDM6;
599 else if (chan->band_type == RTW89_BAND_2G)
600 lowest_rate = RTW89_HW_RATE_CCK1;
601 else
602 lowest_rate = RTW89_HW_RATE_OFDM6;
603
604 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta)
605 return lowest_rate;
606
607 return __ffs(vif->bss_conf.basic_rates) + lowest_rate;
608 }
609
rtw89_core_tx_get_mac_id(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)610 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev,
611 struct rtw89_core_tx_request *tx_req)
612 {
613 struct ieee80211_vif *vif = tx_req->vif;
614 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
615 struct ieee80211_sta *sta = tx_req->sta;
616 struct rtw89_sta *rtwsta;
617
618 if (!sta)
619 return rtwvif->mac_id;
620
621 rtwsta = (struct rtw89_sta *)sta->drv_priv;
622 return rtwsta->mac_id;
623 }
624
625 static void
rtw89_core_tx_update_mgmt_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)626 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev,
627 struct rtw89_core_tx_request *tx_req)
628 {
629 struct ieee80211_vif *vif = tx_req->vif;
630 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
631 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
632 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
633 rtwvif->sub_entity_idx);
634 u8 qsel, ch_dma;
635
636 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT;
637 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
638
639 desc_info->qsel = qsel;
640 desc_info->ch_dma = ch_dma;
641 desc_info->port = desc_info->hiq ? rtwvif->port : 0;
642 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
643 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL;
644 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE;
645
646 /* fixed data rate for mgmt frames */
647 desc_info->en_wd_info = true;
648 desc_info->use_rate = true;
649 desc_info->dis_data_fb = true;
650 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan);
651
652 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
653 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n",
654 desc_info->data_rate, chan->channel, chan->band_type,
655 chan->band_width);
656 }
657
658 static void
rtw89_core_tx_update_h2c_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)659 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev,
660 struct rtw89_core_tx_request *tx_req)
661 {
662 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
663
664 desc_info->is_bmc = false;
665 desc_info->wd_page = false;
666 desc_info->ch_dma = RTW89_DMA_H2C;
667 }
668
rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev * rtwdev,__le32 * htc,const struct rtw89_chan * chan)669 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc,
670 const struct rtw89_chan *chan)
671 {
672 static const u8 rtw89_bandwidth_to_om[] = {
673 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20,
674 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40,
675 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80,
676 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
677 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
678 };
679 const struct rtw89_chip_info *chip = rtwdev->chip;
680 struct rtw89_hal *hal = &rtwdev->hal;
681 u8 om_bandwidth;
682
683 if (!chip->dis_2g_40m_ul_ofdma ||
684 chan->band_type != RTW89_BAND_2G ||
685 chan->band_width != RTW89_CHANNEL_WIDTH_40)
686 return;
687
688 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ?
689 rtw89_bandwidth_to_om[chan->band_width] : 0;
690 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
691 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) |
692 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) |
693 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) |
694 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) |
695 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) |
696 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) |
697 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) |
698 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS);
699 }
700
701 static bool
__rtw89_core_tx_check_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)702 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev,
703 struct rtw89_core_tx_request *tx_req,
704 enum btc_pkt_type pkt_type)
705 {
706 struct ieee80211_sta *sta = tx_req->sta;
707 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
708 struct sk_buff *skb = tx_req->skb;
709 struct ieee80211_hdr *hdr = (void *)skb->data;
710 __le16 fc = hdr->frame_control;
711
712 /* AP IOT issue with EAPoL, ARP and DHCP */
713 if (pkt_type < PACKET_MAX)
714 return false;
715
716 if (!sta || !sta->deflink.he_cap.has_he)
717 return false;
718
719 if (!ieee80211_is_data_qos(fc))
720 return false;
721
722 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN)
723 return false;
724
725 if (rtwsta && rtwsta->ra_report.might_fallback_legacy)
726 return false;
727
728 return true;
729 }
730
731 static void
__rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)732 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev,
733 struct rtw89_core_tx_request *tx_req)
734 {
735 struct ieee80211_sta *sta = tx_req->sta;
736 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
737 struct sk_buff *skb = tx_req->skb;
738 struct ieee80211_hdr *hdr = (void *)skb->data;
739 __le16 fc = hdr->frame_control;
740 void *data;
741 __le32 *htc;
742 u8 *qc;
743 int hdr_len;
744
745 hdr_len = ieee80211_has_a4(fc) ? 32 : 26;
746 data = skb_push(skb, IEEE80211_HT_CTL_LEN);
747 #if defined(__linux__)
748 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len);
749 #elif defined(__FreeBSD__)
750 memmove(data, (u8 *)data + IEEE80211_HT_CTL_LEN, hdr_len);
751 #endif
752
753 hdr = data;
754 #if defined(__linux__)
755 htc = data + hdr_len;
756 #elif defined(__FreeBSD__)
757 htc = (__le32 *)((u8 *)data + hdr_len);
758 #endif
759 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER);
760 *htc = rtwsta->htc_template ? rtwsta->htc_template :
761 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
762 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID);
763
764 #if defined(__linux__)
765 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN;
766 #elif defined(__FreeBSD__)
767 qc = (u8 *)data + hdr_len - IEEE80211_QOS_CTL_LEN;
768 #endif
769 qc[0] |= IEEE80211_QOS_CTL_EOSP;
770 }
771
772 static void
rtw89_core_tx_update_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)773 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev,
774 struct rtw89_core_tx_request *tx_req,
775 enum btc_pkt_type pkt_type)
776 {
777 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
778 struct ieee80211_vif *vif = tx_req->vif;
779 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
780
781 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type))
782 goto desc_bk;
783
784 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req);
785
786 desc_info->pkt_size += IEEE80211_HT_CTL_LEN;
787 desc_info->a_ctrl_bsr = true;
788
789 desc_bk:
790 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr)
791 return;
792
793 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr;
794 desc_info->bk = true;
795 }
796
rtw89_core_get_data_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)797 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev,
798 struct rtw89_core_tx_request *tx_req)
799 {
800 struct ieee80211_vif *vif = tx_req->vif;
801 struct ieee80211_sta *sta = tx_req->sta;
802 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
803 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern;
804 enum rtw89_sub_entity_idx idx = rtwvif->sub_entity_idx;
805 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx);
806 u16 lowest_rate;
807
808 if (rate_pattern->enable)
809 return rate_pattern->rate;
810
811 if (vif->p2p)
812 lowest_rate = RTW89_HW_RATE_OFDM6;
813 else if (chan->band_type == RTW89_BAND_2G)
814 lowest_rate = RTW89_HW_RATE_CCK1;
815 else
816 lowest_rate = RTW89_HW_RATE_OFDM6;
817
818 if (!sta || !sta->deflink.supp_rates[chan->band_type])
819 return lowest_rate;
820
821 return __ffs(sta->deflink.supp_rates[chan->band_type]) + lowest_rate;
822 }
823
824 static void
rtw89_core_tx_update_data_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)825 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev,
826 struct rtw89_core_tx_request *tx_req)
827 {
828 struct ieee80211_vif *vif = tx_req->vif;
829 struct ieee80211_sta *sta = tx_req->sta;
830 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
831 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
832 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
833 struct sk_buff *skb = tx_req->skb;
834 u8 tid, tid_indicate;
835 u8 qsel, ch_dma;
836
837 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
838 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid);
839 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid);
840 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
841
842 desc_info->ch_dma = ch_dma;
843 desc_info->tid_indicate = tid_indicate;
844 desc_info->qsel = qsel;
845 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
846 desc_info->port = desc_info->hiq ? rtwvif->port : 0;
847 desc_info->er_cap = rtwsta ? rtwsta->er_cap : false;
848 desc_info->stbc = rtwsta ? rtwsta->ra.stbc_cap : false;
849 desc_info->ldpc = rtwsta ? rtwsta->ra.ldpc_cap : false;
850
851 /* enable wd_info for AMPDU */
852 desc_info->en_wd_info = true;
853
854 if (IEEE80211_SKB_CB(skb)->control.hw_key)
855 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
856
857 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req);
858 }
859
860 static enum btc_pkt_type
rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)861 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev,
862 struct rtw89_core_tx_request *tx_req)
863 {
864 struct sk_buff *skb = tx_req->skb;
865 struct udphdr *udphdr;
866
867 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) {
868 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work);
869 return PACKET_EAPOL;
870 }
871
872 if (skb->protocol == htons(ETH_P_ARP)) {
873 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work);
874 return PACKET_ARP;
875 }
876
877 if (skb->protocol == htons(ETH_P_IP) &&
878 ip_hdr(skb)->protocol == IPPROTO_UDP) {
879 udphdr = udp_hdr(skb);
880 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) ||
881 (udphdr->source == htons(68) && udphdr->dest == htons(67))) &&
882 skb->len > 282) {
883 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work);
884 return PACKET_DHCP;
885 }
886 }
887
888 if (skb->protocol == htons(ETH_P_IP) &&
889 ip_hdr(skb)->protocol == IPPROTO_ICMP) {
890 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work);
891 return PACKET_ICMP;
892 }
893
894 return PACKET_MAX;
895 }
896
rtw89_core_tx_update_llc_hdr(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,struct sk_buff * skb)897 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev,
898 struct rtw89_tx_desc_info *desc_info,
899 struct sk_buff *skb)
900 {
901 struct ieee80211_hdr *hdr = (void *)skb->data;
902 __le16 fc = hdr->frame_control;
903
904 desc_info->hdr_llc_len = ieee80211_hdrlen(fc);
905 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */
906 }
907
908 static void
rtw89_core_tx_wake(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)909 rtw89_core_tx_wake(struct rtw89_dev *rtwdev,
910 struct rtw89_core_tx_request *tx_req)
911 {
912 const struct rtw89_chip_info *chip = rtwdev->chip;
913
914 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw))
915 return;
916
917 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags))
918 return;
919
920 if (chip->chip_id != RTL8852C &&
921 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT)
922 return;
923
924 rtw89_mac_notify_wake(rtwdev);
925 }
926
927 static void
rtw89_core_tx_update_desc_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)928 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev,
929 struct rtw89_core_tx_request *tx_req)
930 {
931 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
932 struct sk_buff *skb = tx_req->skb;
933 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
934 struct ieee80211_hdr *hdr = (void *)skb->data;
935 enum rtw89_core_tx_type tx_type;
936 enum btc_pkt_type pkt_type;
937 bool is_bmc;
938 u16 seq;
939
940 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
941 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) {
942 tx_type = rtw89_core_get_tx_type(rtwdev, skb);
943 tx_req->tx_type = tx_type;
944 }
945 is_bmc = (is_broadcast_ether_addr(hdr->addr1) ||
946 is_multicast_ether_addr(hdr->addr1));
947
948 desc_info->seq = seq;
949 desc_info->pkt_size = skb->len;
950 desc_info->is_bmc = is_bmc;
951 desc_info->wd_page = true;
952 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM;
953
954 switch (tx_req->tx_type) {
955 case RTW89_CORE_TX_TYPE_MGMT:
956 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req);
957 break;
958 case RTW89_CORE_TX_TYPE_DATA:
959 rtw89_core_tx_update_data_info(rtwdev, tx_req);
960 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req);
961 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type);
962 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type);
963 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
964 break;
965 case RTW89_CORE_TX_TYPE_FWCMD:
966 rtw89_core_tx_update_h2c_info(rtwdev, tx_req);
967 break;
968 }
969 }
970
rtw89_core_tx_kick_off(struct rtw89_dev * rtwdev,u8 qsel)971 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel)
972 {
973 u8 ch_dma;
974
975 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
976
977 rtw89_hci_tx_kick_off(rtwdev, ch_dma);
978 }
979
rtw89_core_tx_kick_off_and_wait(struct rtw89_dev * rtwdev,struct sk_buff * skb,int qsel,unsigned int timeout)980 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
981 int qsel, unsigned int timeout)
982 {
983 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
984 struct rtw89_tx_wait_info *wait;
985 unsigned long time_left;
986 int ret = 0;
987
988 wait = kzalloc(sizeof(*wait), GFP_KERNEL);
989 if (!wait) {
990 rtw89_core_tx_kick_off(rtwdev, qsel);
991 return 0;
992 }
993
994 init_completion(&wait->completion);
995 rcu_assign_pointer(skb_data->wait, wait);
996
997 rtw89_core_tx_kick_off(rtwdev, qsel);
998 time_left = wait_for_completion_timeout(&wait->completion,
999 msecs_to_jiffies(timeout));
1000 if (time_left == 0)
1001 ret = -ETIMEDOUT;
1002 else if (!wait->tx_done)
1003 ret = -EAGAIN;
1004
1005 rcu_assign_pointer(skb_data->wait, NULL);
1006 kfree_rcu(wait, rcu_head);
1007
1008 return ret;
1009 }
1010
rtw89_h2c_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb,bool fwdl)1011 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
1012 struct sk_buff *skb, bool fwdl)
1013 {
1014 struct rtw89_core_tx_request tx_req = {0};
1015 u32 cnt;
1016 int ret;
1017
1018 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) {
1019 rtw89_debug(rtwdev, RTW89_DBG_FW,
1020 "ignore h2c due to power is off with firmware state=%d\n",
1021 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags));
1022 dev_kfree_skb(skb);
1023 return 0;
1024 }
1025
1026 tx_req.skb = skb;
1027 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD;
1028 if (fwdl)
1029 tx_req.desc_info.fw_dl = true;
1030
1031 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1032
1033 if (!fwdl)
1034 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len);
1035
1036 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12);
1037 if (cnt == 0) {
1038 rtw89_err(rtwdev, "no tx fwcmd resource\n");
1039 return -ENOSPC;
1040 }
1041
1042 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1043 if (ret) {
1044 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1045 return ret;
1046 }
1047 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12);
1048
1049 return 0;
1050 }
1051
rtw89_core_tx_write(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct sk_buff * skb,int * qsel)1052 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1053 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel)
1054 {
1055 struct rtw89_core_tx_request tx_req = {0};
1056 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
1057 int ret;
1058
1059 tx_req.skb = skb;
1060 tx_req.sta = sta;
1061 tx_req.vif = vif;
1062
1063 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true);
1064 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true);
1065 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1066 rtw89_core_tx_wake(rtwdev, &tx_req);
1067
1068 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1069 if (ret) {
1070 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1071 return ret;
1072 }
1073
1074 if (qsel)
1075 *qsel = tx_req.desc_info.qsel;
1076
1077 return 0;
1078 }
1079
rtw89_build_txwd_body0(struct rtw89_tx_desc_info * desc_info)1080 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info)
1081 {
1082 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) |
1083 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1084 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1085 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1086 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1087 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) |
1088 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) |
1089 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode);
1090
1091 return cpu_to_le32(dword);
1092 }
1093
rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info * desc_info)1094 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info)
1095 {
1096 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1097 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1098 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1099 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1100 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1101 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl);
1102
1103 return cpu_to_le32(dword);
1104 }
1105
rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info * desc_info)1106 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info)
1107 {
1108 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1109 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1110 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type);
1111
1112 return cpu_to_le32(dword);
1113 }
1114
rtw89_build_txwd_body2(struct rtw89_tx_desc_info * desc_info)1115 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info)
1116 {
1117 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) |
1118 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) |
1119 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) |
1120 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id);
1121
1122 return cpu_to_le32(dword);
1123 }
1124
rtw89_build_txwd_body3(struct rtw89_tx_desc_info * desc_info)1125 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info)
1126 {
1127 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) |
1128 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) |
1129 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk);
1130
1131 return cpu_to_le32(dword);
1132 }
1133
rtw89_build_txwd_body4(struct rtw89_tx_desc_info * desc_info)1134 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info)
1135 {
1136 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1137 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1138
1139 return cpu_to_le32(dword);
1140 }
1141
rtw89_build_txwd_body5(struct rtw89_tx_desc_info * desc_info)1142 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info)
1143 {
1144 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1145 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1146 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1147 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1148
1149 return cpu_to_le32(dword);
1150 }
1151
rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info * desc_info)1152 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info)
1153 {
1154 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) |
1155 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate);
1156
1157 return cpu_to_le32(dword);
1158 }
1159
rtw89_build_txwd_info0(struct rtw89_tx_desc_info * desc_info)1160 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info)
1161 {
1162 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) |
1163 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) |
1164 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1165 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1166 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1167 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port);
1168
1169 return cpu_to_le32(dword);
1170 }
1171
rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info * desc_info)1172 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info)
1173 {
1174 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1175 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1176 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1177 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) |
1178 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) |
1179 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0);
1180
1181 return cpu_to_le32(dword);
1182 }
1183
rtw89_build_txwd_info1(struct rtw89_tx_desc_info * desc_info)1184 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info)
1185 {
1186 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) |
1187 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1188 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE,
1189 desc_info->data_retry_lowest_rate);
1190
1191 return cpu_to_le32(dword);
1192 }
1193
rtw89_build_txwd_info2(struct rtw89_tx_desc_info * desc_info)1194 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info)
1195 {
1196 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1197 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) |
1198 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) |
1199 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1200
1201 return cpu_to_le32(dword);
1202 }
1203
rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info * desc_info)1204 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info)
1205 {
1206 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1207 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1208 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1209
1210 return cpu_to_le32(dword);
1211 }
1212
rtw89_build_txwd_info4(struct rtw89_tx_desc_info * desc_info)1213 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info)
1214 {
1215 bool rts_en = !desc_info->is_bmc;
1216 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) |
1217 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1);
1218
1219 return cpu_to_le32(dword);
1220 }
1221
rtw89_core_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1222 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
1223 struct rtw89_tx_desc_info *desc_info,
1224 void *txdesc)
1225 {
1226 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc;
1227 struct rtw89_txwd_info *txwd_info;
1228
1229 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info);
1230 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1231 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1232
1233 if (!desc_info->en_wd_info)
1234 return;
1235
1236 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1237 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info);
1238 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1239 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info);
1240 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1241
1242 }
1243 EXPORT_SYMBOL(rtw89_core_fill_txdesc);
1244
rtw89_core_fill_txdesc_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1245 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
1246 struct rtw89_tx_desc_info *desc_info,
1247 void *txdesc)
1248 {
1249 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc;
1250 struct rtw89_txwd_info *txwd_info;
1251
1252 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info);
1253 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info);
1254 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1255 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1256 if (desc_info->sec_en) {
1257 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info);
1258 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info);
1259 }
1260 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info);
1261
1262 if (!desc_info->en_wd_info)
1263 return;
1264
1265 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1266 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info);
1267 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1268 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info);
1269 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1270 }
1271 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1);
1272
rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info * desc_info)1273 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info)
1274 {
1275 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1276 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) |
1277 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) |
1278 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1279 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page);
1280
1281 return cpu_to_le32(dword);
1282 }
1283
rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info * desc_info)1284 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info)
1285 {
1286 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1287 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1288 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type);
1289
1290 return cpu_to_le32(dword);
1291 }
1292
rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info * desc_info)1293 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info)
1294 {
1295 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) |
1296 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) |
1297 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) |
1298 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) |
1299 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) |
1300 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id);
1301
1302 return cpu_to_le32(dword);
1303 }
1304
rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info * desc_info)1305 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info)
1306 {
1307 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq);
1308
1309 return cpu_to_le32(dword);
1310 }
1311
rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info * desc_info)1312 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info)
1313 {
1314 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1315 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1316
1317 return cpu_to_le32(dword);
1318 }
1319
rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info * desc_info)1320 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info)
1321 {
1322 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1323 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1324 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1325 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1326
1327 return cpu_to_le32(dword);
1328 }
1329
rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info * desc_info)1330 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info)
1331 {
1332 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) |
1333 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) |
1334 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) |
1335 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate);
1336
1337 return cpu_to_le32(dword);
1338 }
1339
rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info * desc_info)1340 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info)
1341 {
1342 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) |
1343 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) |
1344 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1345 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port);
1346
1347 return cpu_to_le32(dword);
1348 }
1349
rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info * desc_info)1350 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info)
1351 {
1352 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) |
1353 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1354 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE,
1355 desc_info->data_retry_lowest_rate);
1356
1357 return cpu_to_le32(dword);
1358 }
1359
rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info * desc_info)1360 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info)
1361 {
1362 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1363 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1364 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1365
1366 return cpu_to_le32(dword);
1367 }
1368
rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info * desc_info)1369 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info)
1370 {
1371 bool rts_en = !desc_info->is_bmc;
1372 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) |
1373 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1);
1374
1375 return cpu_to_le32(dword);
1376 }
1377
rtw89_core_fill_txdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1378 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
1379 struct rtw89_tx_desc_info *desc_info,
1380 void *txdesc)
1381 {
1382 struct rtw89_txwd_body_v2 *txwd_body = txdesc;
1383 struct rtw89_txwd_info_v2 *txwd_info;
1384
1385 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info);
1386 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info);
1387 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info);
1388 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info);
1389 if (desc_info->sec_en) {
1390 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info);
1391 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info);
1392 }
1393 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info);
1394
1395 if (!desc_info->en_wd_info)
1396 return;
1397
1398 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1);
1399 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info);
1400 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info);
1401 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info);
1402 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info);
1403 }
1404 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2);
1405
rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info * desc_info)1406 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info)
1407 {
1408 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1409 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1410 RTW89_CORE_RX_TYPE_FWDL :
1411 RTW89_CORE_RX_TYPE_H2C);
1412
1413 return cpu_to_le32(dword);
1414 }
1415
rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1416 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
1417 struct rtw89_tx_desc_info *desc_info,
1418 void *txdesc)
1419 {
1420 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc;
1421
1422 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info);
1423 }
1424 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1);
1425
rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info * desc_info)1426 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info)
1427 {
1428 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1429 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1430 RTW89_CORE_RX_TYPE_FWDL :
1431 RTW89_CORE_RX_TYPE_H2C);
1432
1433 return cpu_to_le32(dword);
1434 }
1435
rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1436 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
1437 struct rtw89_tx_desc_info *desc_info,
1438 void *txdesc)
1439 {
1440 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc;
1441
1442 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info);
1443 }
1444 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2);
1445
rtw89_core_rx_process_mac_ppdu(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_rx_phy_ppdu * phy_ppdu)1446 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev,
1447 struct sk_buff *skb,
1448 struct rtw89_rx_phy_ppdu *phy_ppdu)
1449 {
1450 const struct rtw89_chip_info *chip = rtwdev->chip;
1451 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data;
1452 const struct rtw89_rxinfo_user *user;
1453 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
1454 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE;
1455 bool rx_cnt_valid = false;
1456 bool invalid = false;
1457 u8 plcp_size = 0;
1458 u8 *phy_sts;
1459 u8 usr_num;
1460 int i;
1461
1462 if (chip_gen == RTW89_CHIP_BE) {
1463 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1);
1464 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1;
1465 }
1466
1467 if (invalid)
1468 return -EINVAL;
1469
1470 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD);
1471 if (chip_gen == RTW89_CHIP_BE) {
1472 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3;
1473 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1);
1474 } else {
1475 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3;
1476 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM);
1477 }
1478 if (usr_num > chip->ppdu_max_usr) {
1479 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n",
1480 usr_num);
1481 return -EINVAL;
1482 }
1483
1484 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set by hardware,
1485 * so update mac_id by rxinfo_user[].mac_id.
1486 */
1487 for (i = 0; i < usr_num && chip_gen == RTW89_CHIP_BE; i++) {
1488 user = &rxinfo->user[i];
1489 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID))
1490 continue;
1491
1492 phy_ppdu->mac_id =
1493 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID);
1494 break;
1495 }
1496
1497 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE;
1498 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE;
1499 /* 8-byte alignment */
1500 if (usr_num & BIT(0))
1501 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE;
1502 if (rx_cnt_valid)
1503 phy_sts += rx_cnt_size;
1504 phy_sts += plcp_size;
1505
1506 if (phy_sts > skb->data + skb->len)
1507 return -EINVAL;
1508
1509 phy_ppdu->buf = phy_sts;
1510 phy_ppdu->len = skb->data + skb->len - phy_sts;
1511
1512 return 0;
1513 }
1514
rtw89_core_rx_process_phy_ppdu_iter(void * data,struct ieee80211_sta * sta)1515 static void rtw89_core_rx_process_phy_ppdu_iter(void *data,
1516 struct ieee80211_sta *sta)
1517 {
1518 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
1519 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data;
1520 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
1521 struct rtw89_hal *hal = &rtwdev->hal;
1522 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
1523 u8 ant_pos = U8_MAX;
1524 u8 evm_pos = 0;
1525 int i;
1526
1527 if (rtwsta->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self)
1528 return;
1529
1530 if (hal->ant_diversity && hal->antenna_rx) {
1531 ant_pos = __ffs(hal->antenna_rx);
1532 evm_pos = ant_pos;
1533 }
1534
1535 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg);
1536
1537 if (ant_pos < ant_num) {
1538 ewma_rssi_add(&rtwsta->rssi[ant_pos], phy_ppdu->rssi[0]);
1539 } else {
1540 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
1541 ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]);
1542 }
1543
1544 if (phy_ppdu->ofdm.has) {
1545 ewma_snr_add(&rtwsta->avg_snr, phy_ppdu->ofdm.avg_snr);
1546 ewma_evm_add(&rtwsta->evm_min[evm_pos], phy_ppdu->ofdm.evm_min);
1547 ewma_evm_add(&rtwsta->evm_max[evm_pos], phy_ppdu->ofdm.evm_max);
1548 }
1549 }
1550
1551 #define VAR_LEN 0xff
1552 #define VAR_LEN_UNIT 8
rtw89_core_get_phy_status_ie_len(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr)1553 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev,
1554 const struct rtw89_phy_sts_iehdr *iehdr)
1555 {
1556 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = {
1557 [RTW89_CHIP_AX] = {
1558 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
1559 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN,
1560 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
1561 },
1562 [RTW89_CHIP_BE] = {
1563 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
1564 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN,
1565 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
1566 },
1567 };
1568 const u8 *physts_ie_len_tab;
1569 u16 ie_len;
1570 u8 ie;
1571
1572 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen];
1573
1574 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
1575 if (physts_ie_len_tab[ie] != VAR_LEN)
1576 ie_len = physts_ie_len_tab[ie];
1577 else
1578 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT;
1579
1580 return ie_len;
1581 }
1582
rtw89_core_parse_phy_status_ie01(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1583 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev,
1584 const struct rtw89_phy_sts_iehdr *iehdr,
1585 struct rtw89_rx_phy_ppdu *phy_ppdu)
1586 {
1587 const struct rtw89_phy_sts_ie0 *ie = (const struct rtw89_phy_sts_ie0 *)iehdr;
1588 s16 cfo;
1589 u32 t;
1590
1591 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX);
1592
1593 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
1594 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC);
1595 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC);
1596 }
1597
1598 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6)
1599 return;
1600
1601 if (!phy_ppdu->to_self)
1602 return;
1603
1604 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR);
1605 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX);
1606 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN);
1607 phy_ppdu->ofdm.has = true;
1608
1609 /* sign conversion for S(12,2) */
1610 if (rtwdev->chip->cfo_src_fd) {
1611 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO);
1612 cfo = sign_extend32(t, 11);
1613 } else {
1614 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO);
1615 cfo = sign_extend32(t, 11);
1616 }
1617
1618 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu);
1619 }
1620
rtw89_core_process_phy_status_ie(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1621 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev,
1622 const struct rtw89_phy_sts_iehdr *iehdr,
1623 struct rtw89_rx_phy_ppdu *phy_ppdu)
1624 {
1625 u8 ie;
1626
1627 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
1628
1629 switch (ie) {
1630 case RTW89_PHYSTS_IE01_CMN_OFDM:
1631 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu);
1632 break;
1633 default:
1634 break;
1635 }
1636
1637 return 0;
1638 }
1639
rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu * phy_ppdu)1640 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu)
1641 {
1642 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
1643 u8 *rssi = phy_ppdu->rssi;
1644
1645 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP);
1646 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG);
1647 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A);
1648 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B);
1649 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C);
1650 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D);
1651 }
1652
rtw89_core_rx_process_phy_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1653 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev,
1654 struct rtw89_rx_phy_ppdu *phy_ppdu)
1655 {
1656 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
1657 u32 len_from_header;
1658 bool physts_valid;
1659
1660 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID);
1661 if (!physts_valid)
1662 return -EINVAL;
1663
1664 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3;
1665
1666 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
1667 len_from_header += PHY_STS_HDR_LEN;
1668
1669 if (len_from_header != phy_ppdu->len) {
1670 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n");
1671 return -EINVAL;
1672 }
1673 rtw89_core_update_phy_ppdu(phy_ppdu);
1674
1675 return 0;
1676 }
1677
rtw89_core_rx_parse_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1678 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev,
1679 struct rtw89_rx_phy_ppdu *phy_ppdu)
1680 {
1681 u16 ie_len;
1682 #if defined(__linux__)
1683 void *pos, *end;
1684 #elif defined(__FreeBSD__)
1685 u8 *pos, *end;
1686 #endif
1687
1688 /* mark invalid reports and bypass them */
1689 if (phy_ppdu->ie < RTW89_CCK_PKT)
1690 return -EINVAL;
1691
1692 #if defined(__linux__)
1693 pos = phy_ppdu->buf + PHY_STS_HDR_LEN;
1694 end = phy_ppdu->buf + phy_ppdu->len;
1695 #elif defined(__FreeBSD__)
1696 pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN;
1697 end = (u8 *)phy_ppdu->buf + phy_ppdu->len;
1698 #endif
1699 while (pos < end) {
1700 #if defined(__linux__)
1701 const struct rtw89_phy_sts_iehdr *iehdr = pos;
1702 #elif defined(__FreeBSD__)
1703 const struct rtw89_phy_sts_iehdr *iehdr = (void *)pos;
1704 #endif
1705
1706 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr);
1707 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu);
1708 pos += ie_len;
1709 if (pos > end || ie_len == 0) {
1710 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
1711 "phy status parse failed\n");
1712 return -EINVAL;
1713 }
1714 }
1715
1716 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu);
1717
1718 return 0;
1719 }
1720
rtw89_core_rx_process_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1721 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev,
1722 struct rtw89_rx_phy_ppdu *phy_ppdu)
1723 {
1724 int ret;
1725
1726 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu);
1727 if (ret)
1728 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n");
1729 else
1730 phy_ppdu->valid = true;
1731
1732 ieee80211_iterate_stations_atomic(rtwdev->hw,
1733 rtw89_core_rx_process_phy_ppdu_iter,
1734 phy_ppdu);
1735 }
1736
rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status,bool eht)1737 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev,
1738 u8 desc_info_gi,
1739 bool rx_status, bool eht)
1740 {
1741 switch (desc_info_gi) {
1742 case RTW89_GILTF_SGI_4XHE08:
1743 case RTW89_GILTF_2XHE08:
1744 case RTW89_GILTF_1XHE08:
1745 return eht ? NL80211_RATE_INFO_EHT_GI_0_8 :
1746 NL80211_RATE_INFO_HE_GI_0_8;
1747 case RTW89_GILTF_2XHE16:
1748 case RTW89_GILTF_1XHE16:
1749 return eht ? NL80211_RATE_INFO_EHT_GI_1_6 :
1750 NL80211_RATE_INFO_HE_GI_1_6;
1751 case RTW89_GILTF_LGI_4XHE32:
1752 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 :
1753 NL80211_RATE_INFO_HE_GI_3_2;
1754 default:
1755 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi);
1756 if (rx_status)
1757 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 :
1758 NL80211_RATE_INFO_HE_GI_3_2;
1759 return U8_MAX;
1760 }
1761 }
1762
1763 static
rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status * status,u8 gi_ltf,bool eht)1764 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf,
1765 bool eht)
1766 {
1767 if (eht)
1768 return status->eht.gi == gi_ltf;
1769
1770 return status->he_gi == gi_ltf;
1771 }
1772
rtw89_core_rx_ppdu_match(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * status)1773 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev,
1774 struct rtw89_rx_desc_info *desc_info,
1775 struct ieee80211_rx_status *status)
1776 {
1777 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
1778 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf;
1779 bool eht = false;
1780 u16 data_rate;
1781 bool ret;
1782
1783 data_rate = desc_info->data_rate;
1784 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
1785 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
1786 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
1787 /* rate_idx is still hardware value here */
1788 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
1789 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
1790 } else if (data_rate_mode == DATA_RATE_MODE_VHT ||
1791 data_rate_mode == DATA_RATE_MODE_HE ||
1792 data_rate_mode == DATA_RATE_MODE_EHT) {
1793 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
1794 } else {
1795 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
1796 }
1797
1798 eht = data_rate_mode == DATA_RATE_MODE_EHT;
1799 bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
1800 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht);
1801 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt &&
1802 status->rate_idx == rate_idx &&
1803 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) &&
1804 status->bw == bw;
1805
1806 return ret;
1807 }
1808
1809 struct rtw89_vif_rx_stats_iter_data {
1810 struct rtw89_dev *rtwdev;
1811 struct rtw89_rx_phy_ppdu *phy_ppdu;
1812 struct rtw89_rx_desc_info *desc_info;
1813 struct sk_buff *skb;
1814 const u8 *bssid;
1815 };
1816
rtw89_stats_trigger_frame(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct sk_buff * skb)1817 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev,
1818 struct ieee80211_vif *vif,
1819 struct sk_buff *skb)
1820 {
1821 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
1822 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data;
1823 u8 *pos, *end, type, tf_bw;
1824 u16 aid, tf_rua;
1825
1826 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) ||
1827 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION ||
1828 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK)
1829 return;
1830
1831 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK);
1832 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR)
1833 return;
1834
1835 end = (u8 *)tf + skb->len;
1836 pos = tf->variable;
1837
1838 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) {
1839 aid = RTW89_GET_TF_USER_INFO_AID12(pos);
1840 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos);
1841 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK);
1842 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
1843 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n",
1844 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos),
1845 tf_rua, tf_bw);
1846
1847 if (aid == RTW89_TF_PAD)
1848 break;
1849
1850 if (aid == vif->cfg.aid) {
1851 enum nl80211_he_ru_alloc rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1);
1852
1853 rtwvif->stats.rx_tf_acc++;
1854 rtwdev->stats.rx_tf_acc++;
1855 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ &&
1856 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106)
1857 rtwvif->pwr_diff_en = true;
1858 break;
1859 }
1860
1861 pos += RTW89_TF_BASIC_USER_INFO_SZ;
1862 }
1863 }
1864
rtw89_cancel_6ghz_probe_work(struct work_struct * work)1865 static void rtw89_cancel_6ghz_probe_work(struct work_struct *work)
1866 {
1867 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
1868 cancel_6ghz_probe_work);
1869 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
1870 struct rtw89_pktofld_info *info;
1871
1872 mutex_lock(&rtwdev->mutex);
1873
1874 if (!rtwdev->scanning)
1875 goto out;
1876
1877 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
1878 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload))
1879 continue;
1880
1881 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
1882
1883 /* Don't delete/free info from pkt_list at this moment. Let it
1884 * be deleted/freed in rtw89_release_pkt_list() after scanning,
1885 * since if during scanning, pkt_list is accessed in bottom half.
1886 */
1887 }
1888
1889 out:
1890 mutex_unlock(&rtwdev->mutex);
1891 }
1892
rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb)1893 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev,
1894 struct sk_buff *skb)
1895 {
1896 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
1897 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1898 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
1899 struct rtw89_pktofld_info *info;
1900 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie;
1901 bool queue_work = false;
1902
1903 if (rx_status->band != NL80211_BAND_6GHZ)
1904 return;
1905
1906 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len);
1907
1908 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
1909 if (ether_addr_equal(info->bssid, mgmt->bssid)) {
1910 info->cancel = true;
1911 queue_work = true;
1912 continue;
1913 }
1914
1915 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0)
1916 continue;
1917
1918 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) {
1919 info->cancel = true;
1920 queue_work = true;
1921 }
1922 }
1923
1924 if (queue_work)
1925 ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work);
1926 }
1927
rtw89_vif_sync_bcn_tsf(struct rtw89_vif * rtwvif,struct ieee80211_hdr * hdr,size_t len)1928 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif *rtwvif,
1929 struct ieee80211_hdr *hdr, size_t len)
1930 {
1931 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr;
1932
1933 if (len < offsetof(typeof(*mgmt), u.beacon.variable))
1934 return;
1935
1936 WRITE_ONCE(rtwvif->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp));
1937 }
1938
rtw89_vif_rx_stats_iter(void * data,u8 * mac,struct ieee80211_vif * vif)1939 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac,
1940 struct ieee80211_vif *vif)
1941 {
1942 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
1943 struct rtw89_vif_rx_stats_iter_data *iter_data = data;
1944 struct rtw89_dev *rtwdev = iter_data->rtwdev;
1945 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat;
1946 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
1947 struct sk_buff *skb = iter_data->skb;
1948 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1949 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu;
1950 const u8 *bssid = iter_data->bssid;
1951
1952 if (rtwdev->scanning &&
1953 (ieee80211_is_beacon(hdr->frame_control) ||
1954 ieee80211_is_probe_resp(hdr->frame_control)))
1955 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb);
1956
1957 if (!vif->bss_conf.bssid)
1958 return;
1959
1960 if (ieee80211_is_trigger(hdr->frame_control)) {
1961 rtw89_stats_trigger_frame(rtwdev, vif, skb);
1962 return;
1963 }
1964
1965 if (!ether_addr_equal(vif->bss_conf.bssid, bssid))
1966 return;
1967
1968 if (ieee80211_is_beacon(hdr->frame_control)) {
1969 if (vif->type == NL80211_IFTYPE_STATION &&
1970 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) {
1971 rtw89_vif_sync_bcn_tsf(rtwvif, hdr, skb->len);
1972 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu);
1973 }
1974 pkt_stat->beacon_nr++;
1975 }
1976
1977 if (!ether_addr_equal(vif->addr, hdr->addr1))
1978 return;
1979
1980 if (desc_info->data_rate < RTW89_HW_RATE_NR)
1981 pkt_stat->rx_rate_cnt[desc_info->data_rate]++;
1982
1983 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false);
1984 }
1985
rtw89_core_rx_stats(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)1986 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev,
1987 struct rtw89_rx_phy_ppdu *phy_ppdu,
1988 struct rtw89_rx_desc_info *desc_info,
1989 struct sk_buff *skb)
1990 {
1991 struct rtw89_vif_rx_stats_iter_data iter_data;
1992
1993 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false);
1994
1995 iter_data.rtwdev = rtwdev;
1996 iter_data.phy_ppdu = phy_ppdu;
1997 iter_data.desc_info = desc_info;
1998 iter_data.skb = skb;
1999 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data);
2000 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data);
2001 }
2002
rtw89_correct_cck_chan(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * status)2003 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev,
2004 struct ieee80211_rx_status *status)
2005 {
2006 const struct rtw89_chan_rcd *rcd =
2007 rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0);
2008 u16 chan = rcd->prev_primary_channel;
2009 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type);
2010
2011 if (status->band != NL80211_BAND_2GHZ &&
2012 status->encoding == RX_ENC_LEGACY &&
2013 status->rate_idx < RTW89_HW_RATE_OFDM6) {
2014 status->freq = ieee80211_channel_to_frequency(chan, band);
2015 status->band = band;
2016 }
2017 }
2018
rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status * rx_status)2019 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status)
2020 {
2021 if (rx_status->band == NL80211_BAND_2GHZ ||
2022 rx_status->encoding != RX_ENC_LEGACY)
2023 return;
2024
2025 /* Some control frames' freq(ACKs in this case) are reported wrong due
2026 * to FW notify timing, set to lowest rate to prevent overflow.
2027 */
2028 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) {
2029 rx_status->rate_idx = 0;
2030 return;
2031 }
2032
2033 /* No 4 CCK rates for non-2G */
2034 rx_status->rate_idx -= 4;
2035 }
2036
2037 static
rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * rx_status,struct rtw89_rx_phy_ppdu * phy_ppdu)2038 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev,
2039 struct ieee80211_rx_status *rx_status,
2040 struct rtw89_rx_phy_ppdu *phy_ppdu)
2041 {
2042 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
2043 return;
2044
2045 if (!phy_ppdu)
2046 return;
2047
2048 if (phy_ppdu->ldpc)
2049 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
2050 if (phy_ppdu->stbc)
2051 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK);
2052 }
2053
2054 static const u8 rx_status_bw_to_radiotap_eht_usig[] = {
2055 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ,
2056 [RATE_INFO_BW_5] = U8_MAX,
2057 [RATE_INFO_BW_10] = U8_MAX,
2058 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ,
2059 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ,
2060 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ,
2061 [RATE_INFO_BW_HE_RU] = U8_MAX,
2062 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1,
2063 [RATE_INFO_BW_EHT_RU] = U8_MAX,
2064 };
2065
rtw89_core_update_radiotap_eht(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)2066 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev,
2067 struct sk_buff *skb,
2068 struct ieee80211_rx_status *rx_status)
2069 {
2070 struct ieee80211_radiotap_eht_usig *usig;
2071 struct ieee80211_radiotap_eht *eht;
2072 struct ieee80211_radiotap_tlv *tlv;
2073 int eht_len = struct_size(eht, user_info, 1);
2074 int usig_len = sizeof(*usig);
2075 int len;
2076 u8 bw;
2077
2078 len = sizeof(*tlv) + ALIGN(eht_len, 4) +
2079 sizeof(*tlv) + ALIGN(usig_len, 4);
2080
2081 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END;
2082 skb_reset_mac_header(skb);
2083
2084 /* EHT */
2085 tlv = skb_push(skb, len);
2086 memset(tlv, 0, len);
2087 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT);
2088 tlv->len = cpu_to_le16(eht_len);
2089
2090 eht = (struct ieee80211_radiotap_eht *)tlv->data;
2091 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI);
2092 eht->data[0] =
2093 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI);
2094
2095 eht->user_info[0] =
2096 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN |
2097 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O |
2098 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN);
2099 eht->user_info[0] |=
2100 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) |
2101 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O);
2102 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC)
2103 eht->user_info[0] |=
2104 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING);
2105
2106 /* U-SIG */
2107 #if defined(__linux__)
2108 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4);
2109 #elif defined(__FreeBSD__)
2110 tlv = (void *)((u8 *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4));
2111 #endif
2112 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG);
2113 tlv->len = cpu_to_le16(usig_len);
2114
2115 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig))
2116 return;
2117
2118 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw];
2119 if (bw == U8_MAX)
2120 return;
2121
2122 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data;
2123 usig->common =
2124 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) |
2125 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW);
2126 }
2127
rtw89_core_update_radiotap(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)2128 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev,
2129 struct sk_buff *skb,
2130 struct ieee80211_rx_status *rx_status)
2131 {
2132 static const struct ieee80211_radiotap_he known_he = {
2133 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2134 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN |
2135 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN |
2136 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2137 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2138 };
2139 struct ieee80211_radiotap_he *he;
2140
2141 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
2142 return;
2143
2144 if (rx_status->encoding == RX_ENC_HE) {
2145 rx_status->flag |= RX_FLAG_RADIOTAP_HE;
2146 he = skb_push(skb, sizeof(*he));
2147 *he = known_he;
2148 } else if (rx_status->encoding == RX_ENC_EHT) {
2149 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status);
2150 }
2151 }
2152
rtw89_core_rx_to_mac80211(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb_ppdu,struct ieee80211_rx_status * rx_status)2153 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev,
2154 struct rtw89_rx_phy_ppdu *phy_ppdu,
2155 struct rtw89_rx_desc_info *desc_info,
2156 struct sk_buff *skb_ppdu,
2157 struct ieee80211_rx_status *rx_status)
2158 {
2159 struct napi_struct *napi = &rtwdev->napi;
2160
2161 /* In low power mode, napi isn't scheduled. Receive it to netif. */
2162 if (unlikely(!napi_is_scheduled(napi)))
2163 napi = NULL;
2164
2165 rtw89_core_hw_to_sband_rate(rx_status);
2166 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu);
2167 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu);
2168 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status);
2169 /* In low power mode, it does RX in thread context. */
2170 local_bh_disable();
2171 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi);
2172 local_bh_enable();
2173 rtwdev->napi_budget_countdown--;
2174 }
2175
rtw89_core_rx_pending_skb(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2176 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev,
2177 struct rtw89_rx_phy_ppdu *phy_ppdu,
2178 struct rtw89_rx_desc_info *desc_info,
2179 struct sk_buff *skb)
2180 {
2181 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2182 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band];
2183 struct sk_buff *skb_ppdu = NULL, *tmp;
2184 struct ieee80211_rx_status *rx_status;
2185
2186 if (curr > RTW89_MAX_PPDU_CNT)
2187 return;
2188
2189 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) {
2190 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]);
2191 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
2192 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status))
2193 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status);
2194 rtw89_correct_cck_chan(rtwdev, rx_status);
2195 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status);
2196 }
2197 }
2198
rtw89_core_rx_process_ppdu_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2199 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev,
2200 struct rtw89_rx_desc_info *desc_info,
2201 struct sk_buff *skb)
2202 {
2203 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false,
2204 .len = skb->len,
2205 .to_self = desc_info->addr1_match,
2206 .rate = desc_info->data_rate,
2207 .mac_id = desc_info->mac_id};
2208 int ret;
2209
2210 if (desc_info->mac_info_valid) {
2211 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu);
2212 if (ret)
2213 goto out;
2214 }
2215
2216 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu);
2217 if (ret)
2218 goto out;
2219
2220 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu);
2221
2222 out:
2223 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb);
2224 dev_kfree_skb_any(skb);
2225 }
2226
rtw89_core_rx_process_report(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2227 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev,
2228 struct rtw89_rx_desc_info *desc_info,
2229 struct sk_buff *skb)
2230 {
2231 switch (desc_info->pkt_type) {
2232 case RTW89_CORE_RX_TYPE_C2H:
2233 rtw89_fw_c2h_irqsafe(rtwdev, skb);
2234 break;
2235 case RTW89_CORE_RX_TYPE_PPDU_STAT:
2236 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb);
2237 break;
2238 default:
2239 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n",
2240 desc_info->pkt_type);
2241 dev_kfree_skb_any(skb);
2242 break;
2243 }
2244 }
2245
rtw89_core_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)2246 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
2247 struct rtw89_rx_desc_info *desc_info,
2248 u8 *data, u32 data_offset)
2249 {
2250 const struct rtw89_chip_info *chip = rtwdev->chip;
2251 struct rtw89_rxdesc_short *rxd_s;
2252 struct rtw89_rxdesc_long *rxd_l;
2253 u8 shift_len, drv_info_len;
2254
2255 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset);
2256 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK);
2257 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK);
2258 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD);
2259 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK);
2260 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD);
2261 if (chip->chip_id == RTL8852C)
2262 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK);
2263 else
2264 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK);
2265 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK);
2266 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK);
2267 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK);
2268 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN);
2269 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK);
2270 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK);
2271 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK);
2272 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR);
2273 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR);
2274 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC);
2275 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC);
2276 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH);
2277
2278 shift_len = desc_info->shift << 1; /* 2-byte unit */
2279 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
2280 desc_info->offset = data_offset + shift_len + drv_info_len;
2281 if (desc_info->long_rxdesc)
2282 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long);
2283 else
2284 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short);
2285 desc_info->ready = true;
2286
2287 if (!desc_info->long_rxdesc)
2288 return;
2289
2290 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset);
2291 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK);
2292 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD);
2293 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK);
2294 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK);
2295 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK);
2296 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK);
2297 }
2298 EXPORT_SYMBOL(rtw89_core_query_rxdesc);
2299
rtw89_core_query_rxdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)2300 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
2301 struct rtw89_rx_desc_info *desc_info,
2302 u8 *data, u32 data_offset)
2303 {
2304 struct rtw89_rxdesc_short_v2 *rxd_s;
2305 struct rtw89_rxdesc_long_v2 *rxd_l;
2306 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len;
2307
2308 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset);
2309
2310 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK);
2311 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK);
2312 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK);
2313 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK);
2314 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK);
2315 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD);
2316 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK);
2317 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT)
2318 desc_info->mac_info_valid = true;
2319
2320 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK);
2321 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK);
2322 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
2323
2324 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
2325 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
2326 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
2327 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC);
2328 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH);
2329
2330 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK);
2331 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK);
2332 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK);
2333 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK);
2334 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK);
2335
2336 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5);
2337
2338 shift_len = desc_info->shift << 1; /* 2-byte unit */
2339 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
2340 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */
2341 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */
2342 desc_info->offset = data_offset + shift_len + drv_info_len +
2343 phy_rtp_len + hdr_cnv_len;
2344
2345 if (desc_info->long_rxdesc)
2346 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2);
2347 else
2348 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2);
2349 desc_info->ready = true;
2350
2351 if (!desc_info->long_rxdesc)
2352 return;
2353
2354 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset);
2355
2356 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN);
2357 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK);
2358 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK);
2359 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK);
2360
2361 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK);
2362 }
2363 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2);
2364
2365 struct rtw89_core_iter_rx_status {
2366 struct rtw89_dev *rtwdev;
2367 struct ieee80211_rx_status *rx_status;
2368 struct rtw89_rx_desc_info *desc_info;
2369 u8 mac_id;
2370 };
2371
2372 static
rtw89_core_stats_sta_rx_status_iter(void * data,struct ieee80211_sta * sta)2373 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta)
2374 {
2375 struct rtw89_core_iter_rx_status *iter_data =
2376 (struct rtw89_core_iter_rx_status *)data;
2377 struct ieee80211_rx_status *rx_status = iter_data->rx_status;
2378 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2379 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
2380 u8 mac_id = iter_data->mac_id;
2381
2382 if (mac_id != rtwsta->mac_id)
2383 return;
2384
2385 rtwsta->rx_status = *rx_status;
2386 rtwsta->rx_hw_rate = desc_info->data_rate;
2387 }
2388
rtw89_core_stats_sta_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)2389 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev,
2390 struct rtw89_rx_desc_info *desc_info,
2391 struct ieee80211_rx_status *rx_status)
2392 {
2393 struct rtw89_core_iter_rx_status iter_data;
2394
2395 if (!desc_info->addr1_match || !desc_info->long_rxdesc)
2396 return;
2397
2398 if (desc_info->frame_type != RTW89_RX_TYPE_DATA)
2399 return;
2400
2401 iter_data.rtwdev = rtwdev;
2402 iter_data.rx_status = rx_status;
2403 iter_data.desc_info = desc_info;
2404 iter_data.mac_id = desc_info->mac_id;
2405 ieee80211_iterate_stations_atomic(rtwdev->hw,
2406 rtw89_core_stats_sta_rx_status_iter,
2407 &iter_data);
2408 }
2409
rtw89_core_update_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)2410 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev,
2411 struct rtw89_rx_desc_info *desc_info,
2412 struct ieee80211_rx_status *rx_status)
2413 {
2414 const struct cfg80211_chan_def *chandef =
2415 rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0);
2416 u16 data_rate;
2417 u8 data_rate_mode;
2418 bool eht = false;
2419 u8 gi;
2420
2421 /* currently using single PHY */
2422 rx_status->freq = chandef->chan->center_freq;
2423 rx_status->band = chandef->chan->band;
2424
2425 if (rtwdev->scanning &&
2426 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) {
2427 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev);
2428 u8 chan = cur->primary_channel;
2429 u8 band = cur->band_type;
2430 enum nl80211_band nl_band;
2431
2432 nl_band = rtw89_hw_to_nl80211_band(band);
2433 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band);
2434 rx_status->band = nl_band;
2435 }
2436
2437 if (desc_info->icv_err || desc_info->crc32_err)
2438 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2439
2440 if (desc_info->hw_dec &&
2441 !(desc_info->sw_dec || desc_info->icv_err))
2442 rx_status->flag |= RX_FLAG_DECRYPTED;
2443
2444 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
2445
2446 data_rate = desc_info->data_rate;
2447 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
2448 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
2449 rx_status->encoding = RX_ENC_LEGACY;
2450 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
2451 /* convert rate_idx after we get the correct band */
2452 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
2453 rx_status->encoding = RX_ENC_HT;
2454 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
2455 if (desc_info->gi_ltf)
2456 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2457 } else if (data_rate_mode == DATA_RATE_MODE_VHT) {
2458 rx_status->encoding = RX_ENC_VHT;
2459 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2460 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
2461 if (desc_info->gi_ltf)
2462 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2463 } else if (data_rate_mode == DATA_RATE_MODE_HE) {
2464 rx_status->encoding = RX_ENC_HE;
2465 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2466 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
2467 } else if (data_rate_mode == DATA_RATE_MODE_EHT) {
2468 rx_status->encoding = RX_ENC_EHT;
2469 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2470 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
2471 eht = true;
2472 } else {
2473 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
2474 }
2475
2476 /* he_gi is used to match ppdu, so we always fill it. */
2477 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht);
2478 if (eht)
2479 rx_status->eht.gi = gi;
2480 else
2481 rx_status->he_gi = gi;
2482 rx_status->flag |= RX_FLAG_MACTIME_START;
2483 rx_status->mactime = desc_info->free_run_cnt;
2484
2485 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status);
2486 }
2487
rtw89_update_ps_mode(struct rtw89_dev * rtwdev)2488 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev)
2489 {
2490 const struct rtw89_chip_info *chip = rtwdev->chip;
2491
2492 if (rtw89_disable_ps_mode || !chip->ps_mode_supported ||
2493 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw))
2494 return RTW89_PS_MODE_NONE;
2495
2496 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) &&
2497 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw))
2498 return RTW89_PS_MODE_PWR_GATED;
2499
2500 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED))
2501 return RTW89_PS_MODE_CLK_GATED;
2502
2503 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF))
2504 return RTW89_PS_MODE_RFOFF;
2505
2506 return RTW89_PS_MODE_NONE;
2507 }
2508
rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info)2509 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev,
2510 struct rtw89_rx_desc_info *desc_info)
2511 {
2512 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
2513 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2514 struct ieee80211_rx_status *rx_status;
2515 struct sk_buff *skb_ppdu, *tmp;
2516
2517 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) {
2518 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]);
2519 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
2520 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status);
2521 }
2522 }
2523
rtw89_core_rx(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2524 void rtw89_core_rx(struct rtw89_dev *rtwdev,
2525 struct rtw89_rx_desc_info *desc_info,
2526 struct sk_buff *skb)
2527 {
2528 struct ieee80211_rx_status *rx_status;
2529 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
2530 u8 ppdu_cnt = desc_info->ppdu_cnt;
2531 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2532
2533 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) {
2534 rtw89_core_rx_process_report(rtwdev, desc_info, skb);
2535 return;
2536 }
2537
2538 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) {
2539 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info);
2540 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt;
2541 }
2542
2543 rx_status = IEEE80211_SKB_RXCB(skb);
2544 memset(rx_status, 0, sizeof(*rx_status));
2545 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status);
2546 if (desc_info->long_rxdesc &&
2547 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP)
2548 skb_queue_tail(&ppdu_sts->rx_queue[band], skb);
2549 else
2550 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status);
2551 }
2552 EXPORT_SYMBOL(rtw89_core_rx);
2553
rtw89_core_napi_start(struct rtw89_dev * rtwdev)2554 void rtw89_core_napi_start(struct rtw89_dev *rtwdev)
2555 {
2556 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
2557 return;
2558
2559 napi_enable(&rtwdev->napi);
2560 }
2561 EXPORT_SYMBOL(rtw89_core_napi_start);
2562
rtw89_core_napi_stop(struct rtw89_dev * rtwdev)2563 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev)
2564 {
2565 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
2566 return;
2567
2568 napi_synchronize(&rtwdev->napi);
2569 napi_disable(&rtwdev->napi);
2570 }
2571 EXPORT_SYMBOL(rtw89_core_napi_stop);
2572
rtw89_core_napi_init(struct rtw89_dev * rtwdev)2573 int rtw89_core_napi_init(struct rtw89_dev *rtwdev)
2574 {
2575 rtwdev->netdev = alloc_netdev_dummy(0);
2576 if (!rtwdev->netdev)
2577 return -ENOMEM;
2578
2579 netif_napi_add(rtwdev->netdev, &rtwdev->napi,
2580 rtwdev->hci.ops->napi_poll);
2581 return 0;
2582 }
2583 EXPORT_SYMBOL(rtw89_core_napi_init);
2584
rtw89_core_napi_deinit(struct rtw89_dev * rtwdev)2585 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev)
2586 {
2587 rtw89_core_napi_stop(rtwdev);
2588 netif_napi_del(&rtwdev->napi);
2589 free_netdev(rtwdev->netdev);
2590 }
2591 EXPORT_SYMBOL(rtw89_core_napi_deinit);
2592
rtw89_core_ba_work(struct work_struct * work)2593 static void rtw89_core_ba_work(struct work_struct *work)
2594 {
2595 struct rtw89_dev *rtwdev =
2596 container_of(work, struct rtw89_dev, ba_work);
2597 struct rtw89_txq *rtwtxq, *tmp;
2598 int ret;
2599
2600 spin_lock_bh(&rtwdev->ba_lock);
2601 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
2602 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2603 struct ieee80211_sta *sta = txq->sta;
2604 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
2605 u8 tid = txq->tid;
2606
2607 if (!sta) {
2608 rtw89_warn(rtwdev, "cannot start BA without sta\n");
2609 goto skip_ba_work;
2610 }
2611
2612 if (rtwsta->disassoc) {
2613 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2614 "cannot start BA with disassoc sta\n");
2615 goto skip_ba_work;
2616 }
2617
2618 ret = ieee80211_start_tx_ba_session(sta, tid, 0);
2619 if (ret) {
2620 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2621 "failed to setup BA session for %pM:%2d: %d\n",
2622 sta->addr, tid, ret);
2623 if (ret == -EINVAL)
2624 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags);
2625 }
2626 skip_ba_work:
2627 list_del_init(&rtwtxq->list);
2628 }
2629 spin_unlock_bh(&rtwdev->ba_lock);
2630 }
2631
rtw89_core_free_sta_pending_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2632 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
2633 struct ieee80211_sta *sta)
2634 {
2635 struct rtw89_txq *rtwtxq, *tmp;
2636
2637 spin_lock_bh(&rtwdev->ba_lock);
2638 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
2639 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2640
2641 if (sta == txq->sta)
2642 list_del_init(&rtwtxq->list);
2643 }
2644 spin_unlock_bh(&rtwdev->ba_lock);
2645 }
2646
rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2647 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
2648 struct ieee80211_sta *sta)
2649 {
2650 struct rtw89_txq *rtwtxq, *tmp;
2651
2652 spin_lock_bh(&rtwdev->ba_lock);
2653 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
2654 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2655
2656 if (sta == txq->sta) {
2657 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
2658 list_del_init(&rtwtxq->list);
2659 }
2660 }
2661 spin_unlock_bh(&rtwdev->ba_lock);
2662 }
2663
rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2664 static void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev,
2665 struct ieee80211_sta *sta)
2666 {
2667 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2668 struct sk_buff *skb, *tmp;
2669
2670 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) {
2671 skb_unlink(skb, &rtwsta->roc_queue);
2672 dev_kfree_skb_any(skb);
2673 }
2674 }
2675
rtw89_core_stop_tx_ba_session(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq)2676 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev,
2677 struct rtw89_txq *rtwtxq)
2678 {
2679 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2680 struct ieee80211_sta *sta = txq->sta;
2681 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
2682
2683 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc))
2684 return;
2685
2686 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) ||
2687 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
2688 return;
2689
2690 spin_lock_bh(&rtwdev->ba_lock);
2691 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
2692 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list);
2693 spin_unlock_bh(&rtwdev->ba_lock);
2694
2695 ieee80211_stop_tx_ba_session(sta, txq->tid);
2696 cancel_delayed_work(&rtwdev->forbid_ba_work);
2697 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work,
2698 RTW89_FORBID_BA_TIMER);
2699 }
2700
rtw89_core_txq_check_agg(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,struct sk_buff * skb)2701 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev,
2702 struct rtw89_txq *rtwtxq,
2703 struct sk_buff *skb)
2704 {
2705 struct ieee80211_hw *hw = rtwdev->hw;
2706 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2707 struct ieee80211_sta *sta = txq->sta;
2708 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
2709
2710 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
2711 return;
2712
2713 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
2714 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq);
2715 return;
2716 }
2717
2718 if (unlikely(!sta))
2719 return;
2720
2721 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags)))
2722 return;
2723
2724 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) {
2725 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU;
2726 return;
2727 }
2728
2729 spin_lock_bh(&rtwdev->ba_lock);
2730 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) {
2731 list_add_tail(&rtwtxq->list, &rtwdev->ba_list);
2732 ieee80211_queue_work(hw, &rtwdev->ba_work);
2733 }
2734 spin_unlock_bh(&rtwdev->ba_lock);
2735 }
2736
rtw89_core_txq_push(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,unsigned long frame_cnt,unsigned long byte_cnt)2737 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev,
2738 struct rtw89_txq *rtwtxq,
2739 unsigned long frame_cnt,
2740 unsigned long byte_cnt)
2741 {
2742 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2743 struct ieee80211_vif *vif = txq->vif;
2744 struct ieee80211_sta *sta = txq->sta;
2745 struct sk_buff *skb;
2746 unsigned long i;
2747 int ret;
2748
2749 rcu_read_lock();
2750 for (i = 0; i < frame_cnt; i++) {
2751 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq);
2752 if (!skb) {
2753 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n");
2754 goto out;
2755 }
2756 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb);
2757 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL);
2758 if (ret) {
2759 rtw89_err(rtwdev, "failed to push txq: %d\n", ret);
2760 ieee80211_free_txskb(rtwdev->hw, skb);
2761 break;
2762 }
2763 }
2764 out:
2765 rcu_read_unlock();
2766 }
2767
rtw89_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 tid)2768 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid)
2769 {
2770 u8 qsel, ch_dma;
2771
2772 qsel = rtw89_core_get_qsel(rtwdev, tid);
2773 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
2774
2775 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma);
2776 }
2777
rtw89_core_txq_agg_wait(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq,unsigned long * frame_cnt,bool * sched_txq,bool * reinvoke)2778 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev,
2779 struct ieee80211_txq *txq,
2780 unsigned long *frame_cnt,
2781 bool *sched_txq, bool *reinvoke)
2782 {
2783 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv;
2784 struct ieee80211_sta *sta = txq->sta;
2785 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
2786
2787 if (!sta || rtwsta->max_agg_wait <= 0)
2788 return false;
2789
2790 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID)
2791 return false;
2792
2793 if (*frame_cnt > 1) {
2794 *frame_cnt -= 1;
2795 *sched_txq = true;
2796 *reinvoke = true;
2797 rtwtxq->wait_cnt = 1;
2798 return false;
2799 }
2800
2801 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) {
2802 *reinvoke = true;
2803 rtwtxq->wait_cnt++;
2804 return true;
2805 }
2806
2807 rtwtxq->wait_cnt = 0;
2808 return false;
2809 }
2810
rtw89_core_txq_schedule(struct rtw89_dev * rtwdev,u8 ac,bool * reinvoke)2811 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke)
2812 {
2813 struct ieee80211_hw *hw = rtwdev->hw;
2814 struct ieee80211_txq *txq;
2815 struct rtw89_vif *rtwvif;
2816 struct rtw89_txq *rtwtxq;
2817 unsigned long frame_cnt;
2818 unsigned long byte_cnt;
2819 u32 tx_resource;
2820 bool sched_txq;
2821
2822 ieee80211_txq_schedule_start(hw, ac);
2823 while ((txq = ieee80211_next_txq(hw, ac))) {
2824 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
2825 rtwvif = (struct rtw89_vif *)txq->vif->drv_priv;
2826
2827 if (rtwvif->offchan) {
2828 ieee80211_return_txq(hw, txq, true);
2829 continue;
2830 }
2831 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid);
2832 sched_txq = false;
2833
2834 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt);
2835 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) {
2836 ieee80211_return_txq(hw, txq, true);
2837 continue;
2838 }
2839 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource);
2840 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt);
2841 ieee80211_return_txq(hw, txq, sched_txq);
2842 if (frame_cnt != 0)
2843 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid));
2844
2845 /* bound of tx_resource could get stuck due to burst traffic */
2846 if (frame_cnt == tx_resource)
2847 *reinvoke = true;
2848 }
2849 ieee80211_txq_schedule_end(hw, ac);
2850 }
2851
rtw89_ips_work(struct work_struct * work)2852 static void rtw89_ips_work(struct work_struct *work)
2853 {
2854 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
2855 ips_work);
2856 mutex_lock(&rtwdev->mutex);
2857 rtw89_enter_ips_by_hwflags(rtwdev);
2858 mutex_unlock(&rtwdev->mutex);
2859 }
2860
rtw89_core_txq_work(struct work_struct * w)2861 static void rtw89_core_txq_work(struct work_struct *w)
2862 {
2863 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work);
2864 bool reinvoke = false;
2865 u8 ac;
2866
2867 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2868 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke);
2869
2870 if (reinvoke) {
2871 /* reinvoke to process the last frame */
2872 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1);
2873 }
2874 }
2875
rtw89_core_txq_reinvoke_work(struct work_struct * w)2876 static void rtw89_core_txq_reinvoke_work(struct work_struct *w)
2877 {
2878 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
2879 txq_reinvoke_work.work);
2880
2881 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
2882 }
2883
rtw89_forbid_ba_work(struct work_struct * w)2884 static void rtw89_forbid_ba_work(struct work_struct *w)
2885 {
2886 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
2887 forbid_ba_work.work);
2888 struct rtw89_txq *rtwtxq, *tmp;
2889
2890 spin_lock_bh(&rtwdev->ba_lock);
2891 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
2892 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
2893 list_del_init(&rtwtxq->list);
2894 }
2895 spin_unlock_bh(&rtwdev->ba_lock);
2896 }
2897
rtw89_core_sta_pending_tx_iter(void * data,struct ieee80211_sta * sta)2898 static void rtw89_core_sta_pending_tx_iter(void *data,
2899 struct ieee80211_sta *sta)
2900 {
2901 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2902 struct rtw89_vif *rtwvif_target = data, *rtwvif = rtwsta->rtwvif;
2903 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
2904 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
2905 struct sk_buff *skb, *tmp;
2906 int qsel, ret;
2907
2908 if (rtwvif->sub_entity_idx != rtwvif_target->sub_entity_idx)
2909 return;
2910
2911 if (skb_queue_len(&rtwsta->roc_queue) == 0)
2912 return;
2913
2914 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) {
2915 skb_unlink(skb, &rtwsta->roc_queue);
2916
2917 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
2918 if (ret) {
2919 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret);
2920 dev_kfree_skb_any(skb);
2921 } else {
2922 rtw89_core_tx_kick_off(rtwdev, qsel);
2923 }
2924 }
2925 }
2926
rtw89_core_handle_sta_pending_tx(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)2927 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev,
2928 struct rtw89_vif *rtwvif)
2929 {
2930 ieee80211_iterate_stations_atomic(rtwdev->hw,
2931 rtw89_core_sta_pending_tx_iter,
2932 rtwvif);
2933 }
2934
rtw89_core_send_nullfunc(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool qos,bool ps)2935 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev,
2936 struct rtw89_vif *rtwvif, bool qos, bool ps)
2937 {
2938 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
2939 struct ieee80211_sta *sta;
2940 struct ieee80211_hdr *hdr;
2941 struct sk_buff *skb;
2942 int ret, qsel;
2943
2944 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
2945 return 0;
2946
2947 rcu_read_lock();
2948 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid);
2949 if (!sta) {
2950 ret = -EINVAL;
2951 goto out;
2952 }
2953
2954 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, qos);
2955 if (!skb) {
2956 ret = -ENOMEM;
2957 goto out;
2958 }
2959
2960 hdr = (struct ieee80211_hdr *)skb->data;
2961 if (ps)
2962 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2963
2964 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
2965 if (ret) {
2966 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret);
2967 dev_kfree_skb_any(skb);
2968 goto out;
2969 }
2970
2971 rcu_read_unlock();
2972
2973 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel,
2974 RTW89_ROC_TX_TIMEOUT);
2975 out:
2976 rcu_read_unlock();
2977
2978 return ret;
2979 }
2980
rtw89_roc_start(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)2981 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
2982 {
2983 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2984 struct ieee80211_hw *hw = rtwdev->hw;
2985 struct rtw89_roc *roc = &rtwvif->roc;
2986 struct cfg80211_chan_def roc_chan;
2987 struct rtw89_vif *tmp;
2988 int ret;
2989
2990 lockdep_assert_held(&rtwdev->mutex);
2991
2992 rtw89_leave_ips_by_hwflags(rtwdev);
2993 rtw89_leave_lps(rtwdev);
2994 rtw89_chanctx_pause(rtwdev, RTW89_CHANCTX_PAUSE_REASON_ROC);
2995
2996 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, true);
2997 if (ret)
2998 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2999 "roc send null-1 failed: %d\n", ret);
3000
3001 rtw89_for_each_rtwvif(rtwdev, tmp)
3002 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx)
3003 tmp->offchan = true;
3004
3005 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT);
3006 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, &roc_chan);
3007 rtw89_set_channel(rtwdev);
3008 rtw89_write32_clr(rtwdev,
3009 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0),
3010 B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH);
3011
3012 ieee80211_ready_on_channel(hw);
3013 cancel_delayed_work(&rtwvif->roc.roc_work);
3014 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work,
3015 msecs_to_jiffies(rtwvif->roc.duration));
3016 }
3017
rtw89_roc_end(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3018 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3019 {
3020 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3021 struct ieee80211_hw *hw = rtwdev->hw;
3022 struct rtw89_roc *roc = &rtwvif->roc;
3023 struct rtw89_vif *tmp;
3024 int ret;
3025
3026 lockdep_assert_held(&rtwdev->mutex);
3027
3028 ieee80211_remain_on_channel_expired(hw);
3029
3030 rtw89_leave_ips_by_hwflags(rtwdev);
3031 rtw89_leave_lps(rtwdev);
3032
3033 rtw89_write32_mask(rtwdev,
3034 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0),
3035 B_AX_RX_FLTR_CFG_MASK,
3036 rtwdev->hal.rx_fltr);
3037
3038 roc->state = RTW89_ROC_IDLE;
3039 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, NULL);
3040 rtw89_chanctx_proceed(rtwdev);
3041 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, false);
3042 if (ret)
3043 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
3044 "roc send null-0 failed: %d\n", ret);
3045
3046 rtw89_for_each_rtwvif(rtwdev, tmp)
3047 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx)
3048 tmp->offchan = false;
3049
3050 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif);
3051 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
3052
3053 if (hw->conf.flags & IEEE80211_CONF_IDLE)
3054 ieee80211_queue_delayed_work(hw, &roc->roc_work,
3055 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT));
3056 }
3057
rtw89_roc_work(struct work_struct * work)3058 void rtw89_roc_work(struct work_struct *work)
3059 {
3060 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif,
3061 roc.roc_work.work);
3062 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
3063 struct rtw89_roc *roc = &rtwvif->roc;
3064
3065 mutex_lock(&rtwdev->mutex);
3066
3067 switch (roc->state) {
3068 case RTW89_ROC_IDLE:
3069 rtw89_enter_ips_by_hwflags(rtwdev);
3070 break;
3071 case RTW89_ROC_MGMT:
3072 case RTW89_ROC_NORMAL:
3073 rtw89_roc_end(rtwdev, rtwvif);
3074 break;
3075 default:
3076 break;
3077 }
3078
3079 mutex_unlock(&rtwdev->mutex);
3080 }
3081
rtw89_get_traffic_level(struct rtw89_dev * rtwdev,u32 throughput,u64 cnt)3082 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev,
3083 u32 throughput, u64 cnt)
3084 {
3085 if (cnt < 100)
3086 return RTW89_TFC_IDLE;
3087 if (throughput > 50)
3088 return RTW89_TFC_HIGH;
3089 if (throughput > 10)
3090 return RTW89_TFC_MID;
3091 if (throughput > 2)
3092 return RTW89_TFC_LOW;
3093 return RTW89_TFC_ULTRA_LOW;
3094 }
3095
rtw89_traffic_stats_calc(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)3096 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev,
3097 struct rtw89_traffic_stats *stats)
3098 {
3099 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv;
3100 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv;
3101
3102 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT);
3103 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT);
3104
3105 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw);
3106 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw);
3107
3108 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
3109 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
3110 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput,
3111 stats->tx_cnt);
3112 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput,
3113 stats->rx_cnt);
3114 stats->tx_avg_len = stats->tx_cnt ?
3115 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0;
3116 stats->rx_avg_len = stats->rx_cnt ?
3117 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0;
3118
3119 stats->tx_unicast = 0;
3120 stats->rx_unicast = 0;
3121 stats->tx_cnt = 0;
3122 stats->rx_cnt = 0;
3123 stats->rx_tf_periodic = stats->rx_tf_acc;
3124 stats->rx_tf_acc = 0;
3125
3126 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv)
3127 return true;
3128
3129 return false;
3130 }
3131
rtw89_traffic_stats_track(struct rtw89_dev * rtwdev)3132 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev)
3133 {
3134 struct rtw89_vif *rtwvif;
3135 bool tfc_changed;
3136
3137 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats);
3138 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
3139 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats);
3140 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif);
3141 }
3142
3143 return tfc_changed;
3144 }
3145
rtw89_vif_enter_lps(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3146 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3147 {
3148 if ((rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION &&
3149 rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT) ||
3150 rtwvif->tdls_peer)
3151 return;
3152
3153 if (rtwvif->offchan)
3154 return;
3155
3156 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE &&
3157 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE)
3158 rtw89_enter_lps(rtwdev, rtwvif, true);
3159 }
3160
rtw89_enter_lps_track(struct rtw89_dev * rtwdev)3161 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev)
3162 {
3163 struct rtw89_vif *rtwvif;
3164
3165 rtw89_for_each_rtwvif(rtwdev, rtwvif)
3166 rtw89_vif_enter_lps(rtwdev, rtwvif);
3167 }
3168
rtw89_core_rfk_track(struct rtw89_dev * rtwdev)3169 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev)
3170 {
3171 enum rtw89_entity_mode mode;
3172
3173 mode = rtw89_get_entity_mode(rtwdev);
3174 if (mode == RTW89_ENTITY_MODE_MCC)
3175 return;
3176
3177 rtw89_chip_rfk_track(rtwdev);
3178 }
3179
rtw89_core_update_p2p_ps(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif)3180 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif)
3181 {
3182 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev);
3183
3184 if (mode == RTW89_ENTITY_MODE_MCC)
3185 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE);
3186 else
3187 rtw89_process_p2p_ps(rtwdev, vif);
3188 }
3189
rtw89_traffic_stats_init(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)3190 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
3191 struct rtw89_traffic_stats *stats)
3192 {
3193 stats->tx_unicast = 0;
3194 stats->rx_unicast = 0;
3195 stats->tx_cnt = 0;
3196 stats->rx_cnt = 0;
3197 ewma_tp_init(&stats->tx_ewma_tp);
3198 ewma_tp_init(&stats->rx_ewma_tp);
3199 }
3200
rtw89_track_work(struct work_struct * work)3201 static void rtw89_track_work(struct work_struct *work)
3202 {
3203 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
3204 track_work.work);
3205 bool tfc_changed;
3206
3207 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags))
3208 return;
3209
3210 mutex_lock(&rtwdev->mutex);
3211
3212 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
3213 goto out;
3214
3215 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
3216 RTW89_TRACK_WORK_PERIOD);
3217
3218 tfc_changed = rtw89_traffic_stats_track(rtwdev);
3219 if (rtwdev->scanning)
3220 goto out;
3221
3222 rtw89_leave_lps(rtwdev);
3223
3224 if (tfc_changed) {
3225 rtw89_hci_recalc_int_mit(rtwdev);
3226 rtw89_btc_ntfy_wl_sta(rtwdev);
3227 }
3228 rtw89_mac_bf_monitor_track(rtwdev);
3229 rtw89_phy_stat_track(rtwdev);
3230 rtw89_phy_env_monitor_track(rtwdev);
3231 rtw89_phy_dig(rtwdev);
3232 rtw89_core_rfk_track(rtwdev);
3233 rtw89_phy_ra_update(rtwdev);
3234 rtw89_phy_cfo_track(rtwdev);
3235 rtw89_phy_tx_path_div_track(rtwdev);
3236 rtw89_phy_antdiv_track(rtwdev);
3237 rtw89_phy_ul_tb_ctrl_track(rtwdev);
3238 rtw89_phy_edcca_track(rtwdev);
3239 rtw89_tas_track(rtwdev);
3240 rtw89_chanctx_track(rtwdev);
3241
3242 if (rtwdev->lps_enabled && !rtwdev->btc.lps)
3243 rtw89_enter_lps_track(rtwdev);
3244
3245 out:
3246 mutex_unlock(&rtwdev->mutex);
3247 }
3248
rtw89_core_acquire_bit_map(unsigned long * addr,unsigned long size)3249 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size)
3250 {
3251 unsigned long bit;
3252
3253 bit = find_first_zero_bit(addr, size);
3254 if (bit < size)
3255 set_bit(bit, addr);
3256
3257 return bit;
3258 }
3259
rtw89_core_release_bit_map(unsigned long * addr,u8 bit)3260 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit)
3261 {
3262 clear_bit(bit, addr);
3263 }
3264
rtw89_core_release_all_bits_map(unsigned long * addr,unsigned int nbits)3265 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits)
3266 {
3267 bitmap_zero(addr, nbits);
3268 }
3269
rtw89_core_acquire_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u8 tid,u8 * cam_idx)3270 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
3271 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx)
3272 {
3273 const struct rtw89_chip_info *chip = rtwdev->chip;
3274 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
3275 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
3276 u8 idx;
3277 int i;
3278
3279 lockdep_assert_held(&rtwdev->mutex);
3280
3281 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num);
3282 if (idx == chip->bacam_num) {
3283 /* allocate a static BA CAM to tid=0/5, so replace the existing
3284 * one if BA CAM is full. Hardware will process the original tid
3285 * automatically.
3286 */
3287 if (tid != 0 && tid != 5)
3288 return -ENOSPC;
3289
3290 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) {
3291 tmp = &cam_info->ba_cam_entry[i];
3292 if (tmp->tid == 0 || tmp->tid == 5)
3293 continue;
3294
3295 idx = i;
3296 entry = tmp;
3297 list_del(&entry->list);
3298 break;
3299 }
3300
3301 if (!entry)
3302 return -ENOSPC;
3303 } else {
3304 entry = &cam_info->ba_cam_entry[idx];
3305 }
3306
3307 entry->tid = tid;
3308 list_add_tail(&entry->list, &rtwsta->ba_cam_list);
3309
3310 *cam_idx = idx;
3311
3312 return 0;
3313 }
3314
rtw89_core_release_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u8 tid,u8 * cam_idx)3315 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
3316 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx)
3317 {
3318 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
3319 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
3320 u8 idx;
3321
3322 lockdep_assert_held(&rtwdev->mutex);
3323
3324 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) {
3325 if (entry->tid != tid)
3326 continue;
3327
3328 idx = entry - cam_info->ba_cam_entry;
3329 list_del(&entry->list);
3330
3331 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx);
3332 *cam_idx = idx;
3333 return 0;
3334 }
3335
3336 return -ENOENT;
3337 }
3338
3339 #define RTW89_TYPE_MAPPING(_type) \
3340 case NL80211_IFTYPE_ ## _type: \
3341 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \
3342 break
rtw89_vif_type_mapping(struct ieee80211_vif * vif,bool assoc)3343 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc)
3344 {
3345 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3346
3347 switch (vif->type) {
3348 case NL80211_IFTYPE_STATION:
3349 if (vif->p2p)
3350 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT;
3351 else
3352 rtwvif->wifi_role = RTW89_WIFI_ROLE_STATION;
3353 break;
3354 case NL80211_IFTYPE_AP:
3355 if (vif->p2p)
3356 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_GO;
3357 else
3358 rtwvif->wifi_role = RTW89_WIFI_ROLE_AP;
3359 break;
3360 RTW89_TYPE_MAPPING(ADHOC);
3361 RTW89_TYPE_MAPPING(MONITOR);
3362 RTW89_TYPE_MAPPING(MESH_POINT);
3363 default:
3364 WARN_ON(1);
3365 break;
3366 }
3367
3368 switch (vif->type) {
3369 case NL80211_IFTYPE_AP:
3370 case NL80211_IFTYPE_MESH_POINT:
3371 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE;
3372 rtwvif->self_role = RTW89_SELF_ROLE_AP;
3373 break;
3374 case NL80211_IFTYPE_ADHOC:
3375 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC;
3376 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT;
3377 break;
3378 case NL80211_IFTYPE_STATION:
3379 if (assoc) {
3380 rtwvif->net_type = RTW89_NET_TYPE_INFRA;
3381 rtwvif->trigger = vif->bss_conf.he_support;
3382 } else {
3383 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK;
3384 rtwvif->trigger = false;
3385 }
3386 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT;
3387 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL;
3388 break;
3389 case NL80211_IFTYPE_MONITOR:
3390 break;
3391 default:
3392 WARN_ON(1);
3393 break;
3394 }
3395 }
3396
rtw89_core_sta_add(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)3397 int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
3398 struct ieee80211_vif *vif,
3399 struct ieee80211_sta *sta)
3400 {
3401 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3402 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
3403 struct rtw89_hal *hal = &rtwdev->hal;
3404 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
3405 int i;
3406 int ret;
3407
3408 rtwsta->rtwdev = rtwdev;
3409 rtwsta->rtwvif = rtwvif;
3410 rtwsta->prev_rssi = 0;
3411 INIT_LIST_HEAD(&rtwsta->ba_cam_list);
3412 skb_queue_head_init(&rtwsta->roc_queue);
3413
3414 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
3415 rtw89_core_txq_init(rtwdev, sta->txq[i]);
3416
3417 ewma_rssi_init(&rtwsta->avg_rssi);
3418 ewma_snr_init(&rtwsta->avg_snr);
3419 for (i = 0; i < ant_num; i++) {
3420 ewma_rssi_init(&rtwsta->rssi[i]);
3421 ewma_evm_init(&rtwsta->evm_min[i]);
3422 ewma_evm_init(&rtwsta->evm_max[i]);
3423 }
3424
3425 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3426 /* for station mode, assign the mac_id from itself */
3427 rtwsta->mac_id = rtwvif->mac_id;
3428
3429 /* must do rtw89_reg_6ghz_recalc() before rfk channel */
3430 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif, true);
3431 if (ret)
3432 return ret;
3433
3434 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
3435 BTC_ROLE_MSTS_STA_CONN_START);
3436 rtw89_chip_rfk_channel(rtwdev);
3437 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3438 rtwsta->mac_id = rtw89_acquire_mac_id(rtwdev);
3439 if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM)
3440 return -ENOSPC;
3441
3442 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false);
3443 if (ret) {
3444 rtw89_release_mac_id(rtwdev, rtwsta->mac_id);
3445 rtw89_warn(rtwdev, "failed to send h2c macid pause\n");
3446 return ret;
3447 }
3448
3449 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta,
3450 RTW89_ROLE_CREATE);
3451 if (ret) {
3452 rtw89_release_mac_id(rtwdev, rtwsta->mac_id);
3453 rtw89_warn(rtwdev, "failed to send h2c role info\n");
3454 return ret;
3455 }
3456
3457 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif, rtwsta);
3458 if (ret)
3459 return ret;
3460
3461 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, rtwsta);
3462 if (ret)
3463 return ret;
3464
3465 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE);
3466 }
3467
3468 return 0;
3469 }
3470
rtw89_core_sta_disassoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)3471 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
3472 struct ieee80211_vif *vif,
3473 struct ieee80211_sta *sta)
3474 {
3475 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3476 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
3477
3478 if (vif->type == NL80211_IFTYPE_STATION)
3479 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, false);
3480
3481 rtwdev->total_sta_assoc--;
3482 if (sta->tdls)
3483 rtwvif->tdls_peer--;
3484 rtwsta->disassoc = true;
3485
3486 return 0;
3487 }
3488
rtw89_core_sta_disconnect(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)3489 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
3490 struct ieee80211_vif *vif,
3491 struct ieee80211_sta *sta)
3492 {
3493 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3494 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
3495 int ret;
3496
3497 rtw89_mac_bf_monitor_calc(rtwdev, sta, true);
3498 rtw89_mac_bf_disassoc(rtwdev, vif, sta);
3499 rtw89_core_free_sta_pending_ba(rtwdev, sta);
3500 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta);
3501 rtw89_core_free_sta_pending_roc_tx(rtwdev, sta);
3502
3503 if (vif->type == NL80211_IFTYPE_AP || sta->tdls)
3504 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam);
3505 if (sta->tdls)
3506 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam);
3507
3508 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3509 rtw89_vif_type_mapping(vif, false);
3510 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif, true);
3511 }
3512
3513 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, vif, sta);
3514 if (ret) {
3515 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
3516 return ret;
3517 }
3518
3519 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true);
3520 if (ret) {
3521 rtw89_warn(rtwdev, "failed to send h2c join info\n");
3522 return ret;
3523 }
3524
3525 /* update cam aid mac_id net_type */
3526 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL);
3527 if (ret) {
3528 rtw89_warn(rtwdev, "failed to send h2c cam\n");
3529 return ret;
3530 }
3531
3532 return ret;
3533 }
3534
rtw89_core_sta_assoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)3535 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
3536 struct ieee80211_vif *vif,
3537 struct ieee80211_sta *sta)
3538 {
3539 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3540 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
3541 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta);
3542 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
3543 rtwvif->sub_entity_idx);
3544 int ret;
3545
3546 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3547 if (sta->tdls) {
3548 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr);
3549 if (ret) {
3550 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n");
3551 return ret;
3552 }
3553 }
3554
3555 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam);
3556 if (ret) {
3557 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n");
3558 return ret;
3559 }
3560 }
3561
3562 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, vif, sta);
3563 if (ret) {
3564 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
3565 return ret;
3566 }
3567
3568 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false);
3569 if (ret) {
3570 rtw89_warn(rtwdev, "failed to send h2c join info\n");
3571 return ret;
3572 }
3573
3574 /* update cam aid mac_id net_type */
3575 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL);
3576 if (ret) {
3577 rtw89_warn(rtwdev, "failed to send h2c cam\n");
3578 return ret;
3579 }
3580
3581 rtwdev->total_sta_assoc++;
3582 if (sta->tdls)
3583 rtwvif->tdls_peer++;
3584 rtw89_phy_ra_assoc(rtwdev, sta);
3585 rtw89_mac_bf_assoc(rtwdev, vif, sta);
3586 rtw89_mac_bf_monitor_calc(rtwdev, sta, false);
3587
3588 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3589 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
3590
3591 if (bss_conf->he_support &&
3592 !(bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE))
3593 rtwsta->er_cap = true;
3594
3595 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
3596 BTC_ROLE_MSTS_STA_CONN_END);
3597 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template, chan);
3598 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif);
3599
3600 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif, rtwsta->mac_id);
3601 if (ret) {
3602 rtw89_warn(rtwdev, "failed to send h2c general packet\n");
3603 return ret;
3604 }
3605
3606 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true);
3607 }
3608
3609 return ret;
3610 }
3611
rtw89_core_sta_remove(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)3612 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
3613 struct ieee80211_vif *vif,
3614 struct ieee80211_sta *sta)
3615 {
3616 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3617 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
3618 int ret;
3619
3620 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3621 rtw89_reg_6ghz_recalc(rtwdev, rtwvif, false);
3622 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
3623 BTC_ROLE_MSTS_STA_DIS_CONN);
3624 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3625 rtw89_release_mac_id(rtwdev, rtwsta->mac_id);
3626
3627 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta,
3628 RTW89_ROLE_REMOVE);
3629 if (ret) {
3630 rtw89_warn(rtwdev, "failed to send h2c role info\n");
3631 return ret;
3632 }
3633
3634 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE);
3635 }
3636
3637 return 0;
3638 }
3639
_rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_cfg * tid_conf)3640 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
3641 struct ieee80211_sta *sta,
3642 struct cfg80211_tid_cfg *tid_conf)
3643 {
3644 struct ieee80211_txq *txq;
3645 struct rtw89_txq *rtwtxq;
3646 u32 mask = tid_conf->mask;
3647 u8 tids = tid_conf->tids;
3648 int tids_nbit = BITS_PER_BYTE;
3649 int i;
3650
3651 for (i = 0; i < tids_nbit; i++, tids >>= 1) {
3652 if (!tids)
3653 break;
3654
3655 if (!(tids & BIT(0)))
3656 continue;
3657
3658 txq = sta->txq[i];
3659 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
3660
3661 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) {
3662 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) {
3663 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
3664 } else {
3665 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags))
3666 ieee80211_stop_tx_ba_session(sta, txq->tid);
3667 spin_lock_bh(&rtwdev->ba_lock);
3668 list_del_init(&rtwtxq->list);
3669 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
3670 spin_unlock_bh(&rtwdev->ba_lock);
3671 }
3672 }
3673
3674 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) {
3675 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE)
3676 sta->max_amsdu_subframes = 0;
3677 else
3678 sta->max_amsdu_subframes = 1;
3679 }
3680 }
3681 }
3682
rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_config * tid_config)3683 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
3684 struct ieee80211_sta *sta,
3685 struct cfg80211_tid_config *tid_config)
3686 {
3687 int i;
3688
3689 for (i = 0; i < tid_config->n_tid_conf; i++)
3690 _rtw89_core_set_tid_config(rtwdev, sta,
3691 &tid_config->tid_conf[i]);
3692 }
3693
rtw89_init_ht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_ht_cap * ht_cap)3694 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev,
3695 struct ieee80211_sta_ht_cap *ht_cap)
3696 {
3697 static const __le16 highest[RF_PATH_MAX] = {
3698 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600),
3699 };
3700 struct rtw89_hal *hal = &rtwdev->hal;
3701 u8 nss = hal->rx_nss;
3702 int i;
3703
3704 ht_cap->ht_supported = true;
3705 ht_cap->cap = 0;
3706 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
3707 IEEE80211_HT_CAP_MAX_AMSDU |
3708 IEEE80211_HT_CAP_TX_STBC |
3709 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
3710 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
3711 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
3712 IEEE80211_HT_CAP_DSSSCCK40 |
3713 IEEE80211_HT_CAP_SGI_40;
3714 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
3715 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
3716 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
3717 for (i = 0; i < nss; i++)
3718 ht_cap->mcs.rx_mask[i] = 0xFF;
3719 ht_cap->mcs.rx_mask[4] = 0x01;
3720 ht_cap->mcs.rx_highest = highest[nss - 1];
3721 }
3722
rtw89_init_vht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_vht_cap * vht_cap)3723 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev,
3724 struct ieee80211_sta_vht_cap *vht_cap)
3725 {
3726 static const __le16 highest_bw80[RF_PATH_MAX] = {
3727 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733),
3728 };
3729 static const __le16 highest_bw160[RF_PATH_MAX] = {
3730 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467),
3731 };
3732 const struct rtw89_chip_info *chip = rtwdev->chip;
3733 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ?
3734 highest_bw160 : highest_bw80;
3735 struct rtw89_hal *hal = &rtwdev->hal;
3736 u16 tx_mcs_map = 0, rx_mcs_map = 0;
3737 u8 sts_cap = 3;
3738 int i;
3739
3740 for (i = 0; i < 8; i++) {
3741 if (i < hal->tx_nss)
3742 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
3743 else
3744 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
3745 if (i < hal->rx_nss)
3746 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
3747 else
3748 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
3749 }
3750
3751 vht_cap->vht_supported = true;
3752 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
3753 IEEE80211_VHT_CAP_SHORT_GI_80 |
3754 IEEE80211_VHT_CAP_RXSTBC_1 |
3755 IEEE80211_VHT_CAP_HTC_VHT |
3756 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
3757 0;
3758 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
3759 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
3760 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
3761 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
3762 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT;
3763 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
3764 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
3765 IEEE80211_VHT_CAP_SHORT_GI_160;
3766 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map);
3767 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map);
3768 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1];
3769 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1];
3770
3771 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW))
3772 vht_cap->vht_mcs.tx_highest |=
3773 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
3774 }
3775
rtw89_init_he_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)3776 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev,
3777 enum nl80211_band band,
3778 enum nl80211_iftype iftype,
3779 struct ieee80211_sband_iftype_data *iftype_data)
3780 {
3781 const struct rtw89_chip_info *chip = rtwdev->chip;
3782 struct rtw89_hal *hal = &rtwdev->hal;
3783 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) ||
3784 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV);
3785 struct ieee80211_sta_he_cap *he_cap;
3786 int nss = hal->rx_nss;
3787 u8 *mac_cap_info;
3788 u8 *phy_cap_info;
3789 u16 mcs_map = 0;
3790 int i;
3791
3792 for (i = 0; i < 8; i++) {
3793 if (i < nss)
3794 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2);
3795 else
3796 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2);
3797 }
3798
3799 he_cap = &iftype_data->he_cap;
3800 mac_cap_info = he_cap->he_cap_elem.mac_cap_info;
3801 phy_cap_info = he_cap->he_cap_elem.phy_cap_info;
3802
3803 he_cap->has_he = true;
3804 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE;
3805 if (iftype == NL80211_IFTYPE_STATION)
3806 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
3807 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK |
3808 IEEE80211_HE_MAC_CAP2_BSR;
3809 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2;
3810 if (iftype == NL80211_IFTYPE_AP)
3811 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL;
3812 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS |
3813 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
3814 if (iftype == NL80211_IFTYPE_STATION)
3815 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX;
3816 if (band == NL80211_BAND_2GHZ) {
3817 phy_cap_info[0] =
3818 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
3819 } else {
3820 phy_cap_info[0] =
3821 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G;
3822 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
3823 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
3824 }
3825 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
3826 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD |
3827 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
3828 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
3829 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
3830 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ |
3831 IEEE80211_HE_PHY_CAP2_DOPPLER_TX;
3832 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM;
3833 if (iftype == NL80211_IFTYPE_STATION)
3834 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM |
3835 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2;
3836 if (iftype == NL80211_IFTYPE_AP)
3837 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU;
3838 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
3839 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4;
3840 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
3841 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
3842 phy_cap_info[5] = no_ng16 ? 0 :
3843 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK |
3844 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK;
3845 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
3846 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU |
3847 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
3848 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE;
3849 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
3850 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
3851 IEEE80211_HE_PHY_CAP7_MAX_NC_1;
3852 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
3853 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI |
3854 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996;
3855 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
3856 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
3857 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;
3858 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
3859 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
3860 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
3861 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
3862 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
3863 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
3864 if (iftype == NL80211_IFTYPE_STATION)
3865 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
3866 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map);
3867 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map);
3868 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) {
3869 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map);
3870 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map);
3871 }
3872
3873 if (band == NL80211_BAND_6GHZ) {
3874 __le16 capa;
3875
3876 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE,
3877 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
3878 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
3879 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
3880 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
3881 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
3882 iftype_data->he_6ghz_capa.capa = capa;
3883 }
3884 }
3885
rtw89_init_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)3886 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev,
3887 enum nl80211_band band,
3888 enum nl80211_iftype iftype,
3889 struct ieee80211_sband_iftype_data *iftype_data)
3890 {
3891 const struct rtw89_chip_info *chip = rtwdev->chip;
3892 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem;
3893 struct ieee80211_eht_mcs_nss_supp *eht_nss;
3894 struct ieee80211_sta_eht_cap *eht_cap;
3895 struct rtw89_hal *hal = &rtwdev->hal;
3896 bool support_320mhz = false;
3897 int sts = 8;
3898 u8 val;
3899
3900 if (chip->chip_gen == RTW89_CHIP_AX)
3901 return;
3902
3903 if (band == NL80211_BAND_6GHZ &&
3904 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320))
3905 support_320mhz = true;
3906
3907 eht_cap = &iftype_data->eht_cap;
3908 eht_cap_elem = &eht_cap->eht_cap_elem;
3909 eht_nss = &eht_cap->eht_mcs_nss_supp;
3910
3911 eht_cap->has_eht = true;
3912
3913 eht_cap_elem->mac_cap_info[0] =
3914 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991,
3915 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
3916 eht_cap_elem->mac_cap_info[1] = 0;
3917
3918 eht_cap_elem->phy_cap_info[0] =
3919 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
3920 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE;
3921 if (support_320mhz)
3922 eht_cap_elem->phy_cap_info[0] |=
3923 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
3924
3925 eht_cap_elem->phy_cap_info[0] |=
3926 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)),
3927 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK);
3928 eht_cap_elem->phy_cap_info[1] =
3929 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)),
3930 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) |
3931 u8_encode_bits(sts - 1,
3932 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK);
3933 if (support_320mhz)
3934 eht_cap_elem->phy_cap_info[1] |=
3935 u8_encode_bits(sts - 1,
3936 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK);
3937
3938 eht_cap_elem->phy_cap_info[2] = 0;
3939
3940 eht_cap_elem->phy_cap_info[3] =
3941 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
3942 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
3943 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
3944 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK;
3945
3946 eht_cap_elem->phy_cap_info[4] =
3947 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP |
3948 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK);
3949
3950 eht_cap_elem->phy_cap_info[5] =
3951 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US,
3952 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK);
3953
3954 eht_cap_elem->phy_cap_info[6] = 0;
3955 eht_cap_elem->phy_cap_info[7] = 0;
3956 eht_cap_elem->phy_cap_info[8] = 0;
3957
3958 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) |
3959 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX);
3960 eht_nss->bw._80.rx_tx_mcs9_max_nss = val;
3961 eht_nss->bw._80.rx_tx_mcs11_max_nss = val;
3962 eht_nss->bw._80.rx_tx_mcs13_max_nss = val;
3963 eht_nss->bw._160.rx_tx_mcs9_max_nss = val;
3964 eht_nss->bw._160.rx_tx_mcs11_max_nss = val;
3965 eht_nss->bw._160.rx_tx_mcs13_max_nss = val;
3966 if (support_320mhz) {
3967 eht_nss->bw._320.rx_tx_mcs9_max_nss = val;
3968 eht_nss->bw._320.rx_tx_mcs11_max_nss = val;
3969 eht_nss->bw._320.rx_tx_mcs13_max_nss = val;
3970 }
3971 }
3972
3973 #define RTW89_SBAND_IFTYPES_NR 2
3974
rtw89_init_he_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,struct ieee80211_supported_band * sband)3975 static void rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev,
3976 enum nl80211_band band,
3977 struct ieee80211_supported_band *sband)
3978 {
3979 struct ieee80211_sband_iftype_data *iftype_data;
3980 enum nl80211_iftype iftype;
3981 int idx = 0;
3982
3983 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL);
3984 if (!iftype_data)
3985 return;
3986
3987 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) {
3988 switch (iftype) {
3989 case NL80211_IFTYPE_STATION:
3990 case NL80211_IFTYPE_AP:
3991 break;
3992 default:
3993 continue;
3994 }
3995
3996 if (idx >= RTW89_SBAND_IFTYPES_NR) {
3997 rtw89_warn(rtwdev, "run out of iftype_data\n");
3998 break;
3999 }
4000
4001 iftype_data[idx].types_mask = BIT(iftype);
4002
4003 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]);
4004 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]);
4005
4006 idx++;
4007 }
4008
4009 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx);
4010 }
4011
rtw89_core_set_supported_band(struct rtw89_dev * rtwdev)4012 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev)
4013 {
4014 struct ieee80211_hw *hw = rtwdev->hw;
4015 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL;
4016 struct ieee80211_supported_band *sband_6ghz = NULL;
4017 u32 size = sizeof(struct ieee80211_supported_band);
4018 u8 support_bands = rtwdev->chip->support_bands;
4019
4020 if (support_bands & BIT(NL80211_BAND_2GHZ)) {
4021 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL);
4022 if (!sband_2ghz)
4023 goto err;
4024 #if defined(__FreeBSD__)
4025 if (rtw_ht_support)
4026 #endif
4027 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap);
4028 #if defined(__FreeBSD__)
4029 if (rtw_eht_support)
4030 #endif
4031 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz);
4032 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz;
4033 }
4034
4035 if (support_bands & BIT(NL80211_BAND_5GHZ)) {
4036 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL);
4037 if (!sband_5ghz)
4038 goto err;
4039 #if defined(__FreeBSD__)
4040 if (rtw_ht_support)
4041 #endif
4042 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap);
4043 #if defined(__FreeBSD__)
4044 if (rtw_vht_support)
4045 #endif
4046 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap);
4047 #if defined(__FreeBSD__)
4048 if (rtw_eht_support)
4049 #endif
4050 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz);
4051 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz;
4052 }
4053
4054 if (support_bands & BIT(NL80211_BAND_6GHZ)) {
4055 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL);
4056 if (!sband_6ghz)
4057 goto err;
4058 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz);
4059 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz;
4060 }
4061
4062 return 0;
4063
4064 err:
4065 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
4066 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL;
4067 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL;
4068 if (sband_2ghz)
4069 kfree((__force void *)sband_2ghz->iftype_data);
4070 if (sband_5ghz)
4071 kfree((__force void *)sband_5ghz->iftype_data);
4072 if (sband_6ghz)
4073 kfree((__force void *)sband_6ghz->iftype_data);
4074 kfree(sband_2ghz);
4075 kfree(sband_5ghz);
4076 kfree(sband_6ghz);
4077 return -ENOMEM;
4078 }
4079
rtw89_core_clr_supported_band(struct rtw89_dev * rtwdev)4080 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev)
4081 {
4082 struct ieee80211_hw *hw = rtwdev->hw;
4083
4084 if (hw->wiphy->bands[NL80211_BAND_2GHZ])
4085 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data);
4086 if (hw->wiphy->bands[NL80211_BAND_5GHZ])
4087 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data);
4088 if (hw->wiphy->bands[NL80211_BAND_6GHZ])
4089 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data);
4090 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
4091 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
4092 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]);
4093 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
4094 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL;
4095 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL;
4096 }
4097
rtw89_core_ppdu_sts_init(struct rtw89_dev * rtwdev)4098 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev)
4099 {
4100 int i;
4101
4102 for (i = 0; i < RTW89_PHY_MAX; i++)
4103 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]);
4104 for (i = 0; i < RTW89_PHY_MAX; i++)
4105 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX;
4106 }
4107
rtw89_core_update_beacon_work(struct work_struct * work)4108 void rtw89_core_update_beacon_work(struct work_struct *work)
4109 {
4110 struct rtw89_dev *rtwdev;
4111 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif,
4112 update_beacon_work);
4113
4114 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE)
4115 return;
4116
4117 rtwdev = rtwvif->rtwdev;
4118 mutex_lock(&rtwdev->mutex);
4119 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif);
4120 mutex_unlock(&rtwdev->mutex);
4121 }
4122
rtw89_wait_for_cond(struct rtw89_wait_info * wait,unsigned int cond)4123 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond)
4124 {
4125 struct completion *cmpl = &wait->completion;
4126 unsigned long time_left;
4127 unsigned int cur;
4128
4129 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond);
4130 if (cur != RTW89_WAIT_COND_IDLE)
4131 return -EBUSY;
4132
4133 time_left = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT);
4134 if (time_left == 0) {
4135 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
4136 return -ETIMEDOUT;
4137 }
4138
4139 if (wait->data.err)
4140 return -EFAULT;
4141
4142 return 0;
4143 }
4144
rtw89_complete_cond(struct rtw89_wait_info * wait,unsigned int cond,const struct rtw89_completion_data * data)4145 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
4146 const struct rtw89_completion_data *data)
4147 {
4148 unsigned int cur;
4149
4150 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE);
4151 if (cur != cond)
4152 return;
4153
4154 wait->data = *data;
4155 complete(&wait->completion);
4156 }
4157
rtw89_core_ntfy_btc_event(struct rtw89_dev * rtwdev,enum rtw89_btc_hmsg event)4158 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event)
4159 {
4160 u16 bt_req_len;
4161
4162 switch (event) {
4163 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT:
4164 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0);
4165 rtw89_debug(rtwdev, RTW89_DBG_BTC,
4166 "coex updates BT req len to %d TU\n", bt_req_len);
4167 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE);
4168 break;
4169 default:
4170 if (event < NUM_OF_RTW89_BTC_HMSG)
4171 rtw89_debug(rtwdev, RTW89_DBG_BTC,
4172 "unhandled BTC HMSG event: %d\n", event);
4173 else
4174 rtw89_warn(rtwdev,
4175 "unrecognized BTC HMSG event: %d\n", event);
4176 break;
4177 }
4178 }
4179
rtw89_check_quirks(struct rtw89_dev * rtwdev,const struct dmi_system_id * quirks)4180 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks)
4181 {
4182 const struct dmi_system_id *match;
4183 enum rtw89_quirks quirk;
4184
4185 if (!quirks)
4186 return;
4187
4188 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) {
4189 quirk = (uintptr_t)match->driver_data;
4190 if (quirk >= NUM_OF_RTW89_QUIRKS)
4191 continue;
4192
4193 set_bit(quirk, rtwdev->quirks);
4194 }
4195 }
4196 EXPORT_SYMBOL(rtw89_check_quirks);
4197
rtw89_core_start(struct rtw89_dev * rtwdev)4198 int rtw89_core_start(struct rtw89_dev *rtwdev)
4199 {
4200 int ret;
4201
4202 ret = rtw89_mac_init(rtwdev);
4203 if (ret) {
4204 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret);
4205 return ret;
4206 }
4207
4208 rtw89_btc_ntfy_poweron(rtwdev);
4209
4210 /* efuse process */
4211
4212 /* pre-config BB/RF, BB reset/RFC reset */
4213 ret = rtw89_chip_reset_bb_rf(rtwdev);
4214 if (ret)
4215 return ret;
4216
4217 rtw89_phy_init_bb_reg(rtwdev);
4218 rtw89_chip_bb_postinit(rtwdev);
4219 rtw89_phy_init_rf_reg(rtwdev, false);
4220
4221 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL);
4222
4223 rtw89_phy_dm_init(rtwdev);
4224
4225 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
4226 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0);
4227
4228 rtw89_tas_reset(rtwdev);
4229
4230 ret = rtw89_hci_start(rtwdev);
4231 if (ret) {
4232 rtw89_err(rtwdev, "failed to start hci\n");
4233 return ret;
4234 }
4235
4236 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
4237 RTW89_TRACK_WORK_PERIOD);
4238
4239 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
4240
4241 rtw89_chip_rfk_init_late(rtwdev);
4242 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON);
4243 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable);
4244 rtw89_fw_h2c_init_ba_cam(rtwdev);
4245
4246 return 0;
4247 }
4248
rtw89_core_stop(struct rtw89_dev * rtwdev)4249 void rtw89_core_stop(struct rtw89_dev *rtwdev)
4250 {
4251 struct rtw89_btc *btc = &rtwdev->btc;
4252
4253 /* Prvent to stop twice; enter_ips and ops_stop */
4254 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
4255 return;
4256
4257 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF);
4258
4259 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
4260
4261 mutex_unlock(&rtwdev->mutex);
4262
4263 cancel_work_sync(&rtwdev->c2h_work);
4264 cancel_work_sync(&rtwdev->cancel_6ghz_probe_work);
4265 cancel_work_sync(&btc->eapol_notify_work);
4266 cancel_work_sync(&btc->arp_notify_work);
4267 cancel_work_sync(&btc->dhcp_notify_work);
4268 cancel_work_sync(&btc->icmp_notify_work);
4269 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work);
4270 cancel_delayed_work_sync(&rtwdev->track_work);
4271 cancel_delayed_work_sync(&rtwdev->chanctx_work);
4272 cancel_delayed_work_sync(&rtwdev->coex_act1_work);
4273 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work);
4274 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work);
4275 cancel_delayed_work_sync(&rtwdev->cfo_track_work);
4276 cancel_delayed_work_sync(&rtwdev->forbid_ba_work);
4277 cancel_delayed_work_sync(&rtwdev->antdiv_work);
4278
4279 mutex_lock(&rtwdev->mutex);
4280
4281 rtw89_btc_ntfy_poweroff(rtwdev);
4282 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
4283 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
4284 rtw89_hci_stop(rtwdev);
4285 rtw89_hci_deinit(rtwdev);
4286 rtw89_mac_pwr_off(rtwdev);
4287 rtw89_hci_reset(rtwdev);
4288 }
4289
rtw89_acquire_mac_id(struct rtw89_dev * rtwdev)4290 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev)
4291 {
4292 const struct rtw89_chip_info *chip = rtwdev->chip;
4293 u8 mac_id_num = chip->support_macid_num;
4294 u8 mac_id;
4295
4296 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num);
4297 if (mac_id == mac_id_num)
4298 return RTW89_MAX_MAC_ID_NUM;
4299
4300 set_bit(mac_id, rtwdev->mac_id_map);
4301 return mac_id;
4302 }
4303
rtw89_release_mac_id(struct rtw89_dev * rtwdev,u8 mac_id)4304 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id)
4305 {
4306 clear_bit(mac_id, rtwdev->mac_id_map);
4307 }
4308
rtw89_core_init(struct rtw89_dev * rtwdev)4309 int rtw89_core_init(struct rtw89_dev *rtwdev)
4310 {
4311 struct rtw89_btc *btc = &rtwdev->btc;
4312 u8 band;
4313
4314 INIT_LIST_HEAD(&rtwdev->ba_list);
4315 INIT_LIST_HEAD(&rtwdev->forbid_ba_list);
4316 INIT_LIST_HEAD(&rtwdev->rtwvifs_list);
4317 INIT_LIST_HEAD(&rtwdev->early_h2c_list);
4318 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) {
4319 if (!(rtwdev->chip->support_bands & BIT(band)))
4320 continue;
4321 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]);
4322 }
4323 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work);
4324 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work);
4325 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work);
4326 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work);
4327 INIT_DELAYED_WORK(&rtwdev->chanctx_work, rtw89_chanctx_work);
4328 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work);
4329 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work);
4330 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work);
4331 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work);
4332 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work);
4333 INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work);
4334 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
4335 if (!rtwdev->txq_wq)
4336 return -ENOMEM;
4337 spin_lock_init(&rtwdev->ba_lock);
4338 spin_lock_init(&rtwdev->rpwm_lock);
4339 mutex_init(&rtwdev->mutex);
4340 mutex_init(&rtwdev->rf_mutex);
4341 rtwdev->total_sta_assoc = 0;
4342
4343 rtw89_init_wait(&rtwdev->mcc.wait);
4344 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait);
4345
4346 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work);
4347 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work);
4348 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work);
4349 INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work);
4350
4351 skb_queue_head_init(&rtwdev->c2h_queue);
4352 rtw89_core_ppdu_sts_init(rtwdev);
4353 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats);
4354
4355 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR;
4356 rtwdev->dbcc_en = false;
4357 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT;
4358 rtwdev->mac.qta_mode = RTW89_QTA_SCC;
4359
4360 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
4361 rtwdev->dbcc_en = true;
4362 rtwdev->mac.qta_mode = RTW89_QTA_DBCC;
4363 rtwdev->mlo_dbcc_mode = MLO_2_PLUS_0_1RF;
4364 }
4365
4366 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work);
4367 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work);
4368 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work);
4369 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work);
4370
4371 init_completion(&rtwdev->fw.req.completion);
4372 init_completion(&rtwdev->rfk_wait.completion);
4373
4374 schedule_work(&rtwdev->load_firmware_work);
4375
4376 rtw89_ser_init(rtwdev);
4377 rtw89_entity_init(rtwdev);
4378 rtw89_tas_init(rtwdev);
4379
4380 return 0;
4381 }
4382 EXPORT_SYMBOL(rtw89_core_init);
4383
rtw89_core_deinit(struct rtw89_dev * rtwdev)4384 void rtw89_core_deinit(struct rtw89_dev *rtwdev)
4385 {
4386 rtw89_ser_deinit(rtwdev);
4387 rtw89_unload_firmware(rtwdev);
4388 rtw89_fw_free_all_early_h2c(rtwdev);
4389
4390 destroy_workqueue(rtwdev->txq_wq);
4391 mutex_destroy(&rtwdev->rf_mutex);
4392 mutex_destroy(&rtwdev->mutex);
4393 }
4394 EXPORT_SYMBOL(rtw89_core_deinit);
4395
rtw89_core_scan_start(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,const u8 * mac_addr,bool hw_scan)4396 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4397 const u8 *mac_addr, bool hw_scan)
4398 {
4399 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
4400 rtwvif->sub_entity_idx);
4401
4402 rtwdev->scanning = true;
4403 rtw89_leave_lps(rtwdev);
4404 if (hw_scan)
4405 rtw89_leave_ips_by_hwflags(rtwdev);
4406
4407 ether_addr_copy(rtwvif->mac_addr, mac_addr);
4408 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type);
4409 rtw89_chip_rfk_scan(rtwdev, true);
4410 rtw89_hci_recalc_int_mit(rtwdev);
4411 rtw89_phy_config_edcca(rtwdev, true);
4412
4413 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr);
4414 }
4415
rtw89_core_scan_complete(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,bool hw_scan)4416 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
4417 struct ieee80211_vif *vif, bool hw_scan)
4418 {
4419 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL;
4420
4421 if (!rtwvif)
4422 return;
4423
4424 ether_addr_copy(rtwvif->mac_addr, vif->addr);
4425 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL);
4426
4427 rtw89_chip_rfk_scan(rtwdev, false);
4428 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0);
4429 rtw89_phy_config_edcca(rtwdev, false);
4430
4431 rtwdev->scanning = false;
4432 rtwdev->dig.bypass_dig = true;
4433 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
4434 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
4435 }
4436
rtw89_read_chip_ver(struct rtw89_dev * rtwdev)4437 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
4438 {
4439 const struct rtw89_chip_info *chip = rtwdev->chip;
4440 int ret;
4441 u8 val;
4442 u8 cv;
4443
4444 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK);
4445 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) {
4446 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD)
4447 cv = CHIP_CAV;
4448 else
4449 cv = CHIP_CBV;
4450 }
4451
4452 rtwdev->hal.cv = cv;
4453
4454 if (rtw89_is_rtl885xb(rtwdev)) {
4455 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val);
4456 if (ret)
4457 return;
4458
4459 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK);
4460 }
4461 }
4462
rtw89_core_setup_phycap(struct rtw89_dev * rtwdev)4463 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev)
4464 {
4465 rtwdev->hal.support_cckpd =
4466 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) &&
4467 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV);
4468 rtwdev->hal.support_igi =
4469 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV;
4470 }
4471
rtw89_core_setup_rfe_parms(struct rtw89_dev * rtwdev)4472 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev)
4473 {
4474 const struct rtw89_chip_info *chip = rtwdev->chip;
4475 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf;
4476 struct rtw89_efuse *efuse = &rtwdev->efuse;
4477 const struct rtw89_rfe_parms *sel;
4478 u8 rfe_type = efuse->rfe_type;
4479
4480 if (!conf) {
4481 sel = chip->dflt_parms;
4482 goto out;
4483 }
4484
4485 while (conf->rfe_parms) {
4486 if (rfe_type == conf->rfe_type) {
4487 sel = conf->rfe_parms;
4488 goto out;
4489 }
4490 conf++;
4491 }
4492
4493 sel = chip->dflt_parms;
4494
4495 out:
4496 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel);
4497 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl);
4498 }
4499
rtw89_chip_efuse_info_setup(struct rtw89_dev * rtwdev)4500 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev)
4501 {
4502 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4503 int ret;
4504
4505 ret = rtw89_mac_partial_init(rtwdev, false);
4506 if (ret)
4507 return ret;
4508
4509 ret = mac->parse_efuse_map(rtwdev);
4510 if (ret)
4511 return ret;
4512
4513 ret = mac->parse_phycap_map(rtwdev);
4514 if (ret)
4515 return ret;
4516
4517 ret = rtw89_mac_setup_phycap(rtwdev);
4518 if (ret)
4519 return ret;
4520
4521 rtw89_core_setup_phycap(rtwdev);
4522
4523 rtw89_hci_mac_pre_deinit(rtwdev);
4524
4525 rtw89_mac_pwr_off(rtwdev);
4526
4527 return 0;
4528 }
4529
rtw89_chip_board_info_setup(struct rtw89_dev * rtwdev)4530 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev)
4531 {
4532 rtw89_chip_fem_setup(rtwdev);
4533
4534 return 0;
4535 }
4536
rtw89_chip_info_setup(struct rtw89_dev * rtwdev)4537 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev)
4538 {
4539 int ret;
4540
4541 rtw89_read_chip_ver(rtwdev);
4542
4543 ret = rtw89_wait_firmware_completion(rtwdev);
4544 if (ret) {
4545 rtw89_err(rtwdev, "failed to wait firmware completion\n");
4546 return ret;
4547 }
4548
4549 ret = rtw89_fw_recognize(rtwdev);
4550 if (ret) {
4551 rtw89_err(rtwdev, "failed to recognize firmware\n");
4552 return ret;
4553 }
4554
4555 ret = rtw89_chip_efuse_info_setup(rtwdev);
4556 if (ret)
4557 return ret;
4558
4559 ret = rtw89_fw_recognize_elements(rtwdev);
4560 if (ret) {
4561 rtw89_err(rtwdev, "failed to recognize firmware elements\n");
4562 return ret;
4563 }
4564
4565 ret = rtw89_chip_board_info_setup(rtwdev);
4566 if (ret)
4567 return ret;
4568
4569 rtw89_core_setup_rfe_parms(rtwdev);
4570 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev);
4571
4572 return 0;
4573 }
4574 EXPORT_SYMBOL(rtw89_chip_info_setup);
4575
rtw89_core_register_hw(struct rtw89_dev * rtwdev)4576 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev)
4577 {
4578 const struct rtw89_chip_info *chip = rtwdev->chip;
4579 struct ieee80211_hw *hw = rtwdev->hw;
4580 struct rtw89_efuse *efuse = &rtwdev->efuse;
4581 struct rtw89_hal *hal = &rtwdev->hal;
4582 int ret;
4583 int tx_headroom = IEEE80211_HT_CTL_LEN;
4584
4585 hw->vif_data_size = sizeof(struct rtw89_vif);
4586 hw->sta_data_size = sizeof(struct rtw89_sta);
4587 hw->txq_data_size = sizeof(struct rtw89_txq);
4588 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg);
4589
4590 SET_IEEE80211_PERM_ADDR(hw, efuse->addr);
4591
4592 hw->extra_tx_headroom = tx_headroom;
4593 hw->queues = IEEE80211_NUM_ACS;
4594 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM;
4595 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM;
4596 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL;
4597
4598 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC |
4599 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
4600 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC;
4601
4602 ieee80211_hw_set(hw, SIGNAL_DBM);
4603 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
4604 ieee80211_hw_set(hw, MFP_CAPABLE);
4605 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
4606 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
4607 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
4608 ieee80211_hw_set(hw, TX_AMSDU);
4609 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
4610 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
4611 ieee80211_hw_set(hw, SUPPORTS_PS);
4612 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
4613 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
4614 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
4615 ieee80211_hw_set(hw, WANT_MONITOR_VIF);
4616
4617 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
4618 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
4619
4620 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw))
4621 ieee80211_hw_set(hw, CONNECTION_MONITOR);
4622
4623 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
4624 BIT(NL80211_IFTYPE_AP) |
4625 BIT(NL80211_IFTYPE_P2P_CLIENT) |
4626 BIT(NL80211_IFTYPE_P2P_GO);
4627
4628 if (hal->ant_diversity) {
4629 hw->wiphy->available_antennas_tx = 0x3;
4630 hw->wiphy->available_antennas_rx = 0x3;
4631 } else {
4632 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1;
4633 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1;
4634 }
4635
4636 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
4637 WIPHY_FLAG_TDLS_EXTERNAL_SETUP |
4638 WIPHY_FLAG_AP_UAPSD |
4639 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK;
4640
4641 if (!chip->support_rnr)
4642 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ;
4643
4644 if (chip->chip_gen == RTW89_CHIP_BE)
4645 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT;
4646
4647 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
4648
4649 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
4650 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN;
4651
4652 #ifdef CONFIG_PM
4653 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
4654 #endif
4655
4656 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
4657 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
4658 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
4659 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
4660 hw->wiphy->max_remain_on_channel_duration = 1000;
4661
4662 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
4663 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
4664 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
4665
4666 ret = rtw89_core_set_supported_band(rtwdev);
4667 if (ret) {
4668 rtw89_err(rtwdev, "failed to set supported band\n");
4669 return ret;
4670 }
4671
4672 ret = rtw89_regd_setup(rtwdev);
4673 if (ret) {
4674 rtw89_err(rtwdev, "failed to set up regd\n");
4675 goto err_free_supported_band;
4676 }
4677
4678 hw->wiphy->sar_capa = &rtw89_sar_capa;
4679
4680 ret = ieee80211_register_hw(hw);
4681 if (ret) {
4682 rtw89_err(rtwdev, "failed to register hw\n");
4683 goto err_free_supported_band;
4684 }
4685
4686 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier);
4687 if (ret) {
4688 rtw89_err(rtwdev, "failed to init regd\n");
4689 goto err_unregister_hw;
4690 }
4691
4692 return 0;
4693
4694 err_unregister_hw:
4695 ieee80211_unregister_hw(hw);
4696 err_free_supported_band:
4697 rtw89_core_clr_supported_band(rtwdev);
4698
4699 return ret;
4700 }
4701
rtw89_core_unregister_hw(struct rtw89_dev * rtwdev)4702 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev)
4703 {
4704 struct ieee80211_hw *hw = rtwdev->hw;
4705
4706 ieee80211_unregister_hw(hw);
4707 rtw89_core_clr_supported_band(rtwdev);
4708 }
4709
rtw89_core_register(struct rtw89_dev * rtwdev)4710 int rtw89_core_register(struct rtw89_dev *rtwdev)
4711 {
4712 int ret;
4713
4714 ret = rtw89_core_register_hw(rtwdev);
4715 if (ret) {
4716 rtw89_err(rtwdev, "failed to register core hw\n");
4717 return ret;
4718 }
4719
4720 rtw89_debugfs_init(rtwdev);
4721
4722 return 0;
4723 }
4724 EXPORT_SYMBOL(rtw89_core_register);
4725
rtw89_core_unregister(struct rtw89_dev * rtwdev)4726 void rtw89_core_unregister(struct rtw89_dev *rtwdev)
4727 {
4728 rtw89_core_unregister_hw(rtwdev);
4729 }
4730 EXPORT_SYMBOL(rtw89_core_unregister);
4731
rtw89_alloc_ieee80211_hw(struct device * device,u32 bus_data_size,const struct rtw89_chip_info * chip)4732 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
4733 u32 bus_data_size,
4734 const struct rtw89_chip_info *chip)
4735 {
4736 struct rtw89_fw_info early_fw = {};
4737 const struct firmware *firmware;
4738 struct ieee80211_hw *hw;
4739 struct rtw89_dev *rtwdev;
4740 struct ieee80211_ops *ops;
4741 u32 driver_data_size;
4742 int fw_format = -1;
4743 bool no_chanctx;
4744
4745 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format);
4746
4747 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL);
4748 if (!ops)
4749 goto err;
4750
4751 no_chanctx = chip->support_chanctx_num == 0 ||
4752 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) ||
4753 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw);
4754
4755 if (no_chanctx) {
4756 ops->add_chanctx = ieee80211_emulate_add_chanctx;
4757 ops->remove_chanctx = ieee80211_emulate_remove_chanctx;
4758 ops->change_chanctx = ieee80211_emulate_change_chanctx;
4759 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx;
4760 ops->assign_vif_chanctx = NULL;
4761 ops->unassign_vif_chanctx = NULL;
4762 ops->remain_on_channel = NULL;
4763 ops->cancel_remain_on_channel = NULL;
4764 }
4765
4766 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size;
4767 hw = ieee80211_alloc_hw(driver_data_size, ops);
4768 if (!hw)
4769 goto err;
4770
4771 hw->wiphy->iface_combinations = rtw89_iface_combs;
4772
4773 if (no_chanctx || chip->support_chanctx_num == 1)
4774 hw->wiphy->n_iface_combinations = 1;
4775 else
4776 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs);
4777
4778 rtwdev = hw->priv;
4779 rtwdev->hw = hw;
4780 rtwdev->dev = device;
4781 rtwdev->ops = ops;
4782 rtwdev->chip = chip;
4783 rtwdev->fw.req.firmware = firmware;
4784 rtwdev->fw.fw_format = fw_format;
4785
4786 rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n",
4787 no_chanctx ? "without" : "with");
4788
4789 return rtwdev;
4790
4791 err:
4792 kfree(ops);
4793 release_firmware(firmware);
4794 return NULL;
4795 }
4796 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw);
4797
rtw89_free_ieee80211_hw(struct rtw89_dev * rtwdev)4798 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev)
4799 {
4800 kfree(rtwdev->ops);
4801 kfree(rtwdev->rfe_data);
4802 release_firmware(rtwdev->fw.req.firmware);
4803 ieee80211_free_hw(rtwdev->hw);
4804 }
4805 EXPORT_SYMBOL(rtw89_free_ieee80211_hw);
4806
4807 MODULE_AUTHOR("Realtek Corporation");
4808 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module");
4809 MODULE_LICENSE("Dual BSD/GPL");
4810