1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 #if defined(__FreeBSD__) 16 #include <linux/seq_file.h> 17 #include <linux/lockdep.h> 18 #include <linux/interrupt.h> 19 #include <linux/pm.h> 20 #endif 21 22 struct rtw89_dev; 23 struct rtw89_pci_info; 24 struct rtw89_mac_gen_def; 25 struct rtw89_phy_gen_def; 26 struct rtw89_efuse_block_cfg; 27 struct rtw89_h2c_rf_tssi; 28 struct rtw89_fw_txpwr_track_cfg; 29 struct rtw89_phy_rfk_log_fmt; 30 struct rtw89_debugfs; 31 32 extern const struct ieee80211_ops rtw89_ops; 33 34 #define MASKBYTE0 0xff 35 #define MASKBYTE1 0xff00 36 #define MASKBYTE2 0xff0000 37 #define MASKBYTE3 0xff000000 38 #define MASKBYTE4 0xff00000000ULL 39 #define MASKHWORD 0xffff0000 40 #define MASKLWORD 0x0000ffff 41 #define MASKDWORD 0xffffffff 42 #define RFREG_MASK 0xfffff 43 #define INV_RF_DATA 0xffffffff 44 #define BYPASS_CR_DATA 0xbabecafe 45 46 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 47 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 48 #define CFO_TRACK_MAX_USER 64 49 #define MAX_RSSI 110 50 #define RSSI_FACTOR 1 51 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 52 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 53 #define DELTA_SWINGIDX_SIZE 30 54 55 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 56 #define RTW89_RADIOTAP_ROOM_EHT \ 57 (sizeof(struct ieee80211_radiotap_tlv) + \ 58 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 59 sizeof(struct ieee80211_radiotap_tlv) + \ 60 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 61 #define RTW89_RADIOTAP_ROOM \ 62 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 63 64 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 65 #define RTW89_HTC_VARIANT_HE 3 66 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 67 #define RTW89_HTC_VARIANT_HE_CID_OM 1 68 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 69 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 70 71 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 72 enum htc_om_channel_width { 73 HTC_OM_CHANNEL_WIDTH_20 = 0, 74 HTC_OM_CHANNEL_WIDTH_40 = 1, 75 HTC_OM_CHANNEL_WIDTH_80 = 2, 76 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 77 }; 78 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 79 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 80 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 81 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 82 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 83 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 84 85 #define RTW89_TF_PAD GENMASK(11, 0) 86 #define RTW89_TF_BASIC_USER_INFO_SZ 6 87 88 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 89 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 90 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 91 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 92 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 93 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 94 95 enum rtw89_subband { 96 RTW89_CH_2G = 0, 97 RTW89_CH_5G_BAND_1 = 1, 98 /* RTW89_CH_5G_BAND_2 = 2, unused */ 99 RTW89_CH_5G_BAND_3 = 3, 100 RTW89_CH_5G_BAND_4 = 4, 101 102 RTW89_CH_6G_BAND_IDX0, /* Low */ 103 RTW89_CH_6G_BAND_IDX1, /* Low */ 104 RTW89_CH_6G_BAND_IDX2, /* Mid */ 105 RTW89_CH_6G_BAND_IDX3, /* Mid */ 106 RTW89_CH_6G_BAND_IDX4, /* High */ 107 RTW89_CH_6G_BAND_IDX5, /* High */ 108 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 109 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 110 111 RTW89_SUBBAND_NR, 112 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 113 }; 114 115 enum rtw89_gain_offset { 116 RTW89_GAIN_OFFSET_2G_CCK, 117 RTW89_GAIN_OFFSET_2G_OFDM, 118 RTW89_GAIN_OFFSET_5G_LOW, 119 RTW89_GAIN_OFFSET_5G_MID, 120 RTW89_GAIN_OFFSET_5G_HIGH, 121 RTW89_GAIN_OFFSET_6G_L0, 122 RTW89_GAIN_OFFSET_6G_L1, 123 RTW89_GAIN_OFFSET_6G_M0, 124 RTW89_GAIN_OFFSET_6G_M1, 125 RTW89_GAIN_OFFSET_6G_H0, 126 RTW89_GAIN_OFFSET_6G_H1, 127 RTW89_GAIN_OFFSET_6G_UH0, 128 RTW89_GAIN_OFFSET_6G_UH1, 129 130 RTW89_GAIN_OFFSET_NR, 131 }; 132 133 enum rtw89_hci_type { 134 RTW89_HCI_TYPE_PCIE, 135 RTW89_HCI_TYPE_USB, 136 RTW89_HCI_TYPE_SDIO, 137 }; 138 139 enum rtw89_core_chip_id { 140 RTL8852A, 141 RTL8852B, 142 RTL8852BT, 143 RTL8852C, 144 RTL8851B, 145 RTL8922A, 146 }; 147 148 enum rtw89_chip_gen { 149 RTW89_CHIP_AX, 150 RTW89_CHIP_BE, 151 152 RTW89_CHIP_GEN_NUM, 153 }; 154 155 enum rtw89_cv { 156 CHIP_CAV, 157 CHIP_CBV, 158 CHIP_CCV, 159 CHIP_CDV, 160 CHIP_CEV, 161 CHIP_CFV, 162 CHIP_CV_MAX, 163 CHIP_CV_INVALID = CHIP_CV_MAX, 164 }; 165 166 enum rtw89_bacam_ver { 167 RTW89_BACAM_V0, 168 RTW89_BACAM_V1, 169 170 RTW89_BACAM_V0_EXT = 99, 171 }; 172 173 enum rtw89_core_tx_type { 174 RTW89_CORE_TX_TYPE_DATA, 175 RTW89_CORE_TX_TYPE_MGMT, 176 RTW89_CORE_TX_TYPE_FWCMD, 177 }; 178 179 enum rtw89_core_rx_type { 180 RTW89_CORE_RX_TYPE_WIFI = 0, 181 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 182 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 183 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 184 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 185 RTW89_CORE_RX_TYPE_SS2FW = 5, 186 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 187 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 188 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 189 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 190 RTW89_CORE_RX_TYPE_C2H = 10, 191 RTW89_CORE_RX_TYPE_CSI = 11, 192 RTW89_CORE_RX_TYPE_CQI = 12, 193 RTW89_CORE_RX_TYPE_H2C = 13, 194 RTW89_CORE_RX_TYPE_FWDL = 14, 195 }; 196 197 enum rtw89_txq_flags { 198 RTW89_TXQ_F_AMPDU = 0, 199 RTW89_TXQ_F_BLOCK_BA = 1, 200 RTW89_TXQ_F_FORBID_BA = 2, 201 }; 202 203 enum rtw89_net_type { 204 RTW89_NET_TYPE_NO_LINK = 0, 205 RTW89_NET_TYPE_AD_HOC = 1, 206 RTW89_NET_TYPE_INFRA = 2, 207 RTW89_NET_TYPE_AP_MODE = 3, 208 }; 209 210 enum rtw89_wifi_role { 211 RTW89_WIFI_ROLE_NONE, 212 RTW89_WIFI_ROLE_STATION, 213 RTW89_WIFI_ROLE_AP, 214 RTW89_WIFI_ROLE_AP_VLAN, 215 RTW89_WIFI_ROLE_ADHOC, 216 RTW89_WIFI_ROLE_ADHOC_MASTER, 217 RTW89_WIFI_ROLE_MESH_POINT, 218 RTW89_WIFI_ROLE_MONITOR, 219 RTW89_WIFI_ROLE_P2P_DEVICE, 220 RTW89_WIFI_ROLE_P2P_CLIENT, 221 RTW89_WIFI_ROLE_P2P_GO, 222 RTW89_WIFI_ROLE_NAN, 223 RTW89_WIFI_ROLE_MLME_MAX 224 }; 225 226 enum rtw89_upd_mode { 227 RTW89_ROLE_CREATE, 228 RTW89_ROLE_REMOVE, 229 RTW89_ROLE_TYPE_CHANGE, 230 RTW89_ROLE_INFO_CHANGE, 231 RTW89_ROLE_CON_DISCONN, 232 RTW89_ROLE_BAND_SW, 233 RTW89_ROLE_FW_RESTORE, 234 }; 235 236 enum rtw89_self_role { 237 RTW89_SELF_ROLE_CLIENT, 238 RTW89_SELF_ROLE_AP, 239 RTW89_SELF_ROLE_AP_CLIENT 240 }; 241 242 enum rtw89_msk_sO_el { 243 RTW89_NO_MSK, 244 RTW89_SMA, 245 RTW89_TMA, 246 RTW89_BSSID 247 }; 248 249 enum rtw89_sch_tx_sel { 250 RTW89_SCH_TX_SEL_ALL, 251 RTW89_SCH_TX_SEL_HIQ, 252 RTW89_SCH_TX_SEL_MG0, 253 RTW89_SCH_TX_SEL_MACID, 254 }; 255 256 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 257 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 258 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 259 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 260 */ 261 enum rtw89_add_cam_sec_mode { 262 RTW89_ADDR_CAM_SEC_NONE = 0, 263 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 264 RTW89_ADDR_CAM_SEC_NORMAL = 2, 265 RTW89_ADDR_CAM_SEC_4GROUP = 3, 266 }; 267 268 enum rtw89_sec_key_type { 269 RTW89_SEC_KEY_TYPE_NONE = 0, 270 RTW89_SEC_KEY_TYPE_WEP40 = 1, 271 RTW89_SEC_KEY_TYPE_WEP104 = 2, 272 RTW89_SEC_KEY_TYPE_TKIP = 3, 273 RTW89_SEC_KEY_TYPE_WAPI = 4, 274 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 275 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 276 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 277 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 278 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 279 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 280 }; 281 282 enum rtw89_port { 283 RTW89_PORT_0 = 0, 284 RTW89_PORT_1 = 1, 285 RTW89_PORT_2 = 2, 286 RTW89_PORT_3 = 3, 287 RTW89_PORT_4 = 4, 288 RTW89_PORT_NUM 289 }; 290 291 enum rtw89_band { 292 RTW89_BAND_2G = 0, 293 RTW89_BAND_5G = 1, 294 RTW89_BAND_6G = 2, 295 RTW89_BAND_NUM, 296 }; 297 298 enum rtw89_hw_rate { 299 RTW89_HW_RATE_CCK1 = 0x0, 300 RTW89_HW_RATE_CCK2 = 0x1, 301 RTW89_HW_RATE_CCK5_5 = 0x2, 302 RTW89_HW_RATE_CCK11 = 0x3, 303 RTW89_HW_RATE_OFDM6 = 0x4, 304 RTW89_HW_RATE_OFDM9 = 0x5, 305 RTW89_HW_RATE_OFDM12 = 0x6, 306 RTW89_HW_RATE_OFDM18 = 0x7, 307 RTW89_HW_RATE_OFDM24 = 0x8, 308 RTW89_HW_RATE_OFDM36 = 0x9, 309 RTW89_HW_RATE_OFDM48 = 0xA, 310 RTW89_HW_RATE_OFDM54 = 0xB, 311 RTW89_HW_RATE_MCS0 = 0x80, 312 RTW89_HW_RATE_MCS1 = 0x81, 313 RTW89_HW_RATE_MCS2 = 0x82, 314 RTW89_HW_RATE_MCS3 = 0x83, 315 RTW89_HW_RATE_MCS4 = 0x84, 316 RTW89_HW_RATE_MCS5 = 0x85, 317 RTW89_HW_RATE_MCS6 = 0x86, 318 RTW89_HW_RATE_MCS7 = 0x87, 319 RTW89_HW_RATE_MCS8 = 0x88, 320 RTW89_HW_RATE_MCS9 = 0x89, 321 RTW89_HW_RATE_MCS10 = 0x8A, 322 RTW89_HW_RATE_MCS11 = 0x8B, 323 RTW89_HW_RATE_MCS12 = 0x8C, 324 RTW89_HW_RATE_MCS13 = 0x8D, 325 RTW89_HW_RATE_MCS14 = 0x8E, 326 RTW89_HW_RATE_MCS15 = 0x8F, 327 RTW89_HW_RATE_MCS16 = 0x90, 328 RTW89_HW_RATE_MCS17 = 0x91, 329 RTW89_HW_RATE_MCS18 = 0x92, 330 RTW89_HW_RATE_MCS19 = 0x93, 331 RTW89_HW_RATE_MCS20 = 0x94, 332 RTW89_HW_RATE_MCS21 = 0x95, 333 RTW89_HW_RATE_MCS22 = 0x96, 334 RTW89_HW_RATE_MCS23 = 0x97, 335 RTW89_HW_RATE_MCS24 = 0x98, 336 RTW89_HW_RATE_MCS25 = 0x99, 337 RTW89_HW_RATE_MCS26 = 0x9A, 338 RTW89_HW_RATE_MCS27 = 0x9B, 339 RTW89_HW_RATE_MCS28 = 0x9C, 340 RTW89_HW_RATE_MCS29 = 0x9D, 341 RTW89_HW_RATE_MCS30 = 0x9E, 342 RTW89_HW_RATE_MCS31 = 0x9F, 343 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 344 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 345 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 346 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 347 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 348 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 349 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 350 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 351 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 352 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 353 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 354 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 355 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 356 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 357 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 358 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 359 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 360 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 361 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 362 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 363 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 364 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 365 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 366 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 367 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 368 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 369 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 370 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 371 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 372 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 373 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 374 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 375 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 376 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 377 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 378 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 379 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 380 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 381 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 382 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 383 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 384 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 385 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 386 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 387 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 388 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 389 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 390 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 391 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 392 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 393 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 394 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 395 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 396 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 397 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 398 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 399 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 400 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 401 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 402 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 403 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 404 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 405 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 406 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 407 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 408 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 409 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 410 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 411 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 412 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 413 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 414 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 415 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 416 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 417 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 418 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 419 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 420 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 421 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 422 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 423 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 424 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 425 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 426 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 427 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 428 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 429 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 430 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 431 432 RTW89_HW_RATE_V1_MCS0 = 0x100, 433 RTW89_HW_RATE_V1_MCS1 = 0x101, 434 RTW89_HW_RATE_V1_MCS2 = 0x102, 435 RTW89_HW_RATE_V1_MCS3 = 0x103, 436 RTW89_HW_RATE_V1_MCS4 = 0x104, 437 RTW89_HW_RATE_V1_MCS5 = 0x105, 438 RTW89_HW_RATE_V1_MCS6 = 0x106, 439 RTW89_HW_RATE_V1_MCS7 = 0x107, 440 RTW89_HW_RATE_V1_MCS8 = 0x108, 441 RTW89_HW_RATE_V1_MCS9 = 0x109, 442 RTW89_HW_RATE_V1_MCS10 = 0x10A, 443 RTW89_HW_RATE_V1_MCS11 = 0x10B, 444 RTW89_HW_RATE_V1_MCS12 = 0x10C, 445 RTW89_HW_RATE_V1_MCS13 = 0x10D, 446 RTW89_HW_RATE_V1_MCS14 = 0x10E, 447 RTW89_HW_RATE_V1_MCS15 = 0x10F, 448 RTW89_HW_RATE_V1_MCS16 = 0x110, 449 RTW89_HW_RATE_V1_MCS17 = 0x111, 450 RTW89_HW_RATE_V1_MCS18 = 0x112, 451 RTW89_HW_RATE_V1_MCS19 = 0x113, 452 RTW89_HW_RATE_V1_MCS20 = 0x114, 453 RTW89_HW_RATE_V1_MCS21 = 0x115, 454 RTW89_HW_RATE_V1_MCS22 = 0x116, 455 RTW89_HW_RATE_V1_MCS23 = 0x117, 456 RTW89_HW_RATE_V1_MCS24 = 0x118, 457 RTW89_HW_RATE_V1_MCS25 = 0x119, 458 RTW89_HW_RATE_V1_MCS26 = 0x11A, 459 RTW89_HW_RATE_V1_MCS27 = 0x11B, 460 RTW89_HW_RATE_V1_MCS28 = 0x11C, 461 RTW89_HW_RATE_V1_MCS29 = 0x11D, 462 RTW89_HW_RATE_V1_MCS30 = 0x11E, 463 RTW89_HW_RATE_V1_MCS31 = 0x11F, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 467 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 468 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 469 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 470 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 471 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 472 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 473 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 474 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 475 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 479 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 480 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 481 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 482 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 483 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 484 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 485 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 486 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 487 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 491 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 492 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 493 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 494 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 495 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 496 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 497 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 498 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 499 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 503 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 504 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 505 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 506 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 507 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 508 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 509 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 510 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 511 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 515 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 516 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 517 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 518 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 519 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 520 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 521 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 522 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 523 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 527 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 528 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 529 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 530 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 531 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 532 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 533 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 534 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 535 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 539 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 540 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 541 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 542 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 543 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 544 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 545 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 546 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 547 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 551 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 552 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 553 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 554 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 555 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 556 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 557 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 558 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 559 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 567 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 568 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 569 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 570 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 571 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 572 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 573 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 574 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 575 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 581 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 582 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 583 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 584 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 585 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 586 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 587 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 588 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 589 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 595 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 596 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 597 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 598 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 599 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 600 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 601 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 602 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 603 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 609 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 610 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 611 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 612 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 613 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 614 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 615 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 616 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 617 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 618 619 RTW89_HW_RATE_NR, 620 RTW89_HW_RATE_INVAL, 621 622 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 623 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 624 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 625 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 626 }; 627 628 /* 2G channels, 629 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 630 */ 631 #define RTW89_2G_CH_NUM 14 632 633 /* 5G channels, 634 * 36, 38, 40, 42, 44, 46, 48, 50, 635 * 52, 54, 56, 58, 60, 62, 64, 636 * 100, 102, 104, 106, 108, 110, 112, 114, 637 * 116, 118, 120, 122, 124, 126, 128, 130, 638 * 132, 134, 136, 138, 140, 142, 144, 639 * 149, 151, 153, 155, 157, 159, 161, 163, 640 * 165, 167, 169, 171, 173, 175, 177 641 */ 642 #define RTW89_5G_CH_NUM 53 643 644 /* 6G channels, 645 * 1, 3, 5, 7, 9, 11, 13, 15, 646 * 17, 19, 21, 23, 25, 27, 29, 33, 647 * 35, 37, 39, 41, 43, 45, 47, 49, 648 * 51, 53, 55, 57, 59, 61, 65, 67, 649 * 69, 71, 73, 75, 77, 79, 81, 83, 650 * 85, 87, 89, 91, 93, 97, 99, 101, 651 * 103, 105, 107, 109, 111, 113, 115, 117, 652 * 119, 121, 123, 125, 129, 131, 133, 135, 653 * 137, 139, 141, 143, 145, 147, 149, 151, 654 * 153, 155, 157, 161, 163, 165, 167, 169, 655 * 171, 173, 175, 177, 179, 181, 183, 185, 656 * 187, 189, 193, 195, 197, 199, 201, 203, 657 * 205, 207, 209, 211, 213, 215, 217, 219, 658 * 221, 225, 227, 229, 231, 233, 235, 237, 659 * 239, 241, 243, 245, 247, 249, 251, 253, 660 */ 661 #define RTW89_6G_CH_NUM 120 662 663 enum rtw89_rate_section { 664 RTW89_RS_CCK, 665 RTW89_RS_OFDM, 666 RTW89_RS_MCS, /* for HT/VHT/HE */ 667 RTW89_RS_HEDCM, 668 RTW89_RS_OFFSET, 669 RTW89_RS_NUM, 670 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 671 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 672 }; 673 674 enum rtw89_rate_offset_indexes { 675 RTW89_RATE_OFFSET_HE, 676 RTW89_RATE_OFFSET_VHT, 677 RTW89_RATE_OFFSET_HT, 678 RTW89_RATE_OFFSET_OFDM, 679 RTW89_RATE_OFFSET_CCK, 680 RTW89_RATE_OFFSET_DLRU_EHT, 681 RTW89_RATE_OFFSET_DLRU_HE, 682 RTW89_RATE_OFFSET_EHT, 683 __RTW89_RATE_OFFSET_NUM, 684 685 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 686 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 687 }; 688 689 enum rtw89_rate_num { 690 RTW89_RATE_CCK_NUM = 4, 691 RTW89_RATE_OFDM_NUM = 8, 692 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 693 694 RTW89_RATE_MCS_NUM_AX = 12, 695 RTW89_RATE_MCS_NUM_BE = 16, 696 __RTW89_RATE_MCS_NUM = 16, 697 }; 698 699 enum rtw89_nss { 700 RTW89_NSS_1 = 0, 701 RTW89_NSS_2 = 1, 702 /* HE DCM only support 1ss and 2ss */ 703 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 704 RTW89_NSS_3 = 2, 705 RTW89_NSS_4 = 3, 706 RTW89_NSS_NUM, 707 }; 708 709 enum rtw89_ntx { 710 RTW89_1TX = 0, 711 RTW89_2TX = 1, 712 RTW89_NTX_NUM, 713 }; 714 715 enum rtw89_beamforming_type { 716 RTW89_NONBF = 0, 717 RTW89_BF = 1, 718 RTW89_BF_NUM, 719 }; 720 721 enum rtw89_ofdma_type { 722 RTW89_NON_OFDMA = 0, 723 RTW89_OFDMA = 1, 724 RTW89_OFDMA_NUM, 725 }; 726 727 enum rtw89_regulation_type { 728 RTW89_WW = 0, 729 RTW89_ETSI = 1, 730 RTW89_FCC = 2, 731 RTW89_MKK = 3, 732 RTW89_NA = 4, 733 RTW89_IC = 5, 734 RTW89_KCC = 6, 735 RTW89_ACMA = 7, 736 RTW89_NCC = 8, 737 RTW89_MEXICO = 9, 738 RTW89_CHILE = 10, 739 RTW89_UKRAINE = 11, 740 RTW89_CN = 12, 741 RTW89_QATAR = 13, 742 RTW89_UK = 14, 743 RTW89_THAILAND = 15, 744 RTW89_REGD_NUM, 745 }; 746 747 enum rtw89_reg_6ghz_power { 748 RTW89_REG_6GHZ_POWER_VLP = 0, 749 RTW89_REG_6GHZ_POWER_LPI = 1, 750 RTW89_REG_6GHZ_POWER_STD = 2, 751 752 NUM_OF_RTW89_REG_6GHZ_POWER, 753 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 754 }; 755 756 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 757 758 /* calculate based on ieee80211 Transmit Power Envelope */ 759 struct rtw89_reg_6ghz_tpe { 760 bool valid; 761 s8 constraint; /* unit: dBm */ 762 }; 763 764 enum rtw89_fw_pkt_ofld_type { 765 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 766 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 767 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 768 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 769 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 770 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 771 RTW89_PKT_OFLD_TYPE_NDP = 6, 772 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 773 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 774 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 775 RTW89_PKT_OFLD_TYPE_NUM, 776 }; 777 778 struct rtw89_txpwr_byrate { 779 s8 cck[RTW89_RATE_CCK_NUM]; 780 s8 ofdm[RTW89_RATE_OFDM_NUM]; 781 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 782 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 783 s8 offset[__RTW89_RATE_OFFSET_NUM]; 784 s8 trap; 785 }; 786 787 struct rtw89_rate_desc { 788 enum rtw89_nss nss; 789 enum rtw89_rate_section rs; 790 enum rtw89_ofdma_type ofdma; 791 u8 idx; 792 }; 793 794 #define PHY_STS_HDR_LEN 8 795 #define RF_PATH_MAX 4 796 #define RTW89_MAX_PPDU_CNT 8 797 struct rtw89_rx_phy_ppdu { 798 void *buf; 799 u32 len; 800 u8 rssi_avg; 801 u8 rssi[RF_PATH_MAX]; 802 u8 mac_id; 803 u8 chan_idx; 804 u8 ie; 805 u16 rate; 806 u8 rpl_avg; 807 u8 rpl_path[RF_PATH_MAX]; 808 u8 rpl_fd[RF_PATH_MAX]; 809 u8 bw_idx; 810 u8 rx_path_en; 811 struct { 812 bool has; 813 u8 avg_snr; 814 u8 evm_max; 815 u8 evm_min; 816 } ofdm; 817 bool has_data; 818 bool has_bcn; 819 bool ldpc; 820 bool stbc; 821 bool to_self; 822 bool valid; 823 bool hdr_2_en; 824 }; 825 826 enum rtw89_mac_idx { 827 RTW89_MAC_0 = 0, 828 RTW89_MAC_1 = 1, 829 RTW89_MAC_NUM, 830 }; 831 832 enum rtw89_phy_idx { 833 RTW89_PHY_0 = 0, 834 RTW89_PHY_1 = 1, 835 RTW89_PHY_MAX 836 }; 837 838 #define __RTW89_MLD_MAX_LINK_NUM 2 839 #define RTW89_MLD_NON_STA_LINK_NUM 1 840 841 enum rtw89_chanctx_idx { 842 RTW89_CHANCTX_0 = 0, 843 RTW89_CHANCTX_1 = 1, 844 845 NUM_OF_RTW89_CHANCTX, 846 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 847 }; 848 849 enum rtw89_rf_path { 850 RF_PATH_A = 0, 851 RF_PATH_B = 1, 852 RF_PATH_C = 2, 853 RF_PATH_D = 3, 854 RF_PATH_AB, 855 RF_PATH_AC, 856 RF_PATH_AD, 857 RF_PATH_BC, 858 RF_PATH_BD, 859 RF_PATH_CD, 860 RF_PATH_ABC, 861 RF_PATH_ABD, 862 RF_PATH_ACD, 863 RF_PATH_BCD, 864 RF_PATH_ABCD, 865 }; 866 867 enum rtw89_rf_path_bit { 868 RF_A = BIT(0), 869 RF_B = BIT(1), 870 RF_C = BIT(2), 871 RF_D = BIT(3), 872 873 RF_AB = (RF_A | RF_B), 874 RF_AC = (RF_A | RF_C), 875 RF_AD = (RF_A | RF_D), 876 RF_BC = (RF_B | RF_C), 877 RF_BD = (RF_B | RF_D), 878 RF_CD = (RF_C | RF_D), 879 880 RF_ABC = (RF_A | RF_B | RF_C), 881 RF_ABD = (RF_A | RF_B | RF_D), 882 RF_ACD = (RF_A | RF_C | RF_D), 883 RF_BCD = (RF_B | RF_C | RF_D), 884 885 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 886 }; 887 888 enum rtw89_bandwidth { 889 RTW89_CHANNEL_WIDTH_20 = 0, 890 RTW89_CHANNEL_WIDTH_40 = 1, 891 RTW89_CHANNEL_WIDTH_80 = 2, 892 RTW89_CHANNEL_WIDTH_160 = 3, 893 RTW89_CHANNEL_WIDTH_320 = 4, 894 895 /* keep index order above */ 896 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 897 898 RTW89_CHANNEL_WIDTH_80_80 = 5, 899 RTW89_CHANNEL_WIDTH_5 = 6, 900 RTW89_CHANNEL_WIDTH_10 = 7, 901 }; 902 903 enum rtw89_ps_mode { 904 RTW89_PS_MODE_NONE = 0, 905 RTW89_PS_MODE_RFOFF = 1, 906 RTW89_PS_MODE_CLK_GATED = 2, 907 RTW89_PS_MODE_PWR_GATED = 3, 908 }; 909 910 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 911 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 912 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 913 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 914 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 915 916 enum rtw89_pe_duration { 917 RTW89_PE_DURATION_0 = 0, 918 RTW89_PE_DURATION_8 = 1, 919 RTW89_PE_DURATION_16 = 2, 920 RTW89_PE_DURATION_16_20 = 3, 921 }; 922 923 enum rtw89_ru_bandwidth { 924 RTW89_RU26 = 0, 925 RTW89_RU52 = 1, 926 RTW89_RU106 = 2, 927 RTW89_RU52_26 = 3, 928 RTW89_RU106_26 = 4, 929 RTW89_RU_NUM, 930 }; 931 932 enum rtw89_sc_offset { 933 RTW89_SC_DONT_CARE = 0, 934 RTW89_SC_20_UPPER = 1, 935 RTW89_SC_20_LOWER = 2, 936 RTW89_SC_20_UPMOST = 3, 937 RTW89_SC_20_LOWEST = 4, 938 RTW89_SC_20_UP2X = 5, 939 RTW89_SC_20_LOW2X = 6, 940 RTW89_SC_20_UP3X = 7, 941 RTW89_SC_20_LOW3X = 8, 942 RTW89_SC_40_UPPER = 9, 943 RTW89_SC_40_LOWER = 10, 944 }; 945 946 /* only mgd features can be added to the enum */ 947 enum rtw89_wow_flags { 948 RTW89_WOW_FLAG_EN_MAGIC_PKT, 949 RTW89_WOW_FLAG_EN_REKEY_PKT, 950 RTW89_WOW_FLAG_EN_DISCONNECT, 951 RTW89_WOW_FLAG_EN_PATTERN, 952 RTW89_WOW_FLAG_NUM, 953 }; 954 955 struct rtw89_chan { 956 u8 channel; 957 u8 primary_channel; 958 enum rtw89_band band_type; 959 enum rtw89_bandwidth band_width; 960 961 /* The follow-up are derived from the above. We must ensure that it 962 * is assigned correctly in rtw89_chan_create() if new one is added. 963 */ 964 u32 freq; 965 enum rtw89_subband subband_type; 966 enum rtw89_sc_offset pri_ch_idx; 967 u8 pri_sb_idx; 968 }; 969 970 struct rtw89_chan_rcd { 971 u8 prev_primary_channel; 972 enum rtw89_band prev_band_type; 973 bool band_changed; 974 }; 975 976 struct rtw89_channel_help_params { 977 u32 tx_en; 978 }; 979 980 struct rtw89_port_reg { 981 u32 port_cfg; 982 u32 tbtt_prohib; 983 u32 bcn_area; 984 u32 bcn_early; 985 u32 tbtt_early; 986 u32 tbtt_agg; 987 u32 bcn_space; 988 u32 bcn_forcetx; 989 u32 bcn_err_cnt; 990 u32 bcn_err_flag; 991 u32 dtim_ctrl; 992 u32 tbtt_shift; 993 u32 bcn_cnt_tmr; 994 u32 tsftr_l; 995 u32 tsftr_h; 996 u32 md_tsft; 997 u32 bss_color; 998 u32 mbssid; 999 u32 mbssid_drop; 1000 u32 tsf_sync; 1001 u32 ptcl_dbg; 1002 u32 ptcl_dbg_info; 1003 u32 bcn_drop_all; 1004 u32 hiq_win[RTW89_PORT_NUM]; 1005 }; 1006 1007 struct rtw89_txwd_body { 1008 __le32 dword0; 1009 __le32 dword1; 1010 __le32 dword2; 1011 __le32 dword3; 1012 __le32 dword4; 1013 __le32 dword5; 1014 } __packed; 1015 1016 struct rtw89_txwd_body_v1 { 1017 __le32 dword0; 1018 __le32 dword1; 1019 __le32 dword2; 1020 __le32 dword3; 1021 __le32 dword4; 1022 __le32 dword5; 1023 __le32 dword6; 1024 __le32 dword7; 1025 } __packed; 1026 1027 struct rtw89_txwd_body_v2 { 1028 __le32 dword0; 1029 __le32 dword1; 1030 __le32 dword2; 1031 __le32 dword3; 1032 __le32 dword4; 1033 __le32 dword5; 1034 __le32 dword6; 1035 __le32 dword7; 1036 } __packed; 1037 1038 struct rtw89_txwd_info { 1039 __le32 dword0; 1040 __le32 dword1; 1041 __le32 dword2; 1042 __le32 dword3; 1043 __le32 dword4; 1044 __le32 dword5; 1045 } __packed; 1046 1047 struct rtw89_txwd_info_v2 { 1048 __le32 dword0; 1049 __le32 dword1; 1050 __le32 dword2; 1051 __le32 dword3; 1052 __le32 dword4; 1053 __le32 dword5; 1054 __le32 dword6; 1055 __le32 dword7; 1056 } __packed; 1057 1058 struct rtw89_rx_desc_info { 1059 u16 pkt_size; 1060 u8 pkt_type; 1061 u8 drv_info_size; 1062 u8 phy_rpt_size; 1063 u8 hdr_cnv_size; 1064 u8 shift; 1065 u8 wl_hd_iv_len; 1066 bool long_rxdesc; 1067 bool bb_sel; 1068 bool mac_info_valid; 1069 u16 data_rate; 1070 u8 gi_ltf; 1071 u8 bw; 1072 u32 free_run_cnt; 1073 u8 user_id; 1074 bool sr_en; 1075 u8 ppdu_cnt; 1076 u8 ppdu_type; 1077 bool icv_err; 1078 bool crc32_err; 1079 bool hw_dec; 1080 bool sw_dec; 1081 bool addr1_match; 1082 u8 frag; 1083 u16 seq; 1084 u8 frame_type; 1085 u8 rx_pl_id; 1086 bool addr_cam_valid; 1087 u8 addr_cam_id; 1088 u8 sec_cam_id; 1089 u8 mac_id; 1090 u16 offset; 1091 u16 rxd_len; 1092 bool ready; 1093 u16 rssi; 1094 }; 1095 1096 struct rtw89_rxdesc_short { 1097 __le32 dword0; 1098 __le32 dword1; 1099 __le32 dword2; 1100 __le32 dword3; 1101 } __packed; 1102 1103 struct rtw89_rxdesc_short_v2 { 1104 __le32 dword0; 1105 __le32 dword1; 1106 __le32 dword2; 1107 __le32 dword3; 1108 __le32 dword4; 1109 __le32 dword5; 1110 } __packed; 1111 1112 struct rtw89_rxdesc_long { 1113 __le32 dword0; 1114 __le32 dword1; 1115 __le32 dword2; 1116 __le32 dword3; 1117 __le32 dword4; 1118 __le32 dword5; 1119 __le32 dword6; 1120 __le32 dword7; 1121 } __packed; 1122 1123 struct rtw89_rxdesc_long_v2 { 1124 __le32 dword0; 1125 __le32 dword1; 1126 __le32 dword2; 1127 __le32 dword3; 1128 __le32 dword4; 1129 __le32 dword5; 1130 __le32 dword6; 1131 __le32 dword7; 1132 __le32 dword8; 1133 __le32 dword9; 1134 } __packed; 1135 1136 struct rtw89_rxdesc_phy_rpt_v2 { 1137 __le32 dword0; 1138 __le32 dword1; 1139 } __packed; 1140 1141 struct rtw89_tx_desc_info { 1142 u16 pkt_size; 1143 u8 wp_offset; 1144 u8 mac_id; 1145 u8 qsel; 1146 u8 ch_dma; 1147 u8 hdr_llc_len; 1148 bool is_bmc; 1149 bool en_wd_info; 1150 bool wd_page; 1151 bool use_rate; 1152 bool dis_data_fb; 1153 bool tid_indicate; 1154 bool agg_en; 1155 bool bk; 1156 u8 ampdu_density; 1157 u8 ampdu_num; 1158 bool sec_en; 1159 u8 addr_info_nr; 1160 u8 sec_keyid; 1161 u8 sec_type; 1162 u8 sec_cam_idx; 1163 u8 sec_seq[6]; 1164 u16 data_rate; 1165 u16 data_retry_lowest_rate; 1166 bool fw_dl; 1167 u16 seq; 1168 bool a_ctrl_bsr; 1169 u8 hw_ssn_sel; 1170 #define RTW89_MGMT_HW_SSN_SEL 1 1171 u8 hw_seq_mode; 1172 #define RTW89_MGMT_HW_SEQ_MODE 1 1173 bool hiq; 1174 u8 port; 1175 bool er_cap; 1176 bool stbc; 1177 bool ldpc; 1178 bool upd_wlan_hdr; 1179 bool mlo; 1180 }; 1181 1182 struct rtw89_core_tx_request { 1183 enum rtw89_core_tx_type tx_type; 1184 1185 struct sk_buff *skb; 1186 struct ieee80211_vif *vif; 1187 struct ieee80211_sta *sta; 1188 struct rtw89_vif_link *rtwvif_link; 1189 struct rtw89_sta_link *rtwsta_link; 1190 struct rtw89_tx_desc_info desc_info; 1191 }; 1192 1193 struct rtw89_txq { 1194 struct list_head list; 1195 unsigned long flags; 1196 int wait_cnt; 1197 }; 1198 1199 struct rtw89_mac_ax_gnt { 1200 u8 gnt_bt_sw_en; 1201 u8 gnt_bt; 1202 u8 gnt_wl_sw_en; 1203 u8 gnt_wl; 1204 } __packed; 1205 1206 struct rtw89_mac_ax_wl_act { 1207 u8 wlan_act_en; 1208 u8 wlan_act; 1209 }; 1210 1211 #define RTW89_MAC_AX_COEX_GNT_NR 2 1212 struct rtw89_mac_ax_coex_gnt { 1213 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1214 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1215 }; 1216 1217 enum rtw89_btc_ncnt { 1218 BTC_NCNT_POWER_ON = 0x0, 1219 BTC_NCNT_POWER_OFF, 1220 BTC_NCNT_INIT_COEX, 1221 BTC_NCNT_SCAN_START, 1222 BTC_NCNT_SCAN_FINISH, 1223 BTC_NCNT_SPECIAL_PACKET, 1224 BTC_NCNT_SWITCH_BAND, 1225 BTC_NCNT_RFK_TIMEOUT, 1226 BTC_NCNT_SHOW_COEX_INFO, 1227 BTC_NCNT_ROLE_INFO, 1228 BTC_NCNT_CONTROL, 1229 BTC_NCNT_RADIO_STATE, 1230 BTC_NCNT_CUSTOMERIZE, 1231 BTC_NCNT_WL_RFK, 1232 BTC_NCNT_WL_STA, 1233 BTC_NCNT_WL_STA_LAST, 1234 BTC_NCNT_FWINFO, 1235 BTC_NCNT_TIMER, 1236 BTC_NCNT_SWITCH_CHBW, 1237 BTC_NCNT_RESUME_DL_FW, 1238 BTC_NCNT_COUNTRYCODE, 1239 BTC_NCNT_NUM, 1240 }; 1241 1242 enum rtw89_btc_btinfo { 1243 BTC_BTINFO_L0 = 0, 1244 BTC_BTINFO_L1, 1245 BTC_BTINFO_L2, 1246 BTC_BTINFO_L3, 1247 BTC_BTINFO_H0, 1248 BTC_BTINFO_H1, 1249 BTC_BTINFO_H2, 1250 BTC_BTINFO_H3, 1251 BTC_BTINFO_MAX 1252 }; 1253 1254 enum rtw89_btc_dcnt { 1255 BTC_DCNT_RUN = 0x0, 1256 BTC_DCNT_CX_RUNINFO, 1257 BTC_DCNT_RPT, 1258 BTC_DCNT_RPT_HANG, 1259 BTC_DCNT_CYCLE, 1260 BTC_DCNT_CYCLE_HANG, 1261 BTC_DCNT_W1, 1262 BTC_DCNT_W1_HANG, 1263 BTC_DCNT_B1, 1264 BTC_DCNT_B1_HANG, 1265 BTC_DCNT_TDMA_NONSYNC, 1266 BTC_DCNT_SLOT_NONSYNC, 1267 BTC_DCNT_BTCNT_HANG, 1268 BTC_DCNT_BTTX_HANG, 1269 BTC_DCNT_WL_SLOT_DRIFT, 1270 BTC_DCNT_WL_STA_LAST, 1271 BTC_DCNT_BT_SLOT_DRIFT, 1272 BTC_DCNT_BT_SLOT_FLOOD, 1273 BTC_DCNT_FDDT_TRIG, 1274 BTC_DCNT_E2G, 1275 BTC_DCNT_E2G_HANG, 1276 BTC_DCNT_WL_FW_VER_MATCH, 1277 BTC_DCNT_NULL_TX_FAIL, 1278 BTC_DCNT_WL_STA_NTFY, 1279 BTC_DCNT_NUM, 1280 }; 1281 1282 enum rtw89_btc_wl_state_cnt { 1283 BTC_WCNT_SCANAP = 0x0, 1284 BTC_WCNT_DHCP, 1285 BTC_WCNT_EAPOL, 1286 BTC_WCNT_ARP, 1287 BTC_WCNT_SCBDUPDATE, 1288 BTC_WCNT_RFK_REQ, 1289 BTC_WCNT_RFK_GO, 1290 BTC_WCNT_RFK_REJECT, 1291 BTC_WCNT_RFK_TIMEOUT, 1292 BTC_WCNT_CH_UPDATE, 1293 BTC_WCNT_DBCC_ALL_2G, 1294 BTC_WCNT_DBCC_CHG, 1295 BTC_WCNT_RX_OK_LAST, 1296 BTC_WCNT_RX_OK_LAST2S, 1297 BTC_WCNT_RX_ERR_LAST, 1298 BTC_WCNT_RX_ERR_LAST2S, 1299 BTC_WCNT_RX_LAST, 1300 BTC_WCNT_NUM 1301 }; 1302 1303 enum rtw89_btc_bt_state_cnt { 1304 BTC_BCNT_RETRY = 0x0, 1305 BTC_BCNT_REINIT, 1306 BTC_BCNT_REENABLE, 1307 BTC_BCNT_SCBDREAD, 1308 BTC_BCNT_RELINK, 1309 BTC_BCNT_IGNOWL, 1310 BTC_BCNT_INQPAG, 1311 BTC_BCNT_INQ, 1312 BTC_BCNT_PAGE, 1313 BTC_BCNT_ROLESW, 1314 BTC_BCNT_AFH, 1315 BTC_BCNT_INFOUPDATE, 1316 BTC_BCNT_INFOSAME, 1317 BTC_BCNT_SCBDUPDATE, 1318 BTC_BCNT_HIPRI_TX, 1319 BTC_BCNT_HIPRI_RX, 1320 BTC_BCNT_LOPRI_TX, 1321 BTC_BCNT_LOPRI_RX, 1322 BTC_BCNT_POLUT, 1323 BTC_BCNT_POLUT_NOW, 1324 BTC_BCNT_POLUT_DIFF, 1325 BTC_BCNT_RATECHG, 1326 BTC_BCNT_NUM, 1327 }; 1328 1329 enum rtw89_btc_bt_profile { 1330 BTC_BT_NOPROFILE = 0, 1331 BTC_BT_HFP = BIT(0), 1332 BTC_BT_HID = BIT(1), 1333 BTC_BT_A2DP = BIT(2), 1334 BTC_BT_PAN = BIT(3), 1335 BTC_PROFILE_MAX = 4, 1336 }; 1337 1338 struct rtw89_btc_ant_info { 1339 u8 type; /* shared, dedicated */ 1340 u8 num; 1341 u8 isolation; 1342 1343 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1344 u8 diversity: 1; 1345 u8 btg_pos: 2; 1346 u8 stream_cnt: 4; 1347 }; 1348 1349 struct rtw89_btc_ant_info_v7 { 1350 u8 type; /* shared, dedicated(non-shared) */ 1351 u8 num; /* antenna count */ 1352 u8 isolation; 1353 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1354 1355 u8 diversity; /* only for wifi use 1-antenna */ 1356 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1357 u8 stream_cnt; /* spatial_stream count */ 1358 u8 rsvd; 1359 } __packed; 1360 1361 enum rtw89_tfc_dir { 1362 RTW89_TFC_UL, 1363 RTW89_TFC_DL, 1364 }; 1365 1366 struct rtw89_btc_wl_smap { 1367 u32 busy: 1; 1368 u32 scan: 1; 1369 u32 connecting: 1; 1370 u32 roaming: 1; 1371 u32 dbccing: 1; 1372 u32 _4way: 1; 1373 u32 rf_off: 1; 1374 u32 lps: 2; 1375 u32 ips: 1; 1376 u32 init_ok: 1; 1377 u32 traffic_dir : 2; 1378 u32 rf_off_pre: 1; 1379 u32 lps_pre: 2; 1380 u32 lps_exiting: 1; 1381 u32 emlsr: 1; 1382 }; 1383 1384 enum rtw89_tfc_lv { 1385 RTW89_TFC_IDLE, 1386 RTW89_TFC_ULTRA_LOW, 1387 RTW89_TFC_LOW, 1388 RTW89_TFC_MID, 1389 RTW89_TFC_HIGH, 1390 }; 1391 1392 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1393 DECLARE_EWMA(tp, 10, 2); 1394 1395 struct rtw89_traffic_stats { 1396 /* units in bytes */ 1397 u64 tx_unicast; 1398 u64 rx_unicast; 1399 u32 tx_avg_len; 1400 u32 rx_avg_len; 1401 1402 /* count for packets */ 1403 u64 tx_cnt; 1404 u64 rx_cnt; 1405 1406 /* units in Mbps */ 1407 u32 tx_throughput; 1408 u32 rx_throughput; 1409 u32 tx_throughput_raw; 1410 u32 rx_throughput_raw; 1411 1412 u32 rx_tf_acc; 1413 u32 rx_tf_periodic; 1414 1415 enum rtw89_tfc_lv tx_tfc_lv; 1416 enum rtw89_tfc_lv rx_tfc_lv; 1417 struct ewma_tp tx_ewma_tp; 1418 struct ewma_tp rx_ewma_tp; 1419 1420 u16 tx_rate; 1421 u16 rx_rate; 1422 }; 1423 1424 struct rtw89_btc_chdef { 1425 u8 center_ch; 1426 u8 band; 1427 u8 chan; 1428 enum rtw89_sc_offset offset; 1429 enum rtw89_bandwidth bw; 1430 }; 1431 1432 struct rtw89_btc_statistic { 1433 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1434 struct rtw89_traffic_stats traffic; 1435 }; 1436 1437 #define BTC_WL_RSSI_THMAX 4 1438 1439 struct rtw89_btc_wl_link_info { 1440 struct rtw89_btc_chdef chdef; 1441 struct rtw89_btc_statistic stat; 1442 enum rtw89_tfc_dir dir; 1443 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1444 u8 mac_addr[ETH_ALEN]; 1445 u8 busy; 1446 u8 ch; 1447 u8 bw; 1448 u8 band; 1449 u8 role; 1450 u8 pid; 1451 u8 phy; 1452 u8 dtim_period; 1453 u8 mode; 1454 u8 tx_1ss_limit; 1455 1456 u8 mac_id; 1457 u8 tx_retry; 1458 1459 u32 bcn_period; 1460 u32 busy_t; 1461 u32 tx_time; 1462 u32 client_cnt; 1463 u32 rx_rate_drop_cnt; 1464 u32 noa_duration; 1465 1466 u32 active: 1; 1467 u32 noa: 1; 1468 u32 client_ps: 1; 1469 u32 connected: 2; 1470 }; 1471 1472 union rtw89_btc_wl_state_map { 1473 u32 val; 1474 struct rtw89_btc_wl_smap map; 1475 }; 1476 1477 struct rtw89_btc_bt_hfp_desc { 1478 u32 exist: 1; 1479 u32 type: 2; 1480 u32 rsvd: 29; 1481 }; 1482 1483 struct rtw89_btc_bt_hid_desc { 1484 u32 exist: 1; 1485 u32 slot_info: 2; 1486 u32 pair_cnt: 2; 1487 u32 type: 8; 1488 u32 rsvd: 19; 1489 }; 1490 1491 struct rtw89_btc_bt_a2dp_desc { 1492 u8 exist: 1; 1493 u8 exist_last: 1; 1494 u8 play_latency: 1; 1495 u8 type: 3; 1496 u8 active: 1; 1497 u8 sink: 1; 1498 u32 handle_update: 1; 1499 u32 devinfo_query: 1; 1500 u32 no_empty_streak_2s: 8; 1501 u32 no_empty_streak_max: 8; 1502 u32 rsvd: 6; 1503 1504 u8 bitpool; 1505 u16 vendor_id; 1506 u32 device_name; 1507 u32 flush_time; 1508 }; 1509 1510 struct rtw89_btc_bt_pan_desc { 1511 u32 exist: 1; 1512 u32 type: 1; 1513 u32 active: 1; 1514 u32 rsvd: 29; 1515 }; 1516 1517 struct rtw89_btc_bt_rfk_info { 1518 u32 run: 1; 1519 u32 req: 1; 1520 u32 timeout: 1; 1521 u32 rsvd: 29; 1522 }; 1523 1524 union rtw89_btc_bt_rfk_info_map { 1525 u32 val; 1526 struct rtw89_btc_bt_rfk_info map; 1527 }; 1528 1529 struct rtw89_btc_bt_ver_info { 1530 u32 fw_coex; /* match with which coex_ver */ 1531 u32 fw; 1532 }; 1533 1534 struct rtw89_btc_bool_sta_chg { 1535 u32 now: 1; 1536 u32 last: 1; 1537 u32 remain: 1; 1538 u32 srvd: 29; 1539 }; 1540 1541 struct rtw89_btc_u8_sta_chg { 1542 u8 now; 1543 u8 last; 1544 u8 remain; 1545 u8 rsvd; 1546 }; 1547 1548 struct rtw89_btc_wl_scan_info { 1549 u8 band[RTW89_PHY_MAX]; 1550 u8 phy_map; 1551 u8 rsvd; 1552 }; 1553 1554 struct rtw89_btc_wl_dbcc_info { 1555 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1556 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1557 u8 real_band[RTW89_PHY_MAX]; 1558 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1559 }; 1560 1561 struct rtw89_btc_wl_active_role { 1562 u8 connected: 1; 1563 u8 pid: 3; 1564 u8 phy: 1; 1565 u8 noa: 1; 1566 u8 band: 2; 1567 1568 u8 client_ps: 1; 1569 u8 bw: 7; 1570 1571 u8 role; 1572 u8 ch; 1573 1574 u16 tx_lvl; 1575 u16 rx_lvl; 1576 u16 tx_rate; 1577 u16 rx_rate; 1578 }; 1579 1580 struct rtw89_btc_wl_active_role_v1 { 1581 u8 connected: 1; 1582 u8 pid: 3; 1583 u8 phy: 1; 1584 u8 noa: 1; 1585 u8 band: 2; 1586 1587 u8 client_ps: 1; 1588 u8 bw: 7; 1589 1590 u8 role; 1591 u8 ch; 1592 1593 u16 tx_lvl; 1594 u16 rx_lvl; 1595 u16 tx_rate; 1596 u16 rx_rate; 1597 1598 u32 noa_duration; /* ms */ 1599 }; 1600 1601 struct rtw89_btc_wl_active_role_v2 { 1602 u8 connected: 1; 1603 u8 pid: 3; 1604 u8 phy: 1; 1605 u8 noa: 1; 1606 u8 band: 2; 1607 1608 u8 client_ps: 1; 1609 u8 bw: 7; 1610 1611 u8 role; 1612 u8 ch; 1613 1614 u32 noa_duration; /* ms */ 1615 }; 1616 1617 struct rtw89_btc_wl_active_role_v7 { 1618 u8 connected; 1619 u8 pid; 1620 u8 phy; 1621 u8 noa; 1622 1623 u8 band; 1624 u8 client_ps; 1625 u8 bw; 1626 u8 role; 1627 1628 u8 ch; 1629 u8 noa_dur; 1630 u8 client_cnt; 1631 u8 rsvd2; 1632 } __packed; 1633 1634 struct rtw89_btc_wl_role_info_bpos { 1635 u16 none: 1; 1636 u16 station: 1; 1637 u16 ap: 1; 1638 u16 vap: 1; 1639 u16 adhoc: 1; 1640 u16 adhoc_master: 1; 1641 u16 mesh: 1; 1642 u16 moniter: 1; 1643 u16 p2p_device: 1; 1644 u16 p2p_gc: 1; 1645 u16 p2p_go: 1; 1646 u16 nan: 1; 1647 }; 1648 1649 struct rtw89_btc_wl_scc_ctrl { 1650 u8 null_role1; 1651 u8 null_role2; 1652 u8 ebt_null; /* if tx null at EBT slot */ 1653 }; 1654 1655 union rtw89_btc_wl_role_info_map { 1656 u16 val; 1657 struct rtw89_btc_wl_role_info_bpos role; 1658 }; 1659 1660 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1661 u8 connect_cnt; 1662 u8 link_mode; 1663 union rtw89_btc_wl_role_info_map role_map; 1664 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1665 }; 1666 1667 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1668 u8 connect_cnt; 1669 u8 link_mode; 1670 union rtw89_btc_wl_role_info_map role_map; 1671 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1672 u32 mrole_type; /* btc_wl_mrole_type */ 1673 u32 mrole_noa_duration; /* ms */ 1674 1675 u32 dbcc_en: 1; 1676 u32 dbcc_chg: 1; 1677 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1678 u32 link_mode_chg: 1; 1679 u32 rsvd: 27; 1680 }; 1681 1682 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1683 u8 connect_cnt; 1684 u8 link_mode; 1685 union rtw89_btc_wl_role_info_map role_map; 1686 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1687 u32 mrole_type; /* btc_wl_mrole_type */ 1688 u32 mrole_noa_duration; /* ms */ 1689 1690 u32 dbcc_en: 1; 1691 u32 dbcc_chg: 1; 1692 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1693 u32 link_mode_chg: 1; 1694 u32 rsvd: 27; 1695 }; 1696 1697 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1698 u8 connected; 1699 u8 pid; 1700 u8 phy; 1701 u8 noa; 1702 1703 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1704 u8 active; /* 0:rlink is under doze */ 1705 u8 bw; /* enum channel_width */ 1706 u8 role; /*enum role_type */ 1707 1708 u8 ch; 1709 u8 noa_dur; /* ms */ 1710 u8 client_cnt; /* for Role = P2P-Go/AP */ 1711 u8 mode; /* wifi protocol */ 1712 } __packed; 1713 1714 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1715 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 1716 u8 connect_cnt; 1717 u8 link_mode; 1718 u8 link_mode_chg; 1719 u8 p2p_2g; 1720 1721 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 1722 1723 u32 role_map; 1724 u32 mrole_type; /* btc_wl_mrole_type */ 1725 u32 mrole_noa_duration; /* ms */ 1726 u32 dbcc_en; 1727 u32 dbcc_chg; 1728 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1729 } __packed; 1730 1731 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1732 u8 connect_cnt; 1733 u8 link_mode; 1734 u8 link_mode_chg; 1735 u8 p2p_2g; 1736 1737 u8 pta_req_band; 1738 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1739 u8 dbcc_chg; 1740 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1741 1742 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1743 1744 u32 role_map; 1745 u32 mrole_type; /* btc_wl_mrole_type */ 1746 u32 mrole_noa_duration; /* ms */ 1747 } __packed; 1748 1749 struct rtw89_btc_wl_ver_info { 1750 u32 fw_coex; /* match with which coex_ver */ 1751 u32 fw; 1752 u32 mac; 1753 u32 bb; 1754 u32 rf; 1755 }; 1756 1757 struct rtw89_btc_wl_afh_info { 1758 u8 en; 1759 u8 ch; 1760 u8 bw; 1761 u8 rsvd; 1762 } __packed; 1763 1764 struct rtw89_btc_wl_rfk_info { 1765 u32 state: 2; 1766 u32 path_map: 4; 1767 u32 phy_map: 2; 1768 u32 band: 2; 1769 u32 type: 8; 1770 u32 rsvd: 14; 1771 1772 u32 start_time; 1773 u32 proc_time; 1774 }; 1775 1776 struct rtw89_btc_bt_smap { 1777 u32 connect: 1; 1778 u32 ble_connect: 1; 1779 u32 acl_busy: 1; 1780 u32 sco_busy: 1; 1781 u32 mesh_busy: 1; 1782 u32 inq_pag: 1; 1783 }; 1784 1785 union rtw89_btc_bt_state_map { 1786 u32 val; 1787 struct rtw89_btc_bt_smap map; 1788 }; 1789 1790 #define BTC_BT_RSSI_THMAX 4 1791 #define BTC_BT_AFH_GROUP 12 1792 #define BTC_BT_AFH_LE_GROUP 5 1793 1794 struct rtw89_btc_bt_link_info { 1795 struct rtw89_btc_u8_sta_chg profile_cnt; 1796 struct rtw89_btc_bool_sta_chg multi_link; 1797 struct rtw89_btc_bool_sta_chg relink; 1798 struct rtw89_btc_bt_hfp_desc hfp_desc; 1799 struct rtw89_btc_bt_hid_desc hid_desc; 1800 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1801 struct rtw89_btc_bt_pan_desc pan_desc; 1802 union rtw89_btc_bt_state_map status; 1803 1804 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1805 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1806 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1807 u8 afh_map[BTC_BT_AFH_GROUP]; 1808 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1809 1810 u32 role_sw: 1; 1811 u32 slave_role: 1; 1812 u32 afh_update: 1; 1813 u32 cqddr: 1; 1814 u32 rssi: 8; 1815 u32 tx_3m: 1; 1816 u32 rsvd: 19; 1817 }; 1818 1819 struct rtw89_btc_3rdcx_info { 1820 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1821 u8 hw_coex; 1822 u16 rsvd; 1823 }; 1824 1825 struct rtw89_btc_dm_emap { 1826 u32 init: 1; 1827 u32 pta_owner: 1; 1828 u32 wl_rfk_timeout: 1; 1829 u32 bt_rfk_timeout: 1; 1830 u32 wl_fw_hang: 1; 1831 u32 cycle_hang: 1; 1832 u32 w1_hang: 1; 1833 u32 b1_hang: 1; 1834 u32 tdma_no_sync: 1; 1835 u32 slot_no_sync: 1; 1836 u32 wl_slot_drift: 1; 1837 u32 bt_slot_drift: 1; 1838 u32 role_num_mismatch: 1; 1839 u32 null1_tx_late: 1; 1840 u32 bt_afh_conflict: 1; 1841 u32 bt_leafh_conflict: 1; 1842 u32 bt_slot_flood: 1; 1843 u32 wl_e2g_hang: 1; 1844 u32 wl_ver_mismatch: 1; 1845 u32 bt_ver_mismatch: 1; 1846 u32 rfe_type0: 1; 1847 u32 h2c_buffer_over: 1; 1848 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1849 u32 wl_no_sta_ntfy: 1; 1850 1851 u32 h2c_bmap_mismatch: 1; 1852 u32 c2h_bmap_mismatch: 1; 1853 u32 h2c_struct_invalid: 1; 1854 u32 c2h_struct_invalid: 1; 1855 u32 h2c_c2h_buffer_mismatch: 1; 1856 }; 1857 1858 union rtw89_btc_dm_error_map { 1859 u32 val; 1860 struct rtw89_btc_dm_emap map; 1861 }; 1862 1863 struct rtw89_btc_rf_para { 1864 u32 tx_pwr_freerun; 1865 u32 rx_gain_freerun; 1866 u32 tx_pwr_perpkt; 1867 u32 rx_gain_perpkt; 1868 }; 1869 1870 struct rtw89_btc_wl_nhm { 1871 u8 instant_wl_nhm_dbm; 1872 u8 instant_wl_nhm_per_mhz; 1873 u16 valid_record_times; 1874 s8 record_pwr[16]; 1875 u8 record_ratio[16]; 1876 s8 pwr; /* dbm_per_MHz */ 1877 u8 ratio; 1878 u8 current_status; 1879 u8 refresh; 1880 bool start_flag; 1881 s8 pwr_max; 1882 s8 pwr_min; 1883 }; 1884 1885 struct rtw89_btc_wl_info { 1886 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1887 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1888 struct rtw89_btc_wl_rfk_info rfk_info; 1889 struct rtw89_btc_wl_ver_info ver_info; 1890 struct rtw89_btc_wl_afh_info afh_info; 1891 struct rtw89_btc_wl_role_info role_info; 1892 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1893 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1894 struct rtw89_btc_wl_role_info_v7 role_info_v7; 1895 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1896 struct rtw89_btc_wl_scan_info scan_info; 1897 struct rtw89_btc_wl_dbcc_info dbcc_info; 1898 struct rtw89_btc_rf_para rf_para; 1899 struct rtw89_btc_wl_nhm nhm; 1900 union rtw89_btc_wl_state_map status; 1901 1902 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1903 u8 rssi_level; 1904 u8 cn_report; 1905 u8 coex_mode; 1906 u8 pta_req_mac; 1907 u8 bt_polut_type[RTW89_PHY_MAX]; /* BT polluted WL-Tx type for phy0/1 */ 1908 1909 bool is_5g_hi_channel; 1910 bool pta_reg_mac_chg; 1911 bool bg_mode; 1912 bool he_mode; 1913 bool scbd_change; 1914 bool fw_ver_mismatch; 1915 bool client_cnt_inc_2g; 1916 u32 scbd; 1917 }; 1918 1919 struct rtw89_btc_module { 1920 struct rtw89_btc_ant_info ant; 1921 u8 rfe_type; 1922 u8 cv; 1923 1924 u8 bt_solo: 1; 1925 u8 bt_pos: 1; 1926 u8 switch_type: 1; 1927 u8 wa_type: 3; 1928 1929 u8 kt_ver_adie; 1930 }; 1931 1932 struct rtw89_btc_module_v7 { 1933 u8 rfe_type; 1934 u8 kt_ver; 1935 u8 bt_solo; 1936 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1937 1938 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1939 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1940 u8 kt_ver_adie; 1941 u8 rsvd; 1942 1943 struct rtw89_btc_ant_info_v7 ant; 1944 } __packed; 1945 1946 union rtw89_btc_module_info { 1947 struct rtw89_btc_module md; 1948 struct rtw89_btc_module_v7 md_v7; 1949 }; 1950 1951 #define RTW89_BTC_DM_MAXSTEP 30 1952 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1953 1954 struct rtw89_btc_dm_step { 1955 u16 step[RTW89_BTC_DM_MAXSTEP]; 1956 u8 step_pos; 1957 bool step_ov; 1958 }; 1959 1960 struct rtw89_btc_init_info { 1961 struct rtw89_btc_module module; 1962 u8 wl_guard_ch; 1963 1964 u8 wl_only: 1; 1965 u8 wl_init_ok: 1; 1966 u8 dbcc_en: 1; 1967 u8 cx_other: 1; 1968 u8 bt_only: 1; 1969 1970 u16 rsvd; 1971 }; 1972 1973 struct rtw89_btc_init_info_v7 { 1974 u8 wl_guard_ch; 1975 u8 wl_only; 1976 u8 wl_init_ok; 1977 u8 rsvd3; 1978 1979 u8 cx_other; 1980 u8 bt_only; 1981 u8 pta_mode; 1982 u8 pta_direction; 1983 1984 struct rtw89_btc_module_v7 module; 1985 } __packed; 1986 1987 union rtw89_btc_init_info_u { 1988 struct rtw89_btc_init_info init; 1989 struct rtw89_btc_init_info_v7 init_v7; 1990 }; 1991 1992 struct rtw89_btc_wl_tx_limit_para { 1993 u16 enable; 1994 u32 tx_time; /* unit: us */ 1995 u16 tx_retry; 1996 }; 1997 1998 enum rtw89_btc_bt_scan_type { 1999 BTC_SCAN_INQ = 0, 2000 BTC_SCAN_PAGE, 2001 BTC_SCAN_BLE, 2002 BTC_SCAN_INIT, 2003 BTC_SCAN_TV, 2004 BTC_SCAN_ADV, 2005 BTC_SCAN_MAX1, 2006 }; 2007 2008 enum rtw89_btc_ble_scan_type { 2009 CXSCAN_BG = 0, 2010 CXSCAN_INIT, 2011 CXSCAN_LE, 2012 CXSCAN_MAX 2013 }; 2014 2015 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 2016 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2017 2018 struct rtw89_btc_bt_scan_info_v1 { 2019 __le16 win; 2020 __le16 intvl; 2021 __le32 flags; 2022 } __packed; 2023 2024 struct rtw89_btc_bt_scan_info_v2 { 2025 __le16 win; 2026 __le16 intvl; 2027 } __packed; 2028 2029 struct rtw89_btc_fbtc_btscan_v1 { 2030 u8 fver; /* btc_ver::fcxbtscan */ 2031 u8 rsvd; 2032 __le16 rsvd2; 2033 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2034 } __packed; 2035 2036 struct rtw89_btc_fbtc_btscan_v2 { 2037 u8 fver; /* btc_ver::fcxbtscan */ 2038 u8 type; 2039 __le16 rsvd2; 2040 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2041 } __packed; 2042 2043 struct rtw89_btc_fbtc_btscan_v7 { 2044 u8 fver; /* btc_ver::fcxbtscan */ 2045 u8 type; 2046 u8 rsvd0; 2047 u8 rsvd1; 2048 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2049 } __packed; 2050 2051 union rtw89_btc_fbtc_btscan { 2052 struct rtw89_btc_fbtc_btscan_v1 v1; 2053 struct rtw89_btc_fbtc_btscan_v2 v2; 2054 struct rtw89_btc_fbtc_btscan_v7 v7; 2055 }; 2056 2057 struct rtw89_btc_bt_info { 2058 struct rtw89_btc_bt_link_info link_info; 2059 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2060 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2061 struct rtw89_btc_bt_ver_info ver_info; 2062 struct rtw89_btc_bool_sta_chg enable; 2063 struct rtw89_btc_bool_sta_chg inq_pag; 2064 struct rtw89_btc_rf_para rf_para; 2065 union rtw89_btc_bt_rfk_info_map rfk_info; 2066 2067 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2068 u8 rssi_level; 2069 2070 u32 scbd; 2071 u32 feature; 2072 2073 u32 mbx_avl: 1; 2074 u32 whql_test: 1; 2075 u32 igno_wl: 1; 2076 u32 reinit: 1; 2077 u32 ble_scan_en: 1; 2078 u32 btg_type: 1; 2079 u32 inq: 1; 2080 u32 pag: 1; 2081 u32 run_patch_code: 1; 2082 u32 hi_lna_rx: 1; 2083 u32 scan_rx_low_pri: 1; 2084 u32 scan_info_update: 1; 2085 u32 lna_constrain: 3; 2086 u32 rsvd: 17; 2087 }; 2088 2089 struct rtw89_btc_cx { 2090 struct rtw89_btc_wl_info wl; 2091 struct rtw89_btc_bt_info bt; 2092 struct rtw89_btc_3rdcx_info other; 2093 u32 state_map; 2094 u32 cnt_bt[BTC_BCNT_NUM]; 2095 u32 cnt_wl[BTC_WCNT_NUM]; 2096 }; 2097 2098 struct rtw89_btc_fbtc_tdma { 2099 u8 type; /* btc_ver::fcxtdma */ 2100 u8 rxflctrl; 2101 u8 txpause; 2102 u8 wtgle_n; 2103 u8 leak_n; 2104 u8 ext_ctrl; 2105 u8 rxflctrl_role; 2106 u8 option_ctrl; 2107 } __packed; 2108 2109 struct rtw89_btc_fbtc_tdma_v3 { 2110 u8 fver; /* btc_ver::fcxtdma */ 2111 u8 rsvd; 2112 __le16 rsvd1; 2113 struct rtw89_btc_fbtc_tdma tdma; 2114 } __packed; 2115 2116 union rtw89_btc_fbtc_tdma_le32 { 2117 struct rtw89_btc_fbtc_tdma v1; 2118 struct rtw89_btc_fbtc_tdma_v3 v3; 2119 }; 2120 2121 #define CXMREG_MAX 30 2122 #define CXMREG_MAX_V2 20 2123 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2124 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2125 2126 enum rtw89_btc_bt_sta_counter { 2127 BTC_BCNT_RFK_REQ = 0, 2128 BTC_BCNT_RFK_GO = 1, 2129 BTC_BCNT_RFK_REJECT = 2, 2130 BTC_BCNT_RFK_FAIL = 3, 2131 BTC_BCNT_RFK_TIMEOUT = 4, 2132 BTC_BCNT_HI_TX = 5, 2133 BTC_BCNT_HI_RX = 6, 2134 BTC_BCNT_LO_TX = 7, 2135 BTC_BCNT_LO_RX = 8, 2136 BTC_BCNT_POLLUTED = 9, 2137 BTC_BCNT_STA_MAX 2138 }; 2139 2140 enum rtw89_btc_bt_sta_counter_v105 { 2141 BTC_BCNT_RFK_REQ_V105 = 0, 2142 BTC_BCNT_HI_TX_V105 = 1, 2143 BTC_BCNT_HI_RX_V105 = 2, 2144 BTC_BCNT_LO_TX_V105 = 3, 2145 BTC_BCNT_LO_RX_V105 = 4, 2146 BTC_BCNT_POLLUTED_V105 = 5, 2147 BTC_BCNT_STA_MAX_V105 2148 }; 2149 2150 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2151 u16 fver; /* btc_ver::fcxbtcrpt */ 2152 u16 rpt_cnt; /* tmr counters */ 2153 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2154 u32 wl_fw_cx_offload; 2155 u32 wl_fw_ver; 2156 u32 rpt_enable; 2157 u32 rpt_para; /* ms */ 2158 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2159 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2160 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2161 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2162 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2163 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2164 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2165 u32 c2h_cnt; /* fw send c2h counter */ 2166 u32 h2c_cnt; /* fw recv h2c counter */ 2167 } __packed; 2168 2169 struct rtw89_btc_fbtc_rpt_ctrl_info { 2170 __le32 cnt; /* fw report counter */ 2171 __le32 en; /* report map */ 2172 __le32 para; /* not used */ 2173 2174 __le32 cnt_c2h; /* fw send c2h counter */ 2175 __le32 cnt_h2c; /* fw recv h2c counter */ 2176 __le32 len_c2h; /* The total length of the last C2H */ 2177 2178 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2179 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2180 } __packed; 2181 2182 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2183 __le32 cx_ver; /* match which driver's coex version */ 2184 __le32 fw_ver; 2185 __le32 en; /* report map */ 2186 2187 __le16 cnt; /* fw report counter */ 2188 __le16 cnt_c2h; /* fw send c2h counter */ 2189 __le16 cnt_h2c; /* fw recv h2c counter */ 2190 __le16 len_c2h; /* The total length of the last C2H */ 2191 2192 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2193 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2194 } __packed; 2195 2196 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2197 __le16 cnt; /* fw report counter */ 2198 __le16 cnt_c2h; /* fw send c2h counter */ 2199 __le16 cnt_h2c; /* fw recv h2c counter */ 2200 __le16 len_c2h; /* The total length of the last C2H */ 2201 2202 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2203 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2204 2205 __le32 cx_ver; /* match which driver's coex version */ 2206 __le32 fw_ver; 2207 __le32 en; /* report map */ 2208 } __packed; 2209 2210 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2211 __le32 cx_ver; /* match which driver's coex version */ 2212 __le32 cx_offload; 2213 __le32 fw_ver; 2214 } __packed; 2215 2216 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2217 __le32 cnt_empty; /* a2dp empty count */ 2218 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2219 __le32 cnt_tx; 2220 __le32 cnt_ack; 2221 __le32 cnt_nack; 2222 } __packed; 2223 2224 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2225 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2226 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2227 __le32 cnt_recv; /* fw recv mailbox counter */ 2228 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2229 } __packed; 2230 2231 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2232 u8 fver; 2233 u8 rsvd; 2234 __le16 rsvd1; 2235 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2236 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2237 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2238 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2239 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 2240 } __packed; 2241 2242 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2243 u8 fver; 2244 u8 rsvd; 2245 __le16 rsvd1; 2246 2247 u8 gnt_val[RTW89_PHY_MAX][4]; 2248 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2249 2250 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2251 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2252 } __packed; 2253 2254 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2255 u8 fver; 2256 u8 rsvd; 2257 __le16 rsvd1; 2258 2259 u8 gnt_val[RTW89_PHY_MAX][4]; 2260 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2261 2262 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2263 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2264 } __packed; 2265 2266 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2267 u8 fver; 2268 u8 rsvd0; 2269 u8 rsvd1; 2270 u8 rsvd2; 2271 2272 u8 gnt_val[RTW89_PHY_MAX][4]; 2273 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2274 2275 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2276 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2277 } __packed; 2278 2279 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2280 u8 fver; 2281 u8 rsvd0; 2282 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2283 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2284 2285 u8 gnt_val[RTW89_PHY_MAX][4]; 2286 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2287 2288 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2289 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2290 } __packed; 2291 2292 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2293 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2294 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2295 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2296 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2297 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 2298 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2299 }; 2300 2301 enum rtw89_fbtc_ext_ctrl_type { 2302 CXECTL_OFF = 0x0, /* tdma off */ 2303 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2304 CXECTL_EXT = 0x2, 2305 CXECTL_MAX 2306 }; 2307 2308 union rtw89_btc_fbtc_rxflct { 2309 u8 val; 2310 u8 type: 3; 2311 u8 tgln_n: 5; 2312 }; 2313 2314 enum rtw89_btc_cxst_state { 2315 CXST_OFF = 0x0, 2316 CXST_B2W = 0x1, 2317 CXST_W1 = 0x2, 2318 CXST_W2 = 0x3, 2319 CXST_W2B = 0x4, 2320 CXST_B1 = 0x5, 2321 CXST_B2 = 0x6, 2322 CXST_B3 = 0x7, 2323 CXST_B4 = 0x8, 2324 CXST_LK = 0x9, 2325 CXST_BLK = 0xa, 2326 CXST_E2G = 0xb, 2327 CXST_E5G = 0xc, 2328 CXST_EBT = 0xd, 2329 CXST_ENULL = 0xe, 2330 CXST_WLK = 0xf, 2331 CXST_W1FDD = 0x10, 2332 CXST_B1FDD = 0x11, 2333 CXST_MAX = 0x12, 2334 }; 2335 2336 enum rtw89_btc_cxevnt { 2337 CXEVNT_TDMA_ENTRY = 0x0, 2338 CXEVNT_WL_TMR, 2339 CXEVNT_B1_TMR, 2340 CXEVNT_B2_TMR, 2341 CXEVNT_B3_TMR, 2342 CXEVNT_B4_TMR, 2343 CXEVNT_W2B_TMR, 2344 CXEVNT_B2W_TMR, 2345 CXEVNT_BCN_EARLY, 2346 CXEVNT_A2DP_EMPTY, 2347 CXEVNT_LK_END, 2348 CXEVNT_RX_ISR, 2349 CXEVNT_RX_FC0, 2350 CXEVNT_RX_FC1, 2351 CXEVNT_BT_RELINK, 2352 CXEVNT_BT_RETRY, 2353 CXEVNT_E2G, 2354 CXEVNT_E5G, 2355 CXEVNT_EBT, 2356 CXEVNT_ENULL, 2357 CXEVNT_DRV_WLK, 2358 CXEVNT_BCN_OK, 2359 CXEVNT_BT_CHANGE, 2360 CXEVNT_EBT_EXTEND, 2361 CXEVNT_E2G_NULL1, 2362 CXEVNT_B1FDD_TMR, 2363 CXEVNT_MAX 2364 }; 2365 2366 enum { 2367 CXBCN_ALL = 0x0, 2368 CXBCN_ALL_OK, 2369 CXBCN_BT_SLOT, 2370 CXBCN_BT_OK, 2371 CXBCN_MAX 2372 }; 2373 2374 enum btc_slot_type { 2375 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2376 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2377 CXSTYPE_NUM, 2378 }; 2379 2380 enum { /* TIME */ 2381 CXT_BT = 0x0, 2382 CXT_WL = 0x1, 2383 CXT_MAX 2384 }; 2385 2386 enum { /* TIME-A2DP */ 2387 CXT_FLCTRL_OFF = 0x0, 2388 CXT_FLCTRL_ON = 0x1, 2389 CXT_FLCTRL_MAX 2390 }; 2391 2392 enum { /* STEP TYPE */ 2393 CXSTEP_NONE = 0x0, 2394 CXSTEP_EVNT = 0x1, 2395 CXSTEP_SLOT = 0x2, 2396 CXSTEP_MAX, 2397 }; 2398 2399 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2400 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2401 RPT_BT_AFH_SEQ_LE = 0x20 2402 }; 2403 2404 #define BTC_DBG_MAX1 32 2405 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2406 u8 fver; /* btc_ver::fcxgpiodbg */ 2407 u8 rsvd; 2408 __le16 rsvd2; 2409 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2410 __le32 pre_state; /* the debug signal is 1 or 0 */ 2411 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2412 } __packed; 2413 2414 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2415 u8 fver; 2416 u8 rsvd0; 2417 u8 rsvd1; 2418 u8 rsvd2; 2419 2420 u8 gpio_map[BTC_DBG_MAX1]; 2421 2422 __le32 en_map; 2423 __le32 pre_state; 2424 } __packed; 2425 2426 union rtw89_btc_fbtc_gpio_dbg { 2427 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2428 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2429 }; 2430 2431 struct rtw89_btc_fbtc_mreg_val_v1 { 2432 u8 fver; /* btc_ver::fcxmreg */ 2433 u8 reg_num; 2434 __le16 rsvd; 2435 __le32 mreg_val[CXMREG_MAX]; 2436 } __packed; 2437 2438 struct rtw89_btc_fbtc_mreg_val_v2 { 2439 u8 fver; /* btc_ver::fcxmreg */ 2440 u8 reg_num; 2441 __le16 rsvd; 2442 __le32 mreg_val[CXMREG_MAX_V2]; 2443 } __packed; 2444 2445 struct rtw89_btc_fbtc_mreg_val_v7 { 2446 u8 fver; 2447 u8 reg_num; 2448 u8 rsvd0; 2449 u8 rsvd1; 2450 __le32 mreg_val[CXMREG_MAX_V2]; 2451 } __packed; 2452 2453 union rtw89_btc_fbtc_mreg_val { 2454 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2455 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2456 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2457 }; 2458 2459 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2460 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2461 .offset = cpu_to_le32(__offset), } 2462 2463 struct rtw89_btc_fbtc_mreg { 2464 __le16 type; 2465 __le16 bytes; 2466 __le32 offset; 2467 } __packed; 2468 2469 struct rtw89_btc_fbtc_slot { 2470 __le16 dur; 2471 __le32 cxtbl; 2472 __le16 cxtype; 2473 } __packed; 2474 2475 struct rtw89_btc_fbtc_slots { 2476 u8 fver; /* btc_ver::fcxslots */ 2477 u8 tbl_num; 2478 __le16 rsvd; 2479 __le32 update_map; 2480 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2481 } __packed; 2482 2483 struct rtw89_btc_fbtc_slot_v7 { 2484 __le16 dur; /* slot duration */ 2485 __le16 cxtype; 2486 __le32 cxtbl; 2487 } __packed; 2488 2489 struct rtw89_btc_fbtc_slot_u16 { 2490 __le16 dur; /* slot duration */ 2491 __le16 cxtype; 2492 __le16 cxtbl_l16; /* coex table [15:0] */ 2493 __le16 cxtbl_h16; /* coex table [31:16] */ 2494 } __packed; 2495 2496 struct rtw89_btc_fbtc_1slot_v7 { 2497 u8 fver; 2498 u8 sid; /* slot id */ 2499 __le16 rsvd; 2500 struct rtw89_btc_fbtc_slot_v7 slot; 2501 } __packed; 2502 2503 struct rtw89_btc_fbtc_slots_v7 { 2504 u8 fver; 2505 u8 slot_cnt; 2506 u8 rsvd0; 2507 u8 rsvd1; 2508 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2509 __le32 update_map; 2510 } __packed; 2511 2512 union rtw89_btc_fbtc_slots_info { 2513 struct rtw89_btc_fbtc_slots v1; 2514 struct rtw89_btc_fbtc_slots_v7 v7; 2515 } __packed; 2516 2517 struct rtw89_btc_fbtc_step { 2518 u8 type; 2519 u8 val; 2520 __le16 difft; 2521 } __packed; 2522 2523 struct rtw89_btc_fbtc_steps_v2 { 2524 u8 fver; /* btc_ver::fcxstep */ 2525 u8 rsvd; 2526 __le16 cnt; 2527 __le16 pos_old; 2528 __le16 pos_new; 2529 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2530 } __packed; 2531 2532 struct rtw89_btc_fbtc_steps_v3 { 2533 u8 fver; 2534 u8 en; 2535 __le16 rsvd; 2536 __le32 cnt; 2537 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2538 } __packed; 2539 2540 union rtw89_btc_fbtc_steps_info { 2541 struct rtw89_btc_fbtc_steps_v2 v2; 2542 struct rtw89_btc_fbtc_steps_v3 v3; 2543 }; 2544 2545 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2546 u8 fver; /* btc_ver::fcxcysta */ 2547 u8 rsvd; 2548 __le16 cycles; /* total cycle number */ 2549 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2550 __le16 a2dpept; /* a2dp empty cnt */ 2551 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2552 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2553 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2554 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2555 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2556 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2557 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2558 __le16 tmax_a2dpept; /* max a2dp empty time */ 2559 __le16 tavg_lk; /* avg leak-slot time */ 2560 __le16 tmax_lk; /* max leak-slot time */ 2561 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2562 __le32 bcn_cnt[CXBCN_MAX]; 2563 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2564 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2565 __le32 skip_cnt; 2566 __le32 exception; 2567 __le32 except_cnt; 2568 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2569 } __packed; 2570 2571 struct rtw89_btc_fbtc_fdd_try_info { 2572 __le16 cycles[CXT_FLCTRL_MAX]; 2573 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2574 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2575 } __packed; 2576 2577 struct rtw89_btc_fbtc_cycle_time_info { 2578 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2579 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2580 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2581 } __packed; 2582 2583 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2584 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2585 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2586 } __packed; 2587 2588 struct rtw89_btc_fbtc_a2dp_trx_stat { 2589 u8 empty_cnt; 2590 u8 retry_cnt; 2591 u8 tx_rate; 2592 u8 tx_cnt; 2593 u8 ack_cnt; 2594 u8 nack_cnt; 2595 u8 rsvd1; 2596 u8 rsvd2; 2597 } __packed; 2598 2599 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2600 u8 empty_cnt; 2601 u8 retry_cnt; 2602 u8 tx_rate; 2603 u8 tx_cnt; 2604 u8 ack_cnt; 2605 u8 nack_cnt; 2606 u8 no_empty_cnt; 2607 u8 rsvd; 2608 } __packed; 2609 2610 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2611 __le16 cnt; /* a2dp empty cnt */ 2612 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2613 __le16 tavg; /* avg a2dp empty time */ 2614 __le16 tmax; /* max a2dp empty time */ 2615 } __packed; 2616 2617 struct rtw89_btc_fbtc_cycle_leak_info { 2618 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2619 __le16 tavg; /* avg leak-slot time */ 2620 __le16 tmax; /* max leak-slot time */ 2621 } __packed; 2622 2623 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2624 __le16 tavg; 2625 __le16 tamx; 2626 __le32 cnt_rximr; 2627 } __packed; 2628 2629 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2630 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2631 2632 struct rtw89_btc_fbtc_cycle_fddt_info { 2633 __le16 train_cycle; 2634 __le16 tp; 2635 2636 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2637 s8 bt_tx_power; /* decrease Tx power (dB) */ 2638 s8 bt_rx_gain; /* LNA constrain level */ 2639 u8 no_empty_cnt; 2640 2641 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2642 u8 cn; /* condition_num */ 2643 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2644 u8 train_result; /* refer to enum btc_fddt_check_map */ 2645 } __packed; 2646 2647 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2648 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2649 2650 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2651 __le16 train_cycle; 2652 __le16 tp; 2653 2654 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2655 s8 bt_tx_power; /* decrease Tx power (dB) */ 2656 s8 bt_rx_gain; /* LNA constrain level */ 2657 u8 no_empty_cnt; 2658 2659 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2660 u8 cn; /* condition_num */ 2661 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2662 u8 train_result; /* refer to enum btc_fddt_check_map */ 2663 } __packed; 2664 2665 struct rtw89_btc_fbtc_fddt_cell_status { 2666 s8 wl_tx_pwr; 2667 s8 bt_tx_pwr; 2668 s8 bt_rx_gain; 2669 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2670 } __packed; 2671 2672 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2673 u8 fver; 2674 u8 rsvd; 2675 __le16 cycles; /* total cycle number */ 2676 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2677 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2678 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2679 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2680 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2681 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2682 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2683 __le32 bcn_cnt[CXBCN_MAX]; 2684 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2685 __le32 skip_cnt; 2686 __le32 except_cnt; 2687 __le32 except_map; 2688 } __packed; 2689 2690 #define FDD_TRAIN_WL_DIRECTION 2 2691 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2692 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2693 2694 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2695 u8 fver; 2696 u8 rsvd; 2697 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2698 u8 except_cnt; 2699 2700 __le16 skip_cnt; 2701 __le16 cycles; /* total cycle number */ 2702 2703 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2704 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2705 __le16 bcn_cnt[CXBCN_MAX]; 2706 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2707 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2708 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2709 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2710 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2711 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2712 [FDD_TRAIN_WL_RSSI_LEVEL] 2713 [FDD_TRAIN_BT_RSSI_LEVEL]; 2714 __le32 except_map; 2715 } __packed; 2716 2717 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2718 u8 fver; 2719 u8 rsvd; 2720 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2721 u8 except_cnt; 2722 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2723 2724 __le16 skip_cnt; 2725 __le16 cycles; /* total cycle number */ 2726 2727 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2728 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2729 __le16 bcn_cnt[CXBCN_MAX]; 2730 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2731 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2732 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2733 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2734 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2735 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2736 [FDD_TRAIN_WL_RSSI_LEVEL] 2737 [FDD_TRAIN_BT_RSSI_LEVEL]; 2738 __le32 except_map; 2739 } __packed; 2740 2741 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2742 u8 fver; 2743 u8 rsvd; 2744 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2745 u8 except_cnt; 2746 2747 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2748 2749 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2750 2751 __le16 skip_cnt; 2752 __le16 cycles; /* total cycle number */ 2753 2754 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2755 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2756 __le16 bcn_cnt[CXBCN_MAX]; 2757 2758 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2759 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2760 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2761 2762 __le32 except_map; 2763 } __packed; 2764 2765 union rtw89_btc_fbtc_cysta_info { 2766 struct rtw89_btc_fbtc_cysta_v2 v2; 2767 struct rtw89_btc_fbtc_cysta_v3 v3; 2768 struct rtw89_btc_fbtc_cysta_v4 v4; 2769 struct rtw89_btc_fbtc_cysta_v5 v5; 2770 struct rtw89_btc_fbtc_cysta_v7 v7; 2771 }; 2772 2773 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2774 u8 fver; /* btc_ver::fcxnullsta */ 2775 u8 rsvd; 2776 __le16 rsvd2; 2777 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2778 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2779 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2780 } __packed; 2781 2782 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2783 u8 fver; /* btc_ver::fcxnullsta */ 2784 u8 rsvd; 2785 __le16 rsvd2; 2786 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2787 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2788 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2789 } __packed; 2790 2791 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2792 u8 fver; 2793 u8 rsvd0; 2794 u8 rsvd1; 2795 u8 rsvd2; 2796 2797 __le32 tmax[2]; 2798 __le32 tavg[2]; 2799 __le32 result[2][5]; 2800 } __packed; 2801 2802 union rtw89_btc_fbtc_cynullsta_info { 2803 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2804 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2805 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2806 }; 2807 2808 struct rtw89_btc_fbtc_btver_v1 { 2809 u8 fver; /* btc_ver::fcxbtver */ 2810 u8 rsvd; 2811 __le16 rsvd2; 2812 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2813 __le32 fw_ver; 2814 __le32 feature; 2815 } __packed; 2816 2817 struct rtw89_btc_fbtc_btver_v7 { 2818 u8 fver; 2819 u8 rsvd0; 2820 u8 rsvd1; 2821 u8 rsvd2; 2822 2823 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2824 __le32 fw_ver; 2825 __le32 feature; 2826 } __packed; 2827 2828 union rtw89_btc_fbtc_btver { 2829 struct rtw89_btc_fbtc_btver_v1 v1; 2830 struct rtw89_btc_fbtc_btver_v7 v7; 2831 } __packed; 2832 2833 struct rtw89_btc_fbtc_btafh { 2834 u8 fver; /* btc_ver::fcxbtafh */ 2835 u8 rsvd; 2836 __le16 rsvd2; 2837 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2838 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2839 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2840 } __packed; 2841 2842 struct rtw89_btc_fbtc_btafh_v2 { 2843 u8 fver; /* btc_ver::fcxbtafh */ 2844 u8 rsvd; 2845 u8 rsvd2; 2846 u8 map_type; 2847 u8 afh_l[4]; 2848 u8 afh_m[4]; 2849 u8 afh_h[4]; 2850 u8 afh_le_a[4]; 2851 u8 afh_le_b[4]; 2852 } __packed; 2853 2854 struct rtw89_btc_fbtc_btafh_v7 { 2855 u8 fver; 2856 u8 map_type; 2857 u8 rsvd0; 2858 u8 rsvd1; 2859 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2860 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2861 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2862 u8 afh_le_a[4]; 2863 u8 afh_le_b[4]; 2864 } __packed; 2865 2866 struct rtw89_btc_fbtc_btdevinfo { 2867 u8 fver; /* btc_ver::fcxbtdevinfo */ 2868 u8 rsvd; 2869 __le16 vendor_id; 2870 __le32 dev_name; /* only 24 bits valid */ 2871 __le32 flush_time; 2872 } __packed; 2873 2874 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2875 struct rtw89_btc_rf_trx_para { 2876 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2877 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2878 u8 bt_tx_power; /* decrease Tx power (dB) */ 2879 u8 bt_rx_gain; /* LNA constrain level */ 2880 }; 2881 2882 struct rtw89_btc_trx_info { 2883 u8 tx_lvl; 2884 u8 rx_lvl; 2885 u8 wl_rssi; 2886 u8 bt_rssi; 2887 2888 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2889 s8 rx_gain; /* rx gain table index (TBD.) */ 2890 s8 bt_tx_power; /* decrease Tx power (dB) */ 2891 s8 bt_rx_gain; /* LNA constrain level */ 2892 2893 u8 cn; /* condition_num */ 2894 s8 nhm; 2895 u8 bt_profile; 2896 u8 rsvd2; 2897 2898 u16 tx_rate; 2899 u16 rx_rate; 2900 2901 u32 tx_tp; 2902 u32 rx_tp; 2903 u32 rx_err_ratio; 2904 }; 2905 2906 union rtw89_btc_fbtc_slot_u { 2907 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2908 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2909 }; 2910 2911 struct rtw89_btc_dm { 2912 union rtw89_btc_fbtc_slot_u slot; 2913 union rtw89_btc_fbtc_slot_u slot_now; 2914 struct rtw89_btc_fbtc_tdma tdma; 2915 struct rtw89_btc_fbtc_tdma tdma_now; 2916 struct rtw89_mac_ax_coex_gnt gnt; 2917 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2918 struct rtw89_btc_rf_trx_para rf_trx_para; 2919 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2920 struct rtw89_btc_dm_step dm_step; 2921 struct rtw89_btc_wl_scc_ctrl wl_scc; 2922 struct rtw89_btc_trx_info trx_info; 2923 union rtw89_btc_dm_error_map error; 2924 u32 cnt_dm[BTC_DCNT_NUM]; 2925 u32 cnt_notify[BTC_NCNT_NUM]; 2926 2927 u32 update_slot_map; 2928 u32 set_ant_path; 2929 u32 e2g_slot_limit; 2930 u32 e2g_slot_nulltx_time; 2931 2932 u32 wl_only: 1; 2933 u32 wl_fw_cx_offload: 1; 2934 u32 freerun: 1; 2935 u32 fddt_train: 1; 2936 u32 wl_ps_ctrl: 2; 2937 u32 wl_mimo_ps: 1; 2938 u32 leak_ap: 1; 2939 u32 noisy_level: 3; 2940 u32 coex_info_map: 8; 2941 u32 bt_only: 1; 2942 u32 wl_btg_rx: 2; 2943 u32 trx_para_level: 8; 2944 u32 wl_stb_chg: 1; 2945 u32 pta_owner: 1; 2946 2947 u32 tdma_instant_excute: 1; 2948 u32 wl_btg_rx_rb: 2; 2949 2950 u16 slot_dur[CXST_MAX]; 2951 u16 bt_slot_flood; 2952 2953 u8 run_reason; 2954 u8 run_action; 2955 2956 u8 wl_pre_agc: 2; 2957 u8 wl_lna2: 1; 2958 u8 freerun_chk: 1; 2959 u8 wl_pre_agc_rb: 2; 2960 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 2961 u8 slot_req_more: 1; 2962 }; 2963 2964 struct rtw89_btc_ctrl { 2965 u32 manual: 1; 2966 u32 igno_bt: 1; 2967 u32 always_freerun: 1; 2968 u32 trace_step: 16; 2969 u32 rsvd: 12; 2970 }; 2971 2972 struct rtw89_btc_ctrl_v7 { 2973 u8 manual; 2974 u8 igno_bt; 2975 u8 always_freerun; 2976 u8 rsvd; 2977 } __packed; 2978 2979 union rtw89_btc_ctrl_list { 2980 struct rtw89_btc_ctrl ctrl; 2981 struct rtw89_btc_ctrl_v7 ctrl_v7; 2982 }; 2983 2984 struct rtw89_btc_dbg { 2985 /* cmd "rb" */ 2986 bool rb_done; 2987 u32 rb_val; 2988 }; 2989 2990 enum rtw89_btc_btf_fw_event { 2991 BTF_EVNT_RPT = 0, 2992 BTF_EVNT_BT_INFO = 1, 2993 BTF_EVNT_BT_SCBD = 2, 2994 BTF_EVNT_BT_REG = 3, 2995 BTF_EVNT_CX_RUNINFO = 4, 2996 BTF_EVNT_BT_PSD = 5, 2997 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 2998 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 2999 BTF_EVNT_BUF_OVERFLOW, 3000 BTF_EVNT_C2H_LOOPBACK, 3001 BTF_EVNT_MAX, 3002 }; 3003 3004 enum btf_fw_event_report { 3005 BTC_RPT_TYPE_CTRL = 0x0, 3006 BTC_RPT_TYPE_TDMA, 3007 BTC_RPT_TYPE_SLOT, 3008 BTC_RPT_TYPE_CYSTA, 3009 BTC_RPT_TYPE_STEP, 3010 BTC_RPT_TYPE_NULLSTA, 3011 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 3012 BTC_RPT_TYPE_MREG, 3013 BTC_RPT_TYPE_GPIO_DBG, 3014 BTC_RPT_TYPE_BT_VER, 3015 BTC_RPT_TYPE_BT_SCAN, 3016 BTC_RPT_TYPE_BT_AFH, 3017 BTC_RPT_TYPE_BT_DEVICE, 3018 BTC_RPT_TYPE_TEST, 3019 BTC_RPT_TYPE_MAX = 31, 3020 3021 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 3022 __BTC_RPT_TYPE_V0_MAX = 12, 3023 }; 3024 3025 enum rtw_btc_btf_reg_type { 3026 REG_MAC = 0x0, 3027 REG_BB = 0x1, 3028 REG_RF = 0x2, 3029 REG_BT_RF = 0x3, 3030 REG_BT_MODEM = 0x4, 3031 REG_BT_BLUEWIZE = 0x5, 3032 REG_BT_VENDOR = 0x6, 3033 REG_BT_LE = 0x7, 3034 REG_MAX_TYPE, 3035 }; 3036 3037 struct rtw89_btc_rpt_cmn_info { 3038 u32 rx_cnt; 3039 u32 rx_len; 3040 u32 req_len; /* expected rsp len */ 3041 u8 req_fver; /* expected rsp fver */ 3042 u8 rsp_fver; /* fver from fw */ 3043 u8 valid; 3044 } __packed; 3045 3046 union rtw89_btc_fbtc_btafh_info { 3047 struct rtw89_btc_fbtc_btafh v1; 3048 struct rtw89_btc_fbtc_btafh_v2 v2; 3049 }; 3050 3051 struct rtw89_btc_report_ctrl_state { 3052 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3053 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 3054 }; 3055 3056 struct rtw89_btc_rpt_fbtc_tdma { 3057 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3058 union rtw89_btc_fbtc_tdma_le32 finfo; 3059 }; 3060 3061 struct rtw89_btc_rpt_fbtc_slots { 3062 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3063 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 3064 }; 3065 3066 struct rtw89_btc_rpt_fbtc_cysta { 3067 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3068 union rtw89_btc_fbtc_cysta_info finfo; 3069 }; 3070 3071 struct rtw89_btc_rpt_fbtc_step { 3072 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3073 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 3074 }; 3075 3076 struct rtw89_btc_rpt_fbtc_nullsta { 3077 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3078 union rtw89_btc_fbtc_cynullsta_info finfo; 3079 }; 3080 3081 struct rtw89_btc_rpt_fbtc_mreg { 3082 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3083 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3084 }; 3085 3086 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3087 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3088 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3089 }; 3090 3091 struct rtw89_btc_rpt_fbtc_btver { 3092 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3093 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3094 }; 3095 3096 struct rtw89_btc_rpt_fbtc_btscan { 3097 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3098 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3099 }; 3100 3101 struct rtw89_btc_rpt_fbtc_btafh { 3102 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3103 union rtw89_btc_fbtc_btafh_info finfo; 3104 }; 3105 3106 struct rtw89_btc_rpt_fbtc_btdev { 3107 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3108 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3109 }; 3110 3111 enum rtw89_btc_btfre_type { 3112 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3113 BTFRE_UNDEF_TYPE, 3114 BTFRE_EXCEPTION, 3115 BTFRE_MAX, 3116 }; 3117 3118 struct rtw89_btc_btf_fwinfo { 3119 u32 cnt_c2h; 3120 u32 cnt_h2c; 3121 u32 cnt_h2c_fail; 3122 u32 event[BTF_EVNT_MAX]; 3123 3124 u32 err[BTFRE_MAX]; 3125 u32 len_mismch; 3126 u32 fver_mismch; 3127 u32 rpt_en_map; 3128 3129 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3130 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3131 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3132 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3133 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3134 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3135 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3136 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3137 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3138 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3139 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3140 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3141 }; 3142 3143 struct rtw89_btc_ver { 3144 enum rtw89_core_chip_id chip_id; 3145 u32 fw_ver_code; 3146 3147 u8 fcxbtcrpt; 3148 u8 fcxtdma; 3149 u8 fcxslots; 3150 u8 fcxcysta; 3151 u8 fcxstep; 3152 u8 fcxnullsta; 3153 u8 fcxmreg; 3154 u8 fcxgpiodbg; 3155 u8 fcxbtver; 3156 u8 fcxbtscan; 3157 u8 fcxbtafh; 3158 u8 fcxbtdevinfo; 3159 u8 fwlrole; 3160 u8 frptmap; 3161 u8 fcxctrl; 3162 u8 fcxinit; 3163 3164 u8 fwevntrptl; 3165 u8 fwc2hfunc; 3166 u8 drvinfo_type; 3167 u16 info_buf; 3168 u8 max_role_num; 3169 }; 3170 3171 #define RTW89_BTC_POLICY_MAXLEN 512 3172 3173 struct rtw89_btc { 3174 const struct rtw89_btc_ver *ver; 3175 3176 struct rtw89_btc_cx cx; 3177 struct rtw89_btc_dm dm; 3178 union rtw89_btc_ctrl_list ctrl; 3179 union rtw89_btc_module_info mdinfo; 3180 struct rtw89_btc_btf_fwinfo fwinfo; 3181 struct rtw89_btc_dbg dbg; 3182 3183 struct work_struct eapol_notify_work; 3184 struct work_struct arp_notify_work; 3185 struct work_struct dhcp_notify_work; 3186 struct work_struct icmp_notify_work; 3187 3188 u32 bt_req_len; 3189 3190 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3191 u8 ant_type; 3192 u8 btg_pos; 3193 u16 policy_len; 3194 u16 policy_type; 3195 u32 hubmsg_cnt; 3196 bool bt_req_en; 3197 bool update_policy_force; 3198 bool lps; 3199 bool manual_ctrl; 3200 }; 3201 3202 enum rtw89_btc_hmsg { 3203 RTW89_BTC_HMSG_TMR_EN = 0x0, 3204 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3205 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3206 RTW89_BTC_HMSG_FW_EV = 0x3, 3207 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3208 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3209 3210 NUM_OF_RTW89_BTC_HMSG, 3211 }; 3212 3213 enum rtw89_ra_mode { 3214 RTW89_RA_MODE_CCK = BIT(0), 3215 RTW89_RA_MODE_OFDM = BIT(1), 3216 RTW89_RA_MODE_HT = BIT(2), 3217 RTW89_RA_MODE_VHT = BIT(3), 3218 RTW89_RA_MODE_HE = BIT(4), 3219 RTW89_RA_MODE_EHT = BIT(5), 3220 }; 3221 3222 enum rtw89_ra_report_mode { 3223 RTW89_RA_RPT_MODE_LEGACY, 3224 RTW89_RA_RPT_MODE_HT, 3225 RTW89_RA_RPT_MODE_VHT, 3226 RTW89_RA_RPT_MODE_HE, 3227 RTW89_RA_RPT_MODE_EHT, 3228 }; 3229 3230 enum rtw89_dig_noisy_level { 3231 RTW89_DIG_NOISY_LEVEL0 = -1, 3232 RTW89_DIG_NOISY_LEVEL1 = 0, 3233 RTW89_DIG_NOISY_LEVEL2 = 1, 3234 RTW89_DIG_NOISY_LEVEL3 = 2, 3235 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3236 }; 3237 3238 enum rtw89_gi_ltf { 3239 RTW89_GILTF_LGI_4XHE32 = 0, 3240 RTW89_GILTF_SGI_4XHE08 = 1, 3241 RTW89_GILTF_2XHE16 = 2, 3242 RTW89_GILTF_2XHE08 = 3, 3243 RTW89_GILTF_1XHE16 = 4, 3244 RTW89_GILTF_1XHE08 = 5, 3245 RTW89_GILTF_MAX 3246 }; 3247 3248 enum rtw89_rx_frame_type { 3249 RTW89_RX_TYPE_MGNT = 0, 3250 RTW89_RX_TYPE_CTRL = 1, 3251 RTW89_RX_TYPE_DATA = 2, 3252 RTW89_RX_TYPE_RSVD = 3, 3253 }; 3254 3255 enum rtw89_efuse_block { 3256 RTW89_EFUSE_BLOCK_SYS = 0, 3257 RTW89_EFUSE_BLOCK_RF = 1, 3258 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3259 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3260 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3261 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3262 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3263 RTW89_EFUSE_BLOCK_ADIE = 7, 3264 3265 RTW89_EFUSE_BLOCK_NUM, 3266 RTW89_EFUSE_BLOCK_IGNORE, 3267 }; 3268 3269 struct rtw89_ra_info { 3270 u8 is_dis_ra:1; 3271 /* Bit0 : CCK 3272 * Bit1 : OFDM 3273 * Bit2 : HT 3274 * Bit3 : VHT 3275 * Bit4 : HE 3276 * Bit5 : EHT 3277 */ 3278 u8 mode_ctrl:6; 3279 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3280 u8 macid; 3281 u8 dcm_cap:1; 3282 u8 er_cap:1; 3283 u8 init_rate_lv:2; 3284 u8 upd_all:1; 3285 u8 en_sgi:1; 3286 u8 ldpc_cap:1; 3287 u8 stbc_cap:1; 3288 u8 ss_num:3; 3289 u8 giltf:3; 3290 u8 upd_bw_nss_mask:1; 3291 u8 upd_mask:1; 3292 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3293 /* BFee CSI */ 3294 u8 band_num; 3295 u8 ra_csi_rate_en:1; 3296 u8 fixed_csi_rate_en:1; 3297 u8 cr_tbl_sel:1; 3298 u8 fix_giltf_en:1; 3299 u8 fix_giltf:3; 3300 u8 rsvd2:1; 3301 u8 csi_mcs_ss_idx; 3302 u8 csi_mode:2; 3303 u8 csi_gi_ltf:3; 3304 u8 csi_bw:3; 3305 }; 3306 3307 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3308 #define RTW89_PPDU_MAC_INFO_SIZE 8 3309 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3310 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3311 3312 #define RTW89_MAX_RX_AGG_NUM 64 3313 #define RTW89_MAX_TX_AGG_NUM 128 3314 3315 struct rtw89_ampdu_params { 3316 u16 agg_num; 3317 bool amsdu; 3318 }; 3319 3320 struct rtw89_ra_report { 3321 struct rate_info txrate; 3322 u32 bit_rate; 3323 u16 hw_rate; 3324 bool might_fallback_legacy; 3325 }; 3326 3327 DECLARE_EWMA(rssi, 10, 16); 3328 DECLARE_EWMA(evm, 10, 16); 3329 DECLARE_EWMA(snr, 10, 16); 3330 3331 struct rtw89_ba_cam_entry { 3332 struct list_head list; 3333 u8 tid; 3334 }; 3335 3336 #define RTW89_MAX_ADDR_CAM_NUM 128 3337 #define RTW89_MAX_BSSID_CAM_NUM 20 3338 #define RTW89_MAX_SEC_CAM_NUM 128 3339 #define RTW89_MAX_BA_CAM_NUM 24 3340 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3341 3342 struct rtw89_addr_cam_entry { 3343 u8 addr_cam_idx; 3344 u8 offset; 3345 u8 len; 3346 u8 valid : 1; 3347 u8 addr_mask : 6; 3348 u8 wapi : 1; 3349 u8 mask_sel : 2; 3350 u8 bssid_cam_idx: 6; 3351 3352 u8 sec_ent_mode; 3353 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3354 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3355 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3356 }; 3357 3358 struct rtw89_bssid_cam_entry { 3359 u8 bssid[ETH_ALEN]; 3360 u8 phy_idx; 3361 u8 bssid_cam_idx; 3362 u8 offset; 3363 u8 len; 3364 u8 valid : 1; 3365 u8 num; 3366 }; 3367 3368 struct rtw89_sec_cam_entry { 3369 u8 sec_cam_idx; 3370 u8 offset; 3371 u8 len; 3372 u8 type : 4; 3373 u8 ext_key : 1; 3374 u8 spp_mode : 1; 3375 /* 256 bits */ 3376 u8 key[32]; 3377 3378 struct ieee80211_key_conf *key_conf; 3379 }; 3380 3381 struct rtw89_sta_link { 3382 struct rtw89_sta *rtwsta; 3383 unsigned int link_id; 3384 3385 u8 mac_id; 3386 bool er_cap; 3387 struct rtw89_vif_link *rtwvif_link; 3388 struct rtw89_ra_info ra; 3389 struct rtw89_ra_report ra_report; 3390 int max_agg_wait; 3391 u8 prev_rssi; 3392 struct ewma_rssi avg_rssi; 3393 struct ewma_rssi rssi[RF_PATH_MAX]; 3394 struct ewma_snr avg_snr; 3395 struct ewma_evm evm_1ss; 3396 struct ewma_evm evm_min[RF_PATH_MAX]; 3397 struct ewma_evm evm_max[RF_PATH_MAX]; 3398 struct ieee80211_rx_status rx_status; 3399 u16 rx_hw_rate; 3400 __le32 htc_template; 3401 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3402 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3403 struct list_head ba_cam_list; 3404 3405 bool use_cfg_mask; 3406 struct cfg80211_bitrate_mask mask; 3407 3408 bool cctl_tx_time; 3409 u32 ampdu_max_time:4; 3410 bool cctl_tx_retry_limit; 3411 u32 data_tx_cnt_lmt:6; 3412 }; 3413 3414 struct rtw89_efuse { 3415 bool valid; 3416 bool power_k_valid; 3417 u8 xtal_cap; 3418 u8 addr[ETH_ALEN]; 3419 u8 rfe_type; 3420 char country_code[2]; 3421 }; 3422 3423 struct rtw89_phy_rate_pattern { 3424 u64 ra_mask; 3425 u16 rate; 3426 u8 ra_mode; 3427 bool enable; 3428 }; 3429 3430 struct rtw89_tx_wait_info { 3431 struct rcu_head rcu_head; 3432 struct completion completion; 3433 bool tx_done; 3434 }; 3435 3436 struct rtw89_tx_skb_data { 3437 struct rtw89_tx_wait_info __rcu *wait; 3438 u8 hci_priv[]; 3439 }; 3440 3441 #define RTW89_ROC_IDLE_TIMEOUT 500 3442 #define RTW89_ROC_TX_TIMEOUT 30 3443 enum rtw89_roc_state { 3444 RTW89_ROC_IDLE, 3445 RTW89_ROC_NORMAL, 3446 RTW89_ROC_MGMT, 3447 }; 3448 3449 #define RTW89_ROC_BY_LINK_INDEX 0 3450 3451 struct rtw89_roc { 3452 struct ieee80211_channel chan; 3453 struct delayed_work roc_work; 3454 enum ieee80211_roc_type type; 3455 enum rtw89_roc_state state; 3456 int duration; 3457 }; 3458 3459 #define RTW89_P2P_MAX_NOA_NUM 2 3460 3461 struct rtw89_p2p_ie_head { 3462 u8 eid; 3463 u8 ie_len; 3464 u8 oui[3]; 3465 u8 oui_type; 3466 } __packed; 3467 3468 struct rtw89_noa_attr_head { 3469 u8 attr_type; 3470 __le16 attr_len; 3471 u8 index; 3472 u8 oppps_ctwindow; 3473 } __packed; 3474 3475 struct rtw89_p2p_noa_ie { 3476 struct rtw89_p2p_ie_head p2p_head; 3477 struct rtw89_noa_attr_head noa_head; 3478 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3479 } __packed; 3480 3481 struct rtw89_p2p_noa_setter { 3482 struct rtw89_p2p_noa_ie ie; 3483 u8 noa_count; 3484 u8 noa_index; 3485 }; 3486 3487 struct rtw89_vif_link { 3488 struct rtw89_vif *rtwvif; 3489 unsigned int link_id; 3490 3491 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3492 enum rtw89_chanctx_idx chanctx_idx; 3493 enum rtw89_reg_6ghz_power reg_6ghz_power; 3494 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3495 3496 u8 mac_id; 3497 u8 port; 3498 u8 mac_addr[ETH_ALEN]; 3499 u8 bssid[ETH_ALEN]; 3500 u8 phy_idx; 3501 u8 mac_idx; 3502 u8 net_type; 3503 u8 wifi_role; 3504 u8 self_role; 3505 u8 wmm; 3506 u8 bcn_hit_cond; 3507 u8 hit_rule; 3508 u8 last_noa_nr; 3509 u64 sync_bcn_tsf; 3510 bool trigger; 3511 bool lsig_txop; 3512 u8 tgt_ind; 3513 u8 frm_tgt_ind; 3514 bool wowlan_pattern; 3515 bool wowlan_uc; 3516 bool wowlan_magic; 3517 bool is_hesta; 3518 bool last_a_ctrl; 3519 bool dyn_tb_bedge_en; 3520 bool pre_pwr_diff_en; 3521 bool pwr_diff_en; 3522 u8 def_tri_idx; 3523 struct work_struct update_beacon_work; 3524 struct rtw89_addr_cam_entry addr_cam; 3525 struct rtw89_bssid_cam_entry bssid_cam; 3526 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3527 struct rtw89_phy_rate_pattern rate_pattern; 3528 struct list_head general_pkt_list; 3529 struct rtw89_p2p_noa_setter p2p_noa; 3530 }; 3531 3532 enum rtw89_lv1_rcvy_step { 3533 RTW89_LV1_RCVY_STEP_1, 3534 RTW89_LV1_RCVY_STEP_2, 3535 }; 3536 3537 struct rtw89_hci_ops { 3538 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3539 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3540 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3541 void (*reset)(struct rtw89_dev *rtwdev); 3542 int (*start)(struct rtw89_dev *rtwdev); 3543 void (*stop)(struct rtw89_dev *rtwdev); 3544 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3545 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3546 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3547 3548 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3549 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3550 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3551 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3552 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3553 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3554 3555 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3556 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3557 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3558 int (*deinit)(struct rtw89_dev *rtwdev); 3559 3560 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3561 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3562 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3563 int (*napi_poll)(struct napi_struct *napi, int budget); 3564 3565 /* Deal with locks inside recovery_start and recovery_complete callbacks 3566 * by hci instance, and handle things which need to consider under SER. 3567 * e.g. turn on/off interrupts except for the one for halt notification. 3568 */ 3569 void (*recovery_start)(struct rtw89_dev *rtwdev); 3570 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3571 3572 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3573 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3574 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3575 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3576 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3577 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3578 void (*disable_intr)(struct rtw89_dev *rtwdev); 3579 void (*enable_intr)(struct rtw89_dev *rtwdev); 3580 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3581 }; 3582 3583 struct rtw89_hci_info { 3584 const struct rtw89_hci_ops *ops; 3585 enum rtw89_hci_type type; 3586 u32 rpwm_addr; 3587 u32 cpwm_addr; 3588 bool paused; 3589 }; 3590 3591 struct rtw89_chip_ops { 3592 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3593 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3594 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3595 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3596 void (*bb_reset)(struct rtw89_dev *rtwdev, 3597 enum rtw89_phy_idx phy_idx); 3598 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3599 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3600 u32 addr, u32 mask); 3601 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3602 u32 addr, u32 mask, u32 data); 3603 void (*set_channel)(struct rtw89_dev *rtwdev, 3604 const struct rtw89_chan *chan, 3605 enum rtw89_mac_idx mac_idx, 3606 enum rtw89_phy_idx phy_idx); 3607 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3608 struct rtw89_channel_help_params *p, 3609 const struct rtw89_chan *chan, 3610 enum rtw89_mac_idx mac_idx, 3611 enum rtw89_phy_idx phy_idx); 3612 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3613 enum rtw89_efuse_block block); 3614 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3615 void (*fem_setup)(struct rtw89_dev *rtwdev); 3616 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3617 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3618 void (*rfk_init)(struct rtw89_dev *rtwdev); 3619 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3620 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 3621 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3622 enum rtw89_phy_idx phy_idx, 3623 const struct rtw89_chan *chan); 3624 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3625 bool start); 3626 void (*rfk_track)(struct rtw89_dev *rtwdev); 3627 void (*power_trim)(struct rtw89_dev *rtwdev); 3628 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3629 const struct rtw89_chan *chan, 3630 enum rtw89_phy_idx phy_idx); 3631 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3632 enum rtw89_phy_idx phy_idx); 3633 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3634 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3635 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3636 enum rtw89_phy_idx phy_idx); 3637 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3638 struct rtw89_rx_phy_ppdu *phy_ppdu, 3639 struct ieee80211_rx_status *status); 3640 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 3641 struct rtw89_rx_phy_ppdu *phy_ppdu); 3642 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev, 3643 struct rtw89_rx_desc_info *desc_info, 3644 struct ieee80211_rx_status *rx_status); 3645 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3646 enum rtw89_phy_idx phy_idx); 3647 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3648 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3649 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3650 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 3651 enum rtw89_phy_idx phy_idx); 3652 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3653 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3654 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3655 struct rtw89_rx_desc_info *desc_info, 3656 u8 *data, u32 data_offset); 3657 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3658 struct rtw89_tx_desc_info *desc_info, 3659 void *txdesc); 3660 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3661 struct rtw89_tx_desc_info *desc_info, 3662 void *txdesc); 3663 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3664 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3665 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3666 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3667 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3668 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3669 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3670 struct rtw89_vif_link *rtwvif_link, 3671 struct rtw89_sta_link *rtwsta_link); 3672 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3673 struct rtw89_vif_link *rtwvif_link, 3674 struct rtw89_sta_link *rtwsta_link); 3675 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3676 struct rtw89_vif_link *rtwvif_link, 3677 struct rtw89_sta_link *rtwsta_link); 3678 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3679 struct rtw89_vif_link *rtwvif_link, 3680 struct rtw89_sta_link *rtwsta_link); 3681 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3682 struct rtw89_vif_link *rtwvif_link, 3683 struct rtw89_sta_link *rtwsta_link); 3684 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3685 struct rtw89_vif_link *rtwvif_link); 3686 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, 3687 struct rtw89_vif_link *rtwvif_link, 3688 struct rtw89_sta_link *rtwsta_link, 3689 bool valid, struct ieee80211_ampdu_params *params); 3690 3691 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3692 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3693 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3694 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3695 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3696 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3697 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3698 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3699 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3700 }; 3701 3702 enum rtw89_dma_ch { 3703 RTW89_DMA_ACH0 = 0, 3704 RTW89_DMA_ACH1 = 1, 3705 RTW89_DMA_ACH2 = 2, 3706 RTW89_DMA_ACH3 = 3, 3707 RTW89_DMA_ACH4 = 4, 3708 RTW89_DMA_ACH5 = 5, 3709 RTW89_DMA_ACH6 = 6, 3710 RTW89_DMA_ACH7 = 7, 3711 RTW89_DMA_B0MG = 8, 3712 RTW89_DMA_B0HI = 9, 3713 RTW89_DMA_B1MG = 10, 3714 RTW89_DMA_B1HI = 11, 3715 RTW89_DMA_H2C = 12, 3716 RTW89_DMA_CH_NUM = 13 3717 }; 3718 3719 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3720 3721 enum rtw89_mlo_dbcc_mode { 3722 MLO_DBCC_NOT_SUPPORT = 1, 3723 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3724 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3725 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3726 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3727 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3728 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3729 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3730 DBCC_LEGACY = 0xffffffff, 3731 }; 3732 3733 enum rtw89_scan_be_operation { 3734 RTW89_SCAN_OP_STOP, 3735 RTW89_SCAN_OP_START, 3736 RTW89_SCAN_OP_SETPARM, 3737 RTW89_SCAN_OP_GETRPT, 3738 RTW89_SCAN_OP_NUM 3739 }; 3740 3741 enum rtw89_scan_be_mode { 3742 RTW89_SCAN_MODE_SA, 3743 RTW89_SCAN_MODE_MACC, 3744 RTW89_SCAN_MODE_NUM 3745 }; 3746 3747 enum rtw89_scan_be_opmode { 3748 RTW89_SCAN_OPMODE_NONE, 3749 RTW89_SCAN_OPMODE_TBTT, 3750 RTW89_SCAN_OPMODE_INTV, 3751 RTW89_SCAN_OPMODE_CNT, 3752 RTW89_SCAN_OPMODE_NUM, 3753 }; 3754 3755 struct rtw89_scan_option { 3756 bool enable; 3757 bool target_ch_mode; 3758 u8 num_macc_role; 3759 u8 num_opch; 3760 u8 repeat; 3761 u16 norm_pd; 3762 u16 slow_pd; 3763 u16 norm_cy; 3764 u8 opch_end; 3765 u16 delay; 3766 u64 prohib_chan; 3767 enum rtw89_phy_idx band; 3768 enum rtw89_scan_be_operation operation; 3769 enum rtw89_scan_be_mode scan_mode; 3770 enum rtw89_mlo_dbcc_mode mlo_mode; 3771 }; 3772 3773 enum rtw89_qta_mode { 3774 RTW89_QTA_SCC, 3775 RTW89_QTA_DBCC, 3776 RTW89_QTA_DLFW, 3777 RTW89_QTA_WOW, 3778 3779 /* keep last */ 3780 RTW89_QTA_INVALID, 3781 }; 3782 3783 struct rtw89_hfc_ch_cfg { 3784 u16 min; 3785 u16 max; 3786 #define grp_0 0 3787 #define grp_1 1 3788 #define grp_num 2 3789 u8 grp; 3790 }; 3791 3792 struct rtw89_hfc_ch_info { 3793 u16 aval; 3794 u16 used; 3795 }; 3796 3797 struct rtw89_hfc_pub_cfg { 3798 u16 grp0; 3799 u16 grp1; 3800 u16 pub_max; 3801 u16 wp_thrd; 3802 }; 3803 3804 struct rtw89_hfc_pub_info { 3805 u16 g0_used; 3806 u16 g1_used; 3807 u16 g0_aval; 3808 u16 g1_aval; 3809 u16 pub_aval; 3810 u16 wp_aval; 3811 }; 3812 3813 struct rtw89_hfc_prec_cfg { 3814 u16 ch011_prec; 3815 u16 h2c_prec; 3816 u16 wp_ch07_prec; 3817 u16 wp_ch811_prec; 3818 u8 ch011_full_cond; 3819 u8 h2c_full_cond; 3820 u8 wp_ch07_full_cond; 3821 u8 wp_ch811_full_cond; 3822 }; 3823 3824 struct rtw89_hfc_param { 3825 bool en; 3826 bool h2c_en; 3827 u8 mode; 3828 const struct rtw89_hfc_ch_cfg *ch_cfg; 3829 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3830 struct rtw89_hfc_pub_cfg pub_cfg; 3831 struct rtw89_hfc_pub_info pub_info; 3832 struct rtw89_hfc_prec_cfg prec_cfg; 3833 }; 3834 3835 struct rtw89_hfc_param_ini { 3836 const struct rtw89_hfc_ch_cfg *ch_cfg; 3837 const struct rtw89_hfc_pub_cfg *pub_cfg; 3838 const struct rtw89_hfc_prec_cfg *prec_cfg; 3839 u8 mode; 3840 }; 3841 3842 struct rtw89_dle_size { 3843 u16 pge_size; 3844 u16 lnk_pge_num; 3845 u16 unlnk_pge_num; 3846 /* for WiFi 7 chips below */ 3847 u32 srt_ofst; 3848 }; 3849 3850 struct rtw89_wde_quota { 3851 u16 hif; 3852 u16 wcpu; 3853 u16 pkt_in; 3854 u16 cpu_io; 3855 }; 3856 3857 struct rtw89_ple_quota { 3858 u16 cma0_tx; 3859 u16 cma1_tx; 3860 u16 c2h; 3861 u16 h2c; 3862 u16 wcpu; 3863 u16 mpdu_proc; 3864 u16 cma0_dma; 3865 u16 cma1_dma; 3866 u16 bb_rpt; 3867 u16 wd_rel; 3868 u16 cpu_io; 3869 u16 tx_rpt; 3870 /* for WiFi 7 chips below */ 3871 u16 h2d; 3872 }; 3873 3874 struct rtw89_rsvd_quota { 3875 u16 mpdu_info_tbl; 3876 u16 b0_csi; 3877 u16 b1_csi; 3878 u16 b0_lmr; 3879 u16 b1_lmr; 3880 u16 b0_ftm; 3881 u16 b1_ftm; 3882 u16 b0_smr; 3883 u16 b1_smr; 3884 u16 others; 3885 }; 3886 3887 struct rtw89_dle_rsvd_size { 3888 u32 srt_ofst; 3889 u32 size; 3890 }; 3891 3892 struct rtw89_dle_mem { 3893 enum rtw89_qta_mode mode; 3894 const struct rtw89_dle_size *wde_size; 3895 const struct rtw89_dle_size *ple_size; 3896 const struct rtw89_wde_quota *wde_min_qt; 3897 const struct rtw89_wde_quota *wde_max_qt; 3898 const struct rtw89_ple_quota *ple_min_qt; 3899 const struct rtw89_ple_quota *ple_max_qt; 3900 /* for WiFi 7 chips below */ 3901 const struct rtw89_rsvd_quota *rsvd_qt; 3902 const struct rtw89_dle_rsvd_size *rsvd0_size; 3903 const struct rtw89_dle_rsvd_size *rsvd1_size; 3904 }; 3905 3906 struct rtw89_reg_def { 3907 u32 addr; 3908 u32 mask; 3909 }; 3910 3911 struct rtw89_reg2_def { 3912 u32 addr; 3913 u32 data; 3914 }; 3915 3916 struct rtw89_reg3_def { 3917 u32 addr; 3918 u32 mask; 3919 u32 data; 3920 }; 3921 3922 struct rtw89_reg5_def { 3923 u8 flag; /* recognized by parsers */ 3924 u8 path; 3925 u32 addr; 3926 u32 mask; 3927 u32 data; 3928 }; 3929 3930 struct rtw89_reg_imr { 3931 u32 addr; 3932 u32 clr; 3933 u32 set; 3934 }; 3935 3936 struct rtw89_phy_table { 3937 const struct rtw89_reg2_def *regs; 3938 u32 n_regs; 3939 enum rtw89_rf_path rf_path; 3940 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3941 enum rtw89_rf_path rf_path, void *data); 3942 }; 3943 3944 struct rtw89_txpwr_table { 3945 const void *data; 3946 u32 size; 3947 void (*load)(struct rtw89_dev *rtwdev, 3948 const struct rtw89_txpwr_table *tbl); 3949 }; 3950 3951 struct rtw89_txpwr_rule_2ghz { 3952 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3953 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3954 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3955 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3956 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3957 }; 3958 3959 struct rtw89_txpwr_rule_5ghz { 3960 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3961 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3962 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3963 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3964 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3965 }; 3966 3967 struct rtw89_txpwr_rule_6ghz { 3968 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3969 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3970 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3971 [RTW89_6G_CH_NUM]; 3972 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3973 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3974 [RTW89_6G_CH_NUM]; 3975 }; 3976 3977 struct rtw89_tx_shape { 3978 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3979 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3980 }; 3981 3982 struct rtw89_rfe_parms { 3983 const struct rtw89_txpwr_table *byr_tbl; 3984 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3985 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3986 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3987 struct rtw89_tx_shape tx_shape; 3988 }; 3989 3990 struct rtw89_rfe_parms_conf { 3991 const struct rtw89_rfe_parms *rfe_parms; 3992 u8 rfe_type; 3993 }; 3994 3995 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3996 3997 struct rtw89_txpwr_conf { 3998 u8 rfe_type; 3999 u8 ent_sz; 4000 u32 num_ents; 4001 const void *data; 4002 }; 4003 4004 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 4005 const struct rtw89_txpwr_conf *conf) 4006 { 4007 u8 valid_size = min(size, conf->ent_sz); 4008 4009 memcpy(entry, cursor, valid_size); 4010 return true; 4011 } 4012 4013 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 4014 4015 #if defined(__linux__) 4016 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 4017 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 4018 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 4019 (cursor) += (conf)->ent_sz) \ 4020 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 4021 #elif defined(__FreeBSD__) 4022 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 4023 for (typecheck(const u8 *, cursor), (cursor) = (conf)->data, \ 4024 memcpy(&(entry), cursor, \ 4025 min_t(u8, sizeof(entry), (conf)->ent_sz)); \ 4026 (cursor) < (const u8 *)(conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 4027 (cursor) += (conf)->ent_sz) \ 4028 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 4029 #endif 4030 4031 struct rtw89_txpwr_byrate_data { 4032 struct rtw89_txpwr_conf conf; 4033 struct rtw89_txpwr_table tbl; 4034 }; 4035 4036 struct rtw89_txpwr_lmt_2ghz_data { 4037 struct rtw89_txpwr_conf conf; 4038 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4039 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4040 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4041 }; 4042 4043 struct rtw89_txpwr_lmt_5ghz_data { 4044 struct rtw89_txpwr_conf conf; 4045 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4046 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4047 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4048 }; 4049 4050 struct rtw89_txpwr_lmt_6ghz_data { 4051 struct rtw89_txpwr_conf conf; 4052 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4053 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4054 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4055 [RTW89_6G_CH_NUM]; 4056 }; 4057 4058 struct rtw89_txpwr_lmt_ru_2ghz_data { 4059 struct rtw89_txpwr_conf conf; 4060 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4061 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4062 }; 4063 4064 struct rtw89_txpwr_lmt_ru_5ghz_data { 4065 struct rtw89_txpwr_conf conf; 4066 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4067 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4068 }; 4069 4070 struct rtw89_txpwr_lmt_ru_6ghz_data { 4071 struct rtw89_txpwr_conf conf; 4072 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4073 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4074 [RTW89_6G_CH_NUM]; 4075 }; 4076 4077 struct rtw89_tx_shape_lmt_data { 4078 struct rtw89_txpwr_conf conf; 4079 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4080 }; 4081 4082 struct rtw89_tx_shape_lmt_ru_data { 4083 struct rtw89_txpwr_conf conf; 4084 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4085 }; 4086 4087 struct rtw89_rfe_data { 4088 struct rtw89_txpwr_byrate_data byrate; 4089 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 4090 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 4091 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 4092 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 4093 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 4094 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 4095 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 4096 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 4097 struct rtw89_rfe_parms rfe_parms; 4098 }; 4099 4100 struct rtw89_page_regs { 4101 u32 hci_fc_ctrl; 4102 u32 ch_page_ctrl; 4103 u32 ach_page_ctrl; 4104 u32 ach_page_info; 4105 u32 pub_page_info3; 4106 u32 pub_page_ctrl1; 4107 u32 pub_page_ctrl2; 4108 u32 pub_page_info1; 4109 u32 pub_page_info2; 4110 u32 wp_page_ctrl1; 4111 u32 wp_page_ctrl2; 4112 u32 wp_page_info1; 4113 }; 4114 4115 struct rtw89_imr_info { 4116 u32 wdrls_imr_set; 4117 u32 wsec_imr_reg; 4118 u32 wsec_imr_set; 4119 u32 mpdu_tx_imr_set; 4120 u32 mpdu_rx_imr_set; 4121 u32 sta_sch_imr_set; 4122 u32 txpktctl_imr_b0_reg; 4123 u32 txpktctl_imr_b0_clr; 4124 u32 txpktctl_imr_b0_set; 4125 u32 txpktctl_imr_b1_reg; 4126 u32 txpktctl_imr_b1_clr; 4127 u32 txpktctl_imr_b1_set; 4128 u32 wde_imr_clr; 4129 u32 wde_imr_set; 4130 u32 ple_imr_clr; 4131 u32 ple_imr_set; 4132 u32 host_disp_imr_clr; 4133 u32 host_disp_imr_set; 4134 u32 cpu_disp_imr_clr; 4135 u32 cpu_disp_imr_set; 4136 u32 other_disp_imr_clr; 4137 u32 other_disp_imr_set; 4138 u32 bbrpt_com_err_imr_reg; 4139 u32 bbrpt_chinfo_err_imr_reg; 4140 u32 bbrpt_err_imr_set; 4141 u32 bbrpt_dfs_err_imr_reg; 4142 u32 ptcl_imr_clr; 4143 u32 ptcl_imr_set; 4144 u32 cdma_imr_0_reg; 4145 u32 cdma_imr_0_clr; 4146 u32 cdma_imr_0_set; 4147 u32 cdma_imr_1_reg; 4148 u32 cdma_imr_1_clr; 4149 u32 cdma_imr_1_set; 4150 u32 phy_intf_imr_reg; 4151 u32 phy_intf_imr_clr; 4152 u32 phy_intf_imr_set; 4153 u32 rmac_imr_reg; 4154 u32 rmac_imr_clr; 4155 u32 rmac_imr_set; 4156 u32 tmac_imr_reg; 4157 u32 tmac_imr_clr; 4158 u32 tmac_imr_set; 4159 }; 4160 4161 struct rtw89_imr_table { 4162 const struct rtw89_reg_imr *regs; 4163 u32 n_regs; 4164 }; 4165 4166 struct rtw89_xtal_info { 4167 u32 xcap_reg; 4168 u32 sc_xo_mask; 4169 u32 sc_xi_mask; 4170 }; 4171 4172 struct rtw89_rrsr_cfgs { 4173 struct rtw89_reg3_def ref_rate; 4174 struct rtw89_reg3_def rsc; 4175 }; 4176 4177 struct rtw89_rfkill_regs { 4178 struct rtw89_reg3_def pinmux; 4179 struct rtw89_reg3_def mode; 4180 }; 4181 4182 struct rtw89_dig_regs { 4183 u32 seg0_pd_reg; 4184 u32 pd_lower_bound_mask; 4185 u32 pd_spatial_reuse_en; 4186 u32 bmode_pd_reg; 4187 u32 bmode_cca_rssi_limit_en; 4188 u32 bmode_pd_lower_bound_reg; 4189 u32 bmode_rssi_nocca_low_th_mask; 4190 struct rtw89_reg_def p0_lna_init; 4191 struct rtw89_reg_def p1_lna_init; 4192 struct rtw89_reg_def p0_tia_init; 4193 struct rtw89_reg_def p1_tia_init; 4194 struct rtw89_reg_def p0_rxb_init; 4195 struct rtw89_reg_def p1_rxb_init; 4196 struct rtw89_reg_def p0_p20_pagcugc_en; 4197 struct rtw89_reg_def p0_s20_pagcugc_en; 4198 struct rtw89_reg_def p1_p20_pagcugc_en; 4199 struct rtw89_reg_def p1_s20_pagcugc_en; 4200 }; 4201 4202 struct rtw89_edcca_regs { 4203 u32 edcca_level; 4204 u32 edcca_mask; 4205 u32 edcca_p_mask; 4206 u32 ppdu_level; 4207 u32 ppdu_mask; 4208 u32 rpt_a; 4209 u32 rpt_b; 4210 u32 rpt_sel; 4211 u32 rpt_sel_mask; 4212 u32 rpt_sel_be; 4213 u32 rpt_sel_be_mask; 4214 u32 tx_collision_t2r_st; 4215 u32 tx_collision_t2r_st_mask; 4216 }; 4217 4218 struct rtw89_phy_ul_tb_info { 4219 bool dyn_tb_tri_en; 4220 u8 def_if_bandedge; 4221 }; 4222 4223 struct rtw89_antdiv_stats { 4224 struct ewma_rssi cck_rssi_avg; 4225 struct ewma_rssi ofdm_rssi_avg; 4226 struct ewma_rssi non_legacy_rssi_avg; 4227 u16 pkt_cnt_cck; 4228 u16 pkt_cnt_ofdm; 4229 u16 pkt_cnt_non_legacy; 4230 u32 evm; 4231 }; 4232 4233 struct rtw89_antdiv_info { 4234 struct rtw89_antdiv_stats target_stats; 4235 struct rtw89_antdiv_stats main_stats; 4236 struct rtw89_antdiv_stats aux_stats; 4237 u8 training_count; 4238 u8 rssi_pre; 4239 bool get_stats; 4240 }; 4241 4242 enum rtw89_chanctx_state { 4243 RTW89_CHANCTX_STATE_MCC_START, 4244 RTW89_CHANCTX_STATE_MCC_STOP, 4245 }; 4246 4247 enum rtw89_chanctx_callbacks { 4248 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4249 RTW89_CHANCTX_CALLBACK_RFK, 4250 4251 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4252 }; 4253 4254 struct rtw89_chanctx_listener { 4255 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4256 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4257 }; 4258 4259 struct rtw89_chip_info { 4260 enum rtw89_core_chip_id chip_id; 4261 enum rtw89_chip_gen chip_gen; 4262 const struct rtw89_chip_ops *ops; 4263 const struct rtw89_mac_gen_def *mac_def; 4264 const struct rtw89_phy_gen_def *phy_def; 4265 const char *fw_basename; 4266 u8 fw_format_max; 4267 bool try_ce_fw; 4268 u8 bbmcu_nr; 4269 u32 needed_fw_elms; 4270 u32 fifo_size; 4271 bool small_fifo_size; 4272 u32 dle_scc_rsvd_size; 4273 u16 max_amsdu_limit; 4274 bool dis_2g_40m_ul_ofdma; 4275 u32 rsvd_ple_ofst; 4276 const struct rtw89_hfc_param_ini *hfc_param_ini; 4277 const struct rtw89_dle_mem *dle_mem; 4278 u8 wde_qempty_acq_grpnum; 4279 u8 wde_qempty_mgq_grpsel; 4280 u32 rf_base_addr[2]; 4281 u8 thermal_th[2]; 4282 u8 support_macid_num; 4283 u8 support_link_num; 4284 u8 support_chanctx_num; 4285 u8 support_bands; 4286 u16 support_bandwidths; 4287 bool support_unii4; 4288 bool support_rnr; 4289 bool support_ant_gain; 4290 bool ul_tb_waveform_ctrl; 4291 bool ul_tb_pwr_diff; 4292 bool hw_sec_hdr; 4293 bool hw_mgmt_tx_encrypt; 4294 u8 rf_path_num; 4295 u8 tx_nss; 4296 u8 rx_nss; 4297 u8 acam_num; 4298 u8 bcam_num; 4299 u8 scam_num; 4300 u8 bacam_num; 4301 u8 bacam_dynamic_num; 4302 enum rtw89_bacam_ver bacam_ver; 4303 u8 ppdu_max_usr; 4304 4305 u8 sec_ctrl_efuse_size; 4306 u32 physical_efuse_size; 4307 u32 logical_efuse_size; 4308 u32 limit_efuse_size; 4309 u32 dav_phy_efuse_size; 4310 u32 dav_log_efuse_size; 4311 u32 phycap_addr; 4312 u32 phycap_size; 4313 const struct rtw89_efuse_block_cfg *efuse_blocks; 4314 4315 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4316 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4317 const struct rtw89_phy_table *bb_table; 4318 const struct rtw89_phy_table *bb_gain_table; 4319 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4320 const struct rtw89_phy_table *nctl_table; 4321 const struct rtw89_rfk_tbl *nctl_post_table; 4322 const struct rtw89_phy_dig_gain_table *dig_table; 4323 const struct rtw89_dig_regs *dig_regs; 4324 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4325 4326 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4327 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4328 const struct rtw89_rfe_parms *dflt_parms; 4329 const struct rtw89_chanctx_listener *chanctx_listener; 4330 4331 u8 txpwr_factor_bb; 4332 u8 txpwr_factor_rf; 4333 u8 txpwr_factor_mac; 4334 4335 u32 para_ver; 4336 u32 wlcx_desired; 4337 u8 btcx_desired; 4338 u8 scbd; 4339 u8 mailbox; 4340 4341 u8 afh_guard_ch; 4342 const u8 *wl_rssi_thres; 4343 const u8 *bt_rssi_thres; 4344 u8 rssi_tol; 4345 4346 u8 mon_reg_num; 4347 const struct rtw89_btc_fbtc_mreg *mon_reg; 4348 u8 rf_para_ulink_num; 4349 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4350 u8 rf_para_dlink_num; 4351 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4352 u8 ps_mode_supported; 4353 u8 low_power_hci_modes; 4354 4355 u32 h2c_cctl_func_id; 4356 u32 hci_func_en_addr; 4357 u32 h2c_desc_size; 4358 u32 txwd_body_size; 4359 u32 txwd_info_size; 4360 u32 h2c_ctrl_reg; 4361 const u32 *h2c_regs; 4362 struct rtw89_reg_def h2c_counter_reg; 4363 u32 c2h_ctrl_reg; 4364 const u32 *c2h_regs; 4365 struct rtw89_reg_def c2h_counter_reg; 4366 const struct rtw89_page_regs *page_regs; 4367 const u32 *wow_reason_reg; 4368 bool cfo_src_fd; 4369 bool cfo_hw_comp; 4370 const struct rtw89_reg_def *dcfo_comp; 4371 u8 dcfo_comp_sft; 4372 const struct rtw89_imr_info *imr_info; 4373 const struct rtw89_imr_table *imr_dmac_table; 4374 const struct rtw89_imr_table *imr_cmac_table; 4375 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4376 struct rtw89_reg_def bss_clr_vld; 4377 u32 bss_clr_map_reg; 4378 const struct rtw89_rfkill_regs *rfkill_init; 4379 struct rtw89_reg_def rfkill_get; 4380 u32 dma_ch_mask; 4381 const struct rtw89_edcca_regs *edcca_regs; 4382 const struct wiphy_wowlan_support *wowlan_stub; 4383 const struct rtw89_xtal_info *xtal_info; 4384 }; 4385 4386 struct rtw89_chip_variant { 4387 bool no_mcs_12_13: 1; 4388 u32 fw_min_ver_code; 4389 }; 4390 4391 union rtw89_bus_info { 4392 const struct rtw89_pci_info *pci; 4393 }; 4394 4395 struct rtw89_driver_info { 4396 const struct rtw89_chip_info *chip; 4397 const struct rtw89_chip_variant *variant; 4398 const struct dmi_system_id *quirks; 4399 union rtw89_bus_info bus; 4400 }; 4401 4402 enum rtw89_hcifc_mode { 4403 RTW89_HCIFC_POH = 0, 4404 RTW89_HCIFC_STF = 1, 4405 RTW89_HCIFC_SDIO = 2, 4406 4407 /* keep last */ 4408 RTW89_HCIFC_MODE_INVALID, 4409 }; 4410 4411 struct rtw89_dle_info { 4412 const struct rtw89_rsvd_quota *rsvd_qt; 4413 enum rtw89_qta_mode qta_mode; 4414 u16 ple_pg_size; 4415 u16 ple_free_pg; 4416 u16 c0_rx_qta; 4417 u16 c1_rx_qta; 4418 }; 4419 4420 enum rtw89_host_rpr_mode { 4421 RTW89_RPR_MODE_POH = 0, 4422 RTW89_RPR_MODE_STF 4423 }; 4424 4425 #define RTW89_COMPLETION_BUF_SIZE 40 4426 #define RTW89_WAIT_COND_IDLE UINT_MAX 4427 4428 struct rtw89_completion_data { 4429 bool err; 4430 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4431 }; 4432 4433 struct rtw89_wait_info { 4434 atomic_t cond; 4435 struct completion completion; 4436 struct rtw89_completion_data data; 4437 }; 4438 4439 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4440 4441 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4442 { 4443 init_completion(&wait->completion); 4444 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4445 } 4446 4447 struct rtw89_mac_info { 4448 struct rtw89_dle_info dle_info; 4449 struct rtw89_hfc_param hfc_param; 4450 enum rtw89_qta_mode qta_mode; 4451 u8 rpwm_seq_num; 4452 u8 cpwm_seq_num; 4453 4454 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4455 struct rtw89_wait_info fw_ofld_wait; 4456 /* see RTW89_PS_WAIT_COND series for wait condition */ 4457 struct rtw89_wait_info ps_wait; 4458 }; 4459 4460 enum rtw89_fwdl_check_type { 4461 RTW89_FWDL_CHECK_FREERTOS_DONE, 4462 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4463 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4464 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4465 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4466 }; 4467 4468 enum rtw89_fw_type { 4469 RTW89_FW_NORMAL = 1, 4470 RTW89_FW_WOWLAN = 3, 4471 RTW89_FW_NORMAL_CE = 5, 4472 RTW89_FW_BBMCU0 = 64, 4473 RTW89_FW_BBMCU1 = 65, 4474 RTW89_FW_LOGFMT = 255, 4475 }; 4476 4477 enum rtw89_fw_feature { 4478 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4479 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4480 RTW89_FW_FEATURE_TX_WAKE, 4481 RTW89_FW_FEATURE_CRASH_TRIGGER, 4482 RTW89_FW_FEATURE_NO_PACKET_DROP, 4483 RTW89_FW_FEATURE_NO_DEEP_PS, 4484 RTW89_FW_FEATURE_NO_LPS_PG, 4485 RTW89_FW_FEATURE_BEACON_FILTER, 4486 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4487 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 4488 RTW89_FW_FEATURE_WOW_REASON_V1, 4489 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 4490 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1, 4491 RTW89_FW_FEATURE_RFK_RXDCK_V0, 4492 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 4493 RTW89_FW_FEATURE_NOTIFY_AP_INFO, 4494 RTW89_FW_FEATURE_CH_INFO_BE_V0, 4495 RTW89_FW_FEATURE_LPS_CH_INFO, 4496 RTW89_FW_FEATURE_NO_PHYCAP_P1, 4497 }; 4498 4499 struct rtw89_fw_suit { 4500 enum rtw89_fw_type type; 4501 const u8 *data; 4502 u32 size; 4503 u8 major_ver; 4504 u8 minor_ver; 4505 u8 sub_ver; 4506 u8 sub_idex; 4507 u16 build_year; 4508 u16 build_mon; 4509 u16 build_date; 4510 u16 build_hour; 4511 u16 build_min; 4512 u8 cmd_ver; 4513 u8 hdr_ver; 4514 u32 commitid; 4515 }; 4516 4517 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4518 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4519 #define RTW89_FW_SUIT_VER_CODE(s) \ 4520 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4521 4522 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4523 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4524 (mfw_hdr)->ver.minor, \ 4525 (mfw_hdr)->ver.sub, \ 4526 (mfw_hdr)->ver.idx) 4527 4528 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4529 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4530 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4531 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4532 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4533 4534 struct rtw89_fw_req_info { 4535 const struct firmware *firmware; 4536 struct completion completion; 4537 }; 4538 4539 struct rtw89_fw_log { 4540 struct rtw89_fw_suit suit; 4541 bool enable; 4542 u32 last_fmt_id; 4543 u32 fmt_count; 4544 const __le32 *fmt_ids; 4545 const char *(*fmts)[]; 4546 }; 4547 4548 struct rtw89_fw_elm_info { 4549 struct rtw89_phy_table *bb_tbl; 4550 struct rtw89_phy_table *bb_gain; 4551 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4552 struct rtw89_phy_table *rf_nctl; 4553 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4554 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4555 }; 4556 4557 enum rtw89_fw_mss_dev_type { 4558 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4559 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4560 }; 4561 4562 struct rtw89_fw_secure { 4563 bool secure_boot: 1; 4564 bool can_mss_v1: 1; 4565 bool can_mss_v0: 1; 4566 u32 sb_sel_mgn; 4567 u8 mss_dev_type; 4568 u8 mss_cust_idx; 4569 u8 mss_key_num; 4570 u8 mss_idx; /* v0 */ 4571 }; 4572 4573 struct rtw89_fw_info { 4574 struct rtw89_fw_req_info req; 4575 int fw_format; 4576 u8 h2c_seq; 4577 u8 rec_seq; 4578 u8 h2c_counter; 4579 u8 c2h_counter; 4580 struct rtw89_fw_suit normal; 4581 struct rtw89_fw_suit wowlan; 4582 struct rtw89_fw_suit bbmcu0; 4583 struct rtw89_fw_suit bbmcu1; 4584 struct rtw89_fw_log log; 4585 u32 feature_map; 4586 struct rtw89_fw_elm_info elm_info; 4587 struct rtw89_fw_secure sec; 4588 }; 4589 4590 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4591 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4592 4593 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4594 ((_fw)->feature_map |= BIT(_fw_feature)) 4595 4596 struct rtw89_cam_info { 4597 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4598 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4599 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4600 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4601 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4602 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4603 }; 4604 4605 enum rtw89_sar_sources { 4606 RTW89_SAR_SOURCE_NONE, 4607 RTW89_SAR_SOURCE_COMMON, 4608 4609 RTW89_SAR_SOURCE_NR, 4610 }; 4611 4612 enum rtw89_sar_subband { 4613 RTW89_SAR_2GHZ_SUBBAND, 4614 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4615 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4616 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4617 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4618 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4619 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4620 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4621 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4622 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4623 4624 RTW89_SAR_SUBBAND_NR, 4625 }; 4626 4627 struct rtw89_sar_cfg_common { 4628 bool set[RTW89_SAR_SUBBAND_NR]; 4629 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4630 }; 4631 4632 struct rtw89_sar_info { 4633 /* used to decide how to acces SAR cfg union */ 4634 enum rtw89_sar_sources src; 4635 4636 /* reserved for different knids of SAR cfg struct. 4637 * supposed that a single cfg struct cannot handle various SAR sources. 4638 */ 4639 union { 4640 struct rtw89_sar_cfg_common cfg_common; 4641 }; 4642 }; 4643 4644 enum rtw89_ant_gain_subband { 4645 RTW89_ANT_GAIN_2GHZ_SUBBAND, 4646 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */ 4647 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */ 4648 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4649 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4650 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4651 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4652 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */ 4653 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4654 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4655 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */ 4656 4657 RTW89_ANT_GAIN_SUBBAND_NR, 4658 }; 4659 4660 enum rtw89_ant_gain_domain_type { 4661 RTW89_ANT_GAIN_ETSI = 0, 4662 4663 RTW89_ANT_GAIN_DOMAIN_NUM, 4664 }; 4665 4666 #define RTW89_ANT_GAIN_CHAIN_NUM 2 4667 struct rtw89_ant_gain_info { 4668 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR]; 4669 u32 regd_enabled; 4670 }; 4671 4672 struct rtw89_6ghz_span { 4673 enum rtw89_sar_subband sar_subband_low; 4674 enum rtw89_sar_subband sar_subband_high; 4675 enum rtw89_ant_gain_subband ant_gain_subband_low; 4676 enum rtw89_ant_gain_subband ant_gain_subband_high; 4677 }; 4678 4679 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high) 4680 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high) 4681 4682 enum rtw89_tas_state { 4683 RTW89_TAS_STATE_DPR_OFF, 4684 RTW89_TAS_STATE_DPR_ON, 4685 RTW89_TAS_STATE_DPR_FORBID, 4686 }; 4687 4688 #define RTW89_TAS_MAX_WINDOW 50 4689 struct rtw89_tas_info { 4690 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 4691 s32 total_txpwr; 4692 u8 cur_idx; 4693 s8 dpr_gap; 4694 s8 delta; 4695 enum rtw89_tas_state state; 4696 bool enable; 4697 }; 4698 4699 struct rtw89_chanctx_cfg { 4700 enum rtw89_chanctx_idx idx; 4701 int ref_count; 4702 }; 4703 4704 enum rtw89_chanctx_changes { 4705 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4706 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4707 RTW89_CHANCTX_P2P_PS_CHANGE, 4708 RTW89_CHANCTX_BT_SLOT_CHANGE, 4709 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4710 4711 NUM_OF_RTW89_CHANCTX_CHANGES, 4712 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4713 }; 4714 4715 enum rtw89_entity_mode { 4716 RTW89_ENTITY_MODE_SCC_OR_SMLD, 4717 RTW89_ENTITY_MODE_MCC_PREPARE, 4718 RTW89_ENTITY_MODE_MCC, 4719 4720 NUM_OF_RTW89_ENTITY_MODE, 4721 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4722 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4723 }; 4724 4725 #define RTW89_MAX_INTERFACE_NUM 2 4726 4727 /* only valid when running with chanctx_ops */ 4728 struct rtw89_entity_mgnt { 4729 struct list_head active_list; 4730 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM]; 4731 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM] 4732 [__RTW89_MLD_MAX_LINK_NUM]; 4733 }; 4734 4735 struct rtw89_chanctx { 4736 struct cfg80211_chan_def chandef; 4737 struct rtw89_chan chan; 4738 struct rtw89_chan_rcd rcd; 4739 4740 /* only assigned when running with chanctx_ops */ 4741 struct rtw89_chanctx_cfg *cfg; 4742 }; 4743 4744 struct rtw89_edcca_bak { 4745 u8 a; 4746 u8 p; 4747 u8 ppdu; 4748 u8 th_old; 4749 }; 4750 4751 enum rtw89_dm_type { 4752 RTW89_DM_DYNAMIC_EDCCA, 4753 RTW89_DM_THERMAL_PROTECT, 4754 }; 4755 4756 #define RTW89_THERMAL_PROT_LV_MAX 5 4757 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */ 4758 4759 struct rtw89_hal { 4760 u32 rx_fltr; 4761 u8 cv; 4762 u8 acv; 4763 u32 antenna_tx; 4764 u32 antenna_rx; 4765 u8 tx_nss; 4766 u8 rx_nss; 4767 bool tx_path_diversity; 4768 bool ant_diversity; 4769 bool ant_diversity_fixed; 4770 bool support_cckpd; 4771 bool support_igi; 4772 bool no_mcs_12_13; 4773 4774 atomic_t roc_chanctx_idx; 4775 4776 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4777 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 4778 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 4779 struct cfg80211_chan_def roc_chandef; 4780 4781 bool entity_active[RTW89_PHY_MAX]; 4782 bool entity_pause; 4783 enum rtw89_entity_mode entity_mode; 4784 struct rtw89_entity_mgnt entity_mgnt; 4785 4786 struct rtw89_edcca_bak edcca_bak; 4787 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4788 4789 u8 thermal_prot_th; 4790 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */ 4791 }; 4792 4793 #define RTW89_MAX_MAC_ID_NUM 128 4794 #define RTW89_MAX_PKT_OFLD_NUM 255 4795 4796 enum rtw89_flags { 4797 RTW89_FLAG_POWERON, 4798 RTW89_FLAG_DMAC_FUNC, 4799 RTW89_FLAG_CMAC0_FUNC, 4800 RTW89_FLAG_CMAC1_FUNC, 4801 RTW89_FLAG_FW_RDY, 4802 RTW89_FLAG_RUNNING, 4803 RTW89_FLAG_PROBE_DONE, 4804 RTW89_FLAG_BFEE_MON, 4805 RTW89_FLAG_BFEE_EN, 4806 RTW89_FLAG_BFEE_TIMER_KEEP, 4807 RTW89_FLAG_NAPI_RUNNING, 4808 RTW89_FLAG_LEISURE_PS, 4809 RTW89_FLAG_LOW_POWER_MODE, 4810 RTW89_FLAG_INACTIVE_PS, 4811 RTW89_FLAG_CRASH_SIMULATING, 4812 RTW89_FLAG_SER_HANDLING, 4813 RTW89_FLAG_WOWLAN, 4814 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4815 RTW89_FLAG_CHANGING_INTERFACE, 4816 RTW89_FLAG_HW_RFKILL_STATE, 4817 4818 NUM_OF_RTW89_FLAGS, 4819 }; 4820 4821 enum rtw89_quirks { 4822 RTW89_QUIRK_PCI_BER, 4823 RTW89_QUIRK_THERMAL_PROT_120C, 4824 RTW89_QUIRK_THERMAL_PROT_110C, 4825 4826 NUM_OF_RTW89_QUIRKS, 4827 }; 4828 4829 enum rtw89_custid { 4830 RTW89_CUSTID_NONE, 4831 RTW89_CUSTID_ACER, 4832 RTW89_CUSTID_AMD, 4833 RTW89_CUSTID_ASUS, 4834 RTW89_CUSTID_DELL, 4835 RTW89_CUSTID_HP, 4836 RTW89_CUSTID_LENOVO, 4837 }; 4838 4839 enum rtw89_pkt_drop_sel { 4840 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4841 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4842 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4843 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4844 RTW89_PKT_DROP_SEL_MACID_ALL, 4845 RTW89_PKT_DROP_SEL_MG0_ONCE, 4846 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4847 RTW89_PKT_DROP_SEL_HIQ_PORT, 4848 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4849 RTW89_PKT_DROP_SEL_BAND, 4850 RTW89_PKT_DROP_SEL_BAND_ONCE, 4851 RTW89_PKT_DROP_SEL_REL_MACID, 4852 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4853 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4854 }; 4855 4856 struct rtw89_pkt_drop_params { 4857 enum rtw89_pkt_drop_sel sel; 4858 enum rtw89_mac_idx mac_band; 4859 u8 macid; 4860 u8 port; 4861 u8 mbssid; 4862 bool tf_trs; 4863 u32 macid_band_sel[4]; 4864 }; 4865 4866 struct rtw89_pkt_stat { 4867 u16 beacon_nr; 4868 u8 beacon_rate; 4869 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4870 }; 4871 4872 DECLARE_EWMA(thermal, 4, 4); 4873 4874 struct rtw89_phy_stat { 4875 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4876 u8 last_thermal_max; 4877 struct ewma_rssi bcn_rssi; 4878 struct rtw89_pkt_stat cur_pkt_stat; 4879 struct rtw89_pkt_stat last_pkt_stat; 4880 }; 4881 4882 enum rtw89_rfk_report_state { 4883 RTW89_RFK_STATE_START = 0x0, 4884 RTW89_RFK_STATE_OK = 0x1, 4885 RTW89_RFK_STATE_FAIL = 0x2, 4886 RTW89_RFK_STATE_TIMEOUT = 0x3, 4887 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 4888 }; 4889 4890 struct rtw89_rfk_wait_info { 4891 struct completion completion; 4892 ktime_t start_time; 4893 enum rtw89_rfk_report_state state; 4894 u8 version; 4895 }; 4896 4897 #define RTW89_DACK_PATH_NR 2 4898 #define RTW89_DACK_IDX_NR 2 4899 #define RTW89_DACK_MSBK_NR 16 4900 struct rtw89_dack_info { 4901 bool dack_done; 4902 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4903 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4904 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4905 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4906 u32 dack_cnt; 4907 bool addck_timeout[RTW89_DACK_PATH_NR]; 4908 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4909 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4910 }; 4911 4912 enum rtw89_rfk_chs_nrs { 4913 __RTW89_RFK_CHS_NR_V0 = 2, 4914 __RTW89_RFK_CHS_NR_V1 = 3, 4915 4916 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 4917 }; 4918 4919 struct rtw89_rfk_mcc_info_data { 4920 u8 ch[RTW89_RFK_CHS_NR]; 4921 u8 band[RTW89_RFK_CHS_NR]; 4922 u8 bw[RTW89_RFK_CHS_NR]; 4923 u8 table_idx; 4924 }; 4925 4926 struct rtw89_rfk_mcc_info { 4927 struct rtw89_rfk_mcc_info_data data[2]; 4928 }; 4929 4930 #define RTW89_IQK_CHS_NR 2 4931 #define RTW89_IQK_PATH_NR 4 4932 4933 struct rtw89_lck_info { 4934 u8 thermal[RF_PATH_MAX]; 4935 }; 4936 4937 struct rtw89_rx_dck_info { 4938 u8 thermal[RF_PATH_MAX]; 4939 }; 4940 4941 struct rtw89_iqk_info { 4942 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4943 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4944 bool lok_fail[RTW89_IQK_PATH_NR]; 4945 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4946 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4947 u32 iqk_fail_cnt; 4948 bool is_iqk_init; 4949 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4950 u8 iqk_band[RTW89_IQK_PATH_NR]; 4951 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4952 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4953 u8 iqk_times; 4954 u8 version; 4955 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4956 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4957 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4958 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4959 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4960 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4961 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4962 bool is_nbiqk; 4963 bool iqk_fft_en; 4964 bool iqk_xym_en; 4965 bool iqk_sram_en; 4966 bool iqk_cfir_en; 4967 u32 syn1to2; 4968 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4969 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4970 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4971 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4972 }; 4973 4974 #define RTW89_DPK_RF_PATH 2 4975 #define RTW89_DPK_AVG_THERMAL_NUM 8 4976 #define RTW89_DPK_BKUP_NUM 2 4977 struct rtw89_dpk_bkup_para { 4978 enum rtw89_band band; 4979 enum rtw89_bandwidth bw; 4980 u8 ch; 4981 bool path_ok; 4982 u8 mdpd_en; 4983 u8 txagc_dpk; 4984 u8 ther_dpk; 4985 u8 gs; 4986 u16 pwsf; 4987 }; 4988 4989 struct rtw89_dpk_info { 4990 bool is_dpk_enable; 4991 bool is_dpk_reload_en; 4992 u8 dpk_gs[RTW89_PHY_MAX]; 4993 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4994 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4995 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4996 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4997 u8 cur_idx[RTW89_DPK_RF_PATH]; 4998 u8 cur_k_set; 4999 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5000 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 5001 u32 dpk_order[RTW89_DPK_RF_PATH]; 5002 }; 5003 5004 struct rtw89_fem_info { 5005 bool elna_2g; 5006 bool elna_5g; 5007 bool epa_2g; 5008 bool epa_5g; 5009 bool epa_6g; 5010 }; 5011 5012 struct rtw89_phy_ch_info { 5013 u8 rssi_min; 5014 u16 rssi_min_macid; 5015 u8 pre_rssi_min; 5016 u8 rssi_max; 5017 u16 rssi_max_macid; 5018 u8 rxsc_160; 5019 u8 rxsc_80; 5020 u8 rxsc_40; 5021 u8 rxsc_20; 5022 u8 rxsc_l; 5023 u8 is_noisy; 5024 }; 5025 5026 struct rtw89_agc_gaincode_set { 5027 u8 lna_idx; 5028 u8 tia_idx; 5029 u8 rxb_idx; 5030 }; 5031 5032 #define IGI_RSSI_TH_NUM 5 5033 #define FA_TH_NUM 4 5034 #define TIA_LNA_OP1DB_NUM 8 5035 #define LNA_GAIN_NUM 7 5036 #define TIA_GAIN_NUM 2 5037 struct rtw89_dig_info { 5038 struct rtw89_agc_gaincode_set cur_gaincode; 5039 bool force_gaincode_idx_en; 5040 struct rtw89_agc_gaincode_set force_gaincode; 5041 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 5042 u16 fa_th[FA_TH_NUM]; 5043 u8 igi_rssi; 5044 u8 igi_fa_rssi; 5045 u8 fa_rssi_ofst; 5046 u8 dyn_igi_max; 5047 u8 dyn_igi_min; 5048 bool dyn_pd_th_en; 5049 u8 dyn_pd_th_max; 5050 u8 pd_low_th_ofst; 5051 u8 ib_pbk; 5052 s8 ib_pkpwr; 5053 s8 lna_gain_a[LNA_GAIN_NUM]; 5054 s8 lna_gain_g[LNA_GAIN_NUM]; 5055 s8 *lna_gain; 5056 s8 tia_gain_a[TIA_GAIN_NUM]; 5057 s8 tia_gain_g[TIA_GAIN_NUM]; 5058 s8 *tia_gain; 5059 bool is_linked_pre; 5060 bool bypass_dig; 5061 }; 5062 5063 enum rtw89_multi_cfo_mode { 5064 RTW89_PKT_BASED_AVG_MODE = 0, 5065 RTW89_ENTRY_BASED_AVG_MODE = 1, 5066 RTW89_TP_BASED_AVG_MODE = 2, 5067 }; 5068 5069 enum rtw89_phy_cfo_status { 5070 RTW89_PHY_DCFO_STATE_NORMAL = 0, 5071 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 5072 RTW89_PHY_DCFO_STATE_HOLD = 2, 5073 RTW89_PHY_DCFO_STATE_MAX 5074 }; 5075 5076 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 5077 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 5078 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 5079 }; 5080 5081 struct rtw89_cfo_tracking_info { 5082 u16 cfo_timer_ms; 5083 bool cfo_trig_by_timer_en; 5084 enum rtw89_phy_cfo_status phy_cfo_status; 5085 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 5086 u8 phy_cfo_trk_cnt; 5087 bool is_adjust; 5088 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 5089 bool apply_compensation; 5090 u8 crystal_cap; 5091 u8 crystal_cap_default; 5092 u8 def_x_cap; 5093 s8 x_cap_ofst; 5094 u32 sta_cfo_tolerance; 5095 s32 cfo_tail[CFO_TRACK_MAX_USER]; 5096 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 5097 s32 cfo_avg_pre; 5098 s32 cfo_avg[CFO_TRACK_MAX_USER]; 5099 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 5100 s32 dcfo_avg; 5101 s32 dcfo_avg_pre; 5102 u32 packet_count; 5103 u32 packet_count_pre; 5104 s32 residual_cfo_acc; 5105 u8 phy_cfotrk_state; 5106 u8 phy_cfotrk_cnt; 5107 bool divergence_lock_en; 5108 u8 x_cap_lb; 5109 u8 x_cap_ub; 5110 u8 lock_cnt; 5111 }; 5112 5113 enum rtw89_tssi_mode { 5114 RTW89_TSSI_NORMAL = 0, 5115 RTW89_TSSI_SCAN = 1, 5116 }; 5117 5118 enum rtw89_tssi_alimk_band { 5119 TSSI_ALIMK_2G = 0, 5120 TSSI_ALIMK_5GL, 5121 TSSI_ALIMK_5GM, 5122 TSSI_ALIMK_5GH, 5123 TSSI_ALIMK_MAX 5124 }; 5125 5126 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 5127 #define TSSI_TRIM_CH_GROUP_NUM 8 5128 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 5129 5130 #define TSSI_CCK_CH_GROUP_NUM 6 5131 #define TSSI_MCS_2G_CH_GROUP_NUM 5 5132 #define TSSI_MCS_5G_CH_GROUP_NUM 14 5133 #define TSSI_MCS_6G_CH_GROUP_NUM 32 5134 #define TSSI_MCS_CH_GROUP_NUM \ 5135 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 5136 #define TSSI_MAX_CH_NUM 67 5137 #define TSSI_ALIMK_VALUE_NUM 8 5138 5139 struct rtw89_tssi_info { 5140 u8 thermal[RF_PATH_MAX]; 5141 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 5142 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 5143 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 5144 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 5145 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 5146 s8 extra_ofst[RF_PATH_MAX]; 5147 bool tssi_tracking_check[RF_PATH_MAX]; 5148 u8 default_txagc_offset[RF_PATH_MAX]; 5149 u32 base_thermal[RF_PATH_MAX]; 5150 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 5151 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 5152 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 5153 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 5154 u32 tssi_alimk_time; 5155 }; 5156 5157 struct rtw89_power_trim_info { 5158 bool pg_thermal_trim; 5159 bool pg_pa_bias_trim; 5160 u8 thermal_trim[RF_PATH_MAX]; 5161 u8 pa_bias_trim[RF_PATH_MAX]; 5162 u8 pad_bias_trim[RF_PATH_MAX]; 5163 }; 5164 5165 struct rtw89_regd { 5166 char alpha2[3]; 5167 u8 txpwr_regd[RTW89_BAND_NUM]; 5168 }; 5169 5170 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 5171 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 5172 #define RTW89_5GHZ_UNII4_START_INDEX 25 5173 5174 struct rtw89_regulatory_info { 5175 const struct rtw89_regd *regd; 5176 enum rtw89_reg_6ghz_power reg_6ghz_power; 5177 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 5178 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 5179 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 5180 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 5181 }; 5182 5183 enum rtw89_ifs_clm_application { 5184 RTW89_IFS_CLM_INIT = 0, 5185 RTW89_IFS_CLM_BACKGROUND = 1, 5186 RTW89_IFS_CLM_ACS = 2, 5187 RTW89_IFS_CLM_DIG = 3, 5188 RTW89_IFS_CLM_TDMA_DIG = 4, 5189 RTW89_IFS_CLM_DBG = 5, 5190 RTW89_IFS_CLM_DBG_MANUAL = 6 5191 }; 5192 5193 enum rtw89_env_racing_lv { 5194 RTW89_RAC_RELEASE = 0, 5195 RTW89_RAC_LV_1 = 1, 5196 RTW89_RAC_LV_2 = 2, 5197 RTW89_RAC_LV_3 = 3, 5198 RTW89_RAC_LV_4 = 4, 5199 RTW89_RAC_MAX_NUM = 5 5200 }; 5201 5202 struct rtw89_ccx_para_info { 5203 enum rtw89_env_racing_lv rac_lv; 5204 u16 mntr_time; 5205 u8 nhm_manual_th_ofst; 5206 u8 nhm_manual_th0; 5207 enum rtw89_ifs_clm_application ifs_clm_app; 5208 u32 ifs_clm_manual_th_times; 5209 u32 ifs_clm_manual_th0; 5210 u8 fahm_manual_th_ofst; 5211 u8 fahm_manual_th0; 5212 u8 fahm_numer_opt; 5213 u8 fahm_denom_opt; 5214 }; 5215 5216 enum rtw89_ccx_edcca_opt_sc_idx { 5217 RTW89_CCX_EDCCA_SEG0_P0 = 0, 5218 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5219 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5220 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5221 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5222 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5223 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5224 RTW89_CCX_EDCCA_SEG1_S3 = 7 5225 }; 5226 5227 enum rtw89_ccx_edcca_opt_bw_idx { 5228 RTW89_CCX_EDCCA_BW20_0 = 0, 5229 RTW89_CCX_EDCCA_BW20_1 = 1, 5230 RTW89_CCX_EDCCA_BW20_2 = 2, 5231 RTW89_CCX_EDCCA_BW20_3 = 3, 5232 RTW89_CCX_EDCCA_BW20_4 = 4, 5233 RTW89_CCX_EDCCA_BW20_5 = 5, 5234 RTW89_CCX_EDCCA_BW20_6 = 6, 5235 RTW89_CCX_EDCCA_BW20_7 = 7 5236 }; 5237 5238 #define RTW89_NHM_TH_NUM 11 5239 #define RTW89_FAHM_TH_NUM 11 5240 #define RTW89_NHM_RPT_NUM 12 5241 #define RTW89_FAHM_RPT_NUM 12 5242 #define RTW89_IFS_CLM_NUM 4 5243 struct rtw89_env_monitor_info { 5244 u8 ccx_watchdog_result; 5245 bool ccx_ongoing; 5246 u8 ccx_rac_lv; 5247 bool ccx_manual_ctrl; 5248 u16 ifs_clm_mntr_time; 5249 enum rtw89_ifs_clm_application ifs_clm_app; 5250 u16 ccx_period; 5251 u8 ccx_unit_idx; 5252 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5253 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5254 u16 ifs_clm_tx; 5255 u16 ifs_clm_edcca_excl_cca; 5256 u16 ifs_clm_ofdmfa; 5257 u16 ifs_clm_ofdmcca_excl_fa; 5258 u16 ifs_clm_cckfa; 5259 u16 ifs_clm_cckcca_excl_fa; 5260 u16 ifs_clm_total_ifs; 5261 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5262 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5263 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5264 u8 ifs_clm_tx_ratio; 5265 u8 ifs_clm_edcca_excl_cca_ratio; 5266 u8 ifs_clm_cck_fa_ratio; 5267 u8 ifs_clm_ofdm_fa_ratio; 5268 u8 ifs_clm_cck_cca_excl_fa_ratio; 5269 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5270 u16 ifs_clm_cck_fa_permil; 5271 u16 ifs_clm_ofdm_fa_permil; 5272 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5273 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5274 }; 5275 5276 enum rtw89_ser_rcvy_step { 5277 RTW89_SER_DRV_STOP_TX, 5278 RTW89_SER_DRV_STOP_RX, 5279 RTW89_SER_DRV_STOP_RUN, 5280 RTW89_SER_HAL_STOP_DMA, 5281 RTW89_SER_SUPPRESS_LOG, 5282 RTW89_NUM_OF_SER_FLAGS 5283 }; 5284 5285 struct rtw89_ser { 5286 u8 state; 5287 u8 alarm_event; 5288 bool prehandle_l1; 5289 5290 struct work_struct ser_hdl_work; 5291 struct delayed_work ser_alarm_work; 5292 const struct state_ent *st_tbl; 5293 const struct event_ent *ev_tbl; 5294 struct list_head msg_q; 5295 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5296 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5297 }; 5298 5299 enum rtw89_mac_ax_ps_mode { 5300 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5301 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5302 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5303 RTW89_MAC_AX_PS_MODE_MAX = 3, 5304 }; 5305 5306 enum rtw89_last_rpwm_mode { 5307 RTW89_LAST_RPWM_PS = 0x0, 5308 RTW89_LAST_RPWM_ACTIVE = 0x6, 5309 }; 5310 5311 struct rtw89_lps_parm { 5312 u8 macid; 5313 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5314 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5315 }; 5316 5317 struct rtw89_ppdu_sts_info { 5318 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 5319 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 5320 }; 5321 5322 struct rtw89_early_h2c { 5323 struct list_head list; 5324 u8 *h2c; 5325 u16 h2c_len; 5326 }; 5327 5328 struct rtw89_hw_scan_info { 5329 struct rtw89_vif_link *scanning_vif; 5330 struct list_head pkt_list[NUM_NL80211_BANDS]; 5331 struct rtw89_chan op_chan; 5332 bool abort; 5333 u32 last_chan_idx; 5334 }; 5335 5336 enum rtw89_phy_bb_gain_band { 5337 RTW89_BB_GAIN_BAND_2G = 0, 5338 RTW89_BB_GAIN_BAND_5G_L = 1, 5339 RTW89_BB_GAIN_BAND_5G_M = 2, 5340 RTW89_BB_GAIN_BAND_5G_H = 3, 5341 RTW89_BB_GAIN_BAND_6G_L = 4, 5342 RTW89_BB_GAIN_BAND_6G_M = 5, 5343 RTW89_BB_GAIN_BAND_6G_H = 6, 5344 RTW89_BB_GAIN_BAND_6G_UH = 7, 5345 5346 RTW89_BB_GAIN_BAND_NR, 5347 }; 5348 5349 enum rtw89_phy_gain_band_be { 5350 RTW89_BB_GAIN_BAND_2G_BE = 0, 5351 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5352 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5353 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5354 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5355 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5356 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5357 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5358 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5359 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5360 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5361 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5362 5363 RTW89_BB_GAIN_BAND_NR_BE, 5364 }; 5365 5366 enum rtw89_phy_bb_bw_be { 5367 RTW89_BB_BW_20_40 = 0, 5368 RTW89_BB_BW_80_160_320 = 1, 5369 5370 RTW89_BB_BW_NR_BE, 5371 }; 5372 5373 enum rtw89_bw20_sc { 5374 RTW89_BW20_SC_20M = 1, 5375 RTW89_BW20_SC_40M = 2, 5376 RTW89_BW20_SC_80M = 4, 5377 RTW89_BW20_SC_160M = 8, 5378 RTW89_BW20_SC_320M = 16, 5379 }; 5380 5381 enum rtw89_cmac_table_bw { 5382 RTW89_CMAC_BW_20M = 0, 5383 RTW89_CMAC_BW_40M = 1, 5384 RTW89_CMAC_BW_80M = 2, 5385 RTW89_CMAC_BW_160M = 3, 5386 RTW89_CMAC_BW_320M = 4, 5387 5388 RTW89_CMAC_BW_NR, 5389 }; 5390 5391 enum rtw89_phy_bb_rxsc_num { 5392 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5393 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5394 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5395 }; 5396 5397 struct rtw89_phy_bb_gain_info { 5398 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5399 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5400 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5401 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5402 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5403 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5404 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5405 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5406 [RTW89_BB_RXSC_NUM_40]; 5407 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5408 [RTW89_BB_RXSC_NUM_80]; 5409 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5410 [RTW89_BB_RXSC_NUM_160]; 5411 }; 5412 5413 struct rtw89_phy_bb_gain_info_be { 5414 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5415 [LNA_GAIN_NUM]; 5416 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5417 [TIA_GAIN_NUM]; 5418 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5419 [RF_PATH_MAX][LNA_GAIN_NUM]; 5420 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5421 [RF_PATH_MAX][LNA_GAIN_NUM]; 5422 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5423 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5424 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5425 [RTW89_BW20_SC_20M]; 5426 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5427 [RTW89_BW20_SC_40M]; 5428 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5429 [RTW89_BW20_SC_80M]; 5430 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5431 [RTW89_BW20_SC_160M]; 5432 }; 5433 5434 struct rtw89_phy_efuse_gain { 5435 bool offset_valid; 5436 bool comp_valid; 5437 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5438 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5439 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5440 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5441 }; 5442 5443 #define RTW89_MAX_PATTERN_NUM 18 5444 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5445 #define RTW89_MAX_PATTERN_SIZE 128 5446 5447 struct rtw89_wow_cam_info { 5448 bool r_w; 5449 u8 idx; 5450 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5451 u16 crc; 5452 bool negative_pattern_match; 5453 bool skip_mac_hdr; 5454 bool uc; 5455 bool mc; 5456 bool bc; 5457 bool valid; 5458 }; 5459 5460 struct rtw89_wow_key_info { 5461 u8 ptk_tx_iv[8]; 5462 u8 valid_check; 5463 u8 symbol_check_en; 5464 u8 gtk_keyidx; 5465 u8 rsvd[5]; 5466 u8 ptk_rx_iv[8]; 5467 u8 gtk_rx_iv[4][8]; 5468 } __packed; 5469 5470 struct rtw89_wow_gtk_info { 5471 u8 kck[32]; 5472 u8 kek[32]; 5473 u8 tk1[16]; 5474 u8 txmickey[8]; 5475 u8 rxmickey[8]; 5476 __le32 igtk_keyid; 5477 __le64 ipn; 5478 u8 igtk[2][32]; 5479 u8 psk[32]; 5480 } __packed; 5481 5482 struct rtw89_wow_aoac_report { 5483 u8 rpt_ver; 5484 u8 sec_type; 5485 u8 key_idx; 5486 u8 pattern_idx; 5487 u8 rekey_ok; 5488 u8 ptk_tx_iv[8]; 5489 u8 eapol_key_replay_count[8]; 5490 u8 gtk[32]; 5491 u8 ptk_rx_iv[8]; 5492 u8 gtk_rx_iv[4][8]; 5493 u64 igtk_key_id; 5494 u64 igtk_ipn; 5495 u8 igtk[32]; 5496 u8 csa_pri_ch; 5497 u8 csa_bw; 5498 u8 csa_ch_offset; 5499 u8 csa_chsw_failed; 5500 u8 csa_ch_band; 5501 }; 5502 5503 struct rtw89_wow_param { 5504 struct rtw89_vif_link *rtwvif_link; 5505 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5506 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5507 struct rtw89_wow_key_info key_info; 5508 struct rtw89_wow_gtk_info gtk_info; 5509 struct rtw89_wow_aoac_report aoac_rpt; 5510 u8 pattern_cnt; 5511 u8 ptk_alg; 5512 u8 gtk_alg; 5513 u8 ptk_keyidx; 5514 u8 akm; 5515 5516 /* see RTW89_WOW_WAIT_COND series for wait condition */ 5517 struct rtw89_wait_info wait; 5518 5519 bool pno_inited; 5520 struct list_head pno_pkt_list; 5521 struct cfg80211_sched_scan_request *nd_config; 5522 }; 5523 5524 struct rtw89_mcc_limit { 5525 bool enable; 5526 u16 max_tob; /* TU; max time offset behind */ 5527 u16 max_toa; /* TU; max time offset ahead */ 5528 u16 max_dur; /* TU */ 5529 }; 5530 5531 struct rtw89_mcc_policy { 5532 u8 c2h_rpt; 5533 u8 tx_null_early; 5534 u8 dis_tx_null; 5535 u8 in_curr_ch; 5536 u8 dis_sw_retry; 5537 u8 sw_retry_count; 5538 }; 5539 5540 struct rtw89_mcc_role { 5541 struct rtw89_vif_link *rtwvif_link; 5542 struct rtw89_mcc_policy policy; 5543 struct rtw89_mcc_limit limit; 5544 5545 /* only valid when running with FW MRC mechanism */ 5546 u8 slot_idx; 5547 5548 /* byte-array in LE order for FW */ 5549 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5550 5551 u16 duration; /* TU */ 5552 u16 beacon_interval; /* TU */ 5553 bool is_2ghz; 5554 bool is_go; 5555 bool is_gc; 5556 }; 5557 5558 struct rtw89_mcc_bt_role { 5559 u16 duration; /* TU */ 5560 }; 5561 5562 struct rtw89_mcc_courtesy { 5563 bool enable; 5564 u8 slot_num; 5565 u8 macid_src; 5566 u8 macid_tgt; 5567 }; 5568 5569 enum rtw89_mcc_plan { 5570 RTW89_MCC_PLAN_TAIL_BT, 5571 RTW89_MCC_PLAN_MID_BT, 5572 RTW89_MCC_PLAN_NO_BT, 5573 5574 NUM_OF_RTW89_MCC_PLAN, 5575 }; 5576 5577 struct rtw89_mcc_pattern { 5578 s16 tob_ref; /* TU; time offset behind of reference role */ 5579 s16 toa_ref; /* TU; time offset ahead of reference role */ 5580 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5581 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5582 5583 enum rtw89_mcc_plan plan; 5584 struct rtw89_mcc_courtesy courtesy; 5585 }; 5586 5587 struct rtw89_mcc_sync { 5588 bool enable; 5589 u16 offset; /* TU */ 5590 u8 macid_src; 5591 u8 band_src; 5592 u8 port_src; 5593 u8 macid_tgt; 5594 u8 band_tgt; 5595 u8 port_tgt; 5596 }; 5597 5598 struct rtw89_mcc_config { 5599 struct rtw89_mcc_pattern pattern; 5600 struct rtw89_mcc_sync sync; 5601 u64 start_tsf; 5602 u16 mcc_interval; /* TU */ 5603 u16 beacon_offset; /* TU */ 5604 }; 5605 5606 enum rtw89_mcc_mode { 5607 RTW89_MCC_MODE_GO_STA, 5608 RTW89_MCC_MODE_GC_STA, 5609 }; 5610 5611 struct rtw89_mcc_info { 5612 struct rtw89_wait_info wait; 5613 5614 u8 group; 5615 enum rtw89_mcc_mode mode; 5616 struct rtw89_mcc_role role_ref; /* reference role */ 5617 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5618 struct rtw89_mcc_bt_role bt_role; 5619 struct rtw89_mcc_config config; 5620 }; 5621 5622 struct rtw89_dev { 5623 struct ieee80211_hw *hw; 5624 struct device *dev; 5625 const struct ieee80211_ops *ops; 5626 5627 bool dbcc_en; 5628 bool support_mlo; 5629 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5630 struct rtw89_hw_scan_info scan_info; 5631 const struct rtw89_chip_info *chip; 5632 const struct rtw89_chip_variant *variant; 5633 const struct rtw89_pci_info *pci_info; 5634 const struct rtw89_rfe_parms *rfe_parms; 5635 struct rtw89_hal hal; 5636 struct rtw89_mcc_info mcc; 5637 struct rtw89_mac_info mac; 5638 struct rtw89_fw_info fw; 5639 struct rtw89_hci_info hci; 5640 struct rtw89_efuse efuse; 5641 struct rtw89_traffic_stats stats; 5642 struct rtw89_rfe_data *rfe_data; 5643 enum rtw89_custid custid; 5644 5645 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM]; 5646 refcount_t refcount_ap_info; 5647 5648 /* ensures exclusive access from mac80211 callbacks */ 5649 struct mutex mutex; 5650 struct list_head rtwvifs_list; 5651 /* used to protect rf read write */ 5652 struct mutex rf_mutex; 5653 struct workqueue_struct *txq_wq; 5654 struct work_struct txq_work; 5655 struct delayed_work txq_reinvoke_work; 5656 /* used to protect ba_list and forbid_ba_list */ 5657 spinlock_t ba_lock; 5658 /* txqs to setup ba session */ 5659 struct list_head ba_list; 5660 /* txqs to forbid ba session */ 5661 struct list_head forbid_ba_list; 5662 struct work_struct ba_work; 5663 /* used to protect rpwm */ 5664 spinlock_t rpwm_lock; 5665 5666 struct rtw89_cam_info cam_info; 5667 5668 struct sk_buff_head c2h_queue; 5669 struct work_struct c2h_work; 5670 struct work_struct ips_work; 5671 struct work_struct load_firmware_work; 5672 struct work_struct cancel_6ghz_probe_work; 5673 5674 struct list_head early_h2c_list; 5675 5676 struct rtw89_ser ser; 5677 5678 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5679 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5680 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5681 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5682 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 5683 5684 struct rtw89_phy_stat phystat; 5685 struct rtw89_rfk_wait_info rfk_wait; 5686 struct rtw89_dack_info dack; 5687 struct rtw89_iqk_info iqk; 5688 struct rtw89_dpk_info dpk; 5689 struct rtw89_rfk_mcc_info rfk_mcc; 5690 struct rtw89_lck_info lck; 5691 struct rtw89_rx_dck_info rx_dck; 5692 bool is_tssi_mode[RF_PATH_MAX]; 5693 bool is_bt_iqk_timeout; 5694 5695 struct rtw89_fem_info fem; 5696 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5697 struct rtw89_tssi_info tssi; 5698 struct rtw89_power_trim_info pwr_trim; 5699 5700 struct rtw89_cfo_tracking_info cfo_tracking; 5701 struct rtw89_env_monitor_info env_monitor; 5702 struct rtw89_dig_info dig; 5703 struct rtw89_phy_ch_info ch_info; 5704 union { 5705 struct rtw89_phy_bb_gain_info ax; 5706 struct rtw89_phy_bb_gain_info_be be; 5707 } bb_gain; 5708 struct rtw89_phy_efuse_gain efuse_gain; 5709 struct rtw89_phy_ul_tb_info ul_tb_info; 5710 struct rtw89_antdiv_info antdiv; 5711 5712 struct delayed_work track_work; 5713 struct delayed_work chanctx_work; 5714 struct delayed_work coex_act1_work; 5715 struct delayed_work coex_bt_devinfo_work; 5716 struct delayed_work coex_rfk_chk_work; 5717 struct delayed_work cfo_track_work; 5718 struct delayed_work forbid_ba_work; 5719 struct delayed_work roc_work; 5720 struct delayed_work antdiv_work; 5721 struct rtw89_ppdu_sts_info ppdu_sts; 5722 u8 total_sta_assoc; 5723 bool scanning; 5724 5725 struct rtw89_regulatory_info regulatory; 5726 struct rtw89_sar_info sar; 5727 struct rtw89_tas_info tas; 5728 struct rtw89_ant_gain_info ant_gain; 5729 5730 struct rtw89_btc btc; 5731 enum rtw89_ps_mode ps_mode; 5732 bool lps_enabled; 5733 5734 struct rtw89_wow_param wow; 5735 5736 /* napi structure */ 5737 struct net_device *netdev; 5738 struct napi_struct napi; 5739 int napi_budget_countdown; 5740 5741 struct rtw89_debugfs *debugfs; 5742 5743 /* HCI related data, keep last */ 5744 u8 priv[] __aligned(sizeof(void *)); 5745 }; 5746 5747 struct rtw89_link_conf_container { 5748 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS]; 5749 }; 5750 5751 #define RTW89_VIF_IDLE_LINK_ID 0 5752 5753 struct rtw89_vif { 5754 struct rtw89_dev *rtwdev; 5755 struct list_head list; 5756 struct list_head mgnt_entry; 5757 struct rtw89_link_conf_container __rcu *snap_link_confs; 5758 5759 u8 mac_addr[ETH_ALEN]; 5760 __be32 ip_addr; 5761 5762 struct rtw89_traffic_stats stats; 5763 u32 tdls_peer; 5764 5765 struct ieee80211_scan_ies *scan_ies; 5766 struct cfg80211_scan_request *scan_req; 5767 5768 struct rtw89_roc roc; 5769 bool offchan; 5770 5771 u8 links_inst_valid_num; 5772 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5773 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5774 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 5775 }; 5776 5777 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 5778 const struct rtw89_vif *rtwvif, 5779 unsigned int link_id) 5780 { 5781 *rtwvif_link = rtwvif->links[link_id]; 5782 return !!*rtwvif_link; 5783 } 5784 5785 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 5786 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5787 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 5788 5789 enum rtw89_sta_flags { 5790 RTW89_REMOTE_STA_IN_PS, 5791 5792 NUM_OF_RTW89_STA_FLAGS, 5793 }; 5794 5795 struct rtw89_sta { 5796 struct rtw89_dev *rtwdev; 5797 struct rtw89_vif *rtwvif; 5798 5799 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS); 5800 5801 bool disassoc; 5802 5803 struct sk_buff_head roc_queue; 5804 5805 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 5806 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 5807 5808 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 5809 5810 u8 links_inst_valid_num; 5811 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5812 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5813 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 5814 }; 5815 5816 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 5817 const struct rtw89_sta *rtwsta, 5818 unsigned int link_id) 5819 { 5820 *rtwsta_link = rtwsta->links[link_id]; 5821 return !!*rtwsta_link; 5822 } 5823 5824 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 5825 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5826 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 5827 5828 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 5829 { 5830 /* const after init, so no need to check if active first */ 5831 return rtwvif->links_inst[0].mac_id; 5832 } 5833 5834 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 5835 { 5836 /* const after init, so no need to check if active first */ 5837 return rtwvif->links_inst[0].port; 5838 } 5839 5840 static inline struct rtw89_vif_link * 5841 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 5842 { 5843 if (index >= rtwvif->links_inst_valid_num || 5844 !test_bit(index, rtwvif->links_inst_map)) 5845 return NULL; 5846 return &rtwvif->links_inst[index]; 5847 } 5848 5849 static inline 5850 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 5851 { 5852 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5853 5854 return rtwvif_link - rtwvif->links_inst; 5855 } 5856 5857 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 5858 { 5859 /* const after init, so no need to check if active first */ 5860 return rtwsta->links_inst[0].mac_id; 5861 } 5862 5863 static inline struct rtw89_sta_link * 5864 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 5865 { 5866 if (index >= rtwsta->links_inst_valid_num || 5867 !test_bit(index, rtwsta->links_inst_map)) 5868 return NULL; 5869 return &rtwsta->links_inst[index]; 5870 } 5871 5872 static inline 5873 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 5874 { 5875 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5876 5877 return rtwsta_link - rtwsta->links_inst; 5878 } 5879 5880 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link) 5881 { 5882 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5883 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 5884 5885 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 5886 rtwsta_link); 5887 } 5888 5889 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link) 5890 { 5891 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5892 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 5893 5894 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 5895 NULL); 5896 synchronize_rcu(); 5897 } 5898 5899 static inline struct rtw89_sta_link * 5900 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid) 5901 { 5902 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]); 5903 } 5904 5905 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 5906 struct rtw89_core_tx_request *tx_req) 5907 { 5908 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 5909 } 5910 5911 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 5912 { 5913 rtwdev->hci.ops->reset(rtwdev); 5914 } 5915 5916 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 5917 { 5918 return rtwdev->hci.ops->start(rtwdev); 5919 } 5920 5921 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 5922 { 5923 rtwdev->hci.ops->stop(rtwdev); 5924 } 5925 5926 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 5927 { 5928 return rtwdev->hci.ops->deinit(rtwdev); 5929 } 5930 5931 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 5932 { 5933 rtwdev->hci.ops->pause(rtwdev, pause); 5934 } 5935 5936 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 5937 { 5938 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 5939 } 5940 5941 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 5942 { 5943 rtwdev->hci.ops->recalc_int_mit(rtwdev); 5944 } 5945 5946 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 5947 { 5948 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 5949 } 5950 5951 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 5952 { 5953 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 5954 } 5955 5956 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 5957 { 5958 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 5959 } 5960 5961 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 5962 bool drop) 5963 { 5964 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5965 return; 5966 5967 if (rtwdev->hci.ops->flush_queues) 5968 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 5969 } 5970 5971 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 5972 { 5973 if (rtwdev->hci.ops->recovery_start) 5974 rtwdev->hci.ops->recovery_start(rtwdev); 5975 } 5976 5977 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 5978 { 5979 if (rtwdev->hci.ops->recovery_complete) 5980 rtwdev->hci.ops->recovery_complete(rtwdev); 5981 } 5982 5983 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 5984 { 5985 if (rtwdev->hci.ops->enable_intr) 5986 rtwdev->hci.ops->enable_intr(rtwdev); 5987 } 5988 5989 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 5990 { 5991 if (rtwdev->hci.ops->disable_intr) 5992 rtwdev->hci.ops->disable_intr(rtwdev); 5993 } 5994 5995 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 5996 { 5997 if (rtwdev->hci.ops->ctrl_txdma_ch) 5998 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 5999 } 6000 6001 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 6002 { 6003 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 6004 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 6005 } 6006 6007 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 6008 { 6009 if (rtwdev->hci.ops->ctrl_trxhci) 6010 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 6011 } 6012 6013 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 6014 { 6015 int ret = 0; 6016 6017 if (rtwdev->hci.ops->poll_txdma_ch_idle) 6018 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 6019 return ret; 6020 } 6021 6022 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 6023 { 6024 if (rtwdev->hci.ops->clr_idx_all) 6025 rtwdev->hci.ops->clr_idx_all(rtwdev); 6026 } 6027 6028 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 6029 { 6030 int ret = 0; 6031 6032 if (rtwdev->hci.ops->rst_bdram) 6033 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 6034 return ret; 6035 } 6036 6037 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 6038 { 6039 if (rtwdev->hci.ops->clear) 6040 rtwdev->hci.ops->clear(rtwdev, pdev); 6041 } 6042 6043 static inline 6044 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 6045 { 6046 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 6047 6048 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 6049 } 6050 6051 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 6052 { 6053 return rtwdev->hci.ops->read8(rtwdev, addr); 6054 } 6055 6056 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 6057 { 6058 return rtwdev->hci.ops->read16(rtwdev, addr); 6059 } 6060 6061 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 6062 { 6063 return rtwdev->hci.ops->read32(rtwdev, addr); 6064 } 6065 6066 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 6067 { 6068 rtwdev->hci.ops->write8(rtwdev, addr, data); 6069 } 6070 6071 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 6072 { 6073 rtwdev->hci.ops->write16(rtwdev, addr, data); 6074 } 6075 6076 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 6077 { 6078 rtwdev->hci.ops->write32(rtwdev, addr, data); 6079 } 6080 6081 static inline void 6082 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6083 { 6084 u8 val; 6085 6086 val = rtw89_read8(rtwdev, addr); 6087 rtw89_write8(rtwdev, addr, val | bit); 6088 } 6089 6090 static inline void 6091 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6092 { 6093 u16 val; 6094 6095 val = rtw89_read16(rtwdev, addr); 6096 rtw89_write16(rtwdev, addr, val | bit); 6097 } 6098 6099 static inline void 6100 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6101 { 6102 u32 val; 6103 6104 val = rtw89_read32(rtwdev, addr); 6105 rtw89_write32(rtwdev, addr, val | bit); 6106 } 6107 6108 static inline void 6109 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6110 { 6111 u8 val; 6112 6113 val = rtw89_read8(rtwdev, addr); 6114 rtw89_write8(rtwdev, addr, val & ~bit); 6115 } 6116 6117 static inline void 6118 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6119 { 6120 u16 val; 6121 6122 val = rtw89_read16(rtwdev, addr); 6123 rtw89_write16(rtwdev, addr, val & ~bit); 6124 } 6125 6126 static inline void 6127 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6128 { 6129 u32 val; 6130 6131 val = rtw89_read32(rtwdev, addr); 6132 rtw89_write32(rtwdev, addr, val & ~bit); 6133 } 6134 6135 static inline u32 6136 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6137 { 6138 u32 shift = __ffs(mask); 6139 u32 orig; 6140 u32 ret; 6141 6142 orig = rtw89_read32(rtwdev, addr); 6143 ret = (orig & mask) >> shift; 6144 6145 return ret; 6146 } 6147 6148 static inline u16 6149 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6150 { 6151 u32 shift = __ffs(mask); 6152 u32 orig; 6153 u32 ret; 6154 6155 orig = rtw89_read16(rtwdev, addr); 6156 ret = (orig & mask) >> shift; 6157 6158 return ret; 6159 } 6160 6161 static inline u8 6162 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6163 { 6164 u32 shift = __ffs(mask); 6165 u32 orig; 6166 u32 ret; 6167 6168 orig = rtw89_read8(rtwdev, addr); 6169 ret = (orig & mask) >> shift; 6170 6171 return ret; 6172 } 6173 6174 static inline void 6175 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 6176 { 6177 u32 shift = __ffs(mask); 6178 u32 orig; 6179 u32 set; 6180 6181 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 6182 6183 orig = rtw89_read32(rtwdev, addr); 6184 set = (orig & ~mask) | ((data << shift) & mask); 6185 rtw89_write32(rtwdev, addr, set); 6186 } 6187 6188 static inline void 6189 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 6190 { 6191 u32 shift; 6192 u16 orig, set; 6193 6194 mask &= 0xffff; 6195 shift = __ffs(mask); 6196 6197 orig = rtw89_read16(rtwdev, addr); 6198 set = (orig & ~mask) | ((data << shift) & mask); 6199 rtw89_write16(rtwdev, addr, set); 6200 } 6201 6202 static inline void 6203 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 6204 { 6205 u32 shift; 6206 u8 orig, set; 6207 6208 mask &= 0xff; 6209 shift = __ffs(mask); 6210 6211 orig = rtw89_read8(rtwdev, addr); 6212 set = (orig & ~mask) | ((data << shift) & mask); 6213 rtw89_write8(rtwdev, addr, set); 6214 } 6215 6216 static inline u32 6217 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6218 u32 addr, u32 mask) 6219 { 6220 u32 val; 6221 6222 mutex_lock(&rtwdev->rf_mutex); 6223 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 6224 mutex_unlock(&rtwdev->rf_mutex); 6225 6226 return val; 6227 } 6228 6229 static inline void 6230 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6231 u32 addr, u32 mask, u32 data) 6232 { 6233 mutex_lock(&rtwdev->rf_mutex); 6234 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 6235 mutex_unlock(&rtwdev->rf_mutex); 6236 } 6237 6238 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 6239 { 6240 void *p = rtwtxq; 6241 6242 return container_of(p, struct ieee80211_txq, drv_priv); 6243 } 6244 6245 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 6246 struct ieee80211_txq *txq) 6247 { 6248 struct rtw89_txq *rtwtxq; 6249 6250 if (!txq) 6251 return; 6252 6253 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 6254 INIT_LIST_HEAD(&rtwtxq->list); 6255 } 6256 6257 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 6258 { 6259 void *p = rtwvif; 6260 6261 return container_of(p, struct ieee80211_vif, drv_priv); 6262 } 6263 6264 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 6265 { 6266 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 6267 } 6268 6269 static inline 6270 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 6271 { 6272 return rtwvif_to_vif(rtwvif_link->rtwvif); 6273 } 6274 6275 static inline 6276 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 6277 { 6278 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 6279 } 6280 6281 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 6282 { 6283 return (struct rtw89_vif *)vif->drv_priv; 6284 } 6285 6286 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 6287 { 6288 return vif ? vif_to_rtwvif(vif) : NULL; 6289 } 6290 6291 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 6292 { 6293 void *p = rtwsta; 6294 6295 return container_of(p, struct ieee80211_sta, drv_priv); 6296 } 6297 6298 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 6299 { 6300 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 6301 } 6302 6303 static inline 6304 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 6305 { 6306 return rtwsta_to_sta(rtwsta_link->rtwsta); 6307 } 6308 6309 static inline 6310 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 6311 { 6312 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 6313 } 6314 6315 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 6316 { 6317 return (struct rtw89_sta *)sta->drv_priv; 6318 } 6319 6320 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 6321 { 6322 return sta ? sta_to_rtwsta(sta) : NULL; 6323 } 6324 6325 static inline struct ieee80211_bss_conf * 6326 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 6327 { 6328 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6329 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6330 struct rtw89_link_conf_container *snap; 6331 struct ieee80211_bss_conf *bss_conf; 6332 6333 snap = rcu_dereference(rtwvif->snap_link_confs); 6334 if (snap) { 6335 bss_conf = snap->link_conf[rtwvif_link->link_id]; 6336 goto out; 6337 } 6338 6339 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 6340 6341 out: 6342 if (unlikely(!bss_conf)) { 6343 *nolink = true; 6344 return &vif->bss_conf; 6345 } 6346 6347 *nolink = false; 6348 return bss_conf; 6349 } 6350 6351 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 6352 ({ \ 6353 typeof(rtwvif_link) p = rtwvif_link; \ 6354 struct ieee80211_bss_conf *bss_conf; \ 6355 bool nolink; \ 6356 \ 6357 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 6358 if (unlikely(nolink) && (assert)) \ 6359 rtw89_err(p->rtwvif->rtwdev, \ 6360 "%s: cannot find exact bss_conf for link_id %u\n",\ 6361 __func__, p->link_id); \ 6362 bss_conf; \ 6363 }) 6364 6365 static inline struct ieee80211_link_sta * 6366 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 6367 { 6368 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6369 struct ieee80211_link_sta *link_sta; 6370 6371 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 6372 if (unlikely(!link_sta)) { 6373 *nolink = true; 6374 return &sta->deflink; 6375 } 6376 6377 *nolink = false; 6378 return link_sta; 6379 } 6380 6381 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 6382 ({ \ 6383 typeof(rtwsta_link) p = rtwsta_link; \ 6384 struct ieee80211_link_sta *link_sta; \ 6385 bool nolink; \ 6386 \ 6387 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 6388 if (unlikely(nolink) && (assert)) \ 6389 rtw89_err(p->rtwsta->rtwdev, \ 6390 "%s: cannot find exact link_sta for link_id %u\n",\ 6391 __func__, p->link_id); \ 6392 link_sta; \ 6393 }) 6394 6395 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 6396 { 6397 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 6398 return RATE_INFO_BW_160; 6399 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 6400 return RATE_INFO_BW_80; 6401 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 6402 return RATE_INFO_BW_40; 6403 else 6404 return RATE_INFO_BW_20; 6405 } 6406 6407 static inline 6408 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 6409 { 6410 switch (hw_band) { 6411 default: 6412 case RTW89_BAND_2G: 6413 return NL80211_BAND_2GHZ; 6414 case RTW89_BAND_5G: 6415 return NL80211_BAND_5GHZ; 6416 case RTW89_BAND_6G: 6417 return NL80211_BAND_6GHZ; 6418 } 6419 } 6420 6421 static inline 6422 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 6423 { 6424 switch (nl_band) { 6425 default: 6426 case NL80211_BAND_2GHZ: 6427 return RTW89_BAND_2G; 6428 case NL80211_BAND_5GHZ: 6429 return RTW89_BAND_5G; 6430 case NL80211_BAND_6GHZ: 6431 return RTW89_BAND_6G; 6432 } 6433 } 6434 6435 static inline 6436 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 6437 { 6438 switch (width) { 6439 default: 6440 WARN(1, "Not support bandwidth %d\n", width); 6441 fallthrough; 6442 case NL80211_CHAN_WIDTH_20_NOHT: 6443 case NL80211_CHAN_WIDTH_20: 6444 return RTW89_CHANNEL_WIDTH_20; 6445 case NL80211_CHAN_WIDTH_40: 6446 return RTW89_CHANNEL_WIDTH_40; 6447 case NL80211_CHAN_WIDTH_80: 6448 return RTW89_CHANNEL_WIDTH_80; 6449 case NL80211_CHAN_WIDTH_160: 6450 return RTW89_CHANNEL_WIDTH_160; 6451 } 6452 } 6453 6454 static inline 6455 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 6456 { 6457 switch (rua) { 6458 default: 6459 WARN(1, "Invalid RU allocation: %d\n", rua); 6460 fallthrough; 6461 case 0 ... 36: 6462 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 6463 case 37 ... 52: 6464 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 6465 case 53 ... 60: 6466 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 6467 case 61 ... 64: 6468 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 6469 case 65 ... 66: 6470 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 6471 case 67: 6472 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 6473 case 68: 6474 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 6475 } 6476 } 6477 6478 static inline 6479 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 6480 struct rtw89_sta_link *rtwsta_link) 6481 { 6482 if (rtwsta_link) { 6483 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6484 6485 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 6486 return &rtwsta_link->addr_cam; 6487 } 6488 return &rtwvif_link->addr_cam; 6489 } 6490 6491 static inline 6492 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 6493 struct rtw89_sta_link *rtwsta_link) 6494 { 6495 if (rtwsta_link) { 6496 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6497 6498 if (sta->tdls) 6499 return &rtwsta_link->bssid_cam; 6500 } 6501 return &rtwvif_link->bssid_cam; 6502 } 6503 6504 static inline 6505 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 6506 struct rtw89_channel_help_params *p, 6507 const struct rtw89_chan *chan, 6508 enum rtw89_mac_idx mac_idx, 6509 enum rtw89_phy_idx phy_idx) 6510 { 6511 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 6512 mac_idx, phy_idx); 6513 } 6514 6515 static inline 6516 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 6517 struct rtw89_channel_help_params *p, 6518 const struct rtw89_chan *chan, 6519 enum rtw89_mac_idx mac_idx, 6520 enum rtw89_phy_idx phy_idx) 6521 { 6522 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 6523 mac_idx, phy_idx); 6524 } 6525 6526 static inline 6527 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 6528 enum rtw89_chanctx_idx idx) 6529 { 6530 struct rtw89_hal *hal = &rtwdev->hal; 6531 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 6532 6533 if (roc_idx == idx) 6534 return &hal->roc_chandef; 6535 6536 return &hal->chanctx[idx].chandef; 6537 } 6538 6539 static inline 6540 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 6541 enum rtw89_chanctx_idx idx) 6542 { 6543 struct rtw89_hal *hal = &rtwdev->hal; 6544 6545 return &hal->chanctx[idx].chan; 6546 } 6547 6548 static inline 6549 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 6550 enum rtw89_chanctx_idx idx) 6551 { 6552 struct rtw89_hal *hal = &rtwdev->hal; 6553 6554 return &hal->chanctx[idx].rcd; 6555 } 6556 6557 static inline 6558 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan) 6559 { 6560 const struct rtw89_chanctx *chanctx = 6561 container_of_const(chan, struct rtw89_chanctx, chan); 6562 6563 return &chanctx->rcd; 6564 } 6565 6566 static inline 6567 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 6568 { 6569 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 6570 6571 if (rtwvif_link) 6572 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 6573 else 6574 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 6575 } 6576 6577 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 6578 { 6579 const struct rtw89_chip_info *chip = rtwdev->chip; 6580 6581 if (chip->ops->fem_setup) 6582 chip->ops->fem_setup(rtwdev); 6583 } 6584 6585 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 6586 { 6587 const struct rtw89_chip_info *chip = rtwdev->chip; 6588 6589 if (chip->ops->rfe_gpio) 6590 chip->ops->rfe_gpio(rtwdev); 6591 } 6592 6593 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 6594 { 6595 const struct rtw89_chip_info *chip = rtwdev->chip; 6596 6597 if (chip->ops->rfk_hw_init) 6598 chip->ops->rfk_hw_init(rtwdev); 6599 } 6600 6601 static inline 6602 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 6603 { 6604 const struct rtw89_chip_info *chip = rtwdev->chip; 6605 6606 if (chip->ops->bb_preinit) 6607 chip->ops->bb_preinit(rtwdev, phy_idx); 6608 } 6609 6610 static inline 6611 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 6612 { 6613 const struct rtw89_chip_info *chip = rtwdev->chip; 6614 6615 if (!chip->ops->bb_postinit) 6616 return; 6617 6618 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 6619 6620 if (rtwdev->dbcc_en) 6621 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 6622 } 6623 6624 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 6625 { 6626 const struct rtw89_chip_info *chip = rtwdev->chip; 6627 6628 if (chip->ops->bb_sethw) 6629 chip->ops->bb_sethw(rtwdev); 6630 } 6631 6632 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 6633 { 6634 const struct rtw89_chip_info *chip = rtwdev->chip; 6635 6636 if (chip->ops->rfk_init) 6637 chip->ops->rfk_init(rtwdev); 6638 } 6639 6640 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 6641 { 6642 const struct rtw89_chip_info *chip = rtwdev->chip; 6643 6644 if (chip->ops->rfk_init_late) 6645 chip->ops->rfk_init_late(rtwdev); 6646 } 6647 6648 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 6649 struct rtw89_vif_link *rtwvif_link) 6650 { 6651 const struct rtw89_chip_info *chip = rtwdev->chip; 6652 6653 if (chip->ops->rfk_channel) 6654 chip->ops->rfk_channel(rtwdev, rtwvif_link); 6655 } 6656 6657 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 6658 enum rtw89_phy_idx phy_idx, 6659 const struct rtw89_chan *chan) 6660 { 6661 const struct rtw89_chip_info *chip = rtwdev->chip; 6662 6663 if (chip->ops->rfk_band_changed) 6664 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 6665 } 6666 6667 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 6668 struct rtw89_vif_link *rtwvif_link, bool start) 6669 { 6670 const struct rtw89_chip_info *chip = rtwdev->chip; 6671 6672 if (chip->ops->rfk_scan) 6673 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 6674 } 6675 6676 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 6677 { 6678 const struct rtw89_chip_info *chip = rtwdev->chip; 6679 6680 if (chip->ops->rfk_track) 6681 chip->ops->rfk_track(rtwdev); 6682 } 6683 6684 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 6685 { 6686 const struct rtw89_chip_info *chip = rtwdev->chip; 6687 6688 if (!chip->ops->set_txpwr_ctrl) 6689 return; 6690 6691 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 6692 if (rtwdev->dbcc_en) 6693 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 6694 } 6695 6696 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 6697 { 6698 const struct rtw89_chip_info *chip = rtwdev->chip; 6699 6700 if (chip->ops->power_trim) 6701 chip->ops->power_trim(rtwdev); 6702 } 6703 6704 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 6705 enum rtw89_phy_idx phy_idx) 6706 { 6707 const struct rtw89_chip_info *chip = rtwdev->chip; 6708 6709 if (chip->ops->init_txpwr_unit) 6710 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 6711 } 6712 6713 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 6714 { 6715 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 6716 if (rtwdev->dbcc_en) 6717 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 6718 } 6719 6720 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 6721 enum rtw89_rf_path rf_path) 6722 { 6723 const struct rtw89_chip_info *chip = rtwdev->chip; 6724 6725 if (!chip->ops->get_thermal) 6726 return 0x10; 6727 6728 return chip->ops->get_thermal(rtwdev, rf_path); 6729 } 6730 6731 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 6732 struct rtw89_rx_phy_ppdu *phy_ppdu, 6733 struct ieee80211_rx_status *status) 6734 { 6735 const struct rtw89_chip_info *chip = rtwdev->chip; 6736 6737 if (chip->ops->query_ppdu) 6738 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 6739 } 6740 6741 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 6742 struct rtw89_rx_phy_ppdu *phy_ppdu) 6743 { 6744 const struct rtw89_chip_info *chip = rtwdev->chip; 6745 6746 if (chip->ops->convert_rpl_to_rssi) 6747 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 6748 } 6749 6750 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev, 6751 struct rtw89_rx_desc_info *desc_info, 6752 struct ieee80211_rx_status *rx_status) 6753 { 6754 const struct rtw89_chip_info *chip = rtwdev->chip; 6755 6756 if (chip->ops->phy_rpt_to_rssi) 6757 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 6758 } 6759 6760 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 6761 enum rtw89_phy_idx phy_idx) 6762 { 6763 const struct rtw89_chip_info *chip = rtwdev->chip; 6764 6765 if (chip->ops->ctrl_nbtg_bt_tx) 6766 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 6767 } 6768 6769 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 6770 { 6771 const struct rtw89_chip_info *chip = rtwdev->chip; 6772 6773 if (chip->ops->cfg_txrx_path) 6774 chip->ops->cfg_txrx_path(rtwdev); 6775 } 6776 6777 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 6778 enum rtw89_phy_idx phy_idx) 6779 { 6780 const struct rtw89_chip_info *chip = rtwdev->chip; 6781 6782 if (chip->ops->digital_pwr_comp) 6783 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 6784 } 6785 6786 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 6787 const struct rtw89_txpwr_table *tbl) 6788 { 6789 tbl->load(rtwdev, tbl); 6790 } 6791 6792 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 6793 { 6794 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 6795 6796 return regd->txpwr_regd[band]; 6797 } 6798 6799 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 6800 enum rtw89_phy_idx phy_idx) 6801 { 6802 const struct rtw89_chip_info *chip = rtwdev->chip; 6803 6804 if (chip->ops->ctrl_btg_bt_rx) 6805 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 6806 } 6807 6808 static inline 6809 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 6810 struct rtw89_rx_desc_info *desc_info, 6811 u8 *data, u32 data_offset) 6812 { 6813 const struct rtw89_chip_info *chip = rtwdev->chip; 6814 6815 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 6816 } 6817 6818 static inline 6819 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 6820 struct rtw89_tx_desc_info *desc_info, 6821 void *txdesc) 6822 { 6823 const struct rtw89_chip_info *chip = rtwdev->chip; 6824 6825 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 6826 } 6827 6828 static inline 6829 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 6830 struct rtw89_tx_desc_info *desc_info, 6831 void *txdesc) 6832 { 6833 const struct rtw89_chip_info *chip = rtwdev->chip; 6834 6835 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 6836 } 6837 6838 static inline 6839 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6840 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6841 { 6842 const struct rtw89_chip_info *chip = rtwdev->chip; 6843 6844 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 6845 } 6846 6847 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6848 { 6849 const struct rtw89_chip_info *chip = rtwdev->chip; 6850 6851 chip->ops->cfg_ctrl_path(rtwdev, wl); 6852 } 6853 6854 static inline 6855 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 6856 u32 *tx_en, enum rtw89_sch_tx_sel sel) 6857 { 6858 const struct rtw89_chip_info *chip = rtwdev->chip; 6859 6860 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 6861 } 6862 6863 static inline 6864 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 6865 { 6866 const struct rtw89_chip_info *chip = rtwdev->chip; 6867 6868 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 6869 } 6870 6871 static inline 6872 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 6873 struct rtw89_vif_link *rtwvif_link, 6874 struct rtw89_sta_link *rtwsta_link) 6875 { 6876 const struct rtw89_chip_info *chip = rtwdev->chip; 6877 6878 if (!chip->ops->h2c_dctl_sec_cam) 6879 return 0; 6880 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 6881 } 6882 6883 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 6884 { 6885 __le16 fc = hdr->frame_control; 6886 6887 if (ieee80211_has_tods(fc)) 6888 return hdr->addr1; 6889 else if (ieee80211_has_fromds(fc)) 6890 return hdr->addr2; 6891 else 6892 return hdr->addr3; 6893 } 6894 6895 static inline 6896 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 6897 { 6898 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6899 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 6900 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 6901 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6902 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 6903 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 6904 return true; 6905 return false; 6906 } 6907 6908 static inline 6909 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta) 6910 { 6911 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] & 6912 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI) 6913 return true; 6914 6915 return false; 6916 } 6917 6918 static inline 6919 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta) 6920 { 6921 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] & 6922 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI) 6923 return true; 6924 6925 return false; 6926 } 6927 6928 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 6929 #if defined(__linux__) 6930 enum rtw89_fw_type type) 6931 #elif defined(__FreeBSD__) 6932 const enum rtw89_fw_type type) 6933 #endif 6934 { 6935 struct rtw89_fw_info *fw_info = &rtwdev->fw; 6936 6937 switch (type) { 6938 case RTW89_FW_WOWLAN: 6939 return &fw_info->wowlan; 6940 case RTW89_FW_LOGFMT: 6941 return &fw_info->log.suit; 6942 case RTW89_FW_BBMCU0: 6943 return &fw_info->bbmcu0; 6944 case RTW89_FW_BBMCU1: 6945 return &fw_info->bbmcu1; 6946 default: 6947 break; 6948 } 6949 6950 return &fw_info->normal; 6951 } 6952 6953 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 6954 unsigned int length) 6955 { 6956 struct sk_buff *skb; 6957 6958 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 6959 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 6960 if (!skb) 6961 return NULL; 6962 6963 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 6964 return skb; 6965 } 6966 6967 return dev_alloc_skb(length); 6968 } 6969 6970 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 6971 struct rtw89_tx_skb_data *skb_data, 6972 bool tx_done) 6973 { 6974 struct rtw89_tx_wait_info *wait; 6975 6976 rcu_read_lock(); 6977 6978 wait = rcu_dereference(skb_data->wait); 6979 if (!wait) 6980 goto out; 6981 6982 wait->tx_done = tx_done; 6983 complete(&wait->completion); 6984 6985 out: 6986 rcu_read_unlock(); 6987 } 6988 6989 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 6990 { 6991 switch (rtwdev->mlo_dbcc_mode) { 6992 case MLO_1_PLUS_1_1RF: 6993 case MLO_1_PLUS_1_2RF: 6994 case DBCC_LEGACY: 6995 return true; 6996 default: 6997 return false; 6998 } 6999 } 7000 7001 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 7002 { 7003 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 7004 7005 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 7006 return true; 7007 7008 return false; 7009 } 7010 7011 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 7012 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 7013 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 7014 struct sk_buff *skb, bool fwdl); 7015 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 7016 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 7017 int qsel, unsigned int timeout); 7018 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 7019 struct rtw89_tx_desc_info *desc_info, 7020 void *txdesc); 7021 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 7022 struct rtw89_tx_desc_info *desc_info, 7023 void *txdesc); 7024 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 7025 struct rtw89_tx_desc_info *desc_info, 7026 void *txdesc); 7027 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 7028 struct rtw89_tx_desc_info *desc_info, 7029 void *txdesc); 7030 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 7031 struct rtw89_tx_desc_info *desc_info, 7032 void *txdesc); 7033 void rtw89_core_rx(struct rtw89_dev *rtwdev, 7034 struct rtw89_rx_desc_info *desc_info, 7035 struct sk_buff *skb); 7036 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 7037 struct rtw89_rx_desc_info *desc_info, 7038 u8 *data, u32 data_offset); 7039 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 7040 struct rtw89_rx_desc_info *desc_info, 7041 u8 *data, u32 data_offset); 7042 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 7043 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 7044 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 7045 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 7046 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 7047 struct rtw89_vif_link *rtwvif_link, 7048 struct rtw89_sta_link *rtwsta_link); 7049 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 7050 struct rtw89_vif_link *rtwvif_link, 7051 struct rtw89_sta_link *rtwsta_link); 7052 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 7053 struct rtw89_vif_link *rtwvif_link, 7054 struct rtw89_sta_link *rtwsta_link); 7055 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 7056 struct rtw89_vif_link *rtwvif_link, 7057 struct rtw89_sta_link *rtwsta_link); 7058 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 7059 struct rtw89_vif_link *rtwvif_link, 7060 struct rtw89_sta_link *rtwsta_link); 7061 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 7062 struct ieee80211_sta *sta, 7063 struct cfg80211_tid_config *tid_config); 7064 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 7065 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 7066 int rtw89_core_init(struct rtw89_dev *rtwdev); 7067 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 7068 int rtw89_core_register(struct rtw89_dev *rtwdev); 7069 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 7070 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 7071 u32 bus_data_size, 7072 const struct rtw89_chip_info *chip, 7073 const struct rtw89_chip_variant *variant); 7074 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 7075 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 7076 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 7077 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7078 u8 mac_id, u8 port); 7079 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7080 struct rtw89_sta *rtwsta, u8 mac_id); 7081 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 7082 unsigned int link_id); 7083 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 7084 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 7085 unsigned int link_id); 7086 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 7087 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 7088 const struct rtw89_6ghz_span * 7089 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq); 7090 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 7091 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 7092 struct rtw89_chan *chan); 7093 int rtw89_set_channel(struct rtw89_dev *rtwdev); 7094 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 7095 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 7096 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 7097 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 7098 struct rtw89_sta_link *rtwsta_link, u8 tid, 7099 u8 *cam_idx); 7100 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 7101 struct rtw89_sta_link *rtwsta_link, u8 tid, 7102 u8 *cam_idx); 7103 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 7104 struct ieee80211_sta *sta); 7105 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 7106 struct ieee80211_sta *sta); 7107 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 7108 struct ieee80211_sta *sta); 7109 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 7110 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 7111 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 7112 struct rtw89_vif_link *rtwvif_link); 7113 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 7114 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 7115 int rtw89_regd_init(struct rtw89_dev *rtwdev, 7116 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 7117 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 7118 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 7119 struct rtw89_traffic_stats *stats); 7120 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 7121 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 7122 const struct rtw89_completion_data *data); 7123 int rtw89_core_start(struct rtw89_dev *rtwdev); 7124 void rtw89_core_stop(struct rtw89_dev *rtwdev); 7125 void rtw89_core_update_beacon_work(struct work_struct *work); 7126 void rtw89_roc_work(struct work_struct *work); 7127 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7128 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7129 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7130 const u8 *mac_addr, bool hw_scan); 7131 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 7132 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 7133 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7134 bool active); 7135 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 7136 struct rtw89_vif_link *rtwvif_link, 7137 struct ieee80211_bss_conf *bss_conf); 7138 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 7139 7140 #if defined(__linux__) 7141 #define rtw89_static_assert(_x) static_assert(_x) 7142 #elif defined(__FreeBSD__) 7143 #define rtw89_static_assert(_x) _Static_assert(_x, "bad array size") 7144 #endif 7145 7146 #endif 7147