1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2022-2023 Realtek Corporation
3 */
4
5 #include "coex.h"
6 #include "efuse.h"
7 #include "fw.h"
8 #include "mac.h"
9 #include "phy.h"
10 #include "reg.h"
11 #include "rtw8851b.h"
12 #include "rtw8851b_rfk.h"
13 #include "rtw8851b_rfk_table.h"
14 #include "rtw8851b_table.h"
15 #include "txrx.h"
16 #include "util.h"
17
18 #define RTW8851B_FW_FORMAT_MAX 0
19 #define RTW8851B_FW_BASENAME "rtw89/rtw8851b_fw"
20 #define RTW8851B_MODULE_FIRMWARE \
21 RTW8851B_FW_BASENAME ".bin"
22
23 static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_pcie[] = {
24 {5, 343, grp_0}, /* ACH 0 */
25 {5, 343, grp_0}, /* ACH 1 */
26 {5, 343, grp_0}, /* ACH 2 */
27 {5, 343, grp_0}, /* ACH 3 */
28 {0, 0, grp_0}, /* ACH 4 */
29 {0, 0, grp_0}, /* ACH 5 */
30 {0, 0, grp_0}, /* ACH 6 */
31 {0, 0, grp_0}, /* ACH 7 */
32 {4, 344, grp_0}, /* B0MGQ */
33 {4, 344, grp_0}, /* B0HIQ */
34 {0, 0, grp_0}, /* B1MGQ */
35 {0, 0, grp_0}, /* B1HIQ */
36 {40, 0, 0} /* FWCMDQ */
37 };
38
39 static const struct rtw89_hfc_pub_cfg rtw8851b_hfc_pubcfg_pcie = {
40 448, /* Group 0 */
41 0, /* Group 1 */
42 448, /* Public Max */
43 0 /* WP threshold */
44 };
45
46 static const struct rtw89_hfc_param_ini rtw8851b_hfc_param_ini_pcie[] = {
47 [RTW89_QTA_SCC] = {rtw8851b_hfc_chcfg_pcie, &rtw8851b_hfc_pubcfg_pcie,
48 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
49 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
50 RTW89_HCIFC_POH},
51 [RTW89_QTA_INVALID] = {NULL},
52 };
53
54 static const struct rtw89_dle_mem rtw8851b_dle_mem_pcie[] = {
55 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size6,
56 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6,
57 &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18,
58 &rtw89_mac_size.ple_qt58},
59 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size6,
60 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6,
61 &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18,
62 &rtw89_mac_size.ple_qt_51b_wow},
63 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
64 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
65 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
66 &rtw89_mac_size.ple_qt13},
67 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
68 NULL},
69 };
70
71 static const struct rtw89_reg3_def rtw8851b_btc_preagc_en_defs[] = {
72 {0x46D0, GENMASK(1, 0), 0x3},
73 {0x4AD4, GENMASK(31, 0), 0xf},
74 {0x4688, GENMASK(23, 16), 0x80},
75 {0x4688, GENMASK(31, 24), 0x80},
76 {0x4694, GENMASK(7, 0), 0x80},
77 {0x4694, GENMASK(15, 8), 0x80},
78 {0x4AE4, GENMASK(11, 6), 0x34},
79 {0x4AE4, GENMASK(17, 12), 0x0},
80 {0x469C, GENMASK(31, 26), 0x34},
81 };
82
83 static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_en_defs);
84
85 static const struct rtw89_reg3_def rtw8851b_btc_preagc_dis_defs[] = {
86 {0x46D0, GENMASK(1, 0), 0x0},
87 {0x4AD4, GENMASK(31, 0), 0x60},
88 {0x4688, GENMASK(23, 16), 0x10},
89 {0x4690, GENMASK(31, 24), 0x2a},
90 {0x4694, GENMASK(15, 8), 0x2a},
91 {0x4AE4, GENMASK(11, 6), 0x26},
92 {0x4AE4, GENMASK(17, 12), 0x1e},
93 {0x469C, GENMASK(31, 26), 0x26},
94 };
95
96 static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_dis_defs);
97
98 static const u32 rtw8851b_h2c_regs[RTW89_H2CREG_MAX] = {
99 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
100 R_AX_H2CREG_DATA3
101 };
102
103 static const u32 rtw8851b_c2h_regs[RTW89_C2HREG_MAX] = {
104 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
105 R_AX_C2HREG_DATA3
106 };
107
108 static const u32 rtw8851b_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
109 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3,
110 };
111
112 static const struct rtw89_page_regs rtw8851b_page_regs = {
113 .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
114 .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
115 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
116 .ach_page_info = R_AX_ACH0_PAGE_INFO,
117 .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
118 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
119 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
120 .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
121 .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
122 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
123 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
124 .wp_page_info1 = R_AX_WP_PAGE_INFO1,
125 };
126
127 static const struct rtw89_reg_def rtw8851b_dcfo_comp = {
128 R_DCFO_COMP_S0_V2, B_DCFO_COMP_S0_MSK_V2
129 };
130
131 static const struct rtw89_imr_info rtw8851b_imr_info = {
132 .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
133 .wsec_imr_reg = R_AX_SEC_DEBUG,
134 .wsec_imr_set = B_AX_IMR_ERROR,
135 .mpdu_tx_imr_set = 0,
136 .mpdu_rx_imr_set = 0,
137 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
138 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
139 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
140 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
141 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
142 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
143 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
144 .wde_imr_clr = B_AX_WDE_IMR_CLR,
145 .wde_imr_set = B_AX_WDE_IMR_SET,
146 .ple_imr_clr = B_AX_PLE_IMR_CLR,
147 .ple_imr_set = B_AX_PLE_IMR_SET,
148 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
149 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
150 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
151 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
152 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
153 .other_disp_imr_set = 0,
154 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
155 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
156 .bbrpt_err_imr_set = 0,
157 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
158 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL,
159 .ptcl_imr_set = B_AX_PTCL_IMR_SET,
160 .cdma_imr_0_reg = R_AX_DLE_CTRL,
161 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
162 .cdma_imr_0_set = B_AX_DLE_IMR_SET,
163 .cdma_imr_1_reg = 0,
164 .cdma_imr_1_clr = 0,
165 .cdma_imr_1_set = 0,
166 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
167 .phy_intf_imr_clr = 0,
168 .phy_intf_imr_set = 0,
169 .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
170 .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
171 .rmac_imr_set = B_AX_RMAC_IMR_SET,
172 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
173 .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
174 .tmac_imr_set = B_AX_TMAC_IMR_SET,
175 };
176
177 static const struct rtw89_xtal_info rtw8851b_xtal_info = {
178 .xcap_reg = R_AX_XTAL_ON_CTRL3,
179 .sc_xo_mask = B_AX_XTAL_SC_XO_A_BLOCK_MASK,
180 .sc_xi_mask = B_AX_XTAL_SC_XI_A_BLOCK_MASK,
181 };
182
183 static const struct rtw89_rrsr_cfgs rtw8851b_rrsr_cfgs = {
184 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
185 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
186 };
187
188 static const struct rtw89_rfkill_regs rtw8851b_rfkill_regs = {
189 .pinmux = {R_AX_GPIO8_15_FUNC_SEL,
190 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK,
191 0xf},
192 .mode = {R_AX_GPIO_EXT_CTRL + 2,
193 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16,
194 0x0},
195 };
196
197 static const struct rtw89_dig_regs rtw8851b_dig_regs = {
198 .seg0_pd_reg = R_SEG0R_PD_V1,
199 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
200 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
201 .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
202 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
203 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
204 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
205 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
206 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
207 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
208 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
209 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
210 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
211 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2,
212 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
213 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2,
214 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
215 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2,
216 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
217 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2,
218 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
219 };
220
221 static const struct rtw89_edcca_regs rtw8851b_edcca_regs = {
222 .edcca_level = R_SEG0R_EDCCA_LVL_V1,
223 .edcca_mask = B_EDCCA_LVL_MSK0,
224 .edcca_p_mask = B_EDCCA_LVL_MSK1,
225 .ppdu_level = R_SEG0R_EDCCA_LVL_V1,
226 .ppdu_mask = B_EDCCA_LVL_MSK3,
227 .p = {{
228 .rpt_a = R_EDCCA_RPT_A,
229 .rpt_b = R_EDCCA_RPT_B,
230 .rpt_sel = R_EDCCA_RPT_SEL,
231 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK,
232 }, {
233 .rpt_a = R_EDCCA_RPT_P1_A,
234 .rpt_b = R_EDCCA_RPT_P1_B,
235 .rpt_sel = R_EDCCA_RPT_SEL,
236 .rpt_sel_mask = B_EDCCA_RPT_SEL_P1_MSK,
237 }},
238 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST,
239 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
240 };
241
242 static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_ul[] = {
243 {255, 0, 0, 7}, /* 0 -> original */
244 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
245 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
246 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
247 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
248 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
249 {6, 1, 0, 7},
250 {13, 1, 0, 7},
251 {13, 1, 0, 7}
252 };
253
254 static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_dl[] = {
255 {255, 0, 0, 7}, /* 0 -> original */
256 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
257 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
258 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
259 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
260 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
261 {255, 1, 0, 7},
262 {255, 1, 0, 7},
263 {255, 1, 0, 7}
264 };
265
266 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8851b_mon_reg[] = {
267 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
268 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
269 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
270 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
271 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
272 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
273 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
274 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
275 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
276 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
277 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
278 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
279 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
280 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738),
281 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688),
282 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694),
283 };
284
285 static const u8 rtw89_btc_8851b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40};
286 static const u8 rtw89_btc_8851b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
287
rtw8851b_pwr_on_func(struct rtw89_dev * rtwdev)288 static int rtw8851b_pwr_on_func(struct rtw89_dev *rtwdev)
289 {
290 u32 val32;
291 u8 val8;
292 int ret;
293
294 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
295 B_AX_AFSM_PCIE_SUS_EN);
296 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
297 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
298 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
299 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
300
301 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
302 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
303 if (ret)
304 return ret;
305
306 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
307 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
308
309 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
310 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
311 if (ret)
312 return ret;
313
314 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
315 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
316 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
317 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
318
319 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
320 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
321
322 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
323 XTAL_SI_OFF_WEI);
324 if (ret)
325 return ret;
326 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
327 XTAL_SI_OFF_EI);
328 if (ret)
329 return ret;
330 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
331 if (ret)
332 return ret;
333 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
334 XTAL_SI_PON_WEI);
335 if (ret)
336 return ret;
337 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
338 XTAL_SI_PON_EI);
339 if (ret)
340 return ret;
341 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
342 if (ret)
343 return ret;
344 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
345 if (ret)
346 return ret;
347 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
348 if (ret)
349 return ret;
350 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
351 if (ret)
352 return ret;
353 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_DRV, 0, XTAL_SI_DRV_LATCH);
354 if (ret)
355 return ret;
356
357 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
358 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
359 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
360
361 fsleep(1000);
362
363 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
364 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
365 rtw89_write32_set(rtwdev, R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN,
366 B_AX_GPIO10_PULL_LOW_EN | B_AX_GPIO16_PULL_LOW_EN_V1);
367
368 if (rtwdev->hal.cv == CHIP_CAV) {
369 ret = rtw89_read_efuse_ver(rtwdev, &val8);
370 if (!ret)
371 rtwdev->hal.cv = val8;
372 }
373
374 rtw89_write32_clr(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
375 B_AX_XTAL_SI_ADDR_NOT_CHK);
376 if (rtwdev->hal.cv != CHIP_CAV) {
377 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
378 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
379 }
380
381 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
382 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
383 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
384 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
385 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
386 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
387 B_AX_DMACREG_GCKEN);
388 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
389 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
390 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN |
391 B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN |
392 B_AX_RMAC_EN);
393
394 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
395 PINMUX_EESK_FUNC_SEL_BT_LOG);
396
397 return 0;
398 }
399
rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev * rtwdev)400 static void rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev *rtwdev)
401 {
402 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_PWMM_DSWR);
403 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_ASWRM);
404 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_DSWRM);
405 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_ASWRM);
406 }
407
rtw8851b_pwr_off_func(struct rtw89_dev * rtwdev)408 static int rtw8851b_pwr_off_func(struct rtw89_dev *rtwdev)
409 {
410 u32 val32;
411 int ret;
412
413 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
414 XTAL_SI_RFC2RF);
415 if (ret)
416 return ret;
417 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
418 if (ret)
419 return ret;
420 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
421 if (ret)
422 return ret;
423 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
424 if (ret)
425 return ret;
426 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
427 XTAL_SI_SRAM2RFC);
428 if (ret)
429 return ret;
430 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
431 if (ret)
432 return ret;
433 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
434 if (ret)
435 return ret;
436
437 rtw89_write32_set(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
438 B_AX_XTAL_SI_ADDR_NOT_CHK);
439 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
440 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
441 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
442
443 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
444
445 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
446 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
447 if (ret)
448 return ret;
449
450 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
451
452 if (rtwdev->hal.cv == CHIP_CAV) {
453 rtw8851b_patch_swr_pfm2pwm(rtwdev);
454 } else {
455 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
456 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
457 }
458
459 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
460
461 return 0;
462 }
463
rtw8851b_efuse_parsing(struct rtw89_efuse * efuse,struct rtw8851b_efuse * map)464 static void rtw8851b_efuse_parsing(struct rtw89_efuse *efuse,
465 struct rtw8851b_efuse *map)
466 {
467 ether_addr_copy(efuse->addr, map->e.mac_addr);
468 efuse->rfe_type = map->rfe_type;
469 efuse->xtal_cap = map->xtal_k;
470 }
471
rtw8851b_efuse_parsing_tssi(struct rtw89_dev * rtwdev,struct rtw8851b_efuse * map)472 static void rtw8851b_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
473 struct rtw8851b_efuse *map)
474 {
475 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
476 struct rtw8851b_tssi_offset *ofst[] = {&map->path_a_tssi};
477 u8 i, j;
478
479 tssi->thermal[RF_PATH_A] = map->path_a_therm;
480
481 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
482 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
483 sizeof(ofst[i]->cck_tssi));
484
485 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
486 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
487 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
488 i, j, tssi->tssi_cck[i][j]);
489
490 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
491 sizeof(ofst[i]->bw40_tssi));
492 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
493 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
494
495 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
496 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
497 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
498 i, j, tssi->tssi_mcs[i][j]);
499 }
500 }
501
_decode_efuse_gain(u8 data,s8 * high,s8 * low)502 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
503 {
504 if (high)
505 *high = sign_extend32(u8_get_bits(data, GENMASK(7, 4)), 3);
506 if (low)
507 *low = sign_extend32(u8_get_bits(data, GENMASK(3, 0)), 3);
508
509 return data != 0xff;
510 }
511
rtw8851b_efuse_parsing_gain_offset(struct rtw89_dev * rtwdev,struct rtw8851b_efuse * map)512 static void rtw8851b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
513 struct rtw8851b_efuse *map)
514 {
515 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
516 bool valid = false;
517
518 valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
519 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
520 NULL);
521 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
522 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
523 NULL);
524 valid |= _decode_efuse_gain(map->rx_gain_5g_low,
525 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
526 NULL);
527 valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
528 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
529 NULL);
530 valid |= _decode_efuse_gain(map->rx_gain_5g_high,
531 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
532 NULL);
533
534 gain->offset_valid = valid;
535 }
536
rtw8851b_read_efuse(struct rtw89_dev * rtwdev,u8 * log_map,enum rtw89_efuse_block block)537 static int rtw8851b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
538 enum rtw89_efuse_block block)
539 {
540 struct rtw89_efuse *efuse = &rtwdev->efuse;
541 struct rtw8851b_efuse *map;
542
543 map = (struct rtw8851b_efuse *)log_map;
544
545 efuse->country_code[0] = map->country_code[0];
546 efuse->country_code[1] = map->country_code[1];
547 rtw8851b_efuse_parsing_tssi(rtwdev, map);
548 rtw8851b_efuse_parsing_gain_offset(rtwdev, map);
549
550 switch (rtwdev->hci.type) {
551 case RTW89_HCI_TYPE_PCIE:
552 rtw8851b_efuse_parsing(efuse, map);
553 break;
554 default:
555 return -EOPNOTSUPP;
556 }
557
558 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
559
560 return 0;
561 }
562
rtw8851b_phycap_parsing_tssi(struct rtw89_dev * rtwdev,u8 * phycap_map)563 static void rtw8851b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
564 {
565 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
566 static const u32 tssi_trim_addr[RF_PATH_NUM_8851B] = {0x5D6};
567 u32 addr = rtwdev->chip->phycap_addr;
568 bool pg = false;
569 u32 ofst;
570 u8 i, j;
571
572 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
573 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
574 /* addrs are in decreasing order */
575 ofst = tssi_trim_addr[i] - addr - j;
576 tssi->tssi_trim[i][j] = phycap_map[ofst];
577
578 if (phycap_map[ofst] != 0xff)
579 pg = true;
580 }
581 }
582
583 if (!pg) {
584 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
585 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
586 "[TSSI][TRIM] no PG, set all trim info to 0\n");
587 }
588
589 for (i = 0; i < RF_PATH_NUM_8851B; i++)
590 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
591 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
592 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
593 i, j, tssi->tssi_trim[i][j],
594 tssi_trim_addr[i] - j);
595 }
596
rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)597 static void rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
598 u8 *phycap_map)
599 {
600 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
601 static const u32 thm_trim_addr[RF_PATH_NUM_8851B] = {0x5DF};
602 u32 addr = rtwdev->chip->phycap_addr;
603 u8 i;
604
605 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
606 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
607
608 rtw89_debug(rtwdev, RTW89_DBG_RFK,
609 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
610 i, info->thermal_trim[i]);
611
612 if (info->thermal_trim[i] != 0xff)
613 info->pg_thermal_trim = true;
614 }
615 }
616
rtw8851b_thermal_trim(struct rtw89_dev * rtwdev)617 static void rtw8851b_thermal_trim(struct rtw89_dev *rtwdev)
618 {
619 #define __thm_setting(raw) \
620 ({ \
621 u8 __v = (raw); \
622 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
623 })
624 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
625 u8 i, val;
626
627 if (!info->pg_thermal_trim) {
628 rtw89_debug(rtwdev, RTW89_DBG_RFK,
629 "[THERMAL][TRIM] no PG, do nothing\n");
630
631 return;
632 }
633
634 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
635 val = __thm_setting(info->thermal_trim[i]);
636 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
637
638 rtw89_debug(rtwdev, RTW89_DBG_RFK,
639 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
640 i, val);
641 }
642 #undef __thm_setting
643 }
644
rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)645 static void rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
646 u8 *phycap_map)
647 {
648 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
649 static const u32 pabias_trim_addr[] = {0x5DE};
650 u32 addr = rtwdev->chip->phycap_addr;
651 u8 i;
652
653 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
654 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
655
656 rtw89_debug(rtwdev, RTW89_DBG_RFK,
657 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
658 i, info->pa_bias_trim[i]);
659
660 if (info->pa_bias_trim[i] != 0xff)
661 info->pg_pa_bias_trim = true;
662 }
663 }
664
rtw8851b_pa_bias_trim(struct rtw89_dev * rtwdev)665 static void rtw8851b_pa_bias_trim(struct rtw89_dev *rtwdev)
666 {
667 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
668 u8 pabias_2g, pabias_5g;
669 u8 i;
670
671 if (!info->pg_pa_bias_trim) {
672 rtw89_debug(rtwdev, RTW89_DBG_RFK,
673 "[PA_BIAS][TRIM] no PG, do nothing\n");
674
675 return;
676 }
677
678 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
679 pabias_2g = u8_get_bits(info->pa_bias_trim[i], GENMASK(3, 0));
680 pabias_5g = u8_get_bits(info->pa_bias_trim[i], GENMASK(7, 4));
681
682 rtw89_debug(rtwdev, RTW89_DBG_RFK,
683 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
684 i, pabias_2g, pabias_5g);
685
686 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
687 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
688 }
689 }
690
rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev * rtwdev,u8 * phycap_map)691 static void rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
692 {
693 static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = {
694 {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8},
695 };
696 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
697 u32 phycap_addr = rtwdev->chip->phycap_addr;
698 bool valid = false;
699 int path, i;
700 u8 data;
701
702 for (path = 0; path < BB_PATH_NUM_8851B; path++)
703 for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) {
704 if (comp_addrs[path][i] == 0)
705 continue;
706
707 data = phycap_map[comp_addrs[path][i] - phycap_addr];
708 valid |= _decode_efuse_gain(data, NULL,
709 &gain->comp[path][i]);
710 }
711
712 gain->comp_valid = valid;
713 }
714
rtw8851b_read_phycap(struct rtw89_dev * rtwdev,u8 * phycap_map)715 static int rtw8851b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
716 {
717 rtw8851b_phycap_parsing_tssi(rtwdev, phycap_map);
718 rtw8851b_phycap_parsing_thermal_trim(rtwdev, phycap_map);
719 rtw8851b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
720 rtw8851b_phycap_parsing_gain_comp(rtwdev, phycap_map);
721
722 return 0;
723 }
724
rtw8851b_set_bb_gpio(struct rtw89_dev * rtwdev,u8 gpio_idx,bool inv,u8 src_sel)725 static void rtw8851b_set_bb_gpio(struct rtw89_dev *rtwdev, u8 gpio_idx, bool inv,
726 u8 src_sel)
727 {
728 u32 addr, mask;
729
730 if (gpio_idx >= 32)
731 return;
732
733 /* 2 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 2 bits */
734 addr = R_RFE_SEL0_A2 + (gpio_idx / 16) * sizeof(u32);
735 mask = B_RFE_SEL0_MASK << (gpio_idx % 16) * 2;
736
737 rtw89_phy_write32_mask(rtwdev, addr, mask, RF_PATH_A);
738 rtw89_phy_write32_mask(rtwdev, R_RFE_INV0, BIT(gpio_idx), inv);
739
740 /* 4 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 4 bits */
741 addr = R_RFE_SEL0_BASE + (gpio_idx / 8) * sizeof(u32);
742 mask = B_RFE_SEL0_SRC_MASK << (gpio_idx % 8) * 4;
743
744 rtw89_phy_write32_mask(rtwdev, addr, mask, src_sel);
745 }
746
rtw8851b_set_mac_gpio(struct rtw89_dev * rtwdev,u8 func)747 static void rtw8851b_set_mac_gpio(struct rtw89_dev *rtwdev, u8 func)
748 {
749 static const struct rtw89_reg3_def func16 = {
750 R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO16_FUNC_SEL_MASK, BIT(3)
751 };
752 static const struct rtw89_reg3_def func17 = {
753 R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO17_FUNC_SEL_MASK, BIT(7) >> 4,
754 };
755 const struct rtw89_reg3_def *def;
756
757 switch (func) {
758 case 16:
759 def = &func16;
760 break;
761 case 17:
762 def = &func17;
763 break;
764 default:
765 rtw89_warn(rtwdev, "undefined gpio func %d\n", func);
766 return;
767 }
768
769 rtw89_write8_mask(rtwdev, def->addr, def->mask, def->data);
770 }
771
rtw8851b_rfe_gpio(struct rtw89_dev * rtwdev)772 static void rtw8851b_rfe_gpio(struct rtw89_dev *rtwdev)
773 {
774 u8 rfe_type = rtwdev->efuse.rfe_type;
775
776 if (rfe_type > 50)
777 return;
778
779 if (rfe_type % 3 == 2) {
780 rtw8851b_set_bb_gpio(rtwdev, 16, true, RFE_SEL0_SRC_ANTSEL_0);
781 rtw8851b_set_bb_gpio(rtwdev, 17, false, RFE_SEL0_SRC_ANTSEL_0);
782
783 rtw8851b_set_mac_gpio(rtwdev, 16);
784 rtw8851b_set_mac_gpio(rtwdev, 17);
785 }
786 }
787
rtw8851b_power_trim(struct rtw89_dev * rtwdev)788 static void rtw8851b_power_trim(struct rtw89_dev *rtwdev)
789 {
790 rtw8851b_thermal_trim(rtwdev);
791 rtw8851b_pa_bias_trim(rtwdev);
792 }
793
rtw8851b_set_channel_mac(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 mac_idx)794 static void rtw8851b_set_channel_mac(struct rtw89_dev *rtwdev,
795 const struct rtw89_chan *chan,
796 u8 mac_idx)
797 {
798 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
799 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
800 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
801 u8 txsc20 = 0, txsc40 = 0;
802
803 switch (chan->band_width) {
804 case RTW89_CHANNEL_WIDTH_80:
805 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
806 fallthrough;
807 case RTW89_CHANNEL_WIDTH_40:
808 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
809 break;
810 default:
811 break;
812 }
813
814 switch (chan->band_width) {
815 case RTW89_CHANNEL_WIDTH_80:
816 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
817 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
818 break;
819 case RTW89_CHANNEL_WIDTH_40:
820 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
821 rtw89_write32(rtwdev, sub_carr, txsc20);
822 break;
823 case RTW89_CHANNEL_WIDTH_20:
824 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
825 rtw89_write32(rtwdev, sub_carr, 0);
826 break;
827 default:
828 break;
829 }
830
831 if (chan->channel > 14) {
832 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE);
833 rtw89_write8_set(rtwdev, chk_rate,
834 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
835 } else {
836 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE);
837 rtw89_write8_clr(rtwdev, chk_rate,
838 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
839 }
840 }
841
842 static const u32 rtw8851b_sco_barker_threshold[14] = {
843 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
844 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
845 };
846
847 static const u32 rtw8851b_sco_cck_threshold[14] = {
848 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
849 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
850 };
851
rtw8851b_ctrl_sco_cck(struct rtw89_dev * rtwdev,u8 primary_ch)852 static void rtw8851b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch)
853 {
854 u8 ch_element = primary_ch - 1;
855
856 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
857 rtw8851b_sco_barker_threshold[ch_element]);
858 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
859 rtw8851b_sco_cck_threshold[ch_element]);
860 }
861
rtw8851b_sco_mapping(u8 central_ch)862 static u8 rtw8851b_sco_mapping(u8 central_ch)
863 {
864 if (central_ch == 1)
865 return 109;
866 else if (central_ch >= 2 && central_ch <= 6)
867 return 108;
868 else if (central_ch >= 7 && central_ch <= 10)
869 return 107;
870 else if (central_ch >= 11 && central_ch <= 14)
871 return 106;
872 else if (central_ch == 36 || central_ch == 38)
873 return 51;
874 else if (central_ch >= 40 && central_ch <= 58)
875 return 50;
876 else if (central_ch >= 60 && central_ch <= 64)
877 return 49;
878 else if (central_ch == 100 || central_ch == 102)
879 return 48;
880 else if (central_ch >= 104 && central_ch <= 126)
881 return 47;
882 else if (central_ch >= 128 && central_ch <= 151)
883 return 46;
884 else if (central_ch >= 153 && central_ch <= 177)
885 return 45;
886 else
887 return 0;
888 }
889
890 struct rtw8851b_bb_gain {
891 u32 gain_g[BB_PATH_NUM_8851B];
892 u32 gain_a[BB_PATH_NUM_8851B];
893 u32 gain_mask;
894 };
895
896 static const struct rtw8851b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
897 { .gain_g = {0x4678}, .gain_a = {0x45DC},
898 .gain_mask = 0x00ff0000 },
899 { .gain_g = {0x4678}, .gain_a = {0x45DC},
900 .gain_mask = 0xff000000 },
901 { .gain_g = {0x467C}, .gain_a = {0x4660},
902 .gain_mask = 0x000000ff },
903 { .gain_g = {0x467C}, .gain_a = {0x4660},
904 .gain_mask = 0x0000ff00 },
905 { .gain_g = {0x467C}, .gain_a = {0x4660},
906 .gain_mask = 0x00ff0000 },
907 { .gain_g = {0x467C}, .gain_a = {0x4660},
908 .gain_mask = 0xff000000 },
909 { .gain_g = {0x4680}, .gain_a = {0x4664},
910 .gain_mask = 0x000000ff },
911 };
912
913 static const struct rtw8851b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
914 { .gain_g = {0x4680}, .gain_a = {0x4664},
915 .gain_mask = 0x00ff0000 },
916 { .gain_g = {0x4680}, .gain_a = {0x4664},
917 .gain_mask = 0xff000000 },
918 };
919
rtw8851b_set_gain_error(struct rtw89_dev * rtwdev,enum rtw89_subband subband,enum rtw89_rf_path path)920 static void rtw8851b_set_gain_error(struct rtw89_dev *rtwdev,
921 enum rtw89_subband subband,
922 enum rtw89_rf_path path)
923 {
924 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
925 u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
926 s32 val;
927 u32 reg;
928 u32 mask;
929 int i;
930
931 for (i = 0; i < LNA_GAIN_NUM; i++) {
932 if (subband == RTW89_CH_2G)
933 reg = bb_gain_lna[i].gain_g[path];
934 else
935 reg = bb_gain_lna[i].gain_a[path];
936
937 mask = bb_gain_lna[i].gain_mask;
938 val = gain->lna_gain[gain_band][path][i];
939 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
940 }
941
942 for (i = 0; i < TIA_GAIN_NUM; i++) {
943 if (subband == RTW89_CH_2G)
944 reg = bb_gain_tia[i].gain_g[path];
945 else
946 reg = bb_gain_tia[i].gain_a[path];
947
948 mask = bb_gain_tia[i].gain_mask;
949 val = gain->tia_gain[gain_band][path][i];
950 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
951 }
952 }
953
rtw8851b_set_gain_offset(struct rtw89_dev * rtwdev,enum rtw89_subband subband,enum rtw89_phy_idx phy_idx)954 static void rtw8851b_set_gain_offset(struct rtw89_dev *rtwdev,
955 enum rtw89_subband subband,
956 enum rtw89_phy_idx phy_idx)
957 {
958 static const u32 rssi_ofst_addr[] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1};
959 static const u32 gain_err_addr[] = {R_P0_AGC_RSVD};
960 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
961 enum rtw89_gain_offset gain_ofdm_band;
962 s32 offset_ofdm, offset_cck;
963 s32 offset_a;
964 s32 tmp;
965 u8 path;
966
967 if (!efuse_gain->comp_valid)
968 goto next;
969
970 for (path = RF_PATH_A; path < BB_PATH_NUM_8851B; path++) {
971 tmp = efuse_gain->comp[path][subband];
972 tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX);
973 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
974 }
975
976 next:
977 if (!efuse_gain->offset_valid)
978 return;
979
980 gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband);
981
982 offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
983
984 tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
985 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
986 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp);
987
988 offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
989 offset_cck = -efuse_gain->offset[RF_PATH_A][0];
990
991 tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0];
992 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
993 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
994
995 tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0];
996 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
997 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
998
999 if (subband == RTW89_CH_2G) {
1000 tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1);
1001 tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1);
1002 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST,
1003 B_RX_RPL_OFST_CCK_MASK, tmp);
1004 }
1005 }
1006
1007 static
rtw8851b_set_rxsc_rpl_comp(struct rtw89_dev * rtwdev,enum rtw89_subband subband)1008 void rtw8851b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband)
1009 {
1010 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1011 u8 band = rtw89_subband_to_bb_gain_band(subband);
1012 u32 val;
1013
1014 val = u32_encode_bits(gain->rpl_ofst_20[band][RF_PATH_A], B_P0_RPL1_20_MASK) |
1015 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][0], B_P0_RPL1_40_MASK) |
1016 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][1], B_P0_RPL1_41_MASK);
1017 val >>= B_P0_RPL1_SHIFT;
1018 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val);
1019 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val);
1020
1021 val = u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][2], B_P0_RTL2_42_MASK) |
1022 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][0], B_P0_RTL2_80_MASK) |
1023 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][1], B_P0_RTL2_81_MASK) |
1024 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][10], B_P0_RTL2_8A_MASK);
1025 rtw89_phy_write32(rtwdev, R_P0_RPL2, val);
1026 rtw89_phy_write32(rtwdev, R_P1_RPL2, val);
1027
1028 val = u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][2], B_P0_RTL3_82_MASK) |
1029 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][3], B_P0_RTL3_83_MASK) |
1030 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][4], B_P0_RTL3_84_MASK) |
1031 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][9], B_P0_RTL3_89_MASK);
1032 rtw89_phy_write32(rtwdev, R_P0_RPL3, val);
1033 rtw89_phy_write32(rtwdev, R_P1_RPL3, val);
1034 }
1035
rtw8851b_ctrl_ch(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1036 static void rtw8851b_ctrl_ch(struct rtw89_dev *rtwdev,
1037 const struct rtw89_chan *chan,
1038 enum rtw89_phy_idx phy_idx)
1039 {
1040 u8 subband = chan->subband_type;
1041 u8 central_ch = chan->channel;
1042 bool is_2g = central_ch <= 14;
1043 u8 sco_comp;
1044
1045 if (is_2g)
1046 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1047 B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx);
1048 else
1049 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1050 B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx);
1051 /* SCO compensate FC setting */
1052 sco_comp = rtw8851b_sco_mapping(central_ch);
1053 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx);
1054
1055 if (chan->band_type == RTW89_BAND_6G)
1056 return;
1057
1058 /* CCK parameters */
1059 if (central_ch == 14) {
1060 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
1061 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de);
1062 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad);
1063 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e);
1064 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92);
1065 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
1066 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
1067 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a);
1068 } else {
1069 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);
1070 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354);
1071 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
1072 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053);
1073 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a);
1074 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92);
1075 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc);
1076 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5);
1077 }
1078
1079 rtw8851b_set_gain_error(rtwdev, subband, RF_PATH_A);
1080 rtw8851b_set_gain_offset(rtwdev, subband, phy_idx);
1081 rtw8851b_set_rxsc_rpl_comp(rtwdev, subband);
1082 }
1083
rtw8851b_bw_setting(struct rtw89_dev * rtwdev,u8 bw)1084 static void rtw8851b_bw_setting(struct rtw89_dev *rtwdev, u8 bw)
1085 {
1086 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_CTL, 0x8);
1087 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_EN, 0x2);
1088 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_BW0, 0x2);
1089 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_BW1, 0x4);
1090 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_MUL, 0xf);
1091 rtw89_phy_write32_mask(rtwdev, R_ADCMOD, B_ADCMOD_LP, 0xa);
1092 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92);
1093
1094 switch (bw) {
1095 case RTW89_CHANNEL_WIDTH_5:
1096 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1097 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x0);
1098 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x1);
1099 break;
1100 case RTW89_CHANNEL_WIDTH_10:
1101 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1102 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x1);
1103 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1104 break;
1105 case RTW89_CHANNEL_WIDTH_20:
1106 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1107 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1108 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1109 break;
1110 case RTW89_CHANNEL_WIDTH_40:
1111 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1112 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1113 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1114 break;
1115 case RTW89_CHANNEL_WIDTH_80:
1116 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x0);
1117 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1118 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1119 break;
1120 default:
1121 rtw89_warn(rtwdev, "Fail to set ADC\n");
1122 }
1123 }
1124
rtw8851b_ctrl_bw(struct rtw89_dev * rtwdev,u8 pri_ch,u8 bw,enum rtw89_phy_idx phy_idx)1125 static void rtw8851b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1126 enum rtw89_phy_idx phy_idx)
1127 {
1128 switch (bw) {
1129 case RTW89_CHANNEL_WIDTH_5:
1130 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1131 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx);
1132 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1133 break;
1134 case RTW89_CHANNEL_WIDTH_10:
1135 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1136 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx);
1137 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1138 break;
1139 case RTW89_CHANNEL_WIDTH_20:
1140 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1141 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1142 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1143 break;
1144 case RTW89_CHANNEL_WIDTH_40:
1145 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx);
1146 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1147 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1148 pri_ch, phy_idx);
1149 /* CCK primary channel */
1150 if (pri_ch == RTW89_SC_20_UPPER)
1151 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
1152 else
1153 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
1154
1155 break;
1156 case RTW89_CHANNEL_WIDTH_80:
1157 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx);
1158 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1159 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1160 pri_ch, phy_idx);
1161 break;
1162 default:
1163 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1164 pri_ch);
1165 }
1166
1167 rtw8851b_bw_setting(rtwdev, bw);
1168 }
1169
rtw8851b_ctrl_cck_en(struct rtw89_dev * rtwdev,bool cck_en)1170 static void rtw8851b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en)
1171 {
1172 if (cck_en) {
1173 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1174 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1175 B_PD_ARBITER_OFF, 0);
1176 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1177 } else {
1178 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1179 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1180 B_PD_ARBITER_OFF, 1);
1181 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1182 }
1183 }
1184
rtw8851b_spur_freq(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1185 static u32 rtw8851b_spur_freq(struct rtw89_dev *rtwdev,
1186 const struct rtw89_chan *chan)
1187 {
1188 u8 center_chan = chan->channel;
1189
1190 switch (chan->band_type) {
1191 case RTW89_BAND_5G:
1192 if (center_chan == 151 || center_chan == 153 ||
1193 center_chan == 155 || center_chan == 163)
1194 return 5760;
1195 else if (center_chan == 54 || center_chan == 58)
1196 return 5280;
1197 break;
1198 default:
1199 break;
1200 }
1201
1202 return 0;
1203 }
1204
1205 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
1206 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
1207 #define MAX_TONE_NUM 2048
1208
rtw8851b_set_csi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1209 static void rtw8851b_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1210 const struct rtw89_chan *chan,
1211 enum rtw89_phy_idx phy_idx)
1212 {
1213 u32 spur_freq;
1214 s32 freq_diff, csi_idx, csi_tone_idx;
1215
1216 spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1217 if (spur_freq == 0) {
1218 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN,
1219 0, phy_idx);
1220 return;
1221 }
1222
1223 freq_diff = (spur_freq - chan->freq) * 1000000;
1224 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
1225 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
1226
1227 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_V1, B_SEG0CSI_IDX,
1228 csi_tone_idx, phy_idx);
1229 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx);
1230 }
1231
1232 static const struct rtw89_nbi_reg_def rtw8851b_nbi_reg_def = {
1233 .notch1_idx = {0x46E4, 0xFF},
1234 .notch1_frac_idx = {0x46E4, 0xC00},
1235 .notch1_en = {0x46E4, 0x1000},
1236 .notch2_idx = {0x47A4, 0xFF},
1237 .notch2_frac_idx = {0x47A4, 0xC00},
1238 .notch2_en = {0x47A4, 0x1000},
1239 };
1240
rtw8851b_set_nbi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1241 static void rtw8851b_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1242 const struct rtw89_chan *chan)
1243 {
1244 const struct rtw89_nbi_reg_def *nbi = &rtw8851b_nbi_reg_def;
1245 s32 nbi_frac_idx, nbi_frac_tone_idx;
1246 s32 nbi_idx, nbi_tone_idx;
1247 bool notch2_chk = false;
1248 u32 spur_freq, fc;
1249 s32 freq_diff;
1250
1251 spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1252 if (spur_freq == 0) {
1253 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1254 nbi->notch1_en.mask, 0);
1255 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1256 nbi->notch2_en.mask, 0);
1257 return;
1258 }
1259
1260 fc = chan->freq;
1261 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) {
1262 fc = (spur_freq > fc) ? fc + 40 : fc - 40;
1263 if ((fc > spur_freq &&
1264 chan->channel < chan->primary_channel) ||
1265 (fc < spur_freq &&
1266 chan->channel > chan->primary_channel))
1267 notch2_chk = true;
1268 }
1269
1270 freq_diff = (spur_freq - fc) * 1000000;
1271 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5,
1272 &nbi_frac_idx);
1273
1274 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) {
1275 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx);
1276 } else {
1277 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ?
1278 128 : 256;
1279
1280 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx);
1281 }
1282 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx,
1283 CARRIER_SPACING_78_125);
1284
1285 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
1286 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr,
1287 nbi->notch2_idx.mask, nbi_tone_idx);
1288 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr,
1289 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx);
1290 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1291 nbi->notch2_en.mask, 0);
1292 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1293 nbi->notch2_en.mask, 1);
1294 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1295 nbi->notch1_en.mask, 0);
1296 } else {
1297 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr,
1298 nbi->notch1_idx.mask, nbi_tone_idx);
1299 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr,
1300 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx);
1301 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1302 nbi->notch1_en.mask, 0);
1303 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1304 nbi->notch1_en.mask, 1);
1305 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1306 nbi->notch2_en.mask, 0);
1307 }
1308 }
1309
rtw8851b_set_cfr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1310 static void rtw8851b_set_cfr(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan)
1311 {
1312 if (chan->band_type == RTW89_BAND_2G &&
1313 chan->band_width == RTW89_CHANNEL_WIDTH_20 &&
1314 (chan->channel == 1 || chan->channel == 13)) {
1315 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1316 B_PATH0_TX_CFR_LGC0, 0xf8);
1317 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1318 B_PATH0_TX_CFR_LGC1, 0x120);
1319 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1320 B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x0);
1321 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1322 B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x3);
1323 } else {
1324 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1325 B_PATH0_TX_CFR_LGC0, 0x120);
1326 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1327 B_PATH0_TX_CFR_LGC1, 0x3ff);
1328 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1329 B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x3);
1330 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1331 B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x7);
1332 }
1333 }
1334
rtw8851b_5m_mask(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1335 static void rtw8851b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1336 enum rtw89_phy_idx phy_idx)
1337 {
1338 u8 pri_ch = chan->pri_ch_idx;
1339 bool mask_5m_low;
1340 bool mask_5m_en;
1341
1342 switch (chan->band_width) {
1343 case RTW89_CHANNEL_WIDTH_40:
1344 /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */
1345 mask_5m_en = true;
1346 mask_5m_low = pri_ch == RTW89_SC_20_LOWER;
1347 break;
1348 case RTW89_CHANNEL_WIDTH_80:
1349 /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */
1350 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST ||
1351 pri_ch == RTW89_SC_20_LOWEST;
1352 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST;
1353 break;
1354 default:
1355 mask_5m_en = false;
1356 break;
1357 }
1358
1359 if (!mask_5m_en) {
1360 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0);
1361 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1362 B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx);
1363 return;
1364 }
1365
1366 if (mask_5m_low) {
1367 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1368 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1369 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0);
1370 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1);
1371 } else {
1372 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1373 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1374 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1);
1375 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0);
1376 }
1377 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1378 B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx);
1379 }
1380
rtw8851b_bb_reset_all(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1381 static void rtw8851b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1382 {
1383 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1384 fsleep(1);
1385 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1386 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1387 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1388 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1389 }
1390
rtw8851b_bb_reset_en(struct rtw89_dev * rtwdev,enum rtw89_band band,enum rtw89_phy_idx phy_idx,bool en)1391 static void rtw8851b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1392 enum rtw89_phy_idx phy_idx, bool en)
1393 {
1394 if (en) {
1395 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1396 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1397 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1398 if (band == RTW89_BAND_2G)
1399 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
1400 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
1401 } else {
1402 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
1403 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
1404 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1405 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1406 fsleep(1);
1407 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1408 }
1409 }
1410
rtw8851b_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1411 static void rtw8851b_bb_reset(struct rtw89_dev *rtwdev,
1412 enum rtw89_phy_idx phy_idx)
1413 {
1414 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1415 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x1);
1416 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1417 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1418 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1419 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x3);
1420 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1421 }
1422
1423 static
rtw8851b_bb_gpio_trsw(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 tx_path_en,u8 trsw_tx,u8 trsw_rx,u8 trsw_a,u8 trsw_b)1424 void rtw8851b_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1425 u8 tx_path_en, u8 trsw_tx,
1426 u8 trsw_rx, u8 trsw_a, u8 trsw_b)
1427 {
1428 u32 mask_ofst = 16;
1429 u32 val;
1430
1431 if (path != RF_PATH_A)
1432 return;
1433
1434 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2;
1435 val = u32_encode_bits(trsw_a, B_P0_TRSW_A) |
1436 u32_encode_bits(trsw_b, B_P0_TRSW_B);
1437
1438 rtw89_phy_write32_mask(rtwdev, R_P0_TRSW,
1439 (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val);
1440 }
1441
rtw8851b_bb_gpio_init(struct rtw89_dev * rtwdev)1442 static void rtw8851b_bb_gpio_init(struct rtw89_dev *rtwdev)
1443 {
1444 rtw89_phy_write32_set(rtwdev, R_P0_TRSW, B_P0_TRSW_A);
1445 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_X);
1446 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_SO_A2);
1447 rtw89_phy_write32(rtwdev, R_RFE_SEL0_BASE, 0x77777777);
1448 rtw89_phy_write32(rtwdev, R_RFE_SEL32_BASE, 0x77777777);
1449
1450 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);
1451 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);
1452 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);
1453 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);
1454
1455 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);
1456 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);
1457 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);
1458 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);
1459 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);
1460 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);
1461 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);
1462 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);
1463 }
1464
rtw8851b_bb_macid_ctrl_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1465 static void rtw8851b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1466 enum rtw89_phy_idx phy_idx)
1467 {
1468 u32 addr;
1469
1470 for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1471 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1472 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1473 }
1474
rtw8851b_bb_sethw(struct rtw89_dev * rtwdev)1475 static void rtw8851b_bb_sethw(struct rtw89_dev *rtwdev)
1476 {
1477 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1478
1479 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1480
1481 rtw8851b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1482 rtw8851b_bb_gpio_init(rtwdev);
1483
1484 rtw89_write32_clr(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_VALUE);
1485 rtw89_write32_set(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_EN);
1486
1487 /* read these registers after loading BB parameters */
1488 gain->offset_base[RTW89_PHY_0] =
1489 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
1490 gain->rssi_base[RTW89_PHY_0] =
1491 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
1492 }
1493
rtw8851b_set_channel_bb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1494 static void rtw8851b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1495 enum rtw89_phy_idx phy_idx)
1496 {
1497 u8 band = chan->band_type, chan_idx;
1498 bool cck_en = chan->channel <= 14;
1499 u8 pri_ch_idx = chan->pri_ch_idx;
1500
1501 if (cck_en)
1502 rtw8851b_ctrl_sco_cck(rtwdev, chan->primary_channel);
1503
1504 rtw8851b_ctrl_ch(rtwdev, chan, phy_idx);
1505 rtw8851b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1506 rtw8851b_ctrl_cck_en(rtwdev, cck_en);
1507 rtw8851b_set_nbi_tone_idx(rtwdev, chan);
1508 rtw8851b_set_csi_tone_idx(rtwdev, chan, phy_idx);
1509
1510 if (chan->band_type == RTW89_BAND_5G) {
1511 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1512 B_PATH0_BT_SHARE_V1, 0x0);
1513 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1514 B_PATH0_BTG_PATH_V1, 0x0);
1515 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1516 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1517 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1518 B_BT_DYN_DC_EST_EN_MSK, 0x0);
1519 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1520 }
1521
1522 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1523 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx);
1524 rtw8851b_5m_mask(rtwdev, chan, phy_idx);
1525 rtw8851b_set_cfr(rtwdev, chan);
1526 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1527 }
1528
rtw8851b_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1529 static void rtw8851b_set_channel(struct rtw89_dev *rtwdev,
1530 const struct rtw89_chan *chan,
1531 enum rtw89_mac_idx mac_idx,
1532 enum rtw89_phy_idx phy_idx)
1533 {
1534 rtw8851b_set_channel_mac(rtwdev, chan, mac_idx);
1535 rtw8851b_set_channel_bb(rtwdev, chan, phy_idx);
1536 rtw8851b_set_channel_rf(rtwdev, chan, phy_idx);
1537 }
1538
rtw8851b_tssi_cont_en(struct rtw89_dev * rtwdev,bool en,enum rtw89_rf_path path)1539 static void rtw8851b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1540 enum rtw89_rf_path path)
1541 {
1542 if (en) {
1543 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x0);
1544 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x0);
1545 } else {
1546 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x1);
1547 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x1);
1548 }
1549 }
1550
rtw8851b_tssi_cont_en_phyidx(struct rtw89_dev * rtwdev,bool en,u8 phy_idx)1551 static void rtw8851b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1552 u8 phy_idx)
1553 {
1554 rtw8851b_tssi_cont_en(rtwdev, en, RF_PATH_A);
1555 }
1556
rtw8851b_adc_en(struct rtw89_dev * rtwdev,bool en)1557 static void rtw8851b_adc_en(struct rtw89_dev *rtwdev, bool en)
1558 {
1559 if (en)
1560 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
1561 else
1562 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
1563 }
1564
rtw8851b_set_channel_help(struct rtw89_dev * rtwdev,bool enter,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1565 static void rtw8851b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1566 struct rtw89_channel_help_params *p,
1567 const struct rtw89_chan *chan,
1568 enum rtw89_mac_idx mac_idx,
1569 enum rtw89_phy_idx phy_idx)
1570 {
1571 if (enter) {
1572 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
1573 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
1574 rtw8851b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
1575 rtw8851b_adc_en(rtwdev, false);
1576 fsleep(40);
1577 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
1578 } else {
1579 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
1580 rtw8851b_adc_en(rtwdev, true);
1581 rtw8851b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
1582 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
1583 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
1584 }
1585 }
1586
rtw8851b_rfk_init(struct rtw89_dev * rtwdev)1587 static void rtw8851b_rfk_init(struct rtw89_dev *rtwdev)
1588 {
1589 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1590 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1591 rtw8851b_lck_init(rtwdev);
1592
1593 rtw8851b_dpk_init(rtwdev);
1594 rtw8851b_aack(rtwdev);
1595 rtw8851b_rck(rtwdev);
1596 rtw8851b_dack(rtwdev);
1597 rtw8851b_rx_dck(rtwdev, RTW89_PHY_0, RTW89_CHANCTX_0);
1598 }
1599
rtw8851b_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)1600 static void rtw8851b_rfk_channel(struct rtw89_dev *rtwdev,
1601 struct rtw89_vif_link *rtwvif_link)
1602 {
1603 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx;
1604 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
1605
1606 rtw89_btc_ntfy_conn_rfk(rtwdev, true);
1607
1608 rtw8851b_rx_dck(rtwdev, phy_idx, chanctx_idx);
1609 rtw8851b_iqk(rtwdev, phy_idx, chanctx_idx);
1610 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30);
1611 rtw8851b_tssi(rtwdev, phy_idx, true, chanctx_idx);
1612 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30);
1613 rtw8851b_dpk(rtwdev, phy_idx, chanctx_idx);
1614
1615 rtw89_btc_ntfy_conn_rfk(rtwdev, false);
1616 }
1617
rtw8851b_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)1618 static void rtw8851b_rfk_band_changed(struct rtw89_dev *rtwdev,
1619 enum rtw89_phy_idx phy_idx,
1620 const struct rtw89_chan *chan)
1621 {
1622 rtw8851b_tssi_scan(rtwdev, phy_idx, chan);
1623 }
1624
rtw8851b_rfk_scan(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool start)1625 static void rtw8851b_rfk_scan(struct rtw89_dev *rtwdev,
1626 struct rtw89_vif_link *rtwvif_link,
1627 bool start)
1628 {
1629 rtw8851b_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx,
1630 rtwvif_link->chanctx_idx);
1631 }
1632
rtw8851b_rfk_track(struct rtw89_dev * rtwdev)1633 static void rtw8851b_rfk_track(struct rtw89_dev *rtwdev)
1634 {
1635 rtw8851b_dpk_track(rtwdev);
1636 rtw8851b_lck_track(rtwdev);
1637 }
1638
rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,s16 ref)1639 static u32 rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1640 enum rtw89_phy_idx phy_idx, s16 ref)
1641 {
1642 const u16 tssi_16dbm_cw = 0x12c;
1643 const u8 base_cw_0db = 0x27;
1644 const s8 ofst_int = 0;
1645 s16 pwr_s10_3;
1646 s16 rf_pwr_cw;
1647 u16 bb_pwr_cw;
1648 u32 pwr_cw;
1649 u32 tssi_ofst_cw;
1650
1651 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1652 bb_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(2, 0));
1653 rf_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(8, 3));
1654 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1655 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1656
1657 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1658 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1659 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1660 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1661
1662 return u32_encode_bits(tssi_ofst_cw, B_DPD_TSSI_CW) |
1663 u32_encode_bits(pwr_cw, B_DPD_PWR_CW) |
1664 u32_encode_bits(ref, B_DPD_REF);
1665 }
1666
rtw8851b_set_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1667 static void rtw8851b_set_txpwr_ref(struct rtw89_dev *rtwdev,
1668 enum rtw89_phy_idx phy_idx)
1669 {
1670 static const u32 addr[RF_PATH_NUM_8851B] = {0x5800};
1671 const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF;
1672 const u8 ofst_ofdm = 0x4;
1673 const u8 ofst_cck = 0x8;
1674 const s16 ref_ofdm = 0;
1675 const s16 ref_cck = 0;
1676 u32 val;
1677 u8 i;
1678
1679 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1680
1681 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1682 B_AX_PWR_REF, 0x0);
1683
1684 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1685 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1686
1687 for (i = 0; i < RF_PATH_NUM_8851B; i++)
1688 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1689 phy_idx);
1690
1691 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1692 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1693
1694 for (i = 0; i < RF_PATH_NUM_8851B; i++)
1695 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1696 phy_idx);
1697 }
1698
rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 tx_shape_idx,enum rtw89_phy_idx phy_idx)1699 static void rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
1700 const struct rtw89_chan *chan,
1701 u8 tx_shape_idx,
1702 enum rtw89_phy_idx phy_idx)
1703 {
1704 #define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2))
1705 #define __DFIR_CFG_MASK 0xffffffff
1706 #define __DFIR_CFG_NR 8
1707 #define __DECL_DFIR_PARAM(_name, _val...) \
1708 static const u32 param_ ## _name[] = {_val}; \
1709 static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR)
1710
1711 __DECL_DFIR_PARAM(flat,
1712 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
1713 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5);
1714 __DECL_DFIR_PARAM(sharp,
1715 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090,
1716 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5);
1717 __DECL_DFIR_PARAM(sharp_14,
1718 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
1719 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A);
1720 u8 ch = chan->channel;
1721 const u32 *param;
1722 u32 addr;
1723 int i;
1724
1725 if (ch > 14) {
1726 rtw89_warn(rtwdev,
1727 "set tx shape dfir by unknown ch: %d on 2G\n", ch);
1728 return;
1729 }
1730
1731 if (ch == 14)
1732 param = param_sharp_14;
1733 else
1734 param = tx_shape_idx == 0 ? param_flat : param_sharp;
1735
1736 for (i = 0; i < __DFIR_CFG_NR; i++) {
1737 addr = __DFIR_CFG_ADDR(i);
1738 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1739 "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]);
1740 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i],
1741 phy_idx);
1742 }
1743
1744 #undef __DECL_DFIR_PARAM
1745 #undef __DFIR_CFG_NR
1746 #undef __DFIR_CFG_MASK
1747 #undef __DECL_CFG_ADDR
1748 }
1749
rtw8851b_set_tx_shape(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1750 static void rtw8851b_set_tx_shape(struct rtw89_dev *rtwdev,
1751 const struct rtw89_chan *chan,
1752 enum rtw89_phy_idx phy_idx)
1753 {
1754 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
1755 u8 band = chan->band_type;
1756 u8 regd = rtw89_regd_get(rtwdev, band);
1757 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd];
1758 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd];
1759
1760 if (band == RTW89_BAND_2G)
1761 rtw8851b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
1762
1763 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG,
1764 tx_shape_ofdm);
1765 }
1766
rtw8851b_set_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1767 static void rtw8851b_set_txpwr(struct rtw89_dev *rtwdev,
1768 const struct rtw89_chan *chan,
1769 enum rtw89_phy_idx phy_idx)
1770 {
1771 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1772 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1773 rtw8851b_set_tx_shape(rtwdev, chan, phy_idx);
1774 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1775 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1776 }
1777
rtw8851b_set_txpwr_ctrl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1778 static void rtw8851b_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1779 enum rtw89_phy_idx phy_idx)
1780 {
1781 rtw8851b_set_txpwr_ref(rtwdev, phy_idx);
1782 }
1783
1784 static
rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,s8 pw_ofst,enum rtw89_mac_idx mac_idx)1785 void rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1786 s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1787 {
1788 u32 reg;
1789
1790 if (pw_ofst < -16 || pw_ofst > 15) {
1791 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
1792 return;
1793 }
1794
1795 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx);
1796 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1797
1798 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
1799 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
1800
1801 pw_ofst = max_t(s8, pw_ofst - 3, -16);
1802 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
1803 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst);
1804 }
1805
1806 static int
rtw8851b_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1807 rtw8851b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1808 {
1809 int ret;
1810
1811 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1812 if (ret)
1813 return ret;
1814
1815 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
1816 if (ret)
1817 return ret;
1818
1819 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1820 if (ret)
1821 return ret;
1822
1823 rtw8851b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
1824 RTW89_MAC_1 : RTW89_MAC_0);
1825
1826 return 0;
1827 }
1828
rtw8851b_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)1829 static void rtw8851b_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
1830 enum rtw89_phy_idx phy_idx)
1831 {
1832 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
1833
1834 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8851b_btc_preagc_en_defs_tbl :
1835 &rtw8851b_btc_preagc_dis_defs_tbl);
1836
1837 if (!en) {
1838 if (chan->band_type == RTW89_BAND_2G) {
1839 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1840 B_PATH0_G_LNA6_OP1DB_V1, 0x20);
1841 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1842 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30);
1843 } else {
1844 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1845 B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
1846 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1847 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
1848 }
1849 }
1850 }
1851
rtw8851b_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)1852 static void rtw8851b_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
1853 enum rtw89_phy_idx phy_idx)
1854 {
1855 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
1856
1857 if (en) {
1858 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1859 B_PATH0_BT_SHARE_V1, 0x1);
1860 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1861 B_PATH0_BTG_PATH_V1, 0x1);
1862 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1863 B_PATH0_G_LNA6_OP1DB_V1, 0x20);
1864 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1865 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30);
1866 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1867 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1);
1868 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x1);
1869 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1870 B_BT_DYN_DC_EST_EN_MSK, 0x1);
1871 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1);
1872 } else {
1873 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1874 B_PATH0_BT_SHARE_V1, 0x0);
1875 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1876 B_PATH0_BTG_PATH_V1, 0x0);
1877 if (chan->band_type == RTW89_BAND_2G) {
1878 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1879 B_PATH0_G_LNA6_OP1DB_V1, 0x80);
1880 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1881 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80);
1882 } else {
1883 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1884 B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
1885 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1886 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
1887 }
1888 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc);
1889 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1890 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1891 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1892 B_BT_DYN_DC_EST_EN_MSK, 0x1);
1893 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1894 }
1895 }
1896
rtw8851b_bb_ctrl_rx_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path_bit rx_path)1897 static void rtw8851b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
1898 enum rtw89_rf_path_bit rx_path)
1899 {
1900 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
1901 u32 rst_mask0;
1902
1903 if (rx_path == RF_A) {
1904 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1);
1905 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1);
1906 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1);
1907 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1908 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1909 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1910 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1911 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1912 }
1913
1914 rtw8851b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0);
1915
1916 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
1917 if (rx_path == RF_A) {
1918 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1919 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1920 }
1921 }
1922
rtw8851b_bb_cfg_txrx_path(struct rtw89_dev * rtwdev)1923 static void rtw8851b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
1924 {
1925 rtw8851b_bb_ctrl_rx_path(rtwdev, RF_A);
1926
1927 if (rtwdev->hal.rx_nss == 1) {
1928 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1929 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1930 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1931 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1932 }
1933
1934 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1935 }
1936
rtw8851b_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)1937 static u8 rtw8851b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1938 {
1939 if (rtwdev->is_tssi_mode[rf_path]) {
1940 u32 addr = R_TSSI_THER + (rf_path << 13);
1941
1942 return rtw89_phy_read32_mask(rtwdev, addr, B_TSSI_THER);
1943 }
1944
1945 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1946 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1947 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1948
1949 fsleep(200);
1950
1951 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1952 }
1953
rtw8851b_btc_set_rfe(struct rtw89_dev * rtwdev)1954 static void rtw8851b_btc_set_rfe(struct rtw89_dev *rtwdev)
1955 {
1956 const struct rtw89_btc_ver *ver = rtwdev->btc.ver;
1957 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo;
1958
1959 if (ver->fcxinit == 7) {
1960 md->md_v7.rfe_type = rtwdev->efuse.rfe_type;
1961 md->md_v7.kt_ver = rtwdev->hal.cv;
1962 md->md_v7.bt_solo = 0;
1963 md->md_v7.switch_type = BTC_SWITCH_INTERNAL;
1964 md->md_v7.ant.isolation = 10;
1965 md->md_v7.kt_ver_adie = rtwdev->hal.acv;
1966
1967 if (md->md_v7.rfe_type == 0)
1968 return;
1969
1970 /* rfe_type 3*n+1: 1-Ant(shared),
1971 * 3*n+2: 2-Ant+Div(non-shared),
1972 * 3*n+3: 2-Ant+no-Div(non-shared)
1973 */
1974 md->md_v7.ant.num = (md->md_v7.rfe_type % 3 == 1) ? 1 : 2;
1975 /* WL-1ss at S0, btg at s0 (On 1 WL RF) */
1976 md->md_v7.ant.single_pos = RF_PATH_A;
1977 md->md_v7.ant.btg_pos = RF_PATH_A;
1978 md->md_v7.ant.stream_cnt = 1;
1979
1980 if (md->md_v7.ant.num == 1) {
1981 md->md_v7.ant.type = BTC_ANT_SHARED;
1982 md->md_v7.bt_pos = BTC_BT_BTG;
1983 md->md_v7.wa_type = 1;
1984 md->md_v7.ant.diversity = 0;
1985 } else { /* ant.num == 2 */
1986 md->md_v7.ant.type = BTC_ANT_DEDICATED;
1987 md->md_v7.bt_pos = BTC_BT_ALONE;
1988 md->md_v7.switch_type = BTC_SWITCH_EXTERNAL;
1989 md->md_v7.wa_type = 0;
1990 if (md->md_v7.rfe_type % 3 == 2)
1991 md->md_v7.ant.diversity = 1;
1992 }
1993 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos;
1994 rtwdev->btc.ant_type = md->md_v7.ant.type;
1995 } else {
1996 md->md.rfe_type = rtwdev->efuse.rfe_type;
1997 md->md.cv = rtwdev->hal.cv;
1998 md->md.bt_solo = 0;
1999 md->md.switch_type = BTC_SWITCH_INTERNAL;
2000 md->md.ant.isolation = 10;
2001 md->md.kt_ver_adie = rtwdev->hal.acv;
2002
2003 if (md->md.rfe_type == 0)
2004 return;
2005
2006 /* rfe_type 3*n+1: 1-Ant(shared),
2007 * 3*n+2: 2-Ant+Div(non-shared),
2008 * 3*n+3: 2-Ant+no-Div(non-shared)
2009 */
2010 md->md.ant.num = (md->md.rfe_type % 3 == 1) ? 1 : 2;
2011 /* WL-1ss at S0, btg at s0 (On 1 WL RF) */
2012 md->md.ant.single_pos = RF_PATH_A;
2013 md->md.ant.btg_pos = RF_PATH_A;
2014 md->md.ant.stream_cnt = 1;
2015
2016 if (md->md.ant.num == 1) {
2017 md->md.ant.type = BTC_ANT_SHARED;
2018 md->md.bt_pos = BTC_BT_BTG;
2019 md->md.wa_type = 1;
2020 md->md.ant.diversity = 0;
2021 } else { /* ant.num == 2 */
2022 md->md.ant.type = BTC_ANT_DEDICATED;
2023 md->md.bt_pos = BTC_BT_ALONE;
2024 md->md.switch_type = BTC_SWITCH_EXTERNAL;
2025 md->md.wa_type = 0;
2026 if (md->md.rfe_type % 3 == 2)
2027 md->md.ant.diversity = 1;
2028 }
2029 rtwdev->btc.btg_pos = md->md.ant.btg_pos;
2030 rtwdev->btc.ant_type = md->md.ant.type;
2031 }
2032 }
2033
2034 static
rtw8851b_set_trx_mask(struct rtw89_dev * rtwdev,u8 path,u8 group,u32 val)2035 void rtw8851b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
2036 {
2037 if (group > BTC_BT_SS_GROUP)
2038 group--; /* Tx-group=1, Rx-group=2 */
2039
2040 if (rtwdev->btc.ant_type == BTC_ANT_SHARED) /* 1-Ant */
2041 group += 3;
2042
2043 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
2044 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
2045 }
2046
rtw8851b_btc_init_cfg(struct rtw89_dev * rtwdev)2047 static void rtw8851b_btc_init_cfg(struct rtw89_dev *rtwdev)
2048 {
2049 static const struct rtw89_mac_ax_coex coex_params = {
2050 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
2051 .direction = RTW89_MAC_AX_COEX_INNER,
2052 };
2053 const struct rtw89_chip_info *chip = rtwdev->chip;
2054 struct rtw89_btc *btc = &rtwdev->btc;
2055 union rtw89_btc_module_info *md = &btc->mdinfo;
2056 const struct rtw89_btc_ver *ver = btc->ver;
2057 u8 path, path_min, path_max, str_cnt, ant_sing_pos;
2058
2059 /* PTA init */
2060 rtw89_mac_coex_init(rtwdev, &coex_params);
2061
2062 /* set WL Tx response = Hi-Pri */
2063 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
2064 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
2065
2066 if (ver->fcxinit == 7) {
2067 str_cnt = md->md_v7.ant.stream_cnt;
2068 ant_sing_pos = md->md_v7.ant.single_pos;
2069 } else {
2070 str_cnt = md->md.ant.stream_cnt;
2071 ant_sing_pos = md->md.ant.single_pos;
2072 }
2073
2074 /* for 1-Ant && 1-ss case: only 1-path */
2075 if (str_cnt == 1) {
2076 path_min = ant_sing_pos;
2077 path_max = path_min;
2078 } else {
2079 path_min = RF_PATH_A;
2080 path_max = RF_PATH_B;
2081 }
2082
2083 for (path = path_min; path <= path_max; path++) {
2084 /* set rf gnt-debug off */
2085 rtw89_write_rf(rtwdev, path, RR_WLSEL, RFREG_MASK, 0x0);
2086
2087 /* set DEBUG_LUT_RFMODE_MASK = 1 to start trx-mask-setup */
2088 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, BIT(17));
2089
2090 /* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU */
2091 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff);
2092
2093 /* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */
2094 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df);
2095
2096 /* if GNT_WL = 0 && BT = Tx_group -->
2097 * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff)
2098 */
2099 if (btc->ant_type == BTC_ANT_SHARED && btc->btg_pos == path)
2100 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f);
2101 else
2102 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff);
2103
2104 /* set DEBUG_LUT_RFMODE_MASK = 0 to stop trx-mask-setup */
2105 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0);
2106 }
2107
2108 /* set PTA break table */
2109 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
2110
2111 /* enable BT counter 0xda40[16,2] = 2b'11 */
2112 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
2113
2114 btc->cx.wl.status.map.init_ok = true;
2115 }
2116
2117 static
rtw8851b_btc_set_wl_pri(struct rtw89_dev * rtwdev,u8 map,bool state)2118 void rtw8851b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
2119 {
2120 u32 bitmap;
2121 u32 reg;
2122
2123 switch (map) {
2124 case BTC_PRI_MASK_TX_RESP:
2125 reg = R_BTC_BT_COEX_MSK_TABLE;
2126 bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
2127 break;
2128 case BTC_PRI_MASK_BEACON:
2129 reg = R_AX_WL_PRI_MSK;
2130 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
2131 break;
2132 case BTC_PRI_MASK_RX_CCK:
2133 reg = R_BTC_BT_COEX_MSK_TABLE;
2134 bitmap = B_BTC_PRI_MASK_RXCCK_V1;
2135 break;
2136 default:
2137 return;
2138 }
2139
2140 if (state)
2141 rtw89_write32_set(rtwdev, reg, bitmap);
2142 else
2143 rtw89_write32_clr(rtwdev, reg, bitmap);
2144 }
2145
2146 union rtw8851b_btc_wl_txpwr_ctrl {
2147 u32 txpwr_val;
2148 struct {
2149 union {
2150 u16 ctrl_all_time;
2151 struct {
2152 s16 data:9;
2153 u16 rsvd:6;
2154 u16 flag:1;
2155 } all_time;
2156 };
2157 union {
2158 u16 ctrl_gnt_bt;
2159 struct {
2160 s16 data:9;
2161 u16 rsvd:7;
2162 } gnt_bt;
2163 };
2164 };
2165 } __packed;
2166
2167 static void
rtw8851b_btc_set_wl_txpwr_ctrl(struct rtw89_dev * rtwdev,u32 txpwr_val)2168 rtw8851b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2169 {
2170 union rtw8851b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
2171 s32 val;
2172
2173 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \
2174 do { \
2175 u32 _wrt = FIELD_PREP(_msk, _val); \
2176 BUILD_BUG_ON(!!(_msk & _en)); \
2177 if (_cond) \
2178 _wrt |= _en; \
2179 else \
2180 _wrt &= ~_en; \
2181 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
2182 _msk | _en, _wrt); \
2183 } while (0)
2184
2185 switch (arg.ctrl_all_time) {
2186 case 0xffff:
2187 val = 0;
2188 break;
2189 default:
2190 val = arg.all_time.data;
2191 break;
2192 }
2193
2194 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
2195 val, B_AX_FORCE_PWR_BY_RATE_EN,
2196 arg.ctrl_all_time != 0xffff);
2197
2198 switch (arg.ctrl_gnt_bt) {
2199 case 0xffff:
2200 val = 0;
2201 break;
2202 default:
2203 val = arg.gnt_bt.data;
2204 break;
2205 }
2206
2207 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
2208 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
2209
2210 #undef __write_ctrl
2211 }
2212
2213 static
rtw8851b_btc_get_bt_rssi(struct rtw89_dev * rtwdev,s8 val)2214 s8 rtw8851b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2215 {
2216 val = clamp_t(s8, val, -100, 0) + 100;
2217 val = min(val + 6, 100); /* compensate offset */
2218
2219 return val;
2220 }
2221
2222 static
rtw8851b_btc_update_bt_cnt(struct rtw89_dev * rtwdev)2223 void rtw8851b_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2224 {
2225 /* Feature move to firmware */
2226 }
2227
rtw8851b_btc_wl_s1_standby(struct rtw89_dev * rtwdev,bool state)2228 static void rtw8851b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2229 {
2230 struct rtw89_btc *btc = &rtwdev->btc;
2231
2232 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x80000);
2233 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWA, RFREG_MASK, 0x1);
2234 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD1, RFREG_MASK, 0x110);
2235
2236 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
2237 if (state)
2238 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x179c);
2239 else
2240 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x208);
2241
2242 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x0);
2243 }
2244
2245 #define LNA2_51B_MA 0x700
2246
2247 static const struct rtw89_reg2_def btc_8851b_rf_0[] = {{0x2, 0x0}};
2248 static const struct rtw89_reg2_def btc_8851b_rf_1[] = {{0x2, 0x1}};
2249
rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev * rtwdev,u32 level)2250 static void rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2251 {
2252 /* To improve BT ACI in co-rx
2253 * level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
2254 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
2255 */
2256 struct rtw89_btc *btc = &rtwdev->btc;
2257 const struct rtw89_reg2_def *rf;
2258 u32 n, i, val;
2259
2260 switch (level) {
2261 case 0: /* original */
2262 default:
2263 btc->dm.wl_lna2 = 0;
2264 break;
2265 case 1: /* for FDD free-run */
2266 btc->dm.wl_lna2 = 0;
2267 break;
2268 case 2: /* for BTG Co-Rx*/
2269 btc->dm.wl_lna2 = 1;
2270 break;
2271 }
2272
2273 if (btc->dm.wl_lna2 == 0) {
2274 rf = btc_8851b_rf_0;
2275 n = ARRAY_SIZE(btc_8851b_rf_0);
2276 } else {
2277 rf = btc_8851b_rf_1;
2278 n = ARRAY_SIZE(btc_8851b_rf_1);
2279 }
2280
2281 for (i = 0; i < n; i++, rf++) {
2282 val = rf->data;
2283 /* bit[10] = 1 if non-shared-ant for 8851b */
2284 if (btc->ant_type == BTC_ANT_DEDICATED)
2285 val |= 0x4;
2286
2287 rtw89_write_rf(rtwdev, btc->btg_pos, rf->addr, LNA2_51B_MA, val);
2288 }
2289 }
2290
rtw8851b_fill_freq_with_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2291 static void rtw8851b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2292 struct rtw89_rx_phy_ppdu *phy_ppdu,
2293 struct ieee80211_rx_status *status)
2294 {
2295 u16 chan = phy_ppdu->chan_idx;
2296 enum nl80211_band band;
2297 u8 ch;
2298
2299 if (chan == 0)
2300 return;
2301
2302 rtw89_decode_chan_idx(rtwdev, chan, &ch, &band);
2303 status->freq = ieee80211_channel_to_frequency(ch, band);
2304 status->band = band;
2305 }
2306
rtw8851b_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2307 static void rtw8851b_query_ppdu(struct rtw89_dev *rtwdev,
2308 struct rtw89_rx_phy_ppdu *phy_ppdu,
2309 struct ieee80211_rx_status *status)
2310 {
2311 u8 path;
2312 u8 *rx_power = phy_ppdu->rssi;
2313
2314 if (!status->signal)
2315 status->signal = RTW89_RSSI_RAW_TO_DBM(rx_power[RF_PATH_A]);
2316
2317 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2318 status->chains |= BIT(path);
2319 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2320 }
2321 if (phy_ppdu->valid)
2322 rtw8851b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2323 }
2324
rtw8851b_mac_enable_bb_rf(struct rtw89_dev * rtwdev)2325 static int rtw8851b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2326 {
2327 int ret;
2328
2329 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
2330 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2331 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2332 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2333 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2334
2335 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7,
2336 FULL_BIT_MASK);
2337 if (ret)
2338 return ret;
2339
2340 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7,
2341 FULL_BIT_MASK);
2342 if (ret)
2343 return ret;
2344
2345 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);
2346
2347 return 0;
2348 }
2349
rtw8851b_mac_disable_bb_rf(struct rtw89_dev * rtwdev)2350 static int rtw8851b_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2351 {
2352 u8 wl_rfc_s0;
2353 u8 wl_rfc_s1;
2354 int ret;
2355
2356 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2357 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
2358 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2359
2360 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
2361 if (ret)
2362 return ret;
2363 wl_rfc_s0 &= ~XTAL_SI_RF00S_EN;
2364 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
2365 FULL_BIT_MASK);
2366 if (ret)
2367 return ret;
2368
2369 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
2370 if (ret)
2371 return ret;
2372 wl_rfc_s1 &= ~XTAL_SI_RF10S_EN;
2373 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1,
2374 FULL_BIT_MASK);
2375 return ret;
2376 }
2377
2378 static const struct rtw89_chip_ops rtw8851b_chip_ops = {
2379 .enable_bb_rf = rtw8851b_mac_enable_bb_rf,
2380 .disable_bb_rf = rtw8851b_mac_disable_bb_rf,
2381 .bb_preinit = NULL,
2382 .bb_postinit = NULL,
2383 .bb_reset = rtw8851b_bb_reset,
2384 .bb_sethw = rtw8851b_bb_sethw,
2385 .read_rf = rtw89_phy_read_rf_v1,
2386 .write_rf = rtw89_phy_write_rf_v1,
2387 .set_channel = rtw8851b_set_channel,
2388 .set_channel_help = rtw8851b_set_channel_help,
2389 .read_efuse = rtw8851b_read_efuse,
2390 .read_phycap = rtw8851b_read_phycap,
2391 .fem_setup = NULL,
2392 .rfe_gpio = rtw8851b_rfe_gpio,
2393 .rfk_hw_init = NULL,
2394 .rfk_init = rtw8851b_rfk_init,
2395 .rfk_init_late = NULL,
2396 .rfk_channel = rtw8851b_rfk_channel,
2397 .rfk_band_changed = rtw8851b_rfk_band_changed,
2398 .rfk_scan = rtw8851b_rfk_scan,
2399 .rfk_track = rtw8851b_rfk_track,
2400 .power_trim = rtw8851b_power_trim,
2401 .set_txpwr = rtw8851b_set_txpwr,
2402 .set_txpwr_ctrl = rtw8851b_set_txpwr_ctrl,
2403 .init_txpwr_unit = rtw8851b_init_txpwr_unit,
2404 .get_thermal = rtw8851b_get_thermal,
2405 .ctrl_btg_bt_rx = rtw8851b_ctrl_btg_bt_rx,
2406 .query_ppdu = rtw8851b_query_ppdu,
2407 .convert_rpl_to_rssi = NULL,
2408 .phy_rpt_to_rssi = NULL,
2409 .ctrl_nbtg_bt_tx = rtw8851b_ctrl_nbtg_bt_tx,
2410 .cfg_txrx_path = rtw8851b_bb_cfg_txrx_path,
2411 .set_txpwr_ul_tb_offset = rtw8851b_set_txpwr_ul_tb_offset,
2412 .digital_pwr_comp = NULL,
2413 .pwr_on_func = rtw8851b_pwr_on_func,
2414 .pwr_off_func = rtw8851b_pwr_off_func,
2415 .query_rxdesc = rtw89_core_query_rxdesc,
2416 .fill_txdesc = rtw89_core_fill_txdesc,
2417 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
2418 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
2419 .mac_cfg_gnt = rtw89_mac_cfg_gnt,
2420 .stop_sch_tx = rtw89_mac_stop_sch_tx,
2421 .resume_sch_tx = rtw89_mac_resume_sch_tx,
2422 .h2c_dctl_sec_cam = NULL,
2423 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl,
2424 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl,
2425 .h2c_ampdu_cmac_tbl = NULL,
2426 .h2c_txtime_cmac_tbl = rtw89_fw_h2c_txtime_cmac_tbl,
2427 .h2c_default_dmac_tbl = NULL,
2428 .h2c_update_beacon = rtw89_fw_h2c_update_beacon,
2429 .h2c_ba_cam = rtw89_fw_h2c_ba_cam,
2430
2431 .btc_set_rfe = rtw8851b_btc_set_rfe,
2432 .btc_init_cfg = rtw8851b_btc_init_cfg,
2433 .btc_set_wl_pri = rtw8851b_btc_set_wl_pri,
2434 .btc_set_wl_txpwr_ctrl = rtw8851b_btc_set_wl_txpwr_ctrl,
2435 .btc_get_bt_rssi = rtw8851b_btc_get_bt_rssi,
2436 .btc_update_bt_cnt = rtw8851b_btc_update_bt_cnt,
2437 .btc_wl_s1_standby = rtw8851b_btc_wl_s1_standby,
2438 .btc_set_wl_rx_gain = rtw8851b_btc_set_wl_rx_gain,
2439 .btc_set_policy = rtw89_btc_set_policy_v1,
2440 };
2441
2442 #ifdef CONFIG_PM
2443 static const struct wiphy_wowlan_support rtw_wowlan_stub_8851b = {
2444 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2445 .n_patterns = RTW89_MAX_PATTERN_NUM,
2446 .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
2447 .pattern_min_len = 1,
2448 };
2449 #endif
2450
2451 const struct rtw89_chip_info rtw8851b_chip_info = {
2452 .chip_id = RTL8851B,
2453 .chip_gen = RTW89_CHIP_AX,
2454 .ops = &rtw8851b_chip_ops,
2455 .mac_def = &rtw89_mac_gen_ax,
2456 .phy_def = &rtw89_phy_gen_ax,
2457 .fw_basename = RTW8851B_FW_BASENAME,
2458 .fw_format_max = RTW8851B_FW_FORMAT_MAX,
2459 .try_ce_fw = true,
2460 .bbmcu_nr = 0,
2461 .needed_fw_elms = 0,
2462 .fw_blacklist = NULL,
2463 .fifo_size = 196608,
2464 .small_fifo_size = true,
2465 .dle_scc_rsvd_size = 98304,
2466 .max_amsdu_limit = 3500,
2467 .dis_2g_40m_ul_ofdma = true,
2468 .rsvd_ple_ofst = 0x2f800,
2469 .hfc_param_ini = rtw8851b_hfc_param_ini_pcie,
2470 .dle_mem = rtw8851b_dle_mem_pcie,
2471 .wde_qempty_acq_grpnum = 4,
2472 .wde_qempty_mgq_grpsel = 4,
2473 .rf_base_addr = {0xe000},
2474 .thermal_th = {0x32, 0x35},
2475 .pwr_on_seq = NULL,
2476 .pwr_off_seq = NULL,
2477 .bb_table = &rtw89_8851b_phy_bb_table,
2478 .bb_gain_table = &rtw89_8851b_phy_bb_gain_table,
2479 .rf_table = {&rtw89_8851b_phy_radioa_table,},
2480 .nctl_table = &rtw89_8851b_phy_nctl_table,
2481 .nctl_post_table = &rtw8851b_nctl_post_defs_tbl,
2482 .dflt_parms = &rtw89_8851b_dflt_parms,
2483 .rfe_parms_conf = rtw89_8851b_rfe_parms_conf,
2484 .txpwr_factor_bb = 3,
2485 .txpwr_factor_rf = 2,
2486 .txpwr_factor_mac = 1,
2487 .dig_table = NULL,
2488 .dig_regs = &rtw8851b_dig_regs,
2489 .tssi_dbw_table = NULL,
2490 .support_macid_num = RTW89_MAX_MAC_ID_NUM,
2491 .support_link_num = 0,
2492 .support_chanctx_num = 0,
2493 .support_rnr = false,
2494 .support_bands = BIT(NL80211_BAND_2GHZ) |
2495 BIT(NL80211_BAND_5GHZ),
2496 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
2497 BIT(NL80211_CHAN_WIDTH_40) |
2498 BIT(NL80211_CHAN_WIDTH_80),
2499 .support_unii4 = true,
2500 .support_ant_gain = false,
2501 .support_tas = false,
2502 .ul_tb_waveform_ctrl = true,
2503 .ul_tb_pwr_diff = false,
2504 .rx_freq_frome_ie = true,
2505 .hw_sec_hdr = false,
2506 .hw_mgmt_tx_encrypt = false,
2507 .hw_tkip_crypto = false,
2508 .rf_path_num = 1,
2509 .tx_nss = 1,
2510 .rx_nss = 1,
2511 .acam_num = 32,
2512 .bcam_num = 20,
2513 .scam_num = 128,
2514 .bacam_num = 2,
2515 .bacam_dynamic_num = 4,
2516 .bacam_ver = RTW89_BACAM_V0,
2517 .ppdu_max_usr = 4,
2518 .sec_ctrl_efuse_size = 4,
2519 .physical_efuse_size = 1216,
2520 .logical_efuse_size = 2048,
2521 .limit_efuse_size = 1280,
2522 .dav_phy_efuse_size = 0,
2523 .dav_log_efuse_size = 0,
2524 .efuse_blocks = NULL,
2525 .phycap_addr = 0x580,
2526 .phycap_size = 128,
2527 .para_ver = 0,
2528 .wlcx_desired = 0x06000000,
2529 .btcx_desired = 0x7,
2530 .scbd = 0x1,
2531 .mailbox = 0x1,
2532
2533 .afh_guard_ch = 6,
2534 .wl_rssi_thres = rtw89_btc_8851b_wl_rssi_thres,
2535 .bt_rssi_thres = rtw89_btc_8851b_bt_rssi_thres,
2536 .rssi_tol = 2,
2537 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8851b_mon_reg),
2538 .mon_reg = rtw89_btc_8851b_mon_reg,
2539 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_ul),
2540 .rf_para_ulink = rtw89_btc_8851b_rf_ul,
2541 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_dl),
2542 .rf_para_dlink = rtw89_btc_8851b_rf_dl,
2543 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
2544 BIT(RTW89_PS_MODE_CLK_GATED),
2545 .low_power_hci_modes = 0,
2546 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
2547 .hci_func_en_addr = R_AX_HCI_FUNC_EN,
2548 .h2c_desc_size = sizeof(struct rtw89_txwd_body),
2549 .txwd_body_size = sizeof(struct rtw89_txwd_body),
2550 .txwd_info_size = sizeof(struct rtw89_txwd_info),
2551 .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
2552 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
2553 .h2c_regs = rtw8851b_h2c_regs,
2554 .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
2555 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
2556 .c2h_regs = rtw8851b_c2h_regs,
2557 .page_regs = &rtw8851b_page_regs,
2558 .wow_reason_reg = rtw8851b_wow_wakeup_regs,
2559 .cfo_src_fd = true,
2560 .cfo_hw_comp = true,
2561 .dcfo_comp = &rtw8851b_dcfo_comp,
2562 .dcfo_comp_sft = 12,
2563 .imr_info = &rtw8851b_imr_info,
2564 .imr_dmac_table = NULL,
2565 .imr_cmac_table = NULL,
2566 .rrsr_cfgs = &rtw8851b_rrsr_cfgs,
2567 .bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0},
2568 .bss_clr_map_reg = R_BSS_CLR_MAP_V1,
2569 .rfkill_init = &rtw8851b_rfkill_regs,
2570 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
2571 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
2572 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
2573 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
2574 .edcca_regs = &rtw8851b_edcca_regs,
2575 #ifdef CONFIG_PM
2576 .wowlan_stub = &rtw_wowlan_stub_8851b,
2577 #endif
2578 .xtal_info = &rtw8851b_xtal_info,
2579 };
2580 EXPORT_SYMBOL(rtw8851b_chip_info);
2581
2582 MODULE_FIRMWARE(RTW8851B_MODULE_FIRMWARE);
2583 MODULE_AUTHOR("Realtek Corporation");
2584 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8851B driver");
2585 MODULE_LICENSE("Dual BSD/GPL");
2586