1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2020 Henri Hennebert <hlh@restart.be> 7 * Copyright (c) 2020 Gary Jennejohn <gj@freebsd.org> 8 * Copyright (c) 2020 Jesper Schmitz Mouridsen <jsm@FreeBSD.org> 9 * All rights reserved. 10 * 11 * Patch from: 12 * - Lutz Bichler <Lutz.Bichler@gmail.com> 13 * 14 * Base on OpenBSD /sys/dev/pci/rtsx_pci.c & /dev/ic/rtsx.c 15 * on Linux /drivers/mmc/host/rtsx_pci_sdmmc.c, 16 * /include/linux/rtsx_pci.h & 17 * /drivers/misc/cardreader/rtsx_pcr.c 18 * on NetBSD /sys/dev/ic/rtsx.c 19 * 20 * Permission to use, copy, modify, and distribute this software for any 21 * purpose with or without fee is hereby granted, provided that the above 22 * copyright notice and this permission notice appear in all copies. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/module.h> 39 #include <sys/systm.h> /* For FreeBSD 11 */ 40 #include <sys/types.h> /* For FreeBSD 11 */ 41 #include <sys/errno.h> 42 #include <sys/kernel.h> 43 #include <sys/bus.h> 44 #include <sys/endian.h> 45 #include <machine/bus.h> 46 #include <sys/mutex.h> 47 #include <sys/malloc.h> 48 #include <sys/rman.h> 49 #include <sys/queue.h> 50 #include <sys/taskqueue.h> 51 #include <sys/sysctl.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/mmc/bridge.h> 55 #include <dev/mmc/mmcreg.h> 56 #include <dev/mmc/mmcbrvar.h> 57 #include <machine/_inttypes.h> 58 59 #include "opt_mmccam.h" 60 61 #ifdef MMCCAM 62 #include <cam/cam.h> 63 #include <cam/cam_ccb.h> 64 #include <cam/cam_debug.h> 65 #include <cam/cam_sim.h> 66 #include <cam/cam_xpt_sim.h> 67 #include <cam/mmc/mmc_sim.h> 68 #include "mmc_sim_if.h" 69 #endif /* MMCCAM */ 70 71 #include "rtsxreg.h" 72 73 /* The softc holds our per-instance data. */ 74 struct rtsx_softc { 75 struct mtx rtsx_mtx; /* device mutex */ 76 device_t rtsx_dev; /* device */ 77 uint16_t rtsx_flags; /* device flags */ 78 uint16_t rtsx_device_id; /* device ID */ 79 device_t rtsx_mmc_dev; /* device of mmc bus */ 80 uint32_t rtsx_intr_enabled; /* enabled interrupts */ 81 uint32_t rtsx_intr_status; /* soft interrupt status */ 82 int rtsx_irq_res_id; /* bus IRQ resource id */ 83 struct resource *rtsx_irq_res; /* bus IRQ resource */ 84 void *rtsx_irq_cookie; /* bus IRQ resource cookie */ 85 struct callout rtsx_timeout_callout; /* callout for timeout */ 86 int rtsx_timeout_cmd; /* interrupt timeout for setup commands */ 87 int rtsx_timeout_io; /* interrupt timeout for I/O commands */ 88 void (*rtsx_intr_trans_ok)(struct rtsx_softc *sc); 89 /* function to call if transfer succeed */ 90 void (*rtsx_intr_trans_ko)(struct rtsx_softc *sc); 91 /* function to call if transfer fail */ 92 93 struct timeout_task 94 rtsx_card_insert_task; /* card insert delayed task */ 95 struct task rtsx_card_remove_task; /* card remove task */ 96 97 int rtsx_mem_res_id; /* bus memory resource id */ 98 struct resource *rtsx_mem_res; /* bus memory resource */ 99 bus_space_tag_t rtsx_mem_btag; /* host register set tag */ 100 bus_space_handle_t rtsx_mem_bhandle; /* host register set handle */ 101 102 bus_dma_tag_t rtsx_cmd_dma_tag; /* DMA tag for command transfer */ 103 bus_dmamap_t rtsx_cmd_dmamap; /* DMA map for command transfer */ 104 void *rtsx_cmd_dmamem; /* DMA mem for command transfer */ 105 bus_addr_t rtsx_cmd_buffer; /* device visible address of the DMA segment */ 106 int rtsx_cmd_index; /* index in rtsx_cmd_buffer */ 107 108 bus_dma_tag_t rtsx_data_dma_tag; /* DMA tag for data transfer */ 109 bus_dmamap_t rtsx_data_dmamap; /* DMA map for data transfer */ 110 void *rtsx_data_dmamem; /* DMA mem for data transfer */ 111 bus_addr_t rtsx_data_buffer; /* device visible address of the DMA segment */ 112 113 #ifdef MMCCAM 114 union ccb *rtsx_ccb; /* CAM control block */ 115 struct mmc_sim rtsx_mmc_sim; /* CAM generic sim */ 116 struct mmc_request rtsx_cam_req; /* CAM MMC request */ 117 #endif /* MMCCAM */ 118 119 struct mmc_request *rtsx_req; /* MMC request */ 120 struct mmc_host rtsx_host; /* host parameters */ 121 int rtsx_pcie_cap; /* PCIe capability offset */ 122 int8_t rtsx_bus_busy; /* bus busy status */ 123 int8_t rtsx_ios_bus_width; /* current host.ios.bus_width */ 124 int32_t rtsx_ios_clock; /* current host.ios.clock */ 125 int8_t rtsx_ios_power_mode; /* current host.ios.power mode */ 126 int8_t rtsx_ios_timing; /* current host.ios.timing */ 127 int8_t rtsx_ios_vccq; /* current host.ios.vccq */ 128 uint8_t rtsx_read_only; /* card read only status */ 129 uint8_t rtsx_inversion; /* inversion of card detection and read only status */ 130 uint8_t rtsx_force_timing; /* force bus_timing_uhs_sdr50 */ 131 uint8_t rtsx_debug_mask; /* debugging mask */ 132 #define RTSX_DEBUG_BASIC 0x01 /* debug basic flow */ 133 #define RTSX_TRACE_SD_CMD 0x02 /* trace SD commands */ 134 #define RTSX_DEBUG_TUNING 0x04 /* debug tuning */ 135 #ifdef MMCCAM 136 uint8_t rtsx_cam_status; /* CAM status - 1 if card in use */ 137 #endif /* MMCCAM */ 138 uint64_t rtsx_read_count; /* count of read operations */ 139 uint64_t rtsx_write_count; /* count of write operations */ 140 bool rtsx_discovery_mode; /* are we in discovery mode? */ 141 bool rtsx_tuning_mode; /* are we tuning */ 142 bool rtsx_double_clk; /* double clock freqency */ 143 bool rtsx_vpclk; /* voltage at Pulse-width Modulation(PWM) clock? */ 144 uint8_t rtsx_ssc_depth; /* Spread spectrum clocking depth */ 145 uint8_t rtsx_card_drive_sel; /* value for RTSX_CARD_DRIVE_SEL */ 146 uint8_t rtsx_sd30_drive_sel_3v3;/* value for RTSX_SD30_DRIVE_SEL */ 147 }; 148 149 /* rtsx_flags values */ 150 #define RTSX_F_DEFAULT 0x0000 151 #define RTSX_F_CARD_PRESENT 0x0001 152 #define RTSX_F_SDIO_SUPPORT 0x0002 153 #define RTSX_F_VERSION_A 0x0004 154 #define RTSX_F_VERSION_B 0x0008 155 #define RTSX_F_VERSION_C 0x0010 156 #define RTSX_F_VERSION_D 0x0020 157 #define RTSX_F_8411B_QFN48 0x0040 158 #define RTSX_F_REVERSE_SOCKET 0x0080 159 160 #define RTSX_REALTEK 0x10ec 161 #define RTSX_RTS5209 0x5209 162 #define RTSX_RTS5227 0x5227 163 #define RTSX_RTS5229 0x5229 164 #define RTSX_RTS522A 0x522a 165 #define RTSX_RTS525A 0x525a 166 #define RTSX_RTS5249 0x5249 167 #define RTSX_RTS5260 0x5260 168 #define RTSX_RTL8402 0x5286 169 #define RTSX_RTL8411 0x5289 170 #define RTSX_RTL8411B 0x5287 171 172 #define RTSX_VERSION "2.1g" 173 174 static const struct rtsx_pciids { 175 uint16_t device_id; 176 const char *desc; 177 } rtsx_ids[] = { 178 { RTSX_RTS5209, RTSX_VERSION " Realtek RTS5209 PCIe SD Card Reader" }, 179 { RTSX_RTS5227, RTSX_VERSION " Realtek RTS5227 PCIe SD Card Reader" }, 180 { RTSX_RTS5229, RTSX_VERSION " Realtek RTS5229 PCIe SD Card Reader" }, 181 { RTSX_RTS522A, RTSX_VERSION " Realtek RTS522A PCIe SD Card Reader" }, 182 { RTSX_RTS525A, RTSX_VERSION " Realtek RTS525A PCIe SD Card Reader" }, 183 { RTSX_RTS5249, RTSX_VERSION " Realtek RTS5249 PCIe SD Card Reader" }, 184 { RTSX_RTS5260, RTSX_VERSION " Realtek RTS5260 PCIe SD Card Reader" }, 185 { RTSX_RTL8402, RTSX_VERSION " Realtek RTL8402 PCIe SD Card Reader" }, 186 { RTSX_RTL8411, RTSX_VERSION " Realtek RTL8411 PCIe SD Card Reader" }, 187 { RTSX_RTL8411B, RTSX_VERSION " Realtek RTL8411B PCIe SD Card Reader" }, 188 }; 189 190 /* See `kenv | grep smbios.system` */ 191 static const struct rtsx_inversion_model { 192 char *maker; 193 char *family; 194 char *product; 195 } rtsx_inversion_models[] = { 196 { "LENOVO", "ThinkPad T470p", "20J7S0PM00"}, 197 { "LENOVO", "ThinkPad X13 Gen 1", "20UF000QRT"}, 198 { NULL, NULL, NULL} 199 }; 200 201 static int rtsx_dma_alloc(struct rtsx_softc *sc); 202 static void rtsx_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 203 static void rtsx_dma_free(struct rtsx_softc *sc); 204 static void rtsx_intr(void *arg); 205 static void rtsx_handle_card_present(struct rtsx_softc *sc); 206 static void rtsx_card_task(void *arg, int pending __unused); 207 static bool rtsx_is_card_present(struct rtsx_softc *sc); 208 static int rtsx_init(struct rtsx_softc *sc); 209 static int rtsx_map_sd_drive(int index); 210 static int rtsx_rts5227_fill_driving(struct rtsx_softc *sc); 211 static int rtsx_rts5249_fill_driving(struct rtsx_softc *sc); 212 static int rtsx_rts5260_fill_driving(struct rtsx_softc *sc); 213 static int rtsx_read(struct rtsx_softc *, uint16_t, uint8_t *); 214 static int rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val); 215 static int rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val); 216 static int rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val); 217 static int rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val); 218 static int rtsx_bus_power_off(struct rtsx_softc *sc); 219 static int rtsx_bus_power_on(struct rtsx_softc *sc); 220 static int rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width); 221 static int rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing); 222 static int rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq); 223 static int rtsx_stop_sd_clock(struct rtsx_softc *sc); 224 static int rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu); 225 #ifndef MMCCAM 226 static void rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point); 227 static void rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point); 228 static void rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map); 229 static int rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point); 230 static int rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd); 231 static void rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc); 232 static void rtsx_sd_wait_data_idle(struct rtsx_softc *sc); 233 static uint8_t rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map); 234 static int rtsx_sd_get_rx_phase_len(uint32_t phase_map, int start_bit); 235 #endif /* !MMCCAM */ 236 #if 0 /* For led */ 237 static int rtsx_led_enable(struct rtsx_softc *sc); 238 static int rtsx_led_disable(struct rtsx_softc *sc); 239 #endif /* For led */ 240 static uint8_t rtsx_response_type(uint16_t mmc_rsp); 241 static void rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd); 242 static void rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg, 243 uint8_t mask, uint8_t data); 244 static void rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt); 245 static void rtsx_send_cmd(struct rtsx_softc *sc); 246 static void rtsx_ret_resp(struct rtsx_softc *sc); 247 static void rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd); 248 static void rtsx_stop_cmd(struct rtsx_softc *sc); 249 static void rtsx_clear_error(struct rtsx_softc *sc); 250 static void rtsx_req_done(struct rtsx_softc *sc); 251 static int rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd); 252 static int rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd); 253 static void rtsx_ask_ppbuf_part1(struct rtsx_softc *sc); 254 static void rtsx_get_ppbuf_part1(struct rtsx_softc *sc); 255 static void rtsx_get_ppbuf_part2(struct rtsx_softc *sc); 256 static void rtsx_put_ppbuf_part1(struct rtsx_softc *sc); 257 static void rtsx_put_ppbuf_part2(struct rtsx_softc *sc); 258 static void rtsx_write_ppbuf(struct rtsx_softc *sc); 259 static int rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd); 260 static void rtsx_xfer_begin(struct rtsx_softc *sc); 261 static void rtsx_xfer_start(struct rtsx_softc *sc); 262 static void rtsx_xfer_finish(struct rtsx_softc *sc); 263 static void rtsx_timeout(void *arg); 264 265 #ifdef MMCCAM 266 static int rtsx_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts); 267 static int rtsx_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts); 268 static int rtsx_cam_request(device_t dev, union ccb *ccb); 269 #endif /* MMCCAM */ 270 271 static int rtsx_read_ivar(device_t bus, device_t child, int which, uintptr_t *result); 272 static int rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value); 273 274 static int rtsx_mmcbr_update_ios(device_t bus, device_t child __unused); 275 static int rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused); 276 static int rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req); 277 #ifndef MMCCAM 278 static int rtsx_mmcbr_tune(device_t bus, device_t child __unused, bool hs400 __unused); 279 static int rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused); 280 static int rtsx_mmcbr_get_ro(device_t bus, device_t child __unused); 281 static int rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused); 282 static int rtsx_mmcbr_release_host(device_t bus, device_t child __unused); 283 #endif /* !MMCCAM */ 284 285 static int rtsx_probe(device_t dev); 286 static int rtsx_attach(device_t dev); 287 static int rtsx_detach(device_t dev); 288 static int rtsx_shutdown(device_t dev); 289 static int rtsx_suspend(device_t dev); 290 static int rtsx_resume(device_t dev); 291 292 #define RTSX_LOCK_INIT(_sc) mtx_init(&(_sc)->rtsx_mtx, \ 293 device_get_nameunit(sc->rtsx_dev), "rtsx", MTX_DEF) 294 #define RTSX_LOCK(_sc) mtx_lock(&(_sc)->rtsx_mtx) 295 #define RTSX_UNLOCK(_sc) mtx_unlock(&(_sc)->rtsx_mtx) 296 #define RTSX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rtsx_mtx) 297 298 #define RTSX_SDCLK_OFF 0 299 #define RTSX_SDCLK_250KHZ 250000 300 #define RTSX_SDCLK_400KHZ 400000 301 #define RTSX_SDCLK_25MHZ 25000000 302 #define RTSX_SDCLK_50MHZ 50000000 303 #define RTSX_SDCLK_100MHZ 100000000 304 #define RTSX_SDCLK_208MHZ 208000000 305 306 #define RTSX_MIN_DIV_N 80 307 #define RTSX_MAX_DIV_N 208 308 309 #define RTSX_MAX_DATA_BLKLEN 512 310 311 #define RTSX_DMA_ALIGN 4 312 #define RTSX_HOSTCMD_MAX 256 313 #define RTSX_DMA_CMD_BIFSIZE (sizeof(uint32_t) * RTSX_HOSTCMD_MAX) 314 #define RTSX_DMA_DATA_BUFSIZE maxphys 315 316 #define ISSET(t, f) ((t) & (f)) 317 318 #define READ4(sc, reg) \ 319 (bus_space_read_4((sc)->rtsx_mem_btag, (sc)->rtsx_mem_bhandle, (reg))) 320 #define WRITE4(sc, reg, val) \ 321 (bus_space_write_4((sc)->rtsx_mem_btag, (sc)->rtsx_mem_bhandle, (reg), (val))) 322 323 #define RTSX_READ(sc, reg, val) \ 324 do { \ 325 int err = rtsx_read((sc), (reg), (val)); \ 326 if (err) \ 327 return (err); \ 328 } while (0) 329 330 #define RTSX_WRITE(sc, reg, val) \ 331 do { \ 332 int err = rtsx_write((sc), (reg), 0xff, (val)); \ 333 if (err) \ 334 return (err); \ 335 } while (0) 336 #define RTSX_CLR(sc, reg, bits) \ 337 do { \ 338 int err = rtsx_write((sc), (reg), (bits), 0); \ 339 if (err) \ 340 return (err); \ 341 } while (0) 342 343 #define RTSX_SET(sc, reg, bits) \ 344 do { \ 345 int err = rtsx_write((sc), (reg), (bits), 0xff);\ 346 if (err) \ 347 return (err); \ 348 } while (0) 349 350 #define RTSX_BITOP(sc, reg, mask, bits) \ 351 do { \ 352 int err = rtsx_write((sc), (reg), (mask), (bits)); \ 353 if (err) \ 354 return (err); \ 355 } while (0) 356 357 /* 358 * We use two DMA buffers: a command buffer and a data buffer. 359 * 360 * The command buffer contains a command queue for the host controller, 361 * which describes SD/MMC commands to run, and other parameters. The chip 362 * runs the command queue when a special bit in the RTSX_HCBAR register is 363 * set and signals completion with the RTSX_TRANS_OK_INT interrupt. 364 * Each command is encoded as a 4 byte sequence containing command number 365 * (read, write, or check a host controller register), a register address, 366 * and a data bit-mask and value. 367 * SD/MMC commands which do not transfer any data from/to the card only use 368 * the command buffer. 369 * 370 * The data buffer is used for transfer longer than 512. Data transfer is 371 * controlled via the RTSX_HDBAR register and completion is signalled by 372 * the RTSX_TRANS_OK_INT interrupt. 373 * 374 * The chip is unable to perform DMA above 4GB. 375 */ 376 377 /* 378 * Main commands in the usual seqence used: 379 * 380 * CMD0 Go idle state 381 * CMD8 Send interface condition 382 * CMD55 Application Command for next ACMD 383 * ACMD41 Send Operation Conditions Register (OCR: voltage profile of the card) 384 * CMD2 Send Card Identification (CID) Register 385 * CMD3 Send relative address 386 * CMD9 Send Card Specific Data (CSD) 387 * CMD13 Send status (32 bits - bit 25: card password protected) 388 * CMD7 Select card (before Get card SCR) 389 * ACMD51 Send SCR (SD CARD Configuration Register - [51:48]: Bus widths supported) 390 * CMD6 SD switch function 391 * ACMD13 Send SD status (512 bits) 392 * ACMD42 Set/Clear card detect 393 * ACMD6 Set bus width 394 * CMD19 Send tuning block 395 * CMD12 Stop transmission 396 * 397 * CMD17 Read single block (<=512) 398 * CMD18 Read multiple blocks (>512) 399 * CMD24 Write single block (<=512) 400 * CMD25 Write multiple blocks (>512) 401 * 402 * CMD52 IO R/W direct 403 * CMD5 Send Operation Conditions 404 */ 405 406 static int rtsx_dma_alloc(struct rtsx_softc * sc)407 rtsx_dma_alloc(struct rtsx_softc *sc) 408 { 409 int error = 0; 410 411 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ 412 RTSX_DMA_ALIGN, 0, /* alignment, boundary */ 413 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 414 BUS_SPACE_MAXADDR, /* highaddr */ 415 NULL, NULL, /* filter, filterarg */ 416 RTSX_DMA_CMD_BIFSIZE, 1, /* maxsize, nsegments */ 417 RTSX_DMA_CMD_BIFSIZE, /* maxsegsize */ 418 0, /* flags */ 419 NULL, NULL, /* lockfunc, lockarg */ 420 &sc->rtsx_cmd_dma_tag); 421 if (error) { 422 device_printf(sc->rtsx_dev, 423 "Can't create cmd parent DMA tag\n"); 424 return (error); 425 } 426 error = bus_dmamem_alloc(sc->rtsx_cmd_dma_tag, /* DMA tag */ 427 &sc->rtsx_cmd_dmamem, /* will hold the KVA pointer */ 428 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, /* flags */ 429 &sc->rtsx_cmd_dmamap); /* DMA map */ 430 if (error) { 431 device_printf(sc->rtsx_dev, 432 "Can't create DMA map for command transfer\n"); 433 goto destroy_cmd_dma_tag; 434 435 } 436 error = bus_dmamap_load(sc->rtsx_cmd_dma_tag, /* DMA tag */ 437 sc->rtsx_cmd_dmamap, /* DMA map */ 438 sc->rtsx_cmd_dmamem, /* KVA pointer to be mapped */ 439 RTSX_DMA_CMD_BIFSIZE, /* size of buffer */ 440 rtsx_dmamap_cb, /* callback */ 441 &sc->rtsx_cmd_buffer, /* first arg of callback */ 442 0); /* flags */ 443 if (error || sc->rtsx_cmd_buffer == 0) { 444 device_printf(sc->rtsx_dev, 445 "Can't load DMA memory for command transfer\n"); 446 error = (error) ? error : EFAULT; 447 goto destroy_cmd_dmamem_alloc; 448 } 449 450 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ 451 RTSX_DMA_DATA_BUFSIZE, 0, /* alignment, boundary */ 452 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 453 BUS_SPACE_MAXADDR, /* highaddr */ 454 NULL, NULL, /* filter, filterarg */ 455 RTSX_DMA_DATA_BUFSIZE, 1, /* maxsize, nsegments */ 456 RTSX_DMA_DATA_BUFSIZE, /* maxsegsize */ 457 0, /* flags */ 458 NULL, NULL, /* lockfunc, lockarg */ 459 &sc->rtsx_data_dma_tag); 460 if (error) { 461 device_printf(sc->rtsx_dev, 462 "Can't create data parent DMA tag\n"); 463 goto destroy_cmd_dmamap_load; 464 } 465 error = bus_dmamem_alloc(sc->rtsx_data_dma_tag, /* DMA tag */ 466 &sc->rtsx_data_dmamem, /* will hold the KVA pointer */ 467 BUS_DMA_WAITOK | BUS_DMA_ZERO, /* flags */ 468 &sc->rtsx_data_dmamap); /* DMA map */ 469 if (error) { 470 device_printf(sc->rtsx_dev, 471 "Can't create DMA map for data transfer\n"); 472 goto destroy_data_dma_tag; 473 } 474 error = bus_dmamap_load(sc->rtsx_data_dma_tag, /* DMA tag */ 475 sc->rtsx_data_dmamap, /* DMA map */ 476 sc->rtsx_data_dmamem, /* KVA pointer to be mapped */ 477 RTSX_DMA_DATA_BUFSIZE, /* size of buffer */ 478 rtsx_dmamap_cb, /* callback */ 479 &sc->rtsx_data_buffer, /* first arg of callback */ 480 0); /* flags */ 481 if (error || sc->rtsx_data_buffer == 0) { 482 device_printf(sc->rtsx_dev, 483 "Can't load DMA memory for data transfer\n"); 484 error = (error) ? error : EFAULT; 485 goto destroy_data_dmamem_alloc; 486 } 487 return (error); 488 489 destroy_data_dmamem_alloc: 490 bus_dmamem_free(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamem, sc->rtsx_data_dmamap); 491 destroy_data_dma_tag: 492 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); 493 destroy_cmd_dmamap_load: 494 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap); 495 destroy_cmd_dmamem_alloc: 496 bus_dmamem_free(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamem, sc->rtsx_cmd_dmamap); 497 destroy_cmd_dma_tag: 498 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); 499 500 return (error); 501 } 502 503 static void rtsx_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)504 rtsx_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 505 { 506 if (error) { 507 printf("rtsx_dmamap_cb: error %d\n", error); 508 return; 509 } 510 *(bus_addr_t *)arg = segs[0].ds_addr; 511 } 512 513 static void rtsx_dma_free(struct rtsx_softc * sc)514 rtsx_dma_free(struct rtsx_softc *sc) 515 { 516 if (sc->rtsx_cmd_dma_tag != NULL) { 517 if (sc->rtsx_cmd_dmamap != NULL) 518 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, 519 sc->rtsx_cmd_dmamap); 520 if (sc->rtsx_cmd_dmamem != NULL) 521 bus_dmamem_free(sc->rtsx_cmd_dma_tag, 522 sc->rtsx_cmd_dmamem, 523 sc->rtsx_cmd_dmamap); 524 sc->rtsx_cmd_dmamap = NULL; 525 sc->rtsx_cmd_dmamem = NULL; 526 sc->rtsx_cmd_buffer = 0; 527 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); 528 sc->rtsx_cmd_dma_tag = NULL; 529 } 530 if (sc->rtsx_data_dma_tag != NULL) { 531 if (sc->rtsx_data_dmamap != NULL) 532 bus_dmamap_unload(sc->rtsx_data_dma_tag, 533 sc->rtsx_data_dmamap); 534 if (sc->rtsx_data_dmamem != NULL) 535 bus_dmamem_free(sc->rtsx_data_dma_tag, 536 sc->rtsx_data_dmamem, 537 sc->rtsx_data_dmamap); 538 sc->rtsx_data_dmamap = NULL; 539 sc->rtsx_data_dmamem = NULL; 540 sc->rtsx_data_buffer = 0; 541 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); 542 sc->rtsx_data_dma_tag = NULL; 543 } 544 } 545 546 static void rtsx_intr(void * arg)547 rtsx_intr(void *arg) 548 { 549 struct rtsx_softc *sc = arg; 550 uint32_t enabled; 551 uint32_t status; 552 553 RTSX_LOCK(sc); 554 555 enabled = sc->rtsx_intr_enabled; 556 status = READ4(sc, RTSX_BIPR); /* read Bus Interrupt Pending Register */ 557 sc->rtsx_intr_status = status; 558 559 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 560 device_printf(sc->rtsx_dev, "Interrupt handler - enabled: 0x%08x, status: 0x%08x\n", enabled, status); 561 562 /* Ack interrupts. */ 563 WRITE4(sc, RTSX_BIPR, status); 564 565 if (((enabled & status) == 0) || status == 0xffffffff) { 566 device_printf(sc->rtsx_dev, "Spurious interrupt - enabled: 0x%08x, status: 0x%08x\n", enabled, status); 567 RTSX_UNLOCK(sc); 568 return; 569 } 570 571 /* Detect write protect. */ 572 if (status & RTSX_SD_WRITE_PROTECT) 573 sc->rtsx_read_only = 1; 574 else 575 sc->rtsx_read_only = 0; 576 577 /* Start task to handle SD card status change (from dwmmc.c). */ 578 if (status & RTSX_SD_INT) { 579 device_printf(sc->rtsx_dev, "Interrupt card inserted/removed\n"); 580 rtsx_handle_card_present(sc); 581 } 582 583 if (sc->rtsx_req == NULL) { 584 RTSX_UNLOCK(sc); 585 return; 586 } 587 588 if (status & RTSX_TRANS_OK_INT) { 589 sc->rtsx_req->cmd->error = MMC_ERR_NONE; 590 if (sc->rtsx_intr_trans_ok != NULL) 591 sc->rtsx_intr_trans_ok(sc); 592 } else if (status & RTSX_TRANS_FAIL_INT) { 593 uint8_t stat1; 594 sc->rtsx_req->cmd->error = MMC_ERR_FAILED; 595 if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 && 596 (stat1 & RTSX_SD_CRC_ERR)) { 597 device_printf(sc->rtsx_dev, "CRC error\n"); 598 sc->rtsx_req->cmd->error = MMC_ERR_BADCRC; 599 } 600 if (!sc->rtsx_tuning_mode) 601 device_printf(sc->rtsx_dev, "Transfer fail - status: 0x%08x\n", status); 602 rtsx_stop_cmd(sc); 603 if (sc->rtsx_intr_trans_ko != NULL) 604 sc->rtsx_intr_trans_ko(sc); 605 } 606 607 RTSX_UNLOCK(sc); 608 } 609 610 /* 611 * Function called from the IRQ handler (from dwmmc.c). 612 */ 613 static void rtsx_handle_card_present(struct rtsx_softc * sc)614 rtsx_handle_card_present(struct rtsx_softc *sc) 615 { 616 bool was_present; 617 bool is_present; 618 619 #ifdef MMCCAM 620 was_present = sc->rtsx_cam_status; 621 #else /* !MMCCAM */ 622 was_present = sc->rtsx_mmc_dev != NULL; 623 #endif /* MMCCAM */ 624 is_present = rtsx_is_card_present(sc); 625 if (is_present) 626 device_printf(sc->rtsx_dev, "Card present\n"); 627 else 628 device_printf(sc->rtsx_dev, "Card absent\n"); 629 630 if (!was_present && is_present) { 631 /* 632 * The delay is to debounce the card insert 633 * (sometimes the card detect pin stabilizes 634 * before the other pins have made good contact). 635 */ 636 taskqueue_enqueue_timeout(taskqueue_bus, 637 &sc->rtsx_card_insert_task, -hz); 638 } else if (was_present && !is_present) { 639 taskqueue_enqueue(taskqueue_bus, &sc->rtsx_card_remove_task); 640 } 641 } 642 643 /* 644 * This function is called at startup. 645 */ 646 static void rtsx_card_task(void * arg,int pending __unused)647 rtsx_card_task(void *arg, int pending __unused) 648 { 649 struct rtsx_softc *sc = arg; 650 651 #ifndef MMCCAM 652 bus_topo_lock(); 653 #endif 654 if (rtsx_is_card_present(sc)) { 655 sc->rtsx_flags |= RTSX_F_CARD_PRESENT; 656 /* Card is present, attach if necessary. */ 657 #ifdef MMCCAM 658 if (sc->rtsx_cam_status == 0) { 659 #else /* !MMCCAM */ 660 if (sc->rtsx_mmc_dev == NULL) { 661 #endif /* MMCCAM */ 662 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 663 device_printf(sc->rtsx_dev, "Card inserted\n"); 664 665 sc->rtsx_read_count = sc->rtsx_write_count = 0; 666 #ifdef MMCCAM 667 sc->rtsx_cam_status = 1; 668 mmc_cam_sim_discover(&sc->rtsx_mmc_sim); 669 #else /* !MMCCAM */ 670 sc->rtsx_mmc_dev = device_add_child(sc->rtsx_dev, "mmc", DEVICE_UNIT_ANY); 671 if (sc->rtsx_mmc_dev == NULL) { 672 device_printf(sc->rtsx_dev, "Adding MMC bus failed\n"); 673 } else { 674 device_set_ivars(sc->rtsx_mmc_dev, sc); 675 device_probe_and_attach(sc->rtsx_mmc_dev); 676 } 677 #endif /* MMCCAM */ 678 } 679 } else { 680 sc->rtsx_flags &= ~RTSX_F_CARD_PRESENT; 681 /* Card isn't present, detach if necessary. */ 682 #ifdef MMCCAM 683 if (sc->rtsx_cam_status != 0) { 684 #else /* !MMCCAM */ 685 if (sc->rtsx_mmc_dev != NULL) { 686 #endif /* MMCCAM */ 687 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 688 device_printf(sc->rtsx_dev, "Card removed\n"); 689 690 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 691 device_printf(sc->rtsx_dev, "Read count: %" PRIu64 ", write count: %" PRIu64 "\n", 692 sc->rtsx_read_count, sc->rtsx_write_count); 693 #ifdef MMCCAM 694 sc->rtsx_cam_status = 0; 695 mmc_cam_sim_discover(&sc->rtsx_mmc_sim); 696 #else /* !MMCCAM */ 697 if (device_delete_child(sc->rtsx_dev, sc->rtsx_mmc_dev)) 698 device_printf(sc->rtsx_dev, "Detaching MMC bus failed\n"); 699 sc->rtsx_mmc_dev = NULL; 700 #endif /* MMCCAM */ 701 } 702 } 703 #ifndef MMCCAM 704 bus_topo_unlock(); 705 #endif 706 } 707 708 static bool 709 rtsx_is_card_present(struct rtsx_softc *sc) 710 { 711 uint32_t status; 712 713 status = READ4(sc, RTSX_BIPR); 714 if (sc->rtsx_inversion == 0) 715 return (status & RTSX_SD_EXIST); 716 else 717 return !(status & RTSX_SD_EXIST); 718 } 719 720 static int 721 rtsx_init(struct rtsx_softc *sc) 722 { 723 uint8_t version; 724 uint8_t val; 725 int error; 726 727 sc->rtsx_host.host_ocr = RTSX_SUPPORTED_VOLTAGE; 728 sc->rtsx_host.f_min = RTSX_SDCLK_250KHZ; 729 sc->rtsx_host.f_max = RTSX_SDCLK_208MHZ; 730 sc->rtsx_host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_HSPEED | 731 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 732 733 sc->rtsx_host.caps |= MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104; 734 if (sc->rtsx_device_id == RTSX_RTS5209) 735 sc->rtsx_host.caps |= MMC_CAP_8_BIT_DATA; 736 pci_find_cap(sc->rtsx_dev, PCIY_EXPRESS, &(sc->rtsx_pcie_cap)); 737 738 /* 739 * Check IC version. 740 */ 741 switch (sc->rtsx_device_id) { 742 case RTSX_RTS5229: 743 /* Read IC version from dummy register. */ 744 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 745 if ((version & 0x0F) == RTSX_IC_VERSION_C) 746 sc->rtsx_flags |= RTSX_F_VERSION_C; 747 break; 748 case RTSX_RTS522A: 749 /* Read IC version from dummy register. */ 750 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 751 if ((version & 0x0F) == RTSX_IC_VERSION_A) 752 sc->rtsx_flags |= RTSX_F_VERSION_A; 753 break; 754 case RTSX_RTS525A: 755 /* Read IC version from dummy register. */ 756 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 757 if ((version & 0x0F) == RTSX_IC_VERSION_A) 758 sc->rtsx_flags |= RTSX_F_VERSION_A; 759 break; 760 case RTSX_RTL8411B: 761 RTSX_READ(sc, RTSX_RTL8411B_PACKAGE, &version); 762 if (version & RTSX_RTL8411B_QFN48) 763 sc->rtsx_flags |= RTSX_F_8411B_QFN48; 764 break; 765 } 766 767 /* 768 * Fetch vendor settings. 769 */ 770 /* 771 * Normally OEMs will set vendor setting to the config space 772 * of Realtek card reader in BIOS stage. This statement reads 773 * the setting and configure the internal registers according 774 * to it, to improve card reader's compatibility condition. 775 */ 776 sc->rtsx_card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 777 switch (sc->rtsx_device_id) { 778 uint32_t reg; 779 uint32_t reg1; 780 uint8_t reg3; 781 case RTSX_RTS5209: 782 sc->rtsx_card_drive_sel = RTSX_RTS5209_CARD_DRIVE_DEFAULT; 783 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 784 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 785 if (!(reg & 0x80)) { 786 sc->rtsx_card_drive_sel = (reg >> 8) & 0x3F; 787 sc->rtsx_sd30_drive_sel_3v3 = reg & 0x07; 788 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 789 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 790 } 791 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 792 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 793 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 794 break; 795 case RTSX_RTS5227: 796 case RTSX_RTS522A: 797 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B; 798 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 799 if (!(reg & 0x1000000)) { 800 sc->rtsx_card_drive_sel &= 0x3F; 801 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 802 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 803 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03; 804 if (reg & 0x4000) 805 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET; 806 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 807 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 808 } 809 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 810 device_printf(sc->rtsx_dev, 811 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n", 812 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3, 813 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false"); 814 break; 815 case RTSX_RTS5229: 816 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 817 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 818 if (!(reg & 0x1000000)) { 819 sc->rtsx_card_drive_sel &= 0x3F; 820 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 821 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 822 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive((reg >> 5) & 0x03); 823 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 824 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 825 } 826 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 827 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 828 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 829 break; 830 case RTSX_RTS525A: 831 case RTSX_RTS5249: 832 case RTSX_RTS5260: 833 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B; 834 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 835 if ((reg & 0x1000000)) { 836 sc->rtsx_card_drive_sel &= 0x3F; 837 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 838 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 839 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03; 840 if (reg & 0x4000) 841 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET; 842 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 843 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 844 } 845 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 846 device_printf(sc->rtsx_dev, 847 "card_drive_sel = 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n", 848 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3, 849 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false"); 850 break; 851 case RTSX_RTL8402: 852 case RTSX_RTL8411: 853 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT; 854 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 855 reg1 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 856 if (reg1 & 0x1000000) { 857 sc->rtsx_card_drive_sel &= 0x3F; 858 sc->rtsx_card_drive_sel |= ((reg1 >> 25) & 0x01) << 6; 859 reg3 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG3, 1); 860 sc->rtsx_sd30_drive_sel_3v3 = (reg3 >> 5) & 0x07; 861 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 862 device_printf(sc->rtsx_dev, "pci_read_config() error - reg1: 0x%08x\n", reg1); 863 } 864 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 865 device_printf(sc->rtsx_dev, 866 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 867 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 868 break; 869 case RTSX_RTL8411B: 870 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT; 871 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 872 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 873 if (!(reg & 0x1000000)) { 874 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive(reg & 0x03); 875 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 876 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 877 } 878 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 879 device_printf(sc->rtsx_dev, 880 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 881 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 882 break; 883 } 884 885 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 886 device_printf(sc->rtsx_dev, "rtsx_init() rtsx_flags: 0x%04x\n", sc->rtsx_flags); 887 888 /* Enable interrupts. */ 889 sc->rtsx_intr_enabled = RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN; 890 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled); 891 892 /* Power on SSC clock. */ 893 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN); 894 /* Wait SSC power stable. */ 895 DELAY(200); 896 897 /* Disable ASPM */ 898 val = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, 1); 899 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, val & 0xfc, 1); 900 901 /* 902 * Optimize phy. 903 */ 904 switch (sc->rtsx_device_id) { 905 case RTSX_RTS5209: 906 /* Some magic numbers from Linux driver. */ 907 if ((error = rtsx_write_phy(sc, 0x00, 0xB966))) 908 return (error); 909 break; 910 case RTSX_RTS5227: 911 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 912 913 /* Optimize RX sensitivity. */ 914 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42))) 915 return (error); 916 break; 917 case RTSX_RTS5229: 918 /* Optimize RX sensitivity. */ 919 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42))) 920 return (error); 921 break; 922 case RTSX_RTS522A: 923 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 924 if (sc->rtsx_flags & RTSX_F_VERSION_A) { 925 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2, RTSX_PHY_RCR2_INIT_27S))) 926 return (error); 927 } 928 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1, RTSX_PHY_RCR1_INIT_27S))) 929 return (error); 930 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD0, RTSX_PHY_FLD0_INIT_27S))) 931 return (error); 932 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3, RTSX_PHY_FLD3_INIT_27S))) 933 return (error); 934 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4, RTSX_PHY_FLD4_INIT_27S))) 935 return (error); 936 break; 937 case RTSX_RTS525A: 938 if ((error = rtsx_write_phy(sc, RTSX__PHY_FLD0, 939 RTSX__PHY_FLD0_CLK_REQ_20C | RTSX__PHY_FLD0_RX_IDLE_EN | 940 RTSX__PHY_FLD0_BIT_ERR_RSTN | RTSX__PHY_FLD0_BER_COUNT | 941 RTSX__PHY_FLD0_BER_TIMER | RTSX__PHY_FLD0_CHECK_EN))) 942 return (error); 943 if ((error = rtsx_write_phy(sc, RTSX__PHY_ANA03, 944 RTSX__PHY_ANA03_TIMER_MAX | RTSX__PHY_ANA03_OOBS_DEB_EN | 945 RTSX__PHY_CMU_DEBUG_EN))) 946 return (error); 947 if (sc->rtsx_flags & RTSX_F_VERSION_A) 948 if ((error = rtsx_write_phy(sc, RTSX__PHY_REV0, 949 RTSX__PHY_REV0_FILTER_OUT | RTSX__PHY_REV0_CDR_BYPASS_PFD | 950 RTSX__PHY_REV0_CDR_RX_IDLE_BYPASS))) 951 return (error); 952 break; 953 case RTSX_RTS5249: 954 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 955 if ((error = rtsx_write_phy(sc, RTSX_PHY_REV, 956 RTSX_PHY_REV_RESV | RTSX_PHY_REV_RXIDLE_LATCHED | 957 RTSX_PHY_REV_P1_EN | RTSX_PHY_REV_RXIDLE_EN | 958 RTSX_PHY_REV_CLKREQ_TX_EN | RTSX_PHY_REV_RX_PWST | 959 RTSX_PHY_REV_CLKREQ_DT_1_0 | RTSX_PHY_REV_STOP_CLKRD | 960 RTSX_PHY_REV_STOP_CLKWR))) 961 return (error); 962 DELAY(1000); 963 if ((error = rtsx_write_phy(sc, RTSX_PHY_BPCR, 964 RTSX_PHY_BPCR_IBRXSEL | RTSX_PHY_BPCR_IBTXSEL | 965 RTSX_PHY_BPCR_IB_FILTER | RTSX_PHY_BPCR_CMIRROR_EN))) 966 return (error); 967 if ((error = rtsx_write_phy(sc, RTSX_PHY_PCR, 968 RTSX_PHY_PCR_FORCE_CODE | RTSX_PHY_PCR_OOBS_CALI_50 | 969 RTSX_PHY_PCR_OOBS_VCM_08 | RTSX_PHY_PCR_OOBS_SEN_90 | 970 RTSX_PHY_PCR_RSSI_EN | RTSX_PHY_PCR_RX10K))) 971 return (error); 972 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2, 973 RTSX_PHY_RCR2_EMPHASE_EN | RTSX_PHY_RCR2_NADJR | 974 RTSX_PHY_RCR2_CDR_SR_2 | RTSX_PHY_RCR2_FREQSEL_12 | 975 RTSX_PHY_RCR2_CDR_SC_12P | RTSX_PHY_RCR2_CALIB_LATE))) 976 return (error); 977 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4, 978 RTSX_PHY_FLD4_FLDEN_SEL | RTSX_PHY_FLD4_REQ_REF | 979 RTSX_PHY_FLD4_RXAMP_OFF | RTSX_PHY_FLD4_REQ_ADDA | 980 RTSX_PHY_FLD4_BER_COUNT | RTSX_PHY_FLD4_BER_TIMER | 981 RTSX_PHY_FLD4_BER_CHK_EN))) 982 return (error); 983 if ((error = rtsx_write_phy(sc, RTSX_PHY_RDR, 984 RTSX_PHY_RDR_RXDSEL_1_9 | RTSX_PHY_SSC_AUTO_PWD))) 985 return (error); 986 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1, 987 RTSX_PHY_RCR1_ADP_TIME_4 | RTSX_PHY_RCR1_VCO_COARSE))) 988 return (error); 989 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3, 990 RTSX_PHY_FLD3_TIMER_4 | RTSX_PHY_FLD3_TIMER_6 | 991 RTSX_PHY_FLD3_RXDELINK))) 992 return (error); 993 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE, 994 RTSX_PHY_TUNE_TUNEREF_1_0 | RTSX_PHY_TUNE_VBGSEL_1252 | 995 RTSX_PHY_TUNE_SDBUS_33 | RTSX_PHY_TUNE_TUNED18 | 996 RTSX_PHY_TUNE_TUNED12 | RTSX_PHY_TUNE_TUNEA12))) 997 return (error); 998 break; 999 } 1000 1001 /* Set mcu_cnt to 7 to ensure data can be sampled properly. */ 1002 RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07); 1003 1004 /* Disable sleep mode. */ 1005 RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE, 1006 RTSX_HOST_ENTER_S1 | RTSX_HOST_ENTER_S3); 1007 1008 /* Disable card clock. */ 1009 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 1010 1011 /* Reset delink mode. */ 1012 RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE, 1013 RTSX_FORCE_RST_CORE_EN | RTSX_NON_STICKY_RST_N_DBG); 1014 1015 /* Card driving select. */ 1016 RTSX_WRITE(sc, RTSX_CARD_DRIVE_SEL, sc->rtsx_card_drive_sel); 1017 1018 /* Enable SSC clock. */ 1019 RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M); 1020 RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12); 1021 1022 /* Disable cd_pwr_save. */ 1023 RTSX_BITOP(sc, RTSX_CHANGE_LINK_STATE, 0x16, RTSX_MAC_PHY_RST_N_DBG); 1024 1025 /* Clear Link Ready Interrupt. */ 1026 RTSX_BITOP(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT, RTSX_LINK_READY_INT); 1027 1028 /* Enlarge the estimation window of PERST# glitch 1029 * to reduce the chance of invalid card interrupt. */ 1030 RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80); 1031 1032 /* Set RC oscillator to 400K. */ 1033 RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M); 1034 1035 /* Enable interrupt write-clear (default is read-clear). */ 1036 RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR); 1037 1038 switch (sc->rtsx_device_id) { 1039 case RTSX_RTS525A: 1040 case RTSX_RTS5260: 1041 RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, 1, 1); 1042 break; 1043 } 1044 1045 /* OC power down. */ 1046 RTSX_BITOP(sc, RTSX_FPDCTL, RTSX_SD_OC_POWER_DOWN, RTSX_SD_OC_POWER_DOWN); 1047 1048 /* Enable clk_request_n to enable clock power management */ 1049 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL + 1, 1, 1); 1050 1051 /* Enter L1 when host tx idle */ 1052 pci_write_config(sc->rtsx_dev, 0x70F, 0x5B, 1); 1053 1054 /* 1055 * Specific extra init. 1056 */ 1057 switch (sc->rtsx_device_id) { 1058 uint16_t cap; 1059 case RTSX_RTS5209: 1060 /* Turn off LED. */ 1061 RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03); 1062 /* Reset ASPM state to default value. */ 1063 RTSX_CLR(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK); 1064 /* Force CLKREQ# PIN to drive 0 to request clock. */ 1065 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08); 1066 /* Configure GPIO as output. */ 1067 RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03); 1068 /* Configure driving. */ 1069 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1070 break; 1071 case RTSX_RTS5227: 1072 /* Configure GPIO as output. */ 1073 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1074 /* Reset ASPM state to default value. */ 1075 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1076 /* Switch LDO3318 source from DV33 to 3V3. */ 1077 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1078 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1079 /* Set default OLT blink period. */ 1080 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1081 /* Configure LTR. */ 1082 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2); 1083 if (cap & PCIEM_CTL2_LTR_ENABLE) 1084 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3); 1085 /* Configure OBFF. */ 1086 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE); 1087 /* Configure driving. */ 1088 if ((error = rtsx_rts5227_fill_driving(sc))) 1089 return (error); 1090 /* Configure force_clock_req. */ 1091 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1092 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8); 1093 else 1094 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88); 1095 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 1096 /*!!! Added for reboot after Windows. */ 1097 RTSX_BITOP(sc, RTSX_PM_CTRL3, RTSX_PM_WAKE_EN, RTSX_PM_WAKE_EN); 1098 break; 1099 case RTSX_RTS5229: 1100 /* Configure GPIO as output. */ 1101 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1102 /* Reset ASPM state to default value. */ 1103 /* With this reset: dd if=/dev/random of=/dev/mmcsd0 encounter a timeout. */ 1104 //!!! RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1105 /* Force CLKREQ# PIN to drive 0 to request clock. */ 1106 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08); 1107 /* Switch LDO3318 source from DV33 to card_3v3. */ 1108 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1109 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1110 /* Set default OLT blink period. */ 1111 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1112 /* Configure driving. */ 1113 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1114 break; 1115 case RTSX_RTS522A: 1116 /* Add specific init from RTS5227. */ 1117 /* Configure GPIO as output. */ 1118 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1119 /* Reset ASPM state to default value. */ 1120 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1121 /* Switch LDO3318 source from DV33 to 3V3. */ 1122 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1123 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1124 /* Set default OLT blink period. */ 1125 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1126 /* Configure LTR. */ 1127 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2); 1128 if (cap & PCIEM_CTL2_LTR_ENABLE) 1129 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3); 1130 /* Configure OBFF. */ 1131 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE); 1132 /* Configure driving. */ 1133 if ((error = rtsx_rts5227_fill_driving(sc))) 1134 return (error); 1135 /* Configure force_clock_req. */ 1136 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1137 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8); 1138 else 1139 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88); 1140 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, 0x10); 1141 1142 /* specific for RTS522A. */ 1143 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL, 1144 RTSX_FUNC_FORCE_UPME_XMT_DBG, RTSX_FUNC_FORCE_UPME_XMT_DBG); 1145 RTSX_BITOP(sc, RTSX_PCLK_CTL, 0x04, 0x04); 1146 RTSX_BITOP(sc, RTSX_PM_EVENT_DEBUG, 1147 RTSX_PME_DEBUG_0, RTSX_PME_DEBUG_0); 1148 RTSX_WRITE(sc, RTSX_PM_CLK_FORCE_CTL, 0x11); 1149 break; 1150 case RTSX_RTS525A: 1151 /* Add specific init from RTS5249. */ 1152 /* Rest L1SUB Config. */ 1153 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff); 1154 /* Configure GPIO as output. */ 1155 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1156 /* Reset ASPM state to default value. */ 1157 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1158 /* Switch LDO3318 source from DV33 to 3V3. */ 1159 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1160 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1161 /* Set default OLT blink period. */ 1162 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1163 /* Configure driving. */ 1164 if ((error = rtsx_rts5249_fill_driving(sc))) 1165 return (error); 1166 /* Configure force_clock_req. */ 1167 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1168 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1169 else 1170 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1171 1172 /* Specifc for RTS525A. */ 1173 RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL); 1174 if (sc->rtsx_flags & RTSX_F_VERSION_A) { 1175 RTSX_WRITE(sc, RTSX_L1SUB_CONFIG2, RTSX_L1SUB_AUTO_CFG); 1176 RTSX_BITOP(sc, RTSX_RREF_CFG, 1177 RTSX_RREF_VBGSEL_MASK, RTSX_RREF_VBGSEL_1V25); 1178 RTSX_BITOP(sc, RTSX_LDO_VIO_CFG, 1179 RTSX_LDO_VIO_TUNE_MASK, RTSX_LDO_VIO_1V7); 1180 RTSX_BITOP(sc, RTSX_LDO_DV12S_CFG, 1181 RTSX_LDO_D12_TUNE_MASK, RTSX_LDO_D12_TUNE_DF); 1182 RTSX_BITOP(sc, RTSX_LDO_AV12S_CFG, 1183 RTSX_LDO_AV12S_TUNE_MASK, RTSX_LDO_AV12S_TUNE_DF); 1184 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, 1185 RTSX_LDO_VCC_LMTVTH_MASK, RTSX_LDO_VCC_LMTVTH_2A); 1186 RTSX_BITOP(sc, RTSX_OOBS_CONFIG, 1187 RTSX_OOBS_AUTOK_DIS | RTSX_OOBS_VAL_MASK, 0x89); 1188 } 1189 break; 1190 case RTSX_RTS5249: 1191 /* Rest L1SUB Config. */ 1192 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff); 1193 /* Configure GPIO as output. */ 1194 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1195 /* Reset ASPM state to default value. */ 1196 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1197 /* Switch LDO3318 source from DV33 to 3V3. */ 1198 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1199 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1200 /* Set default OLT blink period. */ 1201 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1202 /* Configure driving. */ 1203 if ((error = rtsx_rts5249_fill_driving(sc))) 1204 return (error); 1205 /* Configure force_clock_req. */ 1206 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1207 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1208 else 1209 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1210 break; 1211 case RTSX_RTS5260: 1212 /* Set mcu_cnt to 7 to ensure data can be sampled properly. */ 1213 RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07); 1214 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, 0x5D); 1215 /* Force no MDIO */ 1216 RTSX_WRITE(sc, RTSX_RTS5260_AUTOLOAD_CFG4, RTSX_RTS5260_MIMO_DISABLE); 1217 /* Modify SDVCC Tune Default Parameters! */ 1218 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33); 1219 1220 RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL); 1221 1222 RTSX_BITOP(sc, RTSX_L1SUB_CONFIG1, RTSX_AUX_CLK_ACTIVE_SEL_MASK, RTSX_MAC_CKSW_DONE); 1223 /* Rest L1SUB Config */ 1224 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xFF); 1225 RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, RTSX_CLK_PM_EN, RTSX_CLK_PM_EN); 1226 RTSX_WRITE(sc, RTSX_PWD_SUSPEND_EN, 0xFF); 1227 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_PWR_GATE_EN, RTSX_PWR_GATE_EN); 1228 RTSX_BITOP(sc, RTSX_REG_VREF, RTSX_PWD_SUSPND_EN, RTSX_PWD_SUSPND_EN); 1229 RTSX_BITOP(sc, RTSX_RBCTL, RTSX_U_AUTO_DMA_EN_MASK, RTSX_U_AUTO_DMA_DISABLE); 1230 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1231 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1232 else 1233 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1234 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_DISABLE); 1235 1236 RTSX_CLR(sc, RTSX_RTS5260_DVCC_CTRL, RTSX_RTS5260_DVCC_OCP_EN | RTSX_RTS5260_DVCC_OCP_CL_EN); 1237 1238 /* CLKREQ# PIN will be forced to drive low. */ 1239 RTSX_BITOP(sc, RTSX_PETXCFG, RTSX_FORCE_CLKREQ_DELINK_MASK, RTSX_FORCE_CLKREQ_LOW); 1240 1241 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, 0x10); 1242 break; 1243 case RTSX_RTL8402: 1244 case RTSX_RTL8411: 1245 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1246 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE, 1247 RTSX_CD_ENABLE); 1248 break; 1249 case RTSX_RTL8411B: 1250 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) 1251 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); 1252 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1253 /* Enable SD interrupt. */ 1254 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE, 1255 RTSX_CD_ENABLE); 1256 /* Clear hw_pfm_en to disable hardware PFM mode. */ 1257 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL, 0x06, 0x00); 1258 break; 1259 } 1260 1261 /*!!! Added for reboot after Windows. */ 1262 rtsx_bus_power_off(sc); 1263 rtsx_set_sd_timing(sc, bus_timing_normal); 1264 rtsx_set_sd_clock(sc, 0); 1265 /*!!! Added for reboot after Windows. */ 1266 1267 return (0); 1268 } 1269 1270 static int 1271 rtsx_map_sd_drive(int index) 1272 { 1273 uint8_t sd_drive[4] = 1274 { 1275 0x01, /* Type D */ 1276 0x02, /* Type C */ 1277 0x05, /* Type A */ 1278 0x03 /* Type B */ 1279 }; 1280 return (sd_drive[index]); 1281 } 1282 1283 /* For voltage 3v3. */ 1284 static int 1285 rtsx_rts5227_fill_driving(struct rtsx_softc *sc) 1286 { 1287 u_char driving_3v3[4][3] = { 1288 {0x13, 0x13, 0x13}, 1289 {0x96, 0x96, 0x96}, 1290 {0x7F, 0x7F, 0x7F}, 1291 {0x96, 0x96, 0x96}, 1292 }; 1293 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1294 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1295 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1296 1297 return (0); 1298 } 1299 1300 /* For voltage 3v3. */ 1301 static int 1302 rtsx_rts5249_fill_driving(struct rtsx_softc *sc) 1303 { 1304 u_char driving_3v3[4][3] = { 1305 {0x11, 0x11, 0x18}, 1306 {0x55, 0x55, 0x5C}, 1307 {0xFF, 0xFF, 0xFF}, 1308 {0x96, 0x96, 0x96}, 1309 }; 1310 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1311 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1312 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1313 1314 return (0); 1315 } 1316 1317 static int 1318 rtsx_rts5260_fill_driving(struct rtsx_softc *sc) 1319 { 1320 u_char driving_3v3[4][3] = { 1321 {0x11, 0x11, 0x11}, 1322 {0x22, 0x22, 0x22}, 1323 {0x55, 0x55, 0x55}, 1324 {0x33, 0x33, 0x33}, 1325 }; 1326 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1327 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1328 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1329 1330 return (0); 1331 } 1332 1333 static int 1334 rtsx_read(struct rtsx_softc *sc, uint16_t addr, uint8_t *val) 1335 { 1336 int tries = 1024; 1337 uint32_t arg; 1338 uint32_t reg; 1339 1340 arg = RTSX_HAIMR_BUSY | (uint32_t)((addr & 0x3FFF) << 16); 1341 WRITE4(sc, RTSX_HAIMR, arg); 1342 1343 while (tries--) { 1344 reg = READ4(sc, RTSX_HAIMR); 1345 if (!(reg & RTSX_HAIMR_BUSY)) 1346 break; 1347 } 1348 *val = (reg & 0xff); 1349 1350 if (tries > 0) { 1351 return (0); 1352 } else { 1353 device_printf(sc->rtsx_dev, "rtsx_read(0x%x) timeout\n", arg); 1354 return (ETIMEDOUT); 1355 } 1356 } 1357 1358 static int 1359 rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val) 1360 { 1361 int tries = 1024; 1362 uint8_t data0, data1, data2, data3, rwctl; 1363 1364 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 1365 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 1366 RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4)); 1367 1368 while (tries--) { 1369 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 1370 if (!(rwctl & RTSX_CFG_BUSY)) 1371 break; 1372 } 1373 1374 if (tries == 0) 1375 return (ETIMEDOUT); 1376 1377 RTSX_READ(sc, RTSX_CFGDATA0, &data0); 1378 RTSX_READ(sc, RTSX_CFGDATA1, &data1); 1379 RTSX_READ(sc, RTSX_CFGDATA2, &data2); 1380 RTSX_READ(sc, RTSX_CFGDATA3, &data3); 1381 1382 *val = (data3 << 24) | (data2 << 16) | (data1 << 8) | data0; 1383 1384 return (0); 1385 } 1386 1387 static int 1388 rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val) 1389 { 1390 int tries = 1024; 1391 uint32_t arg; 1392 uint32_t reg; 1393 1394 arg = RTSX_HAIMR_BUSY | RTSX_HAIMR_WRITE | 1395 (uint32_t)(((addr & 0x3FFF) << 16) | 1396 (mask << 8) | val); 1397 WRITE4(sc, RTSX_HAIMR, arg); 1398 1399 while (tries--) { 1400 reg = READ4(sc, RTSX_HAIMR); 1401 if (!(reg & RTSX_HAIMR_BUSY)) { 1402 if (val != (reg & 0xff)) { 1403 device_printf(sc->rtsx_dev, "rtsx_write(0x%x) error reg=0x%x\n", arg, reg); 1404 return (EIO); 1405 } 1406 return (0); 1407 } 1408 } 1409 device_printf(sc->rtsx_dev, "rtsx_write(0x%x) timeout\n", arg); 1410 1411 return (ETIMEDOUT); 1412 } 1413 1414 static int 1415 rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val) 1416 { 1417 int tries = 100000; 1418 uint8_t data0, data1, rwctl; 1419 1420 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 1421 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_READ); 1422 1423 while (tries--) { 1424 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 1425 if (!(rwctl & RTSX_PHY_BUSY)) 1426 break; 1427 } 1428 if (tries == 0) 1429 return (ETIMEDOUT); 1430 1431 RTSX_READ(sc, RTSX_PHY_DATA0, &data0); 1432 RTSX_READ(sc, RTSX_PHY_DATA1, &data1); 1433 *val = data1 << 8 | data0; 1434 1435 return (0); 1436 } 1437 1438 static int 1439 rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val) 1440 { 1441 int tries = 100000; 1442 uint8_t rwctl; 1443 1444 RTSX_WRITE(sc, RTSX_PHY_DATA0, val); 1445 RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8); 1446 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 1447 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_WRITE); 1448 1449 while (tries--) { 1450 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 1451 if (!(rwctl & RTSX_PHY_BUSY)) 1452 break; 1453 } 1454 1455 return ((tries == 0) ? ETIMEDOUT : 0); 1456 } 1457 1458 /* 1459 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and 1460 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229 1461 * it is a mask of *enabled* gates. 1462 */ 1463 static int 1464 rtsx_bus_power_off(struct rtsx_softc *sc) 1465 { 1466 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1467 device_printf(sc->rtsx_dev, "rtsx_bus_power_off()\n"); 1468 1469 /* Disable SD clock. */ 1470 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN); 1471 1472 /* Disable SD output. */ 1473 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 1474 1475 /* Turn off power. */ 1476 switch (sc->rtsx_device_id) { 1477 case RTSX_RTS5209: 1478 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK, 1479 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA); 1480 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 1481 break; 1482 case RTSX_RTS5227: 1483 case RTSX_RTS5229: 1484 case RTSX_RTS522A: 1485 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK, 1486 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA); 1487 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK); 1488 break; 1489 case RTSX_RTS5260: 1490 rtsx_stop_cmd(sc); 1491 /* Switch vccq to 330 */ 1492 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1); 1493 RTSX_BITOP(sc, RTSX_LDO_DV18_CFG, RTSX_DV331812_MASK, RTSX_DV331812_33); 1494 RTSX_CLR(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8); 1495 rtsx_rts5260_fill_driving(sc); 1496 1497 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_OFF); 1498 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWEROFF); 1499 break; 1500 case RTSX_RTL8402: 1501 case RTSX_RTL8411: 1502 case RTSX_RTL8411B: 1503 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1504 RTSX_BPP_POWER_OFF); 1505 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1506 RTSX_BPP_LDO_SUSPEND); 1507 break; 1508 default: 1509 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK); 1510 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 1511 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA); 1512 break; 1513 } 1514 1515 /* Disable pull control. */ 1516 switch (sc->rtsx_device_id) { 1517 case RTSX_RTS5209: 1518 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12); 1519 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1520 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1521 break; 1522 case RTSX_RTS5227: 1523 case RTSX_RTS522A: 1524 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1525 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1526 break; 1527 case RTSX_RTS5229: 1528 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1529 if (sc->rtsx_flags & RTSX_F_VERSION_C) 1530 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3_TYPE_C); 1531 else 1532 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1533 break; 1534 case RTSX_RTS525A: 1535 case RTSX_RTS5249: 1536 case RTSX_RTS5260: 1537 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66); 1538 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1539 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1540 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x55); 1541 break; 1542 case RTSX_RTL8402: 1543 case RTSX_RTL8411: 1544 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); 1545 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1546 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0x95); 1547 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); 1548 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x05); 1549 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); 1550 break; 1551 case RTSX_RTL8411B: 1552 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) { 1553 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1554 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); 1555 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1556 } else { 1557 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); 1558 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1559 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd5); 1560 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); 1561 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55); 1562 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1563 } 1564 break; 1565 } 1566 1567 return (0); 1568 } 1569 1570 static int 1571 rtsx_bus_power_on(struct rtsx_softc *sc) 1572 { 1573 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1574 device_printf(sc->rtsx_dev, "rtsx_bus_power_on()\n"); 1575 1576 /* Select SD card. */ 1577 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL); 1578 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD); 1579 1580 /* Enable SD clock. */ 1581 RTSX_BITOP(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN, RTSX_SD_CLK_EN); 1582 1583 /* Enable pull control. */ 1584 switch (sc->rtsx_device_id) { 1585 case RTSX_RTS5209: 1586 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12); 1587 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1588 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1589 break; 1590 case RTSX_RTS5227: 1591 case RTSX_RTS522A: 1592 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1593 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1594 break; 1595 case RTSX_RTS5229: 1596 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1597 if (sc->rtsx_flags & RTSX_F_VERSION_C) 1598 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3_TYPE_C); 1599 else 1600 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1601 break; 1602 case RTSX_RTS525A: 1603 case RTSX_RTS5249: 1604 case RTSX_RTS5260: 1605 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66); 1606 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1607 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1608 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0xaa); 1609 break; 1610 case RTSX_RTL8402: 1611 case RTSX_RTL8411: 1612 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); 1613 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1614 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xa9); 1615 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); 1616 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x09); 1617 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); 1618 break; 1619 case RTSX_RTL8411B: 1620 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) { 1621 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1622 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf9); 1623 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x19); 1624 } else { 1625 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); 1626 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1627 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd9); 1628 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); 1629 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55); 1630 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1631 } 1632 break; 1633 } 1634 1635 /* 1636 * To avoid a current peak, enable card power in two phases 1637 * with a delay in between. 1638 */ 1639 switch (sc->rtsx_device_id) { 1640 case RTSX_RTS5209: 1641 /* Partial power. */ 1642 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1643 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC2); 1644 1645 DELAY(200); 1646 1647 /* Full power. */ 1648 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1649 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_ON); 1650 break; 1651 case RTSX_RTS5227: 1652 case RTSX_RTS522A: 1653 /* Partial power. */ 1654 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1655 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1656 1657 DELAY(20000); 1658 1659 /* Full power. */ 1660 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1661 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1662 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1663 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN, RTSX_SD_OUTPUT_EN); 1664 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_MS_OUTPUT_EN, RTSX_MS_OUTPUT_EN); 1665 break; 1666 case RTSX_RTS5229: 1667 /* Partial power. */ 1668 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1669 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1670 1671 DELAY(200); 1672 1673 /* Full power. */ 1674 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1675 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1676 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1677 break; 1678 case RTSX_RTS525A: 1679 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_VCC_TUNE_MASK, RTSX_LDO_VCC_3V3); 1680 case RTSX_RTS5249: 1681 /* Partial power. */ 1682 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1683 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1684 1685 DELAY(5000); 1686 1687 /* Full power. */ 1688 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1689 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1690 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1691 break; 1692 case RTSX_RTS5260: 1693 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1); 1694 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33); 1695 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_ON); 1696 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWERON); 1697 1698 DELAY(20000); 1699 1700 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK | RTSX_SD_ASYNC_FIFO_NOT_RST, 1701 RTSX_SD30_MODE | RTSX_SD_ASYNC_FIFO_NOT_RST); 1702 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CLK_LOW_FREQ); 1703 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1704 RTSX_CRC_VAR_CLK0 | RTSX_SD30_FIX_CLK | RTSX_SAMPLE_VAR_CLK1); 1705 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1706 1707 /* Initialize SD_CFG1 register */ 1708 RTSX_WRITE(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128 | RTSX_SD20_MODE); 1709 RTSX_WRITE(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_POS_EDGE); 1710 RTSX_CLR(sc, RTSX_SD_PUSH_POINT_CTL, 0xff); 1711 RTSX_BITOP(sc, RTSX_CARD_STOP, RTSX_SD_STOP | RTSX_SD_CLR_ERR, 1712 RTSX_SD_STOP | RTSX_SD_CLR_ERR); 1713 /* Reset SD_CFG3 register */ 1714 RTSX_CLR(sc, RTSX_SD_CFG3, RTSX_SD30_CLK_END_EN); 1715 RTSX_CLR(sc, RTSX_REG_SD_STOP_SDCLK_CFG, 1716 RTSX_SD30_CLK_STOP_CFG_EN | RTSX_SD30_CLK_STOP_CFG0 | RTSX_SD30_CLK_STOP_CFG1); 1717 RTSX_CLR(sc, RTSX_REG_PRE_RW_MODE, RTSX_EN_INFINITE_MODE); 1718 break; 1719 case RTSX_RTL8402: 1720 case RTSX_RTL8411: 1721 case RTSX_RTL8411B: 1722 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1723 RTSX_BPP_POWER_5_PERCENT_ON); 1724 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1725 RTSX_BPP_LDO_SUSPEND); 1726 DELAY(150); 1727 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1728 RTSX_BPP_POWER_10_PERCENT_ON); 1729 DELAY(150); 1730 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1731 RTSX_BPP_POWER_15_PERCENT_ON); 1732 DELAY(150); 1733 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1734 RTSX_BPP_POWER_ON); 1735 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1736 RTSX_BPP_LDO_ON); 1737 break; 1738 } 1739 1740 /* Enable SD card output. */ 1741 RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 1742 1743 DELAY(200); 1744 1745 return (0); 1746 } 1747 1748 /* 1749 * Set but width. 1750 */ 1751 static int 1752 rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width) 1753 { 1754 uint32_t bus_width; 1755 1756 switch (width) { 1757 case bus_width_1: 1758 bus_width = RTSX_BUS_WIDTH_1; 1759 break; 1760 case bus_width_4: 1761 bus_width = RTSX_BUS_WIDTH_4; 1762 break; 1763 case bus_width_8: 1764 bus_width = RTSX_BUS_WIDTH_8; 1765 break; 1766 default: 1767 return (MMC_ERR_INVALID); 1768 } 1769 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK, bus_width); 1770 1771 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 1772 char *busw[] = { 1773 "1 bit", 1774 "4 bits", 1775 "8 bits" 1776 }; 1777 device_printf(sc->rtsx_dev, "Setting bus width to %s\n", busw[bus_width]); 1778 } 1779 return (0); 1780 } 1781 1782 static int 1783 rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing) 1784 { 1785 if (timing == bus_timing_hs && sc->rtsx_force_timing) { 1786 timing = bus_timing_uhs_sdr50; 1787 sc->rtsx_ios_timing = timing; 1788 } 1789 1790 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1791 device_printf(sc->rtsx_dev, "rtsx_set_sd_timing(%u)\n", timing); 1792 1793 switch (timing) { 1794 case bus_timing_uhs_sdr50: 1795 case bus_timing_uhs_sdr104: 1796 sc->rtsx_double_clk = false; 1797 sc->rtsx_vpclk = true; 1798 RTSX_BITOP(sc, RTSX_SD_CFG1, 0x0c | RTSX_SD_ASYNC_FIFO_NOT_RST, 1799 RTSX_SD30_MODE | RTSX_SD_ASYNC_FIFO_NOT_RST); 1800 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1801 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1802 RTSX_CRC_VAR_CLK0 | RTSX_SD30_FIX_CLK | RTSX_SAMPLE_VAR_CLK1); 1803 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1804 break; 1805 case bus_timing_hs: 1806 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE); 1807 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1808 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1809 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 1810 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1811 1812 RTSX_BITOP(sc, RTSX_SD_PUSH_POINT_CTL, 1813 RTSX_SD20_TX_SEL_MASK, RTSX_SD20_TX_14_AHEAD); 1814 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL, 1815 RTSX_SD20_RX_SEL_MASK, RTSX_SD20_RX_14_DELAY); 1816 break; 1817 default: 1818 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE); 1819 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1820 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1821 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 1822 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1823 1824 RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE); 1825 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL, 1826 RTSX_SD20_RX_SEL_MASK, RTSX_SD20_RX_POS_EDGE); 1827 break; 1828 } 1829 1830 return (0); 1831 } 1832 1833 /* 1834 * Set or change SDCLK frequency or disable the SD clock. 1835 * Return zero on success. 1836 */ 1837 static int 1838 rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq) 1839 { 1840 uint8_t clk; 1841 uint8_t clk_divider, n, div, mcu; 1842 int error = 0; 1843 1844 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1845 device_printf(sc->rtsx_dev, "rtsx_set_sd_clock(%u)\n", freq); 1846 1847 if (freq == RTSX_SDCLK_OFF) { 1848 error = rtsx_stop_sd_clock(sc); 1849 return error; 1850 } 1851 1852 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_500K; 1853 sc->rtsx_discovery_mode = (freq <= 1000000) ? true : false; 1854 1855 if (sc->rtsx_discovery_mode) { 1856 /* We use 250k(around) here, in discovery stage. */ 1857 clk_divider = RTSX_CLK_DIVIDE_128; 1858 freq = 30000000; 1859 } else { 1860 clk_divider = RTSX_CLK_DIVIDE_0; 1861 } 1862 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, clk_divider); 1863 1864 freq /= 1000000; 1865 if (sc->rtsx_discovery_mode || !sc->rtsx_double_clk) 1866 clk = freq; 1867 else 1868 clk = freq * 2; 1869 1870 switch (sc->rtsx_device_id) { 1871 case RTSX_RTL8402: 1872 case RTSX_RTL8411: 1873 case RTSX_RTL8411B: 1874 n = clk * 4 / 5 - 2; 1875 break; 1876 default: 1877 n = clk - 2; 1878 break; 1879 } 1880 if ((clk <= 2) || (n > RTSX_MAX_DIV_N)) 1881 return (MMC_ERR_INVALID); 1882 1883 mcu = 125 / clk + 3; 1884 if (mcu > 15) 1885 mcu = 15; 1886 1887 /* Make sure that the SSC clock div_n is not less than RTSX_MIN_DIV_N. */ 1888 div = RTSX_CLK_DIV_1; 1889 while ((n < RTSX_MIN_DIV_N) && (div < RTSX_CLK_DIV_8)) { 1890 switch (sc->rtsx_device_id) { 1891 case RTSX_RTL8402: 1892 case RTSX_RTL8411: 1893 case RTSX_RTL8411B: 1894 n = (((n + 2) * 5 / 4) * 2) * 4 / 5 - 2; 1895 break; 1896 default: 1897 n = (n + 2) * 2 - 2; 1898 break; 1899 } 1900 div++; 1901 } 1902 1903 if (sc->rtsx_double_clk && sc->rtsx_ssc_depth > 1) 1904 sc->rtsx_ssc_depth -= 1; 1905 1906 if (div > RTSX_CLK_DIV_1) { 1907 if (sc->rtsx_ssc_depth > (div - 1)) 1908 sc->rtsx_ssc_depth -= (div - 1); 1909 else 1910 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_4M; 1911 } 1912 1913 /* Enable SD clock. */ 1914 error = rtsx_switch_sd_clock(sc, clk, n, div, mcu); 1915 1916 return (error); 1917 } 1918 1919 static int 1920 rtsx_stop_sd_clock(struct rtsx_softc *sc) 1921 { 1922 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 1923 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP); 1924 1925 return (0); 1926 } 1927 1928 static int 1929 rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu) 1930 { 1931 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 1932 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - discovery-mode is %s, ssc_depth: %d\n", 1933 (sc->rtsx_discovery_mode) ? "true" : "false", sc->rtsx_ssc_depth); 1934 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - clk: %d, n: %d, div: %d, mcu: %d\n", 1935 clk, n, div, mcu); 1936 } 1937 1938 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1939 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu); 1940 RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB); 1941 RTSX_BITOP(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK, sc->rtsx_ssc_depth); 1942 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n); 1943 RTSX_BITOP(sc, RTSX_SSC_CTL1, RTSX_RSTB, RTSX_RSTB); 1944 if (sc->rtsx_vpclk) { 1945 RTSX_CLR(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET); 1946 RTSX_BITOP(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1947 } 1948 1949 /* Wait SSC clock stable. */ 1950 DELAY(200); 1951 1952 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1953 1954 return (0); 1955 } 1956 1957 #ifndef MMCCAM 1958 static void 1959 rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point) 1960 { 1961 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1962 device_printf(sc->rtsx_dev, "rtsx_sd_change_tx_phase() - sample_point: %d\n", sample_point); 1963 1964 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK); 1965 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_SELECT_MASK, sample_point); 1966 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, 0); 1967 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1968 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0); 1969 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0); 1970 } 1971 1972 static void 1973 rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point) 1974 { 1975 if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING) 1976 device_printf(sc->rtsx_dev, "rtsx_sd_change_rx_phase() - sample_point: %d\n", sample_point); 1977 1978 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK); 1979 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_SELECT_MASK, sample_point); 1980 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, 0); 1981 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1982 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0); 1983 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0); 1984 } 1985 1986 static void 1987 rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map) 1988 { 1989 uint32_t raw_phase_map = 0; 1990 int i; 1991 int error; 1992 1993 for (i = 0; i < RTSX_RX_PHASE_MAX; i++) { 1994 error = rtsx_sd_tuning_rx_cmd(sc, (uint8_t)i); 1995 if (error == 0) 1996 raw_phase_map |= 1 << i; 1997 } 1998 if (phase_map != NULL) 1999 *phase_map = raw_phase_map; 2000 } 2001 2002 static int 2003 rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point) 2004 { 2005 struct mmc_request req = {}; 2006 struct mmc_command cmd = {}; 2007 int error = 0; 2008 2009 cmd.opcode = MMC_SEND_TUNING_BLOCK; 2010 cmd.arg = 0; 2011 req.cmd = &cmd; 2012 2013 RTSX_LOCK(sc); 2014 2015 sc->rtsx_req = &req; 2016 2017 rtsx_sd_change_rx_phase(sc, sample_point); 2018 2019 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 2020 RTSX_SD_RSP_80CLK_TIMEOUT_EN); 2021 2022 rtsx_init_cmd(sc, &cmd); 2023 rtsx_set_cmd_data_len(sc, 1, 0x40); 2024 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2025 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2026 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6); 2027 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2028 0xff, RTSX_TM_AUTO_TUNING | RTSX_SD_TRANSFER_START); 2029 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2030 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2031 2032 /* Set interrupt post processing */ 2033 sc->rtsx_intr_trans_ok = rtsx_sd_tuning_rx_cmd_wakeup; 2034 sc->rtsx_intr_trans_ko = rtsx_sd_tuning_rx_cmd_wakeup; 2035 2036 /* Run the command queue. */ 2037 rtsx_send_cmd(sc); 2038 2039 error = rtsx_sd_tuning_rx_cmd_wait(sc, &cmd); 2040 2041 if (error) { 2042 if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING) 2043 device_printf(sc->rtsx_dev, "rtsx_sd_tuning_rx_cmd() - error: %d\n", error); 2044 rtsx_sd_wait_data_idle(sc); 2045 rtsx_clear_error(sc); 2046 } 2047 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 0); 2048 2049 sc->rtsx_req = NULL; 2050 2051 RTSX_UNLOCK(sc); 2052 2053 return (error); 2054 } 2055 2056 static int 2057 rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd) 2058 { 2059 int status; 2060 int mask = RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT; 2061 2062 status = sc->rtsx_intr_status & mask; 2063 while (status == 0) { 2064 if (msleep(&sc->rtsx_intr_status, &sc->rtsx_mtx, 0, "rtsxintr", sc->rtsx_timeout_cmd) == EWOULDBLOCK) { 2065 cmd->error = MMC_ERR_TIMEOUT; 2066 return (MMC_ERR_TIMEOUT); 2067 } 2068 status = sc->rtsx_intr_status & mask; 2069 } 2070 return (cmd->error); 2071 } 2072 2073 static void 2074 rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc) 2075 { 2076 wakeup(&sc->rtsx_intr_status); 2077 } 2078 2079 static void 2080 rtsx_sd_wait_data_idle(struct rtsx_softc *sc) 2081 { 2082 int i; 2083 uint8_t val; 2084 2085 for (i = 0; i < 100; i++) { 2086 rtsx_read(sc, RTSX_SD_DATA_STATE, &val); 2087 if (val & RTSX_SD_DATA_IDLE) 2088 return; 2089 DELAY(100); 2090 } 2091 } 2092 2093 static uint8_t 2094 rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map) 2095 { 2096 int start = 0, len = 0; 2097 int start_final = 0, len_final = 0; 2098 uint8_t final_phase = 0xff; 2099 2100 while (start < RTSX_RX_PHASE_MAX) { 2101 len = rtsx_sd_get_rx_phase_len(phase_map, start); 2102 if (len_final < len) { 2103 start_final = start; 2104 len_final = len; 2105 } 2106 start += len ? len : 1; 2107 } 2108 2109 final_phase = (start_final + len_final / 2) % RTSX_RX_PHASE_MAX; 2110 2111 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2112 device_printf(sc->rtsx_dev, 2113 "rtsx_sd_search_final_rx_phase() - phase_map: %x, start_final: %d, len_final: %d, final_phase: %d\n", 2114 phase_map, start_final, len_final, final_phase); 2115 2116 return final_phase; 2117 } 2118 2119 static int 2120 rtsx_sd_get_rx_phase_len(uint32_t phase_map, int start_bit) 2121 { 2122 int i; 2123 2124 for (i = 0; i < RTSX_RX_PHASE_MAX; i++) { 2125 if ((phase_map & (1 << (start_bit + i) % RTSX_RX_PHASE_MAX)) == 0) 2126 return i; 2127 } 2128 return RTSX_RX_PHASE_MAX; 2129 } 2130 #endif /* !MMCCAM */ 2131 2132 #if 0 /* For led */ 2133 static int 2134 rtsx_led_enable(struct rtsx_softc *sc) 2135 { 2136 switch (sc->rtsx_device_id) { 2137 case RTSX_RTS5209: 2138 RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 2139 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 2140 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 2141 break; 2142 case RTSX_RTL8411B: 2143 RTSX_CLR(sc, RTSX_GPIO_CTL, 0x01); 2144 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 2145 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 2146 break; 2147 default: 2148 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 2149 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 2150 break; 2151 } 2152 2153 return (0); 2154 } 2155 2156 static int 2157 rtsx_led_disable(struct rtsx_softc *sc) 2158 { 2159 switch (sc->rtsx_device_id) { 2160 case RTSX_RTS5209: 2161 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 2162 RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 2163 break; 2164 case RTSX_RTL8411B: 2165 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 2166 RTSX_SET(sc, RTSX_GPIO_CTL, 0x01); 2167 break; 2168 default: 2169 RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 2170 RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 2171 break; 2172 } 2173 2174 return (0); 2175 } 2176 #endif /* For led */ 2177 2178 static uint8_t 2179 rtsx_response_type(uint16_t mmc_rsp) 2180 { 2181 int i; 2182 struct rsp_type { 2183 uint16_t mmc_rsp; 2184 uint8_t rtsx_rsp; 2185 } rsp_types[] = { 2186 { MMC_RSP_NONE, RTSX_SD_RSP_TYPE_R0 }, 2187 { MMC_RSP_R1, RTSX_SD_RSP_TYPE_R1 }, 2188 { MMC_RSP_R1B, RTSX_SD_RSP_TYPE_R1B }, 2189 { MMC_RSP_R2, RTSX_SD_RSP_TYPE_R2 }, 2190 { MMC_RSP_R3, RTSX_SD_RSP_TYPE_R3 }, 2191 { MMC_RSP_R4, RTSX_SD_RSP_TYPE_R4 }, 2192 { MMC_RSP_R5, RTSX_SD_RSP_TYPE_R5 }, 2193 { MMC_RSP_R6, RTSX_SD_RSP_TYPE_R6 }, 2194 { MMC_RSP_R7, RTSX_SD_RSP_TYPE_R7 } 2195 }; 2196 2197 for (i = 0; i < nitems(rsp_types); i++) { 2198 if (mmc_rsp == rsp_types[i].mmc_rsp) 2199 return (rsp_types[i].rtsx_rsp); 2200 } 2201 2202 return (0); 2203 } 2204 2205 /* 2206 * Init command buffer with SD command index and argument. 2207 */ 2208 static void 2209 rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd) 2210 { 2211 sc->rtsx_cmd_index = 0; 2212 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 2213 0xff, RTSX_SD_CMD_START | cmd->opcode); 2214 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, 2215 0xff, cmd->arg >> 24); 2216 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, 2217 0xff, cmd->arg >> 16); 2218 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, 2219 0xff, cmd->arg >> 8); 2220 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, 2221 0xff, cmd->arg); 2222 } 2223 2224 /* 2225 * Append a properly encoded host command to the host command buffer. 2226 */ 2227 static void 2228 rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg, 2229 uint8_t mask, uint8_t data) 2230 { 2231 KASSERT(sc->rtsx_cmd_index < RTSX_HOSTCMD_MAX, 2232 ("rtsx: Too many host commands (%d)\n", sc->rtsx_cmd_index)); 2233 2234 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem); 2235 cmd_buffer[sc->rtsx_cmd_index++] = 2236 htole32((uint32_t)(cmd & 0x3) << 30) | 2237 ((uint32_t)(reg & 0x3fff) << 16) | 2238 ((uint32_t)(mask) << 8) | 2239 ((uint32_t)data); 2240 } 2241 2242 /* 2243 * Queue commands to configure data transfer size. 2244 */ 2245 static void 2246 rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt) 2247 { 2248 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, 2249 0xff, block_cnt & 0xff); 2250 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, 2251 0xff, block_cnt >> 8); 2252 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, 2253 0xff, byte_cnt & 0xff); 2254 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, 2255 0xff, byte_cnt >> 8); 2256 } 2257 2258 /* 2259 * Run the command queue. 2260 */ 2261 static void 2262 rtsx_send_cmd(struct rtsx_softc *sc) 2263 { 2264 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2265 device_printf(sc->rtsx_dev, "rtsx_send_cmd()\n"); 2266 2267 sc->rtsx_intr_status = 0; 2268 2269 /* Sync command DMA buffer. */ 2270 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREREAD); 2271 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREWRITE); 2272 2273 /* Tell the chip where the command buffer is and run the commands. */ 2274 WRITE4(sc, RTSX_HCBAR, (uint32_t)sc->rtsx_cmd_buffer); 2275 WRITE4(sc, RTSX_HCBCTLR, 2276 ((sc->rtsx_cmd_index * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP); 2277 } 2278 2279 /* 2280 * Stop previous command. 2281 */ 2282 static void 2283 rtsx_stop_cmd(struct rtsx_softc *sc) 2284 { 2285 /* Stop command transfer. */ 2286 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD); 2287 2288 /* Stop DMA transfer. */ 2289 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA); 2290 2291 switch (sc->rtsx_device_id) { 2292 case RTSX_RTS5260: 2293 rtsx_write(sc, RTSX_RTS5260_DMA_RST_CTL_0, 2294 RTSX_RTS5260_DMA_RST | RTSX_RTS5260_ADMA3_RST, 2295 RTSX_RTS5260_DMA_RST | RTSX_RTS5260_ADMA3_RST); 2296 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 2297 break; 2298 default: 2299 rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST); 2300 2301 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 2302 break; 2303 } 2304 } 2305 2306 /* 2307 * Clear error. 2308 */ 2309 static void 2310 rtsx_clear_error(struct rtsx_softc *sc) 2311 { 2312 /* Clear error. */ 2313 rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP | RTSX_SD_CLR_ERR, 2314 RTSX_SD_STOP | RTSX_SD_CLR_ERR); 2315 } 2316 2317 /* 2318 * Signal end of request to mmc/mmcsd. 2319 */ 2320 static void 2321 rtsx_req_done(struct rtsx_softc *sc) 2322 { 2323 #ifdef MMCCAM 2324 union ccb *ccb; 2325 #endif /* MMCCAM */ 2326 struct mmc_request *req; 2327 2328 req = sc->rtsx_req; 2329 if (req->cmd->error == MMC_ERR_NONE) { 2330 if (req->cmd->opcode == MMC_READ_SINGLE_BLOCK || 2331 req->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 2332 sc->rtsx_read_count++; 2333 else if (req->cmd->opcode == MMC_WRITE_BLOCK || 2334 req->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) 2335 sc->rtsx_write_count++; 2336 } else { 2337 rtsx_clear_error(sc); 2338 } 2339 callout_stop(&sc->rtsx_timeout_callout); 2340 sc->rtsx_req = NULL; 2341 #ifdef MMCCAM 2342 ccb = sc->rtsx_ccb; 2343 sc->rtsx_ccb = NULL; 2344 ccb->ccb_h.status = (req->cmd->error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 2345 xpt_done(ccb); 2346 #else /* !MMCCAM */ 2347 req->done(req); 2348 #endif /* MMCCAM */ 2349 } 2350 2351 /* 2352 * Send request. 2353 */ 2354 static int 2355 rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd) 2356 { 2357 uint8_t rsp_type; 2358 uint16_t reg; 2359 2360 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2361 device_printf(sc->rtsx_dev, "rtsx_send_req() - CMD%d\n", cmd->opcode); 2362 2363 /* Convert response type. */ 2364 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK); 2365 if (rsp_type == 0) { 2366 device_printf(sc->rtsx_dev, "Unknown rsp_type: 0x%lx\n", (cmd->flags & MMC_RSP_MASK)); 2367 cmd->error = MMC_ERR_INVALID; 2368 return (MMC_ERR_INVALID); 2369 } 2370 2371 rtsx_init_cmd(sc, cmd); 2372 2373 /* Queue command to set response type. */ 2374 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, rsp_type); 2375 2376 /* Use the ping-pong buffer (cmd buffer) for commands which do not transfer data. */ 2377 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2378 0x01, RTSX_PINGPONG_BUFFER); 2379 2380 /* Queue commands to perform SD transfer. */ 2381 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2382 0xff, RTSX_TM_CMD_RSP | RTSX_SD_TRANSFER_START); 2383 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2384 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE, 2385 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE); 2386 2387 /* If needed queue commands to read back card status response. */ 2388 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 2389 /* Read data from ping-pong buffer. */ 2390 for (reg = RTSX_PPBUF_BASE2; reg < RTSX_PPBUF_BASE2 + 16; reg++) 2391 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0); 2392 } else if (rsp_type != RTSX_SD_RSP_TYPE_R0) { 2393 /* Read data from SD_CMDx registers. */ 2394 for (reg = RTSX_SD_CMD0; reg <= RTSX_SD_CMD4; reg++) 2395 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0); 2396 } 2397 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, RTSX_SD_STAT1, 0, 0); 2398 2399 /* Set transfer OK function. */ 2400 if (sc->rtsx_intr_trans_ok == NULL) 2401 sc->rtsx_intr_trans_ok = rtsx_ret_resp; 2402 2403 /* Run the command queue. */ 2404 rtsx_send_cmd(sc); 2405 2406 return (0); 2407 } 2408 2409 /* 2410 * Return response of previous command (case cmd->data == NULL) and complete resquest. 2411 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2412 */ 2413 static void 2414 rtsx_ret_resp(struct rtsx_softc *sc) 2415 { 2416 struct mmc_command *cmd; 2417 2418 cmd = sc->rtsx_req->cmd; 2419 rtsx_set_resp(sc, cmd); 2420 rtsx_req_done(sc); 2421 } 2422 2423 /* 2424 * Set response of previous command. 2425 */ 2426 static void 2427 rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd) 2428 { 2429 uint8_t rsp_type; 2430 2431 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK); 2432 2433 /* Sync command DMA buffer. */ 2434 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2435 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2436 2437 /* Copy card response into mmc response buffer. */ 2438 if (ISSET(cmd->flags, MMC_RSP_PRESENT)) { 2439 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem); 2440 2441 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) { 2442 device_printf(sc->rtsx_dev, "cmd_buffer: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 2443 cmd_buffer[0], cmd_buffer[1], cmd_buffer[2], cmd_buffer[3], cmd_buffer[4]); 2444 } 2445 2446 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 2447 /* First byte is CHECK_REG_CMD return value, skip it. */ 2448 unsigned char *ptr = (unsigned char *)cmd_buffer + 1; 2449 int i; 2450 2451 /* 2452 * The controller offloads the last byte {CRC-7, end bit 1} 2453 * of response type R2. Assign dummy CRC, 0, and end bit to this 2454 * byte (ptr[16], goes into the LSB of resp[3] later). 2455 */ 2456 ptr[16] = 0x01; 2457 /* The second byte is the status of response, skip it. */ 2458 for (i = 0; i < 4; i++) 2459 cmd->resp[i] = be32dec(ptr + 1 + i * 4); 2460 } else { 2461 /* 2462 * First byte is CHECK_REG_CMD return value, second 2463 * one is the command op code -- we skip those. 2464 */ 2465 cmd->resp[0] = 2466 ((be32toh(cmd_buffer[0]) & 0x0000ffff) << 16) | 2467 ((be32toh(cmd_buffer[1]) & 0xffff0000) >> 16); 2468 } 2469 2470 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2471 device_printf(sc->rtsx_dev, "cmd->resp: 0x%08x 0x%08x 0x%08x 0x%08x\n", 2472 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); 2473 } 2474 } 2475 2476 /* 2477 * Use the ping-pong buffer (cmd buffer) for transfer <= 512 bytes. 2478 */ 2479 static int 2480 rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd) 2481 { 2482 int read; 2483 2484 if (cmd->data == NULL || cmd->data->len == 0) { 2485 cmd->error = MMC_ERR_INVALID; 2486 return (MMC_ERR_INVALID); 2487 } 2488 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ? 2489 RTSX_MAX_DATA_BLKLEN : cmd->data->len; 2490 2491 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2492 2493 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2494 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - %s xfer: %ld bytes with block size %ld\n", 2495 read ? "Read" : "Write", 2496 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len); 2497 2498 if (cmd->data->len > 512) { 2499 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - length too large: %ld > 512\n", 2500 (unsigned long)cmd->data->len); 2501 cmd->error = MMC_ERR_INVALID; 2502 return (MMC_ERR_INVALID); 2503 } 2504 2505 if (read) { 2506 if (sc->rtsx_discovery_mode) 2507 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_0); 2508 2509 rtsx_init_cmd(sc, cmd); 2510 2511 /* Queue commands to configure data transfer size. */ 2512 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2513 2514 /* From Linux: rtsx_pci_sdmmc.c sd_read_data(). */ 2515 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2516 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2517 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6); 2518 2519 /* Use the ping-pong buffer (cmd buffer). */ 2520 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2521 0x01, RTSX_PINGPONG_BUFFER); 2522 2523 /* Queue commands to perform SD transfer. */ 2524 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2525 0xff, RTSX_TM_NORMAL_READ | RTSX_SD_TRANSFER_START); 2526 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2527 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2528 2529 /* Set transfer OK function. */ 2530 sc->rtsx_intr_trans_ok = rtsx_ask_ppbuf_part1; 2531 2532 /* Run the command queue. */ 2533 rtsx_send_cmd(sc); 2534 } else { 2535 /* Set transfer OK function. */ 2536 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part1; 2537 2538 /* Run the command queue. */ 2539 rtsx_send_req(sc, cmd); 2540 } 2541 2542 return (0); 2543 } 2544 2545 /* 2546 * Use the ping-pong buffer (cmd buffer) for the transfer - first part <= 256 bytes. 2547 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2548 */ 2549 static void 2550 rtsx_ask_ppbuf_part1(struct rtsx_softc *sc) 2551 { 2552 struct mmc_command *cmd; 2553 uint16_t reg = RTSX_PPBUF_BASE2; 2554 int len; 2555 int i; 2556 2557 cmd = sc->rtsx_req->cmd; 2558 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2559 2560 sc->rtsx_cmd_index = 0; 2561 for (i = 0; i < len; i++) { 2562 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0); 2563 } 2564 2565 /* Set transfer OK function. */ 2566 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part1; 2567 2568 /* Run the command queue. */ 2569 rtsx_send_cmd(sc); 2570 } 2571 2572 /* 2573 * Get the data from the ping-pong buffer (cmd buffer) - first part <= 256 bytes. 2574 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2575 */ 2576 static void 2577 rtsx_get_ppbuf_part1(struct rtsx_softc *sc) 2578 { 2579 struct mmc_command *cmd; 2580 uint8_t *ptr; 2581 int len; 2582 2583 cmd = sc->rtsx_req->cmd; 2584 ptr = cmd->data->data; 2585 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2586 2587 /* Sync command DMA buffer. */ 2588 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2589 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2590 2591 memcpy(ptr, sc->rtsx_cmd_dmamem, len); 2592 2593 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? cmd->data->len - RTSX_HOSTCMD_MAX : 0; 2594 2595 /* Use the ping-pong buffer (cmd buffer) for the transfer - second part > 256 bytes. */ 2596 if (len > 0) { 2597 uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX; 2598 int i; 2599 2600 sc->rtsx_cmd_index = 0; 2601 for (i = 0; i < len; i++) { 2602 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0); 2603 } 2604 2605 /* Set transfer OK function. */ 2606 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part2; 2607 2608 /* Run the command queue. */ 2609 rtsx_send_cmd(sc); 2610 } else { 2611 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD && cmd->opcode == ACMD_SEND_SCR) { 2612 uint8_t *ptr = cmd->data->data; 2613 device_printf(sc->rtsx_dev, "SCR: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", 2614 ptr[0], ptr[1], ptr[2], ptr[3], 2615 ptr[4], ptr[5], ptr[6], ptr[7]); 2616 } 2617 2618 if (sc->rtsx_discovery_mode) 2619 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128); 2620 2621 rtsx_req_done(sc); 2622 } 2623 } 2624 2625 /* 2626 * Get the data from the ping-pong buffer (cmd buffer) - second part > 256 bytes. 2627 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2628 */ 2629 static void 2630 rtsx_get_ppbuf_part2(struct rtsx_softc *sc) 2631 { 2632 struct mmc_command *cmd; 2633 uint8_t *ptr; 2634 int len; 2635 2636 cmd = sc->rtsx_req->cmd; 2637 ptr = cmd->data->data; 2638 ptr += RTSX_HOSTCMD_MAX; 2639 len = cmd->data->len - RTSX_HOSTCMD_MAX; 2640 2641 /* Sync command DMA buffer. */ 2642 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2643 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2644 2645 memcpy(ptr, sc->rtsx_cmd_dmamem, len); 2646 2647 if (sc->rtsx_discovery_mode) 2648 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128); 2649 2650 rtsx_req_done(sc); 2651 } 2652 2653 /* 2654 * Use the ping-pong buffer (cmd buffer) for transfer - first part <= 256 bytes. 2655 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2656 */ 2657 static void 2658 rtsx_put_ppbuf_part1(struct rtsx_softc *sc) 2659 { 2660 struct mmc_command *cmd; 2661 uint16_t reg = RTSX_PPBUF_BASE2; 2662 uint8_t *ptr; 2663 int len; 2664 int i; 2665 2666 cmd = sc->rtsx_req->cmd; 2667 ptr = cmd->data->data; 2668 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2669 2670 rtsx_set_resp(sc, cmd); 2671 2672 sc->rtsx_cmd_index = 0; 2673 for (i = 0; i < len; i++) { 2674 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr); 2675 ptr++; 2676 } 2677 2678 /* Set transfer OK function. */ 2679 if (cmd->data->len > RTSX_HOSTCMD_MAX) 2680 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part2; 2681 else 2682 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf; 2683 2684 /* Run the command queue. */ 2685 rtsx_send_cmd(sc); 2686 } 2687 2688 /* 2689 * Use the ping-pong buffer (cmd buffer) for transfer - second part > 256 bytes. 2690 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2691 */ 2692 static void 2693 rtsx_put_ppbuf_part2(struct rtsx_softc *sc) 2694 { 2695 struct mmc_command *cmd; 2696 uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX; 2697 uint8_t *ptr; 2698 int len; 2699 int i; 2700 2701 cmd = sc->rtsx_req->cmd; 2702 ptr = cmd->data->data; 2703 ptr += RTSX_HOSTCMD_MAX; 2704 len = cmd->data->len - RTSX_HOSTCMD_MAX; 2705 2706 sc->rtsx_cmd_index = 0; 2707 for (i = 0; i < len; i++) { 2708 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr); 2709 ptr++; 2710 } 2711 2712 /* Set transfer OK function. */ 2713 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf; 2714 2715 /* Run the command queue. */ 2716 rtsx_send_cmd(sc); 2717 } 2718 2719 /* 2720 * Write the data previously given via the ping-pong buffer on the card. 2721 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2722 */ 2723 static void 2724 rtsx_write_ppbuf(struct rtsx_softc *sc) 2725 { 2726 struct mmc_command *cmd; 2727 2728 cmd = sc->rtsx_req->cmd; 2729 2730 sc->rtsx_cmd_index = 0; 2731 2732 /* Queue commands to configure data transfer size. */ 2733 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2734 2735 /* From Linux: rtsx_pci_sdmmc.c sd_write_data(). */ 2736 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2737 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2738 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_0); 2739 2740 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 0xff, 2741 RTSX_TM_AUTO_WRITE3 | RTSX_SD_TRANSFER_START); 2742 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2743 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2744 2745 /* Set transfer OK function. */ 2746 sc->rtsx_intr_trans_ok = rtsx_req_done; 2747 2748 /* Run the command queue. */ 2749 rtsx_send_cmd(sc); 2750 } 2751 2752 /* 2753 * Use the data buffer for transfer > 512 bytes. 2754 */ 2755 static int 2756 rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd) 2757 { 2758 int read = ISSET(cmd->data->flags, MMC_DATA_READ); 2759 2760 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ? 2761 RTSX_MAX_DATA_BLKLEN : cmd->data->len; 2762 2763 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2764 device_printf(sc->rtsx_dev, "rtsx_xfer() - %s xfer: %ld bytes with block size %ld\n", 2765 read ? "Read" : "Write", 2766 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len); 2767 2768 if (cmd->data->len > RTSX_DMA_DATA_BUFSIZE) { 2769 device_printf(sc->rtsx_dev, "rtsx_xfer() length too large: %ld > %ld\n", 2770 (unsigned long)cmd->data->len, RTSX_DMA_DATA_BUFSIZE); 2771 cmd->error = MMC_ERR_INVALID; 2772 return (MMC_ERR_INVALID); 2773 } 2774 2775 if (!read) { 2776 /* Set transfer OK function. */ 2777 sc->rtsx_intr_trans_ok = rtsx_xfer_begin; 2778 2779 /* Run the command queue. */ 2780 rtsx_send_req(sc, cmd); 2781 } else { 2782 rtsx_xfer_start(sc); 2783 } 2784 2785 return (0); 2786 } 2787 2788 /* 2789 * Get request response and start dma data transfer (write command). 2790 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2791 */ 2792 static void 2793 rtsx_xfer_begin(struct rtsx_softc *sc) 2794 { 2795 struct mmc_command *cmd; 2796 2797 cmd = sc->rtsx_req->cmd; 2798 2799 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2800 device_printf(sc->rtsx_dev, "rtsx_xfer_begin() - CMD%d\n", cmd->opcode); 2801 2802 rtsx_set_resp(sc, cmd); 2803 rtsx_xfer_start(sc); 2804 } 2805 2806 /* 2807 * Start dma data transfer. 2808 */ 2809 static void 2810 rtsx_xfer_start(struct rtsx_softc *sc) 2811 { 2812 struct mmc_command *cmd; 2813 int read; 2814 uint8_t cfg2; 2815 int dma_dir; 2816 int tmode; 2817 2818 cmd = sc->rtsx_req->cmd; 2819 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2820 2821 /* Configure DMA transfer mode parameters. */ 2822 if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 2823 cfg2 = RTSX_SD_CHECK_CRC16 | RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_6; 2824 else 2825 cfg2 = RTSX_SD_CHECK_CRC16 | RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0; 2826 if (read) { 2827 dma_dir = RTSX_DMA_DIR_FROM_CARD; 2828 /* 2829 * Use transfer mode AUTO_READ1, which assume we not 2830 * already send the read command and don't need to send 2831 * CMD 12 manually after read. 2832 */ 2833 tmode = RTSX_TM_AUTO_READ1; 2834 cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7; 2835 2836 rtsx_init_cmd(sc, cmd); 2837 } else { 2838 dma_dir = RTSX_DMA_DIR_TO_CARD; 2839 /* 2840 * Use transfer mode AUTO_WRITE3, wich assumes we've already 2841 * sent the write command and gotten the response, and will 2842 * send CMD 12 manually after writing. 2843 */ 2844 tmode = RTSX_TM_AUTO_WRITE3; 2845 cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7; 2846 2847 sc->rtsx_cmd_index = 0; 2848 } 2849 2850 /* Queue commands to configure data transfer size. */ 2851 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2852 2853 /* Configure DMA controller. */ 2854 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0, 2855 RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT); 2856 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC3, 2857 0xff, cmd->data->len >> 24); 2858 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC2, 2859 0xff, cmd->data->len >> 16); 2860 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC1, 2861 0xff, cmd->data->len >> 8); 2862 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC0, 2863 0xff, cmd->data->len); 2864 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMACTL, 2865 RTSX_DMA_EN | RTSX_DMA_DIR | RTSX_DMA_PACK_SIZE_MASK, 2866 RTSX_DMA_EN | dma_dir | RTSX_DMA_512); 2867 2868 /* Use the DMA ring buffer for commands which transfer data. */ 2869 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2870 0x01, RTSX_RING_BUFFER); 2871 2872 /* Queue command to set response type. */ 2873 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, cfg2); 2874 2875 /* Queue commands to perform SD transfer. */ 2876 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2877 0xff, tmode | RTSX_SD_TRANSFER_START); 2878 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2879 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2880 2881 /* Run the command queue. */ 2882 rtsx_send_cmd(sc); 2883 2884 if (!read) 2885 memcpy(sc->rtsx_data_dmamem, cmd->data->data, cmd->data->len); 2886 2887 /* Sync data DMA buffer. */ 2888 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREREAD); 2889 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREWRITE); 2890 2891 /* Set transfer OK function. */ 2892 sc->rtsx_intr_trans_ok = rtsx_xfer_finish; 2893 2894 /* Tell the chip where the data buffer is and run the transfer. */ 2895 WRITE4(sc, RTSX_HDBAR, sc->rtsx_data_buffer); 2896 WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) | 2897 (cmd->data->len & 0x00ffffff)); 2898 } 2899 2900 /* 2901 * Finish dma data transfer. 2902 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2903 */ 2904 static void 2905 rtsx_xfer_finish(struct rtsx_softc *sc) 2906 { 2907 struct mmc_command *cmd; 2908 int read; 2909 2910 cmd = sc->rtsx_req->cmd; 2911 2912 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2913 device_printf(sc->rtsx_dev, "rtsx_xfer_finish() - CMD%d\n", cmd->opcode); 2914 2915 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2916 2917 /* Sync data DMA buffer. */ 2918 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTREAD); 2919 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTWRITE); 2920 2921 if (read) { 2922 memcpy(cmd->data->data, sc->rtsx_data_dmamem, cmd->data->len); 2923 rtsx_req_done(sc); 2924 } else { 2925 /* Send CMD12 after AUTO_WRITE3 (see mmcsd_rw() in mmcsd.c) */ 2926 /* and complete request. */ 2927 sc->rtsx_intr_trans_ok = NULL; 2928 rtsx_send_req(sc, sc->rtsx_req->stop); 2929 } 2930 } 2931 2932 /* 2933 * Manage request timeout. 2934 */ 2935 static void 2936 rtsx_timeout(void *arg) 2937 { 2938 struct rtsx_softc *sc; 2939 2940 sc = (struct rtsx_softc *)arg; 2941 if (sc->rtsx_req != NULL) { 2942 device_printf(sc->rtsx_dev, "Controller timeout for CMD%u\n", 2943 sc->rtsx_req->cmd->opcode); 2944 sc->rtsx_req->cmd->error = MMC_ERR_TIMEOUT; 2945 rtsx_stop_cmd(sc); 2946 rtsx_req_done(sc); 2947 } else { 2948 device_printf(sc->rtsx_dev, "Controller timeout!\n"); 2949 } 2950 } 2951 2952 #ifdef MMCCAM 2953 static int 2954 rtsx_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 2955 { 2956 struct rtsx_softc *sc; 2957 2958 sc = device_get_softc(dev); 2959 2960 cts->host_ocr = sc->rtsx_host.host_ocr; 2961 cts->host_f_min = sc->rtsx_host.f_min; 2962 cts->host_f_max = sc->rtsx_host.f_max; 2963 cts->host_caps = sc->rtsx_host.caps; 2964 cts->host_max_data = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE; 2965 memcpy(&cts->ios, &sc->rtsx_host.ios, sizeof(struct mmc_ios)); 2966 2967 return (0); 2968 } 2969 2970 /* 2971 * Apply settings and return status accordingly. 2972 */ 2973 static int 2974 rtsx_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 2975 { 2976 struct rtsx_softc *sc; 2977 struct mmc_ios *ios; 2978 struct mmc_ios *new_ios; 2979 2980 sc = device_get_softc(dev); 2981 2982 ios = &sc->rtsx_host.ios; 2983 new_ios = &cts->ios; 2984 2985 /* Update only requested fields */ 2986 if (cts->ios_valid & MMC_CLK) { 2987 ios->clock = new_ios->clock; 2988 sc->rtsx_ios_clock = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 2989 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2990 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - clock: %u\n", ios->clock); 2991 } 2992 if (cts->ios_valid & MMC_VDD) { 2993 ios->vdd = new_ios->vdd; 2994 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2995 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vdd: %d\n", ios->vdd); 2996 } 2997 if (cts->ios_valid & MMC_CS) { 2998 ios->chip_select = new_ios->chip_select; 2999 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3000 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - chip_select: %d\n", ios->chip_select); 3001 } 3002 if (cts->ios_valid & MMC_BW) { 3003 ios->bus_width = new_ios->bus_width; 3004 sc->rtsx_ios_bus_width = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3005 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3006 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus width: %d\n", ios->bus_width); 3007 } 3008 if (cts->ios_valid & MMC_PM) { 3009 ios->power_mode = new_ios->power_mode; 3010 sc->rtsx_ios_power_mode = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3011 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3012 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - power mode: %d\n", ios->power_mode); 3013 } 3014 if (cts->ios_valid & MMC_BT) { 3015 ios->timing = new_ios->timing; 3016 sc->rtsx_ios_timing = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3017 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3018 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - timing: %d\n", ios->timing); 3019 } 3020 if (cts->ios_valid & MMC_BM) { 3021 ios->bus_mode = new_ios->bus_mode; 3022 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3023 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus mode: %d\n", ios->bus_mode); 3024 } 3025 #if __FreeBSD_version >= 1300000 3026 if (cts->ios_valid & MMC_VCCQ) { 3027 ios->vccq = new_ios->vccq; 3028 sc->rtsx_ios_vccq = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3029 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3030 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vccq: %d\n", ios->vccq); 3031 } 3032 #endif /* __FreeBSD_version >= 1300000 */ 3033 if (rtsx_mmcbr_update_ios(sc->rtsx_dev, NULL) == 0) 3034 return (CAM_REQ_CMP); 3035 else 3036 return (CAM_REQ_CMP_ERR); 3037 } 3038 3039 /* 3040 * Build a request and run it. 3041 */ 3042 static int 3043 rtsx_cam_request(device_t dev, union ccb *ccb) 3044 { 3045 struct rtsx_softc *sc; 3046 3047 sc = device_get_softc(dev); 3048 3049 RTSX_LOCK(sc); 3050 if (sc->rtsx_ccb != NULL) { 3051 RTSX_UNLOCK(sc); 3052 return (CAM_BUSY); 3053 } 3054 sc->rtsx_ccb = ccb; 3055 sc->rtsx_cam_req.cmd = &ccb->mmcio.cmd; 3056 sc->rtsx_cam_req.stop = &ccb->mmcio.stop; 3057 RTSX_UNLOCK(sc); 3058 3059 rtsx_mmcbr_request(sc->rtsx_dev, NULL, &sc->rtsx_cam_req); 3060 return (0); 3061 } 3062 #endif /* MMCCAM */ 3063 3064 static int 3065 rtsx_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 3066 { 3067 struct rtsx_softc *sc; 3068 3069 sc = device_get_softc(bus); 3070 switch (which) { 3071 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */ 3072 *result = sc->rtsx_host.ios.bus_mode; 3073 break; 3074 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */ 3075 *result = sc->rtsx_host.ios.bus_width; 3076 break; 3077 case MMCBR_IVAR_CHIP_SELECT: /* ivar 2 - O = dontcare, 1 = cs_high, 2 = cs_low */ 3078 *result = sc->rtsx_host.ios.chip_select; 3079 break; 3080 case MMCBR_IVAR_CLOCK: /* ivar 3 - clock in Hz */ 3081 *result = sc->rtsx_host.ios.clock; 3082 break; 3083 case MMCBR_IVAR_F_MIN: /* ivar 4 */ 3084 *result = sc->rtsx_host.f_min; 3085 break; 3086 case MMCBR_IVAR_F_MAX: /* ivar 5 */ 3087 *result = sc->rtsx_host.f_max; 3088 break; 3089 case MMCBR_IVAR_HOST_OCR: /* ivar 6 - host operation conditions register */ 3090 *result = sc->rtsx_host.host_ocr; 3091 break; 3092 case MMCBR_IVAR_MODE: /* ivar 7 - 0 = mode_mmc, 1 = mode_sd */ 3093 *result = sc->rtsx_host.mode; 3094 break; 3095 case MMCBR_IVAR_OCR: /* ivar 8 - operation conditions register */ 3096 *result = sc->rtsx_host.ocr; 3097 break; 3098 case MMCBR_IVAR_POWER_MODE: /* ivar 9 - 0 = off, 1 = up, 2 = on */ 3099 *result = sc->rtsx_host.ios.power_mode; 3100 break; 3101 case MMCBR_IVAR_VDD: /* ivar 11 - voltage power pin */ 3102 *result = sc->rtsx_host.ios.vdd; 3103 break; 3104 case MMCBR_IVAR_VCCQ: /* ivar 12 - signaling: 0 = 1.20V, 1 = 1.80V, 2 = 3.30V */ 3105 *result = sc->rtsx_host.ios.vccq; 3106 break; 3107 case MMCBR_IVAR_CAPS: /* ivar 13 */ 3108 *result = sc->rtsx_host.caps; 3109 break; 3110 case MMCBR_IVAR_TIMING: /* ivar 14 - 0 = normal, 1 = timing_hs, ... */ 3111 *result = sc->rtsx_host.ios.timing; 3112 break; 3113 case MMCBR_IVAR_MAX_DATA: /* ivar 15 */ 3114 *result = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE; 3115 break; 3116 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */ 3117 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */ 3118 default: 3119 return (EINVAL); 3120 } 3121 3122 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3123 device_printf(bus, "Read ivar #%d, value %#x / #%d\n", 3124 which, *(int *)result, *(int *)result); 3125 3126 return (0); 3127 } 3128 3129 static int 3130 rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 3131 { 3132 struct rtsx_softc *sc; 3133 3134 sc = device_get_softc(bus); 3135 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3136 device_printf(bus, "Write ivar #%d, value %#x / #%d\n", 3137 which, (int)value, (int)value); 3138 3139 switch (which) { 3140 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */ 3141 sc->rtsx_host.ios.bus_mode = value; 3142 break; 3143 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */ 3144 sc->rtsx_host.ios.bus_width = value; 3145 sc->rtsx_ios_bus_width = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3146 break; 3147 case MMCBR_IVAR_CHIP_SELECT: /* ivar 2 - O = dontcare, 1 = cs_high, 2 = cs_low */ 3148 sc->rtsx_host.ios.chip_select = value; 3149 break; 3150 case MMCBR_IVAR_CLOCK: /* ivar 3 - clock in Hz */ 3151 sc->rtsx_host.ios.clock = value; 3152 sc->rtsx_ios_clock = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3153 break; 3154 case MMCBR_IVAR_MODE: /* ivar 7 - 0 = mode_mmc, 1 = mode_sd */ 3155 sc->rtsx_host.mode = value; 3156 break; 3157 case MMCBR_IVAR_OCR: /* ivar 8 - operation conditions register */ 3158 sc->rtsx_host.ocr = value; 3159 break; 3160 case MMCBR_IVAR_POWER_MODE: /* ivar 9 - 0 = off, 1 = up, 2 = on */ 3161 sc->rtsx_host.ios.power_mode = value; 3162 sc->rtsx_ios_power_mode = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3163 break; 3164 case MMCBR_IVAR_VDD: /* ivar 11 - voltage power pin */ 3165 sc->rtsx_host.ios.vdd = value; 3166 break; 3167 case MMCBR_IVAR_VCCQ: /* ivar 12 - signaling: 0 = 1.20V, 1 = 1.80V, 2 = 3.30V */ 3168 sc->rtsx_host.ios.vccq = value; 3169 sc->rtsx_ios_vccq = value; /* rtsx_mmcbr_switch_vccq() will be called by mmc.c (MMCCAM undef). */ 3170 break; 3171 case MMCBR_IVAR_TIMING: /* ivar 14 - 0 = normal, 1 = timing_hs, ... */ 3172 sc->rtsx_host.ios.timing = value; 3173 sc->rtsx_ios_timing = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3174 break; 3175 /* These are read-only. */ 3176 case MMCBR_IVAR_F_MIN: /* ivar 4 */ 3177 case MMCBR_IVAR_F_MAX: /* ivar 5 */ 3178 case MMCBR_IVAR_HOST_OCR: /* ivar 6 - host operation conditions register */ 3179 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */ 3180 case MMCBR_IVAR_CAPS: /* ivar 13 */ 3181 case MMCBR_IVAR_MAX_DATA: /* ivar 15 */ 3182 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */ 3183 default: 3184 return (EINVAL); 3185 } 3186 3187 return (0); 3188 } 3189 3190 static int 3191 rtsx_mmcbr_update_ios(device_t bus, device_t child__unused) 3192 { 3193 struct rtsx_softc *sc; 3194 struct mmc_ios *ios; 3195 int error; 3196 3197 sc = device_get_softc(bus); 3198 ios = &sc->rtsx_host.ios; 3199 3200 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3201 device_printf(bus, "rtsx_mmcbr_update_ios()\n"); 3202 3203 /* if MMCBR_IVAR_BUS_WIDTH updated. */ 3204 if (sc->rtsx_ios_bus_width < 0) { 3205 sc->rtsx_ios_bus_width = ios->bus_width; 3206 if ((error = rtsx_set_bus_width(sc, ios->bus_width))) 3207 return (error); 3208 } 3209 3210 /* if MMCBR_IVAR_POWER_MODE updated. */ 3211 if (sc->rtsx_ios_power_mode < 0) { 3212 sc->rtsx_ios_power_mode = ios->power_mode; 3213 switch (ios->power_mode) { 3214 case power_off: 3215 if ((error = rtsx_bus_power_off(sc))) 3216 return (error); 3217 break; 3218 case power_up: 3219 if ((error = rtsx_bus_power_on(sc))) 3220 return (error); 3221 break; 3222 case power_on: 3223 if ((error = rtsx_bus_power_on(sc))) 3224 return (error); 3225 break; 3226 } 3227 } 3228 3229 sc->rtsx_double_clk = true; 3230 sc->rtsx_vpclk = false; 3231 3232 /* if MMCBR_IVAR_TIMING updated. */ 3233 if (sc->rtsx_ios_timing < 0) { 3234 sc->rtsx_ios_timing = ios->timing; 3235 if ((error = rtsx_set_sd_timing(sc, ios->timing))) 3236 return (error); 3237 } 3238 3239 /* if MMCBR_IVAR_CLOCK updated, must be after rtsx_set_sd_timing() */ 3240 if (sc->rtsx_ios_clock < 0) { 3241 sc->rtsx_ios_clock = ios->clock; 3242 if ((error = rtsx_set_sd_clock(sc, ios->clock))) 3243 return (error); 3244 } 3245 3246 /* if MMCCAM and vccq updated */ 3247 if (sc->rtsx_ios_vccq < 0) { 3248 sc->rtsx_ios_vccq = ios->vccq; 3249 if ((error = rtsx_mmcbr_switch_vccq(sc->rtsx_dev, NULL))) 3250 return (error); 3251 } 3252 3253 return (0); 3254 } 3255 3256 /* 3257 * Set output stage logic power voltage. 3258 */ 3259 static int 3260 rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused) 3261 { 3262 struct rtsx_softc *sc; 3263 int vccq = 0; 3264 int error; 3265 3266 sc = device_get_softc(bus); 3267 3268 switch (sc->rtsx_host.ios.vccq) { 3269 case vccq_120: 3270 vccq = 120; 3271 break; 3272 case vccq_180: 3273 vccq = 180; 3274 break; 3275 case vccq_330: 3276 vccq = 330; 3277 break; 3278 }; 3279 /* It seems it is always vccq_330. */ 3280 if (vccq == 330) { 3281 switch (sc->rtsx_device_id) { 3282 uint16_t val; 3283 case RTSX_RTS5227: 3284 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4))) 3285 return (error); 3286 if ((error = rtsx_rts5227_fill_driving(sc))) 3287 return (error); 3288 break; 3289 case RTSX_RTS5209: 3290 case RTSX_RTS5229: 3291 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3292 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4))) 3293 return (error); 3294 break; 3295 case RTSX_RTS522A: 3296 if ((error = rtsx_write_phy(sc, 0x08, 0x57E4))) 3297 return (error); 3298 if ((error = rtsx_rts5227_fill_driving(sc))) 3299 return (error); 3300 break; 3301 case RTSX_RTS525A: 3302 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_LDO_D3318_MASK, RTSX_LDO_D3318_33V); 3303 RTSX_BITOP(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8, 0); 3304 if ((error = rtsx_rts5249_fill_driving(sc))) 3305 return (error); 3306 break; 3307 case RTSX_RTS5249: 3308 if ((error = rtsx_read_phy(sc, RTSX_PHY_TUNE, &val))) 3309 return (error); 3310 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE, 3311 (val & RTSX_PHY_TUNE_VOLTAGE_MASK) | RTSX_PHY_TUNE_VOLTAGE_3V3))) 3312 return (error); 3313 if ((error = rtsx_rts5249_fill_driving(sc))) 3314 return (error); 3315 break; 3316 case RTSX_RTS5260: 3317 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1); 3318 RTSX_BITOP(sc, RTSX_LDO_DV18_CFG, RTSX_DV331812_MASK, RTSX_DV331812_33); 3319 RTSX_CLR(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8); 3320 if ((error = rtsx_rts5260_fill_driving(sc))) 3321 return (error); 3322 break; 3323 case RTSX_RTL8402: 3324 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3325 RTSX_BITOP(sc, RTSX_LDO_CTL, 3326 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_MASK, 3327 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_3V3); 3328 break; 3329 case RTSX_RTL8411: 3330 case RTSX_RTL8411B: 3331 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3332 RTSX_BITOP(sc, RTSX_LDO_CTL, 3333 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_MASK, 3334 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_3V3); 3335 break; 3336 } 3337 DELAY(300); 3338 } 3339 3340 if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_TRACE_SD_CMD)) 3341 device_printf(sc->rtsx_dev, "rtsx_mmcbr_switch_vccq(%d)\n", vccq); 3342 3343 return (0); 3344 } 3345 3346 #ifndef MMCCAM 3347 /* 3348 * Tune card if bus_timing_uhs_sdr50. 3349 */ 3350 static int 3351 rtsx_mmcbr_tune(device_t bus, device_t child __unused, bool hs400) 3352 { 3353 struct rtsx_softc *sc; 3354 uint32_t raw_phase_map[RTSX_RX_TUNING_CNT] = {0}; 3355 uint32_t phase_map; 3356 uint8_t final_phase; 3357 int i; 3358 3359 sc = device_get_softc(bus); 3360 3361 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3362 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - hs400 is %s\n", 3363 (hs400) ? "true" : "false"); 3364 3365 if (sc->rtsx_ios_timing != bus_timing_uhs_sdr50) 3366 return (0); 3367 3368 sc->rtsx_tuning_mode = true; 3369 3370 switch (sc->rtsx_device_id) { 3371 case RTSX_RTS5209: 3372 case RTSX_RTS5227: 3373 rtsx_sd_change_tx_phase(sc, 27); 3374 break; 3375 case RTSX_RTS522A: 3376 rtsx_sd_change_tx_phase(sc, 20); 3377 break; 3378 case RTSX_RTS5229: 3379 rtsx_sd_change_tx_phase(sc, 27); 3380 break; 3381 case RTSX_RTS525A: 3382 case RTSX_RTS5249: 3383 rtsx_sd_change_tx_phase(sc, 29); 3384 break; 3385 case RTSX_RTL8402: 3386 case RTSX_RTL8411: 3387 case RTSX_RTL8411B: 3388 rtsx_sd_change_tx_phase(sc, 7); 3389 break; 3390 } 3391 3392 /* trying rx tuning for bus_timing_uhs_sdr50. */ 3393 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) { 3394 rtsx_sd_tuning_rx_phase(sc, &(raw_phase_map[i])); 3395 if (raw_phase_map[i] == 0) 3396 break; 3397 } 3398 3399 phase_map = 0xffffffff; 3400 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) { 3401 if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_DEBUG_TUNING)) 3402 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX raw_phase_map[%d]: 0x%08x\n", 3403 i, raw_phase_map[i]); 3404 phase_map &= raw_phase_map[i]; 3405 } 3406 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3407 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX phase_map: 0x%08x\n", phase_map); 3408 3409 if (phase_map) { 3410 final_phase = rtsx_sd_search_final_rx_phase(sc, phase_map); 3411 if (final_phase != 0xff) { 3412 rtsx_sd_change_rx_phase(sc, final_phase); 3413 } 3414 } 3415 3416 sc->rtsx_tuning_mode = false; 3417 3418 return (0); 3419 } 3420 3421 static int 3422 rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused) 3423 { 3424 struct rtsx_softc *sc; 3425 3426 sc = device_get_softc(bus); 3427 3428 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3429 device_printf(sc->rtsx_dev, "rtsx_mmcbr_retune()\n"); 3430 3431 return (0); 3432 } 3433 #endif /* !MMCCAM */ 3434 3435 static int 3436 rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req) 3437 { 3438 struct rtsx_softc *sc; 3439 struct mmc_command *cmd; 3440 int timeout; 3441 int error; 3442 3443 sc = device_get_softc(bus); 3444 3445 RTSX_LOCK(sc); 3446 if (sc->rtsx_req != NULL) { 3447 RTSX_UNLOCK(sc); 3448 return (EBUSY); 3449 } 3450 sc->rtsx_req = req; 3451 cmd = req->cmd; 3452 cmd->error = error = MMC_ERR_NONE; 3453 sc->rtsx_intr_status = 0; 3454 sc->rtsx_intr_trans_ok = NULL; 3455 sc->rtsx_intr_trans_ko = rtsx_req_done; 3456 3457 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3458 device_printf(sc->rtsx_dev, "rtsx_mmcbr_request(CMD%u arg %#x, flags %#x, dlen %u, dflags %#x)\n", 3459 cmd->opcode, cmd->arg, cmd->flags, 3460 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 3461 cmd->data != NULL ? cmd->data->flags : 0); 3462 3463 /* Check if card present. */ 3464 if (!ISSET(sc->rtsx_flags, RTSX_F_CARD_PRESENT)) { 3465 cmd->error = error = MMC_ERR_FAILED; 3466 goto end; 3467 } 3468 3469 /* Refuse SDIO probe if the chip doesn't support SDIO. */ 3470 if (cmd->opcode == IO_SEND_OP_COND && 3471 !ISSET(sc->rtsx_flags, RTSX_F_SDIO_SUPPORT)) { 3472 cmd->error = error = MMC_ERR_INVALID; 3473 goto end; 3474 } 3475 3476 /* Return MMC_ERR_TIMEOUT for SD_IO_RW_DIRECT and IO_SEND_OP_COND. */ 3477 if (cmd->opcode == SD_IO_RW_DIRECT || cmd->opcode == IO_SEND_OP_COND) { 3478 cmd->error = error = MMC_ERR_TIMEOUT; 3479 goto end; 3480 } 3481 3482 /* Select SD card. */ 3483 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL); 3484 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD); 3485 3486 if (cmd->data == NULL) { 3487 DELAY(200); 3488 timeout = sc->rtsx_timeout_cmd; 3489 error = rtsx_send_req(sc, cmd); 3490 } else if (cmd->data->len <= 512) { 3491 timeout = sc->rtsx_timeout_io; 3492 error = rtsx_xfer_short(sc, cmd); 3493 } else { 3494 timeout = sc->rtsx_timeout_io; 3495 error = rtsx_xfer(sc, cmd); 3496 } 3497 end: 3498 if (error == MMC_ERR_NONE) { 3499 callout_reset(&sc->rtsx_timeout_callout, timeout * hz, rtsx_timeout, sc); 3500 } else { 3501 rtsx_req_done(sc); 3502 } 3503 RTSX_UNLOCK(sc); 3504 3505 return (error); 3506 } 3507 3508 #ifndef MMCCAM 3509 static int 3510 rtsx_mmcbr_get_ro(device_t bus, device_t child __unused) 3511 { 3512 struct rtsx_softc *sc; 3513 3514 sc = device_get_softc(bus); 3515 3516 if (sc->rtsx_inversion == 0) 3517 return (sc->rtsx_read_only); 3518 else 3519 return !(sc->rtsx_read_only); 3520 } 3521 3522 static int 3523 rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused) 3524 { 3525 struct rtsx_softc *sc; 3526 3527 sc = device_get_softc(bus); 3528 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3529 device_printf(bus, "rtsx_mmcbr_acquire_host()\n"); 3530 3531 RTSX_LOCK(sc); 3532 while (sc->rtsx_bus_busy) 3533 msleep(&sc->rtsx_bus_busy, &sc->rtsx_mtx, 0, "rtsxah", 0); 3534 sc->rtsx_bus_busy++; 3535 RTSX_UNLOCK(sc); 3536 3537 return (0); 3538 } 3539 3540 static int 3541 rtsx_mmcbr_release_host(device_t bus, device_t child __unused) 3542 { 3543 struct rtsx_softc *sc; 3544 3545 sc = device_get_softc(bus); 3546 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3547 device_printf(bus, "rtsx_mmcbr_release_host()\n"); 3548 3549 RTSX_LOCK(sc); 3550 sc->rtsx_bus_busy--; 3551 wakeup(&sc->rtsx_bus_busy); 3552 RTSX_UNLOCK(sc); 3553 3554 return (0); 3555 } 3556 #endif /* !MMCCAM */ 3557 3558 /* 3559 * 3560 * PCI Support Functions 3561 * 3562 */ 3563 3564 /* 3565 * Compare the device ID (chip) of this device against the IDs that this driver 3566 * supports. If there is a match, set the description and return success. 3567 */ 3568 static int 3569 rtsx_probe(device_t dev) 3570 { 3571 uint16_t vendor_id; 3572 uint16_t device_id; 3573 int i; 3574 3575 vendor_id = pci_get_vendor(dev); 3576 device_id = pci_get_device(dev); 3577 3578 if (vendor_id != RTSX_REALTEK) 3579 return (ENXIO); 3580 for (i = 0; i < nitems(rtsx_ids); i++) { 3581 if (rtsx_ids[i].device_id == device_id) { 3582 device_set_desc(dev, rtsx_ids[i].desc); 3583 return (BUS_PROBE_DEFAULT); 3584 } 3585 } 3586 return (ENXIO); 3587 } 3588 3589 /* 3590 * Attach function is only called if the probe is successful. 3591 */ 3592 static int 3593 rtsx_attach(device_t dev) 3594 { 3595 struct rtsx_softc *sc = device_get_softc(dev); 3596 uint16_t vendor_id; 3597 uint16_t device_id; 3598 struct sysctl_ctx_list *ctx; 3599 struct sysctl_oid_list *tree; 3600 int msi_count = 1; 3601 uint32_t sdio_cfg; 3602 int error; 3603 char *maker; 3604 char *family; 3605 char *product; 3606 int i; 3607 3608 vendor_id = pci_get_vendor(dev); 3609 device_id = pci_get_device(dev); 3610 if (bootverbose) 3611 device_printf(dev, "Attach - Vendor ID: 0x%x - Device ID: 0x%x\n", 3612 vendor_id, device_id); 3613 3614 sc->rtsx_dev = dev; 3615 sc->rtsx_device_id = device_id; 3616 sc->rtsx_req = NULL; 3617 sc->rtsx_timeout_cmd = 1; 3618 sc->rtsx_timeout_io = 10; 3619 sc->rtsx_read_only = 0; 3620 sc->rtsx_inversion = 0; 3621 sc->rtsx_force_timing = 0; 3622 sc->rtsx_debug_mask = 0; 3623 sc->rtsx_read_count = 0; 3624 sc->rtsx_write_count = 0; 3625 3626 maker = kern_getenv("smbios.system.maker"); 3627 family = kern_getenv("smbios.system.family"); 3628 product = kern_getenv("smbios.system.product"); 3629 for (i = 0; rtsx_inversion_models[i].maker != NULL; i++) { 3630 if (strcmp(rtsx_inversion_models[i].maker, maker) == 0 && 3631 strcmp(rtsx_inversion_models[i].family, family) == 0 && 3632 strcmp(rtsx_inversion_models[i].product, product) == 0) { 3633 device_printf(dev, "Inversion activated for %s/%s/%s, see BUG in rtsx(4)\n", maker, family, product); 3634 device_printf(dev, "If a card is detected without an SD card present," 3635 " add dev.rtsx.0.inversion=0 in loader.conf(5)\n"); 3636 sc->rtsx_inversion = 1; 3637 break; 3638 } 3639 } 3640 3641 RTSX_LOCK_INIT(sc); 3642 3643 ctx = device_get_sysctl_ctx(dev); 3644 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 3645 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_io", CTLFLAG_RW, 3646 &sc->rtsx_timeout_io, 0, "Request timeout for I/O commands in seconds"); 3647 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_cmd", CTLFLAG_RW, 3648 &sc->rtsx_timeout_cmd, 0, "Request timeout for setup commands in seconds"); 3649 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "read_only", CTLFLAG_RD, 3650 &sc->rtsx_read_only, 0, "Card is write protected"); 3651 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "inversion", CTLFLAG_RWTUN, 3652 &sc->rtsx_inversion, 0, "Inversion of card detection and read only status"); 3653 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "force_timing", CTLFLAG_RW, 3654 &sc->rtsx_force_timing, 0, "Force bus_timing_uhs_sdr50"); 3655 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "debug_mask", CTLFLAG_RWTUN, 3656 &sc->rtsx_debug_mask, 0, "debugging mask, see rtsx(4)"); 3657 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "read_count", CTLFLAG_RD | CTLFLAG_STATS, 3658 &sc->rtsx_read_count, 0, "Count of read operations"); 3659 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "write_count", CTLFLAG_RD | CTLFLAG_STATS, 3660 &sc->rtsx_write_count, 0, "Count of write operations"); 3661 3662 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3663 device_printf(dev, "We are running with inversion: %d\n", sc->rtsx_inversion); 3664 3665 /* Allocate IRQ. */ 3666 sc->rtsx_irq_res_id = 0; 3667 if (pci_alloc_msi(dev, &msi_count) == 0) 3668 sc->rtsx_irq_res_id = 1; 3669 sc->rtsx_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->rtsx_irq_res_id, 3670 RF_ACTIVE | (sc->rtsx_irq_res_id != 0 ? 0 : RF_SHAREABLE)); 3671 if (sc->rtsx_irq_res == NULL) { 3672 device_printf(dev, "Can't allocate IRQ resources for %d\n", sc->rtsx_irq_res_id); 3673 pci_release_msi(dev); 3674 return (ENXIO); 3675 } 3676 3677 callout_init_mtx(&sc->rtsx_timeout_callout, &sc->rtsx_mtx, 0); 3678 3679 /* Allocate memory resource. */ 3680 if (sc->rtsx_device_id == RTSX_RTS525A) 3681 sc->rtsx_mem_res_id = PCIR_BAR(1); 3682 else 3683 sc->rtsx_mem_res_id = PCIR_BAR(0); 3684 sc->rtsx_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rtsx_mem_res_id, RF_ACTIVE); 3685 if (sc->rtsx_mem_res == NULL) { 3686 device_printf(dev, "Can't allocate memory resource for %d\n", sc->rtsx_mem_res_id); 3687 goto destroy_rtsx_irq_res; 3688 } 3689 3690 if (bootverbose) 3691 device_printf(dev, "rtsx_irq_res_id: %d, rtsx_mem_res_id: %d\n", 3692 sc->rtsx_irq_res_id, sc->rtsx_mem_res_id); 3693 3694 sc->rtsx_mem_btag = rman_get_bustag(sc->rtsx_mem_res); 3695 sc->rtsx_mem_bhandle = rman_get_bushandle(sc->rtsx_mem_res); 3696 3697 TIMEOUT_TASK_INIT(taskqueue_bus, &sc->rtsx_card_insert_task, 0, 3698 rtsx_card_task, sc); 3699 TASK_INIT(&sc->rtsx_card_remove_task, 0, rtsx_card_task, sc); 3700 3701 /* Allocate two DMA buffers: a command buffer and a data buffer. */ 3702 error = rtsx_dma_alloc(sc); 3703 if (error) 3704 goto destroy_rtsx_irq_res; 3705 3706 /* Activate the interrupt. */ 3707 error = bus_setup_intr(dev, sc->rtsx_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 3708 NULL, rtsx_intr, sc, &sc->rtsx_irq_cookie); 3709 if (error) { 3710 device_printf(dev, "Can't set up irq [0x%x]!\n", error); 3711 goto destroy_rtsx_mem_res; 3712 } 3713 pci_enable_busmaster(dev); 3714 3715 if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg) == 0) { 3716 if ((sdio_cfg & RTSX_SDIOCFG_SDIO_ONLY) || 3717 (sdio_cfg & RTSX_SDIOCFG_HAVE_SDIO)) 3718 sc->rtsx_flags |= RTSX_F_SDIO_SUPPORT; 3719 } 3720 3721 #ifdef MMCCAM 3722 sc->rtsx_ccb = NULL; 3723 sc->rtsx_cam_status = 0; 3724 3725 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "cam_status", CTLFLAG_RD, 3726 &sc->rtsx_cam_status, 0, "driver cam card present"); 3727 3728 if (mmc_cam_sim_alloc(dev, "rtsx_mmc", &sc->rtsx_mmc_sim) != 0) { 3729 device_printf(dev, "Can't allocate CAM SIM\n"); 3730 goto destroy_rtsx_irq; 3731 } 3732 #endif /* MMCCAM */ 3733 3734 /* Initialize device. */ 3735 error = rtsx_init(sc); 3736 if (error) { 3737 device_printf(dev, "Error %d during rtsx_init()\n", error); 3738 goto destroy_rtsx_irq; 3739 } 3740 3741 /* 3742 * Schedule a card detection as we won't get an interrupt 3743 * if the card is inserted when we attach. We wait a quarter 3744 * of a second to allow for a "spontaneous" interrupt which may 3745 * change the card presence state. This delay avoid a panic 3746 * on some configuration (e.g. Lenovo T540p). 3747 */ 3748 DELAY(250000); 3749 if (rtsx_is_card_present(sc)) 3750 device_printf(sc->rtsx_dev, "A card is detected\n"); 3751 else 3752 device_printf(sc->rtsx_dev, "No card is detected\n"); 3753 rtsx_card_task(sc, 0); 3754 3755 if (bootverbose) 3756 device_printf(dev, "Device attached\n"); 3757 3758 return (0); 3759 3760 destroy_rtsx_irq: 3761 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie); 3762 destroy_rtsx_mem_res: 3763 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_mem_res_id, 3764 sc->rtsx_mem_res); 3765 rtsx_dma_free(sc); 3766 destroy_rtsx_irq_res: 3767 callout_drain(&sc->rtsx_timeout_callout); 3768 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id, 3769 sc->rtsx_irq_res); 3770 pci_release_msi(dev); 3771 RTSX_LOCK_DESTROY(sc); 3772 3773 return (ENXIO); 3774 } 3775 3776 static int 3777 rtsx_detach(device_t dev) 3778 { 3779 struct rtsx_softc *sc = device_get_softc(dev); 3780 int error; 3781 3782 if (bootverbose) 3783 device_printf(dev, "Detach - Vendor ID: 0x%x - Device ID: 0x%x\n", 3784 pci_get_vendor(dev), sc->rtsx_device_id); 3785 3786 /* Disable interrupts. */ 3787 sc->rtsx_intr_enabled = 0; 3788 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled); 3789 3790 /* Stop device. */ 3791 error = bus_generic_detach(sc->rtsx_dev); 3792 if (error) 3793 return (error); 3794 sc->rtsx_mmc_dev = NULL; 3795 3796 taskqueue_drain_timeout(taskqueue_bus, &sc->rtsx_card_insert_task); 3797 taskqueue_drain(taskqueue_bus, &sc->rtsx_card_remove_task); 3798 3799 /* Teardown the state in our softc created in our attach routine. */ 3800 rtsx_dma_free(sc); 3801 if (sc->rtsx_mem_res != NULL) 3802 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_mem_res_id, 3803 sc->rtsx_mem_res); 3804 if (sc->rtsx_irq_cookie != NULL) 3805 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie); 3806 if (sc->rtsx_irq_res != NULL) { 3807 callout_drain(&sc->rtsx_timeout_callout); 3808 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id, 3809 sc->rtsx_irq_res); 3810 pci_release_msi(dev); 3811 } 3812 RTSX_LOCK_DESTROY(sc); 3813 #ifdef MMCCAM 3814 mmc_cam_sim_free(&sc->rtsx_mmc_sim); 3815 #endif /* MMCCAM */ 3816 3817 return (0); 3818 } 3819 3820 static int 3821 rtsx_shutdown(device_t dev) 3822 { 3823 if (bootverbose) 3824 device_printf(dev, "Shutdown\n"); 3825 3826 return (0); 3827 } 3828 3829 /* 3830 * Device suspend routine. 3831 */ 3832 static int 3833 rtsx_suspend(device_t dev) 3834 { 3835 struct rtsx_softc *sc = device_get_softc(dev); 3836 3837 device_printf(dev, "Suspend\n"); 3838 3839 #ifdef MMCCAM 3840 if (sc->rtsx_ccb != NULL) { 3841 device_printf(dev, "Request in progress: CMD%u, rtsr_intr_status: 0x%08x\n", 3842 sc->rtsx_ccb->mmcio.cmd.opcode, sc->rtsx_intr_status); 3843 } 3844 #else /* !MMCCAM */ 3845 if (sc->rtsx_req != NULL) { 3846 device_printf(dev, "Request in progress: CMD%u, rtsr_intr_status: 0x%08x\n", 3847 sc->rtsx_req->cmd->opcode, sc->rtsx_intr_status); 3848 } 3849 #endif /* MMCCAM */ 3850 3851 bus_generic_suspend(dev); 3852 3853 return (0); 3854 } 3855 3856 /* 3857 * Device resume routine. 3858 */ 3859 static int 3860 rtsx_resume(device_t dev) 3861 { 3862 device_printf(dev, "Resume\n"); 3863 3864 rtsx_init(device_get_softc(dev)); 3865 3866 bus_generic_resume(dev); 3867 3868 return (0); 3869 } 3870 3871 static device_method_t rtsx_methods[] = { 3872 /* Device interface */ 3873 DEVMETHOD(device_probe, rtsx_probe), 3874 DEVMETHOD(device_attach, rtsx_attach), 3875 DEVMETHOD(device_detach, rtsx_detach), 3876 DEVMETHOD(device_shutdown, rtsx_shutdown), 3877 DEVMETHOD(device_suspend, rtsx_suspend), 3878 DEVMETHOD(device_resume, rtsx_resume), 3879 3880 /* Bus interface */ 3881 DEVMETHOD(bus_read_ivar, rtsx_read_ivar), 3882 DEVMETHOD(bus_write_ivar, rtsx_write_ivar), 3883 3884 #ifndef MMCCAM 3885 /* MMC bridge interface */ 3886 DEVMETHOD(mmcbr_update_ios, rtsx_mmcbr_update_ios), 3887 DEVMETHOD(mmcbr_switch_vccq, rtsx_mmcbr_switch_vccq), 3888 DEVMETHOD(mmcbr_tune, rtsx_mmcbr_tune), 3889 DEVMETHOD(mmcbr_retune, rtsx_mmcbr_retune), 3890 DEVMETHOD(mmcbr_request, rtsx_mmcbr_request), 3891 DEVMETHOD(mmcbr_get_ro, rtsx_mmcbr_get_ro), 3892 DEVMETHOD(mmcbr_acquire_host, rtsx_mmcbr_acquire_host), 3893 DEVMETHOD(mmcbr_release_host, rtsx_mmcbr_release_host), 3894 #endif /* !MMCCAM */ 3895 3896 #ifdef MMCCAM 3897 /* MMCCAM interface */ 3898 DEVMETHOD(mmc_sim_get_tran_settings, rtsx_get_tran_settings), 3899 DEVMETHOD(mmc_sim_set_tran_settings, rtsx_set_tran_settings), 3900 DEVMETHOD(mmc_sim_cam_request, rtsx_cam_request), 3901 #endif /* MMCCAM */ 3902 3903 DEVMETHOD_END 3904 }; 3905 3906 DEFINE_CLASS_0(rtsx, rtsx_driver, rtsx_methods, sizeof(struct rtsx_softc)); 3907 DRIVER_MODULE(rtsx, pci, rtsx_driver, NULL, NULL); 3908 3909 /* For Plug and Play */ 3910 MODULE_PNP_INFO("U16:device;D:#;T:vendor=0x10ec", pci, rtsx, 3911 rtsx_ids, nitems(rtsx_ids)); 3912 3913 #ifndef MMCCAM 3914 MMC_DECLARE_BRIDGE(rtsx); 3915 #endif /* !MMCCAM */ 3916