1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2015-2016 Hiroki Mori. 5 * Copyright (c) 2011-2012 Stefan Bethke. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include "opt_etherswitch.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/errno.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/socket.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 45 #include <net/if.h> 46 #include <net/if_var.h> 47 #include <net/ethernet.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <machine/bus.h> 52 #include <dev/iicbus/iic.h> 53 #include <dev/iicbus/iiconf.h> 54 #include <dev/iicbus/iicbus.h> 55 #include <dev/mii/mii.h> 56 #include <dev/mii/miivar.h> 57 #include <dev/mdio/mdio.h> 58 59 #include <dev/etherswitch/etherswitch.h> 60 #include <dev/etherswitch/rtl8366/rtl8366rbvar.h> 61 62 #include "mdio_if.h" 63 #include "iicbus_if.h" 64 #include "miibus_if.h" 65 #include "etherswitch_if.h" 66 67 68 struct rtl8366rb_softc { 69 struct mtx sc_mtx; /* serialize access to softc */ 70 int smi_acquired; /* serialize access to SMI/I2C bus */ 71 struct mtx callout_mtx; /* serialize callout */ 72 device_t dev; 73 int vid[RTL8366_NUM_VLANS]; 74 char *ifname[RTL8366_NUM_PHYS]; 75 device_t miibus[RTL8366_NUM_PHYS]; 76 if_t ifp[RTL8366_NUM_PHYS]; 77 struct callout callout_tick; 78 etherswitch_info_t info; 79 int chip_type; 80 int phy4cpu; 81 int numphys; 82 }; 83 84 #define RTL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 85 #define RTL_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 86 #define RTL_LOCK_ASSERT(_sc, _what) mtx_assert(&(_s)c->sc_mtx, (_what)) 87 #define RTL_TRYLOCK(_sc) mtx_trylock(&(_sc)->sc_mtx) 88 89 #define RTL_WAITOK 0 90 #define RTL_NOWAIT 1 91 92 #define RTL_SMI_ACQUIRED 1 93 #define RTL_SMI_ACQUIRED_ASSERT(_sc) \ 94 KASSERT((_sc)->smi_acquired == RTL_SMI_ACQUIRED, ("smi must be acquired @%s", __FUNCTION__)) 95 96 #if defined(DEBUG) 97 #define DPRINTF(dev, args...) device_printf(dev, args) 98 #define DEVERR(dev, err, fmt, args...) do { \ 99 if (err != 0) device_printf(dev, fmt, err, args); \ 100 } while (0) 101 #define DEBUG_INCRVAR(var) do { \ 102 var++; \ 103 } while (0) 104 105 static int callout_blocked = 0; 106 static int iic_select_retries = 0; 107 static int phy_access_retries = 0; 108 static SYSCTL_NODE(_debug, OID_AUTO, rtl8366rb, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 109 "rtl8366rb"); 110 SYSCTL_INT(_debug_rtl8366rb, OID_AUTO, callout_blocked, CTLFLAG_RW, &callout_blocked, 0, 111 "number of times the callout couldn't acquire the bus"); 112 SYSCTL_INT(_debug_rtl8366rb, OID_AUTO, iic_select_retries, CTLFLAG_RW, &iic_select_retries, 0, 113 "number of times the I2C bus selection had to be retried"); 114 SYSCTL_INT(_debug_rtl8366rb, OID_AUTO, phy_access_retries, CTLFLAG_RW, &phy_access_retries, 0, 115 "number of times PHY register access had to be retried"); 116 #else 117 #define DPRINTF(dev, args...) 118 #define DEVERR(dev, err, fmt, args...) 119 #define DEBUG_INCRVAR(var) 120 #endif 121 122 static int smi_probe(device_t dev); 123 static int smi_read(device_t dev, uint16_t addr, uint16_t *data, int sleep); 124 static int smi_write(device_t dev, uint16_t addr, uint16_t data, int sleep); 125 static int smi_rmw(device_t dev, uint16_t addr, uint16_t mask, uint16_t data, int sleep); 126 static void rtl8366rb_tick(void *arg); 127 static int rtl8366rb_ifmedia_upd(if_t); 128 static void rtl8366rb_ifmedia_sts(if_t, struct ifmediareq *); 129 130 static void 131 rtl8366rb_identify(driver_t *driver, device_t parent) 132 { 133 device_t child; 134 struct iicbus_ivar *devi; 135 136 if (device_find_child(parent, "rtl8366rb", -1) == NULL) { 137 child = BUS_ADD_CHILD(parent, 0, "rtl8366rb", DEVICE_UNIT_ANY); 138 devi = IICBUS_IVAR(child); 139 devi->addr = RTL8366_IIC_ADDR; 140 } 141 } 142 143 static int 144 rtl8366rb_probe(device_t dev) 145 { 146 struct rtl8366rb_softc *sc; 147 148 sc = device_get_softc(dev); 149 150 bzero(sc, sizeof(*sc)); 151 if (smi_probe(dev) != 0) 152 return (ENXIO); 153 if (sc->chip_type == RTL8366RB) 154 device_set_desc(dev, "RTL8366RB Ethernet Switch Controller"); 155 else 156 device_set_desc(dev, "RTL8366SR Ethernet Switch Controller"); 157 return (BUS_PROBE_DEFAULT); 158 } 159 160 static void 161 rtl8366rb_init(device_t dev) 162 { 163 struct rtl8366rb_softc *sc; 164 int i; 165 166 sc = device_get_softc(dev); 167 168 /* Initialisation for TL-WR1043ND */ 169 #ifdef RTL8366_SOFT_RESET 170 smi_rmw(dev, RTL8366_RCR, 171 RTL8366_RCR_SOFT_RESET, 172 RTL8366_RCR_SOFT_RESET, RTL_WAITOK); 173 #else 174 smi_rmw(dev, RTL8366_RCR, 175 RTL8366_RCR_HARD_RESET, 176 RTL8366_RCR_HARD_RESET, RTL_WAITOK); 177 #endif 178 /* hard reset not return ack */ 179 DELAY(100000); 180 /* Enable 16 VLAN mode */ 181 smi_rmw(dev, RTL8366_SGCR, 182 RTL8366_SGCR_EN_VLAN | RTL8366_SGCR_EN_VLAN_4KTB, 183 RTL8366_SGCR_EN_VLAN, RTL_WAITOK); 184 /* Initialize our vlan table. */ 185 for (i = 0; i <= 1; i++) 186 sc->vid[i] = (i + 1) | ETHERSWITCH_VID_VALID; 187 /* Remove port 0 from VLAN 1. */ 188 smi_rmw(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, 0), 189 (1 << 0), 0, RTL_WAITOK); 190 /* Add port 0 untagged and port 5 tagged to VLAN 2. */ 191 smi_rmw(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, 1), 192 ((1 << 5 | 1 << 0) << RTL8366_VMCR_MU_MEMBER_SHIFT) 193 | ((1 << 5 | 1 << 0) << RTL8366_VMCR_MU_UNTAG_SHIFT), 194 ((1 << 5 | 1 << 0) << RTL8366_VMCR_MU_MEMBER_SHIFT 195 | ((1 << 0) << RTL8366_VMCR_MU_UNTAG_SHIFT)), 196 RTL_WAITOK); 197 /* Set PVID 2 for port 0. */ 198 smi_rmw(dev, RTL8366_PVCR_REG(0), 199 RTL8366_PVCR_VAL(0, RTL8366_PVCR_PORT_MASK), 200 RTL8366_PVCR_VAL(0, 1), RTL_WAITOK); 201 } 202 203 static int 204 rtl8366rb_attach(device_t dev) 205 { 206 struct rtl8366rb_softc *sc; 207 uint16_t rev = 0; 208 char name[IFNAMSIZ]; 209 int err = 0; 210 int i; 211 212 sc = device_get_softc(dev); 213 214 sc->dev = dev; 215 mtx_init(&sc->sc_mtx, "rtl8366rb", NULL, MTX_DEF); 216 sc->smi_acquired = 0; 217 mtx_init(&sc->callout_mtx, "rtl8366rbcallout", NULL, MTX_DEF); 218 219 rtl8366rb_init(dev); 220 smi_read(dev, RTL8366_CVCR, &rev, RTL_WAITOK); 221 device_printf(dev, "rev. %d\n", rev & 0x000f); 222 223 sc->phy4cpu = 0; 224 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 225 "phy4cpu", &sc->phy4cpu); 226 227 sc->numphys = sc->phy4cpu ? RTL8366_NUM_PHYS - 1 : RTL8366_NUM_PHYS; 228 229 sc->info.es_nports = sc->numphys + 1; 230 sc->info.es_nvlangroups = RTL8366_NUM_VLANS; 231 sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q; 232 if (sc->chip_type == RTL8366RB) 233 sprintf(sc->info.es_name, "Realtek RTL8366RB"); 234 else 235 sprintf(sc->info.es_name, "Realtek RTL8366SR"); 236 237 /* attach miibus and phys */ 238 /* PHYs need an interface, so we generate a dummy one */ 239 for (i = 0; i < sc->numphys; i++) { 240 sc->ifp[i] = if_alloc(IFT_ETHER); 241 if_setsoftc(sc->ifp[i], sc); 242 if_setflagbits(sc->ifp[i], IFF_UP | IFF_BROADCAST | IFF_DRV_RUNNING 243 | IFF_SIMPLEX, 0); 244 snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(dev)); 245 sc->ifname[i] = malloc(strlen(name)+1, M_DEVBUF, M_WAITOK); 246 bcopy(name, sc->ifname[i], strlen(name)+1); 247 if_initname(sc->ifp[i], sc->ifname[i], i); 248 err = mii_attach(dev, &sc->miibus[i], sc->ifp[i], rtl8366rb_ifmedia_upd, \ 249 rtl8366rb_ifmedia_sts, BMSR_DEFCAPMASK, \ 250 i, MII_OFFSET_ANY, 0); 251 if (err != 0) { 252 device_printf(dev, "attaching PHY %d failed\n", i); 253 return (err); 254 } 255 } 256 257 bus_generic_probe(dev); 258 bus_enumerate_hinted_children(dev); 259 err = bus_generic_attach(dev); 260 if (err != 0) 261 return (err); 262 263 callout_init_mtx(&sc->callout_tick, &sc->callout_mtx, 0); 264 rtl8366rb_tick(sc); 265 266 return (err); 267 } 268 269 static int 270 rtl8366rb_detach(device_t dev) 271 { 272 struct rtl8366rb_softc *sc; 273 int i; 274 275 sc = device_get_softc(dev); 276 277 for (i=0; i < sc->numphys; i++) { 278 if (sc->miibus[i]) 279 device_delete_child(dev, sc->miibus[i]); 280 if (sc->ifp[i] != NULL) 281 if_free(sc->ifp[i]); 282 free(sc->ifname[i], M_DEVBUF); 283 } 284 bus_generic_detach(dev); 285 callout_drain(&sc->callout_tick); 286 mtx_destroy(&sc->callout_mtx); 287 mtx_destroy(&sc->sc_mtx); 288 289 return (0); 290 } 291 292 static void 293 rtl8366rb_update_ifmedia(int portstatus, u_int *media_status, u_int *media_active) 294 { 295 *media_active = IFM_ETHER; 296 *media_status = IFM_AVALID; 297 if ((portstatus & RTL8366_PLSR_LINK) != 0) 298 *media_status |= IFM_ACTIVE; 299 else { 300 *media_active |= IFM_NONE; 301 return; 302 } 303 switch (portstatus & RTL8366_PLSR_SPEED_MASK) { 304 case RTL8366_PLSR_SPEED_10: 305 *media_active |= IFM_10_T; 306 break; 307 case RTL8366_PLSR_SPEED_100: 308 *media_active |= IFM_100_TX; 309 break; 310 case RTL8366_PLSR_SPEED_1000: 311 *media_active |= IFM_1000_T; 312 break; 313 } 314 if ((portstatus & RTL8366_PLSR_FULLDUPLEX) != 0) 315 *media_active |= IFM_FDX; 316 else 317 *media_active |= IFM_HDX; 318 if ((portstatus & RTL8366_PLSR_TXPAUSE) != 0) 319 *media_active |= IFM_ETH_TXPAUSE; 320 if ((portstatus & RTL8366_PLSR_RXPAUSE) != 0) 321 *media_active |= IFM_ETH_RXPAUSE; 322 } 323 324 static void 325 rtl833rb_miipollstat(struct rtl8366rb_softc *sc) 326 { 327 int i; 328 struct mii_data *mii; 329 struct mii_softc *miisc; 330 uint16_t value; 331 int portstatus; 332 333 for (i = 0; i < sc->numphys; i++) { 334 mii = device_get_softc(sc->miibus[i]); 335 if ((i % 2) == 0) { 336 if (smi_read(sc->dev, RTL8366_PLSR_BASE + i/2, &value, RTL_NOWAIT) != 0) { 337 DEBUG_INCRVAR(callout_blocked); 338 return; 339 } 340 portstatus = value & 0xff; 341 } else { 342 portstatus = (value >> 8) & 0xff; 343 } 344 rtl8366rb_update_ifmedia(portstatus, &mii->mii_media_status, &mii->mii_media_active); 345 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 346 if (IFM_INST(mii->mii_media.ifm_cur->ifm_media) != miisc->mii_inst) 347 continue; 348 mii_phy_update(miisc, MII_POLLSTAT); 349 } 350 } 351 } 352 353 static void 354 rtl8366rb_tick(void *arg) 355 { 356 struct rtl8366rb_softc *sc; 357 358 sc = arg; 359 360 rtl833rb_miipollstat(sc); 361 callout_reset(&sc->callout_tick, hz, rtl8366rb_tick, sc); 362 } 363 364 static int 365 smi_probe(device_t dev) 366 { 367 struct rtl8366rb_softc *sc; 368 device_t iicbus, iicha; 369 int err, i, j; 370 uint16_t chipid; 371 char bytes[2]; 372 int xferd; 373 374 sc = device_get_softc(dev); 375 376 iicbus = device_get_parent(dev); 377 iicha = device_get_parent(iicbus); 378 379 for (i = 0; i < 2; ++i) { 380 iicbus_reset(iicbus, IIC_FASTEST, RTL8366_IIC_ADDR, NULL); 381 for (j=3; j--; ) { 382 IICBUS_STOP(iicha); 383 /* 384 * we go directly to the host adapter because iicbus.c 385 * only issues a stop on a bus that was successfully started. 386 */ 387 } 388 err = iicbus_request_bus(iicbus, dev, IIC_WAIT); 389 if (err != 0) 390 goto out; 391 err = iicbus_start(iicbus, RTL8366_IIC_ADDR | RTL_IICBUS_READ, RTL_IICBUS_TIMEOUT); 392 if (err != 0) 393 goto out; 394 if (i == 0) { 395 bytes[0] = RTL8366RB_CIR & 0xff; 396 bytes[1] = (RTL8366RB_CIR >> 8) & 0xff; 397 } else { 398 bytes[0] = RTL8366SR_CIR & 0xff; 399 bytes[1] = (RTL8366SR_CIR >> 8) & 0xff; 400 } 401 err = iicbus_write(iicbus, bytes, 2, &xferd, RTL_IICBUS_TIMEOUT); 402 if (err != 0) 403 goto out; 404 err = iicbus_read(iicbus, bytes, 2, &xferd, IIC_LAST_READ, 0); 405 if (err != 0) 406 goto out; 407 chipid = ((bytes[1] & 0xff) << 8) | (bytes[0] & 0xff); 408 if (i == 0 && chipid == RTL8366RB_CIR_ID8366RB) { 409 DPRINTF(dev, "chip id 0x%04x\n", chipid); 410 sc->chip_type = RTL8366RB; 411 err = 0; 412 break; 413 } 414 if (i == 1 && chipid == RTL8366SR_CIR_ID8366SR) { 415 DPRINTF(dev, "chip id 0x%04x\n", chipid); 416 sc->chip_type = RTL8366SR; 417 err = 0; 418 break; 419 } 420 if (i == 0) { 421 iicbus_stop(iicbus); 422 iicbus_release_bus(iicbus, dev); 423 } 424 } 425 if (i == 2) 426 err = ENXIO; 427 out: 428 iicbus_stop(iicbus); 429 iicbus_release_bus(iicbus, dev); 430 return (err == 0 ? 0 : ENXIO); 431 } 432 433 static int 434 smi_acquire(struct rtl8366rb_softc *sc, int sleep) 435 { 436 int r = 0; 437 if (sleep == RTL_WAITOK) 438 RTL_LOCK(sc); 439 else 440 if (RTL_TRYLOCK(sc) == 0) 441 return (EWOULDBLOCK); 442 if (sc->smi_acquired == RTL_SMI_ACQUIRED) 443 r = EBUSY; 444 else { 445 r = iicbus_request_bus(device_get_parent(sc->dev), sc->dev, \ 446 sleep == RTL_WAITOK ? IIC_WAIT : IIC_DONTWAIT); 447 if (r == 0) 448 sc->smi_acquired = RTL_SMI_ACQUIRED; 449 } 450 RTL_UNLOCK(sc); 451 return (r); 452 } 453 454 static int 455 smi_release(struct rtl8366rb_softc *sc, int sleep) 456 { 457 if (sleep == RTL_WAITOK) 458 RTL_LOCK(sc); 459 else 460 if (RTL_TRYLOCK(sc) == 0) 461 return (EWOULDBLOCK); 462 RTL_SMI_ACQUIRED_ASSERT(sc); 463 iicbus_release_bus(device_get_parent(sc->dev), sc->dev); 464 sc->smi_acquired = 0; 465 RTL_UNLOCK(sc); 466 return (0); 467 } 468 469 static int 470 smi_select(device_t dev, int op, int sleep) 471 { 472 struct rtl8366rb_softc *sc; 473 int err, i; 474 device_t iicbus; 475 struct iicbus_ivar *devi; 476 int slave; 477 478 sc = device_get_softc(dev); 479 480 iicbus = device_get_parent(dev); 481 devi = IICBUS_IVAR(dev); 482 slave = devi->addr; 483 484 RTL_SMI_ACQUIRED_ASSERT((struct rtl8366rb_softc *)device_get_softc(dev)); 485 486 if (sc->chip_type == RTL8366SR) { // RTL8366SR work around 487 // this is same work around at probe 488 for (int i=3; i--; ) 489 IICBUS_STOP(device_get_parent(device_get_parent(dev))); 490 } 491 /* 492 * The chip does not use clock stretching when it is busy, 493 * instead ignoring the command. Retry a few times. 494 */ 495 for (i = RTL_IICBUS_RETRIES; i--; ) { 496 err = iicbus_start(iicbus, slave | op, RTL_IICBUS_TIMEOUT); 497 if (err != IIC_ENOACK) 498 break; 499 if (sleep == RTL_WAITOK) { 500 DEBUG_INCRVAR(iic_select_retries); 501 pause("smi_select", RTL_IICBUS_RETRY_SLEEP); 502 } else 503 break; 504 } 505 return (err); 506 } 507 508 static int 509 smi_read_locked(struct rtl8366rb_softc *sc, uint16_t addr, uint16_t *data, int sleep) 510 { 511 int err; 512 device_t iicbus; 513 char bytes[2]; 514 int xferd; 515 516 iicbus = device_get_parent(sc->dev); 517 518 RTL_SMI_ACQUIRED_ASSERT(sc); 519 bytes[0] = addr & 0xff; 520 bytes[1] = (addr >> 8) & 0xff; 521 err = smi_select(sc->dev, RTL_IICBUS_READ, sleep); 522 if (err != 0) 523 goto out; 524 err = iicbus_write(iicbus, bytes, 2, &xferd, RTL_IICBUS_TIMEOUT); 525 if (err != 0) 526 goto out; 527 err = iicbus_read(iicbus, bytes, 2, &xferd, IIC_LAST_READ, 0); 528 if (err != 0) 529 goto out; 530 *data = ((bytes[1] & 0xff) << 8) | (bytes[0] & 0xff); 531 532 out: 533 iicbus_stop(iicbus); 534 return (err); 535 } 536 537 static int 538 smi_write_locked(struct rtl8366rb_softc *sc, uint16_t addr, uint16_t data, int sleep) 539 { 540 int err; 541 device_t iicbus; 542 char bytes[4]; 543 int xferd; 544 545 iicbus = device_get_parent(sc->dev); 546 547 RTL_SMI_ACQUIRED_ASSERT(sc); 548 bytes[0] = addr & 0xff; 549 bytes[1] = (addr >> 8) & 0xff; 550 bytes[2] = data & 0xff; 551 bytes[3] = (data >> 8) & 0xff; 552 553 err = smi_select(sc->dev, RTL_IICBUS_WRITE, sleep); 554 if (err == 0) 555 err = iicbus_write(iicbus, bytes, 4, &xferd, RTL_IICBUS_TIMEOUT); 556 iicbus_stop(iicbus); 557 558 return (err); 559 } 560 561 static int 562 smi_read(device_t dev, uint16_t addr, uint16_t *data, int sleep) 563 { 564 struct rtl8366rb_softc *sc; 565 int err; 566 567 sc = device_get_softc(dev); 568 569 err = smi_acquire(sc, sleep); 570 if (err != 0) 571 return (EBUSY); 572 err = smi_read_locked(sc, addr, data, sleep); 573 smi_release(sc, sleep); 574 DEVERR(dev, err, "smi_read()=%d: addr=%04x\n", addr); 575 return (err == 0 ? 0 : EIO); 576 } 577 578 static int 579 smi_write(device_t dev, uint16_t addr, uint16_t data, int sleep) 580 { 581 struct rtl8366rb_softc *sc; 582 int err; 583 584 sc = device_get_softc(dev); 585 586 err = smi_acquire(sc, sleep); 587 if (err != 0) 588 return (EBUSY); 589 err = smi_write_locked(sc, addr, data, sleep); 590 smi_release(sc, sleep); 591 DEVERR(dev, err, "smi_write()=%d: addr=%04x\n", addr); 592 return (err == 0 ? 0 : EIO); 593 } 594 595 static int 596 smi_rmw(device_t dev, uint16_t addr, uint16_t mask, uint16_t data, int sleep) 597 { 598 struct rtl8366rb_softc *sc; 599 int err; 600 uint16_t oldv, newv; 601 602 sc = device_get_softc(dev); 603 604 err = smi_acquire(sc, sleep); 605 if (err != 0) 606 return (EBUSY); 607 if (err == 0) { 608 err = smi_read_locked(sc, addr, &oldv, sleep); 609 if (err == 0) { 610 newv = oldv & ~mask; 611 newv |= data & mask; 612 if (newv != oldv) 613 err = smi_write_locked(sc, addr, newv, sleep); 614 } 615 } 616 smi_release(sc, sleep); 617 DEVERR(dev, err, "smi_rmw()=%d: addr=%04x\n", addr); 618 return (err == 0 ? 0 : EIO); 619 } 620 621 static etherswitch_info_t * 622 rtl_getinfo(device_t dev) 623 { 624 struct rtl8366rb_softc *sc; 625 626 sc = device_get_softc(dev); 627 628 return (&sc->info); 629 } 630 631 static int 632 rtl_readreg(device_t dev, int reg) 633 { 634 uint16_t data; 635 636 data = 0; 637 638 smi_read(dev, reg, &data, RTL_WAITOK); 639 return (data); 640 } 641 642 static int 643 rtl_writereg(device_t dev, int reg, int value) 644 { 645 return (smi_write(dev, reg, value, RTL_WAITOK)); 646 } 647 648 static int 649 rtl_getport(device_t dev, etherswitch_port_t *p) 650 { 651 struct rtl8366rb_softc *sc; 652 struct ifmedia *ifm; 653 struct mii_data *mii; 654 struct ifmediareq *ifmr; 655 uint16_t v; 656 int err, vlangroup; 657 658 sc = device_get_softc(dev); 659 660 ifmr = &p->es_ifmr; 661 662 if (p->es_port < 0 || p->es_port >= (sc->numphys + 1)) 663 return (ENXIO); 664 if (sc->phy4cpu && p->es_port == sc->numphys) { 665 vlangroup = RTL8366_PVCR_GET(p->es_port + 1, 666 rtl_readreg(dev, RTL8366_PVCR_REG(p->es_port + 1))); 667 } else { 668 vlangroup = RTL8366_PVCR_GET(p->es_port, 669 rtl_readreg(dev, RTL8366_PVCR_REG(p->es_port))); 670 } 671 p->es_pvid = sc->vid[vlangroup] & ETHERSWITCH_VID_MASK; 672 673 if (p->es_port < sc->numphys) { 674 mii = device_get_softc(sc->miibus[p->es_port]); 675 ifm = &mii->mii_media; 676 err = ifmedia_ioctl(sc->ifp[p->es_port], &p->es_ifr, ifm, SIOCGIFMEDIA); 677 if (err) 678 return (err); 679 } else { 680 /* fill in fixed values for CPU port */ 681 p->es_flags |= ETHERSWITCH_PORT_CPU; 682 smi_read(dev, RTL8366_PLSR_BASE + (RTL8366_NUM_PHYS)/2, &v, RTL_WAITOK); 683 v = v >> (8 * ((RTL8366_NUM_PHYS) % 2)); 684 rtl8366rb_update_ifmedia(v, &ifmr->ifm_status, &ifmr->ifm_active); 685 ifmr->ifm_current = ifmr->ifm_active; 686 ifmr->ifm_mask = 0; 687 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 688 /* Return our static media list. */ 689 if (ifmr->ifm_count > 0) { 690 ifmr->ifm_count = 1; 691 ifmr->ifm_ulist[0] = IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 692 IFM_FDX, 0); 693 } else 694 ifmr->ifm_count = 0; 695 } 696 return (0); 697 } 698 699 static int 700 rtl_setport(device_t dev, etherswitch_port_t *p) 701 { 702 struct rtl8366rb_softc *sc; 703 int i, err, vlangroup; 704 struct ifmedia *ifm; 705 struct mii_data *mii; 706 int port; 707 708 sc = device_get_softc(dev); 709 710 if (p->es_port < 0 || p->es_port >= (sc->numphys + 1)) 711 return (ENXIO); 712 vlangroup = -1; 713 for (i = 0; i < RTL8366_NUM_VLANS; i++) { 714 if ((sc->vid[i] & ETHERSWITCH_VID_MASK) == p->es_pvid) { 715 vlangroup = i; 716 break; 717 } 718 } 719 if (vlangroup == -1) 720 return (ENXIO); 721 if (sc->phy4cpu && p->es_port == sc->numphys) { 722 port = p->es_port + 1; 723 } else { 724 port = p->es_port; 725 } 726 err = smi_rmw(dev, RTL8366_PVCR_REG(port), 727 RTL8366_PVCR_VAL(port, RTL8366_PVCR_PORT_MASK), 728 RTL8366_PVCR_VAL(port, vlangroup), RTL_WAITOK); 729 if (err) 730 return (err); 731 /* CPU Port */ 732 if (p->es_port == sc->numphys) 733 return (0); 734 mii = device_get_softc(sc->miibus[p->es_port]); 735 ifm = &mii->mii_media; 736 err = ifmedia_ioctl(sc->ifp[p->es_port], &p->es_ifr, ifm, SIOCSIFMEDIA); 737 return (err); 738 } 739 740 static int 741 rtl_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 742 { 743 struct rtl8366rb_softc *sc; 744 uint16_t vmcr[3]; 745 int i; 746 int member, untagged; 747 748 sc = device_get_softc(dev); 749 750 for (i=0; i<RTL8366_VMCR_MULT; i++) 751 vmcr[i] = rtl_readreg(dev, RTL8366_VMCR(i, vg->es_vlangroup)); 752 753 vg->es_vid = sc->vid[vg->es_vlangroup]; 754 member = RTL8366_VMCR_MEMBER(vmcr); 755 untagged = RTL8366_VMCR_UNTAG(vmcr); 756 if (sc->phy4cpu) { 757 vg->es_member_ports = ((member & 0x20) >> 1) | (member & 0x0f); 758 vg->es_untagged_ports = ((untagged & 0x20) >> 1) | (untagged & 0x0f); 759 } else { 760 vg->es_member_ports = member; 761 vg->es_untagged_ports = untagged; 762 } 763 vg->es_fid = RTL8366_VMCR_FID(vmcr); 764 return (0); 765 } 766 767 static int 768 rtl_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 769 { 770 struct rtl8366rb_softc *sc; 771 int g; 772 int member, untagged; 773 774 sc = device_get_softc(dev); 775 776 g = vg->es_vlangroup; 777 778 sc->vid[g] = vg->es_vid; 779 /* VLAN group disabled ? */ 780 if (vg->es_member_ports == 0 && vg->es_untagged_ports == 0 && vg->es_vid == 0) 781 return (0); 782 sc->vid[g] |= ETHERSWITCH_VID_VALID; 783 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_DOT1Q_REG, g), 784 (vg->es_vid << RTL8366_VMCR_DOT1Q_VID_SHIFT) & RTL8366_VMCR_DOT1Q_VID_MASK); 785 if (sc->phy4cpu) { 786 /* add space at phy4 */ 787 member = (vg->es_member_ports & 0x0f) | 788 ((vg->es_member_ports & 0x10) << 1); 789 untagged = (vg->es_untagged_ports & 0x0f) | 790 ((vg->es_untagged_ports & 0x10) << 1); 791 } else { 792 member = vg->es_member_ports; 793 untagged = vg->es_untagged_ports; 794 } 795 if (sc->chip_type == RTL8366RB) { 796 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, g), 797 ((member << RTL8366_VMCR_MU_MEMBER_SHIFT) & RTL8366_VMCR_MU_MEMBER_MASK) | 798 ((untagged << RTL8366_VMCR_MU_UNTAG_SHIFT) & RTL8366_VMCR_MU_UNTAG_MASK)); 799 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_FID_REG, g), 800 vg->es_fid); 801 } else { 802 rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, g), 803 ((member << RTL8366_VMCR_MU_MEMBER_SHIFT) & RTL8366_VMCR_MU_MEMBER_MASK) | 804 ((untagged << RTL8366_VMCR_MU_UNTAG_SHIFT) & RTL8366_VMCR_MU_UNTAG_MASK) | 805 ((vg->es_fid << RTL8366_VMCR_FID_FID_SHIFT) & RTL8366_VMCR_FID_FID_MASK)); 806 } 807 return (0); 808 } 809 810 static int 811 rtl_getconf(device_t dev, etherswitch_conf_t *conf) 812 { 813 814 /* Return the VLAN mode. */ 815 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 816 conf->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 817 818 return (0); 819 } 820 821 static int 822 rtl_readphy(device_t dev, int phy, int reg) 823 { 824 struct rtl8366rb_softc *sc; 825 uint16_t data; 826 int err, i, sleep; 827 828 sc = device_get_softc(dev); 829 830 data = 0; 831 832 if (phy < 0 || phy >= RTL8366_NUM_PHYS) 833 return (ENXIO); 834 if (reg < 0 || reg >= RTL8366_NUM_PHY_REG) 835 return (ENXIO); 836 sleep = RTL_WAITOK; 837 err = smi_acquire(sc, sleep); 838 if (err != 0) 839 return (EBUSY); 840 for (i = RTL_IICBUS_RETRIES; i--; ) { 841 err = smi_write_locked(sc, RTL8366_PACR, RTL8366_PACR_READ, sleep); 842 if (err == 0) 843 err = smi_write_locked(sc, RTL8366_PHYREG(phy, 0, reg), 0, sleep); 844 if (err == 0) { 845 err = smi_read_locked(sc, RTL8366_PADR, &data, sleep); 846 break; 847 } 848 DEBUG_INCRVAR(phy_access_retries); 849 DPRINTF(dev, "rtl_readphy(): chip not responsive, retrying %d more times\n", i); 850 pause("rtl_readphy", RTL_IICBUS_RETRY_SLEEP); 851 } 852 smi_release(sc, sleep); 853 DEVERR(dev, err, "rtl_readphy()=%d: phy=%d.%02x\n", phy, reg); 854 return (data); 855 } 856 857 static int 858 rtl_writephy(device_t dev, int phy, int reg, int data) 859 { 860 struct rtl8366rb_softc *sc; 861 int err, i, sleep; 862 863 sc = device_get_softc(dev); 864 865 if (phy < 0 || phy >= RTL8366_NUM_PHYS) 866 return (ENXIO); 867 if (reg < 0 || reg >= RTL8366_NUM_PHY_REG) 868 return (ENXIO); 869 sleep = RTL_WAITOK; 870 err = smi_acquire(sc, sleep); 871 if (err != 0) 872 return (EBUSY); 873 for (i = RTL_IICBUS_RETRIES; i--; ) { 874 err = smi_write_locked(sc, RTL8366_PACR, RTL8366_PACR_WRITE, sleep); 875 if (err == 0) 876 err = smi_write_locked(sc, RTL8366_PHYREG(phy, 0, reg), data, sleep); 877 if (err == 0) { 878 break; 879 } 880 DEBUG_INCRVAR(phy_access_retries); 881 DPRINTF(dev, "rtl_writephy(): chip not responsive, retrying %d more tiems\n", i); 882 pause("rtl_writephy", RTL_IICBUS_RETRY_SLEEP); 883 } 884 smi_release(sc, sleep); 885 DEVERR(dev, err, "rtl_writephy()=%d: phy=%d.%02x\n", phy, reg); 886 return (err == 0 ? 0 : EIO); 887 } 888 889 static int 890 rtl8366rb_ifmedia_upd(if_t ifp) 891 { 892 struct rtl8366rb_softc *sc; 893 struct mii_data *mii; 894 895 sc = if_getsoftc(ifp); 896 mii = device_get_softc(sc->miibus[if_getdunit(ifp)]); 897 898 mii_mediachg(mii); 899 return (0); 900 } 901 902 static void 903 rtl8366rb_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 904 { 905 struct rtl8366rb_softc *sc; 906 struct mii_data *mii; 907 908 sc = if_getsoftc(ifp); 909 mii = device_get_softc(sc->miibus[if_getdunit(ifp)]); 910 911 mii_pollstat(mii); 912 ifmr->ifm_active = mii->mii_media_active; 913 ifmr->ifm_status = mii->mii_media_status; 914 } 915 916 917 static device_method_t rtl8366rb_methods[] = { 918 /* Device interface */ 919 DEVMETHOD(device_identify, rtl8366rb_identify), 920 DEVMETHOD(device_probe, rtl8366rb_probe), 921 DEVMETHOD(device_attach, rtl8366rb_attach), 922 DEVMETHOD(device_detach, rtl8366rb_detach), 923 924 /* bus interface */ 925 DEVMETHOD(bus_add_child, device_add_child_ordered), 926 927 /* MII interface */ 928 DEVMETHOD(miibus_readreg, rtl_readphy), 929 DEVMETHOD(miibus_writereg, rtl_writephy), 930 931 /* MDIO interface */ 932 DEVMETHOD(mdio_readreg, rtl_readphy), 933 DEVMETHOD(mdio_writereg, rtl_writephy), 934 935 /* etherswitch interface */ 936 DEVMETHOD(etherswitch_getconf, rtl_getconf), 937 DEVMETHOD(etherswitch_getinfo, rtl_getinfo), 938 DEVMETHOD(etherswitch_readreg, rtl_readreg), 939 DEVMETHOD(etherswitch_writereg, rtl_writereg), 940 DEVMETHOD(etherswitch_readphyreg, rtl_readphy), 941 DEVMETHOD(etherswitch_writephyreg, rtl_writephy), 942 DEVMETHOD(etherswitch_getport, rtl_getport), 943 DEVMETHOD(etherswitch_setport, rtl_setport), 944 DEVMETHOD(etherswitch_getvgroup, rtl_getvgroup), 945 DEVMETHOD(etherswitch_setvgroup, rtl_setvgroup), 946 947 DEVMETHOD_END 948 }; 949 950 DEFINE_CLASS_0(rtl8366rb, rtl8366rb_driver, rtl8366rb_methods, 951 sizeof(struct rtl8366rb_softc)); 952 953 DRIVER_MODULE(rtl8366rb, iicbus, rtl8366rb_driver, 0, 0); 954 DRIVER_MODULE(miibus, rtl8366rb, miibus_driver, 0, 0); 955 DRIVER_MODULE(mdio, rtl8366rb, mdio_driver, 0, 0); 956 DRIVER_MODULE(etherswitch, rtl8366rb, etherswitch_driver, 0, 0); 957 MODULE_VERSION(rtl8366rb, 1); 958 MODULE_DEPEND(rtl8366rb, iicbus, 1, 1, 1); /* XXX which versions? */ 959 MODULE_DEPEND(rtl8366rb, miibus, 1, 1, 1); /* XXX which versions? */ 960 MODULE_DEPEND(rtl8366rb, etherswitch, 1, 1, 1); /* XXX which versions? */ 961