1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
3 *
4 * This is a sparsely documented chip, the only viable documentation seems
5 * to be a patched up code drop from the vendor that appear in various
6 * GPL source trees.
7 *
8 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
10 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
11 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
12 * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
13 */
14
15 #include <linux/bitops.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_bridge.h>
18 #include <linux/if_vlan.h>
19 #include <linux/interrupt.h>
20 #include <linux/irqdomain.h>
21 #include <linux/irqchip/chained_irq.h>
22 #include <linux/of_irq.h>
23 #include <linux/regmap.h>
24 #include <linux/string_choices.h>
25
26 #include "realtek.h"
27 #include "realtek-smi.h"
28 #include "realtek-mdio.h"
29 #include "rtl83xx.h"
30 #include "rtl8366rb.h"
31
32 /* Switch Global Configuration register */
33 #define RTL8366RB_SGCR 0x0000
34 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
35 #define RTL8366RB_SGCR_MAX_LENGTH(a) ((a) << 4)
36 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
38 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
39 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
40 #define RTL8366RB_SGCR_MAX_LENGTH_16000 RTL8366RB_SGCR_MAX_LENGTH(0x3)
41 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
42 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
43
44 /* Port Enable Control register */
45 #define RTL8366RB_PECR 0x0001
46
47 /* Switch per-port learning disablement register */
48 #define RTL8366RB_PORT_LEARNDIS_CTRL 0x0002
49
50 /* Security control, actually aging register */
51 #define RTL8366RB_SECURITY_CTRL 0x0003
52
53 #define RTL8366RB_SSCR2 0x0004
54 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
55
56 /* Port Mode Control registers */
57 #define RTL8366RB_PMC0 0x0005
58 #define RTL8366RB_PMC0_SPI BIT(0)
59 #define RTL8366RB_PMC0_EN_AUTOLOAD BIT(1)
60 #define RTL8366RB_PMC0_PROBE BIT(2)
61 #define RTL8366RB_PMC0_DIS_BISR BIT(3)
62 #define RTL8366RB_PMC0_ADCTEST BIT(4)
63 #define RTL8366RB_PMC0_SRAM_DIAG BIT(5)
64 #define RTL8366RB_PMC0_EN_SCAN BIT(6)
65 #define RTL8366RB_PMC0_P4_IOMODE_SHIFT 7
66 #define RTL8366RB_PMC0_P4_IOMODE_MASK GENMASK(9, 7)
67 #define RTL8366RB_PMC0_P5_IOMODE_SHIFT 10
68 #define RTL8366RB_PMC0_P5_IOMODE_MASK GENMASK(12, 10)
69 #define RTL8366RB_PMC0_SDSMODE_SHIFT 13
70 #define RTL8366RB_PMC0_SDSMODE_MASK GENMASK(15, 13)
71 #define RTL8366RB_PMC1 0x0006
72
73 /* Port Mirror Control Register */
74 #define RTL8366RB_PMCR 0x0007
75 #define RTL8366RB_PMCR_SOURCE_PORT(a) (a)
76 #define RTL8366RB_PMCR_SOURCE_PORT_MASK 0x000f
77 #define RTL8366RB_PMCR_MONITOR_PORT(a) ((a) << 4)
78 #define RTL8366RB_PMCR_MONITOR_PORT_MASK 0x00f0
79 #define RTL8366RB_PMCR_MIRROR_RX BIT(8)
80 #define RTL8366RB_PMCR_MIRROR_TX BIT(9)
81 #define RTL8366RB_PMCR_MIRROR_SPC BIT(10)
82 #define RTL8366RB_PMCR_MIRROR_ISO BIT(11)
83
84 /* bits 0..7 = port 0, bits 8..15 = port 1 */
85 #define RTL8366RB_PAACR0 0x0010
86 /* bits 0..7 = port 2, bits 8..15 = port 3 */
87 #define RTL8366RB_PAACR1 0x0011
88 /* bits 0..7 = port 4, bits 8..15 = port 5 */
89 #define RTL8366RB_PAACR2 0x0012
90 #define RTL8366RB_PAACR_SPEED_10M 0
91 #define RTL8366RB_PAACR_SPEED_100M 1
92 #define RTL8366RB_PAACR_SPEED_1000M 2
93 #define RTL8366RB_PAACR_FULL_DUPLEX BIT(2)
94 #define RTL8366RB_PAACR_LINK_UP BIT(4)
95 #define RTL8366RB_PAACR_TX_PAUSE BIT(5)
96 #define RTL8366RB_PAACR_RX_PAUSE BIT(6)
97 #define RTL8366RB_PAACR_AN BIT(7)
98
99 /* bits 0..7 = port 0, bits 8..15 = port 1 */
100 #define RTL8366RB_PSTAT0 0x0014
101 /* bits 0..7 = port 2, bits 8..15 = port 3 */
102 #define RTL8366RB_PSTAT1 0x0015
103 /* bits 0..7 = port 4, bits 8..15 = port 5 */
104 #define RTL8366RB_PSTAT2 0x0016
105
106 #define RTL8366RB_POWER_SAVING_REG 0x0021
107
108 /* Spanning tree status (STP) control, two bits per port per FID */
109 #define RTL8366RB_STP_STATE_BASE 0x0050 /* 0x0050..0x0057 */
110 #define RTL8366RB_STP_STATE_DISABLED 0x0
111 #define RTL8366RB_STP_STATE_BLOCKING 0x1
112 #define RTL8366RB_STP_STATE_LEARNING 0x2
113 #define RTL8366RB_STP_STATE_FORWARDING 0x3
114 #define RTL8366RB_STP_MASK GENMASK(1, 0)
115 #define RTL8366RB_STP_STATE(port, state) \
116 ((state) << ((port) * 2))
117 #define RTL8366RB_STP_STATE_MASK(port) \
118 RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK)
119
120 /* CPU port control reg */
121 #define RTL8366RB_CPU_CTRL_REG 0x0061
122 #define RTL8366RB_CPU_PORTS_MSK 0x00FF
123 /* Disables inserting custom tag length/type 0x8899 */
124 #define RTL8366RB_CPU_NO_TAG BIT(15)
125 #define RTL8366RB_CPU_TAG_SIZE 4
126
127 #define RTL8366RB_SMAR0 0x0070 /* bits 0..15 */
128 #define RTL8366RB_SMAR1 0x0071 /* bits 16..31 */
129 #define RTL8366RB_SMAR2 0x0072 /* bits 32..47 */
130
131 #define RTL8366RB_RESET_CTRL_REG 0x0100
132 #define RTL8366RB_CHIP_CTRL_RESET_HW BIT(0)
133 #define RTL8366RB_CHIP_CTRL_RESET_SW BIT(1)
134
135 #define RTL8366RB_CHIP_ID_REG 0x0509
136 #define RTL8366RB_CHIP_ID_8366 0x5937
137 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
138 #define RTL8366RB_CHIP_VERSION_MASK 0xf
139
140 /* PHY registers control */
141 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
142 #define RTL8366RB_PHY_CTRL_READ BIT(0)
143 #define RTL8366RB_PHY_CTRL_WRITE 0
144 #define RTL8366RB_PHY_ACCESS_BUSY_REG 0x8001
145 #define RTL8366RB_PHY_INT_BUSY BIT(0)
146 #define RTL8366RB_PHY_EXT_BUSY BIT(4)
147 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
148 #define RTL8366RB_PHY_EXT_CTRL_REG 0x8010
149 #define RTL8366RB_PHY_EXT_WRDATA_REG 0x8011
150 #define RTL8366RB_PHY_EXT_RDDATA_REG 0x8012
151
152 #define RTL8366RB_PHY_REG_MASK 0x1f
153 #define RTL8366RB_PHY_PAGE_OFFSET 5
154 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
155 #define RTL8366RB_PHY_NO_OFFSET 9
156 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
157
158 /* VLAN Ingress Control Register 1, one bit per port.
159 * bit 0 .. 5 will make the switch drop ingress frames without
160 * VID such as untagged or priority-tagged frames for respective
161 * port.
162 * bit 6 .. 11 will make the switch drop ingress frames carrying
163 * a C-tag with VID != 0 for respective port.
164 */
165 #define RTL8366RB_VLAN_INGRESS_CTRL1_REG 0x037E
166 #define RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) (BIT((port)) | BIT((port) + 6))
167
168 /* VLAN Ingress Control Register 2, one bit per port.
169 * bit0 .. bit5 will make the switch drop all ingress frames with
170 * a VLAN classification that does not include the port is in its
171 * member set.
172 */
173 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
174
175 #define RTL8366RB_MIB_COUNT 33
176 #define RTL8366RB_GLOBAL_MIB_COUNT 1
177 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
178 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
179 #define RTL8366RB_MIB_CTRL_REG 0x13F0
180 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
181 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
182 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
183 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
184 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
185
186 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
187 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
188 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
189 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
190 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
191
192 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
193 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
194
195 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
196 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
197 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
198
199 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
200
201 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
202 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
203 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
204 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
205 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
206 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
207 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
208
209 #define RTL8366RB_NUM_VLANS 16
210 #define RTL8366RB_NUM_VIDS 4096
211 #define RTL8366RB_PRIORITYMAX 7
212 #define RTL8366RB_NUM_FIDS 8
213 #define RTL8366RB_FIDMAX 7
214
215 #define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */
216 #define RTL8366RB_PORT_2 BIT(1) /* In userspace port 1 */
217 #define RTL8366RB_PORT_3 BIT(2) /* In userspace port 2 */
218 #define RTL8366RB_PORT_4 BIT(3) /* In userspace port 3 */
219 #define RTL8366RB_PORT_5 BIT(4) /* In userspace port 4 */
220
221 #define RTL8366RB_PORT_CPU BIT(5) /* CPU port */
222
223 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
224 RTL8366RB_PORT_2 | \
225 RTL8366RB_PORT_3 | \
226 RTL8366RB_PORT_4 | \
227 RTL8366RB_PORT_5 | \
228 RTL8366RB_PORT_CPU)
229
230 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
231 RTL8366RB_PORT_2 | \
232 RTL8366RB_PORT_3 | \
233 RTL8366RB_PORT_4 | \
234 RTL8366RB_PORT_5)
235
236 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
237 RTL8366RB_PORT_2 | \
238 RTL8366RB_PORT_3 | \
239 RTL8366RB_PORT_4)
240
241 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
242
243 /* First configuration word per member config, VID and prio */
244 #define RTL8366RB_VLAN_VID_MASK 0xfff
245 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12
246 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7
247 /* Second configuration word per member config, member and untagged */
248 #define RTL8366RB_VLAN_UNTAG_SHIFT 8
249 #define RTL8366RB_VLAN_UNTAG_MASK 0xff
250 #define RTL8366RB_VLAN_MEMBER_MASK 0xff
251 /* Third config word per member config, STAG currently unused */
252 #define RTL8366RB_VLAN_STAG_MBR_MASK 0xff
253 #define RTL8366RB_VLAN_STAG_MBR_SHIFT 8
254 #define RTL8366RB_VLAN_STAG_IDX_MASK 0x7
255 #define RTL8366RB_VLAN_STAG_IDX_SHIFT 5
256 #define RTL8366RB_VLAN_FID_MASK 0x7
257
258 /* Port ingress bandwidth control */
259 #define RTL8366RB_IB_BASE 0x0200
260 #define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + (pnum))
261 #define RTL8366RB_IB_BDTH_MASK 0x3fff
262 #define RTL8366RB_IB_PREIFG BIT(14)
263
264 /* Port egress bandwidth control */
265 #define RTL8366RB_EB_BASE 0x02d1
266 #define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + (pnum))
267 #define RTL8366RB_EB_BDTH_MASK 0x3fff
268 #define RTL8366RB_EB_PREIFG_REG 0x02f8
269 #define RTL8366RB_EB_PREIFG BIT(9)
270
271 #define RTL8366RB_BDTH_SW_MAX 1048512 /* 1048576? */
272 #define RTL8366RB_BDTH_UNIT 64
273 #define RTL8366RB_BDTH_REG_DEFAULT 16383
274
275 /* QOS */
276 #define RTL8366RB_QOS BIT(15)
277 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
278 #define RTL8366RB_QOS_DEFAULT_PREIFG 1
279
280 /* Interrupt handling */
281 #define RTL8366RB_INTERRUPT_CONTROL_REG 0x0440
282 #define RTL8366RB_INTERRUPT_POLARITY BIT(0)
283 #define RTL8366RB_P4_RGMII_LED BIT(2)
284 #define RTL8366RB_INTERRUPT_MASK_REG 0x0441
285 #define RTL8366RB_INTERRUPT_LINK_CHGALL GENMASK(11, 0)
286 #define RTL8366RB_INTERRUPT_ACLEXCEED BIT(8)
287 #define RTL8366RB_INTERRUPT_STORMEXCEED BIT(9)
288 #define RTL8366RB_INTERRUPT_P4_FIBER BIT(12)
289 #define RTL8366RB_INTERRUPT_P4_UTP BIT(13)
290 #define RTL8366RB_INTERRUPT_VALID (RTL8366RB_INTERRUPT_LINK_CHGALL | \
291 RTL8366RB_INTERRUPT_ACLEXCEED | \
292 RTL8366RB_INTERRUPT_STORMEXCEED | \
293 RTL8366RB_INTERRUPT_P4_FIBER | \
294 RTL8366RB_INTERRUPT_P4_UTP)
295 #define RTL8366RB_INTERRUPT_STATUS_REG 0x0442
296 #define RTL8366RB_NUM_INTERRUPT 14 /* 0..13 */
297
298 /* Port isolation registers */
299 #define RTL8366RB_PORT_ISO_BASE 0x0F08
300 #define RTL8366RB_PORT_ISO(pnum) (RTL8366RB_PORT_ISO_BASE + (pnum))
301 #define RTL8366RB_PORT_ISO_EN BIT(0)
302 #define RTL8366RB_PORT_ISO_PORTS_MASK GENMASK(7, 1)
303 #define RTL8366RB_PORT_ISO_PORTS(pmask) ((pmask) << 1)
304
305 /* bits 0..5 enable force when cleared */
306 #define RTL8366RB_MAC_FORCE_CTRL_REG 0x0F11
307
308 #define RTL8366RB_OAM_PARSER_REG 0x0F14
309 #define RTL8366RB_OAM_MULTIPLEXER_REG 0x0F15
310
311 #define RTL8366RB_GREEN_FEATURE_REG 0x0F51
312 #define RTL8366RB_GREEN_FEATURE_MSK 0x0007
313 #define RTL8366RB_GREEN_FEATURE_TX BIT(0)
314 #define RTL8366RB_GREEN_FEATURE_RX BIT(2)
315
316 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
317 { 0, 0, 4, "IfInOctets" },
318 { 0, 4, 4, "EtherStatsOctets" },
319 { 0, 8, 2, "EtherStatsUnderSizePkts" },
320 { 0, 10, 2, "EtherFragments" },
321 { 0, 12, 2, "EtherStatsPkts64Octets" },
322 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
323 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
324 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
325 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
326 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
327 { 0, 24, 2, "EtherOversizeStats" },
328 { 0, 26, 2, "EtherStatsJabbers" },
329 { 0, 28, 2, "IfInUcastPkts" },
330 { 0, 30, 2, "EtherStatsMulticastPkts" },
331 { 0, 32, 2, "EtherStatsBroadcastPkts" },
332 { 0, 34, 2, "EtherStatsDropEvents" },
333 { 0, 36, 2, "Dot3StatsFCSErrors" },
334 { 0, 38, 2, "Dot3StatsSymbolErrors" },
335 { 0, 40, 2, "Dot3InPauseFrames" },
336 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
337 { 0, 44, 4, "IfOutOctets" },
338 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
339 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
340 { 0, 52, 2, "Dot3sDeferredTransmissions" },
341 { 0, 54, 2, "Dot3StatsLateCollisions" },
342 { 0, 56, 2, "EtherStatsCollisions" },
343 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
344 { 0, 60, 2, "Dot3OutPauseFrames" },
345 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
346 { 0, 64, 2, "Dot1dTpPortInDiscards" },
347 { 0, 66, 2, "IfOutUcastPkts" },
348 { 0, 68, 2, "IfOutMulticastPkts" },
349 { 0, 70, 2, "IfOutBroadcastPkts" },
350 };
351
rtl8366rb_get_mib_counter(struct realtek_priv * priv,int port,struct rtl8366_mib_counter * mib,u64 * mibvalue)352 static int rtl8366rb_get_mib_counter(struct realtek_priv *priv,
353 int port,
354 struct rtl8366_mib_counter *mib,
355 u64 *mibvalue)
356 {
357 u32 addr, val;
358 int ret;
359 int i;
360
361 addr = RTL8366RB_MIB_COUNTER_BASE +
362 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
363 mib->offset;
364
365 /* Writing access counter address first
366 * then ASIC will prepare 64bits counter wait for being retrived
367 */
368 ret = regmap_write(priv->map, addr, 0); /* Write whatever */
369 if (ret)
370 return ret;
371
372 /* Read MIB control register */
373 ret = regmap_read(priv->map, RTL8366RB_MIB_CTRL_REG, &val);
374 if (ret)
375 return -EIO;
376
377 if (val & RTL8366RB_MIB_CTRL_BUSY_MASK)
378 return -EBUSY;
379
380 if (val & RTL8366RB_MIB_CTRL_RESET_MASK)
381 return -EIO;
382
383 /* Read each individual MIB 16 bits at the time */
384 *mibvalue = 0;
385 for (i = mib->length; i > 0; i--) {
386 ret = regmap_read(priv->map, addr + (i - 1), &val);
387 if (ret)
388 return ret;
389 *mibvalue = (*mibvalue << 16) | (val & 0xFFFF);
390 }
391 return 0;
392 }
393
rtl8366rb_get_irqmask(struct irq_data * d)394 static u32 rtl8366rb_get_irqmask(struct irq_data *d)
395 {
396 int line = irqd_to_hwirq(d);
397 u32 val;
398
399 /* For line interrupts we combine link down in bits
400 * 6..11 with link up in bits 0..5 into one interrupt.
401 */
402 if (line < 12)
403 val = BIT(line) | BIT(line + 6);
404 else
405 val = BIT(line);
406 return val;
407 }
408
rtl8366rb_mask_irq(struct irq_data * d)409 static void rtl8366rb_mask_irq(struct irq_data *d)
410 {
411 struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
412 int ret;
413
414 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
415 rtl8366rb_get_irqmask(d), 0);
416 if (ret)
417 dev_err(priv->dev, "could not mask IRQ\n");
418 }
419
rtl8366rb_unmask_irq(struct irq_data * d)420 static void rtl8366rb_unmask_irq(struct irq_data *d)
421 {
422 struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
423 int ret;
424
425 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
426 rtl8366rb_get_irqmask(d),
427 rtl8366rb_get_irqmask(d));
428 if (ret)
429 dev_err(priv->dev, "could not unmask IRQ\n");
430 }
431
rtl8366rb_irq(int irq,void * data)432 static irqreturn_t rtl8366rb_irq(int irq, void *data)
433 {
434 struct realtek_priv *priv = data;
435 u32 stat;
436 int ret;
437
438 /* This clears the IRQ status register */
439 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
440 &stat);
441 if (ret) {
442 dev_err(priv->dev, "can't read interrupt status\n");
443 return IRQ_NONE;
444 }
445 stat &= RTL8366RB_INTERRUPT_VALID;
446 if (!stat)
447 return IRQ_NONE;
448 while (stat) {
449 int line = __ffs(stat);
450 int child_irq;
451
452 stat &= ~BIT(line);
453 /* For line interrupts we combine link down in bits
454 * 6..11 with link up in bits 0..5 into one interrupt.
455 */
456 if (line < 12 && line > 5)
457 line -= 5;
458 child_irq = irq_find_mapping(priv->irqdomain, line);
459 handle_nested_irq(child_irq);
460 }
461 return IRQ_HANDLED;
462 }
463
464 static struct irq_chip rtl8366rb_irq_chip = {
465 .name = "RTL8366RB",
466 .irq_mask = rtl8366rb_mask_irq,
467 .irq_unmask = rtl8366rb_unmask_irq,
468 };
469
rtl8366rb_irq_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)470 static int rtl8366rb_irq_map(struct irq_domain *domain, unsigned int irq,
471 irq_hw_number_t hwirq)
472 {
473 irq_set_chip_data(irq, domain->host_data);
474 irq_set_chip_and_handler(irq, &rtl8366rb_irq_chip, handle_simple_irq);
475 irq_set_nested_thread(irq, 1);
476 irq_set_noprobe(irq);
477
478 return 0;
479 }
480
rtl8366rb_irq_unmap(struct irq_domain * d,unsigned int irq)481 static void rtl8366rb_irq_unmap(struct irq_domain *d, unsigned int irq)
482 {
483 irq_set_nested_thread(irq, 0);
484 irq_set_chip_and_handler(irq, NULL, NULL);
485 irq_set_chip_data(irq, NULL);
486 }
487
488 static const struct irq_domain_ops rtl8366rb_irqdomain_ops = {
489 .map = rtl8366rb_irq_map,
490 .unmap = rtl8366rb_irq_unmap,
491 .xlate = irq_domain_xlate_onecell,
492 };
493
rtl8366rb_setup_cascaded_irq(struct realtek_priv * priv)494 static int rtl8366rb_setup_cascaded_irq(struct realtek_priv *priv)
495 {
496 struct device_node *intc;
497 unsigned long irq_trig;
498 int irq;
499 int ret;
500 u32 val;
501 int i;
502
503 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");
504 if (!intc) {
505 dev_err(priv->dev, "missing child interrupt-controller node\n");
506 return -EINVAL;
507 }
508 /* RB8366RB IRQs cascade off this one */
509 irq = of_irq_get(intc, 0);
510 if (irq <= 0) {
511 dev_err(priv->dev, "failed to get parent IRQ\n");
512 ret = irq ? irq : -EINVAL;
513 goto out_put_node;
514 }
515
516 /* This clears the IRQ status register */
517 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
518 &val);
519 if (ret) {
520 dev_err(priv->dev, "can't read interrupt status\n");
521 goto out_put_node;
522 }
523
524 /* Fetch IRQ edge information from the descriptor */
525 irq_trig = irq_get_trigger_type(irq);
526 switch (irq_trig) {
527 case IRQF_TRIGGER_RISING:
528 case IRQF_TRIGGER_HIGH:
529 dev_info(priv->dev, "active high/rising IRQ\n");
530 val = 0;
531 break;
532 case IRQF_TRIGGER_FALLING:
533 case IRQF_TRIGGER_LOW:
534 dev_info(priv->dev, "active low/falling IRQ\n");
535 val = RTL8366RB_INTERRUPT_POLARITY;
536 break;
537 }
538 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG,
539 RTL8366RB_INTERRUPT_POLARITY,
540 val);
541 if (ret) {
542 dev_err(priv->dev, "could not configure IRQ polarity\n");
543 goto out_put_node;
544 }
545
546 ret = devm_request_threaded_irq(priv->dev, irq, NULL,
547 rtl8366rb_irq, IRQF_ONESHOT,
548 "RTL8366RB", priv);
549 if (ret) {
550 dev_err(priv->dev, "unable to request irq: %d\n", ret);
551 goto out_put_node;
552 }
553 priv->irqdomain = irq_domain_create_linear(of_fwnode_handle(intc), RTL8366RB_NUM_INTERRUPT,
554 &rtl8366rb_irqdomain_ops, priv);
555 if (!priv->irqdomain) {
556 dev_err(priv->dev, "failed to create IRQ domain\n");
557 ret = -EINVAL;
558 goto out_put_node;
559 }
560 for (i = 0; i < priv->num_ports; i++)
561 irq_set_parent(irq_create_mapping(priv->irqdomain, i), irq);
562
563 out_put_node:
564 of_node_put(intc);
565 return ret;
566 }
567
rtl8366rb_set_addr(struct realtek_priv * priv)568 static int rtl8366rb_set_addr(struct realtek_priv *priv)
569 {
570 u8 addr[ETH_ALEN];
571 u16 val;
572 int ret;
573
574 eth_random_addr(addr);
575
576 dev_info(priv->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",
577 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
578 val = addr[0] << 8 | addr[1];
579 ret = regmap_write(priv->map, RTL8366RB_SMAR0, val);
580 if (ret)
581 return ret;
582 val = addr[2] << 8 | addr[3];
583 ret = regmap_write(priv->map, RTL8366RB_SMAR1, val);
584 if (ret)
585 return ret;
586 val = addr[4] << 8 | addr[5];
587 ret = regmap_write(priv->map, RTL8366RB_SMAR2, val);
588 if (ret)
589 return ret;
590
591 return 0;
592 }
593
594 /* Found in a vendor driver */
595
596 /* Struct for handling the jam tables' entries */
597 struct rtl8366rb_jam_tbl_entry {
598 u16 reg;
599 u16 val;
600 };
601
602 /* For the "version 0" early silicon, appear in most source releases */
603 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_0[] = {
604 {0x000B, 0x0001}, {0x03A6, 0x0100}, {0x03A7, 0x0001}, {0x02D1, 0x3FFF},
605 {0x02D2, 0x3FFF}, {0x02D3, 0x3FFF}, {0x02D4, 0x3FFF}, {0x02D5, 0x3FFF},
606 {0x02D6, 0x3FFF}, {0x02D7, 0x3FFF}, {0x02D8, 0x3FFF}, {0x022B, 0x0688},
607 {0x022C, 0x0FAC}, {0x03D0, 0x4688}, {0x03D1, 0x01F5}, {0x0000, 0x0830},
608 {0x02F9, 0x0200}, {0x02F7, 0x7FFF}, {0x02F8, 0x03FF}, {0x0080, 0x03E8},
609 {0x0081, 0x00CE}, {0x0082, 0x00DA}, {0x0083, 0x0230}, {0xBE0F, 0x2000},
610 {0x0231, 0x422A}, {0x0232, 0x422A}, {0x0233, 0x422A}, {0x0234, 0x422A},
611 {0x0235, 0x422A}, {0x0236, 0x422A}, {0x0237, 0x422A}, {0x0238, 0x422A},
612 {0x0239, 0x422A}, {0x023A, 0x422A}, {0x023B, 0x422A}, {0x023C, 0x422A},
613 {0x023D, 0x422A}, {0x023E, 0x422A}, {0x023F, 0x422A}, {0x0240, 0x422A},
614 {0x0241, 0x422A}, {0x0242, 0x422A}, {0x0243, 0x422A}, {0x0244, 0x422A},
615 {0x0245, 0x422A}, {0x0246, 0x422A}, {0x0247, 0x422A}, {0x0248, 0x422A},
616 {0x0249, 0x0146}, {0x024A, 0x0146}, {0x024B, 0x0146}, {0xBE03, 0xC961},
617 {0x024D, 0x0146}, {0x024E, 0x0146}, {0x024F, 0x0146}, {0x0250, 0x0146},
618 {0xBE64, 0x0226}, {0x0252, 0x0146}, {0x0253, 0x0146}, {0x024C, 0x0146},
619 {0x0251, 0x0146}, {0x0254, 0x0146}, {0xBE62, 0x3FD0}, {0x0084, 0x0320},
620 {0x0255, 0x0146}, {0x0256, 0x0146}, {0x0257, 0x0146}, {0x0258, 0x0146},
621 {0x0259, 0x0146}, {0x025A, 0x0146}, {0x025B, 0x0146}, {0x025C, 0x0146},
622 {0x025D, 0x0146}, {0x025E, 0x0146}, {0x025F, 0x0146}, {0x0260, 0x0146},
623 {0x0261, 0xA23F}, {0x0262, 0x0294}, {0x0263, 0xA23F}, {0x0264, 0x0294},
624 {0x0265, 0xA23F}, {0x0266, 0x0294}, {0x0267, 0xA23F}, {0x0268, 0x0294},
625 {0x0269, 0xA23F}, {0x026A, 0x0294}, {0x026B, 0xA23F}, {0x026C, 0x0294},
626 {0x026D, 0xA23F}, {0x026E, 0x0294}, {0x026F, 0xA23F}, {0x0270, 0x0294},
627 {0x02F5, 0x0048}, {0xBE09, 0x0E00}, {0xBE1E, 0x0FA0}, {0xBE14, 0x8448},
628 {0xBE15, 0x1007}, {0xBE4A, 0xA284}, {0xC454, 0x3F0B}, {0xC474, 0x3F0B},
629 {0xBE48, 0x3672}, {0xBE4B, 0x17A7}, {0xBE4C, 0x0B15}, {0xBE52, 0x0EDD},
630 {0xBE49, 0x8C00}, {0xBE5B, 0x785C}, {0xBE5C, 0x785C}, {0xBE5D, 0x785C},
631 {0xBE61, 0x368A}, {0xBE63, 0x9B84}, {0xC456, 0xCC13}, {0xC476, 0xCC13},
632 {0xBE65, 0x307D}, {0xBE6D, 0x0005}, {0xBE6E, 0xE120}, {0xBE2E, 0x7BAF},
633 };
634
635 /* This v1 init sequence is from Belkin F5D8235 U-Boot release */
636 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_1[] = {
637 {0x0000, 0x0830}, {0x0001, 0x8000}, {0x0400, 0x8130}, {0xBE78, 0x3C3C},
638 {0x0431, 0x5432}, {0xBE37, 0x0CE4}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
639 {0xC44C, 0x1585}, {0xC44C, 0x1185}, {0xC44C, 0x1585}, {0xC46C, 0x1585},
640 {0xC46C, 0x1185}, {0xC46C, 0x1585}, {0xC451, 0x2135}, {0xC471, 0x2135},
641 {0xBE10, 0x8140}, {0xBE15, 0x0007}, {0xBE6E, 0xE120}, {0xBE69, 0xD20F},
642 {0xBE6B, 0x0320}, {0xBE24, 0xB000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF20},
643 {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800}, {0xBE24, 0x0000},
644 {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60}, {0xBE21, 0x0140},
645 {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000}, {0xBE2E, 0x7B7A},
646 {0xBE36, 0x0CE4}, {0x02F5, 0x0048}, {0xBE77, 0x2940}, {0x000A, 0x83E0},
647 {0xBE79, 0x3C3C}, {0xBE00, 0x1340},
648 };
649
650 /* This v2 init sequence is from Belkin F5D8235 U-Boot release */
651 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_2[] = {
652 {0x0450, 0x0000}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
653 {0xC44F, 0x6250}, {0xC46F, 0x6250}, {0xC456, 0x0C14}, {0xC476, 0x0C14},
654 {0xC44C, 0x1C85}, {0xC44C, 0x1885}, {0xC44C, 0x1C85}, {0xC46C, 0x1C85},
655 {0xC46C, 0x1885}, {0xC46C, 0x1C85}, {0xC44C, 0x0885}, {0xC44C, 0x0881},
656 {0xC44C, 0x0885}, {0xC46C, 0x0885}, {0xC46C, 0x0881}, {0xC46C, 0x0885},
657 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
658 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6E, 0x0320},
659 {0xBE77, 0x2940}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
660 {0x8000, 0x0001}, {0xBE15, 0x1007}, {0x8000, 0x0000}, {0xBE15, 0x1007},
661 {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160}, {0xBE10, 0x8140},
662 {0xBE00, 0x1340}, {0x0F51, 0x0010},
663 };
664
665 /* Appears in a DDWRT code dump */
666 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_3[] = {
667 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
668 {0x0F51, 0x0017}, {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
669 {0xC456, 0x0C14}, {0xC476, 0x0C14}, {0xC454, 0x3F8B}, {0xC474, 0x3F8B},
670 {0xC450, 0x2071}, {0xC470, 0x2071}, {0xC451, 0x226B}, {0xC471, 0x226B},
671 {0xC452, 0xA293}, {0xC472, 0xA293}, {0xC44C, 0x1585}, {0xC44C, 0x1185},
672 {0xC44C, 0x1585}, {0xC46C, 0x1585}, {0xC46C, 0x1185}, {0xC46C, 0x1585},
673 {0xC44C, 0x0185}, {0xC44C, 0x0181}, {0xC44C, 0x0185}, {0xC46C, 0x0185},
674 {0xC46C, 0x0181}, {0xC46C, 0x0185}, {0xBE24, 0xB000}, {0xBE23, 0xFF51},
675 {0xBE22, 0xDF20}, {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800},
676 {0xBE24, 0x0000}, {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60},
677 {0xBE21, 0x0140}, {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000},
678 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
679 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6B, 0x0320},
680 {0xBE77, 0x2800}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
681 {0x8000, 0x0001}, {0xBE10, 0x8140}, {0x8000, 0x0000}, {0xBE10, 0x8140},
682 {0xBE15, 0x1007}, {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160},
683 {0xBE10, 0x8140}, {0xBE00, 0x1340}, {0x0450, 0x0000}, {0x0401, 0x0000},
684 };
685
686 /* Belkin F5D8235 v1, "belkin,f5d8235-v1" */
687 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_f5d8235[] = {
688 {0x0242, 0x02BF}, {0x0245, 0x02BF}, {0x0248, 0x02BF}, {0x024B, 0x02BF},
689 {0x024E, 0x02BF}, {0x0251, 0x02BF}, {0x0254, 0x0A3F}, {0x0256, 0x0A3F},
690 {0x0258, 0x0A3F}, {0x025A, 0x0A3F}, {0x025C, 0x0A3F}, {0x025E, 0x0A3F},
691 {0x0263, 0x007C}, {0x0100, 0x0004}, {0xBE5B, 0x3500}, {0x800E, 0x200F},
692 {0xBE1D, 0x0F00}, {0x8001, 0x5011}, {0x800A, 0xA2F4}, {0x800B, 0x17A3},
693 {0xBE4B, 0x17A3}, {0xBE41, 0x5011}, {0xBE17, 0x2100}, {0x8000, 0x8304},
694 {0xBE40, 0x8304}, {0xBE4A, 0xA2F4}, {0x800C, 0xA8D5}, {0x8014, 0x5500},
695 {0x8015, 0x0004}, {0xBE4C, 0xA8D5}, {0xBE59, 0x0008}, {0xBE09, 0x0E00},
696 {0xBE36, 0x1036}, {0xBE37, 0x1036}, {0x800D, 0x00FF}, {0xBE4D, 0x00FF},
697 };
698
699 /* DGN3500, "netgear,dgn3500", "netgear,dgn3500b" */
700 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_dgn3500[] = {
701 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0F51, 0x0017},
702 {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, {0x0450, 0x0000},
703 {0x0401, 0x0000}, {0x0431, 0x0960},
704 };
705
706 /* This jam table activates "green ethernet", which means low power mode
707 * and is claimed to detect the cable length and not use more power than
708 * necessary, and the ports should enter power saving mode 10 seconds after
709 * a cable is disconnected. Seems to always be the same.
710 */
711 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_green_jam[] = {
712 {0xBE78, 0x323C}, {0xBE77, 0x5000}, {0xBE2E, 0x7BA7},
713 {0xBE59, 0x3459}, {0xBE5A, 0x745A}, {0xBE5B, 0x785C},
714 {0xBE5C, 0x785C}, {0xBE6E, 0xE120}, {0xBE79, 0x323C},
715 };
716
717 /* Function that jams the tables in the proper registers */
rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry * jam_table,int jam_size,struct realtek_priv * priv,bool write_dbg)718 static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table,
719 int jam_size, struct realtek_priv *priv,
720 bool write_dbg)
721 {
722 u32 val;
723 int ret;
724 int i;
725
726 for (i = 0; i < jam_size; i++) {
727 if ((jam_table[i].reg & 0xBE00) == 0xBE00) {
728 ret = regmap_read(priv->map,
729 RTL8366RB_PHY_ACCESS_BUSY_REG,
730 &val);
731 if (ret)
732 return ret;
733 if (!(val & RTL8366RB_PHY_INT_BUSY)) {
734 ret = regmap_write(priv->map,
735 RTL8366RB_PHY_ACCESS_CTRL_REG,
736 RTL8366RB_PHY_CTRL_WRITE);
737 if (ret)
738 return ret;
739 }
740 }
741 if (write_dbg)
742 dev_dbg(priv->dev, "jam %04x into register %04x\n",
743 jam_table[i].val,
744 jam_table[i].reg);
745 ret = regmap_write(priv->map,
746 jam_table[i].reg,
747 jam_table[i].val);
748 if (ret)
749 return ret;
750 }
751 return 0;
752 }
753
754 /* This code is used also with LEDs disabled */
rb8366rb_set_ledgroup_mode(struct realtek_priv * priv,u8 led_group,enum rtl8366_ledgroup_mode mode)755 int rb8366rb_set_ledgroup_mode(struct realtek_priv *priv,
756 u8 led_group,
757 enum rtl8366_ledgroup_mode mode)
758 {
759 int ret;
760 u32 val;
761
762 val = mode << RTL8366RB_LED_CTRL_OFFSET(led_group);
763
764 ret = regmap_update_bits(priv->map,
765 RTL8366RB_LED_CTRL_REG,
766 RTL8366RB_LED_CTRL_MASK(led_group),
767 val);
768 if (ret)
769 return ret;
770
771 return 0;
772 }
773
774 /* This code is used also with LEDs disabled */
rtl8366rb_setup_all_leds_off(struct realtek_priv * priv)775 static int rtl8366rb_setup_all_leds_off(struct realtek_priv *priv)
776 {
777 int ret = 0;
778 int i;
779
780 regmap_update_bits(priv->map,
781 RTL8366RB_INTERRUPT_CONTROL_REG,
782 RTL8366RB_P4_RGMII_LED,
783 0);
784
785 for (i = 0; i < RTL8366RB_NUM_LEDGROUPS; i++) {
786 ret = rb8366rb_set_ledgroup_mode(priv, i,
787 RTL8366RB_LEDGROUP_OFF);
788 if (ret)
789 return ret;
790 }
791
792 return ret;
793 }
794
rtl8366rb_setup(struct dsa_switch * ds)795 static int rtl8366rb_setup(struct dsa_switch *ds)
796 {
797 struct realtek_priv *priv = ds->priv;
798 const struct rtl8366rb_jam_tbl_entry *jam_table;
799 struct rtl8366rb *rb;
800 u32 chip_ver = 0;
801 u32 chip_id = 0;
802 int jam_size;
803 int ret;
804 int i;
805
806 rb = priv->chip_data;
807
808 ret = regmap_read(priv->map, RTL8366RB_CHIP_ID_REG, &chip_id);
809 if (ret) {
810 dev_err(priv->dev, "unable to read chip id\n");
811 return ret;
812 }
813
814 switch (chip_id) {
815 case RTL8366RB_CHIP_ID_8366:
816 break;
817 default:
818 dev_err(priv->dev, "unknown chip id (%04x)\n", chip_id);
819 return -ENODEV;
820 }
821
822 ret = regmap_read(priv->map, RTL8366RB_CHIP_VERSION_CTRL_REG,
823 &chip_ver);
824 if (ret) {
825 dev_err(priv->dev, "unable to read chip version\n");
826 return ret;
827 }
828
829 dev_info(priv->dev, "RTL%04x ver %u chip found\n",
830 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
831
832 /* Do the init dance using the right jam table */
833 switch (chip_ver) {
834 case 0:
835 jam_table = rtl8366rb_init_jam_ver_0;
836 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_0);
837 break;
838 case 1:
839 jam_table = rtl8366rb_init_jam_ver_1;
840 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_1);
841 break;
842 case 2:
843 jam_table = rtl8366rb_init_jam_ver_2;
844 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_2);
845 break;
846 default:
847 jam_table = rtl8366rb_init_jam_ver_3;
848 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_3);
849 break;
850 }
851
852 /* Special jam tables for special routers
853 * TODO: are these necessary? Maintainers, please test
854 * without them, using just the off-the-shelf tables.
855 */
856 if (of_machine_is_compatible("belkin,f5d8235-v1")) {
857 jam_table = rtl8366rb_init_jam_f5d8235;
858 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_f5d8235);
859 }
860 if (of_machine_is_compatible("netgear,dgn3500") ||
861 of_machine_is_compatible("netgear,dgn3500b")) {
862 jam_table = rtl8366rb_init_jam_dgn3500;
863 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500);
864 }
865
866 ret = rtl8366rb_jam_table(jam_table, jam_size, priv, true);
867 if (ret)
868 return ret;
869
870 /* Isolate all user ports so they can only send packets to itself and the CPU port */
871 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
872 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(i),
873 RTL8366RB_PORT_ISO_PORTS(BIT(RTL8366RB_PORT_NUM_CPU)) |
874 RTL8366RB_PORT_ISO_EN);
875 if (ret)
876 return ret;
877 }
878 /* CPU port can send packets to all ports */
879 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU),
880 RTL8366RB_PORT_ISO_PORTS(dsa_user_ports(ds)) |
881 RTL8366RB_PORT_ISO_EN);
882 if (ret)
883 return ret;
884
885 /* Set up the "green ethernet" feature */
886 ret = rtl8366rb_jam_table(rtl8366rb_green_jam,
887 ARRAY_SIZE(rtl8366rb_green_jam), priv, false);
888 if (ret)
889 return ret;
890
891 ret = regmap_write(priv->map,
892 RTL8366RB_GREEN_FEATURE_REG,
893 (chip_ver == 1) ? 0x0007 : 0x0003);
894 if (ret)
895 return ret;
896
897 /* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */
898 ret = regmap_write(priv->map, 0x0c, 0x240);
899 if (ret)
900 return ret;
901 ret = regmap_write(priv->map, 0x0d, 0x240);
902 if (ret)
903 return ret;
904
905 /* Set some random MAC address */
906 ret = rtl8366rb_set_addr(priv);
907 if (ret)
908 return ret;
909
910 /* Enable CPU port with custom DSA tag 8899.
911 *
912 * If you set RTL8366RB_CPU_NO_TAG (bit 15) in this register
913 * the custom tag is turned off.
914 */
915 ret = regmap_update_bits(priv->map, RTL8366RB_CPU_CTRL_REG,
916 0xFFFF,
917 BIT(priv->cpu_port));
918 if (ret)
919 return ret;
920
921 /* Make sure we default-enable the fixed CPU port */
922 ret = regmap_update_bits(priv->map, RTL8366RB_PECR,
923 BIT(priv->cpu_port),
924 0);
925 if (ret)
926 return ret;
927
928 /* Set default maximum packet length to 1536 bytes */
929 ret = regmap_update_bits(priv->map, RTL8366RB_SGCR,
930 RTL8366RB_SGCR_MAX_LENGTH_MASK,
931 RTL8366RB_SGCR_MAX_LENGTH_1536);
932 if (ret)
933 return ret;
934 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
935 if (i == priv->cpu_port)
936 /* CPU port need to also accept the tag */
937 rb->max_mtu[i] = ETH_DATA_LEN + RTL8366RB_CPU_TAG_SIZE;
938 else
939 rb->max_mtu[i] = ETH_DATA_LEN;
940 }
941
942 /* Disable learning for all ports */
943 ret = regmap_write(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
944 RTL8366RB_PORT_ALL);
945 if (ret)
946 return ret;
947
948 /* Enable auto ageing for all ports */
949 ret = regmap_write(priv->map, RTL8366RB_SECURITY_CTRL, 0);
950 if (ret)
951 return ret;
952
953 /* Port 4 setup: this enables Port 4, usually the WAN port,
954 * common PHY IO mode is apparently mode 0, and this is not what
955 * the port is initialized to. There is no explanation of the
956 * IO modes in the Realtek source code, if your WAN port is
957 * connected to something exotic such as fiber, then this might
958 * be worth experimenting with.
959 */
960 ret = regmap_update_bits(priv->map, RTL8366RB_PMC0,
961 RTL8366RB_PMC0_P4_IOMODE_MASK,
962 0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT);
963 if (ret)
964 return ret;
965
966 /* Accept all packets by default, we enable filtering on-demand */
967 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
968 0);
969 if (ret)
970 return ret;
971 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
972 0);
973 if (ret)
974 return ret;
975
976 /* Don't drop packets whose DA has not been learned */
977 ret = regmap_update_bits(priv->map, RTL8366RB_SSCR2,
978 RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
979 if (ret)
980 return ret;
981
982 /* Set blinking, used by all LED groups using HW triggers.
983 * TODO: make this configurable
984 */
985 ret = regmap_update_bits(priv->map, RTL8366RB_LED_BLINKRATE_REG,
986 RTL8366RB_LED_BLINKRATE_MASK,
987 RTL8366RB_LED_BLINKRATE_56MS);
988 if (ret)
989 return ret;
990
991 /* Set up LED activity:
992 * Each port has 4 LEDs on fixed groups. Each group shares the same
993 * hardware trigger across all ports. LEDs can only be indiviually
994 * controlled setting the LED group to fixed mode and using the driver
995 * to toggle them LEDs on/off.
996 */
997 if (priv->leds_disabled) {
998 ret = rtl8366rb_setup_all_leds_off(priv);
999 if (ret)
1000 return ret;
1001 } else {
1002 ret = rtl8366rb_setup_leds(priv);
1003 if (ret)
1004 return ret;
1005 }
1006
1007 ret = rtl8366_reset_vlan(priv);
1008 if (ret)
1009 return ret;
1010
1011 ret = rtl8366rb_setup_cascaded_irq(priv);
1012 if (ret)
1013 dev_info(priv->dev, "no interrupt support\n");
1014
1015 ret = rtl83xx_setup_user_mdio(ds);
1016 if (ret) {
1017 dev_err(priv->dev, "could not set up MDIO bus\n");
1018 return -ENODEV;
1019 }
1020
1021 return 0;
1022 }
1023
rtl8366_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)1024 static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds,
1025 int port,
1026 enum dsa_tag_protocol mp)
1027 {
1028 /* This switch uses the 4 byte protocol A Realtek DSA tag */
1029 return DSA_TAG_PROTO_RTL4_A;
1030 }
1031
rtl8366rb_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1032 static void rtl8366rb_phylink_get_caps(struct dsa_switch *ds, int port,
1033 struct phylink_config *config)
1034 {
1035 unsigned long *interfaces = config->supported_interfaces;
1036 struct realtek_priv *priv = ds->priv;
1037
1038 if (port == priv->cpu_port) {
1039 __set_bit(PHY_INTERFACE_MODE_MII, interfaces);
1040 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1041 /* REVMII only supports 100M FD */
1042 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);
1043 /* RGMII only supports 1G FD */
1044 phy_interface_set_rgmii(interfaces);
1045
1046 config->mac_capabilities = MAC_1000 | MAC_100 |
1047 MAC_SYM_PAUSE;
1048 } else {
1049 /* RSGMII port, but we don't have that, and we don't
1050 * specify in DT, so phylib uses the default of GMII
1051 */
1052 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1053 config->mac_capabilities = MAC_1000 | MAC_100 | MAC_10 |
1054 MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
1055 }
1056 }
1057
1058 static void
rtl8366rb_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)1059 rtl8366rb_mac_config(struct phylink_config *config, unsigned int mode,
1060 const struct phylink_link_state *state)
1061 {
1062 }
1063
1064 static void
rtl8366rb_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)1065 rtl8366rb_mac_link_up(struct phylink_config *config, struct phy_device *phydev,
1066 unsigned int mode, phy_interface_t interface,
1067 int speed, int duplex, bool tx_pause, bool rx_pause)
1068 {
1069 struct dsa_port *dp = dsa_phylink_to_port(config);
1070 struct realtek_priv *priv = dp->ds->priv;
1071 int port = dp->index;
1072 unsigned int val;
1073 int ret;
1074
1075 /* Allow forcing the mode on the fixed CPU port, no autonegotiation.
1076 * We assume autonegotiation works on the PHY-facing ports.
1077 */
1078 if (port != priv->cpu_port)
1079 return;
1080
1081 dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port);
1082
1083 ret = regmap_update_bits(priv->map, RTL8366RB_MAC_FORCE_CTRL_REG,
1084 BIT(port), BIT(port));
1085 if (ret) {
1086 dev_err(priv->dev, "failed to force CPU port\n");
1087 return;
1088 }
1089
1090 /* Conjure port config */
1091 switch (speed) {
1092 case SPEED_10:
1093 val = RTL8366RB_PAACR_SPEED_10M;
1094 break;
1095 case SPEED_100:
1096 val = RTL8366RB_PAACR_SPEED_100M;
1097 break;
1098 case SPEED_1000:
1099 val = RTL8366RB_PAACR_SPEED_1000M;
1100 break;
1101 default:
1102 val = RTL8366RB_PAACR_SPEED_1000M;
1103 break;
1104 }
1105
1106 if (duplex == DUPLEX_FULL)
1107 val |= RTL8366RB_PAACR_FULL_DUPLEX;
1108
1109 if (tx_pause)
1110 val |= RTL8366RB_PAACR_TX_PAUSE;
1111
1112 if (rx_pause)
1113 val |= RTL8366RB_PAACR_RX_PAUSE;
1114
1115 val |= RTL8366RB_PAACR_LINK_UP;
1116
1117 ret = regmap_update_bits(priv->map, RTL8366RB_PAACR2,
1118 0xFF00U,
1119 val << 8);
1120 if (ret) {
1121 dev_err(priv->dev, "failed to set PAACR on CPU port\n");
1122 return;
1123 }
1124
1125 dev_dbg(priv->dev, "set PAACR to %04x\n", val);
1126
1127 /* Enable the CPU port */
1128 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1129 0);
1130 if (ret) {
1131 dev_err(priv->dev, "failed to enable the CPU port\n");
1132 return;
1133 }
1134 }
1135
1136 static void
rtl8366rb_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)1137 rtl8366rb_mac_link_down(struct phylink_config *config, unsigned int mode,
1138 phy_interface_t interface)
1139 {
1140 struct dsa_port *dp = dsa_phylink_to_port(config);
1141 struct realtek_priv *priv = dp->ds->priv;
1142 int port = dp->index;
1143 int ret;
1144
1145 if (port != priv->cpu_port)
1146 return;
1147
1148 dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port);
1149
1150 /* Disable the CPU port */
1151 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1152 BIT(port));
1153 if (ret) {
1154 dev_err(priv->dev, "failed to disable the CPU port\n");
1155 return;
1156 }
1157 }
1158
1159 static int
rtl8366rb_port_enable(struct dsa_switch * ds,int port,struct phy_device * phy)1160 rtl8366rb_port_enable(struct dsa_switch *ds, int port,
1161 struct phy_device *phy)
1162 {
1163 struct realtek_priv *priv = ds->priv;
1164 int ret;
1165
1166 dev_dbg(priv->dev, "enable port %d\n", port);
1167 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1168 0);
1169 if (ret)
1170 return ret;
1171
1172 return 0;
1173 }
1174
1175 static void
rtl8366rb_port_disable(struct dsa_switch * ds,int port)1176 rtl8366rb_port_disable(struct dsa_switch *ds, int port)
1177 {
1178 struct realtek_priv *priv = ds->priv;
1179 int ret;
1180
1181 dev_dbg(priv->dev, "disable port %d\n", port);
1182 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1183 BIT(port));
1184 if (ret)
1185 return;
1186 }
1187
1188 static int
rtl8366rb_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)1189 rtl8366rb_port_bridge_join(struct dsa_switch *ds, int port,
1190 struct dsa_bridge bridge,
1191 bool *tx_fwd_offload,
1192 struct netlink_ext_ack *extack)
1193 {
1194 struct realtek_priv *priv = ds->priv;
1195 unsigned int port_bitmap = 0;
1196 int ret, i;
1197
1198 /* Loop over all other ports than the current one */
1199 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1200 /* Current port handled last */
1201 if (i == port)
1202 continue;
1203 /* Not on this bridge */
1204 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1205 continue;
1206 /* Join this port to each other port on the bridge */
1207 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1208 RTL8366RB_PORT_ISO_PORTS(BIT(port)),
1209 RTL8366RB_PORT_ISO_PORTS(BIT(port)));
1210 if (ret)
1211 dev_err(priv->dev, "failed to join port %d\n", port);
1212
1213 port_bitmap |= BIT(i);
1214 }
1215
1216 /* Set the bits for the ports we can access */
1217 return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1218 RTL8366RB_PORT_ISO_PORTS(port_bitmap),
1219 RTL8366RB_PORT_ISO_PORTS(port_bitmap));
1220 }
1221
1222 static void
rtl8366rb_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)1223 rtl8366rb_port_bridge_leave(struct dsa_switch *ds, int port,
1224 struct dsa_bridge bridge)
1225 {
1226 struct realtek_priv *priv = ds->priv;
1227 unsigned int port_bitmap = 0;
1228 int ret, i;
1229
1230 /* Loop over all other ports than this one */
1231 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1232 /* Current port handled last */
1233 if (i == port)
1234 continue;
1235 /* Not on this bridge */
1236 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1237 continue;
1238 /* Remove this port from any other port on the bridge */
1239 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1240 RTL8366RB_PORT_ISO_PORTS(BIT(port)), 0);
1241 if (ret)
1242 dev_err(priv->dev, "failed to leave port %d\n", port);
1243
1244 port_bitmap |= BIT(i);
1245 }
1246
1247 /* Clear the bits for the ports we can not access, leave ourselves */
1248 regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1249 RTL8366RB_PORT_ISO_PORTS(port_bitmap), 0);
1250 }
1251
1252 /**
1253 * rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames
1254 * @priv: SMI state container
1255 * @port: the port to drop untagged and C-tagged frames on
1256 * @drop: whether to drop or pass untagged and C-tagged frames
1257 *
1258 * Return: zero for success, a negative number on error.
1259 */
rtl8366rb_drop_untagged(struct realtek_priv * priv,int port,bool drop)1260 static int rtl8366rb_drop_untagged(struct realtek_priv *priv, int port, bool drop)
1261 {
1262 return regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
1263 RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port),
1264 drop ? RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) : 0);
1265 }
1266
rtl8366rb_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)1267 static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port,
1268 bool vlan_filtering,
1269 struct netlink_ext_ack *extack)
1270 {
1271 struct realtek_priv *priv = ds->priv;
1272 struct rtl8366rb *rb;
1273 int ret;
1274
1275 rb = priv->chip_data;
1276
1277 dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port,
1278 str_enable_disable(vlan_filtering));
1279
1280 /* If the port is not in the member set, the frame will be dropped */
1281 ret = regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
1282 BIT(port), vlan_filtering ? BIT(port) : 0);
1283 if (ret)
1284 return ret;
1285
1286 /* If VLAN filtering is enabled and PVID is also enabled, we must
1287 * not drop any untagged or C-tagged frames. If we turn off VLAN
1288 * filtering on a port, we need to accept any frames.
1289 */
1290 if (vlan_filtering)
1291 ret = rtl8366rb_drop_untagged(priv, port, !rb->pvid_enabled[port]);
1292 else
1293 ret = rtl8366rb_drop_untagged(priv, port, false);
1294
1295 return ret;
1296 }
1297
1298 static int
rtl8366rb_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)1299 rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1300 struct switchdev_brport_flags flags,
1301 struct netlink_ext_ack *extack)
1302 {
1303 /* We support enabling/disabling learning */
1304 if (flags.mask & ~(BR_LEARNING))
1305 return -EINVAL;
1306
1307 return 0;
1308 }
1309
1310 static int
rtl8366rb_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)1311 rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port,
1312 struct switchdev_brport_flags flags,
1313 struct netlink_ext_ack *extack)
1314 {
1315 struct realtek_priv *priv = ds->priv;
1316 int ret;
1317
1318 if (flags.mask & BR_LEARNING) {
1319 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
1320 BIT(port),
1321 (flags.val & BR_LEARNING) ? 0 : BIT(port));
1322 if (ret)
1323 return ret;
1324 }
1325
1326 return 0;
1327 }
1328
1329 static void
rtl8366rb_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1330 rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1331 {
1332 struct realtek_priv *priv = ds->priv;
1333 u32 val;
1334 int i;
1335
1336 switch (state) {
1337 case BR_STATE_DISABLED:
1338 val = RTL8366RB_STP_STATE_DISABLED;
1339 break;
1340 case BR_STATE_BLOCKING:
1341 case BR_STATE_LISTENING:
1342 val = RTL8366RB_STP_STATE_BLOCKING;
1343 break;
1344 case BR_STATE_LEARNING:
1345 val = RTL8366RB_STP_STATE_LEARNING;
1346 break;
1347 case BR_STATE_FORWARDING:
1348 val = RTL8366RB_STP_STATE_FORWARDING;
1349 break;
1350 default:
1351 dev_err(priv->dev, "unknown bridge state requested\n");
1352 return;
1353 }
1354
1355 /* Set the same status for the port on all the FIDs */
1356 for (i = 0; i < RTL8366RB_NUM_FIDS; i++) {
1357 regmap_update_bits(priv->map, RTL8366RB_STP_STATE_BASE + i,
1358 RTL8366RB_STP_STATE_MASK(port),
1359 RTL8366RB_STP_STATE(port, val));
1360 }
1361 }
1362
1363 static void
rtl8366rb_port_fast_age(struct dsa_switch * ds,int port)1364 rtl8366rb_port_fast_age(struct dsa_switch *ds, int port)
1365 {
1366 struct realtek_priv *priv = ds->priv;
1367
1368 /* This will age out any learned L2 entries */
1369 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1370 BIT(port), BIT(port));
1371 /* Restore the normal state of things */
1372 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1373 BIT(port), 0);
1374 }
1375
rtl8366rb_change_mtu(struct dsa_switch * ds,int port,int new_mtu)1376 static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1377 {
1378 struct realtek_priv *priv = ds->priv;
1379 struct rtl8366rb *rb;
1380 unsigned int max_mtu;
1381 u32 len;
1382 int i;
1383
1384 /* Cache the per-port MTU setting */
1385 rb = priv->chip_data;
1386 rb->max_mtu[port] = new_mtu;
1387
1388 /* Roof out the MTU for the entire switch to the greatest
1389 * common denominator: the biggest set for any one port will
1390 * be the biggest MTU for the switch.
1391 */
1392 max_mtu = ETH_DATA_LEN;
1393 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1394 if (rb->max_mtu[i] > max_mtu)
1395 max_mtu = rb->max_mtu[i];
1396 }
1397
1398 /* Translate to layer 2 size.
1399 * Add ethernet and (possible) VLAN headers, and checksum to the size.
1400 * For ETH_DATA_LEN (1500 bytes) this will add up to 1522 bytes.
1401 */
1402 max_mtu += VLAN_ETH_HLEN;
1403 max_mtu += ETH_FCS_LEN;
1404
1405 if (max_mtu <= 1522)
1406 len = RTL8366RB_SGCR_MAX_LENGTH_1522;
1407 else if (max_mtu > 1522 && max_mtu <= 1536)
1408 /* This will be the most common default if using VLAN and
1409 * CPU tagging on a port as both VLAN and CPU tag will
1410 * result in 1518 + 4 + 4 = 1526 bytes.
1411 */
1412 len = RTL8366RB_SGCR_MAX_LENGTH_1536;
1413 else if (max_mtu > 1536 && max_mtu <= 1552)
1414 len = RTL8366RB_SGCR_MAX_LENGTH_1552;
1415 else
1416 len = RTL8366RB_SGCR_MAX_LENGTH_16000;
1417
1418 return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1419 RTL8366RB_SGCR_MAX_LENGTH_MASK,
1420 len);
1421 }
1422
rtl8366rb_max_mtu(struct dsa_switch * ds,int port)1423 static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port)
1424 {
1425 /* The max MTU is 16000 bytes, so we subtract the ethernet
1426 * headers with VLAN and checksum and arrive at
1427 * 16000 - 18 - 4 = 15978. This does not include the CPU tag
1428 * since that is added to the requested MTU by the DSA framework.
1429 */
1430 return 16000 - VLAN_ETH_HLEN - ETH_FCS_LEN;
1431 }
1432
rtl8366rb_get_vlan_4k(struct realtek_priv * priv,u32 vid,struct rtl8366_vlan_4k * vlan4k)1433 static int rtl8366rb_get_vlan_4k(struct realtek_priv *priv, u32 vid,
1434 struct rtl8366_vlan_4k *vlan4k)
1435 {
1436 u32 data[3];
1437 int ret;
1438 int i;
1439
1440 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1441
1442 if (vid >= RTL8366RB_NUM_VIDS)
1443 return -EINVAL;
1444
1445 /* write VID */
1446 ret = regmap_write(priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE,
1447 vid & RTL8366RB_VLAN_VID_MASK);
1448 if (ret)
1449 return ret;
1450
1451 /* write table access control word */
1452 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1453 RTL8366RB_TABLE_VLAN_READ_CTRL);
1454 if (ret)
1455 return ret;
1456
1457 for (i = 0; i < 3; i++) {
1458 ret = regmap_read(priv->map,
1459 RTL8366RB_VLAN_TABLE_READ_BASE + i,
1460 &data[i]);
1461 if (ret)
1462 return ret;
1463 }
1464
1465 vlan4k->vid = vid;
1466 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1467 RTL8366RB_VLAN_UNTAG_MASK;
1468 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1469 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1470
1471 return 0;
1472 }
1473
rtl8366rb_set_vlan_4k(struct realtek_priv * priv,const struct rtl8366_vlan_4k * vlan4k)1474 static int rtl8366rb_set_vlan_4k(struct realtek_priv *priv,
1475 const struct rtl8366_vlan_4k *vlan4k)
1476 {
1477 u32 data[3];
1478 int ret;
1479 int i;
1480
1481 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
1482 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
1483 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1484 vlan4k->fid > RTL8366RB_FIDMAX)
1485 return -EINVAL;
1486
1487 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
1488 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
1489 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1490 RTL8366RB_VLAN_UNTAG_SHIFT);
1491 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
1492
1493 for (i = 0; i < 3; i++) {
1494 ret = regmap_write(priv->map,
1495 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
1496 data[i]);
1497 if (ret)
1498 return ret;
1499 }
1500
1501 /* write table access control word */
1502 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1503 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
1504
1505 return ret;
1506 }
1507
rtl8366rb_get_vlan_mc(struct realtek_priv * priv,u32 index,struct rtl8366_vlan_mc * vlanmc)1508 static int rtl8366rb_get_vlan_mc(struct realtek_priv *priv, u32 index,
1509 struct rtl8366_vlan_mc *vlanmc)
1510 {
1511 u32 data[3];
1512 int ret;
1513 int i;
1514
1515 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1516
1517 if (index >= RTL8366RB_NUM_VLANS)
1518 return -EINVAL;
1519
1520 for (i = 0; i < 3; i++) {
1521 ret = regmap_read(priv->map,
1522 RTL8366RB_VLAN_MC_BASE(index) + i,
1523 &data[i]);
1524 if (ret)
1525 return ret;
1526 }
1527
1528 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
1529 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
1530 RTL8366RB_VLAN_PRIORITY_MASK;
1531 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1532 RTL8366RB_VLAN_UNTAG_MASK;
1533 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1534 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1535
1536 return 0;
1537 }
1538
rtl8366rb_set_vlan_mc(struct realtek_priv * priv,u32 index,const struct rtl8366_vlan_mc * vlanmc)1539 static int rtl8366rb_set_vlan_mc(struct realtek_priv *priv, u32 index,
1540 const struct rtl8366_vlan_mc *vlanmc)
1541 {
1542 u32 data[3];
1543 int ret;
1544 int i;
1545
1546 if (index >= RTL8366RB_NUM_VLANS ||
1547 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
1548 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
1549 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
1550 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1551 vlanmc->fid > RTL8366RB_FIDMAX)
1552 return -EINVAL;
1553
1554 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
1555 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
1556 RTL8366RB_VLAN_PRIORITY_SHIFT);
1557 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
1558 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1559 RTL8366RB_VLAN_UNTAG_SHIFT);
1560 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
1561
1562 for (i = 0; i < 3; i++) {
1563 ret = regmap_write(priv->map,
1564 RTL8366RB_VLAN_MC_BASE(index) + i,
1565 data[i]);
1566 if (ret)
1567 return ret;
1568 }
1569
1570 return 0;
1571 }
1572
rtl8366rb_get_mc_index(struct realtek_priv * priv,int port,int * val)1573 static int rtl8366rb_get_mc_index(struct realtek_priv *priv, int port, int *val)
1574 {
1575 u32 data;
1576 int ret;
1577
1578 if (port >= priv->num_ports)
1579 return -EINVAL;
1580
1581 ret = regmap_read(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1582 &data);
1583 if (ret)
1584 return ret;
1585
1586 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
1587 RTL8366RB_PORT_VLAN_CTRL_MASK;
1588
1589 return 0;
1590 }
1591
rtl8366rb_set_mc_index(struct realtek_priv * priv,int port,int index)1592 static int rtl8366rb_set_mc_index(struct realtek_priv *priv, int port, int index)
1593 {
1594 struct dsa_switch *ds = &priv->ds;
1595 struct rtl8366rb *rb;
1596 bool pvid_enabled;
1597 int ret;
1598
1599 rb = priv->chip_data;
1600 pvid_enabled = !!index;
1601
1602 if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS)
1603 return -EINVAL;
1604
1605 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1606 RTL8366RB_PORT_VLAN_CTRL_MASK <<
1607 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
1608 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
1609 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
1610 if (ret)
1611 return ret;
1612
1613 rb->pvid_enabled[port] = pvid_enabled;
1614
1615 /* If VLAN filtering is enabled and PVID is also enabled, we must
1616 * not drop any untagged or C-tagged frames. Make sure to update the
1617 * filtering setting.
1618 */
1619 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1620 ret = rtl8366rb_drop_untagged(priv, port, !pvid_enabled);
1621
1622 return ret;
1623 }
1624
rtl8366rb_is_vlan_valid(struct realtek_priv * priv,unsigned int vlan)1625 static bool rtl8366rb_is_vlan_valid(struct realtek_priv *priv, unsigned int vlan)
1626 {
1627 unsigned int max = RTL8366RB_NUM_VLANS - 1;
1628
1629 if (priv->vlan4k_enabled)
1630 max = RTL8366RB_NUM_VIDS - 1;
1631
1632 if (vlan > max)
1633 return false;
1634
1635 return true;
1636 }
1637
rtl8366rb_enable_vlan(struct realtek_priv * priv,bool enable)1638 static int rtl8366rb_enable_vlan(struct realtek_priv *priv, bool enable)
1639 {
1640 dev_dbg(priv->dev, "%s VLAN\n", str_enable_disable(enable));
1641 return regmap_update_bits(priv->map,
1642 RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
1643 enable ? RTL8366RB_SGCR_EN_VLAN : 0);
1644 }
1645
rtl8366rb_enable_vlan4k(struct realtek_priv * priv,bool enable)1646 static int rtl8366rb_enable_vlan4k(struct realtek_priv *priv, bool enable)
1647 {
1648 dev_dbg(priv->dev, "%s VLAN 4k\n", str_enable_disable(enable));
1649 return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1650 RTL8366RB_SGCR_EN_VLAN_4KTB,
1651 enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
1652 }
1653
rtl8366rb_phy_read(struct realtek_priv * priv,int phy,int regnum)1654 static int rtl8366rb_phy_read(struct realtek_priv *priv, int phy, int regnum)
1655 {
1656 u32 val;
1657 u32 reg;
1658 int ret;
1659
1660 if (phy > RTL8366RB_PHY_NO_MAX)
1661 return -EINVAL;
1662
1663 rtl83xx_lock(priv);
1664
1665 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1666 RTL8366RB_PHY_CTRL_READ);
1667 if (ret)
1668 goto out;
1669
1670 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1671
1672 ret = regmap_write(priv->map_nolock, reg, 0);
1673 if (ret) {
1674 dev_err(priv->dev,
1675 "failed to write PHY%d reg %04x @ %04x, ret %d\n",
1676 phy, regnum, reg, ret);
1677 goto out;
1678 }
1679
1680 ret = regmap_read(priv->map_nolock, RTL8366RB_PHY_ACCESS_DATA_REG,
1681 &val);
1682 if (ret)
1683 goto out;
1684
1685 ret = val;
1686
1687 dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n",
1688 phy, regnum, reg, val);
1689
1690 out:
1691 rtl83xx_unlock(priv);
1692
1693 return ret;
1694 }
1695
rtl8366rb_phy_write(struct realtek_priv * priv,int phy,int regnum,u16 val)1696 static int rtl8366rb_phy_write(struct realtek_priv *priv, int phy, int regnum,
1697 u16 val)
1698 {
1699 u32 reg;
1700 int ret;
1701
1702 if (phy > RTL8366RB_PHY_NO_MAX)
1703 return -EINVAL;
1704
1705 rtl83xx_lock(priv);
1706
1707 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1708 RTL8366RB_PHY_CTRL_WRITE);
1709 if (ret)
1710 goto out;
1711
1712 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1713
1714 dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n",
1715 phy, regnum, reg, val);
1716
1717 ret = regmap_write(priv->map_nolock, reg, val);
1718 if (ret)
1719 goto out;
1720
1721 out:
1722 rtl83xx_unlock(priv);
1723
1724 return ret;
1725 }
1726
rtl8366rb_reset_chip(struct realtek_priv * priv)1727 static int rtl8366rb_reset_chip(struct realtek_priv *priv)
1728 {
1729 int timeout = 10;
1730 u32 val;
1731 int ret;
1732
1733 priv->write_reg_noack(priv, RTL8366RB_RESET_CTRL_REG,
1734 RTL8366RB_CHIP_CTRL_RESET_HW);
1735 do {
1736 usleep_range(20000, 25000);
1737 ret = regmap_read(priv->map, RTL8366RB_RESET_CTRL_REG, &val);
1738 if (ret)
1739 return ret;
1740
1741 if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW))
1742 break;
1743 } while (--timeout);
1744
1745 if (!timeout) {
1746 dev_err(priv->dev, "timeout waiting for the switch to reset\n");
1747 return -EIO;
1748 }
1749
1750 return 0;
1751 }
1752
rtl8366rb_detect(struct realtek_priv * priv)1753 static int rtl8366rb_detect(struct realtek_priv *priv)
1754 {
1755 struct device *dev = priv->dev;
1756 int ret;
1757 u32 val;
1758
1759 /* Detect device */
1760 ret = regmap_read(priv->map, 0x5c, &val);
1761 if (ret) {
1762 dev_err(dev, "can't get chip ID (%d)\n", ret);
1763 return ret;
1764 }
1765
1766 switch (val) {
1767 case 0x6027:
1768 dev_info(dev, "found an RTL8366S switch\n");
1769 dev_err(dev, "this switch is not yet supported, submit patches!\n");
1770 return -ENODEV;
1771 case 0x5937:
1772 dev_info(dev, "found an RTL8366RB switch\n");
1773 priv->cpu_port = RTL8366RB_PORT_NUM_CPU;
1774 priv->num_ports = RTL8366RB_NUM_PORTS;
1775 priv->num_vlan_mc = RTL8366RB_NUM_VLANS;
1776 priv->mib_counters = rtl8366rb_mib_counters;
1777 priv->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1778 break;
1779 default:
1780 dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n",
1781 val);
1782 break;
1783 }
1784
1785 ret = rtl8366rb_reset_chip(priv);
1786 if (ret)
1787 return ret;
1788
1789 return 0;
1790 }
1791
1792 static const struct phylink_mac_ops rtl8366rb_phylink_mac_ops = {
1793 .mac_config = rtl8366rb_mac_config,
1794 .mac_link_down = rtl8366rb_mac_link_down,
1795 .mac_link_up = rtl8366rb_mac_link_up,
1796 };
1797
1798 static const struct dsa_switch_ops rtl8366rb_switch_ops = {
1799 .get_tag_protocol = rtl8366_get_tag_protocol,
1800 .setup = rtl8366rb_setup,
1801 .phylink_get_caps = rtl8366rb_phylink_get_caps,
1802 .get_strings = rtl8366_get_strings,
1803 .get_ethtool_stats = rtl8366_get_ethtool_stats,
1804 .get_sset_count = rtl8366_get_sset_count,
1805 .port_bridge_join = rtl8366rb_port_bridge_join,
1806 .port_bridge_leave = rtl8366rb_port_bridge_leave,
1807 .port_vlan_filtering = rtl8366rb_vlan_filtering,
1808 .port_vlan_add = rtl8366_vlan_add,
1809 .port_vlan_del = rtl8366_vlan_del,
1810 .port_enable = rtl8366rb_port_enable,
1811 .port_disable = rtl8366rb_port_disable,
1812 .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,
1813 .port_bridge_flags = rtl8366rb_port_bridge_flags,
1814 .port_stp_state_set = rtl8366rb_port_stp_state_set,
1815 .port_fast_age = rtl8366rb_port_fast_age,
1816 .port_change_mtu = rtl8366rb_change_mtu,
1817 .port_max_mtu = rtl8366rb_max_mtu,
1818 };
1819
1820 static const struct realtek_ops rtl8366rb_ops = {
1821 .detect = rtl8366rb_detect,
1822 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1823 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1824 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1825 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1826 .get_mc_index = rtl8366rb_get_mc_index,
1827 .set_mc_index = rtl8366rb_set_mc_index,
1828 .get_mib_counter = rtl8366rb_get_mib_counter,
1829 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1830 .enable_vlan = rtl8366rb_enable_vlan,
1831 .enable_vlan4k = rtl8366rb_enable_vlan4k,
1832 .phy_read = rtl8366rb_phy_read,
1833 .phy_write = rtl8366rb_phy_write,
1834 };
1835
1836 const struct realtek_variant rtl8366rb_variant = {
1837 .ds_ops = &rtl8366rb_switch_ops,
1838 .ops = &rtl8366rb_ops,
1839 .phylink_mac_ops = &rtl8366rb_phylink_mac_ops,
1840 .clk_delay = 10,
1841 .cmd_read = 0xa9,
1842 .cmd_write = 0xa8,
1843 .chip_data_sz = sizeof(struct rtl8366rb),
1844 };
1845
1846 static const struct of_device_id rtl8366rb_of_match[] = {
1847 { .compatible = "realtek,rtl8366rb", .data = &rtl8366rb_variant, },
1848 { /* sentinel */ },
1849 };
1850 MODULE_DEVICE_TABLE(of, rtl8366rb_of_match);
1851
1852 static struct platform_driver rtl8366rb_smi_driver = {
1853 .driver = {
1854 .name = "rtl8366rb-smi",
1855 .of_match_table = rtl8366rb_of_match,
1856 },
1857 .probe = realtek_smi_probe,
1858 .remove = realtek_smi_remove,
1859 .shutdown = realtek_smi_shutdown,
1860 };
1861
1862 static struct mdio_driver rtl8366rb_mdio_driver = {
1863 .mdiodrv.driver = {
1864 .name = "rtl8366rb-mdio",
1865 .of_match_table = rtl8366rb_of_match,
1866 },
1867 .probe = realtek_mdio_probe,
1868 .remove = realtek_mdio_remove,
1869 .shutdown = realtek_mdio_shutdown,
1870 };
1871
rtl8366rb_init(void)1872 static int rtl8366rb_init(void)
1873 {
1874 int ret;
1875
1876 ret = realtek_mdio_driver_register(&rtl8366rb_mdio_driver);
1877 if (ret)
1878 return ret;
1879
1880 ret = realtek_smi_driver_register(&rtl8366rb_smi_driver);
1881 if (ret) {
1882 realtek_mdio_driver_unregister(&rtl8366rb_mdio_driver);
1883 return ret;
1884 }
1885
1886 return 0;
1887 }
1888 module_init(rtl8366rb_init);
1889
rtl8366rb_exit(void)1890 static void __exit rtl8366rb_exit(void)
1891 {
1892 realtek_smi_driver_unregister(&rtl8366rb_smi_driver);
1893 realtek_mdio_driver_unregister(&rtl8366rb_mdio_driver);
1894 }
1895 module_exit(rtl8366rb_exit);
1896
1897 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1898 MODULE_DESCRIPTION("Driver for RTL8366RB ethernet switch");
1899 MODULE_LICENSE("GPL");
1900 MODULE_IMPORT_NS("REALTEK_DSA");
1901