1
2 /*-
3 * Copyright (c) 2006
4 * Damien Bergamini <damien.bergamini@free.fr>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #include <sys/cdefs.h>
20 /*-
21 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver
22 * http://www.ralinktech.com/
23 */
24
25 #include <sys/param.h>
26 #include <sys/sysctl.h>
27 #include <sys/sockio.h>
28 #include <sys/mbuf.h>
29 #include <sys/kernel.h>
30 #include <sys/socket.h>
31 #include <sys/systm.h>
32 #include <sys/malloc.h>
33 #include <sys/lock.h>
34 #include <sys/mutex.h>
35 #include <sys/module.h>
36 #include <sys/bus.h>
37 #include <sys/endian.h>
38 #include <sys/firmware.h>
39
40 #include <machine/bus.h>
41 #include <machine/resource.h>
42 #include <sys/rman.h>
43
44 #include <net/bpf.h>
45 #include <net/if.h>
46 #include <net/if_var.h>
47 #include <net/if_arp.h>
48 #include <net/ethernet.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
51 #include <net/if_types.h>
52
53 #include <net80211/ieee80211_var.h>
54 #include <net80211/ieee80211_radiotap.h>
55 #include <net80211/ieee80211_regdomain.h>
56 #include <net80211/ieee80211_ratectl.h>
57
58 #include <netinet/in.h>
59 #include <netinet/in_systm.h>
60 #include <netinet/in_var.h>
61 #include <netinet/ip.h>
62 #include <netinet/if_ether.h>
63
64 #include <dev/ral/rt2661reg.h>
65 #include <dev/ral/rt2661var.h>
66
67 #define RAL_DEBUG
68 #ifdef RAL_DEBUG
69 #define DPRINTF(sc, fmt, ...) do { \
70 if (sc->sc_debug > 0) \
71 printf(fmt, __VA_ARGS__); \
72 } while (0)
73 #define DPRINTFN(sc, n, fmt, ...) do { \
74 if (sc->sc_debug >= (n)) \
75 printf(fmt, __VA_ARGS__); \
76 } while (0)
77 #else
78 #define DPRINTF(sc, fmt, ...)
79 #define DPRINTFN(sc, n, fmt, ...)
80 #endif
81
82 static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *,
83 const char [IFNAMSIZ], int, enum ieee80211_opmode,
84 int, const uint8_t [IEEE80211_ADDR_LEN],
85 const uint8_t [IEEE80211_ADDR_LEN]);
86 static void rt2661_vap_delete(struct ieee80211vap *);
87 static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int,
88 int);
89 static int rt2661_alloc_tx_ring(struct rt2661_softc *,
90 struct rt2661_tx_ring *, int);
91 static void rt2661_reset_tx_ring(struct rt2661_softc *,
92 struct rt2661_tx_ring *);
93 static void rt2661_free_tx_ring(struct rt2661_softc *,
94 struct rt2661_tx_ring *);
95 static int rt2661_alloc_rx_ring(struct rt2661_softc *,
96 struct rt2661_rx_ring *, int);
97 static void rt2661_reset_rx_ring(struct rt2661_softc *,
98 struct rt2661_rx_ring *);
99 static void rt2661_free_rx_ring(struct rt2661_softc *,
100 struct rt2661_rx_ring *);
101 static int rt2661_newstate(struct ieee80211vap *,
102 enum ieee80211_state, int);
103 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t);
104 static void rt2661_rx_intr(struct rt2661_softc *);
105 static void rt2661_tx_intr(struct rt2661_softc *);
106 static void rt2661_tx_dma_intr(struct rt2661_softc *,
107 struct rt2661_tx_ring *);
108 static void rt2661_mcu_beacon_expire(struct rt2661_softc *);
109 static void rt2661_mcu_wakeup(struct rt2661_softc *);
110 static void rt2661_mcu_cmd_intr(struct rt2661_softc *);
111 static void rt2661_scan_start(struct ieee80211com *);
112 static void rt2661_scan_end(struct ieee80211com *);
113 static void rt2661_getradiocaps(struct ieee80211com *, int, int *,
114 struct ieee80211_channel[]);
115 static void rt2661_set_channel(struct ieee80211com *);
116 static void rt2661_setup_tx_desc(struct rt2661_softc *,
117 struct rt2661_tx_desc *, uint32_t, uint16_t, int,
118 int, const bus_dma_segment_t *, int, int);
119 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *,
120 struct ieee80211_node *, int);
121 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *,
122 struct ieee80211_node *);
123 static int rt2661_transmit(struct ieee80211com *, struct mbuf *);
124 static void rt2661_start(struct rt2661_softc *);
125 static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *,
126 const struct ieee80211_bpf_params *);
127 static void rt2661_watchdog(void *);
128 static void rt2661_parent(struct ieee80211com *);
129 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t,
130 uint8_t);
131 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t);
132 static void rt2661_rf_write(struct rt2661_softc *, uint8_t,
133 uint32_t);
134 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t,
135 uint16_t);
136 static void rt2661_select_antenna(struct rt2661_softc *);
137 static void rt2661_enable_mrr(struct rt2661_softc *);
138 static void rt2661_set_txpreamble(struct rt2661_softc *);
139 static void rt2661_set_basicrates(struct rt2661_softc *,
140 const struct ieee80211_rateset *);
141 static void rt2661_select_band(struct rt2661_softc *,
142 struct ieee80211_channel *);
143 static void rt2661_set_chan(struct rt2661_softc *,
144 struct ieee80211_channel *);
145 static void rt2661_set_bssid(struct rt2661_softc *,
146 const uint8_t *);
147 static void rt2661_set_macaddr(struct rt2661_softc *,
148 const uint8_t *);
149 static void rt2661_update_promisc(struct ieee80211com *);
150 static int rt2661_wme_update(struct ieee80211com *) __unused;
151 static void rt2661_update_slot(struct ieee80211com *);
152 static const char *rt2661_get_rf(int);
153 static void rt2661_read_eeprom(struct rt2661_softc *,
154 uint8_t macaddr[IEEE80211_ADDR_LEN]);
155 static int rt2661_bbp_init(struct rt2661_softc *);
156 static void rt2661_init_locked(struct rt2661_softc *);
157 static void rt2661_init(void *);
158 static void rt2661_stop_locked(struct rt2661_softc *);
159 static void rt2661_stop(void *);
160 static int rt2661_load_microcode(struct rt2661_softc *);
161 #ifdef notyet
162 static void rt2661_rx_tune(struct rt2661_softc *);
163 static void rt2661_radar_start(struct rt2661_softc *);
164 static int rt2661_radar_stop(struct rt2661_softc *);
165 #endif
166 static int rt2661_prepare_beacon(struct rt2661_softc *,
167 struct ieee80211vap *);
168 static void rt2661_enable_tsf_sync(struct rt2661_softc *);
169 static void rt2661_enable_tsf(struct rt2661_softc *);
170 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t);
171
172 static const struct {
173 uint32_t reg;
174 uint32_t val;
175 } rt2661_def_mac[] = {
176 RT2661_DEF_MAC
177 };
178
179 static const struct {
180 uint8_t reg;
181 uint8_t val;
182 } rt2661_def_bbp[] = {
183 RT2661_DEF_BBP
184 };
185
186 static const struct rfprog {
187 uint8_t chan;
188 uint32_t r1, r2, r3, r4;
189 } rt2661_rf5225_1[] = {
190 RT2661_RF5225_1
191 }, rt2661_rf5225_2[] = {
192 RT2661_RF5225_2
193 };
194
195 static const uint8_t rt2661_chan_5ghz[] =
196 { 36, 40, 44, 48, 52, 56, 60, 64,
197 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140,
198 149, 153, 157, 161, 165 };
199
200 int
rt2661_attach(device_t dev,int id)201 rt2661_attach(device_t dev, int id)
202 {
203 struct rt2661_softc *sc = device_get_softc(dev);
204 struct ieee80211com *ic = &sc->sc_ic;
205 uint32_t val;
206 int error, ac, ntries;
207
208 sc->sc_id = id;
209 sc->sc_dev = dev;
210
211 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
212 MTX_DEF | MTX_RECURSE);
213
214 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0);
215 mbufq_init(&sc->sc_snd, ifqmaxlen);
216
217 /* wait for NIC to initialize */
218 for (ntries = 0; ntries < 1000; ntries++) {
219 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0)
220 break;
221 DELAY(1000);
222 }
223 if (ntries == 1000) {
224 device_printf(sc->sc_dev,
225 "timeout waiting for NIC to initialize\n");
226 error = EIO;
227 goto fail1;
228 }
229
230 /* retrieve RF rev. no and various other things from EEPROM */
231 rt2661_read_eeprom(sc, ic->ic_macaddr);
232
233 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val,
234 rt2661_get_rf(sc->rf_rev));
235
236 /*
237 * Allocate Tx and Rx rings.
238 */
239 for (ac = 0; ac < 4; ac++) {
240 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac],
241 RT2661_TX_RING_COUNT);
242 if (error != 0) {
243 device_printf(sc->sc_dev,
244 "could not allocate Tx ring %d\n", ac);
245 goto fail2;
246 }
247 }
248
249 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT);
250 if (error != 0) {
251 device_printf(sc->sc_dev, "could not allocate Mgt ring\n");
252 goto fail2;
253 }
254
255 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT);
256 if (error != 0) {
257 device_printf(sc->sc_dev, "could not allocate Rx ring\n");
258 goto fail3;
259 }
260
261 ic->ic_softc = sc;
262 ic->ic_name = device_get_nameunit(dev);
263 ic->ic_opmode = IEEE80211_M_STA;
264 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
265
266 /* set device capabilities */
267 ic->ic_caps =
268 IEEE80211_C_STA /* station mode */
269 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
270 | IEEE80211_C_HOSTAP /* hostap mode */
271 | IEEE80211_C_MONITOR /* monitor mode */
272 | IEEE80211_C_AHDEMO /* adhoc demo mode */
273 | IEEE80211_C_WDS /* 4-address traffic works */
274 | IEEE80211_C_MBSS /* mesh point link mode */
275 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
276 | IEEE80211_C_SHSLOT /* short slot time supported */
277 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
278 | IEEE80211_C_BGSCAN /* capable of bg scanning */
279 #ifdef notyet
280 | IEEE80211_C_TXFRAG /* handle tx frags */
281 | IEEE80211_C_WME /* 802.11e */
282 #endif
283 ;
284
285 rt2661_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
286 ic->ic_channels);
287
288 ieee80211_ifattach(ic);
289 #if 0
290 ic->ic_wme.wme_update = rt2661_wme_update;
291 #endif
292 ic->ic_scan_start = rt2661_scan_start;
293 ic->ic_scan_end = rt2661_scan_end;
294 ic->ic_getradiocaps = rt2661_getradiocaps;
295 ic->ic_set_channel = rt2661_set_channel;
296 ic->ic_updateslot = rt2661_update_slot;
297 ic->ic_update_promisc = rt2661_update_promisc;
298 ic->ic_raw_xmit = rt2661_raw_xmit;
299 ic->ic_transmit = rt2661_transmit;
300 ic->ic_parent = rt2661_parent;
301 ic->ic_vap_create = rt2661_vap_create;
302 ic->ic_vap_delete = rt2661_vap_delete;
303
304 ieee80211_radiotap_attach(ic,
305 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
306 RT2661_TX_RADIOTAP_PRESENT,
307 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
308 RT2661_RX_RADIOTAP_PRESENT);
309
310 #ifdef RAL_DEBUG
311 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
312 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
313 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs");
314 #endif
315 if (bootverbose)
316 ieee80211_announce(ic);
317
318 return 0;
319
320 fail3: rt2661_free_tx_ring(sc, &sc->mgtq);
321 fail2: while (--ac >= 0)
322 rt2661_free_tx_ring(sc, &sc->txq[ac]);
323 fail1: mtx_destroy(&sc->sc_mtx);
324 return error;
325 }
326
327 int
rt2661_detach(void * xsc)328 rt2661_detach(void *xsc)
329 {
330 struct rt2661_softc *sc = xsc;
331 struct ieee80211com *ic = &sc->sc_ic;
332
333 RAL_LOCK(sc);
334 rt2661_stop_locked(sc);
335 RAL_UNLOCK(sc);
336
337 ieee80211_ifdetach(ic);
338 mbufq_drain(&sc->sc_snd);
339
340 rt2661_free_tx_ring(sc, &sc->txq[0]);
341 rt2661_free_tx_ring(sc, &sc->txq[1]);
342 rt2661_free_tx_ring(sc, &sc->txq[2]);
343 rt2661_free_tx_ring(sc, &sc->txq[3]);
344 rt2661_free_tx_ring(sc, &sc->mgtq);
345 rt2661_free_rx_ring(sc, &sc->rxq);
346
347 mtx_destroy(&sc->sc_mtx);
348
349 return 0;
350 }
351
352 static struct ieee80211vap *
rt2661_vap_create(struct ieee80211com * ic,const char name[IFNAMSIZ],int unit,enum ieee80211_opmode opmode,int flags,const uint8_t bssid[IEEE80211_ADDR_LEN],const uint8_t mac[IEEE80211_ADDR_LEN])353 rt2661_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
354 enum ieee80211_opmode opmode, int flags,
355 const uint8_t bssid[IEEE80211_ADDR_LEN],
356 const uint8_t mac[IEEE80211_ADDR_LEN])
357 {
358 struct rt2661_softc *sc = ic->ic_softc;
359 struct rt2661_vap *rvp;
360 struct ieee80211vap *vap;
361
362 switch (opmode) {
363 case IEEE80211_M_STA:
364 case IEEE80211_M_IBSS:
365 case IEEE80211_M_AHDEMO:
366 case IEEE80211_M_MONITOR:
367 case IEEE80211_M_HOSTAP:
368 case IEEE80211_M_MBSS:
369 /* XXXRP: TBD */
370 if (!TAILQ_EMPTY(&ic->ic_vaps)) {
371 device_printf(sc->sc_dev, "only 1 vap supported\n");
372 return NULL;
373 }
374 if (opmode == IEEE80211_M_STA)
375 flags |= IEEE80211_CLONE_NOBEACONS;
376 break;
377 case IEEE80211_M_WDS:
378 if (TAILQ_EMPTY(&ic->ic_vaps) ||
379 ic->ic_opmode != IEEE80211_M_HOSTAP) {
380 device_printf(sc->sc_dev,
381 "wds only supported in ap mode\n");
382 return NULL;
383 }
384 /*
385 * Silently remove any request for a unique
386 * bssid; WDS vap's always share the local
387 * mac address.
388 */
389 flags &= ~IEEE80211_CLONE_BSSID;
390 break;
391 default:
392 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
393 return NULL;
394 }
395 rvp = malloc(sizeof(struct rt2661_vap), M_80211_VAP, M_WAITOK | M_ZERO);
396 vap = &rvp->ral_vap;
397 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid);
398
399 /* override state transition machine */
400 rvp->ral_newstate = vap->iv_newstate;
401 vap->iv_newstate = rt2661_newstate;
402 #if 0
403 vap->iv_update_beacon = rt2661_beacon_update;
404 #endif
405
406 ieee80211_ratectl_init(vap);
407 /* complete setup */
408 ieee80211_vap_attach(vap, ieee80211_media_change,
409 ieee80211_media_status, mac);
410 if (TAILQ_FIRST(&ic->ic_vaps) == vap)
411 ic->ic_opmode = opmode;
412 return vap;
413 }
414
415 static void
rt2661_vap_delete(struct ieee80211vap * vap)416 rt2661_vap_delete(struct ieee80211vap *vap)
417 {
418 struct rt2661_vap *rvp = RT2661_VAP(vap);
419
420 ieee80211_ratectl_deinit(vap);
421 ieee80211_vap_detach(vap);
422 free(rvp, M_80211_VAP);
423 }
424
425 void
rt2661_shutdown(void * xsc)426 rt2661_shutdown(void *xsc)
427 {
428 struct rt2661_softc *sc = xsc;
429
430 rt2661_stop(sc);
431 }
432
433 void
rt2661_suspend(void * xsc)434 rt2661_suspend(void *xsc)
435 {
436 struct rt2661_softc *sc = xsc;
437
438 rt2661_stop(sc);
439 }
440
441 void
rt2661_resume(void * xsc)442 rt2661_resume(void *xsc)
443 {
444 struct rt2661_softc *sc = xsc;
445
446 if (sc->sc_ic.ic_nrunning > 0)
447 rt2661_init(sc);
448 }
449
450 static void
rt2661_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)451 rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
452 {
453 if (error != 0)
454 return;
455
456 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
457
458 *(bus_addr_t *)arg = segs[0].ds_addr;
459 }
460
461 static int
rt2661_alloc_tx_ring(struct rt2661_softc * sc,struct rt2661_tx_ring * ring,int count)462 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring,
463 int count)
464 {
465 int i, error;
466
467 ring->count = count;
468 ring->queued = 0;
469 ring->cur = ring->next = ring->stat = 0;
470
471 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0,
472 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
473 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE,
474 0, NULL, NULL, &ring->desc_dmat);
475 if (error != 0) {
476 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
477 goto fail;
478 }
479
480 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
481 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
482 if (error != 0) {
483 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
484 goto fail;
485 }
486
487 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
488 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr,
489 0);
490 if (error != 0) {
491 device_printf(sc->sc_dev, "could not load desc DMA map\n");
492 goto fail;
493 }
494
495 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF,
496 M_NOWAIT | M_ZERO);
497 if (ring->data == NULL) {
498 device_printf(sc->sc_dev, "could not allocate soft data\n");
499 error = ENOMEM;
500 goto fail;
501 }
502
503 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
504 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
505 RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat);
506 if (error != 0) {
507 device_printf(sc->sc_dev, "could not create data DMA tag\n");
508 goto fail;
509 }
510
511 for (i = 0; i < count; i++) {
512 error = bus_dmamap_create(ring->data_dmat, 0,
513 &ring->data[i].map);
514 if (error != 0) {
515 device_printf(sc->sc_dev, "could not create DMA map\n");
516 goto fail;
517 }
518 }
519
520 return 0;
521
522 fail: rt2661_free_tx_ring(sc, ring);
523 return error;
524 }
525
526 static void
rt2661_reset_tx_ring(struct rt2661_softc * sc,struct rt2661_tx_ring * ring)527 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
528 {
529 struct rt2661_tx_desc *desc;
530 struct rt2661_tx_data *data;
531 int i;
532
533 for (i = 0; i < ring->count; i++) {
534 desc = &ring->desc[i];
535 data = &ring->data[i];
536
537 if (data->m != NULL) {
538 bus_dmamap_sync(ring->data_dmat, data->map,
539 BUS_DMASYNC_POSTWRITE);
540 bus_dmamap_unload(ring->data_dmat, data->map);
541 m_freem(data->m);
542 data->m = NULL;
543 }
544
545 if (data->ni != NULL) {
546 ieee80211_free_node(data->ni);
547 data->ni = NULL;
548 }
549
550 desc->flags = 0;
551 }
552
553 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
554
555 ring->queued = 0;
556 ring->cur = ring->next = ring->stat = 0;
557 }
558
559 static void
rt2661_free_tx_ring(struct rt2661_softc * sc,struct rt2661_tx_ring * ring)560 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
561 {
562 struct rt2661_tx_data *data;
563 int i;
564
565 if (ring->desc != NULL) {
566 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
567 BUS_DMASYNC_POSTWRITE);
568 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
569 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
570 }
571
572 if (ring->desc_dmat != NULL)
573 bus_dma_tag_destroy(ring->desc_dmat);
574
575 if (ring->data != NULL) {
576 for (i = 0; i < ring->count; i++) {
577 data = &ring->data[i];
578
579 if (data->m != NULL) {
580 bus_dmamap_sync(ring->data_dmat, data->map,
581 BUS_DMASYNC_POSTWRITE);
582 bus_dmamap_unload(ring->data_dmat, data->map);
583 m_freem(data->m);
584 }
585
586 if (data->ni != NULL)
587 ieee80211_free_node(data->ni);
588
589 if (data->map != NULL)
590 bus_dmamap_destroy(ring->data_dmat, data->map);
591 }
592
593 free(ring->data, M_DEVBUF);
594 }
595
596 if (ring->data_dmat != NULL)
597 bus_dma_tag_destroy(ring->data_dmat);
598 }
599
600 static int
rt2661_alloc_rx_ring(struct rt2661_softc * sc,struct rt2661_rx_ring * ring,int count)601 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring,
602 int count)
603 {
604 struct rt2661_rx_desc *desc;
605 struct rt2661_rx_data *data;
606 bus_addr_t physaddr;
607 int i, error;
608
609 ring->count = count;
610 ring->cur = ring->next = 0;
611
612 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0,
613 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
614 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE,
615 0, NULL, NULL, &ring->desc_dmat);
616 if (error != 0) {
617 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
618 goto fail;
619 }
620
621 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
622 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
623 if (error != 0) {
624 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
625 goto fail;
626 }
627
628 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
629 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr,
630 0);
631 if (error != 0) {
632 device_printf(sc->sc_dev, "could not load desc DMA map\n");
633 goto fail;
634 }
635
636 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF,
637 M_NOWAIT | M_ZERO);
638 if (ring->data == NULL) {
639 device_printf(sc->sc_dev, "could not allocate soft data\n");
640 error = ENOMEM;
641 goto fail;
642 }
643
644 /*
645 * Pre-allocate Rx buffers and populate Rx ring.
646 */
647 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
648 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
649 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat);
650 if (error != 0) {
651 device_printf(sc->sc_dev, "could not create data DMA tag\n");
652 goto fail;
653 }
654
655 for (i = 0; i < count; i++) {
656 desc = &sc->rxq.desc[i];
657 data = &sc->rxq.data[i];
658
659 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
660 if (error != 0) {
661 device_printf(sc->sc_dev, "could not create DMA map\n");
662 goto fail;
663 }
664
665 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
666 if (data->m == NULL) {
667 device_printf(sc->sc_dev,
668 "could not allocate rx mbuf\n");
669 error = ENOMEM;
670 goto fail;
671 }
672
673 error = bus_dmamap_load(ring->data_dmat, data->map,
674 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr,
675 &physaddr, 0);
676 if (error != 0) {
677 device_printf(sc->sc_dev,
678 "could not load rx buf DMA map");
679 goto fail;
680 }
681
682 desc->flags = htole32(RT2661_RX_BUSY);
683 desc->physaddr = htole32(physaddr);
684 }
685
686 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
687
688 return 0;
689
690 fail: rt2661_free_rx_ring(sc, ring);
691 return error;
692 }
693
694 static void
rt2661_reset_rx_ring(struct rt2661_softc * sc,struct rt2661_rx_ring * ring)695 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
696 {
697 int i;
698
699 for (i = 0; i < ring->count; i++)
700 ring->desc[i].flags = htole32(RT2661_RX_BUSY);
701
702 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
703
704 ring->cur = ring->next = 0;
705 }
706
707 static void
rt2661_free_rx_ring(struct rt2661_softc * sc,struct rt2661_rx_ring * ring)708 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
709 {
710 struct rt2661_rx_data *data;
711 int i;
712
713 if (ring->desc != NULL) {
714 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
715 BUS_DMASYNC_POSTWRITE);
716 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
717 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
718 }
719
720 if (ring->desc_dmat != NULL)
721 bus_dma_tag_destroy(ring->desc_dmat);
722
723 if (ring->data != NULL) {
724 for (i = 0; i < ring->count; i++) {
725 data = &ring->data[i];
726
727 if (data->m != NULL) {
728 bus_dmamap_sync(ring->data_dmat, data->map,
729 BUS_DMASYNC_POSTREAD);
730 bus_dmamap_unload(ring->data_dmat, data->map);
731 m_freem(data->m);
732 }
733
734 if (data->map != NULL)
735 bus_dmamap_destroy(ring->data_dmat, data->map);
736 }
737
738 free(ring->data, M_DEVBUF);
739 }
740
741 if (ring->data_dmat != NULL)
742 bus_dma_tag_destroy(ring->data_dmat);
743 }
744
745 static int
rt2661_newstate(struct ieee80211vap * vap,enum ieee80211_state nstate,int arg)746 rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
747 {
748 struct rt2661_vap *rvp = RT2661_VAP(vap);
749 struct ieee80211com *ic = vap->iv_ic;
750 struct rt2661_softc *sc = ic->ic_softc;
751 int error;
752
753 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) {
754 uint32_t tmp;
755
756 /* abort TSF synchronization */
757 tmp = RAL_READ(sc, RT2661_TXRX_CSR9);
758 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff);
759 }
760
761 error = rvp->ral_newstate(vap, nstate, arg);
762
763 if (error == 0 && nstate == IEEE80211_S_RUN) {
764 struct ieee80211_node *ni = vap->iv_bss;
765
766 if (vap->iv_opmode != IEEE80211_M_MONITOR) {
767 rt2661_enable_mrr(sc);
768 rt2661_set_txpreamble(sc);
769 rt2661_set_basicrates(sc, &ni->ni_rates);
770 rt2661_set_bssid(sc, ni->ni_bssid);
771 }
772
773 if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
774 vap->iv_opmode == IEEE80211_M_IBSS ||
775 vap->iv_opmode == IEEE80211_M_MBSS) {
776 error = rt2661_prepare_beacon(sc, vap);
777 if (error != 0)
778 return error;
779 }
780 if (vap->iv_opmode != IEEE80211_M_MONITOR)
781 rt2661_enable_tsf_sync(sc);
782 else
783 rt2661_enable_tsf(sc);
784 }
785 return error;
786 }
787
788 /*
789 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or
790 * 93C66).
791 */
792 static uint16_t
rt2661_eeprom_read(struct rt2661_softc * sc,uint8_t addr)793 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr)
794 {
795 uint32_t tmp;
796 uint16_t val;
797 int n;
798
799 /* clock C once before the first command */
800 RT2661_EEPROM_CTL(sc, 0);
801
802 RT2661_EEPROM_CTL(sc, RT2661_S);
803 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
804 RT2661_EEPROM_CTL(sc, RT2661_S);
805
806 /* write start bit (1) */
807 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
808 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
809
810 /* write READ opcode (10) */
811 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
812 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
813 RT2661_EEPROM_CTL(sc, RT2661_S);
814 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
815
816 /* write address (A5-A0 or A7-A0) */
817 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7;
818 for (; n >= 0; n--) {
819 RT2661_EEPROM_CTL(sc, RT2661_S |
820 (((addr >> n) & 1) << RT2661_SHIFT_D));
821 RT2661_EEPROM_CTL(sc, RT2661_S |
822 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C);
823 }
824
825 RT2661_EEPROM_CTL(sc, RT2661_S);
826
827 /* read data Q15-Q0 */
828 val = 0;
829 for (n = 15; n >= 0; n--) {
830 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
831 tmp = RAL_READ(sc, RT2661_E2PROM_CSR);
832 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n;
833 RT2661_EEPROM_CTL(sc, RT2661_S);
834 }
835
836 RT2661_EEPROM_CTL(sc, 0);
837
838 /* clear Chip Select and clock C */
839 RT2661_EEPROM_CTL(sc, RT2661_S);
840 RT2661_EEPROM_CTL(sc, 0);
841 RT2661_EEPROM_CTL(sc, RT2661_C);
842
843 return val;
844 }
845
846 static void
rt2661_tx_intr(struct rt2661_softc * sc)847 rt2661_tx_intr(struct rt2661_softc *sc)
848 {
849 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs;
850 struct rt2661_tx_ring *txq;
851 struct rt2661_tx_data *data;
852 uint32_t val;
853 int error, qid;
854
855 txs->flags = IEEE80211_RATECTL_TX_FAIL_LONG;
856 for (;;) {
857 struct ieee80211_node *ni;
858 struct mbuf *m;
859
860 val = RAL_READ(sc, RT2661_STA_CSR4);
861 if (!(val & RT2661_TX_STAT_VALID))
862 break;
863
864 /* retrieve the queue in which this frame was sent */
865 qid = RT2661_TX_QID(val);
866 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq;
867
868 /* retrieve rate control algorithm context */
869 data = &txq->data[txq->stat];
870 m = data->m;
871 data->m = NULL;
872 ni = data->ni;
873 data->ni = NULL;
874
875 /* if no frame has been sent, ignore */
876 if (ni == NULL)
877 continue;
878
879 switch (RT2661_TX_RESULT(val)) {
880 case RT2661_TX_SUCCESS:
881 txs->status = IEEE80211_RATECTL_TX_SUCCESS;
882 txs->long_retries = RT2661_TX_RETRYCNT(val);
883
884 DPRINTFN(sc, 10, "data frame sent successfully after "
885 "%d retries\n", txs->long_retries);
886 if (data->rix != IEEE80211_FIXED_RATE_NONE)
887 ieee80211_ratectl_tx_complete(ni, txs);
888 error = 0;
889 break;
890
891 case RT2661_TX_RETRY_FAIL:
892 txs->status = IEEE80211_RATECTL_TX_FAIL_LONG;
893 txs->long_retries = RT2661_TX_RETRYCNT(val);
894
895 DPRINTFN(sc, 9, "%s\n",
896 "sending data frame failed (too much retries)");
897 if (data->rix != IEEE80211_FIXED_RATE_NONE)
898 ieee80211_ratectl_tx_complete(ni, txs);
899 error = 1;
900 break;
901
902 default:
903 /* other failure */
904 device_printf(sc->sc_dev,
905 "sending data frame failed 0x%08x\n", val);
906 error = 1;
907 }
908
909 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat);
910
911 txq->queued--;
912 if (++txq->stat >= txq->count) /* faster than % count */
913 txq->stat = 0;
914
915 ieee80211_tx_complete(ni, m, error);
916 }
917
918 sc->sc_tx_timer = 0;
919
920 rt2661_start(sc);
921 }
922
923 static void
rt2661_tx_dma_intr(struct rt2661_softc * sc,struct rt2661_tx_ring * txq)924 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq)
925 {
926 struct rt2661_tx_desc *desc;
927 struct rt2661_tx_data *data;
928
929 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD);
930
931 for (;;) {
932 desc = &txq->desc[txq->next];
933 data = &txq->data[txq->next];
934
935 if ((le32toh(desc->flags) & RT2661_TX_BUSY) ||
936 !(le32toh(desc->flags) & RT2661_TX_VALID))
937 break;
938
939 bus_dmamap_sync(txq->data_dmat, data->map,
940 BUS_DMASYNC_POSTWRITE);
941 bus_dmamap_unload(txq->data_dmat, data->map);
942
943 /* descriptor is no longer valid */
944 desc->flags &= ~htole32(RT2661_TX_VALID);
945
946 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next);
947
948 if (++txq->next >= txq->count) /* faster than % count */
949 txq->next = 0;
950 }
951
952 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
953 }
954
955 static void
rt2661_rx_intr(struct rt2661_softc * sc)956 rt2661_rx_intr(struct rt2661_softc *sc)
957 {
958 struct ieee80211com *ic = &sc->sc_ic;
959 struct rt2661_rx_desc *desc;
960 struct rt2661_rx_data *data;
961 bus_addr_t physaddr;
962 struct ieee80211_frame *wh;
963 struct ieee80211_node *ni;
964 struct mbuf *mnew, *m;
965 int error;
966
967 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
968 BUS_DMASYNC_POSTREAD);
969
970 for (;;) {
971 int8_t rssi, nf;
972
973 desc = &sc->rxq.desc[sc->rxq.cur];
974 data = &sc->rxq.data[sc->rxq.cur];
975
976 if (le32toh(desc->flags) & RT2661_RX_BUSY)
977 break;
978
979 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) ||
980 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) {
981 /*
982 * This should not happen since we did not request
983 * to receive those frames when we filled TXRX_CSR0.
984 */
985 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n",
986 le32toh(desc->flags));
987 counter_u64_add(ic->ic_ierrors, 1);
988 goto skip;
989 }
990
991 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) {
992 counter_u64_add(ic->ic_ierrors, 1);
993 goto skip;
994 }
995
996 /*
997 * Try to allocate a new mbuf for this ring element and load it
998 * before processing the current mbuf. If the ring element
999 * cannot be loaded, drop the received packet and reuse the old
1000 * mbuf. In the unlikely case that the old mbuf can't be
1001 * reloaded either, explicitly panic.
1002 */
1003 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1004 if (mnew == NULL) {
1005 counter_u64_add(ic->ic_ierrors, 1);
1006 goto skip;
1007 }
1008
1009 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
1010 BUS_DMASYNC_POSTREAD);
1011 bus_dmamap_unload(sc->rxq.data_dmat, data->map);
1012
1013 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1014 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr,
1015 &physaddr, 0);
1016 if (error != 0) {
1017 m_freem(mnew);
1018
1019 /* try to reload the old mbuf */
1020 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1021 mtod(data->m, void *), MCLBYTES,
1022 rt2661_dma_map_addr, &physaddr, 0);
1023 if (error != 0) {
1024 /* very unlikely that it will fail... */
1025 panic("%s: could not load old rx mbuf",
1026 device_get_name(sc->sc_dev));
1027 }
1028 counter_u64_add(ic->ic_ierrors, 1);
1029 goto skip;
1030 }
1031
1032 /*
1033 * New mbuf successfully loaded, update Rx ring and continue
1034 * processing.
1035 */
1036 m = data->m;
1037 data->m = mnew;
1038 desc->physaddr = htole32(physaddr);
1039
1040 /* finalize mbuf */
1041 m->m_pkthdr.len = m->m_len =
1042 (le32toh(desc->flags) >> 16) & 0xfff;
1043
1044 rssi = rt2661_get_rssi(sc, desc->rssi);
1045 /* Error happened during RSSI conversion. */
1046 if (rssi < 0)
1047 rssi = -30; /* XXX ignored by net80211 */
1048 nf = RT2661_NOISE_FLOOR;
1049
1050 if (ieee80211_radiotap_active(ic)) {
1051 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap;
1052 uint32_t tsf_lo, tsf_hi;
1053
1054 /* get timestamp (low and high 32 bits) */
1055 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13);
1056 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12);
1057
1058 tap->wr_tsf =
1059 htole64(((uint64_t)tsf_hi << 32) | tsf_lo);
1060 tap->wr_flags = 0;
1061 tap->wr_rate = ieee80211_plcp2rate(desc->rate,
1062 (desc->flags & htole32(RT2661_RX_OFDM)) ?
1063 IEEE80211_T_OFDM : IEEE80211_T_CCK);
1064 tap->wr_antsignal = nf + rssi;
1065 tap->wr_antnoise = nf;
1066 }
1067 sc->sc_flags |= RAL_INPUT_RUNNING;
1068 RAL_UNLOCK(sc);
1069 wh = mtod(m, struct ieee80211_frame *);
1070
1071 /* send the frame to the 802.11 layer */
1072 ni = ieee80211_find_rxnode(ic,
1073 (struct ieee80211_frame_min *)wh);
1074 if (ni != NULL) {
1075 (void) ieee80211_input(ni, m, rssi, nf);
1076 ieee80211_free_node(ni);
1077 } else
1078 (void) ieee80211_input_all(ic, m, rssi, nf);
1079
1080 RAL_LOCK(sc);
1081 sc->sc_flags &= ~RAL_INPUT_RUNNING;
1082
1083 skip: desc->flags |= htole32(RT2661_RX_BUSY);
1084
1085 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur);
1086
1087 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT;
1088 }
1089
1090 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1091 BUS_DMASYNC_PREWRITE);
1092 }
1093
1094 /* ARGSUSED */
1095 static void
rt2661_mcu_beacon_expire(struct rt2661_softc * sc)1096 rt2661_mcu_beacon_expire(struct rt2661_softc *sc)
1097 {
1098 /* do nothing */
1099 }
1100
1101 static void
rt2661_mcu_wakeup(struct rt2661_softc * sc)1102 rt2661_mcu_wakeup(struct rt2661_softc *sc)
1103 {
1104 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16);
1105
1106 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7);
1107 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18);
1108 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20);
1109
1110 /* send wakeup command to MCU */
1111 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0);
1112 }
1113
1114 static void
rt2661_mcu_cmd_intr(struct rt2661_softc * sc)1115 rt2661_mcu_cmd_intr(struct rt2661_softc *sc)
1116 {
1117 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR);
1118 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
1119 }
1120
1121 void
rt2661_intr(void * arg)1122 rt2661_intr(void *arg)
1123 {
1124 struct rt2661_softc *sc = arg;
1125 uint32_t r1, r2;
1126
1127 RAL_LOCK(sc);
1128
1129 /* disable MAC and MCU interrupts */
1130 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
1131 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
1132
1133 /* don't re-enable interrupts if we're shutting down */
1134 if (!(sc->sc_flags & RAL_RUNNING)) {
1135 RAL_UNLOCK(sc);
1136 return;
1137 }
1138
1139 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR);
1140 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1);
1141
1142 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR);
1143 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2);
1144
1145 if (r1 & RT2661_MGT_DONE)
1146 rt2661_tx_dma_intr(sc, &sc->mgtq);
1147
1148 if (r1 & RT2661_RX_DONE)
1149 rt2661_rx_intr(sc);
1150
1151 if (r1 & RT2661_TX0_DMA_DONE)
1152 rt2661_tx_dma_intr(sc, &sc->txq[0]);
1153
1154 if (r1 & RT2661_TX1_DMA_DONE)
1155 rt2661_tx_dma_intr(sc, &sc->txq[1]);
1156
1157 if (r1 & RT2661_TX2_DMA_DONE)
1158 rt2661_tx_dma_intr(sc, &sc->txq[2]);
1159
1160 if (r1 & RT2661_TX3_DMA_DONE)
1161 rt2661_tx_dma_intr(sc, &sc->txq[3]);
1162
1163 if (r1 & RT2661_TX_DONE)
1164 rt2661_tx_intr(sc);
1165
1166 if (r2 & RT2661_MCU_CMD_DONE)
1167 rt2661_mcu_cmd_intr(sc);
1168
1169 if (r2 & RT2661_MCU_BEACON_EXPIRE)
1170 rt2661_mcu_beacon_expire(sc);
1171
1172 if (r2 & RT2661_MCU_WAKEUP)
1173 rt2661_mcu_wakeup(sc);
1174
1175 /* re-enable MAC and MCU interrupts */
1176 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
1177 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
1178
1179 RAL_UNLOCK(sc);
1180 }
1181
1182 static uint8_t
rt2661_plcp_signal(int rate)1183 rt2661_plcp_signal(int rate)
1184 {
1185 switch (rate) {
1186 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
1187 case 12: return 0xb;
1188 case 18: return 0xf;
1189 case 24: return 0xa;
1190 case 36: return 0xe;
1191 case 48: return 0x9;
1192 case 72: return 0xd;
1193 case 96: return 0x8;
1194 case 108: return 0xc;
1195
1196 /* CCK rates (NB: not IEEE std, device-specific) */
1197 case 2: return 0x0;
1198 case 4: return 0x1;
1199 case 11: return 0x2;
1200 case 22: return 0x3;
1201 }
1202 return 0xff; /* XXX unsupported/unknown rate */
1203 }
1204
1205 static void
rt2661_setup_tx_desc(struct rt2661_softc * sc,struct rt2661_tx_desc * desc,uint32_t flags,uint16_t xflags,int len,int rate,const bus_dma_segment_t * segs,int nsegs,int ac)1206 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc,
1207 uint32_t flags, uint16_t xflags, int len, int rate,
1208 const bus_dma_segment_t *segs, int nsegs, int ac)
1209 {
1210 struct ieee80211com *ic = &sc->sc_ic;
1211 uint16_t plcp_length;
1212 int i, remainder;
1213
1214 desc->flags = htole32(flags);
1215 desc->flags |= htole32(len << 16);
1216 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID);
1217
1218 desc->xflags = htole16(xflags);
1219 desc->xflags |= htole16(nsegs << 13);
1220
1221 desc->wme = htole16(
1222 RT2661_QID(ac) |
1223 RT2661_AIFSN(2) |
1224 RT2661_LOGCWMIN(4) |
1225 RT2661_LOGCWMAX(10));
1226
1227 /*
1228 * Remember in which queue this frame was sent. This field is driver
1229 * private data only. It will be made available by the NIC in STA_CSR4
1230 * on Tx interrupts.
1231 */
1232 desc->qid = ac;
1233
1234 /* setup PLCP fields */
1235 desc->plcp_signal = rt2661_plcp_signal(rate);
1236 desc->plcp_service = 4;
1237
1238 len += IEEE80211_CRC_LEN;
1239 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) {
1240 desc->flags |= htole32(RT2661_TX_OFDM);
1241
1242 plcp_length = len & 0xfff;
1243 desc->plcp_length_hi = plcp_length >> 6;
1244 desc->plcp_length_lo = plcp_length & 0x3f;
1245 } else {
1246 plcp_length = howmany(16 * len, rate);
1247 if (rate == 22) {
1248 remainder = (16 * len) % 22;
1249 if (remainder != 0 && remainder < 7)
1250 desc->plcp_service |= RT2661_PLCP_LENGEXT;
1251 }
1252 desc->plcp_length_hi = plcp_length >> 8;
1253 desc->plcp_length_lo = plcp_length & 0xff;
1254
1255 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1256 desc->plcp_signal |= 0x08;
1257 }
1258
1259 /* RT2x61 supports scatter with up to 5 segments */
1260 for (i = 0; i < nsegs; i++) {
1261 desc->addr[i] = htole32(segs[i].ds_addr);
1262 desc->len [i] = htole16(segs[i].ds_len);
1263 }
1264 }
1265
1266 static int
rt2661_tx_mgt(struct rt2661_softc * sc,struct mbuf * m0,struct ieee80211_node * ni)1267 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0,
1268 struct ieee80211_node *ni)
1269 {
1270 struct ieee80211vap *vap = ni->ni_vap;
1271 struct ieee80211com *ic = ni->ni_ic;
1272 struct rt2661_tx_desc *desc;
1273 struct rt2661_tx_data *data;
1274 struct ieee80211_frame *wh;
1275 struct ieee80211_key *k;
1276 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
1277 uint16_t dur;
1278 uint32_t flags = 0; /* XXX HWSEQ */
1279 int nsegs, rate, error;
1280
1281 desc = &sc->mgtq.desc[sc->mgtq.cur];
1282 data = &sc->mgtq.data[sc->mgtq.cur];
1283
1284 rate = ni->ni_txparms->mgmtrate;
1285
1286 wh = mtod(m0, struct ieee80211_frame *);
1287
1288 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1289 k = ieee80211_crypto_encap(ni, m0);
1290 if (k == NULL) {
1291 m_freem(m0);
1292 return ENOBUFS;
1293 }
1294 }
1295
1296 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0,
1297 segs, &nsegs, 0);
1298 if (error != 0) {
1299 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1300 error);
1301 m_freem(m0);
1302 return error;
1303 }
1304
1305 if (ieee80211_radiotap_active_vap(vap)) {
1306 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap;
1307
1308 tap->wt_flags = 0;
1309 tap->wt_rate = rate;
1310
1311 ieee80211_radiotap_tx(vap, m0);
1312 }
1313
1314 data->m = m0;
1315 data->ni = ni;
1316 /* management frames are not taken into account for amrr */
1317 data->rix = IEEE80211_FIXED_RATE_NONE;
1318
1319 wh = mtod(m0, struct ieee80211_frame *);
1320
1321 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1322 flags |= RT2661_TX_NEED_ACK;
1323
1324 dur = ieee80211_ack_duration(ic->ic_rt,
1325 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
1326 *(uint16_t *)wh->i_dur = htole16(dur);
1327
1328 /* tell hardware to add timestamp in probe responses */
1329 if (IEEE80211_IS_MGMT_PROBE_RESP(wh))
1330 flags |= RT2661_TX_TIMESTAMP;
1331 }
1332
1333 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */,
1334 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT);
1335
1336 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1337 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map,
1338 BUS_DMASYNC_PREWRITE);
1339
1340 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n",
1341 m0->m_pkthdr.len, sc->mgtq.cur, rate);
1342
1343 /* kick mgt */
1344 sc->mgtq.queued++;
1345 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT;
1346 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT);
1347
1348 return 0;
1349 }
1350
1351 static int
rt2661_sendprot(struct rt2661_softc * sc,int ac,const struct mbuf * m,struct ieee80211_node * ni,int prot,int rate)1352 rt2661_sendprot(struct rt2661_softc *sc, int ac,
1353 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate)
1354 {
1355 struct ieee80211com *ic = ni->ni_ic;
1356 struct rt2661_tx_ring *txq = &sc->txq[ac];
1357 struct rt2661_tx_desc *desc;
1358 struct rt2661_tx_data *data;
1359 struct mbuf *mprot;
1360 int protrate, flags, error;
1361 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
1362 int nsegs;
1363
1364 mprot = ieee80211_alloc_prot(ni, m, rate, prot);
1365 if (mprot == NULL) {
1366 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1);
1367 device_printf(sc->sc_dev,
1368 "could not allocate mbuf for protection mode %d\n", prot);
1369 return ENOBUFS;
1370 }
1371
1372 data = &txq->data[txq->cur];
1373 desc = &txq->desc[txq->cur];
1374
1375 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs,
1376 &nsegs, 0);
1377 if (error != 0) {
1378 device_printf(sc->sc_dev,
1379 "could not map mbuf (error %d)\n", error);
1380 m_freem(mprot);
1381 return error;
1382 }
1383
1384 data->m = mprot;
1385 data->ni = ieee80211_ref_node(ni);
1386 /* ctl frames are not taken into account for amrr */
1387 data->rix = IEEE80211_FIXED_RATE_NONE;
1388
1389 protrate = ieee80211_ctl_rate(ic->ic_rt, rate);
1390 flags = RT2661_TX_MORE_FRAG;
1391 if (prot == IEEE80211_PROT_RTSCTS)
1392 flags |= RT2661_TX_NEED_ACK;
1393
1394 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len,
1395 protrate, segs, 1, ac);
1396
1397 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1398 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1399
1400 txq->queued++;
1401 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1402
1403 return 0;
1404 }
1405
1406 static int
rt2661_tx_data(struct rt2661_softc * sc,struct mbuf * m0,struct ieee80211_node * ni,int ac)1407 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0,
1408 struct ieee80211_node *ni, int ac)
1409 {
1410 struct ieee80211vap *vap = ni->ni_vap;
1411 struct ieee80211com *ic = &sc->sc_ic;
1412 struct rt2661_tx_ring *txq = &sc->txq[ac];
1413 struct rt2661_tx_desc *desc;
1414 struct rt2661_tx_data *data;
1415 struct ieee80211_frame *wh;
1416 const struct ieee80211_txparam *tp = ni->ni_txparms;
1417 struct ieee80211_key *k;
1418 struct mbuf *mnew;
1419 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
1420 uint16_t dur;
1421 uint32_t flags;
1422 int error, nsegs, rate, noack = 0;
1423
1424 wh = mtod(m0, struct ieee80211_frame *);
1425
1426 if (m0->m_flags & M_EAPOL) {
1427 rate = tp->mgmtrate;
1428 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1429 rate = tp->mcastrate;
1430 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
1431 rate = tp->ucastrate;
1432 } else {
1433 (void) ieee80211_ratectl_rate(ni, NULL, 0);
1434 rate = ni->ni_txrate;
1435 }
1436 rate &= IEEE80211_RATE_VAL;
1437
1438 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS_DATA)
1439 noack = !! ieee80211_wme_vap_ac_is_noack(vap, ac);
1440
1441 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1442 k = ieee80211_crypto_encap(ni, m0);
1443 if (k == NULL) {
1444 m_freem(m0);
1445 return ENOBUFS;
1446 }
1447
1448 /* packet header may have moved, reset our local pointer */
1449 wh = mtod(m0, struct ieee80211_frame *);
1450 }
1451
1452 flags = 0;
1453 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1454 int prot = IEEE80211_PROT_NONE;
1455 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold)
1456 prot = IEEE80211_PROT_RTSCTS;
1457 else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1458 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM)
1459 prot = ic->ic_protmode;
1460 if (prot != IEEE80211_PROT_NONE) {
1461 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate);
1462 if (error) {
1463 m_freem(m0);
1464 return error;
1465 }
1466 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS;
1467 }
1468 }
1469
1470 data = &txq->data[txq->cur];
1471 desc = &txq->desc[txq->cur];
1472
1473 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs,
1474 &nsegs, 0);
1475 if (error != 0 && error != EFBIG) {
1476 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1477 error);
1478 m_freem(m0);
1479 return error;
1480 }
1481 if (error != 0) {
1482 mnew = m_defrag(m0, M_NOWAIT);
1483 if (mnew == NULL) {
1484 device_printf(sc->sc_dev,
1485 "could not defragment mbuf\n");
1486 m_freem(m0);
1487 return ENOBUFS;
1488 }
1489 m0 = mnew;
1490
1491 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0,
1492 segs, &nsegs, 0);
1493 if (error != 0) {
1494 device_printf(sc->sc_dev,
1495 "could not map mbuf (error %d)\n", error);
1496 m_freem(m0);
1497 return error;
1498 }
1499
1500 /* packet header have moved, reset our local pointer */
1501 wh = mtod(m0, struct ieee80211_frame *);
1502 }
1503
1504 if (ieee80211_radiotap_active_vap(vap)) {
1505 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap;
1506
1507 tap->wt_flags = 0;
1508 tap->wt_rate = rate;
1509
1510 ieee80211_radiotap_tx(vap, m0);
1511 }
1512
1513 data->m = m0;
1514 data->ni = ni;
1515
1516 /* remember link conditions for rate adaptation algorithm */
1517 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) {
1518 data->rix = ni->ni_txrate;
1519 /* XXX probably need last rssi value and not avg */
1520 data->rssi = ic->ic_node_getrssi(ni);
1521 } else
1522 data->rix = IEEE80211_FIXED_RATE_NONE;
1523
1524 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1525 flags |= RT2661_TX_NEED_ACK;
1526
1527 dur = ieee80211_ack_duration(ic->ic_rt,
1528 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
1529 *(uint16_t *)wh->i_dur = htole16(dur);
1530 }
1531
1532 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs,
1533 nsegs, ac);
1534
1535 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1536 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1537
1538 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n",
1539 m0->m_pkthdr.len, txq->cur, rate);
1540
1541 /* kick Tx */
1542 txq->queued++;
1543 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1544 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac);
1545
1546 return 0;
1547 }
1548
1549 static int
rt2661_transmit(struct ieee80211com * ic,struct mbuf * m)1550 rt2661_transmit(struct ieee80211com *ic, struct mbuf *m)
1551 {
1552 struct rt2661_softc *sc = ic->ic_softc;
1553 int error;
1554
1555 RAL_LOCK(sc);
1556 if ((sc->sc_flags & RAL_RUNNING) == 0) {
1557 RAL_UNLOCK(sc);
1558 return (ENXIO);
1559 }
1560 error = mbufq_enqueue(&sc->sc_snd, m);
1561 if (error) {
1562 RAL_UNLOCK(sc);
1563 return (error);
1564 }
1565 rt2661_start(sc);
1566 RAL_UNLOCK(sc);
1567
1568 return (0);
1569 }
1570
1571 static void
rt2661_start(struct rt2661_softc * sc)1572 rt2661_start(struct rt2661_softc *sc)
1573 {
1574 struct mbuf *m;
1575 struct ieee80211_node *ni;
1576 int ac;
1577
1578 RAL_LOCK_ASSERT(sc);
1579
1580 /* prevent management frames from being sent if we're not ready */
1581 if (!(sc->sc_flags & RAL_RUNNING) || sc->sc_invalid)
1582 return;
1583
1584 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1585 ac = M_WME_GETAC(m);
1586 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) {
1587 /* there is no place left in this ring */
1588 mbufq_prepend(&sc->sc_snd, m);
1589 break;
1590 }
1591 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1592 if (rt2661_tx_data(sc, m, ni, ac) != 0) {
1593 if_inc_counter(ni->ni_vap->iv_ifp,
1594 IFCOUNTER_OERRORS, 1);
1595 ieee80211_free_node(ni);
1596 break;
1597 }
1598 sc->sc_tx_timer = 5;
1599 }
1600 }
1601
1602 static int
rt2661_raw_xmit(struct ieee80211_node * ni,struct mbuf * m,const struct ieee80211_bpf_params * params)1603 rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1604 const struct ieee80211_bpf_params *params)
1605 {
1606 struct ieee80211com *ic = ni->ni_ic;
1607 struct rt2661_softc *sc = ic->ic_softc;
1608
1609 RAL_LOCK(sc);
1610
1611 /* prevent management frames from being sent if we're not ready */
1612 if (!(sc->sc_flags & RAL_RUNNING)) {
1613 RAL_UNLOCK(sc);
1614 m_freem(m);
1615 return ENETDOWN;
1616 }
1617 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) {
1618 RAL_UNLOCK(sc);
1619 m_freem(m);
1620 return ENOBUFS; /* XXX */
1621 }
1622
1623 /*
1624 * Legacy path; interpret frame contents to decide
1625 * precisely how to send the frame.
1626 * XXX raw path
1627 */
1628 if (rt2661_tx_mgt(sc, m, ni) != 0)
1629 goto bad;
1630 sc->sc_tx_timer = 5;
1631
1632 RAL_UNLOCK(sc);
1633
1634 return 0;
1635 bad:
1636 RAL_UNLOCK(sc);
1637 return EIO; /* XXX */
1638 }
1639
1640 static void
rt2661_watchdog(void * arg)1641 rt2661_watchdog(void *arg)
1642 {
1643 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
1644
1645 RAL_LOCK_ASSERT(sc);
1646
1647 KASSERT(sc->sc_flags & RAL_RUNNING, ("not running"));
1648
1649 if (sc->sc_invalid) /* card ejected */
1650 return;
1651
1652 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) {
1653 device_printf(sc->sc_dev, "device timeout\n");
1654 rt2661_init_locked(sc);
1655 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1656 /* NB: callout is reset in rt2661_init() */
1657 return;
1658 }
1659 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc);
1660 }
1661
1662 static void
rt2661_parent(struct ieee80211com * ic)1663 rt2661_parent(struct ieee80211com *ic)
1664 {
1665 struct rt2661_softc *sc = ic->ic_softc;
1666 int startall = 0;
1667
1668 RAL_LOCK(sc);
1669 if (ic->ic_nrunning > 0) {
1670 if ((sc->sc_flags & RAL_RUNNING) == 0) {
1671 rt2661_init_locked(sc);
1672 startall = 1;
1673 } else
1674 rt2661_update_promisc(ic);
1675 } else if (sc->sc_flags & RAL_RUNNING)
1676 rt2661_stop_locked(sc);
1677 RAL_UNLOCK(sc);
1678 if (startall)
1679 ieee80211_start_all(ic);
1680 }
1681
1682 static void
rt2661_bbp_write(struct rt2661_softc * sc,uint8_t reg,uint8_t val)1683 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)
1684 {
1685 uint32_t tmp;
1686 int ntries;
1687
1688 for (ntries = 0; ntries < 100; ntries++) {
1689 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
1690 break;
1691 DELAY(1);
1692 }
1693 if (ntries == 100) {
1694 device_printf(sc->sc_dev, "could not write to BBP\n");
1695 return;
1696 }
1697
1698 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
1699 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp);
1700
1701 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val);
1702 }
1703
1704 static uint8_t
rt2661_bbp_read(struct rt2661_softc * sc,uint8_t reg)1705 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg)
1706 {
1707 uint32_t val;
1708 int ntries;
1709
1710 for (ntries = 0; ntries < 100; ntries++) {
1711 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
1712 break;
1713 DELAY(1);
1714 }
1715 if (ntries == 100) {
1716 device_printf(sc->sc_dev, "could not read from BBP\n");
1717 return 0;
1718 }
1719
1720 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;
1721 RAL_WRITE(sc, RT2661_PHY_CSR3, val);
1722
1723 for (ntries = 0; ntries < 100; ntries++) {
1724 val = RAL_READ(sc, RT2661_PHY_CSR3);
1725 if (!(val & RT2661_BBP_BUSY))
1726 return val & 0xff;
1727 DELAY(1);
1728 }
1729
1730 device_printf(sc->sc_dev, "could not read from BBP\n");
1731 return 0;
1732 }
1733
1734 static void
rt2661_rf_write(struct rt2661_softc * sc,uint8_t reg,uint32_t val)1735 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)
1736 {
1737 uint32_t tmp;
1738 int ntries;
1739
1740 for (ntries = 0; ntries < 100; ntries++) {
1741 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY))
1742 break;
1743 DELAY(1);
1744 }
1745 if (ntries == 100) {
1746 device_printf(sc->sc_dev, "could not write to RF\n");
1747 return;
1748 }
1749
1750 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 |
1751 (reg & 3);
1752 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp);
1753
1754 /* remember last written value in sc */
1755 sc->rf_regs[reg] = val;
1756
1757 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff);
1758 }
1759
1760 static int
rt2661_tx_cmd(struct rt2661_softc * sc,uint8_t cmd,uint16_t arg)1761 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg)
1762 {
1763 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY)
1764 return EIO; /* there is already a command pending */
1765
1766 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR,
1767 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg);
1768
1769 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd);
1770
1771 return 0;
1772 }
1773
1774 static void
rt2661_select_antenna(struct rt2661_softc * sc)1775 rt2661_select_antenna(struct rt2661_softc *sc)
1776 {
1777 uint8_t bbp4, bbp77;
1778 uint32_t tmp;
1779
1780 bbp4 = rt2661_bbp_read(sc, 4);
1781 bbp77 = rt2661_bbp_read(sc, 77);
1782
1783 /* TBD */
1784
1785 /* make sure Rx is disabled before switching antenna */
1786 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
1787 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
1788
1789 rt2661_bbp_write(sc, 4, bbp4);
1790 rt2661_bbp_write(sc, 77, bbp77);
1791
1792 /* restore Rx filter */
1793 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
1794 }
1795
1796 /*
1797 * Enable multi-rate retries for frames sent at OFDM rates.
1798 * In 802.11b/g mode, allow fallback to CCK rates.
1799 */
1800 static void
rt2661_enable_mrr(struct rt2661_softc * sc)1801 rt2661_enable_mrr(struct rt2661_softc *sc)
1802 {
1803 struct ieee80211com *ic = &sc->sc_ic;
1804 uint32_t tmp;
1805
1806 tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
1807
1808 tmp &= ~RT2661_MRR_CCK_FALLBACK;
1809 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan))
1810 tmp |= RT2661_MRR_CCK_FALLBACK;
1811 tmp |= RT2661_MRR_ENABLED;
1812
1813 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1814 }
1815
1816 static void
rt2661_set_txpreamble(struct rt2661_softc * sc)1817 rt2661_set_txpreamble(struct rt2661_softc *sc)
1818 {
1819 struct ieee80211com *ic = &sc->sc_ic;
1820 uint32_t tmp;
1821
1822 tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
1823
1824 tmp &= ~RT2661_SHORT_PREAMBLE;
1825 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1826 tmp |= RT2661_SHORT_PREAMBLE;
1827
1828 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1829 }
1830
1831 static void
rt2661_set_basicrates(struct rt2661_softc * sc,const struct ieee80211_rateset * rs)1832 rt2661_set_basicrates(struct rt2661_softc *sc,
1833 const struct ieee80211_rateset *rs)
1834 {
1835 struct ieee80211com *ic = &sc->sc_ic;
1836 uint32_t mask = 0;
1837 uint8_t rate;
1838 int i;
1839
1840 for (i = 0; i < rs->rs_nrates; i++) {
1841 rate = rs->rs_rates[i];
1842
1843 if (!(rate & IEEE80211_RATE_BASIC))
1844 continue;
1845
1846 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt,
1847 IEEE80211_RV(rate));
1848 }
1849
1850 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask);
1851
1852 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask);
1853 }
1854
1855 /*
1856 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference
1857 * driver.
1858 */
1859 static void
rt2661_select_band(struct rt2661_softc * sc,struct ieee80211_channel * c)1860 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c)
1861 {
1862 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104;
1863 uint32_t tmp;
1864
1865 /* update all BBP registers that depend on the band */
1866 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c;
1867 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48;
1868 if (IEEE80211_IS_CHAN_5GHZ(c)) {
1869 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c;
1870 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10;
1871 }
1872 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
1873 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
1874 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10;
1875 }
1876
1877 rt2661_bbp_write(sc, 17, bbp17);
1878 rt2661_bbp_write(sc, 96, bbp96);
1879 rt2661_bbp_write(sc, 104, bbp104);
1880
1881 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
1882 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
1883 rt2661_bbp_write(sc, 75, 0x80);
1884 rt2661_bbp_write(sc, 86, 0x80);
1885 rt2661_bbp_write(sc, 88, 0x80);
1886 }
1887
1888 rt2661_bbp_write(sc, 35, bbp35);
1889 rt2661_bbp_write(sc, 97, bbp97);
1890 rt2661_bbp_write(sc, 98, bbp98);
1891
1892 tmp = RAL_READ(sc, RT2661_PHY_CSR0);
1893 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ);
1894 if (IEEE80211_IS_CHAN_2GHZ(c))
1895 tmp |= RT2661_PA_PE_2GHZ;
1896 else
1897 tmp |= RT2661_PA_PE_5GHZ;
1898 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp);
1899 }
1900
1901 static void
rt2661_set_chan(struct rt2661_softc * sc,struct ieee80211_channel * c)1902 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c)
1903 {
1904 struct ieee80211com *ic = &sc->sc_ic;
1905 const struct rfprog *rfprog;
1906 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT;
1907 int8_t power;
1908 u_int i, chan;
1909
1910 chan = ieee80211_chan2ieee(ic, c);
1911 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan));
1912
1913 /* select the appropriate RF settings based on what EEPROM says */
1914 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2;
1915
1916 /* find the settings for this channel (we know it exists) */
1917 for (i = 0; rfprog[i].chan != chan; i++);
1918
1919 power = sc->txpow[i];
1920 if (power < 0) {
1921 bbp94 += power;
1922 power = 0;
1923 } else if (power > 31) {
1924 bbp94 += power - 31;
1925 power = 31;
1926 }
1927
1928 /*
1929 * If we are switching from the 2GHz band to the 5GHz band or
1930 * vice-versa, BBP registers need to be reprogrammed.
1931 */
1932 if (c->ic_flags != sc->sc_curchan->ic_flags) {
1933 rt2661_select_band(sc, c);
1934 rt2661_select_antenna(sc);
1935 }
1936 sc->sc_curchan = c;
1937
1938 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
1939 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
1940 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
1941 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
1942
1943 DELAY(200);
1944
1945 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
1946 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
1947 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1);
1948 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
1949
1950 DELAY(200);
1951
1952 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
1953 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
1954 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
1955 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
1956
1957 /* enable smart mode for MIMO-capable RFs */
1958 bbp3 = rt2661_bbp_read(sc, 3);
1959
1960 bbp3 &= ~RT2661_SMART_MODE;
1961 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529)
1962 bbp3 |= RT2661_SMART_MODE;
1963
1964 rt2661_bbp_write(sc, 3, bbp3);
1965
1966 if (bbp94 != RT2661_BBPR94_DEFAULT)
1967 rt2661_bbp_write(sc, 94, bbp94);
1968
1969 /* 5GHz radio needs a 1ms delay here */
1970 if (IEEE80211_IS_CHAN_5GHZ(c))
1971 DELAY(1000);
1972 }
1973
1974 static void
rt2661_set_bssid(struct rt2661_softc * sc,const uint8_t * bssid)1975 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid)
1976 {
1977 uint32_t tmp;
1978
1979 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
1980 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp);
1981
1982 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16;
1983 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp);
1984 }
1985
1986 static void
rt2661_set_macaddr(struct rt2661_softc * sc,const uint8_t * addr)1987 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr)
1988 {
1989 uint32_t tmp;
1990
1991 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
1992 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp);
1993
1994 tmp = addr[4] | addr[5] << 8;
1995 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp);
1996 }
1997
1998 static void
rt2661_update_promisc(struct ieee80211com * ic)1999 rt2661_update_promisc(struct ieee80211com *ic)
2000 {
2001 struct rt2661_softc *sc = ic->ic_softc;
2002 uint32_t tmp;
2003
2004 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2005
2006 tmp &= ~RT2661_DROP_NOT_TO_ME;
2007 if (ic->ic_promisc == 0)
2008 tmp |= RT2661_DROP_NOT_TO_ME;
2009
2010 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2011
2012 DPRINTF(sc, "%s promiscuous mode\n",
2013 (ic->ic_promisc > 0) ? "entering" : "leaving");
2014 }
2015
2016 /*
2017 * Update QoS (802.11e) settings for each h/w Tx ring.
2018 */
2019 static int
rt2661_wme_update(struct ieee80211com * ic)2020 rt2661_wme_update(struct ieee80211com *ic)
2021 {
2022 struct rt2661_softc *sc = ic->ic_softc;
2023 struct chanAccParams chp;
2024 const struct wmeParams *wmep;
2025
2026 ieee80211_wme_ic_getparams(ic, &chp);
2027
2028 wmep = chp.cap_wmeParams;
2029
2030 /* XXX: not sure about shifts. */
2031 /* XXX: the reference driver plays with AC_VI settings too. */
2032
2033 /* update TxOp */
2034 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0,
2035 wmep[WME_AC_BE].wmep_txopLimit << 16 |
2036 wmep[WME_AC_BK].wmep_txopLimit);
2037 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1,
2038 wmep[WME_AC_VI].wmep_txopLimit << 16 |
2039 wmep[WME_AC_VO].wmep_txopLimit);
2040
2041 /* update CWmin */
2042 RAL_WRITE(sc, RT2661_CWMIN_CSR,
2043 wmep[WME_AC_BE].wmep_logcwmin << 12 |
2044 wmep[WME_AC_BK].wmep_logcwmin << 8 |
2045 wmep[WME_AC_VI].wmep_logcwmin << 4 |
2046 wmep[WME_AC_VO].wmep_logcwmin);
2047
2048 /* update CWmax */
2049 RAL_WRITE(sc, RT2661_CWMAX_CSR,
2050 wmep[WME_AC_BE].wmep_logcwmax << 12 |
2051 wmep[WME_AC_BK].wmep_logcwmax << 8 |
2052 wmep[WME_AC_VI].wmep_logcwmax << 4 |
2053 wmep[WME_AC_VO].wmep_logcwmax);
2054
2055 /* update Aifsn */
2056 RAL_WRITE(sc, RT2661_AIFSN_CSR,
2057 wmep[WME_AC_BE].wmep_aifsn << 12 |
2058 wmep[WME_AC_BK].wmep_aifsn << 8 |
2059 wmep[WME_AC_VI].wmep_aifsn << 4 |
2060 wmep[WME_AC_VO].wmep_aifsn);
2061
2062 return 0;
2063 }
2064
2065 static void
rt2661_update_slot(struct ieee80211com * ic)2066 rt2661_update_slot(struct ieee80211com *ic)
2067 {
2068 struct rt2661_softc *sc = ic->ic_softc;
2069 uint8_t slottime;
2070 uint32_t tmp;
2071
2072 slottime = IEEE80211_GET_SLOTTIME(ic);
2073
2074 tmp = RAL_READ(sc, RT2661_MAC_CSR9);
2075 tmp = (tmp & ~0xff) | slottime;
2076 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp);
2077 }
2078
2079 static const char *
rt2661_get_rf(int rev)2080 rt2661_get_rf(int rev)
2081 {
2082 switch (rev) {
2083 case RT2661_RF_5225: return "RT5225";
2084 case RT2661_RF_5325: return "RT5325 (MIMO XR)";
2085 case RT2661_RF_2527: return "RT2527";
2086 case RT2661_RF_2529: return "RT2529 (MIMO XR)";
2087 default: return "unknown";
2088 }
2089 }
2090
2091 static void
rt2661_read_eeprom(struct rt2661_softc * sc,uint8_t macaddr[IEEE80211_ADDR_LEN])2092 rt2661_read_eeprom(struct rt2661_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
2093 {
2094 uint16_t val;
2095 int i;
2096
2097 /* read MAC address */
2098 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01);
2099 macaddr[0] = val & 0xff;
2100 macaddr[1] = val >> 8;
2101
2102 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23);
2103 macaddr[2] = val & 0xff;
2104 macaddr[3] = val >> 8;
2105
2106 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45);
2107 macaddr[4] = val & 0xff;
2108 macaddr[5] = val >> 8;
2109
2110 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA);
2111 /* XXX: test if different from 0xffff? */
2112 sc->rf_rev = (val >> 11) & 0x1f;
2113 sc->hw_radio = (val >> 10) & 0x1;
2114 sc->rx_ant = (val >> 4) & 0x3;
2115 sc->tx_ant = (val >> 2) & 0x3;
2116 sc->nb_ant = val & 0x3;
2117
2118 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev);
2119
2120 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2);
2121 sc->ext_5ghz_lna = (val >> 6) & 0x1;
2122 sc->ext_2ghz_lna = (val >> 4) & 0x1;
2123
2124 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n",
2125 sc->ext_2ghz_lna, sc->ext_5ghz_lna);
2126
2127 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET);
2128 if ((val & 0xff) != 0xff)
2129 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */
2130
2131 /* Only [-10, 10] is valid */
2132 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10)
2133 sc->rssi_2ghz_corr = 0;
2134
2135 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET);
2136 if ((val & 0xff) != 0xff)
2137 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */
2138
2139 /* Only [-10, 10] is valid */
2140 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10)
2141 sc->rssi_5ghz_corr = 0;
2142
2143 /* adjust RSSI correction for external low-noise amplifier */
2144 if (sc->ext_2ghz_lna)
2145 sc->rssi_2ghz_corr -= 14;
2146 if (sc->ext_5ghz_lna)
2147 sc->rssi_5ghz_corr -= 14;
2148
2149 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n",
2150 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr);
2151
2152 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET);
2153 if ((val >> 8) != 0xff)
2154 sc->rfprog = (val >> 8) & 0x3;
2155 if ((val & 0xff) != 0xff)
2156 sc->rffreq = val & 0xff;
2157
2158 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq);
2159
2160 /* read Tx power for all a/b/g channels */
2161 for (i = 0; i < 19; i++) {
2162 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i);
2163 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */
2164 DPRINTF(sc, "Channel=%d Tx power=%d\n",
2165 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]);
2166 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */
2167 DPRINTF(sc, "Channel=%d Tx power=%d\n",
2168 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]);
2169 }
2170
2171 /* read vendor-specific BBP values */
2172 for (i = 0; i < 16; i++) {
2173 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i);
2174 if (val == 0 || val == 0xffff)
2175 continue; /* skip invalid entries */
2176 sc->bbp_prom[i].reg = val >> 8;
2177 sc->bbp_prom[i].val = val & 0xff;
2178 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg,
2179 sc->bbp_prom[i].val);
2180 }
2181 }
2182
2183 static int
rt2661_bbp_init(struct rt2661_softc * sc)2184 rt2661_bbp_init(struct rt2661_softc *sc)
2185 {
2186 int i, ntries;
2187 uint8_t val;
2188
2189 /* wait for BBP to be ready */
2190 for (ntries = 0; ntries < 100; ntries++) {
2191 val = rt2661_bbp_read(sc, 0);
2192 if (val != 0 && val != 0xff)
2193 break;
2194 DELAY(100);
2195 }
2196 if (ntries == 100) {
2197 device_printf(sc->sc_dev, "timeout waiting for BBP\n");
2198 return EIO;
2199 }
2200
2201 /* initialize BBP registers to default values */
2202 for (i = 0; i < nitems(rt2661_def_bbp); i++) {
2203 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg,
2204 rt2661_def_bbp[i].val);
2205 }
2206
2207 /* write vendor-specific BBP values (from EEPROM) */
2208 for (i = 0; i < 16; i++) {
2209 if (sc->bbp_prom[i].reg == 0)
2210 continue;
2211 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
2212 }
2213
2214 return 0;
2215 }
2216
2217 static void
rt2661_init_locked(struct rt2661_softc * sc)2218 rt2661_init_locked(struct rt2661_softc *sc)
2219 {
2220 struct ieee80211com *ic = &sc->sc_ic;
2221 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2222 uint32_t tmp, sta[3];
2223 int i, error, ntries;
2224
2225 RAL_LOCK_ASSERT(sc);
2226
2227 if ((sc->sc_flags & RAL_FW_LOADED) == 0) {
2228 error = rt2661_load_microcode(sc);
2229 if (error != 0) {
2230 device_printf(sc->sc_dev,
2231 "%s: could not load 8051 microcode, error %d\n",
2232 __func__, error);
2233 return;
2234 }
2235 sc->sc_flags |= RAL_FW_LOADED;
2236 }
2237
2238 rt2661_stop_locked(sc);
2239
2240 /* initialize Tx rings */
2241 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr);
2242 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr);
2243 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr);
2244 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr);
2245
2246 /* initialize Mgt ring */
2247 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr);
2248
2249 /* initialize Rx ring */
2250 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr);
2251
2252 /* initialize Tx rings sizes */
2253 RAL_WRITE(sc, RT2661_TX_RING_CSR0,
2254 RT2661_TX_RING_COUNT << 24 |
2255 RT2661_TX_RING_COUNT << 16 |
2256 RT2661_TX_RING_COUNT << 8 |
2257 RT2661_TX_RING_COUNT);
2258
2259 RAL_WRITE(sc, RT2661_TX_RING_CSR1,
2260 RT2661_TX_DESC_WSIZE << 16 |
2261 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */
2262 RT2661_MGT_RING_COUNT);
2263
2264 /* initialize Rx rings */
2265 RAL_WRITE(sc, RT2661_RX_RING_CSR,
2266 RT2661_RX_DESC_BACK << 16 |
2267 RT2661_RX_DESC_WSIZE << 8 |
2268 RT2661_RX_RING_COUNT);
2269
2270 /* XXX: some magic here */
2271 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa);
2272
2273 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */
2274 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f);
2275
2276 /* load base address of Rx ring */
2277 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2);
2278
2279 /* initialize MAC registers to default values */
2280 for (i = 0; i < nitems(rt2661_def_mac); i++)
2281 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
2282
2283 rt2661_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr);
2284
2285 /* set host ready */
2286 RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2287 RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2288
2289 /* wait for BBP/RF to wakeup */
2290 for (ntries = 0; ntries < 1000; ntries++) {
2291 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8)
2292 break;
2293 DELAY(1000);
2294 }
2295 if (ntries == 1000) {
2296 printf("timeout waiting for BBP/RF to wakeup\n");
2297 rt2661_stop_locked(sc);
2298 return;
2299 }
2300
2301 if (rt2661_bbp_init(sc) != 0) {
2302 rt2661_stop_locked(sc);
2303 return;
2304 }
2305
2306 /* select default channel */
2307 sc->sc_curchan = ic->ic_curchan;
2308 rt2661_select_band(sc, sc->sc_curchan);
2309 rt2661_select_antenna(sc);
2310 rt2661_set_chan(sc, sc->sc_curchan);
2311
2312 /* update Rx filter */
2313 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff;
2314
2315 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR;
2316 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2317 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR |
2318 RT2661_DROP_ACKCTS;
2319 if (ic->ic_opmode != IEEE80211_M_HOSTAP &&
2320 ic->ic_opmode != IEEE80211_M_MBSS)
2321 tmp |= RT2661_DROP_TODS;
2322 if (ic->ic_promisc == 0)
2323 tmp |= RT2661_DROP_NOT_TO_ME;
2324 }
2325
2326 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2327
2328 /* clear STA registers */
2329 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, nitems(sta));
2330
2331 /* initialize ASIC */
2332 RAL_WRITE(sc, RT2661_MAC_CSR1, 4);
2333
2334 /* clear any pending interrupt */
2335 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2336
2337 /* enable interrupts */
2338 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
2339 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
2340
2341 /* kick Rx */
2342 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1);
2343
2344 sc->sc_flags |= RAL_RUNNING;
2345
2346 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc);
2347 }
2348
2349 static void
rt2661_init(void * priv)2350 rt2661_init(void *priv)
2351 {
2352 struct rt2661_softc *sc = priv;
2353 struct ieee80211com *ic = &sc->sc_ic;
2354
2355 RAL_LOCK(sc);
2356 rt2661_init_locked(sc);
2357 RAL_UNLOCK(sc);
2358
2359 if (sc->sc_flags & RAL_RUNNING)
2360 ieee80211_start_all(ic); /* start all vap's */
2361 }
2362
2363 void
rt2661_stop_locked(struct rt2661_softc * sc)2364 rt2661_stop_locked(struct rt2661_softc *sc)
2365 {
2366 volatile int *flags = &sc->sc_flags;
2367 uint32_t tmp;
2368
2369 while (*flags & RAL_INPUT_RUNNING)
2370 msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10);
2371
2372 callout_stop(&sc->watchdog_ch);
2373 sc->sc_tx_timer = 0;
2374
2375 if (sc->sc_flags & RAL_RUNNING) {
2376 sc->sc_flags &= ~RAL_RUNNING;
2377
2378 /* abort Tx (for all 5 Tx rings) */
2379 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16);
2380
2381 /* disable Rx (value remains after reset!) */
2382 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2383 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2384
2385 /* reset ASIC */
2386 RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2387 RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2388
2389 /* disable interrupts */
2390 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff);
2391 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
2392
2393 /* clear any pending interrupt */
2394 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2395 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff);
2396
2397 /* reset Tx and Rx rings */
2398 rt2661_reset_tx_ring(sc, &sc->txq[0]);
2399 rt2661_reset_tx_ring(sc, &sc->txq[1]);
2400 rt2661_reset_tx_ring(sc, &sc->txq[2]);
2401 rt2661_reset_tx_ring(sc, &sc->txq[3]);
2402 rt2661_reset_tx_ring(sc, &sc->mgtq);
2403 rt2661_reset_rx_ring(sc, &sc->rxq);
2404 }
2405 }
2406
2407 void
rt2661_stop(void * priv)2408 rt2661_stop(void *priv)
2409 {
2410 struct rt2661_softc *sc = priv;
2411
2412 RAL_LOCK(sc);
2413 rt2661_stop_locked(sc);
2414 RAL_UNLOCK(sc);
2415 }
2416
2417 static int
rt2661_load_microcode(struct rt2661_softc * sc)2418 rt2661_load_microcode(struct rt2661_softc *sc)
2419 {
2420 const struct firmware *fp;
2421 const char *imagename;
2422 int ntries, error;
2423
2424 RAL_LOCK_ASSERT(sc);
2425
2426 switch (sc->sc_id) {
2427 case 0x0301: imagename = "rt2561sfw"; break;
2428 case 0x0302: imagename = "rt2561fw"; break;
2429 case 0x0401: imagename = "rt2661fw"; break;
2430 default:
2431 device_printf(sc->sc_dev, "%s: unexpected pci device id 0x%x, "
2432 "don't know how to retrieve firmware\n",
2433 __func__, sc->sc_id);
2434 return EINVAL;
2435 }
2436 RAL_UNLOCK(sc);
2437 fp = firmware_get(imagename);
2438 RAL_LOCK(sc);
2439 if (fp == NULL) {
2440 device_printf(sc->sc_dev,
2441 "%s: unable to retrieve firmware image %s\n",
2442 __func__, imagename);
2443 return EINVAL;
2444 }
2445
2446 /*
2447 * Load 8051 microcode into NIC.
2448 */
2449 /* reset 8051 */
2450 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2451
2452 /* cancel any pending Host to MCU command */
2453 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0);
2454 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
2455 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0);
2456
2457 /* write 8051's microcode */
2458 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL);
2459 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize);
2460 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2461
2462 /* kick 8051's ass */
2463 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0);
2464
2465 /* wait for 8051 to initialize */
2466 for (ntries = 0; ntries < 500; ntries++) {
2467 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY)
2468 break;
2469 DELAY(100);
2470 }
2471 if (ntries == 500) {
2472 device_printf(sc->sc_dev,
2473 "%s: timeout waiting for MCU to initialize\n", __func__);
2474 error = EIO;
2475 } else
2476 error = 0;
2477
2478 firmware_put(fp, FIRMWARE_UNLOAD);
2479 return error;
2480 }
2481
2482 #ifdef notyet
2483 /*
2484 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and
2485 * false CCA count. This function is called periodically (every seconds) when
2486 * in the RUN state. Values taken from the reference driver.
2487 */
2488 static void
rt2661_rx_tune(struct rt2661_softc * sc)2489 rt2661_rx_tune(struct rt2661_softc *sc)
2490 {
2491 uint8_t bbp17;
2492 uint16_t cca;
2493 int lo, hi, dbm;
2494
2495 /*
2496 * Tuning range depends on operating band and on the presence of an
2497 * external low-noise amplifier.
2498 */
2499 lo = 0x20;
2500 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan))
2501 lo += 0x08;
2502 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) ||
2503 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna))
2504 lo += 0x10;
2505 hi = lo + 0x20;
2506
2507 /* retrieve false CCA count since last call (clear on read) */
2508 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff;
2509
2510 if (dbm >= -35) {
2511 bbp17 = 0x60;
2512 } else if (dbm >= -58) {
2513 bbp17 = hi;
2514 } else if (dbm >= -66) {
2515 bbp17 = lo + 0x10;
2516 } else if (dbm >= -74) {
2517 bbp17 = lo + 0x08;
2518 } else {
2519 /* RSSI < -74dBm, tune using false CCA count */
2520
2521 bbp17 = sc->bbp17; /* current value */
2522
2523 hi -= 2 * (-74 - dbm);
2524 if (hi < lo)
2525 hi = lo;
2526
2527 if (bbp17 > hi) {
2528 bbp17 = hi;
2529
2530 } else if (cca > 512) {
2531 if (++bbp17 > hi)
2532 bbp17 = hi;
2533 } else if (cca < 100) {
2534 if (--bbp17 < lo)
2535 bbp17 = lo;
2536 }
2537 }
2538
2539 if (bbp17 != sc->bbp17) {
2540 rt2661_bbp_write(sc, 17, bbp17);
2541 sc->bbp17 = bbp17;
2542 }
2543 }
2544
2545 /*
2546 * Enter/Leave radar detection mode.
2547 * This is for 802.11h additional regulatory domains.
2548 */
2549 static void
rt2661_radar_start(struct rt2661_softc * sc)2550 rt2661_radar_start(struct rt2661_softc *sc)
2551 {
2552 uint32_t tmp;
2553
2554 /* disable Rx */
2555 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2556 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2557
2558 rt2661_bbp_write(sc, 82, 0x20);
2559 rt2661_bbp_write(sc, 83, 0x00);
2560 rt2661_bbp_write(sc, 84, 0x40);
2561
2562 /* save current BBP registers values */
2563 sc->bbp18 = rt2661_bbp_read(sc, 18);
2564 sc->bbp21 = rt2661_bbp_read(sc, 21);
2565 sc->bbp22 = rt2661_bbp_read(sc, 22);
2566 sc->bbp16 = rt2661_bbp_read(sc, 16);
2567 sc->bbp17 = rt2661_bbp_read(sc, 17);
2568 sc->bbp64 = rt2661_bbp_read(sc, 64);
2569
2570 rt2661_bbp_write(sc, 18, 0xff);
2571 rt2661_bbp_write(sc, 21, 0x3f);
2572 rt2661_bbp_write(sc, 22, 0x3f);
2573 rt2661_bbp_write(sc, 16, 0xbd);
2574 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34);
2575 rt2661_bbp_write(sc, 64, 0x21);
2576
2577 /* restore Rx filter */
2578 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2579 }
2580
2581 static int
rt2661_radar_stop(struct rt2661_softc * sc)2582 rt2661_radar_stop(struct rt2661_softc *sc)
2583 {
2584 uint8_t bbp66;
2585
2586 /* read radar detection result */
2587 bbp66 = rt2661_bbp_read(sc, 66);
2588
2589 /* restore BBP registers values */
2590 rt2661_bbp_write(sc, 16, sc->bbp16);
2591 rt2661_bbp_write(sc, 17, sc->bbp17);
2592 rt2661_bbp_write(sc, 18, sc->bbp18);
2593 rt2661_bbp_write(sc, 21, sc->bbp21);
2594 rt2661_bbp_write(sc, 22, sc->bbp22);
2595 rt2661_bbp_write(sc, 64, sc->bbp64);
2596
2597 return bbp66 == 1;
2598 }
2599 #endif
2600
2601 static int
rt2661_prepare_beacon(struct rt2661_softc * sc,struct ieee80211vap * vap)2602 rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap)
2603 {
2604 struct ieee80211com *ic = vap->iv_ic;
2605 struct rt2661_tx_desc desc;
2606 struct mbuf *m0;
2607 int rate;
2608
2609 if ((m0 = ieee80211_beacon_alloc(vap->iv_bss))== NULL) {
2610 device_printf(sc->sc_dev, "could not allocate beacon frame\n");
2611 return ENOBUFS;
2612 }
2613
2614 /* send beacons at the lowest available rate */
2615 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2;
2616
2617 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ,
2618 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT);
2619
2620 /* copy the first 24 bytes of Tx descriptor into NIC memory */
2621 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24);
2622
2623 /* copy beacon header and payload into NIC memory */
2624 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24,
2625 mtod(m0, uint8_t *), m0->m_pkthdr.len);
2626
2627 m_freem(m0);
2628
2629 return 0;
2630 }
2631
2632 /*
2633 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS
2634 * and HostAP operating modes.
2635 */
2636 static void
rt2661_enable_tsf_sync(struct rt2661_softc * sc)2637 rt2661_enable_tsf_sync(struct rt2661_softc *sc)
2638 {
2639 struct ieee80211com *ic = &sc->sc_ic;
2640 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2641 uint32_t tmp;
2642
2643 if (vap->iv_opmode != IEEE80211_M_STA) {
2644 /*
2645 * Change default 16ms TBTT adjustment to 8ms.
2646 * Must be done before enabling beacon generation.
2647 */
2648 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8);
2649 }
2650
2651 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000;
2652
2653 /* set beacon interval (in 1/16ms unit) */
2654 tmp |= vap->iv_bss->ni_intval * 16;
2655
2656 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT;
2657 if (vap->iv_opmode == IEEE80211_M_STA)
2658 tmp |= RT2661_TSF_MODE(1);
2659 else
2660 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON;
2661
2662 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp);
2663 }
2664
2665 static void
rt2661_enable_tsf(struct rt2661_softc * sc)2666 rt2661_enable_tsf(struct rt2661_softc *sc)
2667 {
2668 RAL_WRITE(sc, RT2661_TXRX_CSR9,
2669 (RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000)
2670 | RT2661_TSF_TICKING | RT2661_TSF_MODE(2));
2671 }
2672
2673 /*
2674 * Retrieve the "Received Signal Strength Indicator" from the raw values
2675 * contained in Rx descriptors. The computation depends on which band the
2676 * frame was received. Correction values taken from the reference driver.
2677 */
2678 static int
rt2661_get_rssi(struct rt2661_softc * sc,uint8_t raw)2679 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw)
2680 {
2681 int lna, agc, rssi;
2682
2683 lna = (raw >> 5) & 0x3;
2684 agc = raw & 0x1f;
2685
2686 if (lna == 0) {
2687 /*
2688 * No mapping available.
2689 *
2690 * NB: Since RSSI is relative to noise floor, -1 is
2691 * adequate for caller to know error happened.
2692 */
2693 return -1;
2694 }
2695
2696 rssi = (2 * agc) - RT2661_NOISE_FLOOR;
2697
2698 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) {
2699 rssi += sc->rssi_2ghz_corr;
2700
2701 if (lna == 1)
2702 rssi -= 64;
2703 else if (lna == 2)
2704 rssi -= 74;
2705 else if (lna == 3)
2706 rssi -= 90;
2707 } else {
2708 rssi += sc->rssi_5ghz_corr;
2709
2710 if (lna == 1)
2711 rssi -= 64;
2712 else if (lna == 2)
2713 rssi -= 86;
2714 else if (lna == 3)
2715 rssi -= 100;
2716 }
2717 return rssi;
2718 }
2719
2720 static void
rt2661_scan_start(struct ieee80211com * ic)2721 rt2661_scan_start(struct ieee80211com *ic)
2722 {
2723 struct rt2661_softc *sc = ic->ic_softc;
2724 uint32_t tmp;
2725
2726 /* abort TSF synchronization */
2727 tmp = RAL_READ(sc, RT2661_TXRX_CSR9);
2728 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff);
2729 rt2661_set_bssid(sc, ieee80211broadcastaddr);
2730 }
2731
2732 static void
rt2661_scan_end(struct ieee80211com * ic)2733 rt2661_scan_end(struct ieee80211com *ic)
2734 {
2735 struct rt2661_softc *sc = ic->ic_softc;
2736 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2737
2738 rt2661_enable_tsf_sync(sc);
2739 /* XXX keep local copy */
2740 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid);
2741 }
2742
2743 static void
rt2661_getradiocaps(struct ieee80211com * ic,int maxchans,int * nchans,struct ieee80211_channel chans[])2744 rt2661_getradiocaps(struct ieee80211com *ic,
2745 int maxchans, int *nchans, struct ieee80211_channel chans[])
2746 {
2747 struct rt2661_softc *sc = ic->ic_softc;
2748 uint8_t bands[IEEE80211_MODE_BYTES];
2749
2750 memset(bands, 0, sizeof(bands));
2751 setbit(bands, IEEE80211_MODE_11B);
2752 setbit(bands, IEEE80211_MODE_11G);
2753 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0);
2754
2755 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) {
2756 setbit(bands, IEEE80211_MODE_11A);
2757 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans,
2758 rt2661_chan_5ghz, nitems(rt2661_chan_5ghz), bands, 0);
2759 }
2760 }
2761
2762 static void
rt2661_set_channel(struct ieee80211com * ic)2763 rt2661_set_channel(struct ieee80211com *ic)
2764 {
2765 struct rt2661_softc *sc = ic->ic_softc;
2766
2767 RAL_LOCK(sc);
2768 rt2661_set_chan(sc, ic->ic_curchan);
2769 RAL_UNLOCK(sc);
2770
2771 }
2772