xref: /linux/sound/soc/codecs/rt1318.c (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5)
1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rt1318.c  --  RT1318 ALSA SoC audio amplifier driver
4 // Author: Jack Yu <jack.yu@realtek.com>
5 //
6 // Copyright(c) 2024 Realtek Semiconductor Corp.
7 //
8 //
9 
10 #include <linux/acpi.h>
11 #include <linux/fs.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/regmap.h>
18 #include <linux/i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/firmware.h>
21 #include <linux/gpio.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/rt1318.h>
30 
31 #include "rt1318.h"
32 
33 static const struct reg_sequence init_list[] = {
34 	{ 0x0000C000, 0x01},
35 	{ 0x0000F20D, 0x00},
36 	{ 0x0000F212, 0x3E},
37 	{ 0x0000C001, 0x02},
38 	{ 0x0000C003, 0x22},
39 	{ 0x0000C004, 0x44},
40 	{ 0x0000C005, 0x44},
41 	{ 0x0000C007, 0x64},
42 	{ 0x0000C00E, 0xE7},
43 	{ 0x0000F223, 0x7F},
44 	{ 0x0000F224, 0xDB},
45 	{ 0x0000F225, 0xEE},
46 	{ 0x0000F226, 0x3F},
47 	{ 0x0000F227, 0x0F},
48 	{ 0x0000F21A, 0x78},
49 	{ 0x0000F242, 0x3C},
50 	{ 0x0000C120, 0x40},
51 	{ 0x0000C125, 0x03},
52 	{ 0x0000C321, 0x0A},
53 	{ 0x0000C200, 0xD8},
54 	{ 0x0000C201, 0x27},
55 	{ 0x0000C202, 0x0F},
56 	{ 0x0000C400, 0x0E},
57 	{ 0x0000C401, 0x43},
58 	{ 0x0000C402, 0xE0},
59 	{ 0x0000C403, 0x00},
60 	{ 0x0000C404, 0x4C},
61 	{ 0x0000C406, 0x40},
62 	{ 0x0000C407, 0x02},
63 	{ 0x0000C408, 0x3F},
64 	{ 0x0000C300, 0x01},
65 	{ 0x0000C125, 0x03},
66 	{ 0x0000DF00, 0x10},
67 	{ 0x0000F20B, 0x2A},
68 	{ 0x0000DF5F, 0x01},
69 	{ 0x0000DF60, 0xA7},
70 	{ 0x0000C203, 0x84},
71 	{ 0x0000C206, 0x78},
72 	{ 0x0000F10A, 0x09},
73 	{ 0x0000F10B, 0x4C},
74 	{ 0x0000F104, 0xF4},
75 	{ 0x0000F105, 0x03},
76 	{ 0x0000F109, 0xE0},
77 	{ 0x0000F10B, 0x5C},
78 	{ 0x0000F104, 0xF4},
79 	{ 0x0000F105, 0x04},
80 	{ 0x0000F109, 0x65},
81 	{ 0x0000F10B, 0x5C},
82 	{ 0x0000F104, 0xF4},
83 	{ 0x0000F105, 0x02},
84 	{ 0x0000F109, 0x30},
85 	{ 0x0000F10B, 0x5C},
86 	{ 0x0000E706, 0x0F},
87 	{ 0x0000E707, 0x30},
88 	{ 0x0000E806, 0x0F},
89 	{ 0x0000E807, 0x30},
90 	{ 0x0000CE04, 0x03},
91 	{ 0x0000CE05, 0x5F},
92 	{ 0x0000CE06, 0xA2},
93 	{ 0x0000CE07, 0x6B},
94 	{ 0x0000CF04, 0x03},
95 	{ 0x0000CF05, 0x5F},
96 	{ 0x0000CF06, 0xA2},
97 	{ 0x0000CF07, 0x6B},
98 	{ 0x0000CE60, 0xE3},
99 	{ 0x0000C130, 0x51},
100 	{ 0x0000E000, 0xA8},
101 	{ 0x0000F102, 0x00},
102 	{ 0x0000F103, 0x00},
103 	{ 0x0000F104, 0xF5},
104 	{ 0x0000F105, 0x23},
105 	{ 0x0000F109, 0x04},
106 	{ 0x0000F10A, 0x0B},
107 	{ 0x0000F10B, 0x4C},
108 	{ 0x0000F10B, 0x5C},
109 	{ 0x41001888, 0x00},
110 	{ 0x0000C121, 0x0B},
111 	{ 0x0000F102, 0x00},
112 	{ 0x0000F103, 0x00},
113 	{ 0x0000F104, 0xF5},
114 	{ 0x0000F105, 0x23},
115 	{ 0x0000F109, 0x00},
116 	{ 0x0000F10A, 0x0B},
117 	{ 0x0000F10B, 0x4C},
118 	{ 0x0000F10B, 0x5C},
119 	{ 0x0000F800, 0x20},
120 	{ 0x0000CA00, 0x80},
121 	{ 0x0000CA10, 0x00},
122 	{ 0x0000CA02, 0x78},
123 	{ 0x0000CA12, 0x78},
124 	{ 0x0000ED00, 0x90},
125 	{ 0x0000E604, 0x00},
126 	{ 0x0000DB00, 0x0C},
127 	{ 0x0000DD00, 0x0C},
128 	{ 0x0000DC19, 0x00},
129 	{ 0x0000DC1A, 0x6A},
130 	{ 0x0000DC1B, 0xAA},
131 	{ 0x0000DC1C, 0xAB},
132 	{ 0x0000DC1D, 0x00},
133 	{ 0x0000DC1E, 0x16},
134 	{ 0x0000DC1F, 0xDB},
135 	{ 0x0000DC20, 0x6D},
136 	{ 0x0000DE19, 0x00},
137 	{ 0x0000DE1A, 0x6A},
138 	{ 0x0000DE1B, 0xAA},
139 	{ 0x0000DE1C, 0xAB},
140 	{ 0x0000DE1D, 0x00},
141 	{ 0x0000DE1E, 0x16},
142 	{ 0x0000DE1F, 0xDB},
143 	{ 0x0000DE20, 0x6D},
144 	{ 0x0000DB32, 0x00},
145 	{ 0x0000DD32, 0x00},
146 	{ 0x0000DB33, 0x0A},
147 	{ 0x0000DD33, 0x0A},
148 	{ 0x0000DB34, 0x1A},
149 	{ 0x0000DD34, 0x1A},
150 	{ 0x0000DB15, 0xEF},
151 	{ 0x0000DD15, 0xEF},
152 	{ 0x0000DB17, 0xEF},
153 	{ 0x0000DD17, 0xEF},
154 	{ 0x0000DB94, 0x70},
155 	{ 0x0000DD94, 0x70},
156 	{ 0x0000DB19, 0x40},
157 	{ 0x0000DD19, 0x40},
158 	{ 0x0000DB12, 0xC0},
159 	{ 0x0000DD12, 0xC0},
160 	{ 0x0000DB00, 0x4C},
161 	{ 0x0000DB04, 0x05},
162 	{ 0x0000DB05, 0x03},
163 	{ 0x0000DD04, 0x05},
164 	{ 0x0000DD05, 0x03},
165 	{ 0x0000DBBB, 0x09},
166 	{ 0x0000DBBC, 0x30},
167 	{ 0x0000DBBD, 0xF0},
168 	{ 0x0000DBBE, 0xF1},
169 	{ 0x0000DDBB, 0x09},
170 	{ 0x0000DDBC, 0x30},
171 	{ 0x0000DDBD, 0xF0},
172 	{ 0x0000DDBE, 0xF1},
173 	{ 0x0000DB01, 0x79},
174 	{ 0x0000DD01, 0x79},
175 	{ 0x0000DB08, 0x40},
176 	{ 0x0000DD08, 0x40},
177 	{ 0x0000DC52, 0xEF},
178 	{ 0x0000DE52, 0xEF},
179 	{ 0x0000DB00, 0xCC},
180 	{ 0x0000CC2C, 0x00},
181 	{ 0x0000CC2D, 0x2A},
182 	{ 0x0000CC2E, 0x83},
183 	{ 0x0000CC2F, 0xA8},
184 	{ 0x0000CD2C, 0x00},
185 	{ 0x0000CD2D, 0x2A},
186 	{ 0x0000CD2E, 0x83},
187 	{ 0x0000CD2F, 0xA8},
188 	{ 0x0000CC24, 0x00},
189 	{ 0x0000CC25, 0x51},
190 	{ 0x0000CC26, 0xEB},
191 	{ 0x0000CC27, 0x85},
192 	{ 0x0000CD24, 0x00},
193 	{ 0x0000CD25, 0x51},
194 	{ 0x0000CD26, 0xEB},
195 	{ 0x0000CD27, 0x85},
196 	{ 0x0000CC20, 0x00},
197 	{ 0x0000CC21, 0x00},
198 	{ 0x0000CC22, 0x43},
199 	{ 0x0000CD20, 0x00},
200 	{ 0x0000CD21, 0x00},
201 	{ 0x0000CD22, 0x43},
202 	{ 0x0000CC16, 0x0F},
203 	{ 0x0000CC17, 0x00},
204 	{ 0x0000CD16, 0x0F},
205 	{ 0x0000CD17, 0x00},
206 	{ 0x0000CC29, 0x5D},
207 	{ 0x0000CC2A, 0xC0},
208 	{ 0x0000CD29, 0x5D},
209 	{ 0x0000CD2A, 0xC0},
210 	{ 0x0000CC31, 0x20},
211 	{ 0x0000CC32, 0x00},
212 	{ 0x0000CC33, 0x00},
213 	{ 0x0000CC34, 0x00},
214 	{ 0x0000CD31, 0x20},
215 	{ 0x0000CD32, 0x00},
216 	{ 0x0000CD33, 0x00},
217 	{ 0x0000CD34, 0x00},
218 	{ 0x0000CC36, 0x79},
219 	{ 0x0000CC37, 0x99},
220 	{ 0x0000CC38, 0x99},
221 	{ 0x0000CC39, 0x99},
222 	{ 0x0000CD36, 0x79},
223 	{ 0x0000CD37, 0x99},
224 	{ 0x0000CD38, 0x99},
225 	{ 0x0000CD39, 0x99},
226 	{ 0x0000CC09, 0x00},
227 	{ 0x0000CC0A, 0x07},
228 	{ 0x0000CC0B, 0x5F},
229 	{ 0x0000CC0C, 0x6F},
230 	{ 0x0000CD09, 0x00},
231 	{ 0x0000CD0A, 0x07},
232 	{ 0x0000CD0B, 0x5F},
233 	{ 0x0000CD0C, 0x6F},
234 	{ 0x0000CC0E, 0x00},
235 	{ 0x0000CC0F, 0x03},
236 	{ 0x0000CC10, 0xAF},
237 	{ 0x0000CC11, 0xB7},
238 	{ 0x0000CD0E, 0x00},
239 	{ 0x0000CD0F, 0x03},
240 	{ 0x0000CD10, 0xAF},
241 	{ 0x0000CD11, 0xB7},
242 	{ 0x0000CCD6, 0x00},
243 	{ 0x0000CCD7, 0x03},
244 	{ 0x0000CDD6, 0x00},
245 	{ 0x0000CDD7, 0x03},
246 	{ 0x0000CCD8, 0x00},
247 	{ 0x0000CCD9, 0x03},
248 	{ 0x0000CDD8, 0x00},
249 	{ 0x0000CDD9, 0x03},
250 	{ 0x0000CCDA, 0x00},
251 	{ 0x0000CCDB, 0x03},
252 	{ 0x0000CDDA, 0x00},
253 	{ 0x0000CDDB, 0x03},
254 	{ 0x0000C320, 0x20},
255 	{ 0x0000C203, 0x9C},
256 };
257 
258 static const struct reg_default rt1318_reg[] = {
259 	{ 0xc000, 0x00 },
260 	{ 0xc001, 0x43 },
261 	{ 0xc003, 0x22 },
262 	{ 0xc004, 0x44 },
263 	{ 0xc005, 0x44 },
264 	{ 0xc006, 0x33 },
265 	{ 0xc007, 0x64 },
266 	{ 0xc008, 0x05 },
267 	{ 0xc00a, 0xfc },
268 	{ 0xc00b, 0x0f },
269 	{ 0xc00c, 0x0e },
270 	{ 0xc00d, 0xef },
271 	{ 0xc00e, 0xe5 },
272 	{ 0xc00f, 0xff },
273 	{ 0xc120, 0xc0 },
274 	{ 0xc121, 0x00 },
275 	{ 0xc122, 0x00 },
276 	{ 0xc123, 0x14 },
277 	{ 0xc125, 0x00 },
278 	{ 0xc130, 0x59 },
279 	{ 0xc200, 0x00 },
280 	{ 0xc201, 0x00 },
281 	{ 0xc202, 0x00 },
282 	{ 0xc203, 0x04 },
283 	{ 0xc204, 0x00 },
284 	{ 0xc205, 0x00 },
285 	{ 0xc206, 0x68 },
286 	{ 0xc207, 0x70 },
287 	{ 0xc208, 0x00 },
288 	{ 0xc20a, 0x00 },
289 	{ 0xc20b, 0x01 },
290 	{ 0xc20c, 0x7f },
291 	{ 0xc20d, 0x01 },
292 	{ 0xc20e, 0x7f },
293 	{ 0xc300, 0x00 },
294 	{ 0xc301, 0x00 },
295 	{ 0xc303, 0x80 },
296 	{ 0xc320, 0x00 },
297 	{ 0xc321, 0x09 },
298 	{ 0xc322, 0x02 },
299 	{ 0xc400, 0x00 },
300 	{ 0xc401, 0x00 },
301 	{ 0xc402, 0x00 },
302 	{ 0xc403, 0x00 },
303 	{ 0xc404, 0x00 },
304 	{ 0xc405, 0x00 },
305 	{ 0xc406, 0x00 },
306 	{ 0xc407, 0x00 },
307 	{ 0xc408, 0x00 },
308 	{ 0xc410, 0x04 },
309 	{ 0xc430, 0x00 },
310 	{ 0xc431, 0x00 },
311 	{ 0xca00, 0x10 },
312 	{ 0xca01, 0x00 },
313 	{ 0xca02, 0x0b },
314 	{ 0xca10, 0x10 },
315 	{ 0xca11, 0x00 },
316 	{ 0xca12, 0x0b },
317 	{ 0xce04, 0x08 },
318 	{ 0xce05, 0x00 },
319 	{ 0xce06, 0x00 },
320 	{ 0xce07, 0x00 },
321 	{ 0xce60, 0x63 },
322 	{ 0xcf04, 0x08 },
323 	{ 0xcf05, 0x00 },
324 	{ 0xcf06, 0x00 },
325 	{ 0xcf07, 0x00 },
326 	{ 0xdb00, 0x00 },
327 	{ 0xdb08, 0x40 },
328 	{ 0xdb12, 0x00 },
329 	{ 0xdb35, 0x00 },
330 	{ 0xdbb5, 0x00 },
331 	{ 0xdbb6, 0x40 },
332 	{ 0xdbb7, 0x00 },
333 	{ 0xdbb8, 0x00 },
334 	{ 0xdbc5, 0x00 },
335 	{ 0xdbc6, 0x00 },
336 	{ 0xdbc7, 0x00 },
337 	{ 0xdbc8, 0x00 },
338 	{ 0xdd08, 0x40 },
339 	{ 0xdd12, 0x00 },
340 	{ 0xdd35, 0x00 },
341 	{ 0xddb5, 0x00 },
342 	{ 0xddb6, 0x40 },
343 	{ 0xddb7, 0x00 },
344 	{ 0xddb8, 0x00 },
345 	{ 0xddc5, 0x00 },
346 	{ 0xddc6, 0x00 },
347 	{ 0xddc7, 0x00 },
348 	{ 0xddc8, 0x00 },
349 	{ 0xdd93, 0x00 },
350 	{ 0xdd94, 0x64 },
351 	{ 0xdf00, 0x00 },
352 	{ 0xdf5f, 0x00 },
353 	{ 0xdf60, 0x00 },
354 	{ 0xe000, 0x08 },
355 	{ 0xe300, 0xa0 },
356 	{ 0xe400, 0x22 },
357 	{ 0xe706, 0x2f },
358 	{ 0xe707, 0x2f },
359 	{ 0xe806, 0x2f },
360 	{ 0xe807, 0x2f },
361 	{ 0xea00, 0x43 },
362 	{ 0xed00, 0x80 },
363 	{ 0xed01, 0x0f },
364 	{ 0xed02, 0xff },
365 	{ 0xed03, 0x00 },
366 	{ 0xed04, 0x00 },
367 	{ 0xed05, 0x0f },
368 	{ 0xed06, 0xff },
369 	{ 0xf010, 0x10 },
370 	{ 0xf011, 0xec },
371 	{ 0xf012, 0x68 },
372 	{ 0xf013, 0x21 },
373 	{ 0xf102, 0x00 },
374 	{ 0xf103, 0x00 },
375 	{ 0xf104, 0x00 },
376 	{ 0xf105, 0x00 },
377 	{ 0xf106, 0x00 },
378 	{ 0xf107, 0x00 },
379 	{ 0xf108, 0x00 },
380 	{ 0xf109, 0x00 },
381 	{ 0xf10a, 0x03 },
382 	{ 0xf10b, 0x40 },
383 	{ 0xf20b, 0x28 },
384 	{ 0xf20d, 0x00 },
385 	{ 0xf212, 0x00 },
386 	{ 0xf21a, 0x00 },
387 	{ 0xf223, 0x40 },
388 	{ 0xf224, 0x00 },
389 	{ 0xf225, 0x00 },
390 	{ 0xf226, 0x00 },
391 	{ 0xf227, 0x00 },
392 	{ 0xf242, 0x0c },
393 	{ 0xf800, 0x00 },
394 	{ 0xf801, 0x12 },
395 	{ 0xf802, 0xe0 },
396 	{ 0xf803, 0x2f },
397 	{ 0xf804, 0x00 },
398 	{ 0xf805, 0x00 },
399 	{ 0xf806, 0x07 },
400 	{ 0xf807, 0xff },
401 };
402 
rt1318_volatile_register(struct device * dev,unsigned int reg)403 static bool rt1318_volatile_register(struct device *dev, unsigned int reg)
404 {
405 	switch (reg) {
406 	case 0xc000:
407 	case 0xc301:
408 	case 0xc410:
409 	case 0xc430 ... 0xc431:
410 	case 0xdb06:
411 	case 0xdb12:
412 	case 0xdb1d ... 0xdb1f:
413 	case 0xdb35:
414 	case 0xdb37:
415 	case 0xdb8a ... 0xdb92:
416 	case 0xdbc5 ... 0xdbc8:
417 	case 0xdc2b ... 0xdc49:
418 	case 0xdd0b:
419 	case 0xdd12:
420 	case 0xdd1d ... 0xdd1f:
421 	case 0xdd35:
422 	case 0xdd8a ... 0xdd92:
423 	case 0xddc5 ... 0xddc8:
424 	case 0xde2b ... 0xde44:
425 	case 0xdf4a ... 0xdf55:
426 	case 0xe224 ... 0xe23b:
427 	case 0xea01:
428 	case 0xebc5:
429 	case 0xebc8:
430 	case 0xebcb ... 0xebcc:
431 	case 0xed03 ... 0xed06:
432 	case 0xf010 ... 0xf014:
433 		return true;
434 
435 	default:
436 		return false;
437 	}
438 }
439 
rt1318_readable_register(struct device * dev,unsigned int reg)440 static bool rt1318_readable_register(struct device *dev, unsigned int reg)
441 {
442 	switch (reg) {
443 	case 0xc000 ... 0xc00f:
444 	case 0xc120 ... 0xc130:
445 	case 0xc200 ... 0xc20e:
446 	case 0xc300 ... 0xc303:
447 	case 0xc320 ... 0xc322:
448 	case 0xc400 ... 0xc408:
449 	case 0xc430 ... 0xc431:
450 	case 0xca00 ... 0xca02:
451 	case 0xca10 ... 0xca12:
452 	case 0xcb00 ... 0xcb0b:
453 	case 0xcc00 ... 0xcce5:
454 	case 0xcd00 ... 0xcde5:
455 	case 0xce00 ... 0xce6a:
456 	case 0xcf00 ... 0xcf53:
457 	case 0xd000 ... 0xd0cc:
458 	case 0xd100 ... 0xd1b9:
459 	case 0xdb00 ... 0xdc53:
460 	case 0xdd00 ... 0xde53:
461 	case 0xdf00 ... 0xdf6b:
462 	case 0xe000:
463 	case 0xe300:
464 	case 0xe400:
465 	case 0xe706 ... 0xe707:
466 	case 0xe806 ... 0xe807:
467 	case 0xea00:
468 	case 0xeb00 ... 0xebcc:
469 	case 0xec00 ... 0xecb9:
470 	case 0xed00 ... 0xed06:
471 	case 0xf010 ... 0xf014:
472 	case 0xf102 ... 0xf10b:
473 	case 0xf20b:
474 	case 0xf20d ... 0xf242:
475 	case 0xf800 ... 0xf807:
476 		return true;
477 	default:
478 		return false;
479 	}
480 }
481 
rt1318_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)482 static int rt1318_dac_event(struct snd_soc_dapm_widget *w,
483 	struct snd_kcontrol *kcontrol, int event)
484 {
485 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
486 	struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
487 
488 	switch (event) {
489 	case SND_SOC_DAPM_PRE_PMU:
490 		regmap_update_bits(rt1318->regmap, RT1318_PWR_STA1,
491 				RT1318_PDB_CTRL_MASK, RT1318_PDB_CTRL_HIGH);
492 		break;
493 
494 	case SND_SOC_DAPM_POST_PMD:
495 		regmap_update_bits(rt1318->regmap, RT1318_PWR_STA1,
496 				RT1318_PDB_CTRL_MASK, RT1318_PDB_CTRL_LOW);
497 		break;
498 
499 	default:
500 		break;
501 	}
502 	return 0;
503 }
504 
rt1318_dvol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)505 static int rt1318_dvol_put(struct snd_kcontrol *kcontrol,
506 		struct snd_ctl_elem_value *ucontrol)
507 {
508 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
509 	struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
510 
511 	rt1318->rt1318_dvol = ucontrol->value.integer.value[0];
512 
513 	if (rt1318->rt1318_dvol <= RT1318_DVOL_STEP && rt1318->rt1318_dvol >= 0) {
514 		regmap_write(rt1318->regmap, RT1318_DA_VOL_L_8,
515 			rt1318->rt1318_dvol >> 8);
516 		regmap_write(rt1318->regmap, RT1318_DA_VOL_L_1_7,
517 			rt1318->rt1318_dvol & 0xff);
518 		regmap_write(rt1318->regmap, RT1318_DA_VOL_R_8,
519 			rt1318->rt1318_dvol >> 8);
520 		regmap_write(rt1318->regmap, RT1318_DA_VOL_R_1_7,
521 			rt1318->rt1318_dvol & 0xff);
522 		return 1;
523 	}
524 
525 	return 0;
526 }
527 
rt1318_dvol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)528 static int rt1318_dvol_get(struct snd_kcontrol *kcontrol,
529 		struct snd_ctl_elem_value *ucontrol)
530 {
531 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
532 	struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
533 
534 	ucontrol->value.integer.value[0] = rt1318->rt1318_dvol;
535 
536 	return 0;
537 }
538 
539 static const struct snd_kcontrol_new rt1318_snd_controls[] = {
540 	SOC_SINGLE_EXT("Amp Playback Volume", SND_SOC_NOPM, 0, 383, 0,
541 		rt1318_dvol_get, rt1318_dvol_put),
542 };
543 
544 static const struct snd_soc_dapm_widget rt1318_dapm_widgets[] = {
545 	/* Audio Interface */
546 	SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
547 	/* DACs */
548 	SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
549 		rt1318_dac_event, SND_SOC_DAPM_PRE_PMU |
550 		SND_SOC_DAPM_POST_PMD),
551 	/* Output Lines */
552 	SND_SOC_DAPM_OUTPUT("Amp"),
553 };
554 
555 static const struct snd_soc_dapm_route rt1318_dapm_routes[] = {
556 	{"DAC", NULL, "AIF1RX"},
557 	{"Amp", NULL, "DAC"},
558 };
559 
rt1318_get_clk_info(int sclk,int rate)560 static int rt1318_get_clk_info(int sclk, int rate)
561 {
562 	int i, pd[] = {1, 2, 4, 8, 16, 24};
563 
564 	if (sclk <= 0 || rate <= 0)
565 		return -EINVAL;
566 
567 	rate = rate << 8;
568 	for (i = 0; i < ARRAY_SIZE(pd); i++)
569 		if (sclk == rate * pd[i])
570 			return i;
571 
572 	return -EINVAL;
573 }
574 
rt1318_clk_ip_info(struct snd_soc_component * component,int lrclk)575 static int rt1318_clk_ip_info(struct snd_soc_component *component, int lrclk)
576 {
577 	struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
578 
579 	switch (lrclk) {
580 	case RT1318_LRCLK_48000:
581 	case RT1318_LRCLK_44100:
582 	case RT1318_LRCLK_16000:
583 		regmap_update_bits(rt1318->regmap, RT1318_SRC_TCON,
584 				RT1318_SRCIN_F12288_MASK | RT1318_SRCIN_DACLK_MASK,
585 				RT1318_SRCIN_TCON4 | RT1318_DACLK_TCON4);
586 		break;
587 	case RT1318_LRCLK_96000:
588 		regmap_update_bits(rt1318->regmap, RT1318_SRC_TCON,
589 				RT1318_SRCIN_F12288_MASK | RT1318_SRCIN_DACLK_MASK,
590 				RT1318_SRCIN_TCON4 | RT1318_DACLK_TCON2);
591 		break;
592 	case RT1318_LRCLK_192000:
593 		regmap_update_bits(rt1318->regmap, RT1318_SRC_TCON,
594 				RT1318_SRCIN_F12288_MASK | RT1318_SRCIN_DACLK_MASK,
595 				RT1318_SRCIN_TCON4 | RT1318_DACLK_TCON1);
596 		break;
597 	default:
598 		dev_err(component->dev, "Unsupported clock rate.\n");
599 		return -EINVAL;
600 	}
601 
602 	return 0;
603 }
604 
rt1318_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)605 static int rt1318_hw_params(struct snd_pcm_substream *substream,
606 	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
607 {
608 	struct snd_soc_component *component = dai->component;
609 	struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
610 	int data_len = 0, ch_len = 0;
611 	int pre_div, ret;
612 
613 	rt1318->lrck = params_rate(params);
614 	pre_div = rt1318_get_clk_info(rt1318->sysclk, rt1318->lrck);
615 	if (pre_div < 0) {
616 		dev_err(component->dev, "Unsupported clock setting\n");
617 		return -EINVAL;
618 	}
619 	ret = rt1318_clk_ip_info(component, rt1318->lrck);
620 	if (ret < 0) {
621 		dev_err(component->dev, "Unsupported clock setting\n");
622 		return -EINVAL;
623 	}
624 
625 	switch (params_width(params)) {
626 	case 16:
627 		break;
628 	case 20:
629 		data_len = RT1318_I2S_DL_20;
630 		ch_len = RT1318_I2S_DL_20;
631 		break;
632 	case 24:
633 		data_len = RT1318_I2S_DL_24;
634 		ch_len = RT1318_I2S_DL_24;
635 		break;
636 	case 32:
637 		data_len = RT1318_I2S_DL_32;
638 		ch_len = RT1318_I2S_DL_32;
639 		break;
640 	case 8:
641 		data_len = RT1318_I2S_DL_8;
642 		ch_len = RT1318_I2S_DL_8;
643 		break;
644 	default:
645 		return -EINVAL;
646 	}
647 
648 	regmap_update_bits(rt1318->regmap, RT1318_CLK2,
649 				RT1318_DIV_AP_MASK | RT1318_DIV_DAMOD_MASK,
650 				pre_div << RT1318_DIV_AP_SFT |
651 				pre_div << RT1318_DIV_DAMOD_SFT);
652 	regmap_update_bits(rt1318->regmap, RT1318_CLK3,
653 				RT1318_AD_STO1_MASK | RT1318_AD_STO2_MASK,
654 				pre_div << RT1318_AD_STO1_SFT |
655 				pre_div << RT1318_AD_STO2_SFT);
656 	regmap_update_bits(rt1318->regmap, RT1318_CLK4,
657 				RT1318_AD_ANA_STO1_MASK | RT1318_AD_ANA_STO2_MASK,
658 				pre_div << RT1318_AD_ANA_STO1_SFT |
659 				pre_div << RT1318_AD_ANA_STO2_SFT);
660 	regmap_update_bits(rt1318->regmap, RT1318_CLK5,
661 				RT1318_DIV_FIFO_IN_MASK | RT1318_DIV_FIFO_OUT_MASK,
662 				pre_div << RT1318_DIV_FIFO_IN_SFT |
663 				pre_div << RT1318_DIV_FIFO_OUT_SFT);
664 	regmap_update_bits(rt1318->regmap, RT1318_CLK6,
665 				RT1318_DIV_NLMS_MASK | RT1318_DIV_AD_MONO_MASK |
666 				RT1318_DIV_POST_G_MASK,  pre_div << RT1318_DIV_NLMS_SFT |
667 				pre_div << RT1318_DIV_AD_MONO_SFT |
668 				pre_div << RT1318_DIV_POST_G_SFT);
669 
670 	regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL2,
671 				RT1318_I2S_DL_MASK, data_len << RT1318_I2S_DL_SFT);
672 	regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL3,
673 				RT1318_I2S_TX_CHL_MASK | RT1318_I2S_RX_CHL_MASK,
674 				ch_len << RT1318_I2S_TX_CHL_SFT |
675 				ch_len << RT1318_I2S_RX_CHL_SFT);
676 
677 	return 0;
678 }
679 
rt1318_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)680 static int rt1318_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
681 {
682 	struct snd_soc_component *component = dai->component;
683 	struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
684 	unsigned int reg_val = 0, reg_val2 = 0;
685 
686 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
687 	case SND_SOC_DAIFMT_NB_NF:
688 		break;
689 	case SND_SOC_DAIFMT_IB_NF:
690 		reg_val2 |= RT1318_TDM_BCLK_INV;
691 		break;
692 	default:
693 		return -EINVAL;
694 	}
695 
696 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
697 	case SND_SOC_DAIFMT_I2S:
698 		break;
699 
700 	case SND_SOC_DAIFMT_LEFT_J:
701 		reg_val |= RT1318_FMT_LEFT_J;
702 		break;
703 
704 	case SND_SOC_DAIFMT_DSP_A:
705 		reg_val |= RT1318_FMT_PCM_A_R;
706 		break;
707 
708 	case SND_SOC_DAIFMT_DSP_B:
709 		reg_val |= RT1318_FMT_PCM_B_R;
710 		break;
711 
712 	default:
713 		return -EINVAL;
714 	}
715 
716 	regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL1,
717 			RT1318_I2S_FMT_MASK, reg_val);
718 	regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL1,
719 			RT1318_TDM_BCLK_MASK, reg_val2);
720 
721 	return 0;
722 }
723 
rt1318_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)724 static int rt1318_set_dai_sysclk(struct snd_soc_dai *dai,
725 		int clk_id, unsigned int freq, int dir)
726 {
727 	struct snd_soc_component *component = dai->component;
728 	struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
729 	int reg_val = 0;
730 
731 	if (freq == rt1318->sysclk && clk_id == rt1318->sysclk_src)
732 		return 0;
733 
734 	switch (clk_id) {
735 	case RT1318_SCLK_S_BCLK:
736 		reg_val |= RT1318_SYSCLK_BCLK;
737 		break;
738 	case RT1318_SCLK_S_SDW:
739 		reg_val |= RT1318_SYSCLK_SDW;
740 		break;
741 	case RT1318_SCLK_S_PLL2F:
742 		reg_val |= RT1318_SYSCLK_PLL2F;
743 		break;
744 	case RT1318_SCLK_S_PLL2B:
745 		reg_val |= RT1318_SYSCLK_PLL2B;
746 		break;
747 	case RT1318_SCLK_S_MCLK:
748 		reg_val |= RT1318_SYSCLK_MCLK;
749 		break;
750 	case RT1318_SCLK_S_RC0:
751 		reg_val |= RT1318_SYSCLK_RC1;
752 		break;
753 	case RT1318_SCLK_S_RC1:
754 		reg_val |= RT1318_SYSCLK_RC2;
755 		break;
756 	case RT1318_SCLK_S_RC2:
757 		reg_val |= RT1318_SYSCLK_RC3;
758 		break;
759 	default:
760 		dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
761 		return -EINVAL;
762 	}
763 
764 	rt1318->sysclk = freq;
765 	rt1318->sysclk_src = clk_id;
766 	dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
767 	regmap_update_bits(rt1318->regmap, RT1318_CLK1,
768 			RT1318_SYSCLK_SEL_MASK, reg_val);
769 
770 	return 0;
771 }
772 
773 static const struct pll_calc_map pll_preset_table[] = {
774 	{512000, 4096000, 22, 190, 0, true, false},
775 	{1024000, 4096000, 22, 94, 0, true, false},
776 	{1024000, 16384000, 4, 190, 0, true, false},
777 	{1411200, 11289600, 6, 62, 0, true, false},
778 	{1536000, 12288000, 6, 62, 0, true, false},
779 	{2822400, 11289600, 6, 62, 0, true, false},
780 	{2822400, 45158400, 0, 62, 0, true, false},
781 	{2822400, 49152000, 0, 62, 0, true, false},
782 	{3072000, 12288000, 6, 62, 0, true, false},
783 	{3072000, 24576000, 2, 62, 0, true, false},
784 	{3072000, 49152000, 0, 62, 0, true, false},
785 	{6144000, 24576000, 2, 94, 4, false, false},
786 	{6144000, 49152000, 0, 30, 0, true, false},
787 	{6144000, 98304000, 0, 94, 4, false, true},
788 	{12288000, 49152000, 0, 62, 6, false, false},
789 };
790 
rt1318_pll_calc(const unsigned int freq_in,const unsigned int freq_out,struct rt1318_pll_code * pll_code)791 static int rt1318_pll_calc(const unsigned int freq_in,
792 	const unsigned int freq_out, struct rt1318_pll_code *pll_code)
793 {
794 	int max_n = RT1318_PLL_N_MAX, max_m = RT1318_PLL_M_MAX;
795 	int i, k, red, n_t, pll_out, in_t, out_t;
796 	int n = 0, m = 0, m_t = 0;
797 	int red_t = abs(freq_out - freq_in);
798 	bool m_bypass = false, k_bypass = false;
799 
800 	if (RT1318_PLL_INP_MAX < freq_in || RT1318_PLL_INP_MIN > freq_in)
801 		return -EINVAL;
802 
803 	for (i = 0; i < ARRAY_SIZE(pll_preset_table); i++) {
804 		if (freq_in == pll_preset_table[i].pll_in &&
805 			freq_out == pll_preset_table[i].pll_out) {
806 			k = pll_preset_table[i].k;
807 			m = pll_preset_table[i].m;
808 			n = pll_preset_table[i].n;
809 			m_bypass = pll_preset_table[i].m_bp;
810 			k_bypass = pll_preset_table[i].k_bp;
811 			goto code_find;
812 		}
813 	}
814 
815 	k = 100000000 / freq_out - 2;
816 	if (k > RT1318_PLL_K_MAX)
817 		k = RT1318_PLL_K_MAX;
818 	if (k < 0) {
819 		k = 0;
820 		k_bypass = true;
821 	}
822 	for (n_t = 0; n_t <= max_n; n_t++) {
823 		in_t = freq_in / (k_bypass ? 1 : (k + 2));
824 		pll_out = freq_out / (n_t + 2);
825 		if (in_t < 0)
826 			continue;
827 		if (in_t == pll_out) {
828 			m_bypass = true;
829 			n = n_t;
830 			goto code_find;
831 		}
832 		red = abs(in_t - pll_out);
833 		if (red < red_t) {
834 			m_bypass = true;
835 			n = n_t;
836 			m = m_t;
837 			if (red == 0)
838 				goto code_find;
839 			red_t = red;
840 		}
841 		for (m_t = 0; m_t <= max_m; m_t++) {
842 			out_t = in_t / (m_t + 2);
843 			red = abs(out_t - pll_out);
844 			if (red < red_t) {
845 				m_bypass = false;
846 				n = n_t;
847 				m = m_t;
848 				if (red == 0)
849 					goto code_find;
850 				red_t = red;
851 			}
852 		}
853 	}
854 	pr_debug("Only get approximation about PLL\n");
855 
856 code_find:
857 
858 	pll_code->m_bp = m_bypass;
859 	pll_code->k_bp = k_bypass;
860 	pll_code->m_code = m;
861 	pll_code->n_code = n;
862 	pll_code->k_code = k;
863 	return 0;
864 }
865 
rt1318_set_dai_pll(struct snd_soc_dai * dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)866 static int rt1318_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
867 			unsigned int freq_in, unsigned int freq_out)
868 {
869 	struct snd_soc_component *component = dai->component;
870 	struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
871 	struct rt1318_pll_code pll_code;
872 	int ret;
873 
874 	if (!freq_in || !freq_out) {
875 		dev_dbg(component->dev, "PLL disabled\n");
876 		rt1318->pll_in = 0;
877 		rt1318->pll_out = 0;
878 		return 0;
879 	}
880 
881 	if (source == rt1318->pll_src && freq_in == rt1318->pll_in &&
882 		freq_out == rt1318->pll_out)
883 		return 0;
884 
885 	switch (source) {
886 	case RT1318_PLL_S_BCLK0:
887 		regmap_update_bits(rt1318->regmap, RT1318_CLK1,
888 			RT1318_PLLIN_MASK, RT1318_PLLIN_BCLK0);
889 		break;
890 	case RT1318_PLL_S_BCLK1:
891 		regmap_update_bits(rt1318->regmap, RT1318_CLK1,
892 			RT1318_PLLIN_MASK, RT1318_PLLIN_BCLK1);
893 		break;
894 	case RT1318_PLL_S_RC:
895 		regmap_update_bits(rt1318->regmap, RT1318_CLK1,
896 			RT1318_PLLIN_MASK, RT1318_PLLIN_RC);
897 		break;
898 	case RT1318_PLL_S_MCLK:
899 		regmap_update_bits(rt1318->regmap, RT1318_CLK1,
900 			RT1318_PLLIN_MASK, RT1318_PLLIN_MCLK);
901 		break;
902 	case RT1318_PLL_S_SDW_IN_PLL:
903 		regmap_update_bits(rt1318->regmap, RT1318_CLK1,
904 			RT1318_PLLIN_MASK, RT1318_PLLIN_SDW1);
905 		break;
906 	case RT1318_PLL_S_SDW_0:
907 		regmap_update_bits(rt1318->regmap, RT1318_CLK1,
908 			RT1318_PLLIN_MASK, RT1318_PLLIN_SDW2);
909 		break;
910 	case RT1318_PLL_S_SDW_1:
911 		regmap_update_bits(rt1318->regmap, RT1318_CLK1,
912 			RT1318_PLLIN_MASK, RT1318_PLLIN_SDW3);
913 		break;
914 	case RT1318_PLL_S_SDW_2:
915 		regmap_update_bits(rt1318->regmap, RT1318_CLK1,
916 			RT1318_PLLIN_MASK, RT1318_PLLIN_SDW4);
917 		break;
918 	default:
919 		dev_err(component->dev, "Unknown PLL source %d\n", source);
920 		return -EINVAL;
921 	}
922 
923 	ret = rt1318_pll_calc(freq_in, freq_out, &pll_code);
924 	if (ret < 0) {
925 		dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
926 		return ret;
927 	}
928 
929 	dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
930 		pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
931 		pll_code.n_code, pll_code.k_code);
932 
933 	regmap_update_bits(rt1318->regmap, RT1318_PLL1_K,
934 			RT1318_K_PLL1_MASK, pll_code.k_code);
935 	regmap_update_bits(rt1318->regmap, RT1318_PLL1_M,
936 			RT1318_M_PLL1_MASK, (pll_code.m_bp ? 0 : pll_code.m_code));
937 	regmap_update_bits(rt1318->regmap, RT1318_PLL1_N_8,
938 			RT1318_N_8_PLL1_MASK, pll_code.n_code >> 8);
939 	regmap_update_bits(rt1318->regmap, RT1318_PLL1_N_7_0,
940 			RT1318_N_7_0_PLL1_MASK, pll_code.n_code);
941 
942 	rt1318->pll_in = freq_in;
943 	rt1318->pll_out = freq_out;
944 	rt1318->pll_src = source;
945 
946 	return 0;
947 }
948 
rt1318_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)949 static int rt1318_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
950 			unsigned int rx_mask, int slots, int slot_width)
951 {
952 	struct snd_soc_component *component = dai->component;
953 	struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
954 	unsigned int cn = 0, cl = 0, rx_slotnum;
955 	int ret = 0, first_bit;
956 
957 	switch (slots) {
958 	case 4:
959 		cn |= RT1318_I2S_CH_TX_4CH;
960 		cn |= RT1318_I2S_CH_RX_4CH;
961 		break;
962 	case 6:
963 		cn |= RT1318_I2S_CH_TX_6CH;
964 		cn |= RT1318_I2S_CH_RX_6CH;
965 		break;
966 	case 8:
967 		cn |= RT1318_I2S_CH_TX_8CH;
968 		cn |= RT1318_I2S_CH_RX_8CH;
969 		break;
970 	case 2:
971 		break;
972 	default:
973 		return -EINVAL;
974 	}
975 
976 	switch (slot_width) {
977 	case 20:
978 		cl |= RT1318_I2S_TX_CHL_20;
979 		cl |= RT1318_I2S_RX_CHL_20;
980 		break;
981 	case 24:
982 		cl |= RT1318_I2S_TX_CHL_24;
983 		cl |= RT1318_I2S_RX_CHL_24;
984 		break;
985 	case 32:
986 		cl |= RT1318_I2S_TX_CHL_32;
987 		cl |= RT1318_I2S_RX_CHL_32;
988 		break;
989 	case 8:
990 		cl |= RT1318_I2S_TX_CHL_8;
991 		cl |= RT1318_I2S_RX_CHL_8;
992 		break;
993 	case 16:
994 		break;
995 	default:
996 		return -EINVAL;
997 	}
998 
999 	/* Rx slot configuration */
1000 	rx_slotnum = hweight_long(rx_mask);
1001 	if (rx_slotnum != 1) {
1002 		ret = -EINVAL;
1003 		dev_err(component->dev, "too many rx slots or zero slot\n");
1004 		goto _set_tdm_err_;
1005 	}
1006 
1007 	first_bit = __ffs(rx_mask);
1008 	switch (first_bit) {
1009 	case 0:
1010 	case 2:
1011 	case 4:
1012 	case 6:
1013 		regmap_update_bits(rt1318->regmap,
1014 			RT1318_TDM_CTRL9,
1015 			RT1318_TDM_I2S_TX_L_DAC1_1_MASK |
1016 			RT1318_TDM_I2S_TX_R_DAC1_1_MASK,
1017 			(first_bit << RT1318_TDM_I2S_TX_L_DAC1_1_SFT) |
1018 			((first_bit + 1) << RT1318_TDM_I2S_TX_R_DAC1_1_SFT));
1019 		break;
1020 	case 1:
1021 	case 3:
1022 	case 5:
1023 	case 7:
1024 		regmap_update_bits(rt1318->regmap,
1025 			RT1318_TDM_CTRL9,
1026 			RT1318_TDM_I2S_TX_L_DAC1_1_MASK |
1027 			RT1318_TDM_I2S_TX_R_DAC1_1_MASK,
1028 			((first_bit - 1) << RT1318_TDM_I2S_TX_L_DAC1_1_SFT) |
1029 			(first_bit << RT1318_TDM_I2S_TX_R_DAC1_1_SFT));
1030 		break;
1031 	default:
1032 		ret = -EINVAL;
1033 		goto _set_tdm_err_;
1034 	}
1035 
1036 	regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL2,
1037 			RT1318_I2S_CH_TX_MASK | RT1318_I2S_CH_RX_MASK, cn);
1038 	regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL3,
1039 			RT1318_I2S_TX_CHL_MASK | RT1318_I2S_RX_CHL_MASK, cl);
1040 
1041 _set_tdm_err_:
1042 	return ret;
1043 }
1044 
rt1318_probe(struct snd_soc_component * component)1045 static int rt1318_probe(struct snd_soc_component *component)
1046 {
1047 	struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
1048 
1049 	rt1318->component = component;
1050 
1051 	schedule_work(&rt1318->cali_work);
1052 	rt1318->rt1318_dvol = RT1318_DVOL_STEP;
1053 
1054 	return 0;
1055 }
1056 
rt1318_remove(struct snd_soc_component * component)1057 static void rt1318_remove(struct snd_soc_component *component)
1058 {
1059 	struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
1060 
1061 	cancel_work_sync(&rt1318->cali_work);
1062 }
1063 
1064 #ifdef CONFIG_PM
rt1318_suspend(struct snd_soc_component * component)1065 static int rt1318_suspend(struct snd_soc_component *component)
1066 {
1067 	struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
1068 
1069 	regcache_cache_only(rt1318->regmap, true);
1070 	regcache_mark_dirty(rt1318->regmap);
1071 	return 0;
1072 }
1073 
rt1318_resume(struct snd_soc_component * component)1074 static int rt1318_resume(struct snd_soc_component *component)
1075 {
1076 	struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
1077 
1078 	regcache_cache_only(rt1318->regmap, false);
1079 	regcache_sync(rt1318->regmap);
1080 	return 0;
1081 }
1082 #else
1083 #define rt1318_suspend NULL
1084 #define rt1318_resume NULL
1085 #endif
1086 
1087 #define RT1318_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1088 #define RT1318_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1089 			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1090 
1091 static const struct snd_soc_dai_ops rt1318_aif_dai_ops = {
1092 	.hw_params = rt1318_hw_params,
1093 	.set_fmt = rt1318_set_dai_fmt,
1094 	.set_sysclk = rt1318_set_dai_sysclk,
1095 	.set_pll = rt1318_set_dai_pll,
1096 	.set_tdm_slot = rt1318_set_tdm_slot,
1097 };
1098 
1099 static struct snd_soc_dai_driver rt1318_dai[] = {
1100 	{
1101 		.name = "rt1318-aif",
1102 		.id = 0,
1103 		.playback = {
1104 			.stream_name = "AIF1 Playback",
1105 			.channels_min = 1,
1106 			.channels_max = 2,
1107 			.rates = RT1318_STEREO_RATES,
1108 			.formats = RT1318_FORMATS,
1109 		},
1110 		.ops = &rt1318_aif_dai_ops,
1111 	}
1112 };
1113 
1114 static const struct snd_soc_component_driver soc_component_dev_rt1318 = {
1115 	.probe = rt1318_probe,
1116 	.remove = rt1318_remove,
1117 	.suspend = rt1318_suspend,
1118 	.resume = rt1318_resume,
1119 	.controls = rt1318_snd_controls,
1120 	.num_controls = ARRAY_SIZE(rt1318_snd_controls),
1121 	.dapm_widgets = rt1318_dapm_widgets,
1122 	.num_dapm_widgets = ARRAY_SIZE(rt1318_dapm_widgets),
1123 	.dapm_routes = rt1318_dapm_routes,
1124 	.num_dapm_routes = ARRAY_SIZE(rt1318_dapm_routes),
1125 	.use_pmdown_time = 1,
1126 	.endianness = 1,
1127 };
1128 
1129 static const struct regmap_config rt1318_regmap = {
1130 	.reg_bits = 32,
1131 	.val_bits = 8,
1132 	.readable_reg = rt1318_readable_register,
1133 	.volatile_reg = rt1318_volatile_register,
1134 	.max_register = 0x41001888,
1135 	.reg_defaults = rt1318_reg,
1136 	.num_reg_defaults = ARRAY_SIZE(rt1318_reg),
1137 	.cache_type = REGCACHE_RBTREE,
1138 	.use_single_read = true,
1139 	.use_single_write = true,
1140 };
1141 
1142 static const struct i2c_device_id rt1318_i2c_id[] = {
1143 	{ "rt1318" },
1144 	{ }
1145 };
1146 MODULE_DEVICE_TABLE(i2c, rt1318_i2c_id);
1147 
1148 static const struct of_device_id rt1318_of_match[] = {
1149 	{ .compatible = "realtek,rt1318", },
1150 	{},
1151 };
1152 MODULE_DEVICE_TABLE(of, rt1318_of_match);
1153 
1154 #ifdef CONFIG_ACPI
1155 static const struct acpi_device_id rt1318_acpi_match[] = {
1156 	{ "10EC1318", 0},
1157 	{ },
1158 };
1159 MODULE_DEVICE_TABLE(acpi, rt1318_acpi_match);
1160 #endif
1161 
rt1318_parse_dt(struct rt1318_priv * rt1318,struct device * dev)1162 static int rt1318_parse_dt(struct rt1318_priv *rt1318, struct device *dev)
1163 {
1164 	device_property_read_u32(dev, "realtek,r0_l",
1165 		&rt1318->pdata.init_r0_l);
1166 	device_property_read_u32(dev, "realtek,r0_r",
1167 		&rt1318->pdata.init_r0_r);
1168 
1169 	return 0;
1170 }
1171 
rt1318_calibration_sequence(struct rt1318_priv * rt1318)1172 static void rt1318_calibration_sequence(struct rt1318_priv *rt1318)
1173 {
1174 	regmap_write(rt1318->regmap, RT1318_CLK1, 0x22);
1175 	regmap_write(rt1318->regmap, RT1318_PLL1_N_7_0, 0x06);
1176 	regmap_write(rt1318->regmap, RT1318_STP_TEMP_L, 0xCC);
1177 	regmap_write(rt1318->regmap, RT1318_STP_SEL_L, 0x40);
1178 	regmap_write(rt1318->regmap, RT1318_STP_SEL_R, 0x40);
1179 	regmap_write(rt1318->regmap, RT1318_SINE_GEN0, 0x20);
1180 	regmap_write(rt1318->regmap, RT1318_SPK_VOL_TH, 0x00);
1181 	regmap_write(rt1318->regmap, RT1318_FEEDBACK_PATH, 0x0B);
1182 	regmap_write(rt1318->regmap, RT1318_TCON, 0x1C);
1183 	regmap_write(rt1318->regmap, RT1318_TCON_RELATE, 0x58);
1184 	regmap_write(rt1318->regmap, RT1318_TCON_RELATE, 0x78);
1185 	regmap_write(rt1318->regmap, RT1318_STP_R0_EN_L, 0xC2);
1186 }
1187 
rt1318_r0_calculate(struct rt1318_priv * rt1318)1188 static void rt1318_r0_calculate(struct rt1318_priv *rt1318)
1189 {
1190 	unsigned int r0_l, r0_l_byte0, r0_l_byte1, r0_l_byte2, r0_l_byte3;
1191 	unsigned int r0_r, r0_r_byte0, r0_r_byte1, r0_r_byte2, r0_r_byte3;
1192 	unsigned int r0_l_integer, r0_l_factor, r0_r_integer, r0_r_factor;
1193 	unsigned int format = 16777216; /* 2^24 */
1194 
1195 	regmap_read(rt1318->regmap, RT1318_R0_L_24, &r0_l_byte0);
1196 	regmap_read(rt1318->regmap, RT1318_R0_L_23_16, &r0_l_byte1);
1197 	regmap_read(rt1318->regmap, RT1318_R0_L_15_8, &r0_l_byte2);
1198 	regmap_read(rt1318->regmap, RT1318_R0_L_7_0, &r0_l_byte3);
1199 	r0_l = r0_l_byte0 << 24 | r0_l_byte1 << 16 | r0_l_byte2 << 8 | r0_l_byte3;
1200 	r0_l_integer = format / r0_l;
1201 	r0_l_factor = (format * 10) / r0_l - r0_l_integer * 10;
1202 
1203 	regmap_read(rt1318->regmap, RT1318_R0_R_24, &r0_r_byte0);
1204 	regmap_read(rt1318->regmap, RT1318_R0_R_23_16, &r0_r_byte1);
1205 	regmap_read(rt1318->regmap, RT1318_R0_R_15_8, &r0_r_byte2);
1206 	regmap_read(rt1318->regmap, RT1318_R0_R_7_0, &r0_r_byte3);
1207 	r0_r = r0_r_byte0 << 24 | r0_r_byte1 << 16 | r0_r_byte2 << 8 | r0_r_byte3;
1208 	r0_r_integer = format / r0_r;
1209 	r0_r_factor = (format * 10) / r0_r - r0_r_integer * 10;
1210 
1211 	dev_dbg(rt1318->component->dev, "r0_l_ch:%d.%d ohm\n", r0_l_integer, r0_l_factor);
1212 	dev_dbg(rt1318->component->dev, "r0_r_ch:%d.%d ohm\n", r0_r_integer, r0_r_factor);
1213 }
1214 
rt1318_r0_restore(struct rt1318_priv * rt1318)1215 static void rt1318_r0_restore(struct rt1318_priv *rt1318)
1216 {
1217 	regmap_write(rt1318->regmap, RT1318_PRE_R0_L_24,
1218 		(rt1318->pdata.init_r0_l >> 24) & 0xff);
1219 	regmap_write(rt1318->regmap, RT1318_PRE_R0_L_23_16,
1220 		(rt1318->pdata.init_r0_l >> 16) & 0xff);
1221 	regmap_write(rt1318->regmap, RT1318_PRE_R0_L_15_8,
1222 		(rt1318->pdata.init_r0_l >> 8) & 0xff);
1223 	regmap_write(rt1318->regmap, RT1318_PRE_R0_L_7_0,
1224 		(rt1318->pdata.init_r0_l >> 0) & 0xff);
1225 	regmap_write(rt1318->regmap, RT1318_PRE_R0_R_24,
1226 		(rt1318->pdata.init_r0_r >> 24) & 0xff);
1227 	regmap_write(rt1318->regmap, RT1318_PRE_R0_R_23_16,
1228 		(rt1318->pdata.init_r0_r >> 16) & 0xff);
1229 	regmap_write(rt1318->regmap, RT1318_PRE_R0_R_15_8,
1230 		(rt1318->pdata.init_r0_r >> 8) & 0xff);
1231 	regmap_write(rt1318->regmap, RT1318_PRE_R0_R_7_0,
1232 		(rt1318->pdata.init_r0_r >> 0) & 0xff);
1233 	regmap_write(rt1318->regmap, RT1318_STP_SEL_L, 0x80);
1234 	regmap_write(rt1318->regmap, RT1318_STP_SEL_R, 0x80);
1235 	regmap_write(rt1318->regmap, RT1318_R0_CMP_L_FLAG, 0xc0);
1236 	regmap_write(rt1318->regmap, RT1318_R0_CMP_R_FLAG, 0xc0);
1237 	regmap_write(rt1318->regmap, RT1318_STP_R0_EN_L, 0xc0);
1238 	regmap_write(rt1318->regmap, RT1318_STP_R0_EN_R, 0xc0);
1239 	regmap_write(rt1318->regmap, RT1318_STP_TEMP_L, 0xcc);
1240 	regmap_write(rt1318->regmap, RT1318_TCON, 0x9c);
1241 }
1242 
rt1318_calibrate(struct rt1318_priv * rt1318)1243 static int rt1318_calibrate(struct rt1318_priv *rt1318)
1244 {
1245 	int chk_cnt = 30, count = 0;
1246 	int val, val2;
1247 
1248 	regmap_write(rt1318->regmap, RT1318_PWR_STA1, 0x1);
1249 	usleep_range(0, 10000);
1250 	rt1318_calibration_sequence(rt1318);
1251 
1252 	while (count < chk_cnt) {
1253 		msleep(100);
1254 		regmap_read(rt1318->regmap, RT1318_R0_CMP_L_FLAG, &val);
1255 		regmap_read(rt1318->regmap, RT1318_R0_CMP_R_FLAG, &val2);
1256 		val = (val >> 1) & 0x1;
1257 		val2 = (val2 >> 1) & 0x1;
1258 		if (val & val2) {
1259 			dev_dbg(rt1318->component->dev, "Calibration done.\n");
1260 			break;
1261 		}
1262 		count++;
1263 		if (count == chk_cnt) {
1264 			regmap_write(rt1318->regmap, RT1318_PWR_STA1, 0x0);
1265 			return RT1318_R0_CALIB_NOT_DONE;
1266 		}
1267 	}
1268 	regmap_write(rt1318->regmap, RT1318_PWR_STA1, 0x0);
1269 	regmap_read(rt1318->regmap, RT1318_R0_CMP_L_FLAG, &val);
1270 	regmap_read(rt1318->regmap, RT1318_R0_CMP_R_FLAG, &val2);
1271 	if ((val & 0x1) & (val2 & 0x1))
1272 		return RT1318_R0_IN_RANGE;
1273 	else
1274 		return RT1318_R0_OUT_OF_RANGE;
1275 }
1276 
rt1318_calibration_work(struct work_struct * work)1277 static void rt1318_calibration_work(struct work_struct *work)
1278 {
1279 	struct rt1318_priv *rt1318 =
1280 		container_of(work, struct rt1318_priv, cali_work);
1281 	int ret;
1282 
1283 	if (rt1318->pdata.init_r0_l && rt1318->pdata.init_r0_r)
1284 		rt1318_r0_restore(rt1318);
1285 	else {
1286 		ret = rt1318_calibrate(rt1318);
1287 		if (ret == RT1318_R0_IN_RANGE)
1288 			rt1318_r0_calculate(rt1318);
1289 		dev_dbg(rt1318->component->dev, "Calibrate R0 result:%d\n", ret);
1290 	}
1291 }
1292 
rt1318_i2c_probe(struct i2c_client * i2c)1293 static int rt1318_i2c_probe(struct i2c_client *i2c)
1294 {
1295 	struct rt1318_platform_data *pdata = dev_get_platdata(&i2c->dev);
1296 	struct rt1318_priv *rt1318;
1297 	int ret, val, val2, dev_id;
1298 
1299 	rt1318 = devm_kzalloc(&i2c->dev, sizeof(struct rt1318_priv),
1300 				GFP_KERNEL);
1301 	if (!rt1318)
1302 		return -ENOMEM;
1303 
1304 	i2c_set_clientdata(i2c, rt1318);
1305 
1306 	if (pdata)
1307 		rt1318->pdata = *pdata;
1308 	else
1309 		rt1318_parse_dt(rt1318, &i2c->dev);
1310 
1311 	rt1318->regmap = devm_regmap_init_i2c(i2c, &rt1318_regmap);
1312 	if (IS_ERR(rt1318->regmap)) {
1313 		ret = PTR_ERR(rt1318->regmap);
1314 		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1315 			ret);
1316 		return ret;
1317 	}
1318 
1319 	regmap_read(rt1318->regmap, RT1318_DEV_ID1, &val);
1320 	regmap_read(rt1318->regmap, RT1318_DEV_ID2, &val2);
1321 	dev_id = (val << 8) | val2;
1322 	if (dev_id != 0x6821) {
1323 		dev_err(&i2c->dev,
1324 			"Device with ID register %#x is not rt1318\n",
1325 			dev_id);
1326 		return -ENODEV;
1327 	}
1328 
1329 	ret = regmap_register_patch(rt1318->regmap, init_list,
1330 				    ARRAY_SIZE(init_list));
1331 	if (ret != 0)
1332 		dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1333 
1334 	INIT_WORK(&rt1318->cali_work, rt1318_calibration_work);
1335 
1336 	return devm_snd_soc_register_component(&i2c->dev,
1337 		&soc_component_dev_rt1318, rt1318_dai, ARRAY_SIZE(rt1318_dai));
1338 }
1339 
1340 static struct i2c_driver rt1318_i2c_driver = {
1341 	.driver = {
1342 		.name = "rt1318",
1343 		.of_match_table = of_match_ptr(rt1318_of_match),
1344 		.acpi_match_table = ACPI_PTR(rt1318_acpi_match),
1345 	},
1346 	.probe = rt1318_i2c_probe,
1347 	.id_table = rt1318_i2c_id,
1348 };
1349 module_i2c_driver(rt1318_i2c_driver);
1350 
1351 MODULE_DESCRIPTION("ASoC RT1318 driver");
1352 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1353 MODULE_LICENSE("GPL");
1354