1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/mbuf.h>
39 #include <sys/rman.h>
40 #include <sys/module.h>
41 #include <sys/queue.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
46
47 #include <net/bpf.h>
48 #include <net/if.h>
49 #include <net/if_var.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/if_types.h>
55 #include <net/if_vlan_var.h>
56
57 #include <netinet/in.h>
58 #include <netinet/in_systm.h>
59 #include <netinet/ip.h>
60 #include <netinet/tcp.h>
61
62 #include <dev/mii/mii.h>
63 #include <dev/mii/miivar.h>
64
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/pcivar.h>
67
68 #include <machine/bus.h>
69 #include <machine/in_cksum.h>
70
71 #include <dev/age/if_agereg.h>
72 #include <dev/age/if_agevar.h>
73
74 /* "device miibus" required. See GENERIC if you get errors here. */
75 #include "miibus_if.h"
76
77 #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
78
79 MODULE_DEPEND(age, pci, 1, 1, 1);
80 MODULE_DEPEND(age, ether, 1, 1, 1);
81 MODULE_DEPEND(age, miibus, 1, 1, 1);
82
83 /* Tunables. */
84 static int msi_disable = 0;
85 static int msix_disable = 0;
86 TUNABLE_INT("hw.age.msi_disable", &msi_disable);
87 TUNABLE_INT("hw.age.msix_disable", &msix_disable);
88
89 /*
90 * Devices supported by this driver.
91 */
92 static struct age_dev {
93 uint16_t age_vendorid;
94 uint16_t age_deviceid;
95 const char *age_name;
96 } age_devs[] = {
97 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1,
98 "Attansic Technology Corp, L1 Gigabit Ethernet" },
99 };
100
101 static int age_miibus_readreg(device_t, int, int);
102 static int age_miibus_writereg(device_t, int, int, int);
103 static void age_miibus_statchg(device_t);
104 static void age_mediastatus(if_t, struct ifmediareq *);
105 static int age_mediachange(if_t);
106 static int age_probe(device_t);
107 static void age_get_macaddr(struct age_softc *);
108 static void age_phy_reset(struct age_softc *);
109 static int age_attach(device_t);
110 static int age_detach(device_t);
111 static void age_sysctl_node(struct age_softc *);
112 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int);
113 static int age_check_boundary(struct age_softc *);
114 static int age_dma_alloc(struct age_softc *);
115 static void age_dma_free(struct age_softc *);
116 static int age_shutdown(device_t);
117 static void age_setwol(struct age_softc *);
118 static int age_suspend(device_t);
119 static int age_resume(device_t);
120 static int age_encap(struct age_softc *, struct mbuf **);
121 static void age_start(if_t);
122 static void age_start_locked(if_t);
123 static void age_watchdog(struct age_softc *);
124 static int age_ioctl(if_t, u_long, caddr_t);
125 static void age_mac_config(struct age_softc *);
126 static void age_link_task(void *, int);
127 static void age_stats_update(struct age_softc *);
128 static int age_intr(void *);
129 static void age_int_task(void *, int);
130 static void age_txintr(struct age_softc *, int);
131 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *);
132 static int age_rxintr(struct age_softc *, int, int);
133 static void age_tick(void *);
134 static void age_reset(struct age_softc *);
135 static void age_init(void *);
136 static void age_init_locked(struct age_softc *);
137 static void age_stop(struct age_softc *);
138 static void age_stop_txmac(struct age_softc *);
139 static void age_stop_rxmac(struct age_softc *);
140 static void age_init_tx_ring(struct age_softc *);
141 static int age_init_rx_ring(struct age_softc *);
142 static void age_init_rr_ring(struct age_softc *);
143 static void age_init_cmb_block(struct age_softc *);
144 static void age_init_smb_block(struct age_softc *);
145 #ifndef __NO_STRICT_ALIGNMENT
146 static struct mbuf *age_fixup_rx(if_t, struct mbuf *);
147 #endif
148 static int age_newbuf(struct age_softc *, struct age_rxdesc *);
149 static void age_rxvlan(struct age_softc *);
150 static void age_rxfilter(struct age_softc *);
151 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS);
152 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
153 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS);
154 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS);
155
156 static device_method_t age_methods[] = {
157 /* Device interface. */
158 DEVMETHOD(device_probe, age_probe),
159 DEVMETHOD(device_attach, age_attach),
160 DEVMETHOD(device_detach, age_detach),
161 DEVMETHOD(device_shutdown, age_shutdown),
162 DEVMETHOD(device_suspend, age_suspend),
163 DEVMETHOD(device_resume, age_resume),
164
165 /* MII interface. */
166 DEVMETHOD(miibus_readreg, age_miibus_readreg),
167 DEVMETHOD(miibus_writereg, age_miibus_writereg),
168 DEVMETHOD(miibus_statchg, age_miibus_statchg),
169 { NULL, NULL }
170 };
171
172 static driver_t age_driver = {
173 "age",
174 age_methods,
175 sizeof(struct age_softc)
176 };
177
178 DRIVER_MODULE(age, pci, age_driver, 0, 0);
179 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, age, age_devs,
180 nitems(age_devs));
181 DRIVER_MODULE(miibus, age, miibus_driver, 0, 0);
182
183 static struct resource_spec age_res_spec_mem[] = {
184 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
185 { -1, 0, 0 }
186 };
187
188 static struct resource_spec age_irq_spec_legacy[] = {
189 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
190 { -1, 0, 0 }
191 };
192
193 static struct resource_spec age_irq_spec_msi[] = {
194 { SYS_RES_IRQ, 1, RF_ACTIVE },
195 { -1, 0, 0 }
196 };
197
198 static struct resource_spec age_irq_spec_msix[] = {
199 { SYS_RES_IRQ, 1, RF_ACTIVE },
200 { -1, 0, 0 }
201 };
202
203 /*
204 * Read a PHY register on the MII of the L1.
205 */
206 static int
age_miibus_readreg(device_t dev,int phy,int reg)207 age_miibus_readreg(device_t dev, int phy, int reg)
208 {
209 struct age_softc *sc;
210 uint32_t v;
211 int i;
212
213 sc = device_get_softc(dev);
214
215 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
216 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
217 for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
218 DELAY(1);
219 v = CSR_READ_4(sc, AGE_MDIO);
220 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
221 break;
222 }
223
224 if (i == 0) {
225 device_printf(sc->age_dev, "phy read timeout : %d\n", reg);
226 return (0);
227 }
228
229 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
230 }
231
232 /*
233 * Write a PHY register on the MII of the L1.
234 */
235 static int
age_miibus_writereg(device_t dev,int phy,int reg,int val)236 age_miibus_writereg(device_t dev, int phy, int reg, int val)
237 {
238 struct age_softc *sc;
239 uint32_t v;
240 int i;
241
242 sc = device_get_softc(dev);
243
244 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
245 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
246 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
247 for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
248 DELAY(1);
249 v = CSR_READ_4(sc, AGE_MDIO);
250 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
251 break;
252 }
253
254 if (i == 0)
255 device_printf(sc->age_dev, "phy write timeout : %d\n", reg);
256
257 return (0);
258 }
259
260 /*
261 * Callback from MII layer when media changes.
262 */
263 static void
age_miibus_statchg(device_t dev)264 age_miibus_statchg(device_t dev)
265 {
266 struct age_softc *sc;
267
268 sc = device_get_softc(dev);
269 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task);
270 }
271
272 /*
273 * Get the current interface media status.
274 */
275 static void
age_mediastatus(if_t ifp,struct ifmediareq * ifmr)276 age_mediastatus(if_t ifp, struct ifmediareq *ifmr)
277 {
278 struct age_softc *sc;
279 struct mii_data *mii;
280
281 sc = if_getsoftc(ifp);
282 AGE_LOCK(sc);
283 mii = device_get_softc(sc->age_miibus);
284
285 mii_pollstat(mii);
286 ifmr->ifm_status = mii->mii_media_status;
287 ifmr->ifm_active = mii->mii_media_active;
288 AGE_UNLOCK(sc);
289 }
290
291 /*
292 * Set hardware to newly-selected media.
293 */
294 static int
age_mediachange(if_t ifp)295 age_mediachange(if_t ifp)
296 {
297 struct age_softc *sc;
298 struct mii_data *mii;
299 struct mii_softc *miisc;
300 int error;
301
302 sc = if_getsoftc(ifp);
303 AGE_LOCK(sc);
304 mii = device_get_softc(sc->age_miibus);
305 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
306 PHY_RESET(miisc);
307 error = mii_mediachg(mii);
308 AGE_UNLOCK(sc);
309
310 return (error);
311 }
312
313 static int
age_probe(device_t dev)314 age_probe(device_t dev)
315 {
316 struct age_dev *sp;
317 int i;
318 uint16_t vendor, devid;
319
320 vendor = pci_get_vendor(dev);
321 devid = pci_get_device(dev);
322 sp = age_devs;
323 for (i = 0; i < nitems(age_devs); i++, sp++) {
324 if (vendor == sp->age_vendorid &&
325 devid == sp->age_deviceid) {
326 device_set_desc(dev, sp->age_name);
327 return (BUS_PROBE_DEFAULT);
328 }
329 }
330
331 return (ENXIO);
332 }
333
334 static void
age_get_macaddr(struct age_softc * sc)335 age_get_macaddr(struct age_softc *sc)
336 {
337 uint32_t ea[2], reg;
338 int i, vpdc;
339
340 reg = CSR_READ_4(sc, AGE_SPI_CTRL);
341 if ((reg & SPI_VPD_ENB) != 0) {
342 /* Get VPD stored in TWSI EEPROM. */
343 reg &= ~SPI_VPD_ENB;
344 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
345 }
346
347 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) {
348 /*
349 * PCI VPD capability found, let TWSI reload EEPROM.
350 * This will set ethernet address of controller.
351 */
352 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
353 TWSI_CTRL_SW_LD_START);
354 for (i = 100; i > 0; i--) {
355 DELAY(1000);
356 reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
357 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
358 break;
359 }
360 if (i == 0)
361 device_printf(sc->age_dev,
362 "reloading EEPROM timeout!\n");
363 } else {
364 if (bootverbose)
365 device_printf(sc->age_dev,
366 "PCI VPD capability not found!\n");
367 }
368
369 ea[0] = CSR_READ_4(sc, AGE_PAR0);
370 ea[1] = CSR_READ_4(sc, AGE_PAR1);
371 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF;
372 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF;
373 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF;
374 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF;
375 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF;
376 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF;
377 }
378
379 static void
age_phy_reset(struct age_softc * sc)380 age_phy_reset(struct age_softc *sc)
381 {
382 uint16_t reg, pn;
383 int i, linkup;
384
385 /* Reset PHY. */
386 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
387 DELAY(2000);
388 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR);
389 DELAY(2000);
390
391 #define ATPHY_DBG_ADDR 0x1D
392 #define ATPHY_DBG_DATA 0x1E
393 #define ATPHY_CDTC 0x16
394 #define PHY_CDTC_ENB 0x0001
395 #define PHY_CDTC_POFF 8
396 #define ATPHY_CDTS 0x1C
397 #define PHY_CDTS_STAT_OK 0x0000
398 #define PHY_CDTS_STAT_SHORT 0x0100
399 #define PHY_CDTS_STAT_OPEN 0x0200
400 #define PHY_CDTS_STAT_INVAL 0x0300
401 #define PHY_CDTS_STAT_MASK 0x0300
402
403 /* Check power saving mode. Magic from Linux. */
404 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET);
405 for (linkup = 0, pn = 0; pn < 4; pn++) {
406 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC,
407 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB);
408 for (i = 200; i > 0; i--) {
409 DELAY(1000);
410 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
411 ATPHY_CDTC);
412 if ((reg & PHY_CDTC_ENB) == 0)
413 break;
414 }
415 DELAY(1000);
416 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
417 ATPHY_CDTS);
418 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) {
419 linkup++;
420 break;
421 }
422 }
423 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR,
424 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
425 if (linkup == 0) {
426 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
427 ATPHY_DBG_ADDR, 0);
428 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
429 ATPHY_DBG_DATA, 0x124E);
430 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
431 ATPHY_DBG_ADDR, 1);
432 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
433 ATPHY_DBG_DATA);
434 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
435 ATPHY_DBG_DATA, reg | 0x03);
436 /* XXX */
437 DELAY(1500 * 1000);
438 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
439 ATPHY_DBG_ADDR, 0);
440 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
441 ATPHY_DBG_DATA, 0x024E);
442 }
443
444 #undef ATPHY_DBG_ADDR
445 #undef ATPHY_DBG_DATA
446 #undef ATPHY_CDTC
447 #undef PHY_CDTC_ENB
448 #undef PHY_CDTC_POFF
449 #undef ATPHY_CDTS
450 #undef PHY_CDTS_STAT_OK
451 #undef PHY_CDTS_STAT_SHORT
452 #undef PHY_CDTS_STAT_OPEN
453 #undef PHY_CDTS_STAT_INVAL
454 #undef PHY_CDTS_STAT_MASK
455 }
456
457 static int
age_attach(device_t dev)458 age_attach(device_t dev)
459 {
460 struct age_softc *sc;
461 if_t ifp;
462 uint16_t burst;
463 int error, i, msic, msixc, pmc;
464
465 error = 0;
466 sc = device_get_softc(dev);
467 sc->age_dev = dev;
468
469 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
470 MTX_DEF);
471 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0);
472 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc);
473 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc);
474
475 /* Map the device. */
476 pci_enable_busmaster(dev);
477 sc->age_res_spec = age_res_spec_mem;
478 sc->age_irq_spec = age_irq_spec_legacy;
479 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res);
480 if (error != 0) {
481 device_printf(dev, "cannot allocate memory resources.\n");
482 goto fail;
483 }
484
485 /* Set PHY address. */
486 sc->age_phyaddr = AGE_PHY_ADDR;
487
488 /* Reset PHY. */
489 age_phy_reset(sc);
490
491 /* Reset the ethernet controller. */
492 age_reset(sc);
493
494 /* Get PCI and chip id/revision. */
495 sc->age_rev = pci_get_revid(dev);
496 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
497 MASTER_CHIP_REV_SHIFT;
498 if (bootverbose) {
499 device_printf(dev, "PCI device revision : 0x%04x\n",
500 sc->age_rev);
501 device_printf(dev, "Chip id/revision : 0x%04x\n",
502 sc->age_chip_rev);
503 }
504
505 /*
506 * XXX
507 * Unintialized hardware returns an invalid chip id/revision
508 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that
509 * unplugged cable results in putting hardware into automatic
510 * power down mode which in turn returns invalld chip revision.
511 */
512 if (sc->age_chip_rev == 0xFFFF) {
513 device_printf(dev,"invalid chip revision : 0x%04x -- "
514 "not initialized?\n", sc->age_chip_rev);
515 error = ENXIO;
516 goto fail;
517 }
518
519 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n",
520 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
521 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));
522
523 /* Allocate IRQ resources. */
524 msixc = pci_msix_count(dev);
525 msic = pci_msi_count(dev);
526 if (bootverbose) {
527 device_printf(dev, "MSIX count : %d\n", msixc);
528 device_printf(dev, "MSI count : %d\n", msic);
529 }
530
531 /* Prefer MSIX over MSI. */
532 if (msix_disable == 0 || msi_disable == 0) {
533 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES &&
534 pci_alloc_msix(dev, &msixc) == 0) {
535 if (msic == AGE_MSIX_MESSAGES) {
536 device_printf(dev, "Using %d MSIX messages.\n",
537 msixc);
538 sc->age_flags |= AGE_FLAG_MSIX;
539 sc->age_irq_spec = age_irq_spec_msix;
540 } else
541 pci_release_msi(dev);
542 }
543 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 &&
544 msic == AGE_MSI_MESSAGES &&
545 pci_alloc_msi(dev, &msic) == 0) {
546 if (msic == AGE_MSI_MESSAGES) {
547 device_printf(dev, "Using %d MSI messages.\n",
548 msic);
549 sc->age_flags |= AGE_FLAG_MSI;
550 sc->age_irq_spec = age_irq_spec_msi;
551 } else
552 pci_release_msi(dev);
553 }
554 }
555
556 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq);
557 if (error != 0) {
558 device_printf(dev, "cannot allocate IRQ resources.\n");
559 goto fail;
560 }
561
562 /* Get DMA parameters from PCIe device control register. */
563 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
564 sc->age_flags |= AGE_FLAG_PCIE;
565 burst = pci_read_config(dev, i + 0x08, 2);
566 /* Max read request size. */
567 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) <<
568 DMA_CFG_RD_BURST_SHIFT;
569 /* Max payload size. */
570 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) <<
571 DMA_CFG_WR_BURST_SHIFT;
572 if (bootverbose) {
573 device_printf(dev, "Read request size : %d bytes.\n",
574 128 << ((burst >> 12) & 0x07));
575 device_printf(dev, "TLP payload size : %d bytes.\n",
576 128 << ((burst >> 5) & 0x07));
577 }
578 } else {
579 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128;
580 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128;
581 }
582
583 /* Create device sysctl node. */
584 age_sysctl_node(sc);
585
586 if ((error = age_dma_alloc(sc)) != 0)
587 goto fail;
588
589 /* Load station address. */
590 age_get_macaddr(sc);
591
592 ifp = sc->age_ifp = if_alloc(IFT_ETHER);
593 if_setsoftc(ifp, sc);
594 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
595 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
596 if_setioctlfn(ifp, age_ioctl);
597 if_setstartfn(ifp, age_start);
598 if_setinitfn(ifp, age_init);
599 if_setsendqlen(ifp, AGE_TX_RING_CNT - 1);
600 if_setsendqready(ifp);
601 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4);
602 if_sethwassist(ifp, AGE_CSUM_FEATURES | CSUM_TSO);
603 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
604 sc->age_flags |= AGE_FLAG_PMCAP;
605 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0);
606 }
607 if_setcapenable(ifp, if_getcapabilities(ifp));
608
609 /* Set up MII bus. */
610 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange,
611 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY,
612 0);
613 if (error != 0) {
614 device_printf(dev, "attaching PHYs failed\n");
615 goto fail;
616 }
617
618 ether_ifattach(ifp, sc->age_eaddr);
619
620 /* VLAN capability setup. */
621 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
622 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
623 if_setcapenable(ifp, if_getcapabilities(ifp));
624
625 /* Tell the upper layer(s) we support long frames. */
626 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
627
628 /* Create local taskq. */
629 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK,
630 taskqueue_thread_enqueue, &sc->age_tq);
631 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq",
632 device_get_nameunit(sc->age_dev));
633
634 if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
635 msic = AGE_MSIX_MESSAGES;
636 else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
637 msic = AGE_MSI_MESSAGES;
638 else
639 msic = 1;
640 for (i = 0; i < msic; i++) {
641 error = bus_setup_intr(dev, sc->age_irq[i],
642 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc,
643 &sc->age_intrhand[i]);
644 if (error != 0)
645 break;
646 }
647 if (error != 0) {
648 device_printf(dev, "could not set up interrupt handler.\n");
649 taskqueue_free(sc->age_tq);
650 sc->age_tq = NULL;
651 ether_ifdetach(ifp);
652 goto fail;
653 }
654
655 fail:
656 if (error != 0)
657 age_detach(dev);
658
659 return (error);
660 }
661
662 static int
age_detach(device_t dev)663 age_detach(device_t dev)
664 {
665 struct age_softc *sc;
666 if_t ifp;
667 int i, msic;
668
669 sc = device_get_softc(dev);
670
671 ifp = sc->age_ifp;
672 if (device_is_attached(dev)) {
673 AGE_LOCK(sc);
674 sc->age_flags |= AGE_FLAG_DETACH;
675 age_stop(sc);
676 AGE_UNLOCK(sc);
677 callout_drain(&sc->age_tick_ch);
678 taskqueue_drain(sc->age_tq, &sc->age_int_task);
679 taskqueue_drain(taskqueue_swi, &sc->age_link_task);
680 ether_ifdetach(ifp);
681 }
682
683 if (sc->age_tq != NULL) {
684 taskqueue_drain(sc->age_tq, &sc->age_int_task);
685 taskqueue_free(sc->age_tq);
686 sc->age_tq = NULL;
687 }
688
689 bus_generic_detach(dev);
690 age_dma_free(sc);
691
692 if (ifp != NULL) {
693 if_free(ifp);
694 sc->age_ifp = NULL;
695 }
696
697 if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
698 msic = AGE_MSIX_MESSAGES;
699 else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
700 msic = AGE_MSI_MESSAGES;
701 else
702 msic = 1;
703 for (i = 0; i < msic; i++) {
704 if (sc->age_intrhand[i] != NULL) {
705 bus_teardown_intr(dev, sc->age_irq[i],
706 sc->age_intrhand[i]);
707 sc->age_intrhand[i] = NULL;
708 }
709 }
710
711 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq);
712 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0)
713 pci_release_msi(dev);
714 bus_release_resources(dev, sc->age_res_spec, sc->age_res);
715 mtx_destroy(&sc->age_mtx);
716
717 return (0);
718 }
719
720 static void
age_sysctl_node(struct age_softc * sc)721 age_sysctl_node(struct age_softc *sc)
722 {
723 int error;
724
725 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
726 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
727 "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
728 sc, 0, sysctl_age_stats, "I", "Statistics");
729
730 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
731 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
732 "int_mod", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
733 &sc->age_int_mod, 0, sysctl_hw_age_int_mod, "I",
734 "age interrupt moderation");
735
736 /* Pull in device tunables. */
737 sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
738 error = resource_int_value(device_get_name(sc->age_dev),
739 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod);
740 if (error == 0) {
741 if (sc->age_int_mod < AGE_IM_TIMER_MIN ||
742 sc->age_int_mod > AGE_IM_TIMER_MAX) {
743 device_printf(sc->age_dev,
744 "int_mod value out of range; using default: %d\n",
745 AGE_IM_TIMER_DEFAULT);
746 sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
747 }
748 }
749
750 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
751 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
752 "process_limit", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
753 &sc->age_process_limit, 0, sysctl_hw_age_proc_limit, "I",
754 "max number of Rx events to process");
755
756 /* Pull in device tunables. */
757 sc->age_process_limit = AGE_PROC_DEFAULT;
758 error = resource_int_value(device_get_name(sc->age_dev),
759 device_get_unit(sc->age_dev), "process_limit",
760 &sc->age_process_limit);
761 if (error == 0) {
762 if (sc->age_process_limit < AGE_PROC_MIN ||
763 sc->age_process_limit > AGE_PROC_MAX) {
764 device_printf(sc->age_dev,
765 "process_limit value out of range; "
766 "using default: %d\n", AGE_PROC_DEFAULT);
767 sc->age_process_limit = AGE_PROC_DEFAULT;
768 }
769 }
770 }
771
772 struct age_dmamap_arg {
773 bus_addr_t age_busaddr;
774 };
775
776 static void
age_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)777 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
778 {
779 struct age_dmamap_arg *ctx;
780
781 if (error != 0)
782 return;
783
784 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
785
786 ctx = (struct age_dmamap_arg *)arg;
787 ctx->age_busaddr = segs[0].ds_addr;
788 }
789
790 /*
791 * Attansic L1 controller have single register to specify high
792 * address part of DMA blocks. So all descriptor structures and
793 * DMA memory blocks should have the same high address of given
794 * 4GB address space(i.e. crossing 4GB boundary is not allowed).
795 */
796 static int
age_check_boundary(struct age_softc * sc)797 age_check_boundary(struct age_softc *sc)
798 {
799 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end;
800 bus_addr_t cmb_block_end, smb_block_end;
801
802 /* Tx/Rx descriptor queue should reside within 4GB boundary. */
803 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ;
804 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ;
805 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ;
806 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ;
807 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ;
808
809 if ((AGE_ADDR_HI(tx_ring_end) !=
810 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) ||
811 (AGE_ADDR_HI(rx_ring_end) !=
812 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) ||
813 (AGE_ADDR_HI(rr_ring_end) !=
814 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) ||
815 (AGE_ADDR_HI(cmb_block_end) !=
816 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) ||
817 (AGE_ADDR_HI(smb_block_end) !=
818 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr)))
819 return (EFBIG);
820
821 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) ||
822 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) ||
823 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) ||
824 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end)))
825 return (EFBIG);
826
827 return (0);
828 }
829
830 static int
age_dma_alloc(struct age_softc * sc)831 age_dma_alloc(struct age_softc *sc)
832 {
833 struct age_txdesc *txd;
834 struct age_rxdesc *rxd;
835 bus_addr_t lowaddr;
836 struct age_dmamap_arg ctx;
837 int error, i;
838
839 lowaddr = BUS_SPACE_MAXADDR;
840
841 again:
842 /* Create parent ring/DMA block tag. */
843 error = bus_dma_tag_create(
844 bus_get_dma_tag(sc->age_dev), /* parent */
845 1, 0, /* alignment, boundary */
846 lowaddr, /* lowaddr */
847 BUS_SPACE_MAXADDR, /* highaddr */
848 NULL, NULL, /* filter, filterarg */
849 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
850 0, /* nsegments */
851 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
852 0, /* flags */
853 NULL, NULL, /* lockfunc, lockarg */
854 &sc->age_cdata.age_parent_tag);
855 if (error != 0) {
856 device_printf(sc->age_dev,
857 "could not create parent DMA tag.\n");
858 goto fail;
859 }
860
861 /* Create tag for Tx ring. */
862 error = bus_dma_tag_create(
863 sc->age_cdata.age_parent_tag, /* parent */
864 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */
865 BUS_SPACE_MAXADDR, /* lowaddr */
866 BUS_SPACE_MAXADDR, /* highaddr */
867 NULL, NULL, /* filter, filterarg */
868 AGE_TX_RING_SZ, /* maxsize */
869 1, /* nsegments */
870 AGE_TX_RING_SZ, /* maxsegsize */
871 0, /* flags */
872 NULL, NULL, /* lockfunc, lockarg */
873 &sc->age_cdata.age_tx_ring_tag);
874 if (error != 0) {
875 device_printf(sc->age_dev,
876 "could not create Tx ring DMA tag.\n");
877 goto fail;
878 }
879
880 /* Create tag for Rx ring. */
881 error = bus_dma_tag_create(
882 sc->age_cdata.age_parent_tag, /* parent */
883 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */
884 BUS_SPACE_MAXADDR, /* lowaddr */
885 BUS_SPACE_MAXADDR, /* highaddr */
886 NULL, NULL, /* filter, filterarg */
887 AGE_RX_RING_SZ, /* maxsize */
888 1, /* nsegments */
889 AGE_RX_RING_SZ, /* maxsegsize */
890 0, /* flags */
891 NULL, NULL, /* lockfunc, lockarg */
892 &sc->age_cdata.age_rx_ring_tag);
893 if (error != 0) {
894 device_printf(sc->age_dev,
895 "could not create Rx ring DMA tag.\n");
896 goto fail;
897 }
898
899 /* Create tag for Rx return ring. */
900 error = bus_dma_tag_create(
901 sc->age_cdata.age_parent_tag, /* parent */
902 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */
903 BUS_SPACE_MAXADDR, /* lowaddr */
904 BUS_SPACE_MAXADDR, /* highaddr */
905 NULL, NULL, /* filter, filterarg */
906 AGE_RR_RING_SZ, /* maxsize */
907 1, /* nsegments */
908 AGE_RR_RING_SZ, /* maxsegsize */
909 0, /* flags */
910 NULL, NULL, /* lockfunc, lockarg */
911 &sc->age_cdata.age_rr_ring_tag);
912 if (error != 0) {
913 device_printf(sc->age_dev,
914 "could not create Rx return ring DMA tag.\n");
915 goto fail;
916 }
917
918 /* Create tag for coalesing message block. */
919 error = bus_dma_tag_create(
920 sc->age_cdata.age_parent_tag, /* parent */
921 AGE_CMB_ALIGN, 0, /* alignment, boundary */
922 BUS_SPACE_MAXADDR, /* lowaddr */
923 BUS_SPACE_MAXADDR, /* highaddr */
924 NULL, NULL, /* filter, filterarg */
925 AGE_CMB_BLOCK_SZ, /* maxsize */
926 1, /* nsegments */
927 AGE_CMB_BLOCK_SZ, /* maxsegsize */
928 0, /* flags */
929 NULL, NULL, /* lockfunc, lockarg */
930 &sc->age_cdata.age_cmb_block_tag);
931 if (error != 0) {
932 device_printf(sc->age_dev,
933 "could not create CMB DMA tag.\n");
934 goto fail;
935 }
936
937 /* Create tag for statistics message block. */
938 error = bus_dma_tag_create(
939 sc->age_cdata.age_parent_tag, /* parent */
940 AGE_SMB_ALIGN, 0, /* alignment, boundary */
941 BUS_SPACE_MAXADDR, /* lowaddr */
942 BUS_SPACE_MAXADDR, /* highaddr */
943 NULL, NULL, /* filter, filterarg */
944 AGE_SMB_BLOCK_SZ, /* maxsize */
945 1, /* nsegments */
946 AGE_SMB_BLOCK_SZ, /* maxsegsize */
947 0, /* flags */
948 NULL, NULL, /* lockfunc, lockarg */
949 &sc->age_cdata.age_smb_block_tag);
950 if (error != 0) {
951 device_printf(sc->age_dev,
952 "could not create SMB DMA tag.\n");
953 goto fail;
954 }
955
956 /* Allocate DMA'able memory and load the DMA map. */
957 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag,
958 (void **)&sc->age_rdata.age_tx_ring,
959 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
960 &sc->age_cdata.age_tx_ring_map);
961 if (error != 0) {
962 device_printf(sc->age_dev,
963 "could not allocate DMA'able memory for Tx ring.\n");
964 goto fail;
965 }
966 ctx.age_busaddr = 0;
967 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag,
968 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring,
969 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0);
970 if (error != 0 || ctx.age_busaddr == 0) {
971 device_printf(sc->age_dev,
972 "could not load DMA'able memory for Tx ring.\n");
973 goto fail;
974 }
975 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr;
976 /* Rx ring */
977 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag,
978 (void **)&sc->age_rdata.age_rx_ring,
979 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
980 &sc->age_cdata.age_rx_ring_map);
981 if (error != 0) {
982 device_printf(sc->age_dev,
983 "could not allocate DMA'able memory for Rx ring.\n");
984 goto fail;
985 }
986 ctx.age_busaddr = 0;
987 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag,
988 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring,
989 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0);
990 if (error != 0 || ctx.age_busaddr == 0) {
991 device_printf(sc->age_dev,
992 "could not load DMA'able memory for Rx ring.\n");
993 goto fail;
994 }
995 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr;
996 /* Rx return ring */
997 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag,
998 (void **)&sc->age_rdata.age_rr_ring,
999 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1000 &sc->age_cdata.age_rr_ring_map);
1001 if (error != 0) {
1002 device_printf(sc->age_dev,
1003 "could not allocate DMA'able memory for Rx return ring.\n");
1004 goto fail;
1005 }
1006 ctx.age_busaddr = 0;
1007 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag,
1008 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring,
1009 AGE_RR_RING_SZ, age_dmamap_cb,
1010 &ctx, 0);
1011 if (error != 0 || ctx.age_busaddr == 0) {
1012 device_printf(sc->age_dev,
1013 "could not load DMA'able memory for Rx return ring.\n");
1014 goto fail;
1015 }
1016 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr;
1017 /* CMB block */
1018 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag,
1019 (void **)&sc->age_rdata.age_cmb_block,
1020 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1021 &sc->age_cdata.age_cmb_block_map);
1022 if (error != 0) {
1023 device_printf(sc->age_dev,
1024 "could not allocate DMA'able memory for CMB block.\n");
1025 goto fail;
1026 }
1027 ctx.age_busaddr = 0;
1028 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag,
1029 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block,
1030 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1031 if (error != 0 || ctx.age_busaddr == 0) {
1032 device_printf(sc->age_dev,
1033 "could not load DMA'able memory for CMB block.\n");
1034 goto fail;
1035 }
1036 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr;
1037 /* SMB block */
1038 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag,
1039 (void **)&sc->age_rdata.age_smb_block,
1040 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1041 &sc->age_cdata.age_smb_block_map);
1042 if (error != 0) {
1043 device_printf(sc->age_dev,
1044 "could not allocate DMA'able memory for SMB block.\n");
1045 goto fail;
1046 }
1047 ctx.age_busaddr = 0;
1048 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag,
1049 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block,
1050 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1051 if (error != 0 || ctx.age_busaddr == 0) {
1052 device_printf(sc->age_dev,
1053 "could not load DMA'able memory for SMB block.\n");
1054 goto fail;
1055 }
1056 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr;
1057
1058 /*
1059 * All ring buffer and DMA blocks should have the same
1060 * high address part of 64bit DMA address space.
1061 */
1062 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1063 (error = age_check_boundary(sc)) != 0) {
1064 device_printf(sc->age_dev, "4GB boundary crossed, "
1065 "switching to 32bit DMA addressing mode.\n");
1066 age_dma_free(sc);
1067 /* Limit DMA address space to 32bit and try again. */
1068 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1069 goto again;
1070 }
1071
1072 /*
1073 * Create Tx/Rx buffer parent tag.
1074 * L1 supports full 64bit DMA addressing in Tx/Rx buffers
1075 * so it needs separate parent DMA tag.
1076 * XXX
1077 * It seems enabling 64bit DMA causes data corruption. Limit
1078 * DMA address space to 32bit.
1079 */
1080 error = bus_dma_tag_create(
1081 bus_get_dma_tag(sc->age_dev), /* parent */
1082 1, 0, /* alignment, boundary */
1083 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1084 BUS_SPACE_MAXADDR, /* highaddr */
1085 NULL, NULL, /* filter, filterarg */
1086 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1087 0, /* nsegments */
1088 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1089 0, /* flags */
1090 NULL, NULL, /* lockfunc, lockarg */
1091 &sc->age_cdata.age_buffer_tag);
1092 if (error != 0) {
1093 device_printf(sc->age_dev,
1094 "could not create parent buffer DMA tag.\n");
1095 goto fail;
1096 }
1097
1098 /* Create tag for Tx buffers. */
1099 error = bus_dma_tag_create(
1100 sc->age_cdata.age_buffer_tag, /* parent */
1101 1, 0, /* alignment, boundary */
1102 BUS_SPACE_MAXADDR, /* lowaddr */
1103 BUS_SPACE_MAXADDR, /* highaddr */
1104 NULL, NULL, /* filter, filterarg */
1105 AGE_TSO_MAXSIZE, /* maxsize */
1106 AGE_MAXTXSEGS, /* nsegments */
1107 AGE_TSO_MAXSEGSIZE, /* maxsegsize */
1108 0, /* flags */
1109 NULL, NULL, /* lockfunc, lockarg */
1110 &sc->age_cdata.age_tx_tag);
1111 if (error != 0) {
1112 device_printf(sc->age_dev, "could not create Tx DMA tag.\n");
1113 goto fail;
1114 }
1115
1116 /* Create tag for Rx buffers. */
1117 error = bus_dma_tag_create(
1118 sc->age_cdata.age_buffer_tag, /* parent */
1119 AGE_RX_BUF_ALIGN, 0, /* alignment, boundary */
1120 BUS_SPACE_MAXADDR, /* lowaddr */
1121 BUS_SPACE_MAXADDR, /* highaddr */
1122 NULL, NULL, /* filter, filterarg */
1123 MCLBYTES, /* maxsize */
1124 1, /* nsegments */
1125 MCLBYTES, /* maxsegsize */
1126 0, /* flags */
1127 NULL, NULL, /* lockfunc, lockarg */
1128 &sc->age_cdata.age_rx_tag);
1129 if (error != 0) {
1130 device_printf(sc->age_dev, "could not create Rx DMA tag.\n");
1131 goto fail;
1132 }
1133
1134 /* Create DMA maps for Tx buffers. */
1135 for (i = 0; i < AGE_TX_RING_CNT; i++) {
1136 txd = &sc->age_cdata.age_txdesc[i];
1137 txd->tx_m = NULL;
1138 txd->tx_dmamap = NULL;
1139 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0,
1140 &txd->tx_dmamap);
1141 if (error != 0) {
1142 device_printf(sc->age_dev,
1143 "could not create Tx dmamap.\n");
1144 goto fail;
1145 }
1146 }
1147 /* Create DMA maps for Rx buffers. */
1148 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1149 &sc->age_cdata.age_rx_sparemap)) != 0) {
1150 device_printf(sc->age_dev,
1151 "could not create spare Rx dmamap.\n");
1152 goto fail;
1153 }
1154 for (i = 0; i < AGE_RX_RING_CNT; i++) {
1155 rxd = &sc->age_cdata.age_rxdesc[i];
1156 rxd->rx_m = NULL;
1157 rxd->rx_dmamap = NULL;
1158 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1159 &rxd->rx_dmamap);
1160 if (error != 0) {
1161 device_printf(sc->age_dev,
1162 "could not create Rx dmamap.\n");
1163 goto fail;
1164 }
1165 }
1166
1167 fail:
1168 return (error);
1169 }
1170
1171 static void
age_dma_free(struct age_softc * sc)1172 age_dma_free(struct age_softc *sc)
1173 {
1174 struct age_txdesc *txd;
1175 struct age_rxdesc *rxd;
1176 int i;
1177
1178 /* Tx buffers */
1179 if (sc->age_cdata.age_tx_tag != NULL) {
1180 for (i = 0; i < AGE_TX_RING_CNT; i++) {
1181 txd = &sc->age_cdata.age_txdesc[i];
1182 if (txd->tx_dmamap != NULL) {
1183 bus_dmamap_destroy(sc->age_cdata.age_tx_tag,
1184 txd->tx_dmamap);
1185 txd->tx_dmamap = NULL;
1186 }
1187 }
1188 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag);
1189 sc->age_cdata.age_tx_tag = NULL;
1190 }
1191 /* Rx buffers */
1192 if (sc->age_cdata.age_rx_tag != NULL) {
1193 for (i = 0; i < AGE_RX_RING_CNT; i++) {
1194 rxd = &sc->age_cdata.age_rxdesc[i];
1195 if (rxd->rx_dmamap != NULL) {
1196 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1197 rxd->rx_dmamap);
1198 rxd->rx_dmamap = NULL;
1199 }
1200 }
1201 if (sc->age_cdata.age_rx_sparemap != NULL) {
1202 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1203 sc->age_cdata.age_rx_sparemap);
1204 sc->age_cdata.age_rx_sparemap = NULL;
1205 }
1206 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag);
1207 sc->age_cdata.age_rx_tag = NULL;
1208 }
1209 /* Tx ring. */
1210 if (sc->age_cdata.age_tx_ring_tag != NULL) {
1211 if (sc->age_rdata.age_tx_ring_paddr != 0)
1212 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag,
1213 sc->age_cdata.age_tx_ring_map);
1214 if (sc->age_rdata.age_tx_ring != NULL)
1215 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag,
1216 sc->age_rdata.age_tx_ring,
1217 sc->age_cdata.age_tx_ring_map);
1218 sc->age_rdata.age_tx_ring_paddr = 0;
1219 sc->age_rdata.age_tx_ring = NULL;
1220 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag);
1221 sc->age_cdata.age_tx_ring_tag = NULL;
1222 }
1223 /* Rx ring. */
1224 if (sc->age_cdata.age_rx_ring_tag != NULL) {
1225 if (sc->age_rdata.age_rx_ring_paddr != 0)
1226 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag,
1227 sc->age_cdata.age_rx_ring_map);
1228 if (sc->age_rdata.age_rx_ring != NULL)
1229 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag,
1230 sc->age_rdata.age_rx_ring,
1231 sc->age_cdata.age_rx_ring_map);
1232 sc->age_rdata.age_rx_ring_paddr = 0;
1233 sc->age_rdata.age_rx_ring = NULL;
1234 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag);
1235 sc->age_cdata.age_rx_ring_tag = NULL;
1236 }
1237 /* Rx return ring. */
1238 if (sc->age_cdata.age_rr_ring_tag != NULL) {
1239 if (sc->age_rdata.age_rr_ring_paddr != 0)
1240 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag,
1241 sc->age_cdata.age_rr_ring_map);
1242 if (sc->age_rdata.age_rr_ring != NULL)
1243 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag,
1244 sc->age_rdata.age_rr_ring,
1245 sc->age_cdata.age_rr_ring_map);
1246 sc->age_rdata.age_rr_ring_paddr = 0;
1247 sc->age_rdata.age_rr_ring = NULL;
1248 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag);
1249 sc->age_cdata.age_rr_ring_tag = NULL;
1250 }
1251 /* CMB block */
1252 if (sc->age_cdata.age_cmb_block_tag != NULL) {
1253 if (sc->age_rdata.age_cmb_block_paddr != 0)
1254 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag,
1255 sc->age_cdata.age_cmb_block_map);
1256 if (sc->age_rdata.age_cmb_block != NULL)
1257 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag,
1258 sc->age_rdata.age_cmb_block,
1259 sc->age_cdata.age_cmb_block_map);
1260 sc->age_rdata.age_cmb_block_paddr = 0;
1261 sc->age_rdata.age_cmb_block = NULL;
1262 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag);
1263 sc->age_cdata.age_cmb_block_tag = NULL;
1264 }
1265 /* SMB block */
1266 if (sc->age_cdata.age_smb_block_tag != NULL) {
1267 if (sc->age_rdata.age_smb_block_paddr != 0)
1268 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag,
1269 sc->age_cdata.age_smb_block_map);
1270 if (sc->age_rdata.age_smb_block != NULL)
1271 bus_dmamem_free(sc->age_cdata.age_smb_block_tag,
1272 sc->age_rdata.age_smb_block,
1273 sc->age_cdata.age_smb_block_map);
1274 sc->age_rdata.age_smb_block_paddr = 0;
1275 sc->age_rdata.age_smb_block = NULL;
1276 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag);
1277 sc->age_cdata.age_smb_block_tag = NULL;
1278 }
1279
1280 if (sc->age_cdata.age_buffer_tag != NULL) {
1281 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag);
1282 sc->age_cdata.age_buffer_tag = NULL;
1283 }
1284 if (sc->age_cdata.age_parent_tag != NULL) {
1285 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag);
1286 sc->age_cdata.age_parent_tag = NULL;
1287 }
1288 }
1289
1290 /*
1291 * Make sure the interface is stopped at reboot time.
1292 */
1293 static int
age_shutdown(device_t dev)1294 age_shutdown(device_t dev)
1295 {
1296
1297 return (age_suspend(dev));
1298 }
1299
1300 static void
age_setwol(struct age_softc * sc)1301 age_setwol(struct age_softc *sc)
1302 {
1303 if_t ifp;
1304 struct mii_data *mii;
1305 uint32_t reg, pmcs;
1306 uint16_t pmstat;
1307 int aneg, i, pmc;
1308
1309 AGE_LOCK_ASSERT(sc);
1310
1311 if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) {
1312 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
1313 /*
1314 * No PME capability, PHY power down.
1315 * XXX
1316 * Due to an unknown reason powering down PHY resulted
1317 * in unexpected results such as inaccessbility of
1318 * hardware of freshly rebooted system. Disable
1319 * powering down PHY until I got more information for
1320 * Attansic/Atheros PHY hardwares.
1321 */
1322 #ifdef notyet
1323 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1324 MII_BMCR, BMCR_PDOWN);
1325 #endif
1326 return;
1327 }
1328
1329 ifp = sc->age_ifp;
1330 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
1331 /*
1332 * Note, this driver resets the link speed to 10/100Mbps with
1333 * auto-negotiation but we don't know whether that operation
1334 * would succeed or not as it have no control after powering
1335 * off. If the renegotiation fail WOL may not work. Running
1336 * at 1Gbps will draw more power than 375mA at 3.3V which is
1337 * specified in PCI specification and that would result in
1338 * complete shutdowning power to ethernet controller.
1339 *
1340 * TODO
1341 * Save current negotiated media speed/duplex/flow-control
1342 * to softc and restore the same link again after resuming.
1343 * PHY handling such as power down/resetting to 100Mbps
1344 * may be better handled in suspend method in phy driver.
1345 */
1346 mii = device_get_softc(sc->age_miibus);
1347 mii_pollstat(mii);
1348 aneg = 0;
1349 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1350 switch IFM_SUBTYPE(mii->mii_media_active) {
1351 case IFM_10_T:
1352 case IFM_100_TX:
1353 goto got_link;
1354 case IFM_1000_T:
1355 aneg++;
1356 default:
1357 break;
1358 }
1359 }
1360 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1361 MII_100T2CR, 0);
1362 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1363 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD |
1364 ANAR_10 | ANAR_CSMA);
1365 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1366 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1367 DELAY(1000);
1368 if (aneg != 0) {
1369 /* Poll link state until age(4) get a 10/100 link. */
1370 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1371 mii_pollstat(mii);
1372 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1373 switch (IFM_SUBTYPE(
1374 mii->mii_media_active)) {
1375 case IFM_10_T:
1376 case IFM_100_TX:
1377 age_mac_config(sc);
1378 goto got_link;
1379 default:
1380 break;
1381 }
1382 }
1383 AGE_UNLOCK(sc);
1384 pause("agelnk", hz);
1385 AGE_LOCK(sc);
1386 }
1387 if (i == MII_ANEGTICKS_GIGE)
1388 device_printf(sc->age_dev,
1389 "establishing link failed, "
1390 "WOL may not work!");
1391 }
1392 /*
1393 * No link, force MAC to have 100Mbps, full-duplex link.
1394 * This is the last resort and may/may not work.
1395 */
1396 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1397 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1398 age_mac_config(sc);
1399 }
1400
1401 got_link:
1402 pmcs = 0;
1403 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
1404 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1405 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs);
1406 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1407 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC);
1408 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST);
1409 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0)
1410 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1411 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
1412 reg |= MAC_CFG_RX_ENB;
1413 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1414 }
1415
1416 /* Request PME. */
1417 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2);
1418 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1419 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
1420 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1421 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1422 #ifdef notyet
1423 /* See above for powering down PHY issues. */
1424 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) {
1425 /* No WOL, PHY power down. */
1426 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1427 MII_BMCR, BMCR_PDOWN);
1428 }
1429 #endif
1430 }
1431
1432 static int
age_suspend(device_t dev)1433 age_suspend(device_t dev)
1434 {
1435 struct age_softc *sc;
1436
1437 sc = device_get_softc(dev);
1438
1439 AGE_LOCK(sc);
1440 age_stop(sc);
1441 age_setwol(sc);
1442 AGE_UNLOCK(sc);
1443
1444 return (0);
1445 }
1446
1447 static int
age_resume(device_t dev)1448 age_resume(device_t dev)
1449 {
1450 struct age_softc *sc;
1451 if_t ifp;
1452
1453 sc = device_get_softc(dev);
1454
1455 AGE_LOCK(sc);
1456 age_phy_reset(sc);
1457 ifp = sc->age_ifp;
1458 if ((if_getflags(ifp) & IFF_UP) != 0)
1459 age_init_locked(sc);
1460
1461 AGE_UNLOCK(sc);
1462
1463 return (0);
1464 }
1465
1466 static int
age_encap(struct age_softc * sc,struct mbuf ** m_head)1467 age_encap(struct age_softc *sc, struct mbuf **m_head)
1468 {
1469 struct age_txdesc *txd, *txd_last;
1470 struct tx_desc *desc;
1471 struct mbuf *m;
1472 struct ip *ip;
1473 struct tcphdr *tcp;
1474 bus_dma_segment_t txsegs[AGE_MAXTXSEGS];
1475 bus_dmamap_t map;
1476 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1477 int error, i, nsegs, prod, si;
1478
1479 AGE_LOCK_ASSERT(sc);
1480
1481 M_ASSERTPKTHDR((*m_head));
1482
1483 m = *m_head;
1484 ip = NULL;
1485 tcp = NULL;
1486 cflags = vtag = 0;
1487 ip_off = poff = 0;
1488 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1489 /*
1490 * L1 requires offset of TCP/UDP payload in its Tx
1491 * descriptor to perform hardware Tx checksum offload.
1492 * Additionally, TSO requires IP/TCP header size and
1493 * modification of IP/TCP header in order to make TSO
1494 * engine work. This kind of operation takes many CPU
1495 * cycles on FreeBSD so fast host CPU is needed to get
1496 * smooth TSO performance.
1497 */
1498 struct ether_header *eh;
1499
1500 if (M_WRITABLE(m) == 0) {
1501 /* Get a writable copy. */
1502 m = m_dup(*m_head, M_NOWAIT);
1503 /* Release original mbufs. */
1504 m_freem(*m_head);
1505 if (m == NULL) {
1506 *m_head = NULL;
1507 return (ENOBUFS);
1508 }
1509 *m_head = m;
1510 }
1511 ip_off = sizeof(struct ether_header);
1512 m = m_pullup(m, ip_off);
1513 if (m == NULL) {
1514 *m_head = NULL;
1515 return (ENOBUFS);
1516 }
1517 eh = mtod(m, struct ether_header *);
1518 /*
1519 * Check if hardware VLAN insertion is off.
1520 * Additional check for LLC/SNAP frame?
1521 */
1522 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1523 ip_off = sizeof(struct ether_vlan_header);
1524 m = m_pullup(m, ip_off);
1525 if (m == NULL) {
1526 *m_head = NULL;
1527 return (ENOBUFS);
1528 }
1529 }
1530 m = m_pullup(m, ip_off + sizeof(struct ip));
1531 if (m == NULL) {
1532 *m_head = NULL;
1533 return (ENOBUFS);
1534 }
1535 ip = (struct ip *)(mtod(m, char *) + ip_off);
1536 poff = ip_off + (ip->ip_hl << 2);
1537 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1538 m = m_pullup(m, poff + sizeof(struct tcphdr));
1539 if (m == NULL) {
1540 *m_head = NULL;
1541 return (ENOBUFS);
1542 }
1543 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1544 m = m_pullup(m, poff + (tcp->th_off << 2));
1545 if (m == NULL) {
1546 *m_head = NULL;
1547 return (ENOBUFS);
1548 }
1549 /*
1550 * L1 requires IP/TCP header size and offset as
1551 * well as TCP pseudo checksum which complicates
1552 * TSO configuration. I guess this comes from the
1553 * adherence to Microsoft NDIS Large Send
1554 * specification which requires insertion of
1555 * pseudo checksum by upper stack. The pseudo
1556 * checksum that NDIS refers to doesn't include
1557 * TCP payload length so age(4) should recompute
1558 * the pseudo checksum here. Hopefully this wouldn't
1559 * be much burden on modern CPUs.
1560 * Reset IP checksum and recompute TCP pseudo
1561 * checksum as NDIS specification said.
1562 */
1563 ip = (struct ip *)(mtod(m, char *) + ip_off);
1564 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1565 ip->ip_sum = 0;
1566 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1567 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1568 }
1569 *m_head = m;
1570 }
1571
1572 si = prod = sc->age_cdata.age_tx_prod;
1573 txd = &sc->age_cdata.age_txdesc[prod];
1574 txd_last = txd;
1575 map = txd->tx_dmamap;
1576
1577 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1578 *m_head, txsegs, &nsegs, 0);
1579 if (error == EFBIG) {
1580 m = m_collapse(*m_head, M_NOWAIT, AGE_MAXTXSEGS);
1581 if (m == NULL) {
1582 m_freem(*m_head);
1583 *m_head = NULL;
1584 return (ENOMEM);
1585 }
1586 *m_head = m;
1587 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1588 *m_head, txsegs, &nsegs, 0);
1589 if (error != 0) {
1590 m_freem(*m_head);
1591 *m_head = NULL;
1592 return (error);
1593 }
1594 } else if (error != 0)
1595 return (error);
1596 if (nsegs == 0) {
1597 m_freem(*m_head);
1598 *m_head = NULL;
1599 return (EIO);
1600 }
1601
1602 /* Check descriptor overrun. */
1603 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) {
1604 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map);
1605 return (ENOBUFS);
1606 }
1607
1608 m = *m_head;
1609 /* Configure VLAN hardware tag insertion. */
1610 if ((m->m_flags & M_VLANTAG) != 0) {
1611 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1612 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK);
1613 cflags |= AGE_TD_INSERT_VLAN_TAG;
1614 }
1615
1616 desc = NULL;
1617 i = 0;
1618 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1619 /* Request TSO and set MSS. */
1620 cflags |= AGE_TD_TSO_IPV4;
1621 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM;
1622 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz <<
1623 AGE_TD_TSO_MSS_SHIFT);
1624 /* Set IP/TCP header size. */
1625 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT;
1626 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT;
1627 /*
1628 * L1 requires the first buffer should only hold IP/TCP
1629 * header data. TCP payload should be handled in other
1630 * descriptors.
1631 */
1632 hdrlen = poff + (tcp->th_off << 2);
1633 desc = &sc->age_rdata.age_tx_ring[prod];
1634 desc->addr = htole64(txsegs[0].ds_addr);
1635 desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag);
1636 desc->flags = htole32(cflags);
1637 sc->age_cdata.age_tx_cnt++;
1638 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1639 if (m->m_len - hdrlen > 0) {
1640 /* Handle remaining payload of the 1st fragment. */
1641 desc = &sc->age_rdata.age_tx_ring[prod];
1642 desc->addr = htole64(txsegs[0].ds_addr + hdrlen);
1643 desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) |
1644 vtag);
1645 desc->flags = htole32(cflags);
1646 sc->age_cdata.age_tx_cnt++;
1647 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1648 }
1649 /* Handle remaining fragments. */
1650 i = 1;
1651 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) {
1652 /* Configure Tx IP/TCP/UDP checksum offload. */
1653 cflags |= AGE_TD_CSUM;
1654 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1655 cflags |= AGE_TD_TCPCSUM;
1656 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1657 cflags |= AGE_TD_UDPCSUM;
1658 /* Set checksum start offset. */
1659 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT);
1660 /* Set checksum insertion position of TCP/UDP. */
1661 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1662 AGE_TD_CSUM_XSUMOFFSET_SHIFT);
1663 }
1664 for (; i < nsegs; i++) {
1665 desc = &sc->age_rdata.age_tx_ring[prod];
1666 desc->addr = htole64(txsegs[i].ds_addr);
1667 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag);
1668 desc->flags = htole32(cflags);
1669 sc->age_cdata.age_tx_cnt++;
1670 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1671 }
1672 /* Update producer index. */
1673 sc->age_cdata.age_tx_prod = prod;
1674
1675 /* Set EOP on the last descriptor. */
1676 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT;
1677 desc = &sc->age_rdata.age_tx_ring[prod];
1678 desc->flags |= htole32(AGE_TD_EOP);
1679
1680 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */
1681 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1682 desc = &sc->age_rdata.age_tx_ring[si];
1683 desc->flags |= htole32(AGE_TD_TSO_HDR);
1684 }
1685
1686 /* Swap dmamap of the first and the last. */
1687 txd = &sc->age_cdata.age_txdesc[prod];
1688 map = txd_last->tx_dmamap;
1689 txd_last->tx_dmamap = txd->tx_dmamap;
1690 txd->tx_dmamap = map;
1691 txd->tx_m = m;
1692
1693 /* Sync descriptors. */
1694 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE);
1695 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
1696 sc->age_cdata.age_tx_ring_map,
1697 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1698
1699 return (0);
1700 }
1701
1702 static void
age_start(if_t ifp)1703 age_start(if_t ifp)
1704 {
1705 struct age_softc *sc;
1706
1707 sc = if_getsoftc(ifp);
1708 AGE_LOCK(sc);
1709 age_start_locked(ifp);
1710 AGE_UNLOCK(sc);
1711 }
1712
1713 static void
age_start_locked(if_t ifp)1714 age_start_locked(if_t ifp)
1715 {
1716 struct age_softc *sc;
1717 struct mbuf *m_head;
1718 int enq;
1719
1720 sc = if_getsoftc(ifp);
1721
1722 AGE_LOCK_ASSERT(sc);
1723
1724 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1725 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0)
1726 return;
1727
1728 for (enq = 0; !if_sendq_empty(ifp); ) {
1729 m_head = if_dequeue(ifp);
1730 if (m_head == NULL)
1731 break;
1732 /*
1733 * Pack the data into the transmit ring. If we
1734 * don't have room, set the OACTIVE flag and wait
1735 * for the NIC to drain the ring.
1736 */
1737 if (age_encap(sc, &m_head)) {
1738 if (m_head == NULL)
1739 break;
1740 if_sendq_prepend(ifp, m_head);
1741 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1742 break;
1743 }
1744
1745 enq++;
1746 /*
1747 * If there's a BPF listener, bounce a copy of this frame
1748 * to him.
1749 */
1750 ETHER_BPF_MTAP(ifp, m_head);
1751 }
1752
1753 if (enq > 0) {
1754 /* Update mbox. */
1755 AGE_COMMIT_MBOX(sc);
1756 /* Set a timeout in case the chip goes out to lunch. */
1757 sc->age_watchdog_timer = AGE_TX_TIMEOUT;
1758 }
1759 }
1760
1761 static void
age_watchdog(struct age_softc * sc)1762 age_watchdog(struct age_softc *sc)
1763 {
1764 if_t ifp;
1765
1766 AGE_LOCK_ASSERT(sc);
1767
1768 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer)
1769 return;
1770
1771 ifp = sc->age_ifp;
1772 if ((sc->age_flags & AGE_FLAG_LINK) == 0) {
1773 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n");
1774 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1775 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1776 age_init_locked(sc);
1777 return;
1778 }
1779 if (sc->age_cdata.age_tx_cnt == 0) {
1780 if_printf(sc->age_ifp,
1781 "watchdog timeout (missed Tx interrupts) -- recovering\n");
1782 if (!if_sendq_empty(ifp))
1783 age_start_locked(ifp);
1784 return;
1785 }
1786 if_printf(sc->age_ifp, "watchdog timeout\n");
1787 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1788 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1789 age_init_locked(sc);
1790 if (!if_sendq_empty(ifp))
1791 age_start_locked(ifp);
1792 }
1793
1794 static int
age_ioctl(if_t ifp,u_long cmd,caddr_t data)1795 age_ioctl(if_t ifp, u_long cmd, caddr_t data)
1796 {
1797 struct age_softc *sc;
1798 struct ifreq *ifr;
1799 struct mii_data *mii;
1800 uint32_t reg;
1801 int error, mask;
1802
1803 sc = if_getsoftc(ifp);
1804 ifr = (struct ifreq *)data;
1805 error = 0;
1806 switch (cmd) {
1807 case SIOCSIFMTU:
1808 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU)
1809 error = EINVAL;
1810 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1811 AGE_LOCK(sc);
1812 if_setmtu(ifp, ifr->ifr_mtu);
1813 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1814 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1815 age_init_locked(sc);
1816 }
1817 AGE_UNLOCK(sc);
1818 }
1819 break;
1820 case SIOCSIFFLAGS:
1821 AGE_LOCK(sc);
1822 if ((if_getflags(ifp) & IFF_UP) != 0) {
1823 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1824 if (((if_getflags(ifp) ^ sc->age_if_flags)
1825 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1826 age_rxfilter(sc);
1827 } else {
1828 if ((sc->age_flags & AGE_FLAG_DETACH) == 0)
1829 age_init_locked(sc);
1830 }
1831 } else {
1832 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1833 age_stop(sc);
1834 }
1835 sc->age_if_flags = if_getflags(ifp);
1836 AGE_UNLOCK(sc);
1837 break;
1838 case SIOCADDMULTI:
1839 case SIOCDELMULTI:
1840 AGE_LOCK(sc);
1841 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1842 age_rxfilter(sc);
1843 AGE_UNLOCK(sc);
1844 break;
1845 case SIOCSIFMEDIA:
1846 case SIOCGIFMEDIA:
1847 mii = device_get_softc(sc->age_miibus);
1848 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1849 break;
1850 case SIOCSIFCAP:
1851 AGE_LOCK(sc);
1852 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1853 if ((mask & IFCAP_TXCSUM) != 0 &&
1854 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
1855 if_togglecapenable(ifp, IFCAP_TXCSUM);
1856 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1857 if_sethwassistbits(ifp, AGE_CSUM_FEATURES, 0);
1858 else
1859 if_sethwassistbits(ifp, 0, AGE_CSUM_FEATURES);
1860 }
1861 if ((mask & IFCAP_RXCSUM) != 0 &&
1862 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
1863 if_togglecapenable(ifp, IFCAP_RXCSUM);
1864 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1865 reg &= ~MAC_CFG_RXCSUM_ENB;
1866 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
1867 reg |= MAC_CFG_RXCSUM_ENB;
1868 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1869 }
1870 if ((mask & IFCAP_TSO4) != 0 &&
1871 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
1872 if_togglecapenable(ifp, IFCAP_TSO4);
1873 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
1874 if_sethwassistbits(ifp, CSUM_TSO, 0);
1875 else
1876 if_sethwassistbits(ifp, 0, CSUM_TSO);
1877 }
1878
1879 if ((mask & IFCAP_WOL_MCAST) != 0 &&
1880 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0)
1881 if_togglecapenable(ifp, IFCAP_WOL_MCAST);
1882 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1883 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
1884 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
1885 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1886 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
1887 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
1888 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1889 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
1890 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
1891 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1892 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
1893 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
1894 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
1895 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
1896 age_rxvlan(sc);
1897 }
1898 AGE_UNLOCK(sc);
1899 VLAN_CAPABILITIES(ifp);
1900 break;
1901 default:
1902 error = ether_ioctl(ifp, cmd, data);
1903 break;
1904 }
1905
1906 return (error);
1907 }
1908
1909 static void
age_mac_config(struct age_softc * sc)1910 age_mac_config(struct age_softc *sc)
1911 {
1912 struct mii_data *mii;
1913 uint32_t reg;
1914
1915 AGE_LOCK_ASSERT(sc);
1916
1917 mii = device_get_softc(sc->age_miibus);
1918 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1919 reg &= ~MAC_CFG_FULL_DUPLEX;
1920 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC);
1921 reg &= ~MAC_CFG_SPEED_MASK;
1922 /* Reprogram MAC with resolved speed/duplex. */
1923 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1924 case IFM_10_T:
1925 case IFM_100_TX:
1926 reg |= MAC_CFG_SPEED_10_100;
1927 break;
1928 case IFM_1000_T:
1929 reg |= MAC_CFG_SPEED_1000;
1930 break;
1931 }
1932 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1933 reg |= MAC_CFG_FULL_DUPLEX;
1934 #ifdef notyet
1935 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1936 reg |= MAC_CFG_TX_FC;
1937 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1938 reg |= MAC_CFG_RX_FC;
1939 #endif
1940 }
1941
1942 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1943 }
1944
1945 static void
age_link_task(void * arg,int pending)1946 age_link_task(void *arg, int pending)
1947 {
1948 struct age_softc *sc;
1949 struct mii_data *mii;
1950 if_t ifp;
1951 uint32_t reg;
1952
1953 sc = (struct age_softc *)arg;
1954
1955 AGE_LOCK(sc);
1956 mii = device_get_softc(sc->age_miibus);
1957 ifp = sc->age_ifp;
1958 if (mii == NULL || ifp == NULL ||
1959 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
1960 AGE_UNLOCK(sc);
1961 return;
1962 }
1963
1964 sc->age_flags &= ~AGE_FLAG_LINK;
1965 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1966 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1967 case IFM_10_T:
1968 case IFM_100_TX:
1969 case IFM_1000_T:
1970 sc->age_flags |= AGE_FLAG_LINK;
1971 break;
1972 default:
1973 break;
1974 }
1975 }
1976
1977 /* Stop Rx/Tx MACs. */
1978 age_stop_rxmac(sc);
1979 age_stop_txmac(sc);
1980
1981 /* Program MACs with resolved speed/duplex/flow-control. */
1982 if ((sc->age_flags & AGE_FLAG_LINK) != 0) {
1983 age_mac_config(sc);
1984 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1985 /* Restart DMA engine and Tx/Rx MAC. */
1986 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
1987 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB);
1988 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
1989 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1990 }
1991
1992 AGE_UNLOCK(sc);
1993 }
1994
1995 static void
age_stats_update(struct age_softc * sc)1996 age_stats_update(struct age_softc *sc)
1997 {
1998 struct age_stats *stat;
1999 struct smb *smb;
2000 if_t ifp;
2001
2002 AGE_LOCK_ASSERT(sc);
2003
2004 stat = &sc->age_stat;
2005
2006 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2007 sc->age_cdata.age_smb_block_map,
2008 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2009
2010 smb = sc->age_rdata.age_smb_block;
2011 if (smb->updated == 0)
2012 return;
2013
2014 ifp = sc->age_ifp;
2015 /* Rx stats. */
2016 stat->rx_frames += smb->rx_frames;
2017 stat->rx_bcast_frames += smb->rx_bcast_frames;
2018 stat->rx_mcast_frames += smb->rx_mcast_frames;
2019 stat->rx_pause_frames += smb->rx_pause_frames;
2020 stat->rx_control_frames += smb->rx_control_frames;
2021 stat->rx_crcerrs += smb->rx_crcerrs;
2022 stat->rx_lenerrs += smb->rx_lenerrs;
2023 stat->rx_bytes += smb->rx_bytes;
2024 stat->rx_runts += smb->rx_runts;
2025 stat->rx_fragments += smb->rx_fragments;
2026 stat->rx_pkts_64 += smb->rx_pkts_64;
2027 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2028 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2029 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2030 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2031 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2032 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2033 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2034 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2035 stat->rx_desc_oflows += smb->rx_desc_oflows;
2036 stat->rx_alignerrs += smb->rx_alignerrs;
2037 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2038 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2039 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2040
2041 /* Tx stats. */
2042 stat->tx_frames += smb->tx_frames;
2043 stat->tx_bcast_frames += smb->tx_bcast_frames;
2044 stat->tx_mcast_frames += smb->tx_mcast_frames;
2045 stat->tx_pause_frames += smb->tx_pause_frames;
2046 stat->tx_excess_defer += smb->tx_excess_defer;
2047 stat->tx_control_frames += smb->tx_control_frames;
2048 stat->tx_deferred += smb->tx_deferred;
2049 stat->tx_bytes += smb->tx_bytes;
2050 stat->tx_pkts_64 += smb->tx_pkts_64;
2051 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2052 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2053 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2054 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2055 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2056 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2057 stat->tx_single_colls += smb->tx_single_colls;
2058 stat->tx_multi_colls += smb->tx_multi_colls;
2059 stat->tx_late_colls += smb->tx_late_colls;
2060 stat->tx_excess_colls += smb->tx_excess_colls;
2061 stat->tx_underrun += smb->tx_underrun;
2062 stat->tx_desc_underrun += smb->tx_desc_underrun;
2063 stat->tx_lenerrs += smb->tx_lenerrs;
2064 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2065 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2066 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2067
2068 /* Update counters in ifnet. */
2069 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames);
2070
2071 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls +
2072 smb->tx_multi_colls + smb->tx_late_colls +
2073 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT);
2074
2075 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_excess_colls +
2076 smb->tx_late_colls + smb->tx_underrun +
2077 smb->tx_pkts_truncated);
2078
2079 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames);
2080
2081 if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs +
2082 smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated +
2083 smb->rx_fifo_oflows + smb->rx_desc_oflows +
2084 smb->rx_alignerrs);
2085
2086 /* Update done, clear. */
2087 smb->updated = 0;
2088
2089 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2090 sc->age_cdata.age_smb_block_map,
2091 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2092 }
2093
2094 static int
age_intr(void * arg)2095 age_intr(void *arg)
2096 {
2097 struct age_softc *sc;
2098 uint32_t status;
2099
2100 sc = (struct age_softc *)arg;
2101
2102 status = CSR_READ_4(sc, AGE_INTR_STATUS);
2103 if (status == 0 || (status & AGE_INTRS) == 0)
2104 return (FILTER_STRAY);
2105 /* Disable interrupts. */
2106 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
2107 taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2108
2109 return (FILTER_HANDLED);
2110 }
2111
2112 static void
age_int_task(void * arg,int pending)2113 age_int_task(void *arg, int pending)
2114 {
2115 struct age_softc *sc;
2116 if_t ifp;
2117 struct cmb *cmb;
2118 uint32_t status;
2119
2120 sc = (struct age_softc *)arg;
2121
2122 AGE_LOCK(sc);
2123
2124 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2125 sc->age_cdata.age_cmb_block_map,
2126 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2127 cmb = sc->age_rdata.age_cmb_block;
2128 status = le32toh(cmb->intr_status);
2129 if (sc->age_morework != 0)
2130 status |= INTR_CMB_RX;
2131 if ((status & AGE_INTRS) == 0)
2132 goto done;
2133
2134 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >>
2135 TPD_CONS_SHIFT;
2136 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >>
2137 RRD_PROD_SHIFT;
2138 /* Let hardware know CMB was served. */
2139 cmb->intr_status = 0;
2140 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2141 sc->age_cdata.age_cmb_block_map,
2142 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2143
2144 ifp = sc->age_ifp;
2145 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2146 if ((status & INTR_CMB_RX) != 0)
2147 sc->age_morework = age_rxintr(sc, sc->age_rr_prod,
2148 sc->age_process_limit);
2149 if ((status & INTR_CMB_TX) != 0)
2150 age_txintr(sc, sc->age_tpd_cons);
2151 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2152 if ((status & INTR_DMA_RD_TO_RST) != 0)
2153 device_printf(sc->age_dev,
2154 "DMA read error! -- resetting\n");
2155 if ((status & INTR_DMA_WR_TO_RST) != 0)
2156 device_printf(sc->age_dev,
2157 "DMA write error! -- resetting\n");
2158 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2159 age_init_locked(sc);
2160 }
2161 if (!if_sendq_empty(ifp))
2162 age_start_locked(ifp);
2163 if ((status & INTR_SMB) != 0)
2164 age_stats_update(sc);
2165 }
2166
2167 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */
2168 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2169 sc->age_cdata.age_cmb_block_map,
2170 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2171 status = le32toh(cmb->intr_status);
2172 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) {
2173 taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2174 AGE_UNLOCK(sc);
2175 return;
2176 }
2177
2178 done:
2179 /* Re-enable interrupts. */
2180 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2181 AGE_UNLOCK(sc);
2182 }
2183
2184 static void
age_txintr(struct age_softc * sc,int tpd_cons)2185 age_txintr(struct age_softc *sc, int tpd_cons)
2186 {
2187 if_t ifp;
2188 struct age_txdesc *txd;
2189 int cons, prog;
2190
2191 AGE_LOCK_ASSERT(sc);
2192
2193 ifp = sc->age_ifp;
2194
2195 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2196 sc->age_cdata.age_tx_ring_map,
2197 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2198
2199 /*
2200 * Go through our Tx list and free mbufs for those
2201 * frames which have been transmitted.
2202 */
2203 cons = sc->age_cdata.age_tx_cons;
2204 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) {
2205 if (sc->age_cdata.age_tx_cnt <= 0)
2206 break;
2207 prog++;
2208 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2209 sc->age_cdata.age_tx_cnt--;
2210 txd = &sc->age_cdata.age_txdesc[cons];
2211 /*
2212 * Clear Tx descriptors, it's not required but would
2213 * help debugging in case of Tx issues.
2214 */
2215 txd->tx_desc->addr = 0;
2216 txd->tx_desc->len = 0;
2217 txd->tx_desc->flags = 0;
2218
2219 if (txd->tx_m == NULL)
2220 continue;
2221 /* Reclaim transmitted mbufs. */
2222 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap,
2223 BUS_DMASYNC_POSTWRITE);
2224 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap);
2225 m_freem(txd->tx_m);
2226 txd->tx_m = NULL;
2227 }
2228
2229 if (prog > 0) {
2230 sc->age_cdata.age_tx_cons = cons;
2231
2232 /*
2233 * Unarm watchdog timer only when there are no pending
2234 * Tx descriptors in queue.
2235 */
2236 if (sc->age_cdata.age_tx_cnt == 0)
2237 sc->age_watchdog_timer = 0;
2238 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2239 sc->age_cdata.age_tx_ring_map,
2240 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2241 }
2242 }
2243
2244 #ifndef __NO_STRICT_ALIGNMENT
2245 static struct mbuf *
age_fixup_rx(if_t ifp,struct mbuf * m)2246 age_fixup_rx(if_t ifp, struct mbuf *m)
2247 {
2248 struct mbuf *n;
2249 int i;
2250 uint16_t *src, *dst;
2251
2252 src = mtod(m, uint16_t *);
2253 dst = src - 3;
2254
2255 if (m->m_next == NULL) {
2256 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2257 *dst++ = *src++;
2258 m->m_data -= 6;
2259 return (m);
2260 }
2261 /*
2262 * Append a new mbuf to received mbuf chain and copy ethernet
2263 * header from the mbuf chain. This can save lots of CPU
2264 * cycles for jumbo frame.
2265 */
2266 MGETHDR(n, M_NOWAIT, MT_DATA);
2267 if (n == NULL) {
2268 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2269 m_freem(m);
2270 return (NULL);
2271 }
2272 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
2273 m->m_data += ETHER_HDR_LEN;
2274 m->m_len -= ETHER_HDR_LEN;
2275 n->m_len = ETHER_HDR_LEN;
2276 M_MOVE_PKTHDR(n, m);
2277 n->m_next = m;
2278 return (n);
2279 }
2280 #endif
2281
2282 /* Receive a frame. */
2283 static void
age_rxeof(struct age_softc * sc,struct rx_rdesc * rxrd)2284 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd)
2285 {
2286 struct age_rxdesc *rxd;
2287 if_t ifp;
2288 struct mbuf *mp, *m;
2289 uint32_t status, index, vtag;
2290 int count, nsegs;
2291 int rx_cons;
2292
2293 AGE_LOCK_ASSERT(sc);
2294
2295 ifp = sc->age_ifp;
2296 status = le32toh(rxrd->flags);
2297 index = le32toh(rxrd->index);
2298 rx_cons = AGE_RX_CONS(index);
2299 nsegs = AGE_RX_NSEGS(index);
2300
2301 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len));
2302 if ((status & (AGE_RRD_ERROR | AGE_RRD_LENGTH_NOK)) != 0) {
2303 /*
2304 * We want to pass the following frames to upper
2305 * layer regardless of error status of Rx return
2306 * ring.
2307 *
2308 * o IP/TCP/UDP checksum is bad.
2309 * o frame length and protocol specific length
2310 * does not match.
2311 */
2312 status |= AGE_RRD_IPCSUM_NOK | AGE_RRD_TCP_UDPCSUM_NOK;
2313 if ((status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE |
2314 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0)
2315 return;
2316 }
2317
2318 for (count = 0; count < nsegs; count++,
2319 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) {
2320 rxd = &sc->age_cdata.age_rxdesc[rx_cons];
2321 mp = rxd->rx_m;
2322 /* Add a new receive buffer to the ring. */
2323 if (age_newbuf(sc, rxd) != 0) {
2324 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2325 /* Reuse Rx buffers. */
2326 if (sc->age_cdata.age_rxhead != NULL)
2327 m_freem(sc->age_cdata.age_rxhead);
2328 break;
2329 }
2330
2331 /*
2332 * Assume we've received a full sized frame.
2333 * Actual size is fixed when we encounter the end of
2334 * multi-segmented frame.
2335 */
2336 mp->m_len = AGE_RX_BUF_SIZE;
2337
2338 /* Chain received mbufs. */
2339 if (sc->age_cdata.age_rxhead == NULL) {
2340 sc->age_cdata.age_rxhead = mp;
2341 sc->age_cdata.age_rxtail = mp;
2342 } else {
2343 mp->m_flags &= ~M_PKTHDR;
2344 sc->age_cdata.age_rxprev_tail =
2345 sc->age_cdata.age_rxtail;
2346 sc->age_cdata.age_rxtail->m_next = mp;
2347 sc->age_cdata.age_rxtail = mp;
2348 }
2349
2350 if (count == nsegs - 1) {
2351 /* Last desc. for this frame. */
2352 m = sc->age_cdata.age_rxhead;
2353 m->m_flags |= M_PKTHDR;
2354 /*
2355 * It seems that L1 controller has no way
2356 * to tell hardware to strip CRC bytes.
2357 */
2358 m->m_pkthdr.len = sc->age_cdata.age_rxlen -
2359 ETHER_CRC_LEN;
2360 if (nsegs > 1) {
2361 /* Set last mbuf size. */
2362 mp->m_len = sc->age_cdata.age_rxlen -
2363 ((nsegs - 1) * AGE_RX_BUF_SIZE);
2364 /* Remove the CRC bytes in chained mbufs. */
2365 if (mp->m_len <= ETHER_CRC_LEN) {
2366 sc->age_cdata.age_rxtail =
2367 sc->age_cdata.age_rxprev_tail;
2368 sc->age_cdata.age_rxtail->m_len -=
2369 (ETHER_CRC_LEN - mp->m_len);
2370 sc->age_cdata.age_rxtail->m_next = NULL;
2371 m_freem(mp);
2372 } else {
2373 mp->m_len -= ETHER_CRC_LEN;
2374 }
2375 } else
2376 m->m_len = m->m_pkthdr.len;
2377 m->m_pkthdr.rcvif = ifp;
2378 /*
2379 * Set checksum information.
2380 * It seems that L1 controller can compute partial
2381 * checksum. The partial checksum value can be used
2382 * to accelerate checksum computation for fragmented
2383 * TCP/UDP packets. Upper network stack already
2384 * takes advantage of the partial checksum value in
2385 * IP reassembly stage. But I'm not sure the
2386 * correctness of the partial hardware checksum
2387 * assistance due to lack of data sheet. If it is
2388 * proven to work on L1 I'll enable it.
2389 */
2390 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 &&
2391 (status & AGE_RRD_IPV4) != 0) {
2392 if ((status & AGE_RRD_IPCSUM_NOK) == 0)
2393 m->m_pkthdr.csum_flags |=
2394 CSUM_IP_CHECKED | CSUM_IP_VALID;
2395 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) &&
2396 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) {
2397 m->m_pkthdr.csum_flags |=
2398 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2399 m->m_pkthdr.csum_data = 0xffff;
2400 }
2401 /*
2402 * Don't mark bad checksum for TCP/UDP frames
2403 * as fragmented frames may always have set
2404 * bad checksummed bit of descriptor status.
2405 */
2406 }
2407
2408 /* Check for VLAN tagged frames. */
2409 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
2410 (status & AGE_RRD_VLAN) != 0) {
2411 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags));
2412 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag);
2413 m->m_flags |= M_VLANTAG;
2414 }
2415 #ifndef __NO_STRICT_ALIGNMENT
2416 m = age_fixup_rx(ifp, m);
2417 if (m != NULL)
2418 #endif
2419 {
2420 /* Pass it on. */
2421 AGE_UNLOCK(sc);
2422 if_input(ifp, m);
2423 AGE_LOCK(sc);
2424 }
2425 }
2426 }
2427
2428 /* Reset mbuf chains. */
2429 AGE_RXCHAIN_RESET(sc);
2430 }
2431
2432 static int
age_rxintr(struct age_softc * sc,int rr_prod,int count)2433 age_rxintr(struct age_softc *sc, int rr_prod, int count)
2434 {
2435 struct rx_rdesc *rxrd;
2436 int rr_cons, nsegs, pktlen, prog;
2437
2438 AGE_LOCK_ASSERT(sc);
2439
2440 rr_cons = sc->age_cdata.age_rr_cons;
2441 if (rr_cons == rr_prod)
2442 return (0);
2443
2444 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2445 sc->age_cdata.age_rr_ring_map,
2446 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2447 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2448 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE);
2449
2450 for (prog = 0; rr_cons != rr_prod; prog++) {
2451 if (count-- <= 0)
2452 break;
2453 rxrd = &sc->age_rdata.age_rr_ring[rr_cons];
2454 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index));
2455 if (nsegs == 0)
2456 break;
2457 /*
2458 * Check number of segments against received bytes.
2459 * Non-matching value would indicate that hardware
2460 * is still trying to update Rx return descriptors.
2461 * I'm not sure whether this check is really needed.
2462 */
2463 pktlen = AGE_RX_BYTES(le32toh(rxrd->len));
2464 if (nsegs != howmany(pktlen, AGE_RX_BUF_SIZE))
2465 break;
2466
2467 /* Received a frame. */
2468 age_rxeof(sc, rxrd);
2469 /* Clear return ring. */
2470 rxrd->index = 0;
2471 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT);
2472 sc->age_cdata.age_rx_cons += nsegs;
2473 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT;
2474 }
2475
2476 if (prog > 0) {
2477 /* Update the consumer index. */
2478 sc->age_cdata.age_rr_cons = rr_cons;
2479
2480 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2481 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE);
2482 /* Sync descriptors. */
2483 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2484 sc->age_cdata.age_rr_ring_map,
2485 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2486
2487 /* Notify hardware availability of new Rx buffers. */
2488 AGE_COMMIT_MBOX(sc);
2489 }
2490
2491 return (count > 0 ? 0 : EAGAIN);
2492 }
2493
2494 static void
age_tick(void * arg)2495 age_tick(void *arg)
2496 {
2497 struct age_softc *sc;
2498 struct mii_data *mii;
2499
2500 sc = (struct age_softc *)arg;
2501
2502 AGE_LOCK_ASSERT(sc);
2503
2504 mii = device_get_softc(sc->age_miibus);
2505 mii_tick(mii);
2506 age_watchdog(sc);
2507 callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2508 }
2509
2510 static void
age_reset(struct age_softc * sc)2511 age_reset(struct age_softc *sc)
2512 {
2513 uint32_t reg;
2514 int i;
2515
2516 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET);
2517 CSR_READ_4(sc, AGE_MASTER_CFG);
2518 DELAY(1000);
2519 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2520 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2521 break;
2522 DELAY(10);
2523 }
2524
2525 if (i == 0)
2526 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg);
2527 /* Initialize PCIe module. From Linux. */
2528 CSR_WRITE_4(sc, 0x12FC, 0x6500);
2529 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2530 }
2531
2532 static void
age_init(void * xsc)2533 age_init(void *xsc)
2534 {
2535 struct age_softc *sc;
2536
2537 sc = (struct age_softc *)xsc;
2538 AGE_LOCK(sc);
2539 age_init_locked(sc);
2540 AGE_UNLOCK(sc);
2541 }
2542
2543 static void
age_init_locked(struct age_softc * sc)2544 age_init_locked(struct age_softc *sc)
2545 {
2546 if_t ifp;
2547 struct mii_data *mii;
2548 uint8_t eaddr[ETHER_ADDR_LEN];
2549 bus_addr_t paddr;
2550 uint32_t reg, fsize;
2551 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo;
2552 int error;
2553
2554 AGE_LOCK_ASSERT(sc);
2555
2556 ifp = sc->age_ifp;
2557 mii = device_get_softc(sc->age_miibus);
2558
2559 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2560 return;
2561
2562 /*
2563 * Cancel any pending I/O.
2564 */
2565 age_stop(sc);
2566
2567 /*
2568 * Reset the chip to a known state.
2569 */
2570 age_reset(sc);
2571
2572 /* Initialize descriptors. */
2573 error = age_init_rx_ring(sc);
2574 if (error != 0) {
2575 device_printf(sc->age_dev, "no memory for Rx buffers.\n");
2576 age_stop(sc);
2577 return;
2578 }
2579 age_init_rr_ring(sc);
2580 age_init_tx_ring(sc);
2581 age_init_cmb_block(sc);
2582 age_init_smb_block(sc);
2583
2584 /* Reprogram the station address. */
2585 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN);
2586 CSR_WRITE_4(sc, AGE_PAR0,
2587 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2588 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]);
2589
2590 /* Set descriptor base addresses. */
2591 paddr = sc->age_rdata.age_tx_ring_paddr;
2592 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr));
2593 paddr = sc->age_rdata.age_rx_ring_paddr;
2594 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr));
2595 paddr = sc->age_rdata.age_rr_ring_paddr;
2596 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr));
2597 paddr = sc->age_rdata.age_tx_ring_paddr;
2598 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr));
2599 paddr = sc->age_rdata.age_cmb_block_paddr;
2600 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr));
2601 paddr = sc->age_rdata.age_smb_block_paddr;
2602 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr));
2603 /* Set Rx/Rx return descriptor counter. */
2604 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT,
2605 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) &
2606 DESC_RRD_CNT_MASK) |
2607 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK));
2608 /* Set Tx descriptor counter. */
2609 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT,
2610 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK);
2611
2612 /* Tell hardware that we're ready to load descriptors. */
2613 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD);
2614
2615 /*
2616 * Initialize mailbox register.
2617 * Updated producer/consumer index information is exchanged
2618 * through this mailbox register. However Tx producer and
2619 * Rx return consumer/Rx producer are all shared such that
2620 * it's hard to separate code path between Tx and Rx without
2621 * locking. If L1 hardware have a separate mail box register
2622 * for Tx and Rx consumer/producer management we could have
2623 * independent Tx/Rx handler which in turn Rx handler could have
2624 * been run without any locking.
2625 */
2626 AGE_COMMIT_MBOX(sc);
2627
2628 /* Configure IPG/IFG parameters. */
2629 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG,
2630 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) |
2631 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2632 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2633 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK));
2634
2635 /* Set parameters for half-duplex media. */
2636 CSR_WRITE_4(sc, AGE_HDPX_CFG,
2637 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2638 HDPX_CFG_LCOL_MASK) |
2639 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2640 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2641 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2642 HDPX_CFG_ABEBT_MASK) |
2643 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2644 HDPX_CFG_JAMIPG_MASK));
2645
2646 /* Configure interrupt moderation timer. */
2647 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod));
2648 reg = CSR_READ_4(sc, AGE_MASTER_CFG);
2649 reg &= ~MASTER_MTIMER_ENB;
2650 if (AGE_USECS(sc->age_int_mod) == 0)
2651 reg &= ~MASTER_ITIMER_ENB;
2652 else
2653 reg |= MASTER_ITIMER_ENB;
2654 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);
2655 if (bootverbose)
2656 device_printf(sc->age_dev, "interrupt moderation is %d us.\n",
2657 sc->age_int_mod);
2658 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000));
2659
2660 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */
2661 if (if_getmtu(ifp) < ETHERMTU)
2662 sc->age_max_frame_size = ETHERMTU;
2663 else
2664 sc->age_max_frame_size = if_getmtu(ifp);
2665 sc->age_max_frame_size += ETHER_HDR_LEN +
2666 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN;
2667 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size);
2668 /* Configure jumbo frame. */
2669 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t));
2670 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG,
2671 (((fsize / sizeof(uint64_t)) <<
2672 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) |
2673 ((RXQ_JUMBO_CFG_LKAH_DEFAULT <<
2674 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) |
2675 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) &
2676 RXQ_JUMBO_CFG_RRD_TIMER_MASK));
2677
2678 /* Configure flow-control parameters. From Linux. */
2679 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) {
2680 /*
2681 * Magic workaround for old-L1.
2682 * Don't know which hw revision requires this magic.
2683 */
2684 CSR_WRITE_4(sc, 0x12FC, 0x6500);
2685 /*
2686 * Another magic workaround for flow-control mode
2687 * change. From Linux.
2688 */
2689 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2690 }
2691 /*
2692 * TODO
2693 * Should understand pause parameter relationships between FIFO
2694 * size and number of Rx descriptors and Rx return descriptors.
2695 *
2696 * Magic parameters came from Linux.
2697 */
2698 switch (sc->age_chip_rev) {
2699 case 0x8001:
2700 case 0x9001:
2701 case 0x9002:
2702 case 0x9003:
2703 rxf_hi = AGE_RX_RING_CNT / 16;
2704 rxf_lo = (AGE_RX_RING_CNT * 7) / 8;
2705 rrd_hi = (AGE_RR_RING_CNT * 7) / 8;
2706 rrd_lo = AGE_RR_RING_CNT / 16;
2707 break;
2708 default:
2709 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);
2710 rxf_lo = reg / 16;
2711 if (rxf_lo < 192)
2712 rxf_lo = 192;
2713 rxf_hi = (reg * 7) / 8;
2714 if (rxf_hi < rxf_lo)
2715 rxf_hi = rxf_lo + 16;
2716 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);
2717 rrd_lo = reg / 8;
2718 rrd_hi = (reg * 7) / 8;
2719 if (rrd_lo < 2)
2720 rrd_lo = 2;
2721 if (rrd_hi < rrd_lo)
2722 rrd_hi = rrd_lo + 3;
2723 break;
2724 }
2725 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH,
2726 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) &
2727 RXQ_FIFO_PAUSE_THRESH_LO_MASK) |
2728 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) &
2729 RXQ_FIFO_PAUSE_THRESH_HI_MASK));
2730 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH,
2731 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) &
2732 RXQ_RRD_PAUSE_THRESH_LO_MASK) |
2733 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) &
2734 RXQ_RRD_PAUSE_THRESH_HI_MASK));
2735
2736 /* Configure RxQ. */
2737 CSR_WRITE_4(sc, AGE_RXQ_CFG,
2738 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
2739 RXQ_CFG_RD_BURST_MASK) |
2740 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT <<
2741 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) |
2742 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT <<
2743 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) |
2744 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2745
2746 /* Configure TxQ. */
2747 CSR_WRITE_4(sc, AGE_TXQ_CFG,
2748 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2749 TXQ_CFG_TPD_BURST_MASK) |
2750 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) &
2751 TXQ_CFG_TX_FIFO_BURST_MASK) |
2752 ((TXQ_CFG_TPD_FETCH_DEFAULT <<
2753 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) |
2754 TXQ_CFG_ENB);
2755
2756 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG,
2757 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) &
2758 TX_JUMBO_TPD_TH_MASK) |
2759 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) &
2760 TX_JUMBO_TPD_IPG_MASK));
2761 /* Configure DMA parameters. */
2762 CSR_WRITE_4(sc, AGE_DMA_CFG,
2763 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 |
2764 sc->age_dma_rd_burst | DMA_CFG_RD_ENB |
2765 sc->age_dma_wr_burst | DMA_CFG_WR_ENB);
2766
2767 /* Configure CMB DMA write threshold. */
2768 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH,
2769 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) &
2770 CMB_WR_THRESH_RRD_MASK) |
2771 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) &
2772 CMB_WR_THRESH_TPD_MASK));
2773
2774 /* Set CMB/SMB timer and enable them. */
2775 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER,
2776 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) |
2777 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK));
2778 /* Request SMB updates for every seconds. */
2779 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000));
2780 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB);
2781
2782 /*
2783 * Disable all WOL bits as WOL can interfere normal Rx
2784 * operation.
2785 */
2786 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
2787
2788 /*
2789 * Configure Tx/Rx MACs.
2790 * - Auto-padding for short frames.
2791 * - Enable CRC generation.
2792 * Start with full-duplex/1000Mbps media. Actual reconfiguration
2793 * of MAC is followed after link establishment.
2794 */
2795 CSR_WRITE_4(sc, AGE_MAC_CFG,
2796 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD |
2797 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 |
2798 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2799 MAC_CFG_PREAMBLE_MASK));
2800 /* Set up the receive filter. */
2801 age_rxfilter(sc);
2802 age_rxvlan(sc);
2803
2804 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2805 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
2806 reg |= MAC_CFG_RXCSUM_ENB;
2807
2808 /* Ack all pending interrupts and clear it. */
2809 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2810 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS);
2811
2812 /* Finally enable Tx/Rx MAC. */
2813 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2814
2815 sc->age_flags &= ~AGE_FLAG_LINK;
2816 /* Switch to the current media. */
2817 mii_mediachg(mii);
2818
2819 callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2820
2821 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
2822 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2823 }
2824
2825 static void
age_stop(struct age_softc * sc)2826 age_stop(struct age_softc *sc)
2827 {
2828 if_t ifp;
2829 struct age_txdesc *txd;
2830 struct age_rxdesc *rxd;
2831 uint32_t reg;
2832 int i;
2833
2834 AGE_LOCK_ASSERT(sc);
2835 /*
2836 * Mark the interface down and cancel the watchdog timer.
2837 */
2838 ifp = sc->age_ifp;
2839 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2840 sc->age_flags &= ~AGE_FLAG_LINK;
2841 callout_stop(&sc->age_tick_ch);
2842 sc->age_watchdog_timer = 0;
2843
2844 /*
2845 * Disable interrupts.
2846 */
2847 CSR_WRITE_4(sc, AGE_INTR_MASK, 0);
2848 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF);
2849 /* Stop CMB/SMB updates. */
2850 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0);
2851 /* Stop Rx/Tx MAC. */
2852 age_stop_rxmac(sc);
2853 age_stop_txmac(sc);
2854 /* Stop DMA. */
2855 CSR_WRITE_4(sc, AGE_DMA_CFG,
2856 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));
2857 /* Stop TxQ/RxQ. */
2858 CSR_WRITE_4(sc, AGE_TXQ_CFG,
2859 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);
2860 CSR_WRITE_4(sc, AGE_RXQ_CFG,
2861 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);
2862 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2863 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2864 break;
2865 DELAY(10);
2866 }
2867 if (i == 0)
2868 device_printf(sc->age_dev,
2869 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg);
2870
2871 /* Reclaim Rx buffers that have been processed. */
2872 if (sc->age_cdata.age_rxhead != NULL)
2873 m_freem(sc->age_cdata.age_rxhead);
2874 AGE_RXCHAIN_RESET(sc);
2875 /*
2876 * Free RX and TX mbufs still in the queues.
2877 */
2878 for (i = 0; i < AGE_RX_RING_CNT; i++) {
2879 rxd = &sc->age_cdata.age_rxdesc[i];
2880 if (rxd->rx_m != NULL) {
2881 bus_dmamap_sync(sc->age_cdata.age_rx_tag,
2882 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2883 bus_dmamap_unload(sc->age_cdata.age_rx_tag,
2884 rxd->rx_dmamap);
2885 m_freem(rxd->rx_m);
2886 rxd->rx_m = NULL;
2887 }
2888 }
2889 for (i = 0; i < AGE_TX_RING_CNT; i++) {
2890 txd = &sc->age_cdata.age_txdesc[i];
2891 if (txd->tx_m != NULL) {
2892 bus_dmamap_sync(sc->age_cdata.age_tx_tag,
2893 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2894 bus_dmamap_unload(sc->age_cdata.age_tx_tag,
2895 txd->tx_dmamap);
2896 m_freem(txd->tx_m);
2897 txd->tx_m = NULL;
2898 }
2899 }
2900 }
2901
2902 static void
age_stop_txmac(struct age_softc * sc)2903 age_stop_txmac(struct age_softc *sc)
2904 {
2905 uint32_t reg;
2906 int i;
2907
2908 AGE_LOCK_ASSERT(sc);
2909
2910 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2911 if ((reg & MAC_CFG_TX_ENB) != 0) {
2912 reg &= ~MAC_CFG_TX_ENB;
2913 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2914 }
2915 /* Stop Tx DMA engine. */
2916 reg = CSR_READ_4(sc, AGE_DMA_CFG);
2917 if ((reg & DMA_CFG_RD_ENB) != 0) {
2918 reg &= ~DMA_CFG_RD_ENB;
2919 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2920 }
2921 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2922 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2923 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0)
2924 break;
2925 DELAY(10);
2926 }
2927 if (i == 0)
2928 device_printf(sc->age_dev, "stopping TxMAC timeout!\n");
2929 }
2930
2931 static void
age_stop_rxmac(struct age_softc * sc)2932 age_stop_rxmac(struct age_softc *sc)
2933 {
2934 uint32_t reg;
2935 int i;
2936
2937 AGE_LOCK_ASSERT(sc);
2938
2939 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2940 if ((reg & MAC_CFG_RX_ENB) != 0) {
2941 reg &= ~MAC_CFG_RX_ENB;
2942 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2943 }
2944 /* Stop Rx DMA engine. */
2945 reg = CSR_READ_4(sc, AGE_DMA_CFG);
2946 if ((reg & DMA_CFG_WR_ENB) != 0) {
2947 reg &= ~DMA_CFG_WR_ENB;
2948 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2949 }
2950 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2951 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2952 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0)
2953 break;
2954 DELAY(10);
2955 }
2956 if (i == 0)
2957 device_printf(sc->age_dev, "stopping RxMAC timeout!\n");
2958 }
2959
2960 static void
age_init_tx_ring(struct age_softc * sc)2961 age_init_tx_ring(struct age_softc *sc)
2962 {
2963 struct age_ring_data *rd;
2964 struct age_txdesc *txd;
2965 int i;
2966
2967 AGE_LOCK_ASSERT(sc);
2968
2969 sc->age_cdata.age_tx_prod = 0;
2970 sc->age_cdata.age_tx_cons = 0;
2971 sc->age_cdata.age_tx_cnt = 0;
2972
2973 rd = &sc->age_rdata;
2974 bzero(rd->age_tx_ring, AGE_TX_RING_SZ);
2975 for (i = 0; i < AGE_TX_RING_CNT; i++) {
2976 txd = &sc->age_cdata.age_txdesc[i];
2977 txd->tx_desc = &rd->age_tx_ring[i];
2978 txd->tx_m = NULL;
2979 }
2980
2981 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2982 sc->age_cdata.age_tx_ring_map,
2983 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2984 }
2985
2986 static int
age_init_rx_ring(struct age_softc * sc)2987 age_init_rx_ring(struct age_softc *sc)
2988 {
2989 struct age_ring_data *rd;
2990 struct age_rxdesc *rxd;
2991 int i;
2992
2993 AGE_LOCK_ASSERT(sc);
2994
2995 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1;
2996 sc->age_morework = 0;
2997 rd = &sc->age_rdata;
2998 bzero(rd->age_rx_ring, AGE_RX_RING_SZ);
2999 for (i = 0; i < AGE_RX_RING_CNT; i++) {
3000 rxd = &sc->age_cdata.age_rxdesc[i];
3001 rxd->rx_m = NULL;
3002 rxd->rx_desc = &rd->age_rx_ring[i];
3003 if (age_newbuf(sc, rxd) != 0)
3004 return (ENOBUFS);
3005 }
3006
3007 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
3008 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE);
3009
3010 return (0);
3011 }
3012
3013 static void
age_init_rr_ring(struct age_softc * sc)3014 age_init_rr_ring(struct age_softc *sc)
3015 {
3016 struct age_ring_data *rd;
3017
3018 AGE_LOCK_ASSERT(sc);
3019
3020 sc->age_cdata.age_rr_cons = 0;
3021 AGE_RXCHAIN_RESET(sc);
3022
3023 rd = &sc->age_rdata;
3024 bzero(rd->age_rr_ring, AGE_RR_RING_SZ);
3025 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
3026 sc->age_cdata.age_rr_ring_map,
3027 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3028 }
3029
3030 static void
age_init_cmb_block(struct age_softc * sc)3031 age_init_cmb_block(struct age_softc *sc)
3032 {
3033 struct age_ring_data *rd;
3034
3035 AGE_LOCK_ASSERT(sc);
3036
3037 rd = &sc->age_rdata;
3038 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ);
3039 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
3040 sc->age_cdata.age_cmb_block_map,
3041 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3042 }
3043
3044 static void
age_init_smb_block(struct age_softc * sc)3045 age_init_smb_block(struct age_softc *sc)
3046 {
3047 struct age_ring_data *rd;
3048
3049 AGE_LOCK_ASSERT(sc);
3050
3051 rd = &sc->age_rdata;
3052 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ);
3053 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
3054 sc->age_cdata.age_smb_block_map,
3055 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3056 }
3057
3058 static int
age_newbuf(struct age_softc * sc,struct age_rxdesc * rxd)3059 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd)
3060 {
3061 struct rx_desc *desc;
3062 struct mbuf *m;
3063 bus_dma_segment_t segs[1];
3064 bus_dmamap_t map;
3065 int nsegs;
3066
3067 AGE_LOCK_ASSERT(sc);
3068
3069 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
3070 if (m == NULL)
3071 return (ENOBUFS);
3072 m->m_len = m->m_pkthdr.len = MCLBYTES;
3073 #ifndef __NO_STRICT_ALIGNMENT
3074 m_adj(m, AGE_RX_BUF_ALIGN);
3075 #endif
3076
3077 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag,
3078 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3079 m_freem(m);
3080 return (ENOBUFS);
3081 }
3082 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3083
3084 if (rxd->rx_m != NULL) {
3085 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3086 BUS_DMASYNC_POSTREAD);
3087 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap);
3088 }
3089 map = rxd->rx_dmamap;
3090 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap;
3091 sc->age_cdata.age_rx_sparemap = map;
3092 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3093 BUS_DMASYNC_PREREAD);
3094 rxd->rx_m = m;
3095
3096 desc = rxd->rx_desc;
3097 desc->addr = htole64(segs[0].ds_addr);
3098 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) <<
3099 AGE_RD_LEN_SHIFT);
3100 return (0);
3101 }
3102
3103 static void
age_rxvlan(struct age_softc * sc)3104 age_rxvlan(struct age_softc *sc)
3105 {
3106 if_t ifp;
3107 uint32_t reg;
3108
3109 AGE_LOCK_ASSERT(sc);
3110
3111 ifp = sc->age_ifp;
3112 reg = CSR_READ_4(sc, AGE_MAC_CFG);
3113 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3114 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
3115 reg |= MAC_CFG_VLAN_TAG_STRIP;
3116 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
3117 }
3118
3119 static u_int
age_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)3120 age_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
3121 {
3122 uint32_t *mchash = arg;
3123 uint32_t crc;
3124
3125 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
3126 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3127
3128 return (1);
3129 }
3130
3131 static void
age_rxfilter(struct age_softc * sc)3132 age_rxfilter(struct age_softc *sc)
3133 {
3134 if_t ifp;
3135 uint32_t mchash[2];
3136 uint32_t rxcfg;
3137
3138 AGE_LOCK_ASSERT(sc);
3139
3140 ifp = sc->age_ifp;
3141
3142 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);
3143 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3144 if ((if_getflags(ifp) & IFF_BROADCAST) != 0)
3145 rxcfg |= MAC_CFG_BCAST;
3146 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3147 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
3148 rxcfg |= MAC_CFG_PROMISC;
3149 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0)
3150 rxcfg |= MAC_CFG_ALLMULTI;
3151 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF);
3152 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF);
3153 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3154 return;
3155 }
3156
3157 /* Program new filter. */
3158 bzero(mchash, sizeof(mchash));
3159 if_foreach_llmaddr(ifp, age_hash_maddr, mchash);
3160
3161 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]);
3162 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]);
3163 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3164 }
3165
3166 static int
sysctl_age_stats(SYSCTL_HANDLER_ARGS)3167 sysctl_age_stats(SYSCTL_HANDLER_ARGS)
3168 {
3169 struct age_softc *sc;
3170 struct age_stats *stats;
3171 int error, result;
3172
3173 result = -1;
3174 error = sysctl_handle_int(oidp, &result, 0, req);
3175
3176 if (error != 0 || req->newptr == NULL)
3177 return (error);
3178
3179 if (result != 1)
3180 return (error);
3181
3182 sc = (struct age_softc *)arg1;
3183 stats = &sc->age_stat;
3184 printf("%s statistics:\n", device_get_nameunit(sc->age_dev));
3185 printf("Transmit good frames : %ju\n",
3186 (uintmax_t)stats->tx_frames);
3187 printf("Transmit good broadcast frames : %ju\n",
3188 (uintmax_t)stats->tx_bcast_frames);
3189 printf("Transmit good multicast frames : %ju\n",
3190 (uintmax_t)stats->tx_mcast_frames);
3191 printf("Transmit pause control frames : %u\n",
3192 stats->tx_pause_frames);
3193 printf("Transmit control frames : %u\n",
3194 stats->tx_control_frames);
3195 printf("Transmit frames with excessive deferrals : %u\n",
3196 stats->tx_excess_defer);
3197 printf("Transmit deferrals : %u\n",
3198 stats->tx_deferred);
3199 printf("Transmit good octets : %ju\n",
3200 (uintmax_t)stats->tx_bytes);
3201 printf("Transmit good broadcast octets : %ju\n",
3202 (uintmax_t)stats->tx_bcast_bytes);
3203 printf("Transmit good multicast octets : %ju\n",
3204 (uintmax_t)stats->tx_mcast_bytes);
3205 printf("Transmit frames 64 bytes : %ju\n",
3206 (uintmax_t)stats->tx_pkts_64);
3207 printf("Transmit frames 65 to 127 bytes : %ju\n",
3208 (uintmax_t)stats->tx_pkts_65_127);
3209 printf("Transmit frames 128 to 255 bytes : %ju\n",
3210 (uintmax_t)stats->tx_pkts_128_255);
3211 printf("Transmit frames 256 to 511 bytes : %ju\n",
3212 (uintmax_t)stats->tx_pkts_256_511);
3213 printf("Transmit frames 512 to 1024 bytes : %ju\n",
3214 (uintmax_t)stats->tx_pkts_512_1023);
3215 printf("Transmit frames 1024 to 1518 bytes : %ju\n",
3216 (uintmax_t)stats->tx_pkts_1024_1518);
3217 printf("Transmit frames 1519 to MTU bytes : %ju\n",
3218 (uintmax_t)stats->tx_pkts_1519_max);
3219 printf("Transmit single collisions : %u\n",
3220 stats->tx_single_colls);
3221 printf("Transmit multiple collisions : %u\n",
3222 stats->tx_multi_colls);
3223 printf("Transmit late collisions : %u\n",
3224 stats->tx_late_colls);
3225 printf("Transmit abort due to excessive collisions : %u\n",
3226 stats->tx_excess_colls);
3227 printf("Transmit underruns due to FIFO underruns : %u\n",
3228 stats->tx_underrun);
3229 printf("Transmit descriptor write-back errors : %u\n",
3230 stats->tx_desc_underrun);
3231 printf("Transmit frames with length mismatched frame size : %u\n",
3232 stats->tx_lenerrs);
3233 printf("Transmit frames with truncated due to MTU size : %u\n",
3234 stats->tx_lenerrs);
3235
3236 printf("Receive good frames : %ju\n",
3237 (uintmax_t)stats->rx_frames);
3238 printf("Receive good broadcast frames : %ju\n",
3239 (uintmax_t)stats->rx_bcast_frames);
3240 printf("Receive good multicast frames : %ju\n",
3241 (uintmax_t)stats->rx_mcast_frames);
3242 printf("Receive pause control frames : %u\n",
3243 stats->rx_pause_frames);
3244 printf("Receive control frames : %u\n",
3245 stats->rx_control_frames);
3246 printf("Receive CRC errors : %u\n",
3247 stats->rx_crcerrs);
3248 printf("Receive frames with length errors : %u\n",
3249 stats->rx_lenerrs);
3250 printf("Receive good octets : %ju\n",
3251 (uintmax_t)stats->rx_bytes);
3252 printf("Receive good broadcast octets : %ju\n",
3253 (uintmax_t)stats->rx_bcast_bytes);
3254 printf("Receive good multicast octets : %ju\n",
3255 (uintmax_t)stats->rx_mcast_bytes);
3256 printf("Receive frames too short : %u\n",
3257 stats->rx_runts);
3258 printf("Receive fragmented frames : %ju\n",
3259 (uintmax_t)stats->rx_fragments);
3260 printf("Receive frames 64 bytes : %ju\n",
3261 (uintmax_t)stats->rx_pkts_64);
3262 printf("Receive frames 65 to 127 bytes : %ju\n",
3263 (uintmax_t)stats->rx_pkts_65_127);
3264 printf("Receive frames 128 to 255 bytes : %ju\n",
3265 (uintmax_t)stats->rx_pkts_128_255);
3266 printf("Receive frames 256 to 511 bytes : %ju\n",
3267 (uintmax_t)stats->rx_pkts_256_511);
3268 printf("Receive frames 512 to 1024 bytes : %ju\n",
3269 (uintmax_t)stats->rx_pkts_512_1023);
3270 printf("Receive frames 1024 to 1518 bytes : %ju\n",
3271 (uintmax_t)stats->rx_pkts_1024_1518);
3272 printf("Receive frames 1519 to MTU bytes : %ju\n",
3273 (uintmax_t)stats->rx_pkts_1519_max);
3274 printf("Receive frames too long : %ju\n",
3275 (uint64_t)stats->rx_pkts_truncated);
3276 printf("Receive frames with FIFO overflow : %u\n",
3277 stats->rx_fifo_oflows);
3278 printf("Receive frames with return descriptor overflow : %u\n",
3279 stats->rx_desc_oflows);
3280 printf("Receive frames with alignment errors : %u\n",
3281 stats->rx_alignerrs);
3282 printf("Receive frames dropped due to address filtering : %ju\n",
3283 (uint64_t)stats->rx_pkts_filtered);
3284
3285 return (error);
3286 }
3287
3288 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)3289 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3290 {
3291 int error, value;
3292
3293 if (arg1 == NULL)
3294 return (EINVAL);
3295 value = *(int *)arg1;
3296 error = sysctl_handle_int(oidp, &value, 0, req);
3297 if (error || req->newptr == NULL)
3298 return (error);
3299 if (value < low || value > high)
3300 return (EINVAL);
3301 *(int *)arg1 = value;
3302
3303 return (0);
3304 }
3305
3306 static int
sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS)3307 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS)
3308 {
3309 return (sysctl_int_range(oidp, arg1, arg2, req,
3310 AGE_PROC_MIN, AGE_PROC_MAX));
3311 }
3312
3313 static int
sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS)3314 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS)
3315 {
3316
3317 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN,
3318 AGE_IM_TIMER_MAX));
3319 }
3320