1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef _HNS_ROCE_DEVICE_H
34 #define _HNS_ROCE_DEVICE_H
35
36 #include <rdma/ib_verbs.h>
37 #include <rdma/hns-abi.h>
38 #include "hns_roce_debugfs.h"
39
40 #define PCI_REVISION_ID_HIP08 0x21
41 #define PCI_REVISION_ID_HIP09 0x30
42
43 #define HNS_ROCE_MAX_MSG_LEN 0x80000000
44
45 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6
46
47 #define BA_BYTE_LEN 8
48
49 #define HNS_ROCE_MIN_CQE_NUM 0x40
50 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1
51
52 #define HNS_ROCE_MAX_IRQ_NUM 128
53
54 #define HNS_ROCE_SGE_IN_WQE 2
55 #define HNS_ROCE_SGE_SHIFT 4
56
57 #define EQ_ENABLE 1
58 #define EQ_DISABLE 0
59
60 #define HNS_ROCE_CEQ 0
61 #define HNS_ROCE_AEQ 1
62
63 #define HNS_ROCE_CEQE_SIZE 0x4
64 #define HNS_ROCE_AEQE_SIZE 0x10
65
66 #define HNS_ROCE_V3_EQE_SIZE 0x40
67
68 #define HNS_ROCE_V2_CQE_SIZE 32
69 #define HNS_ROCE_V3_CQE_SIZE 64
70
71 #define HNS_ROCE_V2_QPC_SZ 256
72 #define HNS_ROCE_V3_QPC_SZ 512
73
74 #define HNS_ROCE_MAX_PORTS 6
75 #define HNS_ROCE_GID_SIZE 16
76 #define HNS_ROCE_SGE_SIZE 16
77 #define HNS_ROCE_DWQE_SIZE 65536
78
79 #define HNS_ROCE_HOP_NUM_0 0xff
80
81 #define MR_TYPE_MR 0x00
82 #define MR_TYPE_FRMR 0x01
83 #define MR_TYPE_DMA 0x03
84
85 #define HNS_ROCE_FRMR_MAX_PA 512
86 #define HNS_ROCE_FRMR_ALIGN_SIZE 128
87
88 #define PKEY_ID 0xffff
89 #define NODE_DESC_SIZE 64
90 #define DB_REG_OFFSET 0x1000
91
92 /* Configure to HW for PAGE_SIZE larger than 4KB */
93 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12)
94
95 #define ATOMIC_WR_LEN 8
96
97 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4
98 #define SRQ_DB_REG 0x230
99
100 #define HNS_ROCE_QP_BANK_NUM 8
101 #define HNS_ROCE_CQ_BANK_NUM 4
102
103 #define CQ_BANKID_SHIFT 2
104 #define CQ_BANKID_MASK GENMASK(1, 0)
105
106 #define HNS_ROCE_MAX_CQ_COUNT 0xFFFF
107 #define HNS_ROCE_MAX_CQ_PERIOD 0xFFFF
108
109 enum {
110 SERV_TYPE_RC,
111 SERV_TYPE_UC,
112 SERV_TYPE_RD,
113 SERV_TYPE_UD,
114 SERV_TYPE_XRC = 5,
115 };
116
117 enum hns_roce_event {
118 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01,
119 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02,
120 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03,
121 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04,
122 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
123 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06,
124 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07,
125 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08,
126 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09,
127 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a,
128 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b,
129 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c,
130 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d,
131 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f,
132 /* 0x10 and 0x11 is unused in currently application case */
133 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12,
134 HNS_ROCE_EVENT_TYPE_MB = 0x13,
135 HNS_ROCE_EVENT_TYPE_FLR = 0x15,
136 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16,
137 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17,
138 };
139
140 enum {
141 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0),
142 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1),
143 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2),
144 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3),
145 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4),
146 HNS_ROCE_CAP_FLAG_SRQ = BIT(5),
147 HNS_ROCE_CAP_FLAG_XRC = BIT(6),
148 HNS_ROCE_CAP_FLAG_MW = BIT(7),
149 HNS_ROCE_CAP_FLAG_FRMR = BIT(8),
150 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9),
151 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10),
152 HNS_ROCE_CAP_FLAG_DIRECT_WQE = BIT(12),
153 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14),
154 HNS_ROCE_CAP_FLAG_STASH = BIT(17),
155 HNS_ROCE_CAP_FLAG_CQE_INLINE = BIT(19),
156 HNS_ROCE_CAP_FLAG_SRQ_RECORD_DB = BIT(22),
157 };
158
159 #define HNS_ROCE_DB_TYPE_COUNT 2
160 #define HNS_ROCE_DB_UNIT_SIZE 4
161
162 enum {
163 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
164 };
165
166 enum hns_roce_reset_stage {
167 HNS_ROCE_STATE_NON_RST,
168 HNS_ROCE_STATE_RST_BEF_DOWN,
169 HNS_ROCE_STATE_RST_DOWN,
170 HNS_ROCE_STATE_RST_UNINIT,
171 HNS_ROCE_STATE_RST_INIT,
172 HNS_ROCE_STATE_RST_INITED,
173 };
174
175 enum hns_roce_instance_state {
176 HNS_ROCE_STATE_NON_INIT,
177 HNS_ROCE_STATE_INIT,
178 HNS_ROCE_STATE_INITED,
179 HNS_ROCE_STATE_UNINIT,
180 };
181
182 enum {
183 HNS_ROCE_RST_DIRECT_RETURN = 0,
184 };
185
186 #define HNS_ROCE_CMD_SUCCESS 1
187
188 #define HNS_ROCE_MAX_HOP_NUM 3
189 /* The minimum page size is 4K for hardware */
190 #define HNS_HW_PAGE_SHIFT 12
191 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT)
192
193 #define HNS_HW_MAX_PAGE_SHIFT 27
194 #define HNS_HW_MAX_PAGE_SIZE (1 << HNS_HW_MAX_PAGE_SHIFT)
195
196 struct hns_roce_uar {
197 u64 pfn;
198 unsigned long index;
199 unsigned long logic_idx;
200 };
201
202 enum hns_roce_mmap_type {
203 HNS_ROCE_MMAP_TYPE_DB = 1,
204 HNS_ROCE_MMAP_TYPE_DWQE,
205 };
206
207 struct hns_user_mmap_entry {
208 struct rdma_user_mmap_entry rdma_entry;
209 enum hns_roce_mmap_type mmap_type;
210 u64 address;
211 };
212
213 struct hns_roce_ucontext {
214 struct ib_ucontext ibucontext;
215 struct hns_roce_uar uar;
216 struct list_head page_list;
217 struct mutex page_mutex;
218 struct hns_user_mmap_entry *db_mmap_entry;
219 u32 config;
220 u8 cq_bank_id;
221 };
222
223 struct hns_roce_pd {
224 struct ib_pd ibpd;
225 unsigned long pdn;
226 };
227
228 struct hns_roce_xrcd {
229 struct ib_xrcd ibxrcd;
230 u32 xrcdn;
231 };
232
233 struct hns_roce_bitmap {
234 /* Bitmap Traversal last a bit which is 1 */
235 unsigned long last;
236 unsigned long top;
237 unsigned long max;
238 unsigned long reserved_top;
239 unsigned long mask;
240 spinlock_t lock;
241 unsigned long *table;
242 };
243
244 struct hns_roce_ida {
245 struct ida ida;
246 u32 min; /* Lowest ID to allocate. */
247 u32 max; /* Highest ID to allocate. */
248 };
249
250 /* For Hardware Entry Memory */
251 struct hns_roce_hem_table {
252 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
253 u32 type;
254 /* HEM array elment num */
255 unsigned long num_hem;
256 /* Single obj size */
257 unsigned long obj_size;
258 unsigned long table_chunk_size;
259 struct mutex mutex;
260 struct hns_roce_hem **hem;
261 u64 **bt_l1;
262 dma_addr_t *bt_l1_dma_addr;
263 u64 **bt_l0;
264 dma_addr_t *bt_l0_dma_addr;
265 };
266
267 struct hns_roce_buf_region {
268 u32 offset; /* page offset */
269 u32 count; /* page count */
270 int hopnum; /* addressing hop num */
271 };
272
273 #define HNS_ROCE_MAX_BT_REGION 3
274 #define HNS_ROCE_MAX_BT_LEVEL 3
275 struct hns_roce_hem_list {
276 struct list_head root_bt;
277 /* link all bt dma mem by hop config */
278 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
279 struct list_head btm_bt; /* link all bottom bt in @mid_bt */
280 dma_addr_t root_ba; /* pointer to the root ba table */
281 };
282
283 enum mtr_type {
284 MTR_DEFAULT = 0,
285 MTR_PBL,
286 };
287
288 struct hns_roce_buf_attr {
289 struct {
290 size_t size; /* region size */
291 int hopnum; /* multi-hop addressing hop num */
292 } region[HNS_ROCE_MAX_BT_REGION];
293 unsigned int region_count; /* valid region count */
294 unsigned int page_shift; /* buffer page shift */
295 unsigned int user_access; /* umem access flag */
296 u64 iova;
297 enum mtr_type type;
298 bool mtt_only; /* only alloc buffer-required MTT memory */
299 bool adaptive; /* adaptive for page_shift and hopnum */
300 };
301
302 struct hns_roce_hem_cfg {
303 dma_addr_t root_ba; /* root BA table's address */
304 bool is_direct; /* addressing without BA table */
305 unsigned int ba_pg_shift; /* BA table page shift */
306 unsigned int buf_pg_shift; /* buffer page shift */
307 unsigned int buf_pg_count; /* buffer page count */
308 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
309 unsigned int region_count;
310 };
311
312 /* memory translate region */
313 struct hns_roce_mtr {
314 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
315 struct ib_umem *umem; /* user space buffer */
316 struct hns_roce_buf *kmem; /* kernel space buffer */
317 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */
318 };
319
320 struct hns_roce_mr {
321 struct ib_mr ibmr;
322 u64 iova; /* MR's virtual original addr */
323 u64 size; /* Address range of MR */
324 u32 key; /* Key of MR */
325 u32 pd; /* PD num of MR */
326 u32 access; /* Access permission of MR */
327 int enabled; /* MR's active status */
328 int type; /* MR's register type */
329 u32 pbl_hop_num; /* multi-hop number */
330 struct hns_roce_mtr pbl_mtr;
331 u32 npages;
332 dma_addr_t *page_list;
333 };
334
335 struct hns_roce_mr_table {
336 struct hns_roce_ida mtpt_ida;
337 struct hns_roce_hem_table mtpt_table;
338 };
339
340 struct hns_roce_wq {
341 u64 *wrid; /* Work request ID */
342 spinlock_t lock;
343 u32 wqe_cnt; /* WQE num */
344 u32 max_gs;
345 u32 rsv_sge;
346 u32 offset;
347 u32 wqe_shift; /* WQE size */
348 u32 head;
349 u32 tail;
350 void __iomem *db_reg;
351 u32 ext_sge_cnt;
352 };
353
354 struct hns_roce_sge {
355 unsigned int sge_cnt; /* SGE num */
356 u32 offset;
357 u32 sge_shift; /* SGE size */
358 };
359
360 struct hns_roce_buf_list {
361 void *buf;
362 dma_addr_t map;
363 };
364
365 /*
366 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous
367 * dma address range.
368 *
369 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep.
370 *
371 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even
372 * the allocated size is smaller than the required size.
373 */
374 enum {
375 HNS_ROCE_BUF_DIRECT = BIT(0),
376 HNS_ROCE_BUF_NOSLEEP = BIT(1),
377 HNS_ROCE_BUF_NOFAIL = BIT(2),
378 };
379
380 struct hns_roce_buf {
381 struct hns_roce_buf_list *trunk_list;
382 u32 ntrunks;
383 u32 npages;
384 unsigned int trunk_shift;
385 unsigned int page_shift;
386 };
387
388 struct hns_roce_db_pgdir {
389 struct list_head list;
390 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
391 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
392 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT];
393 u32 *page;
394 dma_addr_t db_dma;
395 };
396
397 struct hns_roce_user_db_page {
398 struct list_head list;
399 struct ib_umem *umem;
400 unsigned long user_virt;
401 refcount_t refcount;
402 };
403
404 struct hns_roce_db {
405 u32 *db_record;
406 union {
407 struct hns_roce_db_pgdir *pgdir;
408 struct hns_roce_user_db_page *user_page;
409 } u;
410 dma_addr_t dma;
411 void *virt_addr;
412 unsigned long index;
413 unsigned long order;
414 };
415
416 struct hns_roce_cq {
417 struct ib_cq ib_cq;
418 struct hns_roce_mtr mtr;
419 struct hns_roce_db db;
420 u32 flags;
421 spinlock_t lock;
422 u32 cq_depth;
423 u32 cons_index;
424 u32 *set_ci_db;
425 void __iomem *db_reg;
426 int arm_sn;
427 int cqe_size;
428 unsigned long cqn;
429 u32 vector;
430 refcount_t refcount;
431 struct completion free;
432 struct list_head sq_list; /* all qps on this send cq */
433 struct list_head rq_list; /* all qps on this recv cq */
434 int is_armed; /* cq is armed */
435 struct list_head node; /* all armed cqs are on a list */
436 };
437
438 struct hns_roce_idx_que {
439 struct hns_roce_mtr mtr;
440 u32 entry_shift;
441 unsigned long *bitmap;
442 u32 head;
443 u32 tail;
444 };
445
446 struct hns_roce_srq {
447 struct ib_srq ibsrq;
448 unsigned long srqn;
449 u32 wqe_cnt;
450 int max_gs;
451 u32 rsv_sge;
452 u32 wqe_shift;
453 u32 cqn;
454 u32 xrcdn;
455 void __iomem *db_reg;
456
457 refcount_t refcount;
458 struct completion free;
459
460 struct hns_roce_mtr buf_mtr;
461
462 u64 *wrid;
463 struct hns_roce_idx_que idx_que;
464 spinlock_t lock;
465 struct mutex mutex;
466 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
467 struct hns_roce_db rdb;
468 u32 cap_flags;
469 };
470
471 struct hns_roce_uar_table {
472 struct hns_roce_bitmap bitmap;
473 };
474
475 struct hns_roce_bank {
476 struct ida ida;
477 u32 inuse; /* Number of IDs allocated */
478 u32 min; /* Lowest ID to allocate. */
479 u32 max; /* Highest ID to allocate. */
480 u32 next; /* Next ID to allocate. */
481 };
482
483 struct hns_roce_qp_table {
484 struct hns_roce_hem_table qp_table;
485 struct hns_roce_hem_table irrl_table;
486 struct hns_roce_hem_table trrl_table;
487 struct hns_roce_hem_table sccc_table;
488 struct mutex scc_mutex;
489 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
490 struct mutex bank_mutex;
491 struct xarray dip_xa;
492 };
493
494 struct hns_roce_cq_table {
495 struct xarray array;
496 struct hns_roce_hem_table table;
497 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM];
498 struct mutex bank_mutex;
499 u32 ctx_num[HNS_ROCE_CQ_BANK_NUM];
500 };
501
502 struct hns_roce_srq_table {
503 struct hns_roce_ida srq_ida;
504 struct xarray xa;
505 struct hns_roce_hem_table table;
506 };
507
508 struct hns_roce_av {
509 u8 port;
510 u8 gid_index;
511 u8 stat_rate;
512 u8 hop_limit;
513 u32 flowlabel;
514 u16 udp_sport;
515 u8 sl;
516 u8 tclass;
517 u8 dgid[HNS_ROCE_GID_SIZE];
518 u8 mac[ETH_ALEN];
519 u16 vlan_id;
520 u8 vlan_en;
521 };
522
523 struct hns_roce_ah {
524 struct ib_ah ibah;
525 struct hns_roce_av av;
526 };
527
528 struct hns_roce_cmd_context {
529 struct completion done;
530 int result;
531 int next;
532 u64 out_param;
533 u16 token;
534 u16 busy;
535 };
536
537 enum hns_roce_cmdq_state {
538 HNS_ROCE_CMDQ_STATE_NORMAL,
539 HNS_ROCE_CMDQ_STATE_FATAL_ERR,
540 };
541
542 struct hns_roce_cmdq {
543 struct dma_pool *pool;
544 struct semaphore poll_sem;
545 /*
546 * Event mode: cmd register mutex protection,
547 * ensure to not exceed max_cmds and user use limit region
548 */
549 struct semaphore event_sem;
550 int max_cmds;
551 spinlock_t context_lock;
552 int free_head;
553 struct hns_roce_cmd_context *context;
554 /*
555 * Process whether use event mode, init default non-zero
556 * After the event queue of cmd event ready,
557 * can switch into event mode
558 * close device, switch into poll mode(non event mode)
559 */
560 u8 use_events;
561 enum hns_roce_cmdq_state state;
562 };
563
564 struct hns_roce_cmd_mailbox {
565 void *buf;
566 dma_addr_t dma;
567 };
568
569 struct hns_roce_mbox_msg {
570 u64 in_param;
571 u64 out_param;
572 u8 cmd;
573 u32 tag;
574 u16 token;
575 u8 event_en;
576 };
577
578 struct hns_roce_dev;
579
580 enum {
581 HNS_ROCE_FLUSH_FLAG = 0,
582 HNS_ROCE_STOP_FLUSH_FLAG = 1,
583 };
584
585 struct hns_roce_work {
586 struct hns_roce_dev *hr_dev;
587 struct work_struct work;
588 int event_type;
589 int sub_type;
590 u32 queue_num;
591 };
592
593 enum hns_roce_cong_type {
594 CONG_TYPE_DCQCN,
595 CONG_TYPE_LDCP,
596 CONG_TYPE_HC3,
597 CONG_TYPE_DIP,
598 };
599
600 struct hns_roce_qp {
601 struct ib_qp ibqp;
602 struct hns_roce_wq rq;
603 struct hns_roce_db rdb;
604 struct hns_roce_db sdb;
605 unsigned long en_flags;
606 enum ib_sig_type sq_signal_bits;
607 struct hns_roce_wq sq;
608
609 struct hns_roce_mtr mtr;
610
611 u32 buff_size;
612 struct mutex mutex;
613 u8 port;
614 u8 phy_port;
615 u8 sl;
616 u8 resp_depth;
617 u8 state;
618 u32 atomic_rd_en;
619 u32 qkey;
620 void (*event)(struct hns_roce_qp *qp,
621 enum hns_roce_event event_type);
622 unsigned long qpn;
623
624 u32 xrcdn;
625
626 refcount_t refcount;
627 struct completion free;
628
629 struct hns_roce_sge sge;
630 u32 next_sge;
631 enum ib_mtu path_mtu;
632 u32 max_inline_data;
633 u8 free_mr_en;
634
635 /* 0: flush needed, 1: unneeded */
636 unsigned long flush_flag;
637 struct hns_roce_work flush_work;
638 struct list_head node; /* all qps are on a list */
639 struct list_head rq_node; /* all recv qps are on a list */
640 struct list_head sq_node; /* all send qps are on a list */
641 struct hns_user_mmap_entry *dwqe_mmap_entry;
642 u32 config;
643 enum hns_roce_cong_type cong_type;
644 u8 tc_mode;
645 u8 priority;
646 spinlock_t flush_lock;
647 struct hns_roce_dip *dip;
648 };
649
650 struct hns_roce_ib_iboe {
651 spinlock_t lock;
652 struct net_device *netdevs[HNS_ROCE_MAX_PORTS];
653 struct notifier_block nb;
654 u8 phy_port[HNS_ROCE_MAX_PORTS];
655 };
656
657 struct hns_roce_ceqe {
658 __le32 comp;
659 __le32 rsv[15];
660 };
661
662 #define CEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_ceqe, h, l)
663
664 #define CEQE_CQN CEQE_FIELD_LOC(23, 0)
665 #define CEQE_OWNER CEQE_FIELD_LOC(31, 31)
666
667 struct hns_roce_aeqe {
668 __le32 asyn;
669 union {
670 struct {
671 __le32 num;
672 u32 rsv0;
673 u32 rsv1;
674 } queue_event;
675
676 struct {
677 __le64 out_param;
678 __le16 token;
679 u8 status;
680 u8 rsv0;
681 } __packed cmd;
682 } event;
683 __le32 rsv[12];
684 };
685
686 #define AEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_aeqe, h, l)
687
688 #define AEQE_EVENT_TYPE AEQE_FIELD_LOC(7, 0)
689 #define AEQE_SUB_TYPE AEQE_FIELD_LOC(15, 8)
690 #define AEQE_OWNER AEQE_FIELD_LOC(31, 31)
691 #define AEQE_EVENT_QUEUE_NUM AEQE_FIELD_LOC(55, 32)
692
693 struct hns_roce_eq {
694 struct hns_roce_dev *hr_dev;
695 void __iomem *db_reg;
696
697 int type_flag; /* Aeq:1 ceq:0 */
698 int eqn;
699 u32 entries;
700 int eqe_size;
701 int irq;
702 u32 cons_index;
703 int over_ignore;
704 int coalesce;
705 int arm_st;
706 int hop_num;
707 struct hns_roce_mtr mtr;
708 u16 eq_max_cnt;
709 u32 eq_period;
710 int shift;
711 int event_type;
712 int sub_type;
713 struct work_struct work;
714 };
715
716 struct hns_roce_eq_table {
717 struct hns_roce_eq *eq;
718 };
719
720 struct hns_roce_caps {
721 u64 fw_ver;
722 u8 num_ports;
723 int gid_table_len[HNS_ROCE_MAX_PORTS];
724 int pkey_table_len[HNS_ROCE_MAX_PORTS];
725 int local_ca_ack_delay;
726 int num_uars;
727 u32 phy_num_uars;
728 u32 max_sq_sg;
729 u32 max_sq_inline;
730 u32 max_rq_sg;
731 u32 rsv0;
732 u32 num_qps;
733 u32 reserved_qps;
734 u32 num_srqs;
735 u32 max_wqes;
736 u32 max_srq_wrs;
737 u32 max_srq_sges;
738 u32 max_sq_desc_sz;
739 u32 max_rq_desc_sz;
740 u32 rsv2;
741 int max_qp_init_rdma;
742 int max_qp_dest_rdma;
743 u32 num_cqs;
744 u32 max_cqes;
745 u32 min_cqes;
746 u32 min_wqes;
747 u32 reserved_cqs;
748 u32 reserved_srqs;
749 int num_aeq_vectors;
750 int num_comp_vectors;
751 int num_other_vectors;
752 u32 num_mtpts;
753 u32 rsv1;
754 u32 num_srqwqe_segs;
755 u32 num_idx_segs;
756 int reserved_mrws;
757 int reserved_uars;
758 int num_pds;
759 int reserved_pds;
760 u32 num_xrcds;
761 u32 reserved_xrcds;
762 u32 mtt_entry_sz;
763 u32 cqe_sz;
764 u32 page_size_cap;
765 u32 reserved_lkey;
766 int mtpt_entry_sz;
767 int qpc_sz;
768 int irrl_entry_sz;
769 int trrl_entry_sz;
770 int cqc_entry_sz;
771 int sccc_sz;
772 int qpc_timer_entry_sz;
773 int cqc_timer_entry_sz;
774 int srqc_entry_sz;
775 int idx_entry_sz;
776 u32 pbl_ba_pg_sz;
777 u32 pbl_buf_pg_sz;
778 u32 pbl_hop_num;
779 int aeqe_depth;
780 int ceqe_depth;
781 u32 aeqe_size;
782 u32 ceqe_size;
783 enum ib_mtu max_mtu;
784 u32 qpc_bt_num;
785 u32 qpc_timer_bt_num;
786 u32 srqc_bt_num;
787 u32 cqc_bt_num;
788 u32 cqc_timer_bt_num;
789 u32 mpt_bt_num;
790 u32 eqc_bt_num;
791 u32 smac_bt_num;
792 u32 sgid_bt_num;
793 u32 sccc_bt_num;
794 u32 gmv_bt_num;
795 u32 qpc_ba_pg_sz;
796 u32 qpc_buf_pg_sz;
797 u32 qpc_hop_num;
798 u32 srqc_ba_pg_sz;
799 u32 srqc_buf_pg_sz;
800 u32 srqc_hop_num;
801 u32 cqc_ba_pg_sz;
802 u32 cqc_buf_pg_sz;
803 u32 cqc_hop_num;
804 u32 mpt_ba_pg_sz;
805 u32 mpt_buf_pg_sz;
806 u32 mpt_hop_num;
807 u32 mtt_ba_pg_sz;
808 u32 mtt_buf_pg_sz;
809 u32 mtt_hop_num;
810 u32 wqe_sq_hop_num;
811 u32 wqe_sge_hop_num;
812 u32 wqe_rq_hop_num;
813 u32 sccc_ba_pg_sz;
814 u32 sccc_buf_pg_sz;
815 u32 sccc_hop_num;
816 u32 qpc_timer_ba_pg_sz;
817 u32 qpc_timer_buf_pg_sz;
818 u32 qpc_timer_hop_num;
819 u32 cqc_timer_ba_pg_sz;
820 u32 cqc_timer_buf_pg_sz;
821 u32 cqc_timer_hop_num;
822 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */
823 u32 cqe_buf_pg_sz;
824 u32 cqe_hop_num;
825 u32 srqwqe_ba_pg_sz;
826 u32 srqwqe_buf_pg_sz;
827 u32 srqwqe_hop_num;
828 u32 idx_ba_pg_sz;
829 u32 idx_buf_pg_sz;
830 u32 idx_hop_num;
831 u32 eqe_ba_pg_sz;
832 u32 eqe_buf_pg_sz;
833 u32 eqe_hop_num;
834 u32 gmv_entry_num;
835 u32 gmv_entry_sz;
836 u32 gmv_ba_pg_sz;
837 u32 gmv_buf_pg_sz;
838 u32 gmv_hop_num;
839 u32 sl_num;
840 u32 llm_buf_pg_sz;
841 u32 chunk_sz; /* chunk size in non multihop mode */
842 u64 flags;
843 u16 default_ceq_max_cnt;
844 u16 default_ceq_period;
845 u16 default_aeq_max_cnt;
846 u16 default_aeq_period;
847 u16 default_aeq_arm_st;
848 u16 default_ceq_arm_st;
849 u8 cong_cap;
850 enum hns_roce_cong_type default_cong_type;
851 u32 max_ack_req_msg_len;
852 };
853
854 enum hns_roce_device_state {
855 HNS_ROCE_DEVICE_STATE_INITED,
856 HNS_ROCE_DEVICE_STATE_RST_DOWN,
857 HNS_ROCE_DEVICE_STATE_UNINIT,
858 };
859
860 enum hns_roce_hw_pkt_stat_index {
861 HNS_ROCE_HW_RX_RC_PKT_CNT,
862 HNS_ROCE_HW_RX_UC_PKT_CNT,
863 HNS_ROCE_HW_RX_UD_PKT_CNT,
864 HNS_ROCE_HW_RX_XRC_PKT_CNT,
865 HNS_ROCE_HW_RX_PKT_CNT,
866 HNS_ROCE_HW_RX_ERR_PKT_CNT,
867 HNS_ROCE_HW_RX_CNP_PKT_CNT,
868 HNS_ROCE_HW_TX_RC_PKT_CNT,
869 HNS_ROCE_HW_TX_UC_PKT_CNT,
870 HNS_ROCE_HW_TX_UD_PKT_CNT,
871 HNS_ROCE_HW_TX_XRC_PKT_CNT,
872 HNS_ROCE_HW_TX_PKT_CNT,
873 HNS_ROCE_HW_TX_ERR_PKT_CNT,
874 HNS_ROCE_HW_TX_CNP_PKT_CNT,
875 HNS_ROCE_HW_TRP_GET_MPT_ERR_PKT_CNT,
876 HNS_ROCE_HW_TRP_GET_IRRL_ERR_PKT_CNT,
877 HNS_ROCE_HW_ECN_DB_CNT,
878 HNS_ROCE_HW_RX_BUF_CNT,
879 HNS_ROCE_HW_TRP_RX_SOF_CNT,
880 HNS_ROCE_HW_CQ_CQE_CNT,
881 HNS_ROCE_HW_CQ_POE_CNT,
882 HNS_ROCE_HW_CQ_NOTIFY_CNT,
883 HNS_ROCE_HW_CNT_TOTAL
884 };
885
886 enum hns_roce_sw_dfx_stat_index {
887 HNS_ROCE_DFX_AEQE_CNT,
888 HNS_ROCE_DFX_CEQE_CNT,
889 HNS_ROCE_DFX_CMDS_CNT,
890 HNS_ROCE_DFX_CMDS_ERR_CNT,
891 HNS_ROCE_DFX_MBX_POSTED_CNT,
892 HNS_ROCE_DFX_MBX_POLLED_CNT,
893 HNS_ROCE_DFX_MBX_EVENT_CNT,
894 HNS_ROCE_DFX_QP_CREATE_ERR_CNT,
895 HNS_ROCE_DFX_QP_MODIFY_ERR_CNT,
896 HNS_ROCE_DFX_CQ_CREATE_ERR_CNT,
897 HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT,
898 HNS_ROCE_DFX_SRQ_CREATE_ERR_CNT,
899 HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT,
900 HNS_ROCE_DFX_XRCD_ALLOC_ERR_CNT,
901 HNS_ROCE_DFX_MR_REG_ERR_CNT,
902 HNS_ROCE_DFX_MR_REREG_ERR_CNT,
903 HNS_ROCE_DFX_AH_CREATE_ERR_CNT,
904 HNS_ROCE_DFX_MMAP_ERR_CNT,
905 HNS_ROCE_DFX_UCTX_ALLOC_ERR_CNT,
906 HNS_ROCE_DFX_CNT_TOTAL
907 };
908
909 struct hns_roce_hw {
910 int (*cmq_init)(struct hns_roce_dev *hr_dev);
911 void (*cmq_exit)(struct hns_roce_dev *hr_dev);
912 int (*hw_profile)(struct hns_roce_dev *hr_dev);
913 int (*hw_init)(struct hns_roce_dev *hr_dev);
914 void (*hw_exit)(struct hns_roce_dev *hr_dev);
915 int (*post_mbox)(struct hns_roce_dev *hr_dev,
916 struct hns_roce_mbox_msg *mbox_msg);
917 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev);
918 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy);
919 int (*set_gid)(struct hns_roce_dev *hr_dev, int gid_index,
920 const union ib_gid *gid, const struct ib_gid_attr *attr);
921 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port,
922 const u8 *addr);
923 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
924 struct hns_roce_mr *mr);
925 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
926 struct hns_roce_mr *mr, int flags,
927 void *mb_buf);
928 int (*frmr_write_mtpt)(void *mb_buf, struct hns_roce_mr *mr);
929 void (*write_cqc)(struct hns_roce_dev *hr_dev,
930 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
931 dma_addr_t dma_handle);
932 int (*set_hem)(struct hns_roce_dev *hr_dev,
933 struct hns_roce_hem_table *table, int obj, u32 step_idx);
934 int (*clear_hem)(struct hns_roce_dev *hr_dev,
935 struct hns_roce_hem_table *table, int obj,
936 u32 step_idx);
937 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
938 int attr_mask, enum ib_qp_state cur_state,
939 enum ib_qp_state new_state, struct ib_udata *udata);
940 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
941 struct hns_roce_qp *hr_qp);
942 void (*dereg_mr)(struct hns_roce_dev *hr_dev);
943 int (*init_eq)(struct hns_roce_dev *hr_dev);
944 void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
945 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf);
946 int (*query_cqc)(struct hns_roce_dev *hr_dev, u32 cqn, void *buffer);
947 int (*query_qpc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer);
948 int (*query_mpt)(struct hns_roce_dev *hr_dev, u32 key, void *buffer);
949 int (*query_srqc)(struct hns_roce_dev *hr_dev, u32 srqn, void *buffer);
950 int (*query_sccc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer);
951 int (*query_hw_counter)(struct hns_roce_dev *hr_dev,
952 u64 *stats, u32 port, int *hw_counters);
953 int (*get_dscp)(struct hns_roce_dev *hr_dev, u8 dscp,
954 u8 *tc_mode, u8 *priority);
955 const struct ib_device_ops *hns_roce_dev_ops;
956 const struct ib_device_ops *hns_roce_dev_srq_ops;
957 };
958
959 struct hns_roce_dev {
960 struct ib_device ib_dev;
961 struct pci_dev *pci_dev;
962 struct device *dev;
963 struct hns_roce_uar priv_uar;
964 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
965 spinlock_t sm_lock;
966 bool active;
967 bool is_reset;
968 bool dis_db;
969 unsigned long reset_cnt;
970 struct hns_roce_ib_iboe iboe;
971 enum hns_roce_device_state state;
972 struct list_head qp_list; /* list of all qps on this dev */
973 spinlock_t qp_list_lock; /* protect qp_list */
974
975 struct list_head pgdir_list;
976 struct mutex pgdir_mutex;
977 int irq[HNS_ROCE_MAX_IRQ_NUM];
978 u8 __iomem *reg_base;
979 void __iomem *mem_base;
980 struct hns_roce_caps caps;
981 struct xarray qp_table_xa;
982
983 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
984 u64 sys_image_guid;
985 u32 vendor_id;
986 u32 vendor_part_id;
987 u32 hw_rev;
988 void __iomem *priv_addr;
989
990 struct hns_roce_cmdq cmd;
991 struct hns_roce_ida pd_ida;
992 struct hns_roce_ida xrcd_ida;
993 struct hns_roce_ida uar_ida;
994 struct hns_roce_mr_table mr_table;
995 struct hns_roce_cq_table cq_table;
996 struct hns_roce_srq_table srq_table;
997 struct hns_roce_qp_table qp_table;
998 struct hns_roce_eq_table eq_table;
999 struct hns_roce_hem_table qpc_timer_table;
1000 struct hns_roce_hem_table cqc_timer_table;
1001 /* GMV is the memory area that the driver allocates for the hardware
1002 * to store SGID, SMAC and VLAN information.
1003 */
1004 struct hns_roce_hem_table gmv_table;
1005
1006 int cmd_mod;
1007 int loop_idc;
1008 u32 sdb_offset;
1009 u32 odb_offset;
1010 const struct hns_roce_hw *hw;
1011 void *priv;
1012 struct workqueue_struct *irq_workq;
1013 struct work_struct ecc_work;
1014 u32 func_num;
1015 u32 is_vf;
1016 u32 cong_algo_tmpl_id;
1017 u64 dwqe_page;
1018 struct hns_roce_dev_debugfs dbgfs;
1019 atomic64_t *dfx_cnt;
1020 };
1021
1022 enum hns_roce_trace_type {
1023 TRACE_SQ,
1024 TRACE_RQ,
1025 TRACE_SRQ,
1026 };
1027
trace_type_to_str(enum hns_roce_trace_type type)1028 static inline const char *trace_type_to_str(enum hns_roce_trace_type type)
1029 {
1030 switch (type) {
1031 case TRACE_SQ:
1032 return "SQ";
1033 case TRACE_RQ:
1034 return "RQ";
1035 case TRACE_SRQ:
1036 return "SRQ";
1037 default:
1038 return "UNKNOWN";
1039 }
1040 }
1041
to_hr_dev(struct ib_device * ib_dev)1042 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
1043 {
1044 return container_of(ib_dev, struct hns_roce_dev, ib_dev);
1045 }
1046
1047 static inline struct hns_roce_ucontext
to_hr_ucontext(struct ib_ucontext * ibucontext)1048 *to_hr_ucontext(struct ib_ucontext *ibucontext)
1049 {
1050 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
1051 }
1052
to_hr_pd(struct ib_pd * ibpd)1053 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
1054 {
1055 return container_of(ibpd, struct hns_roce_pd, ibpd);
1056 }
1057
to_hr_xrcd(struct ib_xrcd * ibxrcd)1058 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd)
1059 {
1060 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd);
1061 }
1062
to_hr_ah(struct ib_ah * ibah)1063 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
1064 {
1065 return container_of(ibah, struct hns_roce_ah, ibah);
1066 }
1067
to_hr_mr(struct ib_mr * ibmr)1068 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
1069 {
1070 return container_of(ibmr, struct hns_roce_mr, ibmr);
1071 }
1072
to_hr_qp(struct ib_qp * ibqp)1073 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1074 {
1075 return container_of(ibqp, struct hns_roce_qp, ibqp);
1076 }
1077
to_hr_cq(struct ib_cq * ib_cq)1078 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1079 {
1080 return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1081 }
1082
to_hr_srq(struct ib_srq * ibsrq)1083 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1084 {
1085 return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1086 }
1087
1088 static inline struct hns_user_mmap_entry *
to_hns_mmap(struct rdma_user_mmap_entry * rdma_entry)1089 to_hns_mmap(struct rdma_user_mmap_entry *rdma_entry)
1090 {
1091 return container_of(rdma_entry, struct hns_user_mmap_entry, rdma_entry);
1092 }
1093
hns_roce_write64_k(__le32 val[2],void __iomem * dest)1094 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1095 {
1096 writeq(*(u64 *)val, dest);
1097 }
1098
1099 static inline struct hns_roce_qp
__hns_roce_qp_lookup(struct hns_roce_dev * hr_dev,u32 qpn)1100 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1101 {
1102 return xa_load(&hr_dev->qp_table_xa, qpn);
1103 }
1104
hns_roce_buf_offset(struct hns_roce_buf * buf,unsigned int offset)1105 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf,
1106 unsigned int offset)
1107 {
1108 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
1109 (offset & ((1 << buf->trunk_shift) - 1));
1110 }
1111
hns_roce_buf_dma_addr(struct hns_roce_buf * buf,unsigned int offset)1112 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf,
1113 unsigned int offset)
1114 {
1115 return buf->trunk_list[offset >> buf->trunk_shift].map +
1116 (offset & ((1 << buf->trunk_shift) - 1));
1117 }
1118
hns_roce_buf_page(struct hns_roce_buf * buf,u32 idx)1119 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx)
1120 {
1121 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift);
1122 }
1123
1124 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1125
to_hr_hw_page_addr(u64 addr)1126 static inline u64 to_hr_hw_page_addr(u64 addr)
1127 {
1128 return addr >> HNS_HW_PAGE_SHIFT;
1129 }
1130
to_hr_hw_page_shift(u32 page_shift)1131 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1132 {
1133 return page_shift - HNS_HW_PAGE_SHIFT;
1134 }
1135
to_hr_hem_hopnum(u32 hopnum,u32 count)1136 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1137 {
1138 if (count > 0)
1139 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1140
1141 return 0;
1142 }
1143
to_hr_hem_entries_size(u32 count,u32 buf_shift)1144 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1145 {
1146 return hr_hw_page_align(count << buf_shift);
1147 }
1148
to_hr_hem_entries_count(u32 count,u32 buf_shift)1149 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1150 {
1151 return hr_hw_page_align(count << buf_shift) >> buf_shift;
1152 }
1153
to_hr_hem_entries_shift(u32 count,u32 buf_shift)1154 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1155 {
1156 if (!count)
1157 return 0;
1158
1159 return ilog2(to_hr_hem_entries_count(count, buf_shift));
1160 }
1161
1162 #define DSCP_SHIFT 2
1163
get_tclass(const struct ib_global_route * grh)1164 static inline u8 get_tclass(const struct ib_global_route *grh)
1165 {
1166 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ?
1167 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class;
1168 }
1169
1170 void hns_roce_init_uar_table(struct hns_roce_dev *dev);
1171 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1172
1173 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1174 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1175 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1176 u64 out_param);
1177 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1178 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1179
1180 /* hns roce hw need current block and next block addr from mtt */
1181 #define MTT_MIN_COUNT 2
hns_roce_get_mtr_ba(struct hns_roce_mtr * mtr)1182 static inline dma_addr_t hns_roce_get_mtr_ba(struct hns_roce_mtr *mtr)
1183 {
1184 return mtr->hem_cfg.root_ba;
1185 }
1186
1187 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1188 u32 offset, u64 *mtt_buf, int mtt_max);
1189 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1190 struct hns_roce_buf_attr *buf_attr,
1191 unsigned int page_shift, struct ib_udata *udata,
1192 unsigned long user_addr);
1193 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1194 struct hns_roce_mtr *mtr);
1195 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1196 dma_addr_t *pages, unsigned int page_cnt);
1197
1198 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1199 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1200 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1201 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1202 void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1203 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev);
1204
1205 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1206 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1207
1208 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1209
1210 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1211 struct ib_udata *udata);
1212 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
hns_roce_destroy_ah(struct ib_ah * ah,u32 flags)1213 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
1214 {
1215 return 0;
1216 }
1217
1218 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1219 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1220
1221 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1222 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1223 u64 virt_addr, int access_flags,
1224 struct ib_dmah *dmah,
1225 struct ib_udata *udata);
1226 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start,
1227 u64 length, u64 virt_addr,
1228 int mr_access_flags, struct ib_pd *pd,
1229 struct ib_udata *udata);
1230 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1231 u32 max_num_sg);
1232 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1233 unsigned int *sg_offset);
1234 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1235 unsigned long key_to_hw_index(u32 key);
1236
1237 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1238 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size,
1239 u32 page_shift, u32 flags);
1240
1241 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1242 int buf_cnt, struct hns_roce_buf *buf,
1243 unsigned int page_shift);
1244 int hns_roce_get_umem_bufs(dma_addr_t *bufs,
1245 int buf_cnt, struct ib_umem *umem,
1246 unsigned int page_shift);
1247
1248 int hns_roce_create_srq(struct ib_srq *srq,
1249 struct ib_srq_init_attr *srq_init_attr,
1250 struct ib_udata *udata);
1251 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1252
1253 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1254 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1255
1256 int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr,
1257 struct ib_udata *udata);
1258 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1259 int attr_mask, struct ib_udata *udata);
1260 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1261 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1262 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1263 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n);
1264 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1265 struct ib_cq *ib_cq);
1266 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1267 struct hns_roce_cq *recv_cq);
1268 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1269 struct hns_roce_cq *recv_cq);
1270 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1271 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1272 struct ib_udata *udata);
1273 __be32 send_ieth(const struct ib_send_wr *wr);
1274 int to_hr_qp_type(int qp_type);
1275
1276 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1277 struct uverbs_attr_bundle *attrs);
1278
1279 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1280 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt,
1281 struct hns_roce_db *db);
1282 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1283 struct hns_roce_db *db);
1284 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1285 int order);
1286 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1287
1288 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1289 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1290 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp);
1291 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1292 void hns_roce_flush_cqe(struct hns_roce_dev *hr_dev, u32 qpn);
1293 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1294 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1295 int hns_roce_init(struct hns_roce_dev *hr_dev);
1296 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1297 int hns_roce_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq);
1298 int hns_roce_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq);
1299 int hns_roce_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp);
1300 int hns_roce_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ib_qp);
1301 int hns_roce_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr);
1302 int hns_roce_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr);
1303 int hns_roce_fill_res_srq_entry(struct sk_buff *msg, struct ib_srq *ib_srq);
1304 int hns_roce_fill_res_srq_entry_raw(struct sk_buff *msg, struct ib_srq *ib_srq);
1305 struct hns_user_mmap_entry *
1306 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
1307 size_t length,
1308 enum hns_roce_mmap_type mmap_type);
1309 bool check_sl_valid(struct hns_roce_dev *hr_dev, u8 sl);
1310 void hns_roce_put_cq_bankid_for_uctx(struct hns_roce_ucontext *uctx);
1311 void hns_roce_get_cq_bankid_for_uctx(struct hns_roce_ucontext *uctx);
1312
1313 #endif /* _HNS_ROCE_DEVICE_H */
1314