1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip Generic power domain support.
4 *
5 * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
6 */
7
8 #include <linux/arm-smccc.h>
9 #include <linux/io.h>
10 #include <linux/iopoll.h>
11 #include <linux/err.h>
12 #include <linux/mutex.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_clock.h>
15 #include <linux/pm_domain.h>
16 #include <linux/property.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_clk.h>
20 #include <linux/clk.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/mfd/syscon.h>
24 #include <soc/rockchip/pm_domains.h>
25 #include <soc/rockchip/rockchip_sip.h>
26 #include <dt-bindings/power/px30-power.h>
27 #include <dt-bindings/power/rockchip,rv1126-power.h>
28 #include <dt-bindings/power/rk3036-power.h>
29 #include <dt-bindings/power/rk3066-power.h>
30 #include <dt-bindings/power/rk3128-power.h>
31 #include <dt-bindings/power/rk3188-power.h>
32 #include <dt-bindings/power/rk3228-power.h>
33 #include <dt-bindings/power/rk3288-power.h>
34 #include <dt-bindings/power/rk3328-power.h>
35 #include <dt-bindings/power/rk3366-power.h>
36 #include <dt-bindings/power/rk3368-power.h>
37 #include <dt-bindings/power/rk3399-power.h>
38 #include <dt-bindings/power/rk3568-power.h>
39 #include <dt-bindings/power/rockchip,rk3576-power.h>
40 #include <dt-bindings/power/rk3588-power.h>
41
42 struct rockchip_domain_info {
43 const char *name;
44 int pwr_mask;
45 int status_mask;
46 int req_mask;
47 int idle_mask;
48 int ack_mask;
49 bool active_wakeup;
50 bool need_regulator;
51 int pwr_w_mask;
52 int req_w_mask;
53 int clk_ungate_mask;
54 int mem_status_mask;
55 int repair_status_mask;
56 u32 pwr_offset;
57 u32 mem_offset;
58 u32 req_offset;
59 };
60
61 struct rockchip_pmu_info {
62 u32 pwr_offset;
63 u32 status_offset;
64 u32 req_offset;
65 u32 idle_offset;
66 u32 ack_offset;
67 u32 mem_pwr_offset;
68 u32 chain_status_offset;
69 u32 mem_status_offset;
70 u32 repair_status_offset;
71 u32 clk_ungate_offset;
72
73 u32 core_pwrcnt_offset;
74 u32 gpu_pwrcnt_offset;
75
76 unsigned int core_power_transition_time;
77 unsigned int gpu_power_transition_time;
78
79 int num_domains;
80 const struct rockchip_domain_info *domain_info;
81 };
82
83 #define MAX_QOS_REGS_NUM 5
84 #define QOS_PRIORITY 0x08
85 #define QOS_MODE 0x0c
86 #define QOS_BANDWIDTH 0x10
87 #define QOS_SATURATION 0x14
88 #define QOS_EXTCONTROL 0x18
89
90 struct rockchip_pm_domain {
91 struct generic_pm_domain genpd;
92 const struct rockchip_domain_info *info;
93 struct rockchip_pmu *pmu;
94 int num_qos;
95 struct regmap **qos_regmap;
96 u32 *qos_save_regs[MAX_QOS_REGS_NUM];
97 int num_clks;
98 struct clk_bulk_data *clks;
99 struct device_node *node;
100 struct regulator *supply;
101 };
102
103 struct rockchip_pmu {
104 struct device *dev;
105 struct regmap *regmap;
106 const struct rockchip_pmu_info *info;
107 struct mutex mutex; /* mutex lock for pmu */
108 struct genpd_onecell_data genpd_data;
109 struct generic_pm_domain *domains[];
110 };
111
112 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
113
114 #define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \
115 { \
116 .name = _name, \
117 .pwr_mask = (pwr), \
118 .status_mask = (status), \
119 .req_mask = (req), \
120 .idle_mask = (idle), \
121 .ack_mask = (ack), \
122 .active_wakeup = (wakeup), \
123 }
124
125 #define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \
126 { \
127 .name = _name, \
128 .pwr_w_mask = (pwr) << 16, \
129 .pwr_mask = (pwr), \
130 .status_mask = (status), \
131 .req_w_mask = (req) << 16, \
132 .req_mask = (req), \
133 .idle_mask = (idle), \
134 .ack_mask = (ack), \
135 .active_wakeup = wakeup, \
136 }
137
138 #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup, regulator) \
139 { \
140 .name = _name, \
141 .pwr_offset = p_offset, \
142 .pwr_w_mask = (pwr) << 16, \
143 .pwr_mask = (pwr), \
144 .status_mask = (status), \
145 .mem_offset = m_offset, \
146 .mem_status_mask = (m_status), \
147 .repair_status_mask = (r_status), \
148 .req_offset = r_offset, \
149 .req_w_mask = (req) << 16, \
150 .req_mask = (req), \
151 .idle_mask = (idle), \
152 .ack_mask = (ack), \
153 .active_wakeup = wakeup, \
154 .need_regulator = regulator, \
155 }
156
157 #define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup) \
158 { \
159 .name = _name, \
160 .pwr_offset = p_offset, \
161 .pwr_w_mask = (pwr) << 16, \
162 .pwr_mask = (pwr), \
163 .status_mask = (status), \
164 .mem_offset = m_offset, \
165 .mem_status_mask = (m_status), \
166 .repair_status_mask = (r_status), \
167 .req_offset = r_offset, \
168 .req_w_mask = (req) << 16, \
169 .req_mask = (req), \
170 .idle_mask = (idle), \
171 .clk_ungate_mask = (g_mask), \
172 .ack_mask = (ack), \
173 .active_wakeup = wakeup, \
174 }
175
176 #define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \
177 { \
178 .name = _name, \
179 .req_mask = (req), \
180 .req_w_mask = (req) << 16, \
181 .ack_mask = (ack), \
182 .idle_mask = (idle), \
183 .active_wakeup = wakeup, \
184 }
185
186 #define DOMAIN_PX30(name, pwr, status, req, wakeup) \
187 DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup)
188
189 #define DOMAIN_RV1126(name, pwr, req, idle, wakeup) \
190 DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup)
191
192 #define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
193 DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
194
195 #define DOMAIN_RK3328(name, pwr, status, req, wakeup) \
196 DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup)
197
198 #define DOMAIN_RK3368(name, pwr, status, req, wakeup) \
199 DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup)
200
201 #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
202 DOMAIN(name, pwr, status, req, req, req, wakeup)
203
204 #define DOMAIN_RK3568(name, pwr, req, wakeup) \
205 DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
206
207 #define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \
208 DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup)
209
210 /*
211 * Dynamic Memory Controller may need to coordinate with us -- see
212 * rockchip_pmu_block().
213 *
214 * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
215 * block() while we're initializing the PMU.
216 */
217 static DEFINE_MUTEX(dmc_pmu_mutex);
218 static struct rockchip_pmu *dmc_pmu;
219
220 /*
221 * Block PMU transitions and make sure they don't interfere with ARM Trusted
222 * Firmware operations. There are two conflicts, noted in the comments below.
223 *
224 * Caller must unblock PMU transitions via rockchip_pmu_unblock().
225 */
rockchip_pmu_block(void)226 int rockchip_pmu_block(void)
227 {
228 struct rockchip_pmu *pmu;
229 struct generic_pm_domain *genpd;
230 struct rockchip_pm_domain *pd;
231 int i, ret;
232
233 mutex_lock(&dmc_pmu_mutex);
234
235 /* No PMU (yet)? Then we just block rockchip_pmu_probe(). */
236 if (!dmc_pmu)
237 return 0;
238 pmu = dmc_pmu;
239
240 /*
241 * mutex blocks all idle transitions: we can't touch the
242 * PMU_BUS_IDLE_REQ (our ".idle_offset") register while ARM Trusted
243 * Firmware might be using it.
244 */
245 mutex_lock(&pmu->mutex);
246
247 /*
248 * Power domain clocks: Per Rockchip, we *must* keep certain clocks
249 * enabled for the duration of power-domain transitions. Most
250 * transitions are handled by this driver, but some cases (in
251 * particular, DRAM DVFS / memory-controller idle) must be handled by
252 * firmware. Firmware can handle most clock management via a special
253 * "ungate" register (PMU_CRU_GATEDIS_CON0), but unfortunately, this
254 * doesn't handle PLLs. We can assist this transition by doing the
255 * clock management on behalf of firmware.
256 */
257 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
258 genpd = pmu->genpd_data.domains[i];
259 if (genpd) {
260 pd = to_rockchip_pd(genpd);
261 ret = clk_bulk_enable(pd->num_clks, pd->clks);
262 if (ret < 0) {
263 dev_err(pmu->dev,
264 "failed to enable clks for domain '%s': %d\n",
265 genpd->name, ret);
266 goto err;
267 }
268 }
269 }
270
271 return 0;
272
273 err:
274 for (i = i - 1; i >= 0; i--) {
275 genpd = pmu->genpd_data.domains[i];
276 if (genpd) {
277 pd = to_rockchip_pd(genpd);
278 clk_bulk_disable(pd->num_clks, pd->clks);
279 }
280 }
281 mutex_unlock(&pmu->mutex);
282 mutex_unlock(&dmc_pmu_mutex);
283
284 return ret;
285 }
286 EXPORT_SYMBOL_GPL(rockchip_pmu_block);
287
288 /* Unblock PMU transitions. */
rockchip_pmu_unblock(void)289 void rockchip_pmu_unblock(void)
290 {
291 struct rockchip_pmu *pmu;
292 struct generic_pm_domain *genpd;
293 struct rockchip_pm_domain *pd;
294 int i;
295
296 if (dmc_pmu) {
297 pmu = dmc_pmu;
298 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
299 genpd = pmu->genpd_data.domains[i];
300 if (genpd) {
301 pd = to_rockchip_pd(genpd);
302 clk_bulk_disable(pd->num_clks, pd->clks);
303 }
304 }
305
306 mutex_unlock(&pmu->mutex);
307 }
308
309 mutex_unlock(&dmc_pmu_mutex);
310 }
311 EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);
312
313 #define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup, regulator) \
314 DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup, regulator)
315
rockchip_pmu_domain_is_idle(struct rockchip_pm_domain * pd)316 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
317 {
318 struct rockchip_pmu *pmu = pd->pmu;
319 const struct rockchip_domain_info *pd_info = pd->info;
320 unsigned int val;
321
322 regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
323 return (val & pd_info->idle_mask) == pd_info->idle_mask;
324 }
325
rockchip_pmu_read_ack(struct rockchip_pmu * pmu)326 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
327 {
328 unsigned int val;
329
330 regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
331 return val;
332 }
333
rockchip_pmu_ungate_clk(struct rockchip_pm_domain * pd,bool ungate)334 static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ungate)
335 {
336 const struct rockchip_domain_info *pd_info = pd->info;
337 struct rockchip_pmu *pmu = pd->pmu;
338 unsigned int val;
339 int clk_ungate_w_mask = pd_info->clk_ungate_mask << 16;
340
341 if (!pd_info->clk_ungate_mask)
342 return 0;
343
344 if (!pmu->info->clk_ungate_offset)
345 return 0;
346
347 val = ungate ? (pd_info->clk_ungate_mask | clk_ungate_w_mask) :
348 clk_ungate_w_mask;
349 regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val);
350
351 return 0;
352 }
353
rockchip_pmu_set_idle_request(struct rockchip_pm_domain * pd,bool idle)354 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
355 bool idle)
356 {
357 const struct rockchip_domain_info *pd_info = pd->info;
358 struct generic_pm_domain *genpd = &pd->genpd;
359 struct rockchip_pmu *pmu = pd->pmu;
360 u32 pd_req_offset = pd_info->req_offset;
361 unsigned int target_ack;
362 unsigned int val;
363 bool is_idle;
364 int ret;
365
366 if (pd_info->req_mask == 0)
367 return 0;
368 else if (pd_info->req_w_mask)
369 regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset,
370 idle ? (pd_info->req_mask | pd_info->req_w_mask) :
371 pd_info->req_w_mask);
372 else
373 regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset,
374 pd_info->req_mask, idle ? -1U : 0);
375
376 wmb();
377
378 /* Wait util idle_ack = 1 */
379 target_ack = idle ? pd_info->ack_mask : 0;
380 ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
381 (val & pd_info->ack_mask) == target_ack,
382 0, 10000);
383 if (ret) {
384 dev_err(pmu->dev,
385 "failed to get ack on domain '%s', val=0x%x\n",
386 genpd->name, val);
387 return ret;
388 }
389
390 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
391 is_idle, is_idle == idle, 0, 10000);
392 if (ret) {
393 dev_err(pmu->dev,
394 "failed to set idle on domain '%s', val=%d\n",
395 genpd->name, is_idle);
396 return ret;
397 }
398
399 return 0;
400 }
401
rockchip_pmu_save_qos(struct rockchip_pm_domain * pd)402 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
403 {
404 int i;
405
406 for (i = 0; i < pd->num_qos; i++) {
407 regmap_read(pd->qos_regmap[i],
408 QOS_PRIORITY,
409 &pd->qos_save_regs[0][i]);
410 regmap_read(pd->qos_regmap[i],
411 QOS_MODE,
412 &pd->qos_save_regs[1][i]);
413 regmap_read(pd->qos_regmap[i],
414 QOS_BANDWIDTH,
415 &pd->qos_save_regs[2][i]);
416 regmap_read(pd->qos_regmap[i],
417 QOS_SATURATION,
418 &pd->qos_save_regs[3][i]);
419 regmap_read(pd->qos_regmap[i],
420 QOS_EXTCONTROL,
421 &pd->qos_save_regs[4][i]);
422 }
423 return 0;
424 }
425
rockchip_pmu_restore_qos(struct rockchip_pm_domain * pd)426 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
427 {
428 int i;
429
430 for (i = 0; i < pd->num_qos; i++) {
431 regmap_write(pd->qos_regmap[i],
432 QOS_PRIORITY,
433 pd->qos_save_regs[0][i]);
434 regmap_write(pd->qos_regmap[i],
435 QOS_MODE,
436 pd->qos_save_regs[1][i]);
437 regmap_write(pd->qos_regmap[i],
438 QOS_BANDWIDTH,
439 pd->qos_save_regs[2][i]);
440 regmap_write(pd->qos_regmap[i],
441 QOS_SATURATION,
442 pd->qos_save_regs[3][i]);
443 regmap_write(pd->qos_regmap[i],
444 QOS_EXTCONTROL,
445 pd->qos_save_regs[4][i]);
446 }
447
448 return 0;
449 }
450
rockchip_pmu_domain_is_on(struct rockchip_pm_domain * pd)451 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
452 {
453 struct rockchip_pmu *pmu = pd->pmu;
454 unsigned int val;
455
456 if (pd->info->repair_status_mask) {
457 regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val);
458 /* 1'b1: power on, 1'b0: power off */
459 return val & pd->info->repair_status_mask;
460 }
461
462 /* check idle status for idle-only domains */
463 if (pd->info->status_mask == 0)
464 return !rockchip_pmu_domain_is_idle(pd);
465
466 regmap_read(pmu->regmap, pmu->info->status_offset, &val);
467
468 /* 1'b0: power on, 1'b1: power off */
469 return !(val & pd->info->status_mask);
470 }
471
rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain * pd)472 static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
473 {
474 struct rockchip_pmu *pmu = pd->pmu;
475 unsigned int val;
476
477 regmap_read(pmu->regmap,
478 pmu->info->mem_status_offset + pd->info->mem_offset, &val);
479
480 /* 1'b0: power on, 1'b1: power off */
481 return !(val & pd->info->mem_status_mask);
482 }
483
rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain * pd)484 static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
485 {
486 struct rockchip_pmu *pmu = pd->pmu;
487 unsigned int val;
488
489 regmap_read(pmu->regmap,
490 pmu->info->chain_status_offset + pd->info->mem_offset, &val);
491
492 /* 1'b1: power on, 1'b0: power off */
493 return val & pd->info->mem_status_mask;
494 }
495
rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain * pd)496 static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
497 {
498 struct rockchip_pmu *pmu = pd->pmu;
499 struct generic_pm_domain *genpd = &pd->genpd;
500 bool is_on;
501 int ret = 0;
502
503 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
504 is_on == true, 0, 10000);
505 if (ret) {
506 dev_err(pmu->dev,
507 "failed to get chain status '%s', target_on=1, val=%d\n",
508 genpd->name, is_on);
509 goto error;
510 }
511
512 udelay(20);
513
514 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
515 (pd->info->pwr_mask | pd->info->pwr_w_mask));
516 wmb();
517
518 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
519 is_on == false, 0, 10000);
520 if (ret) {
521 dev_err(pmu->dev,
522 "failed to get mem status '%s', target_on=0, val=%d\n",
523 genpd->name, is_on);
524 goto error;
525 }
526
527 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
528 pd->info->pwr_w_mask);
529 wmb();
530
531 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
532 is_on == true, 0, 10000);
533 if (ret) {
534 dev_err(pmu->dev,
535 "failed to get mem status '%s', target_on=1, val=%d\n",
536 genpd->name, is_on);
537 }
538
539 error:
540 return ret;
541 }
542
rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain * pd,bool on)543 static int rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
544 bool on)
545 {
546 struct rockchip_pmu *pmu = pd->pmu;
547 struct generic_pm_domain *genpd = &pd->genpd;
548 u32 pd_pwr_offset = pd->info->pwr_offset;
549 bool is_on, is_mem_on = false;
550 struct arm_smccc_res res;
551 int ret;
552
553 if (pd->info->pwr_mask == 0)
554 return 0;
555
556 if (on && pd->info->mem_status_mask)
557 is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
558
559 if (pd->info->pwr_w_mask)
560 regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
561 on ? pd->info->pwr_w_mask :
562 (pd->info->pwr_mask | pd->info->pwr_w_mask));
563 else
564 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
565 pd->info->pwr_mask, on ? 0 : -1U);
566
567 wmb();
568
569 if (is_mem_on) {
570 ret = rockchip_pmu_domain_mem_reset(pd);
571 if (ret)
572 return ret;
573 }
574
575
576 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
577 is_on == on, 0, 10000);
578 if (ret) {
579 dev_err(pmu->dev, "failed to set domain '%s' %s, val=%d\n",
580 genpd->name, on ? "on" : "off", is_on);
581 return ret;
582 }
583
584 /* Inform firmware to keep this pd on or off */
585 if (arm_smccc_1_1_get_conduit() != SMCCC_CONDUIT_NONE)
586 arm_smccc_smc(ROCKCHIP_SIP_SUSPEND_MODE, ROCKCHIP_SLEEP_PD_CONFIG,
587 pmu->info->pwr_offset + pd_pwr_offset,
588 pd->info->pwr_mask, on, 0, 0, 0, &res);
589
590 return 0;
591 }
592
rockchip_pd_power(struct rockchip_pm_domain * pd,bool power_on)593 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
594 {
595 struct rockchip_pmu *pmu = pd->pmu;
596 int ret;
597
598 guard(mutex)(&pmu->mutex);
599
600 if (rockchip_pmu_domain_is_on(pd) == power_on)
601 return 0;
602
603 ret = clk_bulk_enable(pd->num_clks, pd->clks);
604 if (ret < 0) {
605 dev_err(pmu->dev, "failed to enable clocks\n");
606 return ret;
607 }
608
609 rockchip_pmu_ungate_clk(pd, true);
610
611 if (!power_on) {
612 rockchip_pmu_save_qos(pd);
613
614 /* if powering down, idle request to NIU first */
615 ret = rockchip_pmu_set_idle_request(pd, true);
616 if (ret < 0)
617 goto out;
618 }
619
620 ret = rockchip_do_pmu_set_power_domain(pd, power_on);
621 if (ret < 0)
622 goto out;
623
624 if (power_on) {
625 /* if powering up, leave idle mode */
626 ret = rockchip_pmu_set_idle_request(pd, false);
627 if (ret < 0)
628 goto out;
629
630 rockchip_pmu_restore_qos(pd);
631 }
632
633 out:
634 rockchip_pmu_ungate_clk(pd, false);
635 clk_bulk_disable(pd->num_clks, pd->clks);
636
637 return ret;
638 }
639
rockchip_pd_regulator_disable(struct rockchip_pm_domain * pd)640 static int rockchip_pd_regulator_disable(struct rockchip_pm_domain *pd)
641 {
642 return IS_ERR_OR_NULL(pd->supply) ? 0 : regulator_disable(pd->supply);
643 }
644
rockchip_pd_regulator_enable(struct rockchip_pm_domain * pd)645 static int rockchip_pd_regulator_enable(struct rockchip_pm_domain *pd)
646 {
647 struct rockchip_pmu *pmu = pd->pmu;
648
649 if (!pd->info->need_regulator)
650 return 0;
651
652 if (IS_ERR_OR_NULL(pd->supply)) {
653 pd->supply = devm_of_regulator_get(pmu->dev, pd->node, "domain");
654
655 if (IS_ERR(pd->supply))
656 return PTR_ERR(pd->supply);
657 }
658
659 return regulator_enable(pd->supply);
660 }
661
rockchip_pd_power_on(struct generic_pm_domain * domain)662 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
663 {
664 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
665 int ret;
666
667 ret = rockchip_pd_regulator_enable(pd);
668 if (ret) {
669 dev_err(pd->pmu->dev, "Failed to enable supply: %d\n", ret);
670 return ret;
671 }
672
673 ret = rockchip_pd_power(pd, true);
674 if (ret)
675 rockchip_pd_regulator_disable(pd);
676
677 return ret;
678 }
679
rockchip_pd_power_off(struct generic_pm_domain * domain)680 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
681 {
682 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
683 int ret;
684
685 ret = rockchip_pd_power(pd, false);
686 if (ret)
687 return ret;
688
689 rockchip_pd_regulator_disable(pd);
690 return ret;
691 }
692
rockchip_pd_attach_dev(struct generic_pm_domain * genpd,struct device * dev)693 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
694 struct device *dev)
695 {
696 struct clk *clk;
697 int i;
698 int error;
699
700 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
701
702 error = pm_clk_create(dev);
703 if (error) {
704 dev_err(dev, "pm_clk_create failed %d\n", error);
705 return error;
706 }
707
708 i = 0;
709 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
710 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
711 error = pm_clk_add_clk(dev, clk);
712 if (error) {
713 dev_err(dev, "pm_clk_add_clk failed %d\n", error);
714 clk_put(clk);
715 pm_clk_destroy(dev);
716 return error;
717 }
718 }
719
720 return 0;
721 }
722
rockchip_pd_detach_dev(struct generic_pm_domain * genpd,struct device * dev)723 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
724 struct device *dev)
725 {
726 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
727
728 pm_clk_destroy(dev);
729 }
730
rockchip_pm_add_one_domain(struct rockchip_pmu * pmu,struct device_node * node)731 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
732 struct device_node *node)
733 {
734 const struct rockchip_domain_info *pd_info;
735 struct rockchip_pm_domain *pd;
736 struct device_node *qos_node;
737 int i, j;
738 u32 id;
739 int error;
740
741 error = of_property_read_u32(node, "reg", &id);
742 if (error) {
743 dev_err(pmu->dev,
744 "%pOFn: failed to retrieve domain id (reg): %d\n",
745 node, error);
746 return -EINVAL;
747 }
748
749 if (id >= pmu->info->num_domains) {
750 dev_err(pmu->dev, "%pOFn: invalid domain id %d\n",
751 node, id);
752 return -EINVAL;
753 }
754 /* RK3588 has domains with two parents (RKVDEC0/RKVDEC1) */
755 if (pmu->genpd_data.domains[id])
756 return 0;
757
758 pd_info = &pmu->info->domain_info[id];
759 if (!pd_info) {
760 dev_err(pmu->dev, "%pOFn: undefined domain id %d\n",
761 node, id);
762 return -EINVAL;
763 }
764
765 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL);
766 if (!pd)
767 return -ENOMEM;
768
769 pd->info = pd_info;
770 pd->pmu = pmu;
771 pd->node = node;
772
773 pd->num_clks = of_clk_get_parent_count(node);
774 if (pd->num_clks > 0) {
775 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
776 sizeof(*pd->clks), GFP_KERNEL);
777 if (!pd->clks)
778 return -ENOMEM;
779 } else {
780 dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n",
781 node, pd->num_clks);
782 pd->num_clks = 0;
783 }
784
785 for (i = 0; i < pd->num_clks; i++) {
786 pd->clks[i].clk = of_clk_get(node, i);
787 if (IS_ERR(pd->clks[i].clk)) {
788 error = PTR_ERR(pd->clks[i].clk);
789 dev_err(pmu->dev,
790 "%pOFn: failed to get clk at index %d: %d\n",
791 node, i, error);
792 return error;
793 }
794 }
795
796 error = clk_bulk_prepare(pd->num_clks, pd->clks);
797 if (error)
798 goto err_put_clocks;
799
800 pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
801 NULL);
802
803 if (pd->num_qos > 0) {
804 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
805 sizeof(*pd->qos_regmap),
806 GFP_KERNEL);
807 if (!pd->qos_regmap) {
808 error = -ENOMEM;
809 goto err_unprepare_clocks;
810 }
811
812 for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
813 pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
814 pd->num_qos,
815 sizeof(u32),
816 GFP_KERNEL);
817 if (!pd->qos_save_regs[j]) {
818 error = -ENOMEM;
819 goto err_unprepare_clocks;
820 }
821 }
822
823 for (j = 0; j < pd->num_qos; j++) {
824 qos_node = of_parse_phandle(node, "pm_qos", j);
825 if (!qos_node) {
826 error = -ENODEV;
827 goto err_unprepare_clocks;
828 }
829 pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
830 of_node_put(qos_node);
831 if (IS_ERR(pd->qos_regmap[j])) {
832 error = -ENODEV;
833 goto err_unprepare_clocks;
834 }
835 }
836 }
837
838 if (pd->info->name)
839 pd->genpd.name = pd->info->name;
840 else
841 pd->genpd.name = kbasename(node->full_name);
842 pd->genpd.power_off = rockchip_pd_power_off;
843 pd->genpd.power_on = rockchip_pd_power_on;
844 pd->genpd.attach_dev = rockchip_pd_attach_dev;
845 pd->genpd.detach_dev = rockchip_pd_detach_dev;
846 pd->genpd.flags = GENPD_FLAG_PM_CLK;
847 if (pd_info->active_wakeup)
848 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
849 pm_genpd_init(&pd->genpd, NULL,
850 !rockchip_pmu_domain_is_on(pd) ||
851 (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd)));
852
853 pmu->genpd_data.domains[id] = &pd->genpd;
854 return 0;
855
856 err_unprepare_clocks:
857 clk_bulk_unprepare(pd->num_clks, pd->clks);
858 err_put_clocks:
859 clk_bulk_put(pd->num_clks, pd->clks);
860 return error;
861 }
862
rockchip_pm_remove_one_domain(struct rockchip_pm_domain * pd)863 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
864 {
865 int ret;
866
867 /*
868 * We're in the error cleanup already, so we only complain,
869 * but won't emit another error on top of the original one.
870 */
871 ret = pm_genpd_remove(&pd->genpd);
872 if (ret < 0)
873 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n",
874 pd->genpd.name, ret);
875
876 clk_bulk_unprepare(pd->num_clks, pd->clks);
877 clk_bulk_put(pd->num_clks, pd->clks);
878
879 /* protect the zeroing of pm->num_clks */
880 mutex_lock(&pd->pmu->mutex);
881 pd->num_clks = 0;
882 mutex_unlock(&pd->pmu->mutex);
883
884 /* devm will free our memory */
885 }
886
rockchip_pm_domain_cleanup(struct rockchip_pmu * pmu)887 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
888 {
889 struct generic_pm_domain *genpd;
890 struct rockchip_pm_domain *pd;
891 int i;
892
893 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
894 genpd = pmu->genpd_data.domains[i];
895 if (genpd) {
896 pd = to_rockchip_pd(genpd);
897 rockchip_pm_remove_one_domain(pd);
898 }
899 }
900
901 /* devm will free our memory */
902 }
903
rockchip_configure_pd_cnt(struct rockchip_pmu * pmu,u32 domain_reg_offset,unsigned int count)904 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
905 u32 domain_reg_offset,
906 unsigned int count)
907 {
908 /* First configure domain power down transition count ... */
909 regmap_write(pmu->regmap, domain_reg_offset, count);
910 /* ... and then power up count. */
911 regmap_write(pmu->regmap, domain_reg_offset + 4, count);
912 }
913
rockchip_pm_add_subdomain(struct rockchip_pmu * pmu,struct device_node * parent)914 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
915 struct device_node *parent)
916 {
917 struct generic_pm_domain *child_domain, *parent_domain;
918 int error;
919
920 for_each_child_of_node_scoped(parent, np) {
921 u32 idx;
922
923 error = of_property_read_u32(parent, "reg", &idx);
924 if (error) {
925 dev_err(pmu->dev,
926 "%pOFn: failed to retrieve domain id (reg): %d\n",
927 parent, error);
928 return error;
929 }
930 parent_domain = pmu->genpd_data.domains[idx];
931
932 error = rockchip_pm_add_one_domain(pmu, np);
933 if (error) {
934 dev_err(pmu->dev, "failed to handle node %pOFn: %d\n",
935 np, error);
936 return error;
937 }
938
939 error = of_property_read_u32(np, "reg", &idx);
940 if (error) {
941 dev_err(pmu->dev,
942 "%pOFn: failed to retrieve domain id (reg): %d\n",
943 np, error);
944 return error;
945 }
946 child_domain = pmu->genpd_data.domains[idx];
947
948 error = pm_genpd_add_subdomain(parent_domain, child_domain);
949 if (error) {
950 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
951 parent_domain->name, child_domain->name, error);
952 return error;
953 } else {
954 dev_dbg(pmu->dev, "%s add subdomain: %s\n",
955 parent_domain->name, child_domain->name);
956 }
957
958 rockchip_pm_add_subdomain(pmu, np);
959 }
960
961 return 0;
962 }
963
rockchip_pm_domain_probe(struct platform_device * pdev)964 static int rockchip_pm_domain_probe(struct platform_device *pdev)
965 {
966 struct device *dev = &pdev->dev;
967 struct device_node *np = dev->of_node;
968 struct device *parent;
969 struct rockchip_pmu *pmu;
970 const struct rockchip_pmu_info *pmu_info;
971 int error;
972
973 if (!np) {
974 dev_err(dev, "device tree node not found\n");
975 return -ENODEV;
976 }
977
978 pmu_info = device_get_match_data(dev);
979
980 pmu = devm_kzalloc(dev,
981 struct_size(pmu, domains, pmu_info->num_domains),
982 GFP_KERNEL);
983 if (!pmu)
984 return -ENOMEM;
985
986 pmu->dev = &pdev->dev;
987 mutex_init(&pmu->mutex);
988
989 pmu->info = pmu_info;
990
991 pmu->genpd_data.domains = pmu->domains;
992 pmu->genpd_data.num_domains = pmu_info->num_domains;
993
994 parent = dev->parent;
995 if (!parent) {
996 dev_err(dev, "no parent for syscon devices\n");
997 return -ENODEV;
998 }
999
1000 pmu->regmap = syscon_node_to_regmap(parent->of_node);
1001 if (IS_ERR(pmu->regmap)) {
1002 dev_err(dev, "no regmap available\n");
1003 return PTR_ERR(pmu->regmap);
1004 }
1005
1006 /*
1007 * Configure power up and down transition delays for CORE
1008 * and GPU domains.
1009 */
1010 if (pmu_info->core_power_transition_time)
1011 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
1012 pmu_info->core_power_transition_time);
1013 if (pmu_info->gpu_pwrcnt_offset)
1014 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
1015 pmu_info->gpu_power_transition_time);
1016
1017 error = -ENODEV;
1018
1019 /*
1020 * Prevent any rockchip_pmu_block() from racing with the remainder of
1021 * setup (clocks, register initialization).
1022 */
1023 guard(mutex)(&dmc_pmu_mutex);
1024
1025 for_each_available_child_of_node_scoped(np, node) {
1026 error = rockchip_pm_add_one_domain(pmu, node);
1027 if (error) {
1028 dev_err(dev, "failed to handle node %pOFn: %d\n",
1029 node, error);
1030 goto err_out;
1031 }
1032
1033 error = rockchip_pm_add_subdomain(pmu, node);
1034 if (error < 0) {
1035 dev_err(dev, "failed to handle subdomain node %pOFn: %d\n",
1036 node, error);
1037 goto err_out;
1038 }
1039 }
1040
1041 if (error) {
1042 dev_dbg(dev, "no power domains defined\n");
1043 goto err_out;
1044 }
1045
1046 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
1047 if (error) {
1048 dev_err(dev, "failed to add provider: %d\n", error);
1049 goto err_out;
1050 }
1051
1052 /* We only expect one PMU. */
1053 if (!WARN_ON_ONCE(dmc_pmu))
1054 dmc_pmu = pmu;
1055
1056 return 0;
1057
1058 err_out:
1059 rockchip_pm_domain_cleanup(pmu);
1060 return error;
1061 }
1062
1063 static const struct rockchip_domain_info px30_pm_domains[] = {
1064 [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false),
1065 [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false),
1066 [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false),
1067 [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false),
1068 [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false),
1069 [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false),
1070 [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false),
1071 [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
1072 };
1073
1074 static const struct rockchip_domain_info rv1126_pm_domains[] = {
1075 [RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false),
1076 [RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false),
1077 [RV1126_PD_VO] = DOMAIN_RV1126("vo", BIT(5), BIT(7), BIT(7), false),
1078 [RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false),
1079 [RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
1080 [RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false),
1081 [RV1126_PD_SDIO] = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13), false),
1082 [RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), false),
1083 };
1084
1085 static const struct rockchip_domain_info rk3036_pm_domains[] = {
1086 [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
1087 [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
1088 [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false),
1089 [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false),
1090 [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false),
1091 [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false),
1092 [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false),
1093 };
1094
1095 static const struct rockchip_domain_info rk3066_pm_domains[] = {
1096 [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
1097 [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
1098 [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
1099 [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
1100 [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false),
1101 };
1102
1103 static const struct rockchip_domain_info rk3128_pm_domains[] = {
1104 [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false),
1105 [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true),
1106 [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false),
1107 [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
1108 [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false),
1109 };
1110
1111 static const struct rockchip_domain_info rk3188_pm_domains[] = {
1112 [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
1113 [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
1114 [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
1115 [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
1116 [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false),
1117 };
1118
1119 static const struct rockchip_domain_info rk3228_pm_domains[] = {
1120 [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true),
1121 [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true),
1122 [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true),
1123 [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true),
1124 [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false),
1125 [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false),
1126 [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false),
1127 [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false),
1128 [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false),
1129 [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true),
1130 [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false),
1131 };
1132
1133 static const struct rockchip_domain_info rk3288_pm_domains[] = {
1134 [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false),
1135 [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false),
1136 [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false),
1137 [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false),
1138 };
1139
1140 static const struct rockchip_domain_info rk3328_pm_domains[] = {
1141 [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false),
1142 [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false),
1143 [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true),
1144 [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true),
1145 [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true),
1146 [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
1147 [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false),
1148 [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false),
1149 [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false),
1150 };
1151
1152 static const struct rockchip_domain_info rk3366_pm_domains[] = {
1153 [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true),
1154 [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false),
1155 [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false),
1156 [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false),
1157 [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false),
1158 [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false),
1159 [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false),
1160 };
1161
1162 static const struct rockchip_domain_info rk3368_pm_domains[] = {
1163 [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true),
1164 [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false),
1165 [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false),
1166 [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false),
1167 [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false),
1168 };
1169
1170 static const struct rockchip_domain_info rk3399_pm_domains[] = {
1171 [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false),
1172 [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false),
1173 [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true),
1174 [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true),
1175 [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true),
1176 [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true),
1177 [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true),
1178 [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true),
1179 [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false),
1180 [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false),
1181 [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false),
1182 [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false),
1183 [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false),
1184 [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false),
1185 [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false),
1186 [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false),
1187 [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false),
1188 [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false),
1189 [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false),
1190 [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false),
1191 [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true),
1192 [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true),
1193 [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true),
1194 [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false),
1195 [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true),
1196 [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true),
1197 [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
1198 };
1199
1200 static const struct rockchip_domain_info rk3568_pm_domains[] = {
1201 [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
1202 [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
1203 [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false),
1204 [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false),
1205 [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false),
1206 [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false),
1207 [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false),
1208 [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false),
1209 [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
1210 };
1211
1212 static const struct rockchip_domain_info rk3576_pm_domains[] = {
1213 [RK3576_PD_NPU] = DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, 0x0, 0, 0, 0, false),
1214 [RK3576_PD_NVM] = DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6), 0x4, BIT(2), BIT(18), BIT(2), false),
1215 [RK3576_PD_SDGMAC] = DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(7), 0x4, BIT(1), BIT(17), 0x6, false),
1216 [RK3576_PD_AUDIO] = DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8), 0x4, BIT(0), BIT(16), BIT(0), false),
1217 [RK3576_PD_PHP] = DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9), 0x0, BIT(15), BIT(15), BIT(15), false),
1218 [RK3576_PD_SUBPHP] = DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(10), 0x0, 0, 0, 0, false),
1219 [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, false),
1220 [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, false),
1221 [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, false),
1222 [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, true),
1223 [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), false),
1224 [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, false),
1225 [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), false),
1226 [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), false),
1227 [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), false),
1228 [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, 0x18, false),
1229 [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, false),
1230 [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, false),
1231 [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false),
1232 };
1233
1234 static const struct rockchip_domain_info rk3588_pm_domains[] = {
1235 [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false, true),
1236 [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false, true),
1237 [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false, false),
1238 [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false, false),
1239 [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false, false),
1240 [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false, false),
1241 [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false, false),
1242 [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false, false),
1243 [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false, false),
1244 [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false, false),
1245 [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false, false),
1246 [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false, false),
1247 [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false, false),
1248 [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false, false),
1249 [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false, false),
1250 [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false, false),
1251 [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false, false),
1252 [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false, false),
1253 [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false, false),
1254 [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false, false),
1255 [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false, false),
1256 [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false, false),
1257 [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false, false),
1258 [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true, false),
1259 [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false, false),
1260 [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false, false),
1261 [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false, false),
1262 [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true, false),
1263 [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false, false),
1264 };
1265
1266 static const struct rockchip_pmu_info px30_pmu = {
1267 .pwr_offset = 0x18,
1268 .status_offset = 0x20,
1269 .req_offset = 0x64,
1270 .idle_offset = 0x6c,
1271 .ack_offset = 0x6c,
1272
1273 .num_domains = ARRAY_SIZE(px30_pm_domains),
1274 .domain_info = px30_pm_domains,
1275 };
1276
1277 static const struct rockchip_pmu_info rk3036_pmu = {
1278 .req_offset = 0x148,
1279 .idle_offset = 0x14c,
1280 .ack_offset = 0x14c,
1281
1282 .num_domains = ARRAY_SIZE(rk3036_pm_domains),
1283 .domain_info = rk3036_pm_domains,
1284 };
1285
1286 static const struct rockchip_pmu_info rk3066_pmu = {
1287 .pwr_offset = 0x08,
1288 .status_offset = 0x0c,
1289 .req_offset = 0x38, /* PMU_MISC_CON1 */
1290 .idle_offset = 0x0c,
1291 .ack_offset = 0x0c,
1292
1293 .num_domains = ARRAY_SIZE(rk3066_pm_domains),
1294 .domain_info = rk3066_pm_domains,
1295 };
1296
1297 static const struct rockchip_pmu_info rk3128_pmu = {
1298 .pwr_offset = 0x04,
1299 .status_offset = 0x08,
1300 .req_offset = 0x0c,
1301 .idle_offset = 0x10,
1302 .ack_offset = 0x10,
1303
1304 .num_domains = ARRAY_SIZE(rk3128_pm_domains),
1305 .domain_info = rk3128_pm_domains,
1306 };
1307
1308 static const struct rockchip_pmu_info rk3188_pmu = {
1309 .pwr_offset = 0x08,
1310 .status_offset = 0x0c,
1311 .req_offset = 0x38, /* PMU_MISC_CON1 */
1312 .idle_offset = 0x0c,
1313 .ack_offset = 0x0c,
1314
1315 .num_domains = ARRAY_SIZE(rk3188_pm_domains),
1316 .domain_info = rk3188_pm_domains,
1317 };
1318
1319 static const struct rockchip_pmu_info rk3228_pmu = {
1320 .req_offset = 0x40c,
1321 .idle_offset = 0x488,
1322 .ack_offset = 0x488,
1323
1324 .num_domains = ARRAY_SIZE(rk3228_pm_domains),
1325 .domain_info = rk3228_pm_domains,
1326 };
1327
1328 static const struct rockchip_pmu_info rk3288_pmu = {
1329 .pwr_offset = 0x08,
1330 .status_offset = 0x0c,
1331 .req_offset = 0x10,
1332 .idle_offset = 0x14,
1333 .ack_offset = 0x14,
1334
1335 .core_pwrcnt_offset = 0x34,
1336 .gpu_pwrcnt_offset = 0x3c,
1337
1338 .core_power_transition_time = 24, /* 1us */
1339 .gpu_power_transition_time = 24, /* 1us */
1340
1341 .num_domains = ARRAY_SIZE(rk3288_pm_domains),
1342 .domain_info = rk3288_pm_domains,
1343 };
1344
1345 static const struct rockchip_pmu_info rk3328_pmu = {
1346 .req_offset = 0x414,
1347 .idle_offset = 0x484,
1348 .ack_offset = 0x484,
1349
1350 .num_domains = ARRAY_SIZE(rk3328_pm_domains),
1351 .domain_info = rk3328_pm_domains,
1352 };
1353
1354 static const struct rockchip_pmu_info rk3366_pmu = {
1355 .pwr_offset = 0x0c,
1356 .status_offset = 0x10,
1357 .req_offset = 0x3c,
1358 .idle_offset = 0x40,
1359 .ack_offset = 0x40,
1360
1361 .core_pwrcnt_offset = 0x48,
1362 .gpu_pwrcnt_offset = 0x50,
1363
1364 .core_power_transition_time = 24,
1365 .gpu_power_transition_time = 24,
1366
1367 .num_domains = ARRAY_SIZE(rk3366_pm_domains),
1368 .domain_info = rk3366_pm_domains,
1369 };
1370
1371 static const struct rockchip_pmu_info rk3368_pmu = {
1372 .pwr_offset = 0x0c,
1373 .status_offset = 0x10,
1374 .req_offset = 0x3c,
1375 .idle_offset = 0x40,
1376 .ack_offset = 0x40,
1377
1378 .core_pwrcnt_offset = 0x48,
1379 .gpu_pwrcnt_offset = 0x50,
1380
1381 .core_power_transition_time = 24,
1382 .gpu_power_transition_time = 24,
1383
1384 .num_domains = ARRAY_SIZE(rk3368_pm_domains),
1385 .domain_info = rk3368_pm_domains,
1386 };
1387
1388 static const struct rockchip_pmu_info rk3399_pmu = {
1389 .pwr_offset = 0x14,
1390 .status_offset = 0x18,
1391 .req_offset = 0x60,
1392 .idle_offset = 0x64,
1393 .ack_offset = 0x68,
1394
1395 /* ARM Trusted Firmware manages power transition times */
1396
1397 .num_domains = ARRAY_SIZE(rk3399_pm_domains),
1398 .domain_info = rk3399_pm_domains,
1399 };
1400
1401 static const struct rockchip_pmu_info rk3568_pmu = {
1402 .pwr_offset = 0xa0,
1403 .status_offset = 0x98,
1404 .req_offset = 0x50,
1405 .idle_offset = 0x68,
1406 .ack_offset = 0x60,
1407
1408 .num_domains = ARRAY_SIZE(rk3568_pm_domains),
1409 .domain_info = rk3568_pm_domains,
1410 };
1411
1412 static const struct rockchip_pmu_info rk3576_pmu = {
1413 .pwr_offset = 0x210,
1414 .status_offset = 0x230,
1415 .chain_status_offset = 0x248,
1416 .mem_status_offset = 0x250,
1417 .mem_pwr_offset = 0x300,
1418 .req_offset = 0x110,
1419 .idle_offset = 0x128,
1420 .ack_offset = 0x120,
1421 .repair_status_offset = 0x570,
1422 .clk_ungate_offset = 0x140,
1423
1424 .num_domains = ARRAY_SIZE(rk3576_pm_domains),
1425 .domain_info = rk3576_pm_domains,
1426 };
1427
1428 static const struct rockchip_pmu_info rk3588_pmu = {
1429 .pwr_offset = 0x14c,
1430 .status_offset = 0x180,
1431 .req_offset = 0x10c,
1432 .idle_offset = 0x120,
1433 .ack_offset = 0x118,
1434 .mem_pwr_offset = 0x1a0,
1435 .chain_status_offset = 0x1f0,
1436 .mem_status_offset = 0x1f8,
1437 .repair_status_offset = 0x290,
1438
1439 .num_domains = ARRAY_SIZE(rk3588_pm_domains),
1440 .domain_info = rk3588_pm_domains,
1441 };
1442
1443 static const struct rockchip_pmu_info rv1126_pmu = {
1444 .pwr_offset = 0x110,
1445 .status_offset = 0x108,
1446 .req_offset = 0xc0,
1447 .idle_offset = 0xd8,
1448 .ack_offset = 0xd0,
1449
1450 .num_domains = ARRAY_SIZE(rv1126_pm_domains),
1451 .domain_info = rv1126_pm_domains,
1452 };
1453
1454 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
1455 {
1456 .compatible = "rockchip,px30-power-controller",
1457 .data = (void *)&px30_pmu,
1458 },
1459 {
1460 .compatible = "rockchip,rk3036-power-controller",
1461 .data = (void *)&rk3036_pmu,
1462 },
1463 {
1464 .compatible = "rockchip,rk3066-power-controller",
1465 .data = (void *)&rk3066_pmu,
1466 },
1467 {
1468 .compatible = "rockchip,rk3128-power-controller",
1469 .data = (void *)&rk3128_pmu,
1470 },
1471 {
1472 .compatible = "rockchip,rk3188-power-controller",
1473 .data = (void *)&rk3188_pmu,
1474 },
1475 {
1476 .compatible = "rockchip,rk3228-power-controller",
1477 .data = (void *)&rk3228_pmu,
1478 },
1479 {
1480 .compatible = "rockchip,rk3288-power-controller",
1481 .data = (void *)&rk3288_pmu,
1482 },
1483 {
1484 .compatible = "rockchip,rk3328-power-controller",
1485 .data = (void *)&rk3328_pmu,
1486 },
1487 {
1488 .compatible = "rockchip,rk3366-power-controller",
1489 .data = (void *)&rk3366_pmu,
1490 },
1491 {
1492 .compatible = "rockchip,rk3368-power-controller",
1493 .data = (void *)&rk3368_pmu,
1494 },
1495 {
1496 .compatible = "rockchip,rk3399-power-controller",
1497 .data = (void *)&rk3399_pmu,
1498 },
1499 {
1500 .compatible = "rockchip,rk3568-power-controller",
1501 .data = (void *)&rk3568_pmu,
1502 },
1503 {
1504 .compatible = "rockchip,rk3576-power-controller",
1505 .data = (void *)&rk3576_pmu,
1506 },
1507 {
1508 .compatible = "rockchip,rk3588-power-controller",
1509 .data = (void *)&rk3588_pmu,
1510 },
1511 {
1512 .compatible = "rockchip,rv1126-power-controller",
1513 .data = (void *)&rv1126_pmu,
1514 },
1515 { /* sentinel */ },
1516 };
1517
1518 static struct platform_driver rockchip_pm_domain_driver = {
1519 .probe = rockchip_pm_domain_probe,
1520 .driver = {
1521 .name = "rockchip-pm-domain",
1522 .of_match_table = rockchip_pm_domain_dt_match,
1523 /*
1524 * We can't forcibly eject devices from the power
1525 * domain, so we can't really remove power domains
1526 * once they were added.
1527 */
1528 .suppress_bind_attrs = true,
1529 },
1530 };
1531
rockchip_pm_domain_drv_register(void)1532 static int __init rockchip_pm_domain_drv_register(void)
1533 {
1534 return platform_driver_register(&rockchip_pm_domain_driver);
1535 }
1536 postcore_initcall(rockchip_pm_domain_drv_register);
1537