1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /**************************************************************************
3 *
4 * Copyright 2009-2023 VMware, Inc., Palo Alto, CA., USA
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include "vmwgfx_drv.h"
30
31 #include "vmwgfx_bo.h"
32 #include "vmwgfx_binding.h"
33 #include "vmwgfx_devcaps.h"
34 #include "vmwgfx_mksstat.h"
35 #include "vmwgfx_vkms.h"
36 #include "ttm_object.h"
37
38 #include <drm/clients/drm_client_setup.h>
39 #include <drm/drm_drv.h>
40 #include <drm/drm_fbdev_ttm.h>
41 #include <drm/drm_gem_ttm_helper.h>
42 #include <drm/drm_ioctl.h>
43 #include <drm/drm_module.h>
44 #include <drm/drm_sysfs.h>
45 #include <drm/ttm/ttm_range_manager.h>
46 #include <drm/ttm/ttm_placement.h>
47 #include <generated/utsrelease.h>
48
49 #ifdef CONFIG_X86
50 #include <asm/hypervisor.h>
51 #endif
52
53 #include <linux/aperture.h>
54 #include <linux/cc_platform.h>
55 #include <linux/dma-mapping.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/version.h>
59 #include <linux/vmalloc.h>
60
61 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
62
63 /*
64 * Fully encoded drm commands. Might move to vmw_drm.h
65 */
66
67 #define DRM_IOCTL_VMW_GET_PARAM \
68 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
69 struct drm_vmw_getparam_arg)
70 #define DRM_IOCTL_VMW_ALLOC_DMABUF \
71 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
72 union drm_vmw_alloc_dmabuf_arg)
73 #define DRM_IOCTL_VMW_UNREF_DMABUF \
74 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
75 struct drm_vmw_unref_dmabuf_arg)
76 #define DRM_IOCTL_VMW_CURSOR_BYPASS \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
78 struct drm_vmw_cursor_bypass_arg)
79
80 #define DRM_IOCTL_VMW_CONTROL_STREAM \
81 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
82 struct drm_vmw_control_stream_arg)
83 #define DRM_IOCTL_VMW_CLAIM_STREAM \
84 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
85 struct drm_vmw_stream_arg)
86 #define DRM_IOCTL_VMW_UNREF_STREAM \
87 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
88 struct drm_vmw_stream_arg)
89
90 #define DRM_IOCTL_VMW_CREATE_CONTEXT \
91 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
92 struct drm_vmw_context_arg)
93 #define DRM_IOCTL_VMW_UNREF_CONTEXT \
94 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
95 struct drm_vmw_context_arg)
96 #define DRM_IOCTL_VMW_CREATE_SURFACE \
97 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
98 union drm_vmw_surface_create_arg)
99 #define DRM_IOCTL_VMW_UNREF_SURFACE \
100 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
101 struct drm_vmw_surface_arg)
102 #define DRM_IOCTL_VMW_REF_SURFACE \
103 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
104 union drm_vmw_surface_reference_arg)
105 #define DRM_IOCTL_VMW_EXECBUF \
106 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
107 struct drm_vmw_execbuf_arg)
108 #define DRM_IOCTL_VMW_GET_3D_CAP \
109 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
110 struct drm_vmw_get_3d_cap_arg)
111 #define DRM_IOCTL_VMW_FENCE_WAIT \
112 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
113 struct drm_vmw_fence_wait_arg)
114 #define DRM_IOCTL_VMW_FENCE_SIGNALED \
115 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
116 struct drm_vmw_fence_signaled_arg)
117 #define DRM_IOCTL_VMW_FENCE_UNREF \
118 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
119 struct drm_vmw_fence_arg)
120 #define DRM_IOCTL_VMW_FENCE_EVENT \
121 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
122 struct drm_vmw_fence_event_arg)
123 #define DRM_IOCTL_VMW_PRESENT \
124 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
125 struct drm_vmw_present_arg)
126 #define DRM_IOCTL_VMW_PRESENT_READBACK \
127 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
128 struct drm_vmw_present_readback_arg)
129 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \
130 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
131 struct drm_vmw_update_layout_arg)
132 #define DRM_IOCTL_VMW_CREATE_SHADER \
133 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
134 struct drm_vmw_shader_create_arg)
135 #define DRM_IOCTL_VMW_UNREF_SHADER \
136 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
137 struct drm_vmw_shader_arg)
138 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
139 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
140 union drm_vmw_gb_surface_create_arg)
141 #define DRM_IOCTL_VMW_GB_SURFACE_REF \
142 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
143 union drm_vmw_gb_surface_reference_arg)
144 #define DRM_IOCTL_VMW_SYNCCPU \
145 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
146 struct drm_vmw_synccpu_arg)
147 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
148 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
149 struct drm_vmw_context_arg)
150 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \
151 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \
152 union drm_vmw_gb_surface_create_ext_arg)
153 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \
154 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \
155 union drm_vmw_gb_surface_reference_ext_arg)
156 #define DRM_IOCTL_VMW_MSG \
157 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \
158 struct drm_vmw_msg_arg)
159 #define DRM_IOCTL_VMW_MKSSTAT_RESET \
160 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET)
161 #define DRM_IOCTL_VMW_MKSSTAT_ADD \
162 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \
163 struct drm_vmw_mksstat_add_arg)
164 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \
165 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \
166 struct drm_vmw_mksstat_remove_arg)
167
168 /*
169 * Ioctl definitions.
170 */
171
172 static const struct drm_ioctl_desc vmw_ioctls[] = {
173 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl,
174 DRM_RENDER_ALLOW),
175 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl,
176 DRM_RENDER_ALLOW),
177 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl,
178 DRM_RENDER_ALLOW),
179 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS,
180 vmw_kms_cursor_bypass_ioctl,
181 DRM_MASTER),
182
183 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
184 DRM_MASTER),
185 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
186 DRM_MASTER),
187 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
188 DRM_MASTER),
189
190 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
191 DRM_RENDER_ALLOW),
192 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
193 DRM_RENDER_ALLOW),
194 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
195 DRM_RENDER_ALLOW),
196 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
197 DRM_RENDER_ALLOW),
198 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
199 DRM_RENDER_ALLOW),
200 DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl,
201 DRM_RENDER_ALLOW),
202 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
203 DRM_RENDER_ALLOW),
204 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED,
205 vmw_fence_obj_signaled_ioctl,
206 DRM_RENDER_ALLOW),
207 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
208 DRM_RENDER_ALLOW),
209 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
210 DRM_RENDER_ALLOW),
211 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
212 DRM_RENDER_ALLOW),
213
214 /* these allow direct access to the framebuffers mark as master only */
215 DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl,
216 DRM_MASTER | DRM_AUTH),
217 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK,
218 vmw_present_readback_ioctl,
219 DRM_MASTER | DRM_AUTH),
220 /*
221 * The permissions of the below ioctl are overridden in
222 * vmw_generic_ioctl(). We require either
223 * DRM_MASTER or capable(CAP_SYS_ADMIN).
224 */
225 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT,
226 vmw_kms_update_layout_ioctl,
227 DRM_RENDER_ALLOW),
228 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER,
229 vmw_shader_define_ioctl,
230 DRM_RENDER_ALLOW),
231 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER,
232 vmw_shader_destroy_ioctl,
233 DRM_RENDER_ALLOW),
234 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE,
235 vmw_gb_surface_define_ioctl,
236 DRM_RENDER_ALLOW),
237 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF,
238 vmw_gb_surface_reference_ioctl,
239 DRM_RENDER_ALLOW),
240 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU,
241 vmw_user_bo_synccpu_ioctl,
242 DRM_RENDER_ALLOW),
243 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT,
244 vmw_extended_context_define_ioctl,
245 DRM_RENDER_ALLOW),
246 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT,
247 vmw_gb_surface_define_ext_ioctl,
248 DRM_RENDER_ALLOW),
249 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT,
250 vmw_gb_surface_reference_ext_ioctl,
251 DRM_RENDER_ALLOW),
252 DRM_IOCTL_DEF_DRV(VMW_MSG,
253 vmw_msg_ioctl,
254 DRM_RENDER_ALLOW),
255 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET,
256 vmw_mksstat_reset_ioctl,
257 DRM_RENDER_ALLOW),
258 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD,
259 vmw_mksstat_add_ioctl,
260 DRM_RENDER_ALLOW),
261 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE,
262 vmw_mksstat_remove_ioctl,
263 DRM_RENDER_ALLOW),
264 };
265
266 static const struct pci_device_id vmw_pci_id_list[] = {
267 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) },
268 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) },
269 { }
270 };
271 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
272
273 static int vmw_restrict_iommu;
274 static int vmw_force_coherent;
275 static int vmw_restrict_dma_mask;
276 static int vmw_assume_16bpp;
277
278 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
279 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
280 void *ptr);
281
282 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
283 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
284 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
285 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
286 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
287 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
288 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
289 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
290
291
292 struct bitmap_name {
293 uint32 value;
294 const char *name;
295 };
296
297 static const struct bitmap_name cap1_names[] = {
298 { SVGA_CAP_RECT_COPY, "rect copy" },
299 { SVGA_CAP_CURSOR, "cursor" },
300 { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" },
301 { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" },
302 { SVGA_CAP_8BIT_EMULATION, "8bit emulation" },
303 { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" },
304 { SVGA_CAP_3D, "3D" },
305 { SVGA_CAP_EXTENDED_FIFO, "extended fifo" },
306 { SVGA_CAP_MULTIMON, "multimon" },
307 { SVGA_CAP_PITCHLOCK, "pitchlock" },
308 { SVGA_CAP_IRQMASK, "irq mask" },
309 { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" },
310 { SVGA_CAP_GMR, "gmr" },
311 { SVGA_CAP_TRACES, "traces" },
312 { SVGA_CAP_GMR2, "gmr2" },
313 { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" },
314 { SVGA_CAP_COMMAND_BUFFERS, "command buffers" },
315 { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" },
316 { SVGA_CAP_GBOBJECTS, "gbobject" },
317 { SVGA_CAP_DX, "dx" },
318 { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" },
319 { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" },
320 { SVGA_CAP_CAP2_REGISTER, "cap2 register" },
321 };
322
323
324 static const struct bitmap_name cap2_names[] = {
325 { SVGA_CAP2_GROW_OTABLE, "grow otable" },
326 { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" },
327 { SVGA_CAP2_DX2, "dx2" },
328 { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" },
329 { SVGA_CAP2_SCREENDMA_REG, "screendma reg" },
330 { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" },
331 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" },
332 { SVGA_CAP2_CURSOR_MOB, "cursor mob" },
333 { SVGA_CAP2_MSHINT, "mshint" },
334 { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" },
335 { SVGA_CAP2_DX3, "dx3" },
336 { SVGA_CAP2_FRAME_TYPE, "frame type" },
337 { SVGA_CAP2_COTABLE_COPY, "cotable copy" },
338 { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" },
339 { SVGA_CAP2_EXTRA_REGS, "extra regs" },
340 { SVGA_CAP2_LO_STAGING, "lo staging" },
341 };
342
vmw_print_bitmap(struct drm_device * drm,const char * prefix,uint32_t bitmap,const struct bitmap_name * bnames,uint32_t num_names)343 static void vmw_print_bitmap(struct drm_device *drm,
344 const char *prefix, uint32_t bitmap,
345 const struct bitmap_name *bnames,
346 uint32_t num_names)
347 {
348 char buf[512];
349 uint32_t i;
350 uint32_t offset = 0;
351 for (i = 0; i < num_names; ++i) {
352 if ((bitmap & bnames[i].value) != 0) {
353 offset += snprintf(buf + offset,
354 ARRAY_SIZE(buf) - offset,
355 "%s, ", bnames[i].name);
356 bitmap &= ~bnames[i].value;
357 }
358 }
359
360 drm_info(drm, "%s: %s\n", prefix, buf);
361 if (bitmap != 0)
362 drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap);
363 }
364
365
vmw_print_sm_type(struct vmw_private * dev_priv)366 static void vmw_print_sm_type(struct vmw_private *dev_priv)
367 {
368 static const char *names[] = {
369 [VMW_SM_LEGACY] = "Legacy",
370 [VMW_SM_4] = "SM4",
371 [VMW_SM_4_1] = "SM4_1",
372 [VMW_SM_5] = "SM_5",
373 [VMW_SM_5_1X] = "SM_5_1X",
374 [VMW_SM_MAX] = "Invalid"
375 };
376 BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1));
377 drm_info(&dev_priv->drm, "Available shader model: %s.\n",
378 names[dev_priv->sm_type]);
379 }
380
381 /**
382 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
383 *
384 * @dev_priv: A device private structure.
385 *
386 * This function creates a small buffer object that holds the query
387 * result for dummy queries emitted as query barriers.
388 * The function will then map the first page and initialize a pending
389 * occlusion query result structure, Finally it will unmap the buffer.
390 * No interruptible waits are done within this function.
391 *
392 * Returns an error if bo creation or initialization fails.
393 */
vmw_dummy_query_bo_create(struct vmw_private * dev_priv)394 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
395 {
396 int ret;
397 struct vmw_bo *vbo;
398 struct ttm_bo_kmap_obj map;
399 volatile SVGA3dQueryResult *result;
400 bool dummy;
401 struct vmw_bo_params bo_params = {
402 .domain = VMW_BO_DOMAIN_SYS,
403 .busy_domain = VMW_BO_DOMAIN_SYS,
404 .bo_type = ttm_bo_type_kernel,
405 .size = PAGE_SIZE,
406 .pin = true,
407 .keep_resv = true,
408 };
409
410 /*
411 * Create the vbo as pinned, so that a tryreserve will
412 * immediately succeed. This is because we're the only
413 * user of the bo currently.
414 */
415 ret = vmw_bo_create(dev_priv, &bo_params, &vbo);
416 if (unlikely(ret != 0))
417 return ret;
418
419 ret = ttm_bo_kmap(&vbo->tbo, 0, 1, &map);
420 if (likely(ret == 0)) {
421 result = ttm_kmap_obj_virtual(&map, &dummy);
422 result->totalSize = sizeof(*result);
423 result->state = SVGA3D_QUERYSTATE_PENDING;
424 result->result32 = 0xff;
425 ttm_bo_kunmap(&map);
426 }
427 vmw_bo_pin_reserved(vbo, false);
428 ttm_bo_unreserve(&vbo->tbo);
429
430 if (unlikely(ret != 0)) {
431 DRM_ERROR("Dummy query buffer map failed.\n");
432 vmw_bo_unreference(&vbo);
433 } else
434 dev_priv->dummy_query_bo = vbo;
435
436 return ret;
437 }
438
vmw_device_init(struct vmw_private * dev_priv)439 static int vmw_device_init(struct vmw_private *dev_priv)
440 {
441 bool uses_fb_traces = false;
442
443 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
444 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
445 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
446
447 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |
448 SVGA_REG_ENABLE_HIDE);
449
450 uses_fb_traces = !vmw_cmd_supported(dev_priv) &&
451 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0;
452
453 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces);
454 dev_priv->fifo = vmw_fifo_create(dev_priv);
455 if (IS_ERR(dev_priv->fifo)) {
456 int err = PTR_ERR(dev_priv->fifo);
457 dev_priv->fifo = NULL;
458 return err;
459 } else if (!dev_priv->fifo) {
460 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
461 }
462
463 dev_priv->last_read_seqno = vmw_fence_read(dev_priv);
464 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
465 return 0;
466 }
467
vmw_device_fini(struct vmw_private * vmw)468 static void vmw_device_fini(struct vmw_private *vmw)
469 {
470 /*
471 * Legacy sync
472 */
473 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
474 while (vmw_read(vmw, SVGA_REG_BUSY) != 0)
475 ;
476
477 vmw->last_read_seqno = vmw_fence_read(vmw);
478
479 vmw_write(vmw, SVGA_REG_CONFIG_DONE,
480 vmw->config_done_state);
481 vmw_write(vmw, SVGA_REG_ENABLE,
482 vmw->enable_state);
483 vmw_write(vmw, SVGA_REG_TRACES,
484 vmw->traces_state);
485
486 vmw_fifo_destroy(vmw);
487 }
488
489 /**
490 * vmw_request_device_late - Perform late device setup
491 *
492 * @dev_priv: Pointer to device private.
493 *
494 * This function performs setup of otables and enables large command
495 * buffer submission. These tasks are split out to a separate function
496 * because it reverts vmw_release_device_early and is intended to be used
497 * by an error path in the hibernation code.
498 */
vmw_request_device_late(struct vmw_private * dev_priv)499 static int vmw_request_device_late(struct vmw_private *dev_priv)
500 {
501 int ret;
502
503 if (dev_priv->has_mob) {
504 ret = vmw_otables_setup(dev_priv);
505 if (unlikely(ret != 0)) {
506 DRM_ERROR("Unable to initialize "
507 "guest Memory OBjects.\n");
508 return ret;
509 }
510 }
511
512 if (dev_priv->cman) {
513 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096);
514 if (ret) {
515 struct vmw_cmdbuf_man *man = dev_priv->cman;
516
517 dev_priv->cman = NULL;
518 vmw_cmdbuf_man_destroy(man);
519 }
520 }
521
522 return 0;
523 }
524
vmw_request_device(struct vmw_private * dev_priv)525 static int vmw_request_device(struct vmw_private *dev_priv)
526 {
527 int ret;
528
529 ret = vmw_device_init(dev_priv);
530 if (unlikely(ret != 0)) {
531 DRM_ERROR("Unable to initialize the device.\n");
532 return ret;
533 }
534 vmw_fence_fifo_up(dev_priv->fman);
535 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
536 if (IS_ERR(dev_priv->cman)) {
537 dev_priv->cman = NULL;
538 dev_priv->sm_type = VMW_SM_LEGACY;
539 }
540
541 ret = vmw_request_device_late(dev_priv);
542 if (ret)
543 goto out_no_mob;
544
545 ret = vmw_dummy_query_bo_create(dev_priv);
546 if (unlikely(ret != 0))
547 goto out_no_query_bo;
548
549 return 0;
550
551 out_no_query_bo:
552 if (dev_priv->cman)
553 vmw_cmdbuf_remove_pool(dev_priv->cman);
554 if (dev_priv->has_mob) {
555 struct ttm_resource_manager *man;
556
557 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);
558 ttm_resource_manager_evict_all(&dev_priv->bdev, man);
559 vmw_otables_takedown(dev_priv);
560 }
561 if (dev_priv->cman)
562 vmw_cmdbuf_man_destroy(dev_priv->cman);
563 out_no_mob:
564 vmw_fence_fifo_down(dev_priv->fman);
565 vmw_device_fini(dev_priv);
566 return ret;
567 }
568
569 /**
570 * vmw_release_device_early - Early part of fifo takedown.
571 *
572 * @dev_priv: Pointer to device private struct.
573 *
574 * This is the first part of command submission takedown, to be called before
575 * buffer management is taken down.
576 */
vmw_release_device_early(struct vmw_private * dev_priv)577 static void vmw_release_device_early(struct vmw_private *dev_priv)
578 {
579 /*
580 * Previous destructions should've released
581 * the pinned bo.
582 */
583
584 BUG_ON(dev_priv->pinned_bo != NULL);
585
586 vmw_bo_unreference(&dev_priv->dummy_query_bo);
587 if (dev_priv->cman)
588 vmw_cmdbuf_remove_pool(dev_priv->cman);
589
590 if (dev_priv->has_mob) {
591 struct ttm_resource_manager *man;
592
593 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);
594 ttm_resource_manager_evict_all(&dev_priv->bdev, man);
595 vmw_otables_takedown(dev_priv);
596 }
597 }
598
599 /**
600 * vmw_release_device_late - Late part of fifo takedown.
601 *
602 * @dev_priv: Pointer to device private struct.
603 *
604 * This is the last part of the command submission takedown, to be called when
605 * command submission is no longer needed. It may wait on pending fences.
606 */
vmw_release_device_late(struct vmw_private * dev_priv)607 static void vmw_release_device_late(struct vmw_private *dev_priv)
608 {
609 vmw_fence_fifo_down(dev_priv->fman);
610 if (dev_priv->cman)
611 vmw_cmdbuf_man_destroy(dev_priv->cman);
612
613 vmw_device_fini(dev_priv);
614 }
615
616 /*
617 * Sets the initial_[width|height] fields on the given vmw_private.
618 *
619 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
620 * clamping the value to fb_max_[width|height] fields and the
621 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
622 * If the values appear to be invalid, set them to
623 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
624 */
vmw_get_initial_size(struct vmw_private * dev_priv)625 static void vmw_get_initial_size(struct vmw_private *dev_priv)
626 {
627 uint32_t width;
628 uint32_t height;
629
630 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
631 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
632
633 width = max_t(uint32_t, width, VMWGFX_MIN_INITIAL_WIDTH);
634 height = max_t(uint32_t, height, VMWGFX_MIN_INITIAL_HEIGHT);
635
636 if (width > dev_priv->fb_max_width ||
637 height > dev_priv->fb_max_height) {
638
639 /*
640 * This is a host error and shouldn't occur.
641 */
642
643 width = VMWGFX_MIN_INITIAL_WIDTH;
644 height = VMWGFX_MIN_INITIAL_HEIGHT;
645 }
646
647 dev_priv->initial_width = width;
648 dev_priv->initial_height = height;
649 }
650
651 /**
652 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
653 * system.
654 *
655 * @dev_priv: Pointer to a struct vmw_private
656 *
657 * This functions tries to determine what actions need to be taken by the
658 * driver to make system pages visible to the device.
659 * If this function decides that DMA is not possible, it returns -EINVAL.
660 * The driver may then try to disable features of the device that require
661 * DMA.
662 */
vmw_dma_select_mode(struct vmw_private * dev_priv)663 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
664 {
665 static const char *names[vmw_dma_map_max] = {
666 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
667 [vmw_dma_map_populate] = "Caching DMA mappings.",
668 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
669
670 /*
671 * When running with SEV we always want dma mappings, because
672 * otherwise ttm tt pool pages will bounce through swiotlb running
673 * out of available space.
674 */
675 if (vmw_force_coherent || cc_platform_has(CC_ATTR_MEM_ENCRYPT))
676 dev_priv->map_mode = vmw_dma_alloc_coherent;
677 else if (vmw_restrict_iommu)
678 dev_priv->map_mode = vmw_dma_map_bind;
679 else
680 dev_priv->map_mode = vmw_dma_map_populate;
681
682 drm_info(&dev_priv->drm,
683 "DMA map mode: %s\n", names[dev_priv->map_mode]);
684 return 0;
685 }
686
687 /**
688 * vmw_dma_masks - set required page- and dma masks
689 *
690 * @dev_priv: Pointer to struct drm-device
691 *
692 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
693 * restriction also for 64-bit systems.
694 */
vmw_dma_masks(struct vmw_private * dev_priv)695 static int vmw_dma_masks(struct vmw_private *dev_priv)
696 {
697 struct drm_device *dev = &dev_priv->drm;
698 int ret = 0;
699
700 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64));
701 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) {
702 drm_info(&dev_priv->drm,
703 "Restricting DMA addresses to 44 bits.\n");
704 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44));
705 }
706
707 return ret;
708 }
709
vmw_vram_manager_init(struct vmw_private * dev_priv)710 static int vmw_vram_manager_init(struct vmw_private *dev_priv)
711 {
712 int ret;
713 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false,
714 dev_priv->vram_size >> PAGE_SHIFT);
715 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false);
716 return ret;
717 }
718
vmw_vram_manager_fini(struct vmw_private * dev_priv)719 static void vmw_vram_manager_fini(struct vmw_private *dev_priv)
720 {
721 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM);
722 }
723
vmw_setup_pci_resources(struct vmw_private * dev,u32 pci_id)724 static int vmw_setup_pci_resources(struct vmw_private *dev,
725 u32 pci_id)
726 {
727 resource_size_t rmmio_start;
728 resource_size_t rmmio_size;
729 resource_size_t fifo_start;
730 resource_size_t fifo_size;
731 int ret;
732 struct pci_dev *pdev = to_pci_dev(dev->drm.dev);
733
734 pci_set_master(pdev);
735
736 ret = pci_request_regions(pdev, "vmwgfx probe");
737 if (ret)
738 return ret;
739
740 dev->pci_id = pci_id;
741 if (pci_id == VMWGFX_PCI_ID_SVGA3) {
742 rmmio_start = pci_resource_start(pdev, 0);
743 rmmio_size = pci_resource_len(pdev, 0);
744 dev->vram_start = pci_resource_start(pdev, 2);
745 dev->vram_size = pci_resource_len(pdev, 2);
746
747 drm_info(&dev->drm,
748 "Register MMIO at 0x%pa size is %llu KiB\n",
749 &rmmio_start, (uint64_t)rmmio_size / 1024);
750 dev->rmmio = devm_ioremap(dev->drm.dev,
751 rmmio_start,
752 rmmio_size);
753 if (!dev->rmmio) {
754 drm_err(&dev->drm,
755 "Failed mapping registers mmio memory.\n");
756 pci_release_regions(pdev);
757 return -ENOMEM;
758 }
759 } else if (pci_id == VMWGFX_PCI_ID_SVGA2) {
760 dev->io_start = pci_resource_start(pdev, 0);
761 dev->vram_start = pci_resource_start(pdev, 1);
762 dev->vram_size = pci_resource_len(pdev, 1);
763 fifo_start = pci_resource_start(pdev, 2);
764 fifo_size = pci_resource_len(pdev, 2);
765
766 drm_info(&dev->drm,
767 "FIFO at %pa size is %llu KiB\n",
768 &fifo_start, (uint64_t)fifo_size / 1024);
769 dev->fifo_mem = devm_memremap(dev->drm.dev,
770 fifo_start,
771 fifo_size,
772 MEMREMAP_WB);
773
774 if (IS_ERR(dev->fifo_mem)) {
775 drm_err(&dev->drm,
776 "Failed mapping FIFO memory.\n");
777 pci_release_regions(pdev);
778 return PTR_ERR(dev->fifo_mem);
779 }
780 } else {
781 pci_release_regions(pdev);
782 return -EINVAL;
783 }
784
785 /*
786 * This is approximate size of the vram, the exact size will only
787 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource
788 * size will be equal to or bigger than the size reported by
789 * SVGA_REG_VRAM_SIZE.
790 */
791 drm_info(&dev->drm,
792 "VRAM at %pa size is %llu KiB\n",
793 &dev->vram_start, (uint64_t)dev->vram_size / 1024);
794
795 return 0;
796 }
797
vmw_detect_version(struct vmw_private * dev)798 static int vmw_detect_version(struct vmw_private *dev)
799 {
800 uint32_t svga_id;
801
802 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ?
803 SVGA_ID_3 : SVGA_ID_2);
804 svga_id = vmw_read(dev, SVGA_REG_ID);
805 if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) {
806 drm_err(&dev->drm,
807 "Unsupported SVGA ID 0x%x on chipset 0x%x\n",
808 svga_id, dev->pci_id);
809 return -ENOSYS;
810 }
811 BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3));
812 drm_info(&dev->drm,
813 "Running on SVGA version %d.\n", (svga_id & 0xff));
814 return 0;
815 }
816
vmw_write_driver_id(struct vmw_private * dev)817 static void vmw_write_driver_id(struct vmw_private *dev)
818 {
819 if ((dev->capabilities2 & SVGA_CAP2_DX2) != 0) {
820 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID,
821 SVGA_REG_GUEST_DRIVER_ID_LINUX);
822
823 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION1,
824 LINUX_VERSION_MAJOR << 24 |
825 LINUX_VERSION_PATCHLEVEL << 16 |
826 LINUX_VERSION_SUBLEVEL);
827 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION2,
828 VMWGFX_DRIVER_MAJOR << 24 |
829 VMWGFX_DRIVER_MINOR << 16 |
830 VMWGFX_DRIVER_PATCHLEVEL);
831 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION3, 0);
832
833 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID,
834 SVGA_REG_GUEST_DRIVER_ID_SUBMIT);
835 }
836 }
837
vmw_sw_context_init(struct vmw_private * dev_priv)838 static void vmw_sw_context_init(struct vmw_private *dev_priv)
839 {
840 struct vmw_sw_context *sw_context = &dev_priv->ctx;
841
842 hash_init(sw_context->res_ht);
843 }
844
vmw_sw_context_fini(struct vmw_private * dev_priv)845 static void vmw_sw_context_fini(struct vmw_private *dev_priv)
846 {
847 struct vmw_sw_context *sw_context = &dev_priv->ctx;
848
849 vfree(sw_context->cmd_bounce);
850 if (sw_context->staged_bindings)
851 vmw_binding_state_free(sw_context->staged_bindings);
852 }
853
vmw_driver_load(struct vmw_private * dev_priv,u32 pci_id)854 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
855 {
856 int ret;
857 enum vmw_res_type i;
858 bool refuse_dma = false;
859 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
860
861 vmw_sw_context_init(dev_priv);
862
863 mutex_init(&dev_priv->cmdbuf_mutex);
864 mutex_init(&dev_priv->binding_mutex);
865 spin_lock_init(&dev_priv->resource_lock);
866 spin_lock_init(&dev_priv->hw_lock);
867 spin_lock_init(&dev_priv->waiter_lock);
868 spin_lock_init(&dev_priv->cursor_lock);
869
870 ret = vmw_setup_pci_resources(dev_priv, pci_id);
871 if (ret)
872 return ret;
873 ret = vmw_detect_version(dev_priv);
874 if (ret)
875 goto out_no_pci_or_version;
876
877
878 for (i = vmw_res_context; i < vmw_res_max; ++i) {
879 idr_init_base(&dev_priv->res_idr[i], 1);
880 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
881 }
882
883 init_waitqueue_head(&dev_priv->fence_queue);
884 init_waitqueue_head(&dev_priv->fifo_queue);
885 dev_priv->fence_queue_waiters = 0;
886 dev_priv->fifo_queue_waiters = 0;
887
888 dev_priv->used_memory_size = 0;
889
890 dev_priv->assume_16bpp = !!vmw_assume_16bpp;
891
892 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
893 vmw_print_bitmap(&dev_priv->drm, "Capabilities",
894 dev_priv->capabilities,
895 cap1_names, ARRAY_SIZE(cap1_names));
896 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {
897 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);
898 vmw_print_bitmap(&dev_priv->drm, "Capabilities2",
899 dev_priv->capabilities2,
900 cap2_names, ARRAY_SIZE(cap2_names));
901 }
902
903 if (!vmwgfx_supported(dev_priv)) {
904 vmw_disable_backdoor();
905 drm_err_once(&dev_priv->drm,
906 "vmwgfx seems to be running on an unsupported hypervisor.");
907 drm_err_once(&dev_priv->drm,
908 "This configuration is likely broken.");
909 drm_err_once(&dev_priv->drm,
910 "Please switch to a supported graphics device to avoid problems.");
911 }
912
913 vmw_vkms_init(dev_priv);
914
915 ret = vmw_dma_select_mode(dev_priv);
916 if (unlikely(ret != 0)) {
917 drm_info(&dev_priv->drm,
918 "Restricting capabilities since DMA not available.\n");
919 refuse_dma = true;
920 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS)
921 drm_info(&dev_priv->drm,
922 "Disabling 3D acceleration.\n");
923 }
924
925 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
926 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
927 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
928 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
929
930 vmw_get_initial_size(dev_priv);
931
932 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
933 dev_priv->max_gmr_ids =
934 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
935 dev_priv->max_gmr_pages =
936 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
937 dev_priv->memory_size =
938 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
939 dev_priv->memory_size -= dev_priv->vram_size;
940 } else {
941 /*
942 * An arbitrary limit of 512MiB on surface
943 * memory. But all HWV8 hardware supports GMR2.
944 */
945 dev_priv->memory_size = 512*1024*1024;
946 }
947 dev_priv->max_mob_pages = 0;
948 dev_priv->max_mob_size = 0;
949 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
950 uint64_t mem_size;
951
952 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2)
953 mem_size = vmw_read(dev_priv,
954 SVGA_REG_GBOBJECT_MEM_SIZE_KB);
955 else
956 mem_size =
957 vmw_read(dev_priv,
958 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
959
960 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
961 dev_priv->max_primary_mem =
962 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM);
963 dev_priv->max_mob_size =
964 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
965 dev_priv->stdu_max_width =
966 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
967 dev_priv->stdu_max_height =
968 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
969
970 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
971 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
972 dev_priv->texture_max_width = vmw_read(dev_priv,
973 SVGA_REG_DEV_CAP);
974 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
975 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
976 dev_priv->texture_max_height = vmw_read(dev_priv,
977 SVGA_REG_DEV_CAP);
978 } else {
979 dev_priv->texture_max_width = 8192;
980 dev_priv->texture_max_height = 8192;
981 dev_priv->max_primary_mem = dev_priv->vram_size;
982 }
983 drm_info(&dev_priv->drm,
984 "Legacy memory limits: VRAM = %llu KiB, FIFO = %llu KiB, surface = %u KiB\n",
985 (u64)dev_priv->vram_size / 1024,
986 (u64)dev_priv->fifo_mem_size / 1024,
987 dev_priv->memory_size / 1024);
988
989 drm_info(&dev_priv->drm,
990 "MOB limits: max mob size = %u KiB, max mob pages = %u\n",
991 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages);
992
993 ret = vmw_dma_masks(dev_priv);
994 if (unlikely(ret != 0))
995 goto out_err0;
996
997 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX);
998
999 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
1000 drm_info(&dev_priv->drm,
1001 "Max GMR ids is %u\n",
1002 (unsigned)dev_priv->max_gmr_ids);
1003 drm_info(&dev_priv->drm,
1004 "Max number of GMR pages is %u\n",
1005 (unsigned)dev_priv->max_gmr_pages);
1006 }
1007 drm_info(&dev_priv->drm,
1008 "Maximum display memory size is %llu KiB\n",
1009 (uint64_t)dev_priv->max_primary_mem / 1024);
1010
1011 /* Need mmio memory to check for fifo pitchlock cap. */
1012 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
1013 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
1014 !vmw_fifo_have_pitchlock(dev_priv)) {
1015 ret = -ENOSYS;
1016 DRM_ERROR("Hardware has no pitchlock\n");
1017 goto out_err0;
1018 }
1019
1020 dev_priv->tdev = ttm_object_device_init(&vmw_prime_dmabuf_ops);
1021
1022 if (unlikely(dev_priv->tdev == NULL)) {
1023 drm_err(&dev_priv->drm,
1024 "Unable to initialize TTM object management.\n");
1025 ret = -ENOMEM;
1026 goto out_err0;
1027 }
1028
1029 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
1030 ret = vmw_irq_install(dev_priv);
1031 if (ret != 0) {
1032 drm_err(&dev_priv->drm,
1033 "Failed installing irq: %d\n", ret);
1034 goto out_no_irq;
1035 }
1036 }
1037
1038 dev_priv->fman = vmw_fence_manager_init(dev_priv);
1039 if (unlikely(dev_priv->fman == NULL)) {
1040 ret = -ENOMEM;
1041 goto out_no_fman;
1042 }
1043
1044 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver,
1045 dev_priv->drm.dev,
1046 dev_priv->drm.anon_inode->i_mapping,
1047 dev_priv->drm.vma_offset_manager,
1048 dev_priv->map_mode == vmw_dma_alloc_coherent,
1049 false);
1050 if (unlikely(ret != 0)) {
1051 drm_err(&dev_priv->drm,
1052 "Failed initializing TTM buffer object driver.\n");
1053 goto out_no_bdev;
1054 }
1055
1056 /*
1057 * Enable VRAM, but initially don't use it until SVGA is enabled and
1058 * unhidden.
1059 */
1060
1061 ret = vmw_vram_manager_init(dev_priv);
1062 if (unlikely(ret != 0)) {
1063 drm_err(&dev_priv->drm,
1064 "Failed initializing memory manager for VRAM.\n");
1065 goto out_no_vram;
1066 }
1067
1068 ret = vmw_devcaps_create(dev_priv);
1069 if (unlikely(ret != 0)) {
1070 drm_err(&dev_priv->drm,
1071 "Failed initializing device caps.\n");
1072 goto out_no_vram;
1073 }
1074
1075 /*
1076 * "Guest Memory Regions" is an aperture like feature with
1077 * one slot per bo. There is an upper limit of the number of
1078 * slots as well as the bo size.
1079 */
1080 dev_priv->has_gmr = true;
1081 /* TODO: This is most likely not correct */
1082 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
1083 refuse_dma ||
1084 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) {
1085 drm_info(&dev_priv->drm,
1086 "No GMR memory available. "
1087 "Graphics memory resources are very limited.\n");
1088 dev_priv->has_gmr = false;
1089 }
1090
1091 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) {
1092 dev_priv->has_mob = true;
1093
1094 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) {
1095 drm_info(&dev_priv->drm,
1096 "No MOB memory available. "
1097 "3D will be disabled.\n");
1098 dev_priv->has_mob = false;
1099 }
1100 if (vmw_sys_man_init(dev_priv) != 0) {
1101 drm_info(&dev_priv->drm,
1102 "No MOB page table memory available. "
1103 "3D will be disabled.\n");
1104 dev_priv->has_mob = false;
1105 }
1106 }
1107
1108 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) {
1109 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT))
1110 dev_priv->sm_type = VMW_SM_4;
1111 }
1112
1113 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */
1114 if (has_sm4_context(dev_priv) &&
1115 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) {
1116 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41))
1117 dev_priv->sm_type = VMW_SM_4_1;
1118 if (has_sm4_1_context(dev_priv) &&
1119 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) {
1120 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) {
1121 dev_priv->sm_type = VMW_SM_5;
1122 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43))
1123 dev_priv->sm_type = VMW_SM_5_1X;
1124 }
1125 }
1126 }
1127
1128 ret = vmw_kms_init(dev_priv);
1129 if (unlikely(ret != 0))
1130 goto out_no_kms;
1131 vmw_overlay_init(dev_priv);
1132
1133 ret = vmw_request_device(dev_priv);
1134 if (ret)
1135 goto out_no_fifo;
1136
1137 vmw_print_sm_type(dev_priv);
1138 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)",
1139 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
1140 VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE);
1141 vmw_write_driver_id(dev_priv);
1142
1143 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
1144 register_pm_notifier(&dev_priv->pm_nb);
1145
1146 return 0;
1147
1148 out_no_fifo:
1149 vmw_overlay_close(dev_priv);
1150 vmw_kms_close(dev_priv);
1151 out_no_kms:
1152 if (dev_priv->has_mob) {
1153 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
1154 vmw_sys_man_fini(dev_priv);
1155 }
1156 if (dev_priv->has_gmr)
1157 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
1158 vmw_devcaps_destroy(dev_priv);
1159 vmw_vram_manager_fini(dev_priv);
1160 out_no_vram:
1161 ttm_device_fini(&dev_priv->bdev);
1162 out_no_bdev:
1163 vmw_fence_manager_takedown(dev_priv->fman);
1164 out_no_fman:
1165 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1166 vmw_irq_uninstall(&dev_priv->drm);
1167 out_no_irq:
1168 ttm_object_device_release(&dev_priv->tdev);
1169 out_err0:
1170 for (i = vmw_res_context; i < vmw_res_max; ++i)
1171 idr_destroy(&dev_priv->res_idr[i]);
1172
1173 if (dev_priv->ctx.staged_bindings)
1174 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1175 out_no_pci_or_version:
1176 pci_release_regions(pdev);
1177 return ret;
1178 }
1179
vmw_driver_unload(struct drm_device * dev)1180 static void vmw_driver_unload(struct drm_device *dev)
1181 {
1182 struct vmw_private *dev_priv = vmw_priv(dev);
1183 struct pci_dev *pdev = to_pci_dev(dev->dev);
1184 enum vmw_res_type i;
1185
1186 unregister_pm_notifier(&dev_priv->pm_nb);
1187
1188 vmw_sw_context_fini(dev_priv);
1189 vmw_fifo_resource_dec(dev_priv);
1190
1191 vmw_svga_disable(dev_priv);
1192
1193 vmw_vkms_cleanup(dev_priv);
1194 vmw_kms_close(dev_priv);
1195 vmw_overlay_close(dev_priv);
1196
1197 if (dev_priv->has_gmr)
1198 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
1199
1200 vmw_release_device_early(dev_priv);
1201 if (dev_priv->has_mob) {
1202 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
1203 vmw_sys_man_fini(dev_priv);
1204 }
1205 vmw_devcaps_destroy(dev_priv);
1206 vmw_vram_manager_fini(dev_priv);
1207 ttm_device_fini(&dev_priv->bdev);
1208 vmw_release_device_late(dev_priv);
1209 vmw_fence_manager_takedown(dev_priv->fman);
1210 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1211 vmw_irq_uninstall(&dev_priv->drm);
1212
1213 ttm_object_device_release(&dev_priv->tdev);
1214
1215 for (i = vmw_res_context; i < vmw_res_max; ++i)
1216 idr_destroy(&dev_priv->res_idr[i]);
1217
1218 vmw_mksstat_remove_all(dev_priv);
1219
1220 pci_release_regions(pdev);
1221 }
1222
vmw_postclose(struct drm_device * dev,struct drm_file * file_priv)1223 static void vmw_postclose(struct drm_device *dev,
1224 struct drm_file *file_priv)
1225 {
1226 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1227
1228 ttm_object_file_release(&vmw_fp->tfile);
1229 kfree(vmw_fp);
1230 }
1231
vmw_driver_open(struct drm_device * dev,struct drm_file * file_priv)1232 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1233 {
1234 struct vmw_private *dev_priv = vmw_priv(dev);
1235 struct vmw_fpriv *vmw_fp;
1236 int ret = -ENOMEM;
1237
1238 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1239 if (unlikely(!vmw_fp))
1240 return ret;
1241
1242 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev);
1243 if (unlikely(vmw_fp->tfile == NULL))
1244 goto out_no_tfile;
1245
1246 file_priv->driver_priv = vmw_fp;
1247
1248 return 0;
1249
1250 out_no_tfile:
1251 kfree(vmw_fp);
1252 return ret;
1253 }
1254
vmw_generic_ioctl(struct file * filp,unsigned int cmd,unsigned long arg,long (* ioctl_func)(struct file *,unsigned int,unsigned long))1255 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1256 unsigned long arg,
1257 long (*ioctl_func)(struct file *, unsigned int,
1258 unsigned long))
1259 {
1260 struct drm_file *file_priv = filp->private_data;
1261 struct drm_device *dev = file_priv->minor->dev;
1262 unsigned int nr = DRM_IOCTL_NR(cmd);
1263 unsigned int flags;
1264
1265 /*
1266 * Do extra checking on driver private ioctls.
1267 */
1268
1269 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1270 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1271 const struct drm_ioctl_desc *ioctl =
1272 &vmw_ioctls[nr - DRM_COMMAND_BASE];
1273
1274 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1275 return ioctl_func(filp, cmd, arg);
1276 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) {
1277 if (!drm_is_current_master(file_priv) &&
1278 !capable(CAP_SYS_ADMIN))
1279 return -EACCES;
1280 }
1281
1282 if (unlikely(ioctl->cmd != cmd))
1283 goto out_io_encoding;
1284
1285 flags = ioctl->flags;
1286 } else if (!drm_ioctl_flags(nr, &flags))
1287 return -EINVAL;
1288
1289 return ioctl_func(filp, cmd, arg);
1290
1291 out_io_encoding:
1292 DRM_ERROR("Invalid command format, ioctl %d\n",
1293 nr - DRM_COMMAND_BASE);
1294
1295 return -EINVAL;
1296 }
1297
vmw_unlocked_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)1298 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1299 unsigned long arg)
1300 {
1301 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1302 }
1303
1304 #ifdef CONFIG_COMPAT
vmw_compat_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)1305 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1306 unsigned long arg)
1307 {
1308 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1309 }
1310 #endif
1311
vmw_master_set(struct drm_device * dev,struct drm_file * file_priv,bool from_open)1312 static void vmw_master_set(struct drm_device *dev,
1313 struct drm_file *file_priv,
1314 bool from_open)
1315 {
1316 /*
1317 * Inform a new master that the layout may have changed while
1318 * it was gone.
1319 */
1320 if (!from_open)
1321 drm_sysfs_hotplug_event(dev);
1322 }
1323
vmw_master_drop(struct drm_device * dev,struct drm_file * file_priv)1324 static void vmw_master_drop(struct drm_device *dev,
1325 struct drm_file *file_priv)
1326 {
1327 struct vmw_private *dev_priv = vmw_priv(dev);
1328
1329 vmw_kms_legacy_hotspot_clear(dev_priv);
1330 }
1331
vmwgfx_supported(struct vmw_private * vmw)1332 bool vmwgfx_supported(struct vmw_private *vmw)
1333 {
1334 #if defined(CONFIG_X86)
1335 return hypervisor_is_type(X86_HYPER_VMWARE);
1336 #elif defined(CONFIG_ARM64)
1337 /*
1338 * On aarch64 only svga3 is supported
1339 */
1340 return vmw->pci_id == VMWGFX_PCI_ID_SVGA3;
1341 #else
1342 drm_warn_once(&vmw->drm,
1343 "vmwgfx is running on an unknown architecture.");
1344 return false;
1345 #endif
1346 }
1347
1348 /**
1349 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1350 *
1351 * @dev_priv: Pointer to device private struct.
1352 * Needs the reservation sem to be held in non-exclusive mode.
1353 */
__vmw_svga_enable(struct vmw_private * dev_priv)1354 static void __vmw_svga_enable(struct vmw_private *dev_priv)
1355 {
1356 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1357
1358 if (!ttm_resource_manager_used(man)) {
1359 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE);
1360 ttm_resource_manager_set_used(man, true);
1361 }
1362 }
1363
1364 /**
1365 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1366 *
1367 * @dev_priv: Pointer to device private struct.
1368 */
vmw_svga_enable(struct vmw_private * dev_priv)1369 void vmw_svga_enable(struct vmw_private *dev_priv)
1370 {
1371 __vmw_svga_enable(dev_priv);
1372 }
1373
1374 /**
1375 * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1376 *
1377 * @dev_priv: Pointer to device private struct.
1378 * Needs the reservation sem to be held in exclusive mode.
1379 * Will not empty VRAM. VRAM must be emptied by caller.
1380 */
__vmw_svga_disable(struct vmw_private * dev_priv)1381 static void __vmw_svga_disable(struct vmw_private *dev_priv)
1382 {
1383 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1384
1385 if (ttm_resource_manager_used(man)) {
1386 ttm_resource_manager_set_used(man, false);
1387 vmw_write(dev_priv, SVGA_REG_ENABLE,
1388 SVGA_REG_ENABLE_HIDE |
1389 SVGA_REG_ENABLE_ENABLE);
1390 }
1391 }
1392
1393 /**
1394 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1395 * running.
1396 *
1397 * @dev_priv: Pointer to device private struct.
1398 * Will empty VRAM.
1399 */
vmw_svga_disable(struct vmw_private * dev_priv)1400 void vmw_svga_disable(struct vmw_private *dev_priv)
1401 {
1402 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1403 /*
1404 * Disabling SVGA will turn off device modesetting capabilities, so
1405 * notify KMS about that so that it doesn't cache atomic state that
1406 * isn't valid anymore, for example crtcs turned on.
1407 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
1408 * but vmw_kms_lost_device() takes the reservation sem and thus we'll
1409 * end up with lock order reversal. Thus, a master may actually perform
1410 * a new modeset just after we call vmw_kms_lost_device() and race with
1411 * vmw_svga_disable(), but that should at worst cause atomic KMS state
1412 * to be inconsistent with the device, causing modesetting problems.
1413 *
1414 */
1415 vmw_kms_lost_device(&dev_priv->drm);
1416 if (ttm_resource_manager_used(man)) {
1417 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man))
1418 DRM_ERROR("Failed evicting VRAM buffers.\n");
1419 ttm_resource_manager_set_used(man, false);
1420 vmw_write(dev_priv, SVGA_REG_ENABLE,
1421 SVGA_REG_ENABLE_HIDE |
1422 SVGA_REG_ENABLE_ENABLE);
1423 }
1424 }
1425
vmw_remove(struct pci_dev * pdev)1426 static void vmw_remove(struct pci_dev *pdev)
1427 {
1428 struct drm_device *dev = pci_get_drvdata(pdev);
1429
1430 drm_dev_unregister(dev);
1431 vmw_driver_unload(dev);
1432 }
1433
vmw_debugfs_resource_managers_init(struct vmw_private * vmw)1434 static void vmw_debugfs_resource_managers_init(struct vmw_private *vmw)
1435 {
1436 struct drm_minor *minor = vmw->drm.primary;
1437 struct dentry *root = minor->debugfs_root;
1438
1439 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_SYSTEM),
1440 root, "system_ttm");
1441 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_VRAM),
1442 root, "vram_ttm");
1443 if (vmw->has_gmr)
1444 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_GMR),
1445 root, "gmr_ttm");
1446 if (vmw->has_mob) {
1447 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_MOB),
1448 root, "mob_ttm");
1449 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_SYSTEM),
1450 root, "system_mob_ttm");
1451 }
1452 }
1453
vmwgfx_pm_notifier(struct notifier_block * nb,unsigned long val,void * ptr)1454 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1455 void *ptr)
1456 {
1457 struct vmw_private *dev_priv =
1458 container_of(nb, struct vmw_private, pm_nb);
1459
1460 switch (val) {
1461 case PM_HIBERNATION_PREPARE:
1462 /*
1463 * Take the reservation sem in write mode, which will make sure
1464 * there are no other processes holding a buffer object
1465 * reservation, meaning we should be able to evict all buffer
1466 * objects if needed.
1467 * Once user-space processes have been frozen, we can release
1468 * the lock again.
1469 */
1470 dev_priv->suspend_locked = true;
1471 break;
1472 case PM_POST_HIBERNATION:
1473 case PM_POST_RESTORE:
1474 if (READ_ONCE(dev_priv->suspend_locked)) {
1475 dev_priv->suspend_locked = false;
1476 }
1477 break;
1478 default:
1479 break;
1480 }
1481 return 0;
1482 }
1483
vmw_pci_suspend(struct pci_dev * pdev,pm_message_t state)1484 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1485 {
1486 struct drm_device *dev = pci_get_drvdata(pdev);
1487 struct vmw_private *dev_priv = vmw_priv(dev);
1488
1489 if (dev_priv->refuse_hibernation)
1490 return -EBUSY;
1491
1492 pci_save_state(pdev);
1493 pci_disable_device(pdev);
1494 pci_set_power_state(pdev, PCI_D3hot);
1495 return 0;
1496 }
1497
vmw_pci_resume(struct pci_dev * pdev)1498 static int vmw_pci_resume(struct pci_dev *pdev)
1499 {
1500 pci_set_power_state(pdev, PCI_D0);
1501 pci_restore_state(pdev);
1502 return pci_enable_device(pdev);
1503 }
1504
vmw_pm_suspend(struct device * kdev)1505 static int vmw_pm_suspend(struct device *kdev)
1506 {
1507 struct pci_dev *pdev = to_pci_dev(kdev);
1508 struct pm_message dummy;
1509
1510 dummy.event = 0;
1511
1512 return vmw_pci_suspend(pdev, dummy);
1513 }
1514
vmw_pm_resume(struct device * kdev)1515 static int vmw_pm_resume(struct device *kdev)
1516 {
1517 struct pci_dev *pdev = to_pci_dev(kdev);
1518
1519 return vmw_pci_resume(pdev);
1520 }
1521
vmw_pm_freeze(struct device * kdev)1522 static int vmw_pm_freeze(struct device *kdev)
1523 {
1524 struct pci_dev *pdev = to_pci_dev(kdev);
1525 struct drm_device *dev = pci_get_drvdata(pdev);
1526 struct vmw_private *dev_priv = vmw_priv(dev);
1527 struct ttm_operation_ctx ctx = {
1528 .interruptible = false,
1529 .no_wait_gpu = false
1530 };
1531 int ret;
1532
1533 /*
1534 * No user-space processes should be running now.
1535 */
1536 ret = vmw_kms_suspend(&dev_priv->drm);
1537 if (ret) {
1538 DRM_ERROR("Failed to freeze modesetting.\n");
1539 return ret;
1540 }
1541
1542 vmw_execbuf_release_pinned_bo(dev_priv);
1543 vmw_resource_evict_all(dev_priv);
1544 vmw_release_device_early(dev_priv);
1545 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0);
1546 vmw_fifo_resource_dec(dev_priv);
1547 if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1548 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1549 vmw_fifo_resource_inc(dev_priv);
1550 WARN_ON(vmw_request_device_late(dev_priv));
1551 dev_priv->suspend_locked = false;
1552 if (dev_priv->suspend_state)
1553 vmw_kms_resume(dev);
1554 return -EBUSY;
1555 }
1556
1557 vmw_fence_fifo_down(dev_priv->fman);
1558 __vmw_svga_disable(dev_priv);
1559
1560 vmw_release_device_late(dev_priv);
1561 return 0;
1562 }
1563
vmw_pm_restore(struct device * kdev)1564 static int vmw_pm_restore(struct device *kdev)
1565 {
1566 struct pci_dev *pdev = to_pci_dev(kdev);
1567 struct drm_device *dev = pci_get_drvdata(pdev);
1568 struct vmw_private *dev_priv = vmw_priv(dev);
1569 int ret;
1570
1571 vmw_detect_version(dev_priv);
1572
1573 vmw_fifo_resource_inc(dev_priv);
1574
1575 ret = vmw_request_device(dev_priv);
1576 if (ret)
1577 return ret;
1578
1579 __vmw_svga_enable(dev_priv);
1580
1581 vmw_fence_fifo_up(dev_priv->fman);
1582 dev_priv->suspend_locked = false;
1583 if (dev_priv->suspend_state)
1584 vmw_kms_resume(&dev_priv->drm);
1585
1586 return 0;
1587 }
1588
1589 static const struct dev_pm_ops vmw_pm_ops = {
1590 .freeze = vmw_pm_freeze,
1591 .thaw = vmw_pm_restore,
1592 .restore = vmw_pm_restore,
1593 .suspend = vmw_pm_suspend,
1594 .resume = vmw_pm_resume,
1595 };
1596
1597 static const struct file_operations vmwgfx_driver_fops = {
1598 .owner = THIS_MODULE,
1599 .open = drm_open,
1600 .release = drm_release,
1601 .unlocked_ioctl = vmw_unlocked_ioctl,
1602 .mmap = drm_gem_mmap,
1603 .poll = drm_poll,
1604 .read = drm_read,
1605 #if defined(CONFIG_COMPAT)
1606 .compat_ioctl = vmw_compat_ioctl,
1607 #endif
1608 .llseek = noop_llseek,
1609 .fop_flags = FOP_UNSIGNED_OFFSET,
1610 };
1611
1612 static const struct drm_driver driver = {
1613 .driver_features =
1614 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM | DRIVER_CURSOR_HOTSPOT,
1615 .ioctls = vmw_ioctls,
1616 .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1617 .master_set = vmw_master_set,
1618 .master_drop = vmw_master_drop,
1619 .open = vmw_driver_open,
1620 .postclose = vmw_postclose,
1621
1622 .dumb_create = vmw_dumb_create,
1623 .dumb_map_offset = drm_gem_ttm_dumb_map_offset,
1624
1625 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1626 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1627 .gem_prime_import_sg_table = vmw_prime_import_sg_table,
1628
1629 DRM_FBDEV_TTM_DRIVER_OPS,
1630
1631 .fops = &vmwgfx_driver_fops,
1632 .name = VMWGFX_DRIVER_NAME,
1633 .desc = VMWGFX_DRIVER_DESC,
1634 .major = VMWGFX_DRIVER_MAJOR,
1635 .minor = VMWGFX_DRIVER_MINOR,
1636 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1637 };
1638
1639 static struct pci_driver vmw_pci_driver = {
1640 .name = VMWGFX_DRIVER_NAME,
1641 .id_table = vmw_pci_id_list,
1642 .probe = vmw_probe,
1643 .remove = vmw_remove,
1644 .driver = {
1645 .pm = &vmw_pm_ops
1646 }
1647 };
1648
vmw_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1649 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1650 {
1651 struct vmw_private *vmw;
1652 int ret;
1653
1654 ret = aperture_remove_conflicting_pci_devices(pdev, driver.name);
1655 if (ret)
1656 goto out_error;
1657
1658 ret = pcim_enable_device(pdev);
1659 if (ret)
1660 goto out_error;
1661
1662 vmw = devm_drm_dev_alloc(&pdev->dev, &driver,
1663 struct vmw_private, drm);
1664 if (IS_ERR(vmw)) {
1665 ret = PTR_ERR(vmw);
1666 goto out_error;
1667 }
1668
1669 pci_set_drvdata(pdev, &vmw->drm);
1670
1671 ret = vmw_driver_load(vmw, ent->device);
1672 if (ret)
1673 goto out_error;
1674
1675 ret = drm_dev_register(&vmw->drm, 0);
1676 if (ret)
1677 goto out_unload;
1678
1679 vmw_fifo_resource_inc(vmw);
1680 vmw_svga_enable(vmw);
1681 drm_client_setup(&vmw->drm, NULL);
1682
1683 vmw_debugfs_gem_init(vmw);
1684 vmw_debugfs_resource_managers_init(vmw);
1685
1686 return 0;
1687 out_unload:
1688 vmw_driver_unload(&vmw->drm);
1689 out_error:
1690 return ret;
1691 }
1692
1693 drm_module_pci_driver(vmw_pci_driver);
1694
1695 MODULE_AUTHOR("VMware Inc. and others");
1696 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1697 MODULE_LICENSE("GPL and additional rights");
1698 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1699 __stringify(VMWGFX_DRIVER_MINOR) "."
1700 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1701 "0");
1702