1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 *
26 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
27 */
28
29 /*
30 * Portions Copyright 2009 Advanced Micro Devices, Inc.
31 */
32
33 /*
34 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
35 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
36 * Copyright 2019 Joyent, Inc.
37 * Copyright 2024 Oxide Computer Company
38 */
39
40 /*
41 * Support functions that interpret CPUID and similar information.
42 * These should not be used from anywhere other than cpuid.c and
43 * cmi_hw.c - as such we will not list them in any header file
44 * such as x86_archext.h.
45 *
46 * In cpuid.c we process CPUID information for each cpu_t instance
47 * we're presented with, and stash this raw information and material
48 * derived from it in per-cpu_t structures.
49 *
50 * If we are virtualized then the CPUID information derived from CPUID
51 * instructions executed in the guest is based on whatever the hypervisor
52 * wanted to make things look like, and the cpu_t are not necessarily in 1:1
53 * or fixed correspondence with real processor execution resources. In cmi_hw.c
54 * we are interested in the native properties of a processor - for fault
55 * management (and potentially other, such as power management) purposes;
56 * it will tunnel through to real hardware information, and use the
57 * functionality provided in this file to process it.
58 */
59
60 #include <sys/types.h>
61 #include <sys/systm.h>
62 #include <sys/bitmap.h>
63 #include <sys/x86_archext.h>
64 #include <sys/pci_cfgspace.h>
65 #include <sys/sysmacros.h>
66 #ifdef __xpv
67 #include <sys/hypervisor.h>
68 #endif
69
70 /*
71 * AMD socket types.
72 * First index defines a processor family; see notes inline. The second index
73 * selects the socket type by either (model & 0x3) for family 0fh or the CPUID
74 * pkg bits (Fn8000_0001_EBX[31:28]) for later families.
75 */
76 static uint32_t amd_skts[][16] = {
77 /*
78 * Family 0xf revisions B through E
79 */
80 #define A_SKTS_0 0
81 {
82 [0] = X86_SOCKET_754,
83 [1] = X86_SOCKET_940,
84 [2] = X86_SOCKET_754,
85 [3] = X86_SOCKET_939,
86 },
87 /*
88 * Family 0xf revisions F and G
89 */
90 #define A_SKTS_1 1
91 {
92 [0] = X86_SOCKET_S1g1,
93 [1] = X86_SOCKET_F1207,
94 [3] = X86_SOCKET_AM2
95 },
96 /*
97 * Family 0x10
98 */
99 #define A_SKTS_2 2
100 {
101 [0] = X86_SOCKET_F1207,
102 [1] = X86_SOCKET_AM2R2,
103 [2] = X86_SOCKET_S1g3,
104 [3] = X86_SOCKET_G34,
105 [4] = X86_SOCKET_ASB2,
106 [5] = X86_SOCKET_C32
107 },
108
109 /*
110 * Family 0x11
111 */
112 #define A_SKTS_3 3
113 {
114 [2] = X86_SOCKET_S1g2
115 },
116
117 /*
118 * Family 0x12
119 */
120 #define A_SKTS_4 4
121 {
122 [1] = X86_SOCKET_FS1,
123 [2] = X86_SOCKET_FM1
124 },
125
126 /*
127 * Family 0x14
128 */
129 #define A_SKTS_5 5
130 {
131 [0] = X86_SOCKET_FT1
132 },
133
134 /*
135 * Family 0x15 models 00 - 0f
136 */
137 #define A_SKTS_6 6
138 {
139 [1] = X86_SOCKET_AM3R2,
140 [3] = X86_SOCKET_G34,
141 [5] = X86_SOCKET_C32
142 },
143
144 /*
145 * Family 0x15 models 10 - 1f
146 */
147 #define A_SKTS_7 7
148 {
149 [0] = X86_SOCKET_FP2,
150 [1] = X86_SOCKET_FS1R2,
151 [2] = X86_SOCKET_FM2
152 },
153
154 /*
155 * Family 0x15 models 30-3f
156 */
157 #define A_SKTS_8 8
158 {
159 [0] = X86_SOCKET_FP3,
160 [1] = X86_SOCKET_FM2R2
161 },
162
163 /*
164 * Family 0x15 models 60-6f
165 */
166 #define A_SKTS_9 9
167 {
168 [0] = X86_SOCKET_FP4,
169 [2] = X86_SOCKET_AM4,
170 [3] = X86_SOCKET_FM2R2
171 },
172
173 /*
174 * Family 0x15 models 70-7f
175 */
176 #define A_SKTS_10 10
177 {
178 [0] = X86_SOCKET_FP4,
179 [2] = X86_SOCKET_AM4,
180 [4] = X86_SOCKET_FT4
181 },
182
183 /*
184 * Family 0x16 models 00-0f
185 */
186 #define A_SKTS_11 11
187 {
188 [0] = X86_SOCKET_FT3,
189 [1] = X86_SOCKET_FS1B
190 },
191
192 /*
193 * Family 0x16 models 30-3f
194 */
195 #define A_SKTS_12 12
196 {
197 [0] = X86_SOCKET_FT3B,
198 [3] = X86_SOCKET_FP4
199 },
200
201 /*
202 * Family 0x17 models 00-0f (Zen 1 - Naples, Ryzen)
203 */
204 #define A_SKTS_NAPLES 13
205 {
206 [2] = X86_SOCKET_AM4,
207 [4] = X86_SOCKET_SP3,
208 [7] = X86_SOCKET_SP3R2
209 },
210
211 /*
212 * Family 0x17 models 10-2f (Zen 1 - APU: Raven Ridge)
213 * (Zen 1 - APU: Banded Kestrel)
214 * (Zen 1 - APU: Dali)
215 */
216 #define A_SKTS_RAVEN 14
217 {
218 [0] = X86_SOCKET_FP5,
219 [2] = X86_SOCKET_AM4
220 },
221
222 /*
223 * Family 0x17 models 30-3f (Zen 2 - Rome)
224 */
225 #define A_SKTS_ROME 15
226 {
227 [4] = X86_SOCKET_SP3,
228 [7] = X86_SOCKET_SP3R2
229 },
230
231 /*
232 * Family 0x17 models 60-6f (Zen 2 - Renoir)
233 */
234 #define A_SKTS_RENOIR 16
235 {
236 [0] = X86_SOCKET_FP6,
237 [2] = X86_SOCKET_AM4
238 },
239
240 /*
241 * Family 0x17 models 70-7f (Zen 2 - Matisse)
242 */
243 #define A_SKTS_MATISSE 17
244 {
245 [2] = X86_SOCKET_AM4,
246 },
247
248 /*
249 * Family 0x18 models 00-0f (Dhyana)
250 */
251 #define A_SKTS_DHYANA 18
252 {
253 [4] = X86_SOCKET_SL1,
254 [6] = X86_SOCKET_DM1,
255 [7] = X86_SOCKET_SL1R2
256 },
257
258 /*
259 * Family 0x19 models 00-0f (Zen 3 - Milan)
260 */
261 #define A_SKTS_MILAN 19
262 {
263 [4] = X86_SOCKET_SP3,
264 [7] = X86_SOCKET_STRX4
265 },
266
267 /*
268 * Family 0x19 models 20-2f (Zen 3 - Vermeer)
269 */
270 #define A_SKTS_VERMEER 20
271 {
272 [2] = X86_SOCKET_AM4,
273 },
274
275 /*
276 * Family 0x19 models 50-5f (Zen 3 - Cezanne)
277 */
278 #define A_SKTS_CEZANNE 21
279 {
280 [0] = X86_SOCKET_FP6,
281 [2] = X86_SOCKET_AM4
282 },
283
284 /*
285 * Family 0x19 models 10-1f (Zen 4 - Genoa)
286 */
287 #define A_SKTS_GENOA 22
288 {
289 [4] = X86_SOCKET_SP5,
290 [8] = X86_SOCKET_TR5
291 },
292
293 /*
294 * Family 0x19 models 40-4f (Zen 3 - Rembrandt)
295 */
296 #define A_SKTS_REMBRANDT 23
297 {
298 [0] = X86_SOCKET_AM5,
299 [1] = X86_SOCKET_FP7,
300 [2] = X86_SOCKET_FP7R2
301 },
302
303 /*
304 * Family 0x19 models 60-6f (Zen 4 - Raphael)
305 */
306 #define A_SKTS_RAPHAEL 24
307 {
308 [0] = X86_SOCKET_AM5,
309 [1] = X86_SOCKET_FL1
310 },
311
312 /*
313 * The always-unknown socket group, used for undocumented parts. It
314 * need not be last; the position is arbitrary. The default initializer
315 * for this is zero which is x86 socket unknown.
316 */
317 #define A_SKTS_UNKNOWN 25
318 {
319 },
320 /*
321 * Family 0x17 models 90-97 (Zen 2 - Van Gogh)
322 */
323 #define A_SKTS_VANGOGH 26
324 {
325 [3] = X86_SOCKET_FF3
326 },
327 /*
328 * Family 0x17 models a0-af (Zen 2 - Mendocino)
329 */
330 #define A_SKTS_MENDOCINO 27
331 {
332 [1] = X86_SOCKET_FT6
333 },
334
335 /*
336 * Family 0x19 models 70-7f (Zen 4 - Phoenix)
337 */
338 #define A_SKTS_PHOENIX 28
339 {
340 [0] = X86_SOCKET_AM5,
341 [1] = X86_SOCKET_FP8,
342 [4] = X86_SOCKET_FP7,
343 [5] = X86_SOCKET_FP7R2,
344 },
345
346 /*
347 * Family 0x19 models a0-af (Zen 4c - Bergamo/Siena)
348 */
349 #define A_SKTS_BERGAMO 29
350 {
351 [4] = X86_SOCKET_SP5,
352 [8] = X86_SOCKET_SP6
353 },
354 /*
355 * Family 0x1a models 00-1f (Zen 5[c] - Turin)
356 */
357 #define A_SKTS_TURIN 30
358 {
359 [4] = X86_SOCKET_SP5,
360 }
361 };
362
363 struct amd_sktmap_s {
364 uint32_t skt_code;
365 char sktstr[16];
366 };
367 static struct amd_sktmap_s amd_sktmap_strs[] = {
368 { X86_SOCKET_754, "754" },
369 { X86_SOCKET_939, "939" },
370 { X86_SOCKET_940, "940" },
371 { X86_SOCKET_S1g1, "S1g1" },
372 { X86_SOCKET_AM2, "AM2" },
373 { X86_SOCKET_F1207, "F(1207)" },
374 { X86_SOCKET_S1g2, "S1g2" },
375 { X86_SOCKET_S1g3, "S1g3" },
376 { X86_SOCKET_AM, "AM" },
377 { X86_SOCKET_AM2R2, "AM2r2" },
378 { X86_SOCKET_AM3, "AM3" },
379 { X86_SOCKET_G34, "G34" },
380 { X86_SOCKET_ASB2, "ASB2" },
381 { X86_SOCKET_C32, "C32" },
382 { X86_SOCKET_S1g4, "S1g4" },
383 { X86_SOCKET_FT1, "FT1" },
384 { X86_SOCKET_FM1, "FM1" },
385 { X86_SOCKET_FS1, "FS1" },
386 { X86_SOCKET_AM3R2, "AM3r2" },
387 { X86_SOCKET_FP2, "FP2" },
388 { X86_SOCKET_FS1R2, "FS1r2" },
389 { X86_SOCKET_FM2, "FM2" },
390 { X86_SOCKET_FP3, "FP3" },
391 { X86_SOCKET_FM2R2, "FM2r2" },
392 { X86_SOCKET_FP4, "FP4" },
393 { X86_SOCKET_AM4, "AM4" },
394 { X86_SOCKET_FT3, "FT3" },
395 { X86_SOCKET_FT4, "FT4" },
396 { X86_SOCKET_FS1B, "FS1b" },
397 { X86_SOCKET_FT3B, "FT3b" },
398 { X86_SOCKET_SP3, "SP3" },
399 { X86_SOCKET_SP3R2, "SP3r2" },
400 { X86_SOCKET_FP5, "FP5" },
401 { X86_SOCKET_FP6, "FP6" },
402 { X86_SOCKET_STRX4, "sTRX4" },
403 { X86_SOCKET_SL1, "SL1" },
404 { X86_SOCKET_SL1R2, "SL1R2" },
405 { X86_SOCKET_DM1, "DM1" },
406 { X86_SOCKET_SP5, "SP5" },
407 { X86_SOCKET_AM5, "AM5" },
408 { X86_SOCKET_FP7, "FP7" },
409 { X86_SOCKET_FP7R2, "FP7r2" },
410 { X86_SOCKET_FF3, "FF3" },
411 { X86_SOCKET_FT6, "FT6" },
412 { X86_SOCKET_FP8, "FP8" },
413 { X86_SOCKET_FL1, "FL1" },
414 { X86_SOCKET_SP6, "SP6" },
415 { X86_SOCKET_TR5, "TR5" },
416 { X86_SOCKET_UNKNOWN, "Unknown" } /* Must be last! */
417 };
418
419 /* Keep the array above in sync with the definitions in x86_archext.h. */
420 CTASSERT(ARRAY_SIZE(amd_sktmap_strs) == X86_NUM_SOCKETS + 1);
421
422 /*
423 * Table for mapping AMD family/model/stepping ranges onto three derived items:
424 *
425 * * The "chiprev" and associated string, which is generally the AMD silicon
426 * revision along with a symbolic representation of the marketing (not cpuid)
427 * family. In line with the overall cpuid usage, we refer to this as a
428 * processor family.
429 * * The uarch, which is analogous to the chiprev and provides the
430 * microarchitecture/core generation and silicon revision. Note that this is
431 * distinct from the package-level silicon/product revision and is often common
432 * to multiple product lines offered at a given time.
433 * * The socket map selector, used to translate this collection of products'
434 * last 4 model bits (for family 0xf only) or Fn8000_0001_EBX[30:28] into a
435 * socket ID.
436 *
437 * The first member of this array that matches a given family, extended model
438 * plus model range, and stepping range will be considered a match. This allows
439 * us to end each cpuid family and/or processor family with a catchall that
440 * while less specific than we might like still allows us to provide a fair
441 * amount of detail to both other kernel consumers and userland.
442 */
443 static const struct amd_rev_mapent {
444 uint_t rm_family;
445 uint_t rm_modello;
446 uint_t rm_modelhi;
447 uint_t rm_steplo;
448 uint_t rm_stephi;
449 x86_chiprev_t rm_chiprev;
450 const char *rm_chiprevstr;
451 x86_uarchrev_t rm_uarchrev;
452 uint_t rm_sktidx;
453 } amd_revmap[] = {
454 /*
455 * =============== AuthenticAMD Family 0xf ===============
456 */
457
458 /*
459 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1.
460 */
461 { 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_LEGACY_F_REV_B, "B",
462 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 },
463 { 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_LEGACY_F_REV_B, "B",
464 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 },
465 /*
466 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8
467 */
468 { 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_LEGACY_F_REV_C0, "C0",
469 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 },
470 /*
471 * Rev CG is the rest of extended model 0x0 - i.e., everything
472 * but the rev B and C0 combinations covered above.
473 */
474 { 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_CG, "CG",
475 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 },
476 /*
477 * Rev D has extended model 0x1.
478 */
479 { 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_D, "D",
480 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 },
481 /*
482 * Rev E has extended model 0x2.
483 * Extended model 0x3 is unused but available to grow into.
484 */
485 { 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_E, "E",
486 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 },
487 /*
488 * Rev F has extended models 0x4 and 0x5.
489 */
490 { 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_F, "F",
491 X86_UARCHREV_AMD_LEGACY, A_SKTS_1 },
492 /*
493 * Rev G has extended model 0x6.
494 */
495 { 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_G, "G",
496 X86_UARCHREV_AMD_LEGACY, A_SKTS_1 },
497
498 /*
499 * =============== AuthenticAMD Family 0x10 ===============
500 */
501
502 /*
503 * Rev A has model 0 and stepping 0/1/2 for DR-{A0,A1,A2}.
504 * Give all of model 0 stepping range to rev A.
505 */
506 { 0x10, 0x00, 0x00, 0x0, 0x2, X86_CHIPREV_AMD_LEGACY_10_REV_A, "A",
507 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
508
509 /*
510 * Rev B has model 2 and steppings 0/1/0xa/2 for DR-{B0,B1,BA,B2}.
511 * Give all of model 2 stepping range to rev B.
512 */
513 { 0x10, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_B, "B",
514 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
515
516 /*
517 * Rev C has models 4-6 (depending on L3 cache configuration)
518 * Give all of models 4-6 stepping range 0-2 to rev C2.
519 */
520 { 0x10, 0x4, 0x6, 0x0, 0x2, X86_CHIPREV_AMD_LEGACY_10_REV_C2, "C2",
521 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
522
523 /*
524 * Rev C has models 4-6 (depending on L3 cache configuration)
525 * Give all of models 4-6 stepping range >= 3 to rev C3.
526 */
527 { 0x10, 0x4, 0x6, 0x3, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_C3, "C3",
528 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
529
530 /*
531 * Rev D has models 8 and 9
532 * Give all of model 8 and 9 stepping 0 to rev D0.
533 */
534 { 0x10, 0x8, 0x9, 0x0, 0x0, X86_CHIPREV_AMD_LEGACY_10_REV_D0, "D0",
535 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
536
537 /*
538 * Rev D has models 8 and 9
539 * Give all of model 8 and 9 stepping range >= 1 to rev D1.
540 */
541 { 0x10, 0x8, 0x9, 0x1, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_D1, "D1",
542 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
543
544 /*
545 * Rev E has models A and stepping 0
546 * Give all of model A stepping range to rev E.
547 */
548 { 0x10, 0xA, 0xA, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_E, "E",
549 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
550
551 { 0x10, 0x0, 0xff, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_10_UNKNOWN, "??",
552 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 },
553
554 /*
555 * =============== AuthenticAMD Family 0x11 ===============
556 */
557 { 0x11, 0x03, 0x03, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_11_REV_B, "B",
558 X86_UARCHREV_AMD_LEGACY, A_SKTS_3 },
559 { 0x11, 0x00, 0xff, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_11_UNKNOWN, "??",
560 X86_UARCHREV_AMD_LEGACY, A_SKTS_3 },
561
562 /*
563 * =============== AuthenticAMD Family 0x12 ===============
564 */
565 { 0x12, 0x01, 0x01, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_12_REV_B, "B",
566 X86_UARCHREV_AMD_LEGACY, A_SKTS_4 },
567 { 0x12, 0x00, 0x00, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_12_UNKNOWN, "??",
568 X86_UARCHREV_AMD_LEGACY, A_SKTS_4 },
569
570 /*
571 * =============== AuthenticAMD Family 0x14 ===============
572 */
573 { 0x14, 0x01, 0x01, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_14_REV_B, "B",
574 X86_UARCHREV_AMD_LEGACY, A_SKTS_5 },
575 { 0x14, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_14_REV_C, "C",
576 X86_UARCHREV_AMD_LEGACY, A_SKTS_5 },
577 { 0x14, 0x00, 0xff, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_14_UNKNOWN, "??",
578 X86_UARCHREV_AMD_LEGACY, A_SKTS_5 },
579
580 /*
581 * =============== AuthenticAMD Family 0x15 ===============
582 */
583 { 0x15, 0x01, 0x01, 0x2, 0x2, X86_CHIPREV_AMD_OROCHI_REV_B2, "OR-B2",
584 X86_UARCHREV_AMD_LEGACY, A_SKTS_6 },
585 { 0x15, 0x02, 0x02, 0x0, 0x0, X86_CHIPREV_AMD_OROCHI_REV_C0, "OR-C0",
586 X86_UARCHREV_AMD_LEGACY, A_SKTS_6 },
587 { 0x15, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_OROCHI_UNKNOWN, "OR-??",
588 X86_UARCHREV_AMD_LEGACY, A_SKTS_6 },
589
590 { 0x15, 0x10, 0x10, 0x1, 0x1, X86_CHIPREV_AMD_TRINITY_REV_A1, "TN-A1",
591 X86_UARCHREV_AMD_LEGACY, A_SKTS_7 },
592 { 0x15, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_TRINITY_UNKNOWN, "TN-??",
593 X86_UARCHREV_AMD_LEGACY, A_SKTS_7 },
594
595 { 0x15, 0x30, 0x30, 0x1, 0x1, X86_CHIPREV_AMD_KAVERI_REV_A1, "KV-A1",
596 X86_UARCHREV_AMD_LEGACY, A_SKTS_8 },
597 { 0x15, 0x30, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_KAVERI_UNKNOWN, "KV-??",
598 X86_UARCHREV_AMD_LEGACY, A_SKTS_8 },
599
600 /*
601 * The Carrizo rev guide mentions A0 as having an ID of "00600F00h" but
602 * this appears to be a typo as elsewhere it's given as "00660F00h". We
603 * assume the latter is correct.
604 */
605 { 0x15, 0x60, 0x60, 0x0, 0x0, X86_CHIPREV_AMD_CARRIZO_REV_A0, "CZ-A0",
606 X86_UARCHREV_AMD_LEGACY, A_SKTS_9 },
607 { 0x15, 0x60, 0x60, 0x1, 0x1, X86_CHIPREV_AMD_CARRIZO_REV_A1, "CZ-A1",
608 X86_UARCHREV_AMD_LEGACY, A_SKTS_9 },
609 /*
610 * CZ-DDR4 and BR-A1 are indistinguishable via cpuid; the rev guide
611 * indicates that they should be distinguished by the contents of the
612 * OSVW MSR, but this register is just a software scratch space which
613 * means the actual method of distinguishing the two is not documented
614 * and on PCs will be done by a BIOS. In the extremely unlikely event
615 * it becomes necessary to distinguish these, an OSVW-driven fixup can
616 * be added.
617 */
618 { 0x15, 0x65, 0x65, 0x1, 0x1, X86_CHIPREV_AMD_CARRIZO_REV_DDR4,
619 "CZ-DDR4", X86_UARCHREV_AMD_LEGACY, A_SKTS_9 },
620 { 0x15, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_CARRIZO_UNKNOWN, "CZ-??",
621 X86_UARCHREV_AMD_LEGACY, A_SKTS_9 },
622
623 { 0x15, 0x70, 0x70, 0x0, 0x0, X86_CHIPREV_AMD_STONEY_RIDGE_REV_A0,
624 "ST-A0", X86_UARCHREV_AMD_LEGACY, A_SKTS_10 },
625 { 0x15, 0x70, 0x7f, 0x0, 0xf, X86_CHIPREV_AMD_STONEY_RIDGE_UNKNOWN,
626 "ST-??", X86_UARCHREV_AMD_LEGACY, A_SKTS_10 },
627
628 /*
629 * =============== AuthenticAMD Family 0x16 ===============
630 */
631 { 0x16, 0x00, 0x00, 0x1, 0x1, X86_CHIPREV_AMD_KABINI_A1, "KB-A1",
632 X86_UARCHREV_AMD_LEGACY, A_SKTS_11 },
633 { 0x16, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_KABINI_UNKNOWN, "KB-??",
634 X86_UARCHREV_AMD_LEGACY, A_SKTS_11 },
635
636 { 0x16, 0x30, 0x30, 0x1, 0x1, X86_CHIPREV_AMD_MULLINS_A1, "ML-A1",
637 X86_UARCHREV_AMD_LEGACY, A_SKTS_12 },
638 { 0x16, 0x30, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_MULLINS_UNKNOWN, "ML-??",
639 X86_UARCHREV_AMD_LEGACY, A_SKTS_12 },
640
641 /*
642 * =============== AuthenticAMD Family 0x17 ===============
643 */
644 /* Naples == Zeppelin == ZP */
645 { 0x17, 0x00, 0x00, 0x0, 0x0, X86_CHIPREV_AMD_NAPLES_A0, "ZP-A0",
646 X86_UARCHREV_AMD_ZEN1, A_SKTS_NAPLES },
647 { 0x17, 0x01, 0x01, 0x1, 0x1, X86_CHIPREV_AMD_NAPLES_B1, "ZP-B1",
648 X86_UARCHREV_AMD_ZEN1, A_SKTS_NAPLES },
649 { 0x17, 0x01, 0x01, 0x2, 0x2, X86_CHIPREV_AMD_NAPLES_B2, "ZP-B2",
650 X86_UARCHREV_AMD_ZEN1, A_SKTS_NAPLES },
651 { 0x17, 0x00, 0x07, 0x0, 0xf, X86_CHIPREV_AMD_NAPLES_UNKNOWN, "ZP-??",
652 X86_UARCHREV_AMD_ZEN1, A_SKTS_NAPLES },
653 { 0x17, 0x08, 0x08, 0x2, 0x2, X86_CHIPREV_AMD_PINNACLE_RIDGE_B2,
654 "PiR-B2", X86_UARCHREV_AMD_ZENPLUS, A_SKTS_NAPLES },
655 { 0x17, 0x08, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_PINNACLE_RIDGE_UNKNOWN,
656 "PiR-??", X86_UARCHREV_AMD_ZENPLUS, A_SKTS_NAPLES },
657
658 { 0x17, 0x11, 0x11, 0x0, 0x0, X86_CHIPREV_AMD_RAVEN_RIDGE_B0,
659 "RV-B0", X86_UARCHREV_AMD_ZEN1, A_SKTS_RAVEN },
660 { 0x17, 0x11, 0x11, 0x1, 0x1, X86_CHIPREV_AMD_RAVEN_RIDGE_B1,
661 "RV-B1", X86_UARCHREV_AMD_ZEN1, A_SKTS_RAVEN },
662 { 0x17, 0x10, 0x17, 0x0, 0xf, X86_CHIPREV_AMD_RAVEN_RIDGE_UNKNOWN,
663 "RV-??", X86_UARCHREV_AMD_ZEN1, A_SKTS_RAVEN },
664 { 0x17, 0x18, 0x18, 0x1, 0x1, X86_CHIPREV_AMD_PICASSO_B1, "PCO-B1",
665 X86_UARCHREV_AMD_ZENPLUS, A_SKTS_RAVEN },
666 { 0x17, 0x18, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_PICASSO_UNKNOWN, "PCO-??",
667 X86_UARCHREV_AMD_ZENPLUS, A_SKTS_RAVEN },
668
669 { 0x17, 0x20, 0x20, 0x1, 0x1, X86_CHIPREV_AMD_DALI_A1, "RV2X-A1",
670 X86_UARCHREV_AMD_ZEN1, A_SKTS_RAVEN },
671 { 0x17, 0x20, 0x2f, 0x0, 0xf, X86_CHIPREV_AMD_DALI_UNKNOWN, "RV2X-??",
672 X86_UARCHREV_AMD_ZEN1, A_SKTS_RAVEN },
673
674 /* Rome == Starship == SSP */
675 { 0x17, 0x30, 0x30, 0x0, 0x0, X86_CHIPREV_AMD_ROME_A0, "SSP-A0",
676 X86_UARCHREV_AMD_ZEN2_A0, A_SKTS_ROME },
677 { 0x17, 0x31, 0x31, 0x0, 0x0, X86_CHIPREV_AMD_ROME_B0, "SSP-B0",
678 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_ROME },
679 { 0x17, 0x30, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_ROME_UNKNOWN, "SSP-??",
680 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_ROME },
681
682 { 0x17, 0x60, 0x60, 0x1, 0x1, X86_CHIPREV_AMD_RENOIR_A1, "RN-A1",
683 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_RENOIR },
684 { 0x17, 0x60, 0x67, 0x0, 0xf, X86_CHIPREV_AMD_RENOIR_UNKNOWN, "RN-??",
685 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_RENOIR },
686 { 0x17, 0x68, 0x68, 0x1, 0x1, X86_CHIPREV_AMD_RENOIR_LCN_A1, "LCN-A1",
687 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_RENOIR },
688 { 0x17, 0x68, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_RENOIR_UNKNOWN, "LCN-??",
689 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_RENOIR },
690
691 { 0x17, 0x71, 0x71, 0x0, 0x0, X86_CHIPREV_AMD_MATISSE_B0, "MTS-B0",
692 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_MATISSE },
693 { 0x17, 0x70, 0x7f, 0x0, 0xf, X86_CHIPREV_AMD_MATISSE_UNKNOWN, "MTS-??",
694 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_MATISSE },
695
696 { 0x17, 0x90, 0x97, 0x0, 0xf, X86_CHIPREV_AMD_VAN_GOGH_UNKNOWN, "??",
697 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_VANGOGH },
698 { 0x17, 0x98, 0x9f, 0x0, 0xf, X86_CHIPREV_AMD_VAN_GOGH_UNKNOWN, "??",
699 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_UNKNOWN },
700
701 { 0x17, 0xa0, 0xaf, 0x0, 0xf, X86_CHIPREV_AMD_MENDOCINO_UNKNOWN, "??",
702 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_MENDOCINO },
703
704 /*
705 * =============== HygonGenuine Family 0x18 ===============
706 */
707 { 0x18, 0x00, 0x00, 0x1, 0x1, X86_CHIPREV_HYGON_DHYANA_A1, "DN_A1",
708 X86_UARCHREV_AMD_ZEN1, A_SKTS_DHYANA },
709 { 0x18, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_HYGON_DHYANA_UNKNOWN, "DN_??",
710 X86_UARCHREV_AMD_ZEN1, A_SKTS_DHYANA },
711
712 /*
713 * =============== AuthenticAMD Family 0x19 ===============
714 */
715 /* Milan == Genesis == GN */
716 { 0x19, 0x00, 0x00, 0x0, 0x0, X86_CHIPREV_AMD_MILAN_A0, "GN-A0",
717 X86_UARCHREV_AMD_ZEN3_A0, A_SKTS_MILAN },
718 { 0x19, 0x01, 0x01, 0x0, 0x0, X86_CHIPREV_AMD_MILAN_B0, "GN-B0",
719 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_MILAN },
720 { 0x19, 0x01, 0x01, 0x1, 0x1, X86_CHIPREV_AMD_MILAN_B1, "GN-B1",
721 X86_UARCHREV_AMD_ZEN3_B1, A_SKTS_MILAN },
722 /* Marketed as Milan-X but still GN */
723 { 0x19, 0x01, 0x01, 0x2, 0x2, X86_CHIPREV_AMD_MILAN_B2, "GN-B2",
724 X86_UARCHREV_AMD_ZEN3_B2, A_SKTS_MILAN },
725 { 0x19, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_MILAN_UNKNOWN, "GN-??",
726 X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_MILAN },
727
728 /* Genoa == Stones == RS */
729 { 0x19, 0x10, 0x10, 0x0, 0x0, X86_CHIPREV_AMD_GENOA_A0, "RS-A0",
730 X86_UARCHREV_AMD_ZEN4_A0, A_SKTS_GENOA },
731 /* RS-A0 & RS-A1 both map to Zen 4 uarch A0 */
732 { 0x19, 0x10, 0x10, 0x1, 0x1, X86_CHIPREV_AMD_GENOA_A1, "RS-A1",
733 X86_UARCHREV_AMD_ZEN4_A0, A_SKTS_GENOA },
734 { 0x19, 0x11, 0x11, 0x0, 0x0, X86_CHIPREV_AMD_GENOA_B0, "RS-B0",
735 X86_UARCHREV_AMD_ZEN4_B0, A_SKTS_GENOA },
736 { 0x19, 0x11, 0x11, 0x1, 0x1, X86_CHIPREV_AMD_GENOA_B1, "RS-B1",
737 X86_UARCHREV_AMD_ZEN4_B1, A_SKTS_GENOA },
738 { 0x19, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_GENOA_UNKNOWN, "RS-??",
739 X86_UARCHREV_AMD_ZEN4_UNKNOWN, A_SKTS_GENOA },
740
741 { 0x19, 0x20, 0x20, 0x0, 0x0, X86_CHIPREV_AMD_VERMEER_A0, "VMR-A0",
742 X86_UARCHREV_AMD_ZEN3_A0, A_SKTS_VERMEER },
743 { 0x19, 0x21, 0x21, 0x0, 0x0, X86_CHIPREV_AMD_VERMEER_B0, "VMR-B0",
744 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_VERMEER },
745 { 0x19, 0x21, 0x21, 0x2, 0x2, X86_CHIPREV_AMD_VERMEER_B2, "VMR-B2",
746 X86_UARCHREV_AMD_ZEN3_B2, A_SKTS_VERMEER },
747 { 0x19, 0x20, 0x2f, 0x0, 0xf, X86_CHIPREV_AMD_VERMEER_UNKNOWN, "VMR-??",
748 X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_VERMEER },
749
750 /* Rev guide is missing AM5 information, including A0 and B0 */
751 { 0x19, 0x40, 0x40, 0x0, 0x0, X86_CHIPREV_AMD_REMBRANDT_A0, "RMB-A0",
752 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_REMBRANDT },
753 { 0x19, 0x44, 0x44, 0x0, 0x0, X86_CHIPREV_AMD_REMBRANDT_B0, "RMB-B0",
754 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_REMBRANDT },
755 { 0x19, 0x44, 0x44, 0x1, 0x1, X86_CHIPREV_AMD_REMBRANDT_B1, "RMB-B1",
756 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_REMBRANDT },
757 { 0x19, 0x40, 0x4f, 0x0, 0xf, X86_CHIPREV_AMD_REMBRANDT_UNKNOWN,
758 "RMB-??", X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_REMBRANDT },
759
760 /* Cezanne */
761 { 0x19, 0x50, 0x50, 0x0, 0x0, X86_CHIPREV_AMD_CEZANNE_A0, "CZN-A0",
762 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_CEZANNE },
763 { 0x19, 0x50, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_CEZANNE_UNKNOWN, "CZN-??",
764 X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_CEZANNE },
765
766 /* Raphael */
767 { 0x19, 0x61, 0x61, 0x2, 0x2, X86_CHIPREV_AMD_RAPHAEL_B2, "RPL-B2",
768 X86_UARCHREV_AMD_ZEN4_B2, A_SKTS_RAPHAEL },
769 { 0x19, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_RAPHAEL_UNKNOWN, "RPL-??",
770 X86_UARCHREV_AMD_ZEN4_UNKNOWN, A_SKTS_RAPHAEL },
771
772 /* Phoenix */
773 { 0x19, 0x74, 0x74, 0x1, 0x1, X86_CHIPREV_AMD_PHOENIX_A1, "PHX-A1",
774 X86_UARCHREV_AMD_ZEN4_A1, A_SKTS_PHOENIX },
775 { 0x19, 0x70, 0x7f, 0x0, 0xf, X86_CHIPREV_AMD_PHOENIX_UNKNOWN, "PHX-??",
776 X86_UARCHREV_AMD_ZEN4_UNKNOWN, A_SKTS_PHOENIX },
777
778 /* Bergamo / Siena */
779 { 0x19, 0xa0, 0xaf, 0x0, 0x0, X86_CHIPREV_AMD_BERGAMO_A0, "RSDN-A0",
780 X86_UARCHREV_AMD_ZEN4_A0, A_SKTS_BERGAMO },
781 { 0x19, 0xa0, 0xaf, 0x1, 0x1, X86_CHIPREV_AMD_BERGAMO_A1, "RSDN-A1",
782 X86_UARCHREV_AMD_ZEN4_A1, A_SKTS_BERGAMO },
783 { 0x19, 0xa0, 0xaf, 0x2, 0x2, X86_CHIPREV_AMD_BERGAMO_A2, "RSDN-A2",
784 X86_UARCHREV_AMD_ZEN4_A2, A_SKTS_BERGAMO },
785 { 0x19, 0xa0, 0xaf, 0x0, 0xf, X86_CHIPREV_AMD_BERGAMO_UNKNOWN, "???",
786 X86_UARCHREV_AMD_ZEN4_UNKNOWN, A_SKTS_BERGAMO },
787
788 /* Turin */
789 { 0x1a, 0x00, 0x0f, 0x0, 0x0, X86_CHIPREV_AMD_TURIN_UNKNOWN, "BRH-A0",
790 X86_UARCHREV_AMD_ZEN5_UNKNOWN, A_SKTS_TURIN},
791 { 0x1a, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_TURIN_UNKNOWN, "BRH-???",
792 X86_UARCHREV_AMD_ZEN5_UNKNOWN, A_SKTS_TURIN},
793 { 0x1a, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_DENSE_TURIN_UNKNOWN,
794 "BRHD-???", X86_UARCHREV_AMD_ZEN5_UNKNOWN, A_SKTS_TURIN}
795
796 };
797
798 /*
799 * AMD keeps the socket type in CPUID Fn8000_0001_EBX, bits 31:28.
800 */
801 static uint32_t
synth_amd_skt_cpuid(uint_t family,uint_t sktid)802 synth_amd_skt_cpuid(uint_t family, uint_t sktid)
803 {
804 struct cpuid_regs cp;
805 uint_t idx;
806
807 cp.cp_eax = 0x80000001;
808 (void) __cpuid_insn(&cp);
809
810 /* PkgType bits */
811 idx = BITX(cp.cp_ebx, 31, 28);
812
813 if (family == 0x10) {
814 uint32_t val;
815
816 val = pci_getl_func(0, 24, 2, 0x94);
817 if (BITX(val, 8, 8)) {
818 if (amd_skts[sktid][idx] == X86_SOCKET_AM2R2) {
819 return (X86_SOCKET_AM3);
820 } else if (amd_skts[sktid][idx] == X86_SOCKET_S1g3) {
821 return (X86_SOCKET_S1g4);
822 }
823 }
824 }
825
826 return (amd_skts[sktid][idx]);
827 }
828
829 static void
synth_amd_info(uint_t family,uint_t model,uint_t step,uint32_t * skt_p,x86_chiprev_t * chiprev_p,const char ** chiprevstr_p,x86_uarchrev_t * uarchrev_p)830 synth_amd_info(uint_t family, uint_t model, uint_t step,
831 uint32_t *skt_p, x86_chiprev_t *chiprev_p, const char **chiprevstr_p,
832 x86_uarchrev_t *uarchrev_p)
833 {
834 const struct amd_rev_mapent *rmp;
835 int found = 0;
836 int i;
837
838 if (family < 0xf)
839 return;
840
841 for (i = 0, rmp = amd_revmap; i < ARRAY_SIZE(amd_revmap); i++, rmp++) {
842 if (family == rmp->rm_family &&
843 model >= rmp->rm_modello && model <= rmp->rm_modelhi &&
844 step >= rmp->rm_steplo && step <= rmp->rm_stephi) {
845 found = 1;
846 break;
847 }
848 }
849
850 if (found) {
851 if (chiprev_p != NULL)
852 *chiprev_p = rmp->rm_chiprev;
853 if (chiprevstr_p != NULL)
854 *chiprevstr_p = rmp->rm_chiprevstr;
855 if (uarchrev_p != NULL)
856 *uarchrev_p = rmp->rm_uarchrev;
857 }
858
859 if (skt_p != NULL) {
860 int platform;
861
862 #ifdef __xpv
863 /* PV guest */
864 if (!is_controldom()) {
865 *skt_p = X86_SOCKET_UNKNOWN;
866 return;
867 }
868 #endif
869 platform = get_hwenv();
870
871 if ((platform & HW_VIRTUAL) != 0) {
872 *skt_p = X86_SOCKET_UNKNOWN;
873 return;
874 }
875
876 if (!found)
877 return;
878
879 if (family == 0xf) {
880 *skt_p = amd_skts[rmp->rm_sktidx][model & 0x3];
881 } else {
882 *skt_p = synth_amd_skt_cpuid(family, rmp->rm_sktidx);
883 }
884 }
885 }
886
887 uint32_t
_cpuid_skt(uint_t vendor,uint_t family,uint_t model,uint_t step)888 _cpuid_skt(uint_t vendor, uint_t family, uint_t model, uint_t step)
889 {
890 uint32_t skt = X86_SOCKET_UNKNOWN;
891
892 switch (vendor) {
893 case X86_VENDOR_AMD:
894 case X86_VENDOR_HYGON:
895 synth_amd_info(family, model, step, &skt, NULL, NULL, NULL);
896 break;
897
898 default:
899 break;
900
901 }
902
903 return (skt);
904 }
905
906 const char *
_cpuid_sktstr(uint_t vendor,uint_t family,uint_t model,uint_t step)907 _cpuid_sktstr(uint_t vendor, uint_t family, uint_t model, uint_t step)
908 {
909 const char *sktstr = "Unknown";
910 struct amd_sktmap_s *sktmapp;
911 uint32_t skt = X86_SOCKET_UNKNOWN;
912
913 switch (vendor) {
914 case X86_VENDOR_AMD:
915 case X86_VENDOR_HYGON:
916 synth_amd_info(family, model, step, &skt, NULL, NULL, NULL);
917
918 sktmapp = amd_sktmap_strs;
919 while (sktmapp->skt_code != X86_SOCKET_UNKNOWN) {
920 if (sktmapp->skt_code == skt)
921 break;
922 sktmapp++;
923 }
924 sktstr = sktmapp->sktstr;
925 break;
926
927 default:
928 break;
929
930 }
931
932 return (sktstr);
933 }
934
935 x86_chiprev_t
_cpuid_chiprev(uint_t vendor,uint_t family,uint_t model,uint_t step)936 _cpuid_chiprev(uint_t vendor, uint_t family, uint_t model, uint_t step)
937 {
938 x86_chiprev_t chiprev = X86_CHIPREV_UNKNOWN;
939
940 switch (vendor) {
941 case X86_VENDOR_AMD:
942 case X86_VENDOR_HYGON:
943 synth_amd_info(family, model, step, NULL, &chiprev, NULL, NULL);
944 break;
945
946 default:
947 break;
948
949 }
950
951 return (chiprev);
952 }
953
954 x86_uarchrev_t
_cpuid_uarchrev(uint_t vendor,uint_t family,uint_t model,uint_t step)955 _cpuid_uarchrev(uint_t vendor, uint_t family, uint_t model, uint_t step)
956 {
957 x86_uarchrev_t uarchrev = X86_UARCHREV_UNKNOWN;
958
959 switch (vendor) {
960 case X86_VENDOR_AMD:
961 case X86_VENDOR_HYGON:
962 synth_amd_info(family, model, step, NULL, NULL, NULL,
963 &uarchrev);
964 break;
965
966 default:
967 break;
968
969 }
970
971 return (uarchrev);
972 }
973
974 const char *
_cpuid_chiprevstr(uint_t vendor,uint_t family,uint_t model,uint_t step)975 _cpuid_chiprevstr(uint_t vendor, uint_t family, uint_t model, uint_t step)
976 {
977 const char *revstr = "Unknown";
978
979 switch (vendor) {
980 case X86_VENDOR_AMD:
981 case X86_VENDOR_HYGON:
982 synth_amd_info(family, model, step, NULL, NULL, &revstr, NULL);
983 break;
984
985 default:
986 break;
987
988 }
989
990 return (revstr);
991
992 }
993
994 /*
995 * Map the vendor string to a type code
996 */
997 uint_t
_cpuid_vendorstr_to_vendorcode(char * vendorstr)998 _cpuid_vendorstr_to_vendorcode(char *vendorstr)
999 {
1000 if (strcmp(vendorstr, X86_VENDORSTR_Intel) == 0)
1001 return (X86_VENDOR_Intel);
1002 else if (strcmp(vendorstr, X86_VENDORSTR_AMD) == 0)
1003 return (X86_VENDOR_AMD);
1004 else if (strcmp(vendorstr, X86_VENDORSTR_HYGON) == 0)
1005 return (X86_VENDOR_HYGON);
1006 else if (strcmp(vendorstr, X86_VENDORSTR_TM) == 0)
1007 return (X86_VENDOR_TM);
1008 else if (strcmp(vendorstr, X86_VENDORSTR_CYRIX) == 0)
1009 return (X86_VENDOR_Cyrix);
1010 else if (strcmp(vendorstr, X86_VENDORSTR_UMC) == 0)
1011 return (X86_VENDOR_UMC);
1012 else if (strcmp(vendorstr, X86_VENDORSTR_NexGen) == 0)
1013 return (X86_VENDOR_NexGen);
1014 else if (strcmp(vendorstr, X86_VENDORSTR_Centaur) == 0)
1015 return (X86_VENDOR_Centaur);
1016 else if (strcmp(vendorstr, X86_VENDORSTR_Rise) == 0)
1017 return (X86_VENDOR_Rise);
1018 else if (strcmp(vendorstr, X86_VENDORSTR_SiS) == 0)
1019 return (X86_VENDOR_SiS);
1020 else if (strcmp(vendorstr, X86_VENDORSTR_NSC) == 0)
1021 return (X86_VENDOR_NSC);
1022 else
1023 return (X86_VENDOR_IntelClone);
1024 }
1025