1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip Generic power domain support.
4 *
5 * Copyright (c) 2015 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/arm-smccc.h>
9 #include <linux/io.h>
10 #include <linux/iopoll.h>
11 #include <linux/err.h>
12 #include <linux/mutex.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_clock.h>
15 #include <linux/pm_domain.h>
16 #include <linux/property.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_clk.h>
20 #include <linux/clk.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/mfd/syscon.h>
24 #include <soc/rockchip/pm_domains.h>
25 #include <soc/rockchip/rockchip_sip.h>
26 #include <dt-bindings/power/px30-power.h>
27 #include <dt-bindings/power/rockchip,rv1126-power.h>
28 #include <dt-bindings/power/rk3036-power.h>
29 #include <dt-bindings/power/rk3066-power.h>
30 #include <dt-bindings/power/rk3128-power.h>
31 #include <dt-bindings/power/rk3188-power.h>
32 #include <dt-bindings/power/rk3228-power.h>
33 #include <dt-bindings/power/rk3288-power.h>
34 #include <dt-bindings/power/rk3328-power.h>
35 #include <dt-bindings/power/rk3366-power.h>
36 #include <dt-bindings/power/rk3368-power.h>
37 #include <dt-bindings/power/rk3399-power.h>
38 #include <dt-bindings/power/rockchip,rk3528-power.h>
39 #include <dt-bindings/power/rockchip,rk3562-power.h>
40 #include <dt-bindings/power/rk3568-power.h>
41 #include <dt-bindings/power/rockchip,rk3576-power.h>
42 #include <dt-bindings/power/rk3588-power.h>
43
44 struct rockchip_domain_info {
45 const char *name;
46 int pwr_mask;
47 int status_mask;
48 int req_mask;
49 int idle_mask;
50 int ack_mask;
51 bool active_wakeup;
52 bool need_regulator;
53 int pwr_w_mask;
54 int req_w_mask;
55 int clk_ungate_mask;
56 int mem_status_mask;
57 int repair_status_mask;
58 u32 pwr_offset;
59 u32 mem_offset;
60 u32 req_offset;
61 };
62
63 struct rockchip_pmu_info {
64 u32 pwr_offset;
65 u32 status_offset;
66 u32 req_offset;
67 u32 idle_offset;
68 u32 ack_offset;
69 u32 mem_pwr_offset;
70 u32 chain_status_offset;
71 u32 mem_status_offset;
72 u32 repair_status_offset;
73 u32 clk_ungate_offset;
74
75 u32 core_pwrcnt_offset;
76 u32 gpu_pwrcnt_offset;
77
78 unsigned int core_power_transition_time;
79 unsigned int gpu_power_transition_time;
80
81 int num_domains;
82 const struct rockchip_domain_info *domain_info;
83 };
84
85 #define MAX_QOS_REGS_NUM 5
86 #define QOS_PRIORITY 0x08
87 #define QOS_MODE 0x0c
88 #define QOS_BANDWIDTH 0x10
89 #define QOS_SATURATION 0x14
90 #define QOS_EXTCONTROL 0x18
91
92 struct rockchip_pm_domain {
93 struct generic_pm_domain genpd;
94 const struct rockchip_domain_info *info;
95 struct rockchip_pmu *pmu;
96 int num_qos;
97 struct regmap **qos_regmap;
98 u32 *qos_save_regs[MAX_QOS_REGS_NUM];
99 int num_clks;
100 struct clk_bulk_data *clks;
101 struct device_node *node;
102 struct regulator *supply;
103 };
104
105 struct rockchip_pmu {
106 struct device *dev;
107 struct regmap *regmap;
108 const struct rockchip_pmu_info *info;
109 struct mutex mutex; /* mutex lock for pmu */
110 struct genpd_onecell_data genpd_data;
111 struct generic_pm_domain *domains[];
112 };
113
114 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
115
116 #define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \
117 { \
118 .name = _name, \
119 .pwr_mask = (pwr), \
120 .status_mask = (status), \
121 .req_mask = (req), \
122 .idle_mask = (idle), \
123 .ack_mask = (ack), \
124 .active_wakeup = (wakeup), \
125 }
126
127 #define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \
128 { \
129 .name = _name, \
130 .pwr_w_mask = (pwr) << 16, \
131 .pwr_mask = (pwr), \
132 .status_mask = (status), \
133 .req_w_mask = (req) << 16, \
134 .req_mask = (req), \
135 .idle_mask = (idle), \
136 .ack_mask = (ack), \
137 .active_wakeup = wakeup, \
138 }
139
140 #define DOMAIN_M_G_SD(_name, pwr, status, req, idle, ack, g_mask, mem, wakeup, keepon) \
141 { \
142 .name = _name, \
143 .pwr_w_mask = (pwr) << 16, \
144 .pwr_mask = (pwr), \
145 .status_mask = (status), \
146 .req_w_mask = (req) << 16, \
147 .req_mask = (req), \
148 .idle_mask = (idle), \
149 .ack_mask = (ack), \
150 .clk_ungate_mask = (g_mask), \
151 .active_wakeup = wakeup, \
152 }
153
154 #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup, regulator) \
155 { \
156 .name = _name, \
157 .pwr_offset = p_offset, \
158 .pwr_w_mask = (pwr) << 16, \
159 .pwr_mask = (pwr), \
160 .status_mask = (status), \
161 .mem_offset = m_offset, \
162 .mem_status_mask = (m_status), \
163 .repair_status_mask = (r_status), \
164 .req_offset = r_offset, \
165 .req_w_mask = (req) << 16, \
166 .req_mask = (req), \
167 .idle_mask = (idle), \
168 .ack_mask = (ack), \
169 .active_wakeup = wakeup, \
170 .need_regulator = regulator, \
171 }
172
173 #define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup) \
174 { \
175 .name = _name, \
176 .pwr_offset = p_offset, \
177 .pwr_w_mask = (pwr) << 16, \
178 .pwr_mask = (pwr), \
179 .status_mask = (status), \
180 .mem_offset = m_offset, \
181 .mem_status_mask = (m_status), \
182 .repair_status_mask = (r_status), \
183 .req_offset = r_offset, \
184 .req_w_mask = (req) << 16, \
185 .req_mask = (req), \
186 .idle_mask = (idle), \
187 .clk_ungate_mask = (g_mask), \
188 .ack_mask = (ack), \
189 .active_wakeup = wakeup, \
190 }
191
192 #define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \
193 { \
194 .name = _name, \
195 .req_mask = (req), \
196 .req_w_mask = (req) << 16, \
197 .ack_mask = (ack), \
198 .idle_mask = (idle), \
199 .active_wakeup = wakeup, \
200 }
201
202 #define DOMAIN_PX30(name, pwr, status, req, wakeup) \
203 DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup)
204
205 #define DOMAIN_RV1126(name, pwr, req, idle, wakeup) \
206 DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup)
207
208 #define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
209 DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
210
211 #define DOMAIN_RK3328(name, pwr, status, req, wakeup) \
212 DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup)
213
214 #define DOMAIN_RK3368(name, pwr, status, req, wakeup) \
215 DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup)
216
217 #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
218 DOMAIN(name, pwr, status, req, req, req, wakeup)
219
220 #define DOMAIN_RK3528(name, pwr, req) \
221 DOMAIN_M(name, pwr, pwr, req, req, req, false)
222
223 #define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) \
224 DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false)
225
226 #define DOMAIN_RK3568(name, pwr, req, wakeup) \
227 DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
228
229 #define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \
230 DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup)
231
232 /*
233 * Dynamic Memory Controller may need to coordinate with us -- see
234 * rockchip_pmu_block().
235 *
236 * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
237 * block() while we're initializing the PMU.
238 */
239 static DEFINE_MUTEX(dmc_pmu_mutex);
240 static struct rockchip_pmu *dmc_pmu;
241
242 /*
243 * Block PMU transitions and make sure they don't interfere with ARM Trusted
244 * Firmware operations. There are two conflicts, noted in the comments below.
245 *
246 * Caller must unblock PMU transitions via rockchip_pmu_unblock().
247 */
rockchip_pmu_block(void)248 int rockchip_pmu_block(void)
249 {
250 struct rockchip_pmu *pmu;
251 struct generic_pm_domain *genpd;
252 struct rockchip_pm_domain *pd;
253 int i, ret;
254
255 mutex_lock(&dmc_pmu_mutex);
256
257 /* No PMU (yet)? Then we just block rockchip_pmu_probe(). */
258 if (!dmc_pmu)
259 return 0;
260 pmu = dmc_pmu;
261
262 /*
263 * mutex blocks all idle transitions: we can't touch the
264 * PMU_BUS_IDLE_REQ (our ".idle_offset") register while ARM Trusted
265 * Firmware might be using it.
266 */
267 mutex_lock(&pmu->mutex);
268
269 /*
270 * Power domain clocks: Per Rockchip, we *must* keep certain clocks
271 * enabled for the duration of power-domain transitions. Most
272 * transitions are handled by this driver, but some cases (in
273 * particular, DRAM DVFS / memory-controller idle) must be handled by
274 * firmware. Firmware can handle most clock management via a special
275 * "ungate" register (PMU_CRU_GATEDIS_CON0), but unfortunately, this
276 * doesn't handle PLLs. We can assist this transition by doing the
277 * clock management on behalf of firmware.
278 */
279 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
280 genpd = pmu->genpd_data.domains[i];
281 if (genpd) {
282 pd = to_rockchip_pd(genpd);
283 ret = clk_bulk_enable(pd->num_clks, pd->clks);
284 if (ret < 0) {
285 dev_err(pmu->dev,
286 "failed to enable clks for domain '%s': %d\n",
287 genpd->name, ret);
288 goto err;
289 }
290 }
291 }
292
293 return 0;
294
295 err:
296 for (i = i - 1; i >= 0; i--) {
297 genpd = pmu->genpd_data.domains[i];
298 if (genpd) {
299 pd = to_rockchip_pd(genpd);
300 clk_bulk_disable(pd->num_clks, pd->clks);
301 }
302 }
303 mutex_unlock(&pmu->mutex);
304 mutex_unlock(&dmc_pmu_mutex);
305
306 return ret;
307 }
308 EXPORT_SYMBOL_GPL(rockchip_pmu_block);
309
310 /* Unblock PMU transitions. */
rockchip_pmu_unblock(void)311 void rockchip_pmu_unblock(void)
312 {
313 struct rockchip_pmu *pmu;
314 struct generic_pm_domain *genpd;
315 struct rockchip_pm_domain *pd;
316 int i;
317
318 if (dmc_pmu) {
319 pmu = dmc_pmu;
320 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
321 genpd = pmu->genpd_data.domains[i];
322 if (genpd) {
323 pd = to_rockchip_pd(genpd);
324 clk_bulk_disable(pd->num_clks, pd->clks);
325 }
326 }
327
328 mutex_unlock(&pmu->mutex);
329 }
330
331 mutex_unlock(&dmc_pmu_mutex);
332 }
333 EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);
334
335 #define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup, regulator) \
336 DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup, regulator)
337
rockchip_pmu_domain_is_idle(struct rockchip_pm_domain * pd)338 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
339 {
340 struct rockchip_pmu *pmu = pd->pmu;
341 const struct rockchip_domain_info *pd_info = pd->info;
342 unsigned int val;
343
344 regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
345 return (val & pd_info->idle_mask) == pd_info->idle_mask;
346 }
347
rockchip_pmu_read_ack(struct rockchip_pmu * pmu)348 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
349 {
350 unsigned int val;
351
352 regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
353 return val;
354 }
355
rockchip_pmu_ungate_clk(struct rockchip_pm_domain * pd,bool ungate)356 static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ungate)
357 {
358 const struct rockchip_domain_info *pd_info = pd->info;
359 struct rockchip_pmu *pmu = pd->pmu;
360 unsigned int val;
361 int clk_ungate_w_mask = pd_info->clk_ungate_mask << 16;
362
363 if (!pd_info->clk_ungate_mask)
364 return 0;
365
366 if (!pmu->info->clk_ungate_offset)
367 return 0;
368
369 val = ungate ? (pd_info->clk_ungate_mask | clk_ungate_w_mask) :
370 clk_ungate_w_mask;
371 regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val);
372
373 return 0;
374 }
375
rockchip_pmu_set_idle_request(struct rockchip_pm_domain * pd,bool idle)376 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
377 bool idle)
378 {
379 const struct rockchip_domain_info *pd_info = pd->info;
380 struct generic_pm_domain *genpd = &pd->genpd;
381 struct rockchip_pmu *pmu = pd->pmu;
382 u32 pd_req_offset = pd_info->req_offset;
383 unsigned int target_ack;
384 unsigned int val;
385 bool is_idle;
386 int ret;
387
388 if (pd_info->req_mask == 0)
389 return 0;
390 else if (pd_info->req_w_mask)
391 regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset,
392 idle ? (pd_info->req_mask | pd_info->req_w_mask) :
393 pd_info->req_w_mask);
394 else
395 regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset,
396 pd_info->req_mask, idle ? -1U : 0);
397
398 wmb();
399
400 /* Wait util idle_ack = 1 */
401 target_ack = idle ? pd_info->ack_mask : 0;
402 ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
403 (val & pd_info->ack_mask) == target_ack,
404 0, 10000);
405 if (ret) {
406 dev_err(pmu->dev,
407 "failed to get ack on domain '%s', val=0x%x\n",
408 genpd->name, val);
409 return ret;
410 }
411
412 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
413 is_idle, is_idle == idle, 0, 10000);
414 if (ret) {
415 dev_err(pmu->dev,
416 "failed to set idle on domain '%s', val=%d\n",
417 genpd->name, is_idle);
418 return ret;
419 }
420
421 return 0;
422 }
423
rockchip_pmu_save_qos(struct rockchip_pm_domain * pd)424 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
425 {
426 int i;
427
428 for (i = 0; i < pd->num_qos; i++) {
429 regmap_read(pd->qos_regmap[i],
430 QOS_PRIORITY,
431 &pd->qos_save_regs[0][i]);
432 regmap_read(pd->qos_regmap[i],
433 QOS_MODE,
434 &pd->qos_save_regs[1][i]);
435 regmap_read(pd->qos_regmap[i],
436 QOS_BANDWIDTH,
437 &pd->qos_save_regs[2][i]);
438 regmap_read(pd->qos_regmap[i],
439 QOS_SATURATION,
440 &pd->qos_save_regs[3][i]);
441 regmap_read(pd->qos_regmap[i],
442 QOS_EXTCONTROL,
443 &pd->qos_save_regs[4][i]);
444 }
445 return 0;
446 }
447
rockchip_pmu_restore_qos(struct rockchip_pm_domain * pd)448 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
449 {
450 int i;
451
452 for (i = 0; i < pd->num_qos; i++) {
453 regmap_write(pd->qos_regmap[i],
454 QOS_PRIORITY,
455 pd->qos_save_regs[0][i]);
456 regmap_write(pd->qos_regmap[i],
457 QOS_MODE,
458 pd->qos_save_regs[1][i]);
459 regmap_write(pd->qos_regmap[i],
460 QOS_BANDWIDTH,
461 pd->qos_save_regs[2][i]);
462 regmap_write(pd->qos_regmap[i],
463 QOS_SATURATION,
464 pd->qos_save_regs[3][i]);
465 regmap_write(pd->qos_regmap[i],
466 QOS_EXTCONTROL,
467 pd->qos_save_regs[4][i]);
468 }
469
470 return 0;
471 }
472
rockchip_pmu_domain_is_on(struct rockchip_pm_domain * pd)473 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
474 {
475 struct rockchip_pmu *pmu = pd->pmu;
476 unsigned int val;
477
478 if (pd->info->repair_status_mask) {
479 regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val);
480 /* 1'b1: power on, 1'b0: power off */
481 return val & pd->info->repair_status_mask;
482 }
483
484 /* check idle status for idle-only domains */
485 if (pd->info->status_mask == 0)
486 return !rockchip_pmu_domain_is_idle(pd);
487
488 regmap_read(pmu->regmap, pmu->info->status_offset, &val);
489
490 /* 1'b0: power on, 1'b1: power off */
491 return !(val & pd->info->status_mask);
492 }
493
rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain * pd)494 static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
495 {
496 struct rockchip_pmu *pmu = pd->pmu;
497 unsigned int val;
498
499 regmap_read(pmu->regmap,
500 pmu->info->mem_status_offset + pd->info->mem_offset, &val);
501
502 /* 1'b0: power on, 1'b1: power off */
503 return !(val & pd->info->mem_status_mask);
504 }
505
rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain * pd)506 static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
507 {
508 struct rockchip_pmu *pmu = pd->pmu;
509 unsigned int val;
510
511 regmap_read(pmu->regmap,
512 pmu->info->chain_status_offset + pd->info->mem_offset, &val);
513
514 /* 1'b1: power on, 1'b0: power off */
515 return val & pd->info->mem_status_mask;
516 }
517
rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain * pd)518 static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
519 {
520 struct rockchip_pmu *pmu = pd->pmu;
521 struct generic_pm_domain *genpd = &pd->genpd;
522 bool is_on;
523 int ret = 0;
524
525 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
526 is_on == true, 0, 10000);
527 if (ret) {
528 dev_err(pmu->dev,
529 "failed to get chain status '%s', target_on=1, val=%d\n",
530 genpd->name, is_on);
531 goto error;
532 }
533
534 udelay(20);
535
536 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
537 (pd->info->pwr_mask | pd->info->pwr_w_mask));
538 wmb();
539
540 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
541 is_on == false, 0, 10000);
542 if (ret) {
543 dev_err(pmu->dev,
544 "failed to get mem status '%s', target_on=0, val=%d\n",
545 genpd->name, is_on);
546 goto error;
547 }
548
549 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
550 pd->info->pwr_w_mask);
551 wmb();
552
553 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
554 is_on == true, 0, 10000);
555 if (ret) {
556 dev_err(pmu->dev,
557 "failed to get mem status '%s', target_on=1, val=%d\n",
558 genpd->name, is_on);
559 }
560
561 error:
562 return ret;
563 }
564
rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain * pd,bool on)565 static int rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
566 bool on)
567 {
568 struct rockchip_pmu *pmu = pd->pmu;
569 struct generic_pm_domain *genpd = &pd->genpd;
570 u32 pd_pwr_offset = pd->info->pwr_offset;
571 bool is_on, is_mem_on = false;
572 struct arm_smccc_res res;
573 int ret;
574
575 if (pd->info->pwr_mask == 0)
576 return 0;
577
578 if (on && pd->info->mem_status_mask)
579 is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
580
581 if (pd->info->pwr_w_mask)
582 regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
583 on ? pd->info->pwr_w_mask :
584 (pd->info->pwr_mask | pd->info->pwr_w_mask));
585 else
586 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
587 pd->info->pwr_mask, on ? 0 : -1U);
588
589 wmb();
590
591 if (is_mem_on) {
592 ret = rockchip_pmu_domain_mem_reset(pd);
593 if (ret)
594 return ret;
595 }
596
597
598 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
599 is_on == on, 0, 10000);
600 if (ret) {
601 dev_err(pmu->dev, "failed to set domain '%s' %s, val=%d\n",
602 genpd->name, on ? "on" : "off", is_on);
603 return ret;
604 }
605
606 /* Inform firmware to keep this pd on or off */
607 if (arm_smccc_1_1_get_conduit() != SMCCC_CONDUIT_NONE)
608 arm_smccc_smc(ROCKCHIP_SIP_SUSPEND_MODE, ROCKCHIP_SLEEP_PD_CONFIG,
609 pmu->info->pwr_offset + pd_pwr_offset,
610 pd->info->pwr_mask, on, 0, 0, 0, &res);
611
612 return 0;
613 }
614
rockchip_pd_power(struct rockchip_pm_domain * pd,bool power_on)615 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
616 {
617 struct rockchip_pmu *pmu = pd->pmu;
618 int ret;
619
620 guard(mutex)(&pmu->mutex);
621
622 if (rockchip_pmu_domain_is_on(pd) == power_on)
623 return 0;
624
625 ret = clk_bulk_enable(pd->num_clks, pd->clks);
626 if (ret < 0) {
627 dev_err(pmu->dev, "failed to enable clocks\n");
628 return ret;
629 }
630
631 rockchip_pmu_ungate_clk(pd, true);
632
633 if (!power_on) {
634 rockchip_pmu_save_qos(pd);
635
636 /* if powering down, idle request to NIU first */
637 ret = rockchip_pmu_set_idle_request(pd, true);
638 if (ret < 0)
639 goto out;
640 }
641
642 ret = rockchip_do_pmu_set_power_domain(pd, power_on);
643 if (ret < 0)
644 goto out;
645
646 if (power_on) {
647 /* if powering up, leave idle mode */
648 ret = rockchip_pmu_set_idle_request(pd, false);
649 if (ret < 0)
650 goto out;
651
652 rockchip_pmu_restore_qos(pd);
653 }
654
655 out:
656 rockchip_pmu_ungate_clk(pd, false);
657 clk_bulk_disable(pd->num_clks, pd->clks);
658
659 return ret;
660 }
661
rockchip_pd_regulator_disable(struct rockchip_pm_domain * pd)662 static int rockchip_pd_regulator_disable(struct rockchip_pm_domain *pd)
663 {
664 return IS_ERR_OR_NULL(pd->supply) ? 0 : regulator_disable(pd->supply);
665 }
666
rockchip_pd_regulator_enable(struct rockchip_pm_domain * pd)667 static int rockchip_pd_regulator_enable(struct rockchip_pm_domain *pd)
668 {
669 struct rockchip_pmu *pmu = pd->pmu;
670
671 if (!pd->info->need_regulator)
672 return 0;
673
674 if (IS_ERR_OR_NULL(pd->supply)) {
675 pd->supply = devm_of_regulator_get(pmu->dev, pd->node, "domain");
676
677 if (IS_ERR(pd->supply))
678 return PTR_ERR(pd->supply);
679 }
680
681 return regulator_enable(pd->supply);
682 }
683
rockchip_pd_power_on(struct generic_pm_domain * domain)684 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
685 {
686 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
687 int ret;
688
689 ret = rockchip_pd_regulator_enable(pd);
690 if (ret) {
691 dev_err(pd->pmu->dev, "Failed to enable supply: %d\n", ret);
692 return ret;
693 }
694
695 ret = rockchip_pd_power(pd, true);
696 if (ret)
697 rockchip_pd_regulator_disable(pd);
698
699 return ret;
700 }
701
rockchip_pd_power_off(struct generic_pm_domain * domain)702 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
703 {
704 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
705 int ret;
706
707 ret = rockchip_pd_power(pd, false);
708 if (ret)
709 return ret;
710
711 rockchip_pd_regulator_disable(pd);
712 return ret;
713 }
714
rockchip_pd_attach_dev(struct generic_pm_domain * genpd,struct device * dev)715 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
716 struct device *dev)
717 {
718 struct clk *clk;
719 int i;
720 int error;
721
722 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
723
724 error = pm_clk_create(dev);
725 if (error) {
726 dev_err(dev, "pm_clk_create failed %d\n", error);
727 return error;
728 }
729
730 i = 0;
731 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
732 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
733 error = pm_clk_add_clk(dev, clk);
734 if (error) {
735 dev_err(dev, "pm_clk_add_clk failed %d\n", error);
736 clk_put(clk);
737 pm_clk_destroy(dev);
738 return error;
739 }
740 }
741
742 return 0;
743 }
744
rockchip_pd_detach_dev(struct generic_pm_domain * genpd,struct device * dev)745 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
746 struct device *dev)
747 {
748 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
749
750 pm_clk_destroy(dev);
751 }
752
rockchip_pm_add_one_domain(struct rockchip_pmu * pmu,struct device_node * node)753 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
754 struct device_node *node)
755 {
756 const struct rockchip_domain_info *pd_info;
757 struct rockchip_pm_domain *pd;
758 struct device_node *qos_node;
759 int i, j;
760 u32 id;
761 int error;
762
763 error = of_property_read_u32(node, "reg", &id);
764 if (error) {
765 dev_err(pmu->dev,
766 "%pOFn: failed to retrieve domain id (reg): %d\n",
767 node, error);
768 return -EINVAL;
769 }
770
771 if (id >= pmu->info->num_domains) {
772 dev_err(pmu->dev, "%pOFn: invalid domain id %d\n",
773 node, id);
774 return -EINVAL;
775 }
776 /* RK3588 has domains with two parents (RKVDEC0/RKVDEC1) */
777 if (pmu->genpd_data.domains[id])
778 return 0;
779
780 pd_info = &pmu->info->domain_info[id];
781 if (!pd_info) {
782 dev_err(pmu->dev, "%pOFn: undefined domain id %d\n",
783 node, id);
784 return -EINVAL;
785 }
786
787 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL);
788 if (!pd)
789 return -ENOMEM;
790
791 pd->info = pd_info;
792 pd->pmu = pmu;
793 pd->node = node;
794
795 pd->num_clks = of_clk_get_parent_count(node);
796 if (pd->num_clks > 0) {
797 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
798 sizeof(*pd->clks), GFP_KERNEL);
799 if (!pd->clks)
800 return -ENOMEM;
801 } else {
802 dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n",
803 node, pd->num_clks);
804 pd->num_clks = 0;
805 }
806
807 for (i = 0; i < pd->num_clks; i++) {
808 pd->clks[i].clk = of_clk_get(node, i);
809 if (IS_ERR(pd->clks[i].clk)) {
810 error = PTR_ERR(pd->clks[i].clk);
811 dev_err(pmu->dev,
812 "%pOFn: failed to get clk at index %d: %d\n",
813 node, i, error);
814 return error;
815 }
816 }
817
818 error = clk_bulk_prepare(pd->num_clks, pd->clks);
819 if (error)
820 goto err_put_clocks;
821
822 pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
823 NULL);
824
825 if (pd->num_qos > 0) {
826 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
827 sizeof(*pd->qos_regmap),
828 GFP_KERNEL);
829 if (!pd->qos_regmap) {
830 error = -ENOMEM;
831 goto err_unprepare_clocks;
832 }
833
834 for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
835 pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
836 pd->num_qos,
837 sizeof(u32),
838 GFP_KERNEL);
839 if (!pd->qos_save_regs[j]) {
840 error = -ENOMEM;
841 goto err_unprepare_clocks;
842 }
843 }
844
845 for (j = 0; j < pd->num_qos; j++) {
846 qos_node = of_parse_phandle(node, "pm_qos", j);
847 if (!qos_node) {
848 error = -ENODEV;
849 goto err_unprepare_clocks;
850 }
851 pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
852 of_node_put(qos_node);
853 if (IS_ERR(pd->qos_regmap[j])) {
854 error = -ENODEV;
855 goto err_unprepare_clocks;
856 }
857 }
858 }
859
860 if (pd->info->name)
861 pd->genpd.name = pd->info->name;
862 else
863 pd->genpd.name = kbasename(node->full_name);
864 pd->genpd.power_off = rockchip_pd_power_off;
865 pd->genpd.power_on = rockchip_pd_power_on;
866 pd->genpd.attach_dev = rockchip_pd_attach_dev;
867 pd->genpd.detach_dev = rockchip_pd_detach_dev;
868 pd->genpd.flags = GENPD_FLAG_PM_CLK;
869 if (pd_info->active_wakeup)
870 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
871 pm_genpd_init(&pd->genpd, NULL,
872 !rockchip_pmu_domain_is_on(pd) ||
873 (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd)));
874
875 pmu->genpd_data.domains[id] = &pd->genpd;
876 return 0;
877
878 err_unprepare_clocks:
879 clk_bulk_unprepare(pd->num_clks, pd->clks);
880 err_put_clocks:
881 clk_bulk_put(pd->num_clks, pd->clks);
882 return error;
883 }
884
rockchip_pm_remove_one_domain(struct rockchip_pm_domain * pd)885 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
886 {
887 int ret;
888
889 /*
890 * We're in the error cleanup already, so we only complain,
891 * but won't emit another error on top of the original one.
892 */
893 ret = pm_genpd_remove(&pd->genpd);
894 if (ret < 0)
895 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n",
896 pd->genpd.name, ret);
897
898 clk_bulk_unprepare(pd->num_clks, pd->clks);
899 clk_bulk_put(pd->num_clks, pd->clks);
900
901 /* protect the zeroing of pm->num_clks */
902 mutex_lock(&pd->pmu->mutex);
903 pd->num_clks = 0;
904 mutex_unlock(&pd->pmu->mutex);
905
906 /* devm will free our memory */
907 }
908
rockchip_pm_domain_cleanup(struct rockchip_pmu * pmu)909 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
910 {
911 struct generic_pm_domain *genpd;
912 struct rockchip_pm_domain *pd;
913 int i;
914
915 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
916 genpd = pmu->genpd_data.domains[i];
917 if (genpd) {
918 pd = to_rockchip_pd(genpd);
919 rockchip_pm_remove_one_domain(pd);
920 }
921 }
922
923 /* devm will free our memory */
924 }
925
rockchip_configure_pd_cnt(struct rockchip_pmu * pmu,u32 domain_reg_offset,unsigned int count)926 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
927 u32 domain_reg_offset,
928 unsigned int count)
929 {
930 /* First configure domain power down transition count ... */
931 regmap_write(pmu->regmap, domain_reg_offset, count);
932 /* ... and then power up count. */
933 regmap_write(pmu->regmap, domain_reg_offset + 4, count);
934 }
935
rockchip_pm_add_subdomain(struct rockchip_pmu * pmu,struct device_node * parent)936 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
937 struct device_node *parent)
938 {
939 struct generic_pm_domain *child_domain, *parent_domain;
940 int error;
941
942 for_each_child_of_node_scoped(parent, np) {
943 u32 idx;
944
945 error = of_property_read_u32(parent, "reg", &idx);
946 if (error) {
947 dev_err(pmu->dev,
948 "%pOFn: failed to retrieve domain id (reg): %d\n",
949 parent, error);
950 return error;
951 }
952 parent_domain = pmu->genpd_data.domains[idx];
953
954 error = rockchip_pm_add_one_domain(pmu, np);
955 if (error) {
956 dev_err(pmu->dev, "failed to handle node %pOFn: %d\n",
957 np, error);
958 return error;
959 }
960
961 error = of_property_read_u32(np, "reg", &idx);
962 if (error) {
963 dev_err(pmu->dev,
964 "%pOFn: failed to retrieve domain id (reg): %d\n",
965 np, error);
966 return error;
967 }
968 child_domain = pmu->genpd_data.domains[idx];
969
970 error = pm_genpd_add_subdomain(parent_domain, child_domain);
971 if (error) {
972 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
973 parent_domain->name, child_domain->name, error);
974 return error;
975 } else {
976 dev_dbg(pmu->dev, "%s add subdomain: %s\n",
977 parent_domain->name, child_domain->name);
978 }
979
980 rockchip_pm_add_subdomain(pmu, np);
981 }
982
983 return 0;
984 }
985
rockchip_pm_domain_probe(struct platform_device * pdev)986 static int rockchip_pm_domain_probe(struct platform_device *pdev)
987 {
988 struct device *dev = &pdev->dev;
989 struct device_node *np = dev->of_node;
990 struct device *parent;
991 struct rockchip_pmu *pmu;
992 const struct rockchip_pmu_info *pmu_info;
993 int error;
994
995 if (!np) {
996 dev_err(dev, "device tree node not found\n");
997 return -ENODEV;
998 }
999
1000 pmu_info = device_get_match_data(dev);
1001
1002 pmu = devm_kzalloc(dev,
1003 struct_size(pmu, domains, pmu_info->num_domains),
1004 GFP_KERNEL);
1005 if (!pmu)
1006 return -ENOMEM;
1007
1008 pmu->dev = &pdev->dev;
1009 mutex_init(&pmu->mutex);
1010
1011 pmu->info = pmu_info;
1012
1013 pmu->genpd_data.domains = pmu->domains;
1014 pmu->genpd_data.num_domains = pmu_info->num_domains;
1015
1016 parent = dev->parent;
1017 if (!parent) {
1018 dev_err(dev, "no parent for syscon devices\n");
1019 return -ENODEV;
1020 }
1021
1022 pmu->regmap = syscon_node_to_regmap(parent->of_node);
1023 if (IS_ERR(pmu->regmap)) {
1024 dev_err(dev, "no regmap available\n");
1025 return PTR_ERR(pmu->regmap);
1026 }
1027
1028 /*
1029 * Configure power up and down transition delays for CORE
1030 * and GPU domains.
1031 */
1032 if (pmu_info->core_power_transition_time)
1033 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
1034 pmu_info->core_power_transition_time);
1035 if (pmu_info->gpu_pwrcnt_offset)
1036 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
1037 pmu_info->gpu_power_transition_time);
1038
1039 error = -ENODEV;
1040
1041 /*
1042 * Prevent any rockchip_pmu_block() from racing with the remainder of
1043 * setup (clocks, register initialization).
1044 */
1045 guard(mutex)(&dmc_pmu_mutex);
1046
1047 for_each_available_child_of_node_scoped(np, node) {
1048 error = rockchip_pm_add_one_domain(pmu, node);
1049 if (error) {
1050 dev_err(dev, "failed to handle node %pOFn: %d\n",
1051 node, error);
1052 goto err_out;
1053 }
1054
1055 error = rockchip_pm_add_subdomain(pmu, node);
1056 if (error < 0) {
1057 dev_err(dev, "failed to handle subdomain node %pOFn: %d\n",
1058 node, error);
1059 goto err_out;
1060 }
1061 }
1062
1063 if (error) {
1064 dev_dbg(dev, "no power domains defined\n");
1065 goto err_out;
1066 }
1067
1068 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
1069 if (error) {
1070 dev_err(dev, "failed to add provider: %d\n", error);
1071 goto err_out;
1072 }
1073
1074 /* We only expect one PMU. */
1075 if (!WARN_ON_ONCE(dmc_pmu))
1076 dmc_pmu = pmu;
1077
1078 return 0;
1079
1080 err_out:
1081 rockchip_pm_domain_cleanup(pmu);
1082 return error;
1083 }
1084
1085 static const struct rockchip_domain_info px30_pm_domains[] = {
1086 [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false),
1087 [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false),
1088 [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false),
1089 [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false),
1090 [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false),
1091 [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false),
1092 [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false),
1093 [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
1094 };
1095
1096 static const struct rockchip_domain_info rv1126_pm_domains[] = {
1097 [RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false),
1098 [RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false),
1099 [RV1126_PD_VO] = DOMAIN_RV1126("vo", BIT(5), BIT(7), BIT(7), false),
1100 [RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false),
1101 [RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
1102 [RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false),
1103 [RV1126_PD_SDIO] = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13), false),
1104 [RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), false),
1105 };
1106
1107 static const struct rockchip_domain_info rk3036_pm_domains[] = {
1108 [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
1109 [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
1110 [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false),
1111 [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false),
1112 [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false),
1113 [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false),
1114 [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false),
1115 };
1116
1117 static const struct rockchip_domain_info rk3066_pm_domains[] = {
1118 [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
1119 [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
1120 [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
1121 [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
1122 [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false),
1123 };
1124
1125 static const struct rockchip_domain_info rk3128_pm_domains[] = {
1126 [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false),
1127 [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true),
1128 [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false),
1129 [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
1130 [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false),
1131 };
1132
1133 static const struct rockchip_domain_info rk3188_pm_domains[] = {
1134 [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
1135 [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
1136 [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
1137 [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
1138 [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false),
1139 };
1140
1141 static const struct rockchip_domain_info rk3228_pm_domains[] = {
1142 [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true),
1143 [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true),
1144 [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true),
1145 [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true),
1146 [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false),
1147 [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false),
1148 [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false),
1149 [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false),
1150 [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false),
1151 [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true),
1152 [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false),
1153 };
1154
1155 static const struct rockchip_domain_info rk3288_pm_domains[] = {
1156 [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false),
1157 [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false),
1158 [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false),
1159 [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false),
1160 };
1161
1162 static const struct rockchip_domain_info rk3328_pm_domains[] = {
1163 [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false),
1164 [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false),
1165 [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true),
1166 [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true),
1167 [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true),
1168 [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
1169 [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false),
1170 [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false),
1171 [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false),
1172 };
1173
1174 static const struct rockchip_domain_info rk3366_pm_domains[] = {
1175 [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true),
1176 [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false),
1177 [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false),
1178 [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false),
1179 [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false),
1180 [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false),
1181 [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false),
1182 };
1183
1184 static const struct rockchip_domain_info rk3368_pm_domains[] = {
1185 [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true),
1186 [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false),
1187 [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false),
1188 [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false),
1189 [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false),
1190 };
1191
1192 static const struct rockchip_domain_info rk3399_pm_domains[] = {
1193 [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false),
1194 [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false),
1195 [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true),
1196 [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true),
1197 [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true),
1198 [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true),
1199 [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true),
1200 [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true),
1201 [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false),
1202 [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false),
1203 [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false),
1204 [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false),
1205 [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false),
1206 [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false),
1207 [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false),
1208 [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false),
1209 [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false),
1210 [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false),
1211 [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false),
1212 [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false),
1213 [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true),
1214 [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true),
1215 [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true),
1216 [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false),
1217 [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true),
1218 [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true),
1219 [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
1220 };
1221
1222 static const struct rockchip_domain_info rk3528_pm_domains[] = {
1223 [RK3528_PD_GPU] = DOMAIN_RK3528("gpu", BIT(0), BIT(4)),
1224 [RK3528_PD_RKVDEC] = DOMAIN_RK3528("vdec", 0, BIT(5)),
1225 [RK3528_PD_RKVENC] = DOMAIN_RK3528("venc", 0, BIT(6)),
1226 [RK3528_PD_VO] = DOMAIN_RK3528("vo", 0, BIT(7)),
1227 [RK3528_PD_VPU] = DOMAIN_RK3528("vpu", 0, BIT(8)),
1228 };
1229
1230 static const struct rockchip_domain_info rk3562_pm_domains[] = {
1231 /* name pwr req g_mask mem wakeup */
1232 [RK3562_PD_GPU] = DOMAIN_RK3562("gpu", BIT(0), BIT(1), BIT(1), 0, false),
1233 [RK3562_PD_NPU] = DOMAIN_RK3562("npu", BIT(1), BIT(2), BIT(2), 0, false),
1234 [RK3562_PD_VDPU] = DOMAIN_RK3562("vdpu", BIT(2), BIT(6), BIT(6), 0, false),
1235 [RK3562_PD_VEPU] = DOMAIN_RK3562("vepu", BIT(3), BIT(7), BIT(7) | BIT(3), 0, false),
1236 [RK3562_PD_RGA] = DOMAIN_RK3562("rga", BIT(4), BIT(5), BIT(5) | BIT(4), 0, false),
1237 [RK3562_PD_VI] = DOMAIN_RK3562("vi", BIT(5), BIT(3), BIT(3), 0, false),
1238 [RK3562_PD_VO] = DOMAIN_RK3562("vo", BIT(6), BIT(4), BIT(4), 16, false),
1239 [RK3562_PD_PHP] = DOMAIN_RK3562("php", BIT(7), BIT(8), BIT(8), 0, false),
1240 };
1241
1242 static const struct rockchip_domain_info rk3568_pm_domains[] = {
1243 [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
1244 [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
1245 [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false),
1246 [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false),
1247 [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false),
1248 [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false),
1249 [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false),
1250 [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false),
1251 [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
1252 };
1253
1254 static const struct rockchip_domain_info rk3576_pm_domains[] = {
1255 [RK3576_PD_NPU] = DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, 0x0, 0, 0, 0, false),
1256 [RK3576_PD_NVM] = DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6), 0x4, BIT(2), BIT(18), BIT(2), false),
1257 [RK3576_PD_SDGMAC] = DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(7), 0x4, BIT(1), BIT(17), 0x6, false),
1258 [RK3576_PD_AUDIO] = DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8), 0x4, BIT(0), BIT(16), BIT(0), false),
1259 [RK3576_PD_PHP] = DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9), 0x0, BIT(15), BIT(15), BIT(15), false),
1260 [RK3576_PD_SUBPHP] = DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(10), 0x0, 0, 0, 0, false),
1261 [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, false),
1262 [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, false),
1263 [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, false),
1264 [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, true),
1265 [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), false),
1266 [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, false),
1267 [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), false),
1268 [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), false),
1269 [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), false),
1270 [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, 0x18, false),
1271 [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, false),
1272 [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, false),
1273 [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false),
1274 };
1275
1276 static const struct rockchip_domain_info rk3588_pm_domains[] = {
1277 [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false, true),
1278 [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false, true),
1279 [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false, false),
1280 [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false, false),
1281 [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false, false),
1282 [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false, false),
1283 [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false, false),
1284 [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false, false),
1285 [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false, false),
1286 [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false, false),
1287 [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false, false),
1288 [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false, false),
1289 [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false, false),
1290 [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false, false),
1291 [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false, false),
1292 [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false, false),
1293 [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false, false),
1294 [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false, false),
1295 [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false, false),
1296 [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false, false),
1297 [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false, false),
1298 [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false, false),
1299 [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false, false),
1300 [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true, false),
1301 [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false, false),
1302 [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false, false),
1303 [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false, false),
1304 [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true, false),
1305 [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false, false),
1306 };
1307
1308 static const struct rockchip_pmu_info px30_pmu = {
1309 .pwr_offset = 0x18,
1310 .status_offset = 0x20,
1311 .req_offset = 0x64,
1312 .idle_offset = 0x6c,
1313 .ack_offset = 0x6c,
1314
1315 .num_domains = ARRAY_SIZE(px30_pm_domains),
1316 .domain_info = px30_pm_domains,
1317 };
1318
1319 static const struct rockchip_pmu_info rk3036_pmu = {
1320 .req_offset = 0x148,
1321 .idle_offset = 0x14c,
1322 .ack_offset = 0x14c,
1323
1324 .num_domains = ARRAY_SIZE(rk3036_pm_domains),
1325 .domain_info = rk3036_pm_domains,
1326 };
1327
1328 static const struct rockchip_pmu_info rk3066_pmu = {
1329 .pwr_offset = 0x08,
1330 .status_offset = 0x0c,
1331 .req_offset = 0x38, /* PMU_MISC_CON1 */
1332 .idle_offset = 0x0c,
1333 .ack_offset = 0x0c,
1334
1335 .num_domains = ARRAY_SIZE(rk3066_pm_domains),
1336 .domain_info = rk3066_pm_domains,
1337 };
1338
1339 static const struct rockchip_pmu_info rk3128_pmu = {
1340 .pwr_offset = 0x04,
1341 .status_offset = 0x08,
1342 .req_offset = 0x0c,
1343 .idle_offset = 0x10,
1344 .ack_offset = 0x10,
1345
1346 .num_domains = ARRAY_SIZE(rk3128_pm_domains),
1347 .domain_info = rk3128_pm_domains,
1348 };
1349
1350 static const struct rockchip_pmu_info rk3188_pmu = {
1351 .pwr_offset = 0x08,
1352 .status_offset = 0x0c,
1353 .req_offset = 0x38, /* PMU_MISC_CON1 */
1354 .idle_offset = 0x0c,
1355 .ack_offset = 0x0c,
1356
1357 .num_domains = ARRAY_SIZE(rk3188_pm_domains),
1358 .domain_info = rk3188_pm_domains,
1359 };
1360
1361 static const struct rockchip_pmu_info rk3228_pmu = {
1362 .req_offset = 0x40c,
1363 .idle_offset = 0x488,
1364 .ack_offset = 0x488,
1365
1366 .num_domains = ARRAY_SIZE(rk3228_pm_domains),
1367 .domain_info = rk3228_pm_domains,
1368 };
1369
1370 static const struct rockchip_pmu_info rk3288_pmu = {
1371 .pwr_offset = 0x08,
1372 .status_offset = 0x0c,
1373 .req_offset = 0x10,
1374 .idle_offset = 0x14,
1375 .ack_offset = 0x14,
1376
1377 .core_pwrcnt_offset = 0x34,
1378 .gpu_pwrcnt_offset = 0x3c,
1379
1380 .core_power_transition_time = 24, /* 1us */
1381 .gpu_power_transition_time = 24, /* 1us */
1382
1383 .num_domains = ARRAY_SIZE(rk3288_pm_domains),
1384 .domain_info = rk3288_pm_domains,
1385 };
1386
1387 static const struct rockchip_pmu_info rk3328_pmu = {
1388 .req_offset = 0x414,
1389 .idle_offset = 0x484,
1390 .ack_offset = 0x484,
1391
1392 .num_domains = ARRAY_SIZE(rk3328_pm_domains),
1393 .domain_info = rk3328_pm_domains,
1394 };
1395
1396 static const struct rockchip_pmu_info rk3366_pmu = {
1397 .pwr_offset = 0x0c,
1398 .status_offset = 0x10,
1399 .req_offset = 0x3c,
1400 .idle_offset = 0x40,
1401 .ack_offset = 0x40,
1402
1403 .core_pwrcnt_offset = 0x48,
1404 .gpu_pwrcnt_offset = 0x50,
1405
1406 .core_power_transition_time = 24,
1407 .gpu_power_transition_time = 24,
1408
1409 .num_domains = ARRAY_SIZE(rk3366_pm_domains),
1410 .domain_info = rk3366_pm_domains,
1411 };
1412
1413 static const struct rockchip_pmu_info rk3368_pmu = {
1414 .pwr_offset = 0x0c,
1415 .status_offset = 0x10,
1416 .req_offset = 0x3c,
1417 .idle_offset = 0x40,
1418 .ack_offset = 0x40,
1419
1420 .core_pwrcnt_offset = 0x48,
1421 .gpu_pwrcnt_offset = 0x50,
1422
1423 .core_power_transition_time = 24,
1424 .gpu_power_transition_time = 24,
1425
1426 .num_domains = ARRAY_SIZE(rk3368_pm_domains),
1427 .domain_info = rk3368_pm_domains,
1428 };
1429
1430 static const struct rockchip_pmu_info rk3399_pmu = {
1431 .pwr_offset = 0x14,
1432 .status_offset = 0x18,
1433 .req_offset = 0x60,
1434 .idle_offset = 0x64,
1435 .ack_offset = 0x68,
1436
1437 /* ARM Trusted Firmware manages power transition times */
1438
1439 .num_domains = ARRAY_SIZE(rk3399_pm_domains),
1440 .domain_info = rk3399_pm_domains,
1441 };
1442
1443 static const struct rockchip_pmu_info rk3528_pmu = {
1444 .pwr_offset = 0x1210,
1445 .status_offset = 0x1230,
1446 .req_offset = 0x1110,
1447 .idle_offset = 0x1128,
1448 .ack_offset = 0x1120,
1449
1450 .num_domains = ARRAY_SIZE(rk3528_pm_domains),
1451 .domain_info = rk3528_pm_domains,
1452 };
1453
1454 static const struct rockchip_pmu_info rk3562_pmu = {
1455 .pwr_offset = 0x210,
1456 .status_offset = 0x230,
1457 .req_offset = 0x110,
1458 .idle_offset = 0x128,
1459 .ack_offset = 0x120,
1460 .clk_ungate_offset = 0x140,
1461
1462 .num_domains = ARRAY_SIZE(rk3562_pm_domains),
1463 .domain_info = rk3562_pm_domains,
1464 };
1465
1466 static const struct rockchip_pmu_info rk3568_pmu = {
1467 .pwr_offset = 0xa0,
1468 .status_offset = 0x98,
1469 .req_offset = 0x50,
1470 .idle_offset = 0x68,
1471 .ack_offset = 0x60,
1472
1473 .num_domains = ARRAY_SIZE(rk3568_pm_domains),
1474 .domain_info = rk3568_pm_domains,
1475 };
1476
1477 static const struct rockchip_pmu_info rk3576_pmu = {
1478 .pwr_offset = 0x210,
1479 .status_offset = 0x230,
1480 .chain_status_offset = 0x248,
1481 .mem_status_offset = 0x250,
1482 .mem_pwr_offset = 0x300,
1483 .req_offset = 0x110,
1484 .idle_offset = 0x128,
1485 .ack_offset = 0x120,
1486 .repair_status_offset = 0x570,
1487 .clk_ungate_offset = 0x140,
1488
1489 .num_domains = ARRAY_SIZE(rk3576_pm_domains),
1490 .domain_info = rk3576_pm_domains,
1491 };
1492
1493 static const struct rockchip_pmu_info rk3588_pmu = {
1494 .pwr_offset = 0x14c,
1495 .status_offset = 0x180,
1496 .req_offset = 0x10c,
1497 .idle_offset = 0x120,
1498 .ack_offset = 0x118,
1499 .mem_pwr_offset = 0x1a0,
1500 .chain_status_offset = 0x1f0,
1501 .mem_status_offset = 0x1f8,
1502 .repair_status_offset = 0x290,
1503
1504 .num_domains = ARRAY_SIZE(rk3588_pm_domains),
1505 .domain_info = rk3588_pm_domains,
1506 };
1507
1508 static const struct rockchip_pmu_info rv1126_pmu = {
1509 .pwr_offset = 0x110,
1510 .status_offset = 0x108,
1511 .req_offset = 0xc0,
1512 .idle_offset = 0xd8,
1513 .ack_offset = 0xd0,
1514
1515 .num_domains = ARRAY_SIZE(rv1126_pm_domains),
1516 .domain_info = rv1126_pm_domains,
1517 };
1518
1519 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
1520 {
1521 .compatible = "rockchip,px30-power-controller",
1522 .data = (void *)&px30_pmu,
1523 },
1524 {
1525 .compatible = "rockchip,rk3036-power-controller",
1526 .data = (void *)&rk3036_pmu,
1527 },
1528 {
1529 .compatible = "rockchip,rk3066-power-controller",
1530 .data = (void *)&rk3066_pmu,
1531 },
1532 {
1533 .compatible = "rockchip,rk3128-power-controller",
1534 .data = (void *)&rk3128_pmu,
1535 },
1536 {
1537 .compatible = "rockchip,rk3188-power-controller",
1538 .data = (void *)&rk3188_pmu,
1539 },
1540 {
1541 .compatible = "rockchip,rk3228-power-controller",
1542 .data = (void *)&rk3228_pmu,
1543 },
1544 {
1545 .compatible = "rockchip,rk3288-power-controller",
1546 .data = (void *)&rk3288_pmu,
1547 },
1548 {
1549 .compatible = "rockchip,rk3328-power-controller",
1550 .data = (void *)&rk3328_pmu,
1551 },
1552 {
1553 .compatible = "rockchip,rk3366-power-controller",
1554 .data = (void *)&rk3366_pmu,
1555 },
1556 {
1557 .compatible = "rockchip,rk3368-power-controller",
1558 .data = (void *)&rk3368_pmu,
1559 },
1560 {
1561 .compatible = "rockchip,rk3399-power-controller",
1562 .data = (void *)&rk3399_pmu,
1563 },
1564 {
1565 .compatible = "rockchip,rk3528-power-controller",
1566 .data = (void *)&rk3528_pmu,
1567 },
1568 {
1569 .compatible = "rockchip,rk3562-power-controller",
1570 .data = (void *)&rk3562_pmu,
1571 },
1572 {
1573 .compatible = "rockchip,rk3568-power-controller",
1574 .data = (void *)&rk3568_pmu,
1575 },
1576 {
1577 .compatible = "rockchip,rk3576-power-controller",
1578 .data = (void *)&rk3576_pmu,
1579 },
1580 {
1581 .compatible = "rockchip,rk3588-power-controller",
1582 .data = (void *)&rk3588_pmu,
1583 },
1584 {
1585 .compatible = "rockchip,rv1126-power-controller",
1586 .data = (void *)&rv1126_pmu,
1587 },
1588 { /* sentinel */ },
1589 };
1590
1591 static struct platform_driver rockchip_pm_domain_driver = {
1592 .probe = rockchip_pm_domain_probe,
1593 .driver = {
1594 .name = "rockchip-pm-domain",
1595 .of_match_table = rockchip_pm_domain_dt_match,
1596 /*
1597 * We can't forcibly eject devices from the power
1598 * domain, so we can't really remove power domains
1599 * once they were added.
1600 */
1601 .suppress_bind_attrs = true,
1602 },
1603 };
1604
rockchip_pm_domain_drv_register(void)1605 static int __init rockchip_pm_domain_drv_register(void)
1606 {
1607 return platform_driver_register(&rockchip_pm_domain_driver);
1608 }
1609 postcore_initcall(rockchip_pm_domain_drv_register);
1610