1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * RISC-V performance counter support.
4 *
5 * Copyright (C) 2021 Western Digital Corporation or its affiliates.
6 *
7 * This code is based on ARM perf event code which is in turn based on
8 * sparc64 and x86 code.
9 */
10
11 #define pr_fmt(fmt) "riscv-pmu-sbi: " fmt
12
13 #include <linux/mod_devicetable.h>
14 #include <linux/perf/riscv_pmu.h>
15 #include <linux/platform_device.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/of_irq.h>
19 #include <linux/of.h>
20 #include <linux/cpu_pm.h>
21 #include <linux/sched/clock.h>
22 #include <linux/soc/andes/irq.h>
23 #include <linux/workqueue.h>
24
25 #include <asm/errata_list.h>
26 #include <asm/sbi.h>
27 #include <asm/cpufeature.h>
28 #include <asm/vendor_extensions.h>
29 #include <asm/vendor_extensions/andes.h>
30
31 #define ALT_SBI_PMU_OVERFLOW(__ovl) \
32 asm volatile(ALTERNATIVE_2( \
33 "csrr %0, " __stringify(CSR_SCOUNTOVF), \
34 "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \
35 THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \
36 CONFIG_ERRATA_THEAD_PMU, \
37 "csrr %0, " __stringify(ANDES_CSR_SCOUNTEROF), \
38 ANDES_VENDOR_ID, \
39 RISCV_ISA_VENDOR_EXT_XANDESPMU + RISCV_VENDOR_EXT_ALTERNATIVES_BASE, \
40 CONFIG_ANDES_CUSTOM_PMU) \
41 : "=r" (__ovl) : \
42 : "memory")
43
44 #define ALT_SBI_PMU_OVF_CLEAR_PENDING(__irq_mask) \
45 asm volatile(ALTERNATIVE( \
46 "csrc " __stringify(CSR_IP) ", %0\n\t", \
47 "csrc " __stringify(ANDES_CSR_SLIP) ", %0\n\t", \
48 ANDES_VENDOR_ID, \
49 RISCV_ISA_VENDOR_EXT_XANDESPMU + RISCV_VENDOR_EXT_ALTERNATIVES_BASE, \
50 CONFIG_ANDES_CUSTOM_PMU) \
51 : : "r"(__irq_mask) \
52 : "memory")
53
54 #define SYSCTL_NO_USER_ACCESS 0
55 #define SYSCTL_USER_ACCESS 1
56 #define SYSCTL_LEGACY 2
57
58 #define PERF_EVENT_FLAG_NO_USER_ACCESS BIT(SYSCTL_NO_USER_ACCESS)
59 #define PERF_EVENT_FLAG_USER_ACCESS BIT(SYSCTL_USER_ACCESS)
60 #define PERF_EVENT_FLAG_LEGACY BIT(SYSCTL_LEGACY)
61
62 PMU_FORMAT_ATTR(event, "config:0-47");
63 PMU_FORMAT_ATTR(firmware, "config:62-63");
64
65 static bool sbi_v2_available;
66 static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available);
67 #define sbi_pmu_snapshot_available() \
68 static_branch_unlikely(&sbi_pmu_snapshot_available)
69
70 static struct attribute *riscv_arch_formats_attr[] = {
71 &format_attr_event.attr,
72 &format_attr_firmware.attr,
73 NULL,
74 };
75
76 static struct attribute_group riscv_pmu_format_group = {
77 .name = "format",
78 .attrs = riscv_arch_formats_attr,
79 };
80
81 static const struct attribute_group *riscv_pmu_attr_groups[] = {
82 &riscv_pmu_format_group,
83 NULL,
84 };
85
86 /* Allow user mode access by default */
87 static int sysctl_perf_user_access __read_mostly = SYSCTL_USER_ACCESS;
88
89 /*
90 * RISC-V doesn't have heterogeneous harts yet. This need to be part of
91 * per_cpu in case of harts with different pmu counters
92 */
93 static union sbi_pmu_ctr_info *pmu_ctr_list;
94 static bool riscv_pmu_use_irq;
95 static unsigned int riscv_pmu_irq_num;
96 static unsigned int riscv_pmu_irq_mask;
97 static unsigned int riscv_pmu_irq;
98
99 /* Cache the available counters in a bitmask */
100 static unsigned long cmask;
101
102 struct sbi_pmu_event_data {
103 union {
104 union {
105 struct hw_gen_event {
106 uint32_t event_code:16;
107 uint32_t event_type:4;
108 uint32_t reserved:12;
109 } hw_gen_event;
110 struct hw_cache_event {
111 uint32_t result_id:1;
112 uint32_t op_id:2;
113 uint32_t cache_id:13;
114 uint32_t event_type:4;
115 uint32_t reserved:12;
116 } hw_cache_event;
117 };
118 uint32_t event_idx;
119 };
120 };
121
122 static struct sbi_pmu_event_data pmu_hw_event_map[] = {
123 [PERF_COUNT_HW_CPU_CYCLES] = {.hw_gen_event = {
124 SBI_PMU_HW_CPU_CYCLES,
125 SBI_PMU_EVENT_TYPE_HW, 0}},
126 [PERF_COUNT_HW_INSTRUCTIONS] = {.hw_gen_event = {
127 SBI_PMU_HW_INSTRUCTIONS,
128 SBI_PMU_EVENT_TYPE_HW, 0}},
129 [PERF_COUNT_HW_CACHE_REFERENCES] = {.hw_gen_event = {
130 SBI_PMU_HW_CACHE_REFERENCES,
131 SBI_PMU_EVENT_TYPE_HW, 0}},
132 [PERF_COUNT_HW_CACHE_MISSES] = {.hw_gen_event = {
133 SBI_PMU_HW_CACHE_MISSES,
134 SBI_PMU_EVENT_TYPE_HW, 0}},
135 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = {.hw_gen_event = {
136 SBI_PMU_HW_BRANCH_INSTRUCTIONS,
137 SBI_PMU_EVENT_TYPE_HW, 0}},
138 [PERF_COUNT_HW_BRANCH_MISSES] = {.hw_gen_event = {
139 SBI_PMU_HW_BRANCH_MISSES,
140 SBI_PMU_EVENT_TYPE_HW, 0}},
141 [PERF_COUNT_HW_BUS_CYCLES] = {.hw_gen_event = {
142 SBI_PMU_HW_BUS_CYCLES,
143 SBI_PMU_EVENT_TYPE_HW, 0}},
144 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = {.hw_gen_event = {
145 SBI_PMU_HW_STALLED_CYCLES_FRONTEND,
146 SBI_PMU_EVENT_TYPE_HW, 0}},
147 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = {.hw_gen_event = {
148 SBI_PMU_HW_STALLED_CYCLES_BACKEND,
149 SBI_PMU_EVENT_TYPE_HW, 0}},
150 [PERF_COUNT_HW_REF_CPU_CYCLES] = {.hw_gen_event = {
151 SBI_PMU_HW_REF_CPU_CYCLES,
152 SBI_PMU_EVENT_TYPE_HW, 0}},
153 };
154
155 #define C(x) PERF_COUNT_HW_CACHE_##x
156 static struct sbi_pmu_event_data pmu_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
157 [PERF_COUNT_HW_CACHE_OP_MAX]
158 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
159 [C(L1D)] = {
160 [C(OP_READ)] = {
161 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
162 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
163 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
164 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
165 },
166 [C(OP_WRITE)] = {
167 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
168 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
169 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
170 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
171 },
172 [C(OP_PREFETCH)] = {
173 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
174 C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
175 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
176 C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
177 },
178 },
179 [C(L1I)] = {
180 [C(OP_READ)] = {
181 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
182 C(OP_READ), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
183 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), C(OP_READ),
184 C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
185 },
186 [C(OP_WRITE)] = {
187 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
188 C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
189 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
190 C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
191 },
192 [C(OP_PREFETCH)] = {
193 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
194 C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
195 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
196 C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
197 },
198 },
199 [C(LL)] = {
200 [C(OP_READ)] = {
201 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
202 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
203 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
204 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
205 },
206 [C(OP_WRITE)] = {
207 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
208 C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
209 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
210 C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
211 },
212 [C(OP_PREFETCH)] = {
213 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
214 C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
215 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
216 C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
217 },
218 },
219 [C(DTLB)] = {
220 [C(OP_READ)] = {
221 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
222 C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
223 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
224 C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
225 },
226 [C(OP_WRITE)] = {
227 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
228 C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
229 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
230 C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
231 },
232 [C(OP_PREFETCH)] = {
233 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
234 C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
235 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
236 C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
237 },
238 },
239 [C(ITLB)] = {
240 [C(OP_READ)] = {
241 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
242 C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
243 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
244 C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
245 },
246 [C(OP_WRITE)] = {
247 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
248 C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
249 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
250 C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
251 },
252 [C(OP_PREFETCH)] = {
253 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
254 C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
255 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
256 C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
257 },
258 },
259 [C(BPU)] = {
260 [C(OP_READ)] = {
261 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
262 C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
263 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
264 C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
265 },
266 [C(OP_WRITE)] = {
267 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
268 C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
269 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
270 C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
271 },
272 [C(OP_PREFETCH)] = {
273 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
274 C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
275 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
276 C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
277 },
278 },
279 [C(NODE)] = {
280 [C(OP_READ)] = {
281 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
282 C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
283 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
284 C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
285 },
286 [C(OP_WRITE)] = {
287 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
288 C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
289 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
290 C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
291 },
292 [C(OP_PREFETCH)] = {
293 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
294 C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
295 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
296 C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
297 },
298 },
299 };
300
pmu_sbi_check_event(struct sbi_pmu_event_data * edata)301 static void pmu_sbi_check_event(struct sbi_pmu_event_data *edata)
302 {
303 struct sbiret ret;
304
305 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH,
306 0, cmask, 0, edata->event_idx, 0, 0);
307 if (!ret.error) {
308 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP,
309 ret.value, 0x1, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0);
310 } else if (ret.error == SBI_ERR_NOT_SUPPORTED) {
311 /* This event cannot be monitored by any counter */
312 edata->event_idx = -ENOENT;
313 }
314 }
315
pmu_sbi_check_std_events(struct work_struct * work)316 static void pmu_sbi_check_std_events(struct work_struct *work)
317 {
318 for (int i = 0; i < ARRAY_SIZE(pmu_hw_event_map); i++)
319 pmu_sbi_check_event(&pmu_hw_event_map[i]);
320
321 for (int i = 0; i < ARRAY_SIZE(pmu_cache_event_map); i++)
322 for (int j = 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++)
323 for (int k = 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++)
324 pmu_sbi_check_event(&pmu_cache_event_map[i][j][k]);
325 }
326
327 static DECLARE_WORK(check_std_events_work, pmu_sbi_check_std_events);
328
pmu_sbi_ctr_get_width(int idx)329 static int pmu_sbi_ctr_get_width(int idx)
330 {
331 return pmu_ctr_list[idx].width;
332 }
333
pmu_sbi_ctr_is_fw(int cidx)334 static bool pmu_sbi_ctr_is_fw(int cidx)
335 {
336 union sbi_pmu_ctr_info *info;
337
338 info = &pmu_ctr_list[cidx];
339 if (!info)
340 return false;
341
342 return info->type == SBI_PMU_CTR_TYPE_FW;
343 }
344
345 /*
346 * Returns the counter width of a programmable counter and number of hardware
347 * counters. As we don't support heterogeneous CPUs yet, it is okay to just
348 * return the counter width of the first programmable counter.
349 */
riscv_pmu_get_hpm_info(u32 * hw_ctr_width,u32 * num_hw_ctr)350 int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr)
351 {
352 int i;
353 union sbi_pmu_ctr_info *info;
354 u32 hpm_width = 0, hpm_count = 0;
355
356 if (!cmask)
357 return -EINVAL;
358
359 for_each_set_bit(i, &cmask, RISCV_MAX_COUNTERS) {
360 info = &pmu_ctr_list[i];
361 if (!info)
362 continue;
363 if (!hpm_width && info->csr != CSR_CYCLE && info->csr != CSR_INSTRET)
364 hpm_width = info->width;
365 if (info->type == SBI_PMU_CTR_TYPE_HW)
366 hpm_count++;
367 }
368
369 *hw_ctr_width = hpm_width;
370 *num_hw_ctr = hpm_count;
371
372 return 0;
373 }
374 EXPORT_SYMBOL_GPL(riscv_pmu_get_hpm_info);
375
pmu_sbi_csr_index(struct perf_event * event)376 static uint8_t pmu_sbi_csr_index(struct perf_event *event)
377 {
378 return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE;
379 }
380
pmu_sbi_get_filter_flags(struct perf_event * event)381 static unsigned long pmu_sbi_get_filter_flags(struct perf_event *event)
382 {
383 unsigned long cflags = 0;
384 bool guest_events = false;
385
386 if (event->attr.config1 & RISCV_PMU_CONFIG1_GUEST_EVENTS)
387 guest_events = true;
388 if (event->attr.exclude_kernel)
389 cflags |= guest_events ? SBI_PMU_CFG_FLAG_SET_VSINH : SBI_PMU_CFG_FLAG_SET_SINH;
390 if (event->attr.exclude_user)
391 cflags |= guest_events ? SBI_PMU_CFG_FLAG_SET_VUINH : SBI_PMU_CFG_FLAG_SET_UINH;
392 if (guest_events && event->attr.exclude_hv)
393 cflags |= SBI_PMU_CFG_FLAG_SET_SINH;
394 if (event->attr.exclude_host)
395 cflags |= SBI_PMU_CFG_FLAG_SET_UINH | SBI_PMU_CFG_FLAG_SET_SINH;
396 if (event->attr.exclude_guest)
397 cflags |= SBI_PMU_CFG_FLAG_SET_VSINH | SBI_PMU_CFG_FLAG_SET_VUINH;
398
399 return cflags;
400 }
401
pmu_sbi_ctr_get_idx(struct perf_event * event)402 static int pmu_sbi_ctr_get_idx(struct perf_event *event)
403 {
404 struct hw_perf_event *hwc = &event->hw;
405 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
406 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
407 struct sbiret ret;
408 int idx;
409 uint64_t cbase = 0, cmask = rvpmu->cmask;
410 unsigned long cflags = 0;
411
412 cflags = pmu_sbi_get_filter_flags(event);
413
414 /*
415 * In legacy mode, we have to force the fixed counters for those events
416 * but not in the user access mode as we want to use the other counters
417 * that support sampling/filtering.
418 */
419 if ((hwc->flags & PERF_EVENT_FLAG_LEGACY) && (event->attr.type == PERF_TYPE_HARDWARE)) {
420 if (event->attr.config == PERF_COUNT_HW_CPU_CYCLES) {
421 cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH;
422 cmask = 1;
423 } else if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS) {
424 cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH;
425 cmask = BIT(CSR_INSTRET - CSR_CYCLE);
426 }
427 }
428
429 /* retrieve the available counter index */
430 #if defined(CONFIG_32BIT)
431 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase,
432 cmask, cflags, hwc->event_base, hwc->config,
433 hwc->config >> 32);
434 #else
435 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase,
436 cmask, cflags, hwc->event_base, hwc->config, 0);
437 #endif
438 if (ret.error) {
439 pr_debug("Not able to find a counter for event %lx config %llx\n",
440 hwc->event_base, hwc->config);
441 return sbi_err_map_linux_errno(ret.error);
442 }
443
444 idx = ret.value;
445 if (!test_bit(idx, &rvpmu->cmask) || !pmu_ctr_list[idx].value)
446 return -ENOENT;
447
448 /* Additional sanity check for the counter id */
449 if (pmu_sbi_ctr_is_fw(idx)) {
450 if (!test_and_set_bit(idx, cpuc->used_fw_ctrs))
451 return idx;
452 } else {
453 if (!test_and_set_bit(idx, cpuc->used_hw_ctrs))
454 return idx;
455 }
456
457 return -ENOENT;
458 }
459
pmu_sbi_ctr_clear_idx(struct perf_event * event)460 static void pmu_sbi_ctr_clear_idx(struct perf_event *event)
461 {
462
463 struct hw_perf_event *hwc = &event->hw;
464 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
465 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
466 int idx = hwc->idx;
467
468 if (pmu_sbi_ctr_is_fw(idx))
469 clear_bit(idx, cpuc->used_fw_ctrs);
470 else
471 clear_bit(idx, cpuc->used_hw_ctrs);
472 }
473
pmu_event_find_cache(u64 config)474 static int pmu_event_find_cache(u64 config)
475 {
476 unsigned int cache_type, cache_op, cache_result, ret;
477
478 cache_type = (config >> 0) & 0xff;
479 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
480 return -EINVAL;
481
482 cache_op = (config >> 8) & 0xff;
483 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
484 return -EINVAL;
485
486 cache_result = (config >> 16) & 0xff;
487 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
488 return -EINVAL;
489
490 ret = pmu_cache_event_map[cache_type][cache_op][cache_result].event_idx;
491
492 return ret;
493 }
494
pmu_sbi_is_fw_event(struct perf_event * event)495 static bool pmu_sbi_is_fw_event(struct perf_event *event)
496 {
497 u32 type = event->attr.type;
498 u64 config = event->attr.config;
499
500 if ((type == PERF_TYPE_RAW) && ((config >> 63) == 1))
501 return true;
502 else
503 return false;
504 }
505
pmu_sbi_event_map(struct perf_event * event,u64 * econfig)506 static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig)
507 {
508 u32 type = event->attr.type;
509 u64 config = event->attr.config;
510 int ret = -ENOENT;
511
512 /*
513 * Ensure we are finished checking standard hardware events for
514 * validity before allowing userspace to configure any events.
515 */
516 flush_work(&check_std_events_work);
517
518 switch (type) {
519 case PERF_TYPE_HARDWARE:
520 if (config >= PERF_COUNT_HW_MAX)
521 return -EINVAL;
522 ret = pmu_hw_event_map[event->attr.config].event_idx;
523 break;
524 case PERF_TYPE_HW_CACHE:
525 ret = pmu_event_find_cache(config);
526 break;
527 case PERF_TYPE_RAW:
528 /*
529 * As per SBI specification, the upper 16 bits must be unused
530 * for a hardware raw event.
531 * Bits 63:62 are used to distinguish between raw events
532 * 00 - Hardware raw event
533 * 10 - SBI firmware events
534 * 11 - Risc-V platform specific firmware event
535 */
536
537 switch (config >> 62) {
538 case 0:
539 /* Return error any bits [48-63] is set as it is not allowed by the spec */
540 if (!(config & ~RISCV_PMU_RAW_EVENT_MASK)) {
541 *econfig = config & RISCV_PMU_RAW_EVENT_MASK;
542 ret = RISCV_PMU_RAW_EVENT_IDX;
543 }
544 break;
545 case 2:
546 ret = (config & 0xFFFF) | (SBI_PMU_EVENT_TYPE_FW << 16);
547 break;
548 case 3:
549 /*
550 * For Risc-V platform specific firmware events
551 * Event code - 0xFFFF
552 * Event data - raw event encoding
553 */
554 ret = SBI_PMU_EVENT_TYPE_FW << 16 | RISCV_PLAT_FW_EVENT;
555 *econfig = config & RISCV_PMU_PLAT_FW_EVENT_MASK;
556 break;
557 default:
558 break;
559 }
560 break;
561 default:
562 break;
563 }
564
565 return ret;
566 }
567
pmu_sbi_snapshot_free(struct riscv_pmu * pmu)568 static void pmu_sbi_snapshot_free(struct riscv_pmu *pmu)
569 {
570 int cpu;
571
572 for_each_possible_cpu(cpu) {
573 struct cpu_hw_events *cpu_hw_evt = per_cpu_ptr(pmu->hw_events, cpu);
574
575 if (!cpu_hw_evt->snapshot_addr)
576 continue;
577
578 free_page((unsigned long)cpu_hw_evt->snapshot_addr);
579 cpu_hw_evt->snapshot_addr = NULL;
580 cpu_hw_evt->snapshot_addr_phys = 0;
581 }
582 }
583
pmu_sbi_snapshot_alloc(struct riscv_pmu * pmu)584 static int pmu_sbi_snapshot_alloc(struct riscv_pmu *pmu)
585 {
586 int cpu;
587 struct page *snapshot_page;
588
589 for_each_possible_cpu(cpu) {
590 struct cpu_hw_events *cpu_hw_evt = per_cpu_ptr(pmu->hw_events, cpu);
591
592 snapshot_page = alloc_page(GFP_ATOMIC | __GFP_ZERO);
593 if (!snapshot_page) {
594 pmu_sbi_snapshot_free(pmu);
595 return -ENOMEM;
596 }
597 cpu_hw_evt->snapshot_addr = page_to_virt(snapshot_page);
598 cpu_hw_evt->snapshot_addr_phys = page_to_phys(snapshot_page);
599 }
600
601 return 0;
602 }
603
pmu_sbi_snapshot_disable(void)604 static int pmu_sbi_snapshot_disable(void)
605 {
606 struct sbiret ret;
607
608 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, SBI_SHMEM_DISABLE,
609 SBI_SHMEM_DISABLE, 0, 0, 0, 0);
610 if (ret.error) {
611 pr_warn("failed to disable snapshot shared memory\n");
612 return sbi_err_map_linux_errno(ret.error);
613 }
614
615 return 0;
616 }
617
pmu_sbi_snapshot_setup(struct riscv_pmu * pmu,int cpu)618 static int pmu_sbi_snapshot_setup(struct riscv_pmu *pmu, int cpu)
619 {
620 struct cpu_hw_events *cpu_hw_evt;
621 struct sbiret ret = {0};
622
623 cpu_hw_evt = per_cpu_ptr(pmu->hw_events, cpu);
624 if (!cpu_hw_evt->snapshot_addr_phys)
625 return -EINVAL;
626
627 if (cpu_hw_evt->snapshot_set_done)
628 return 0;
629
630 if (IS_ENABLED(CONFIG_32BIT))
631 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM,
632 cpu_hw_evt->snapshot_addr_phys,
633 (u64)(cpu_hw_evt->snapshot_addr_phys) >> 32, 0, 0, 0, 0);
634 else
635 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM,
636 cpu_hw_evt->snapshot_addr_phys, 0, 0, 0, 0, 0);
637
638 /* Free up the snapshot area memory and fall back to SBI PMU calls without snapshot */
639 if (ret.error) {
640 if (ret.error != SBI_ERR_NOT_SUPPORTED)
641 pr_warn("pmu snapshot setup failed with error %ld\n", ret.error);
642 return sbi_err_map_linux_errno(ret.error);
643 }
644
645 memset(cpu_hw_evt->snapshot_cval_shcopy, 0, sizeof(u64) * RISCV_MAX_COUNTERS);
646 cpu_hw_evt->snapshot_set_done = true;
647
648 return 0;
649 }
650
pmu_sbi_ctr_read(struct perf_event * event)651 static u64 pmu_sbi_ctr_read(struct perf_event *event)
652 {
653 struct hw_perf_event *hwc = &event->hw;
654 int idx = hwc->idx;
655 struct sbiret ret;
656 u64 val = 0;
657 struct riscv_pmu *pmu = to_riscv_pmu(event->pmu);
658 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
659 struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr;
660 union sbi_pmu_ctr_info info = pmu_ctr_list[idx];
661
662 /* Read the value from the shared memory directly only if counter is stopped */
663 if (sbi_pmu_snapshot_available() && (hwc->state & PERF_HES_STOPPED)) {
664 val = sdata->ctr_values[idx];
665 return val;
666 }
667
668 if (pmu_sbi_is_fw_event(event)) {
669 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ,
670 hwc->idx, 0, 0, 0, 0, 0);
671 if (ret.error)
672 return 0;
673
674 val = ret.value;
675 if (IS_ENABLED(CONFIG_32BIT) && sbi_v2_available && info.width >= 32) {
676 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ_HI,
677 hwc->idx, 0, 0, 0, 0, 0);
678 if (!ret.error)
679 val |= ((u64)ret.value << 32);
680 else
681 WARN_ONCE(1, "Unable to read upper 32 bits of firmware counter error: %ld\n",
682 ret.error);
683 }
684 } else {
685 val = riscv_pmu_ctr_read_csr(info.csr);
686 if (IS_ENABLED(CONFIG_32BIT))
687 val |= ((u64)riscv_pmu_ctr_read_csr(info.csr + 0x80)) << 32;
688 }
689
690 return val;
691 }
692
pmu_sbi_set_scounteren(void * arg)693 static void pmu_sbi_set_scounteren(void *arg)
694 {
695 struct perf_event *event = (struct perf_event *)arg;
696
697 if (event->hw.idx != -1)
698 csr_write(CSR_SCOUNTEREN,
699 csr_read(CSR_SCOUNTEREN) | BIT(pmu_sbi_csr_index(event)));
700 }
701
pmu_sbi_reset_scounteren(void * arg)702 static void pmu_sbi_reset_scounteren(void *arg)
703 {
704 struct perf_event *event = (struct perf_event *)arg;
705
706 if (event->hw.idx != -1)
707 csr_write(CSR_SCOUNTEREN,
708 csr_read(CSR_SCOUNTEREN) & ~BIT(pmu_sbi_csr_index(event)));
709 }
710
pmu_sbi_ctr_start(struct perf_event * event,u64 ival)711 static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival)
712 {
713 struct sbiret ret;
714 struct hw_perf_event *hwc = &event->hw;
715 unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE;
716
717 /* There is no benefit setting SNAPSHOT FLAG for a single counter */
718 #if defined(CONFIG_32BIT)
719 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
720 1, flag, ival, ival >> 32, 0);
721 #else
722 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
723 1, flag, ival, 0, 0);
724 #endif
725 if (ret.error && (ret.error != SBI_ERR_ALREADY_STARTED))
726 pr_err("Starting counter idx %d failed with error %d\n",
727 hwc->idx, sbi_err_map_linux_errno(ret.error));
728
729 if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) &&
730 (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT))
731 pmu_sbi_set_scounteren((void *)event);
732 }
733
pmu_sbi_ctr_stop(struct perf_event * event,unsigned long flag)734 static void pmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag)
735 {
736 struct sbiret ret;
737 struct hw_perf_event *hwc = &event->hw;
738 struct riscv_pmu *pmu = to_riscv_pmu(event->pmu);
739 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
740 struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr;
741
742 if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) &&
743 (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT))
744 pmu_sbi_reset_scounteren((void *)event);
745
746 if (sbi_pmu_snapshot_available())
747 flag |= SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT;
748
749 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, hwc->idx, 1, flag, 0, 0, 0);
750 if (!ret.error && sbi_pmu_snapshot_available()) {
751 /*
752 * The counter snapshot is based on the index base specified by hwc->idx.
753 * The actual counter value is updated in shared memory at index 0 when counter
754 * mask is 0x01. To ensure accurate counter values, it's necessary to transfer
755 * the counter value to shared memory. However, if hwc->idx is zero, the counter
756 * value is already correctly updated in shared memory, requiring no further
757 * adjustment.
758 */
759 if (hwc->idx > 0) {
760 sdata->ctr_values[hwc->idx] = sdata->ctr_values[0];
761 sdata->ctr_values[0] = 0;
762 }
763 } else if (ret.error && (ret.error != SBI_ERR_ALREADY_STOPPED) &&
764 flag != SBI_PMU_STOP_FLAG_RESET) {
765 pr_err("Stopping counter idx %d failed with error %d\n",
766 hwc->idx, sbi_err_map_linux_errno(ret.error));
767 }
768 }
769
pmu_sbi_find_num_ctrs(void)770 static int pmu_sbi_find_num_ctrs(void)
771 {
772 struct sbiret ret;
773
774 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_NUM_COUNTERS, 0, 0, 0, 0, 0, 0);
775 if (!ret.error)
776 return ret.value;
777 else
778 return sbi_err_map_linux_errno(ret.error);
779 }
780
pmu_sbi_get_ctrinfo(int nctr,unsigned long * mask)781 static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask)
782 {
783 struct sbiret ret;
784 int i, num_hw_ctr = 0, num_fw_ctr = 0;
785 union sbi_pmu_ctr_info cinfo;
786
787 pmu_ctr_list = kcalloc(nctr, sizeof(*pmu_ctr_list), GFP_KERNEL);
788 if (!pmu_ctr_list)
789 return -ENOMEM;
790
791 for (i = 0; i < nctr; i++) {
792 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0, 0, 0);
793 if (ret.error)
794 /* The logical counter ids are not expected to be contiguous */
795 continue;
796
797 *mask |= BIT(i);
798
799 cinfo.value = ret.value;
800 if (cinfo.type == SBI_PMU_CTR_TYPE_FW)
801 num_fw_ctr++;
802 else
803 num_hw_ctr++;
804 pmu_ctr_list[i].value = cinfo.value;
805 }
806
807 pr_info("%d firmware and %d hardware counters\n", num_fw_ctr, num_hw_ctr);
808
809 return 0;
810 }
811
pmu_sbi_stop_all(struct riscv_pmu * pmu)812 static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu)
813 {
814 /*
815 * No need to check the error because we are disabling all the counters
816 * which may include counters that are not enabled yet.
817 */
818 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP,
819 0, pmu->cmask, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0);
820 }
821
pmu_sbi_stop_hw_ctrs(struct riscv_pmu * pmu)822 static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu)
823 {
824 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
825 struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr;
826 unsigned long flag = 0;
827 int i, idx;
828 struct sbiret ret;
829 u64 temp_ctr_overflow_mask = 0;
830
831 if (sbi_pmu_snapshot_available())
832 flag = SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT;
833
834 /* Reset the shadow copy to avoid save/restore any value from previous overflow */
835 memset(cpu_hw_evt->snapshot_cval_shcopy, 0, sizeof(u64) * RISCV_MAX_COUNTERS);
836
837 for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) {
838 /* No need to check the error here as we can't do anything about the error */
839 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, i * BITS_PER_LONG,
840 cpu_hw_evt->used_hw_ctrs[i], flag, 0, 0, 0);
841 if (!ret.error && sbi_pmu_snapshot_available()) {
842 /* Save the counter values to avoid clobbering */
843 for_each_set_bit(idx, &cpu_hw_evt->used_hw_ctrs[i], BITS_PER_LONG)
844 cpu_hw_evt->snapshot_cval_shcopy[i * BITS_PER_LONG + idx] =
845 sdata->ctr_values[idx];
846 /* Save the overflow mask to avoid clobbering */
847 temp_ctr_overflow_mask |= sdata->ctr_overflow_mask << (i * BITS_PER_LONG);
848 }
849 }
850
851 /* Restore the counter values to the shared memory for used hw counters */
852 if (sbi_pmu_snapshot_available()) {
853 for_each_set_bit(idx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS)
854 sdata->ctr_values[idx] = cpu_hw_evt->snapshot_cval_shcopy[idx];
855 if (temp_ctr_overflow_mask)
856 sdata->ctr_overflow_mask = temp_ctr_overflow_mask;
857 }
858 }
859
860 /*
861 * This function starts all the used counters in two step approach.
862 * Any counter that did not overflow can be start in a single step
863 * while the overflowed counters need to be started with updated initialization
864 * value.
865 */
pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events * cpu_hw_evt,u64 ctr_ovf_mask)866 static inline void pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_hw_evt,
867 u64 ctr_ovf_mask)
868 {
869 int idx = 0, i;
870 struct perf_event *event;
871 unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE;
872 unsigned long ctr_start_mask = 0;
873 uint64_t max_period;
874 struct hw_perf_event *hwc;
875 u64 init_val = 0;
876
877 for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) {
878 ctr_start_mask = cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask;
879 /* Start all the counters that did not overflow in a single shot */
880 if (ctr_start_mask) {
881 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i * BITS_PER_LONG,
882 ctr_start_mask, 0, 0, 0, 0);
883 }
884 }
885
886 /* Reinitialize and start all the counter that overflowed */
887 while (ctr_ovf_mask) {
888 if (ctr_ovf_mask & 0x01) {
889 event = cpu_hw_evt->events[idx];
890 hwc = &event->hw;
891 max_period = riscv_pmu_ctr_get_width_mask(event);
892 init_val = local64_read(&hwc->prev_count) & max_period;
893 #if defined(CONFIG_32BIT)
894 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
895 flag, init_val, init_val >> 32, 0);
896 #else
897 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
898 flag, init_val, 0, 0);
899 #endif
900 perf_event_update_userpage(event);
901 }
902 ctr_ovf_mask = ctr_ovf_mask >> 1;
903 idx++;
904 }
905 }
906
pmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events * cpu_hw_evt,u64 ctr_ovf_mask)907 static inline void pmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events *cpu_hw_evt,
908 u64 ctr_ovf_mask)
909 {
910 int i, idx = 0;
911 struct perf_event *event;
912 unsigned long flag = SBI_PMU_START_FLAG_INIT_SNAPSHOT;
913 u64 max_period, init_val = 0;
914 struct hw_perf_event *hwc;
915 struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr;
916
917 for_each_set_bit(idx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) {
918 if (ctr_ovf_mask & BIT(idx)) {
919 event = cpu_hw_evt->events[idx];
920 hwc = &event->hw;
921 max_period = riscv_pmu_ctr_get_width_mask(event);
922 init_val = local64_read(&hwc->prev_count) & max_period;
923 cpu_hw_evt->snapshot_cval_shcopy[idx] = init_val;
924 }
925 /*
926 * We do not need to update the non-overflow counters the previous
927 * value should have been there already.
928 */
929 }
930
931 for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) {
932 /* Restore the counter values to relative indices for used hw counters */
933 for_each_set_bit(idx, &cpu_hw_evt->used_hw_ctrs[i], BITS_PER_LONG)
934 sdata->ctr_values[idx] =
935 cpu_hw_evt->snapshot_cval_shcopy[idx + i * BITS_PER_LONG];
936 /* Start all the counters in a single shot */
937 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx * BITS_PER_LONG,
938 cpu_hw_evt->used_hw_ctrs[i], flag, 0, 0, 0);
939 }
940 }
941
pmu_sbi_start_overflow_mask(struct riscv_pmu * pmu,u64 ctr_ovf_mask)942 static void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
943 u64 ctr_ovf_mask)
944 {
945 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
946
947 if (sbi_pmu_snapshot_available())
948 pmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask);
949 else
950 pmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask);
951 }
952
pmu_sbi_ovf_handler(int irq,void * dev)953 static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
954 {
955 struct perf_sample_data data;
956 struct pt_regs *regs;
957 struct hw_perf_event *hw_evt;
958 union sbi_pmu_ctr_info *info;
959 int lidx, hidx, fidx;
960 struct riscv_pmu *pmu;
961 struct perf_event *event;
962 u64 overflow;
963 u64 overflowed_ctrs = 0;
964 struct cpu_hw_events *cpu_hw_evt = dev;
965 u64 start_clock = sched_clock();
966 struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr;
967
968 if (WARN_ON_ONCE(!cpu_hw_evt))
969 return IRQ_NONE;
970
971 /* Firmware counter don't support overflow yet */
972 fidx = find_first_bit(cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS);
973 if (fidx == RISCV_MAX_COUNTERS) {
974 csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num));
975 return IRQ_NONE;
976 }
977
978 event = cpu_hw_evt->events[fidx];
979 if (!event) {
980 ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask);
981 return IRQ_NONE;
982 }
983
984 pmu = to_riscv_pmu(event->pmu);
985 pmu_sbi_stop_hw_ctrs(pmu);
986
987 /* Overflow status register should only be read after counter are stopped */
988 if (sbi_pmu_snapshot_available())
989 overflow = sdata->ctr_overflow_mask;
990 else
991 ALT_SBI_PMU_OVERFLOW(overflow);
992
993 /*
994 * Overflow interrupt pending bit should only be cleared after stopping
995 * all the counters to avoid any race condition.
996 */
997 ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask);
998
999 /* No overflow bit is set */
1000 if (!overflow)
1001 return IRQ_NONE;
1002
1003 regs = get_irq_regs();
1004
1005 for_each_set_bit(lidx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) {
1006 struct perf_event *event = cpu_hw_evt->events[lidx];
1007
1008 /* Skip if invalid event or user did not request a sampling */
1009 if (!event || !is_sampling_event(event))
1010 continue;
1011
1012 info = &pmu_ctr_list[lidx];
1013 /* Do a sanity check */
1014 if (!info || info->type != SBI_PMU_CTR_TYPE_HW)
1015 continue;
1016
1017 if (sbi_pmu_snapshot_available())
1018 /* SBI implementation already updated the logical indicies */
1019 hidx = lidx;
1020 else
1021 /* compute hardware counter index */
1022 hidx = info->csr - CSR_CYCLE;
1023
1024 /* check if the corresponding bit is set in sscountovf or overflow mask in shmem */
1025 if (!(overflow & BIT(hidx)))
1026 continue;
1027
1028 /*
1029 * Keep a track of overflowed counters so that they can be started
1030 * with updated initial value.
1031 */
1032 overflowed_ctrs |= BIT(lidx);
1033 hw_evt = &event->hw;
1034 /* Update the event states here so that we know the state while reading */
1035 hw_evt->state |= PERF_HES_STOPPED;
1036 riscv_pmu_event_update(event);
1037 hw_evt->state |= PERF_HES_UPTODATE;
1038 perf_sample_data_init(&data, 0, hw_evt->last_period);
1039 if (riscv_pmu_event_set_period(event)) {
1040 /*
1041 * Unlike other ISAs, RISC-V don't have to disable interrupts
1042 * to avoid throttling here. As per the specification, the
1043 * interrupt remains disabled until the OF bit is set.
1044 * Interrupts are enabled again only during the start.
1045 * TODO: We will need to stop the guest counters once
1046 * virtualization support is added.
1047 */
1048 perf_event_overflow(event, &data, regs);
1049 }
1050 /* Reset the state as we are going to start the counter after the loop */
1051 hw_evt->state = 0;
1052 }
1053
1054 pmu_sbi_start_overflow_mask(pmu, overflowed_ctrs);
1055 perf_sample_event_took(sched_clock() - start_clock);
1056
1057 return IRQ_HANDLED;
1058 }
1059
pmu_sbi_starting_cpu(unsigned int cpu,struct hlist_node * node)1060 static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
1061 {
1062 struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node);
1063 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
1064
1065 /*
1066 * We keep enabling userspace access to CYCLE, TIME and INSTRET via the
1067 * legacy option but that will be removed in the future.
1068 */
1069 if (sysctl_perf_user_access == SYSCTL_LEGACY)
1070 csr_write(CSR_SCOUNTEREN, 0x7);
1071 else
1072 csr_write(CSR_SCOUNTEREN, 0x2);
1073
1074 /* Stop all the counters so that they can be enabled from perf */
1075 pmu_sbi_stop_all(pmu);
1076
1077 if (riscv_pmu_use_irq) {
1078 cpu_hw_evt->irq = riscv_pmu_irq;
1079 ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask);
1080 enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
1081 }
1082
1083 if (sbi_pmu_snapshot_available())
1084 return pmu_sbi_snapshot_setup(pmu, cpu);
1085
1086 return 0;
1087 }
1088
pmu_sbi_dying_cpu(unsigned int cpu,struct hlist_node * node)1089 static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node)
1090 {
1091 if (riscv_pmu_use_irq) {
1092 disable_percpu_irq(riscv_pmu_irq);
1093 }
1094
1095 /* Disable all counters access for user mode now */
1096 csr_write(CSR_SCOUNTEREN, 0x0);
1097
1098 if (sbi_pmu_snapshot_available())
1099 return pmu_sbi_snapshot_disable();
1100
1101 return 0;
1102 }
1103
pmu_sbi_setup_irqs(struct riscv_pmu * pmu,struct platform_device * pdev)1104 static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pdev)
1105 {
1106 int ret;
1107 struct cpu_hw_events __percpu *hw_events = pmu->hw_events;
1108 struct irq_domain *domain = NULL;
1109
1110 if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
1111 riscv_pmu_irq_num = RV_IRQ_PMU;
1112 riscv_pmu_use_irq = true;
1113 } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
1114 riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
1115 riscv_cached_marchid(0) == 0 &&
1116 riscv_cached_mimpid(0) == 0) {
1117 riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
1118 riscv_pmu_use_irq = true;
1119 } else if (riscv_has_vendor_extension_unlikely(ANDES_VENDOR_ID,
1120 RISCV_ISA_VENDOR_EXT_XANDESPMU) &&
1121 IS_ENABLED(CONFIG_ANDES_CUSTOM_PMU)) {
1122 riscv_pmu_irq_num = ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMOVI;
1123 riscv_pmu_use_irq = true;
1124 }
1125
1126 riscv_pmu_irq_mask = BIT(riscv_pmu_irq_num % BITS_PER_LONG);
1127
1128 if (!riscv_pmu_use_irq)
1129 return -EOPNOTSUPP;
1130
1131 domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(),
1132 DOMAIN_BUS_ANY);
1133 if (!domain) {
1134 pr_err("Failed to find INTC IRQ root domain\n");
1135 return -ENODEV;
1136 }
1137
1138 riscv_pmu_irq = irq_create_mapping(domain, riscv_pmu_irq_num);
1139 if (!riscv_pmu_irq) {
1140 pr_err("Failed to map PMU interrupt for node\n");
1141 return -ENODEV;
1142 }
1143
1144 ret = request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu", hw_events);
1145 if (ret) {
1146 pr_err("registering percpu irq failed [%d]\n", ret);
1147 return ret;
1148 }
1149
1150 return 0;
1151 }
1152
1153 #ifdef CONFIG_CPU_PM
riscv_pm_pmu_notify(struct notifier_block * b,unsigned long cmd,void * v)1154 static int riscv_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
1155 void *v)
1156 {
1157 struct riscv_pmu *rvpmu = container_of(b, struct riscv_pmu, riscv_pm_nb);
1158 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
1159 int enabled = bitmap_weight(cpuc->used_hw_ctrs, RISCV_MAX_COUNTERS);
1160 struct perf_event *event;
1161 int idx;
1162
1163 if (!enabled)
1164 return NOTIFY_OK;
1165
1166 for (idx = 0; idx < RISCV_MAX_COUNTERS; idx++) {
1167 event = cpuc->events[idx];
1168 if (!event)
1169 continue;
1170
1171 switch (cmd) {
1172 case CPU_PM_ENTER:
1173 /*
1174 * Stop and update the counter
1175 */
1176 riscv_pmu_stop(event, PERF_EF_UPDATE);
1177 break;
1178 case CPU_PM_EXIT:
1179 case CPU_PM_ENTER_FAILED:
1180 /*
1181 * Restore and enable the counter.
1182 */
1183 riscv_pmu_start(event, PERF_EF_RELOAD);
1184 break;
1185 default:
1186 break;
1187 }
1188 }
1189
1190 return NOTIFY_OK;
1191 }
1192
riscv_pm_pmu_register(struct riscv_pmu * pmu)1193 static int riscv_pm_pmu_register(struct riscv_pmu *pmu)
1194 {
1195 pmu->riscv_pm_nb.notifier_call = riscv_pm_pmu_notify;
1196 return cpu_pm_register_notifier(&pmu->riscv_pm_nb);
1197 }
1198
riscv_pm_pmu_unregister(struct riscv_pmu * pmu)1199 static void riscv_pm_pmu_unregister(struct riscv_pmu *pmu)
1200 {
1201 cpu_pm_unregister_notifier(&pmu->riscv_pm_nb);
1202 }
1203 #else
riscv_pm_pmu_register(struct riscv_pmu * pmu)1204 static inline int riscv_pm_pmu_register(struct riscv_pmu *pmu) { return 0; }
riscv_pm_pmu_unregister(struct riscv_pmu * pmu)1205 static inline void riscv_pm_pmu_unregister(struct riscv_pmu *pmu) { }
1206 #endif
1207
riscv_pmu_destroy(struct riscv_pmu * pmu)1208 static void riscv_pmu_destroy(struct riscv_pmu *pmu)
1209 {
1210 if (sbi_v2_available) {
1211 if (sbi_pmu_snapshot_available()) {
1212 pmu_sbi_snapshot_disable();
1213 pmu_sbi_snapshot_free(pmu);
1214 }
1215 }
1216 riscv_pm_pmu_unregister(pmu);
1217 cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node);
1218 }
1219
pmu_sbi_event_init(struct perf_event * event)1220 static void pmu_sbi_event_init(struct perf_event *event)
1221 {
1222 /*
1223 * The permissions are set at event_init so that we do not depend
1224 * on the sysctl value that can change.
1225 */
1226 if (sysctl_perf_user_access == SYSCTL_NO_USER_ACCESS)
1227 event->hw.flags |= PERF_EVENT_FLAG_NO_USER_ACCESS;
1228 else if (sysctl_perf_user_access == SYSCTL_USER_ACCESS)
1229 event->hw.flags |= PERF_EVENT_FLAG_USER_ACCESS;
1230 else
1231 event->hw.flags |= PERF_EVENT_FLAG_LEGACY;
1232 }
1233
pmu_sbi_event_mapped(struct perf_event * event,struct mm_struct * mm)1234 static void pmu_sbi_event_mapped(struct perf_event *event, struct mm_struct *mm)
1235 {
1236 if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS)
1237 return;
1238
1239 if (event->hw.flags & PERF_EVENT_FLAG_LEGACY) {
1240 if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&
1241 event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) {
1242 return;
1243 }
1244 }
1245
1246 /*
1247 * The user mmapped the event to directly access it: this is where
1248 * we determine based on sysctl_perf_user_access if we grant userspace
1249 * the direct access to this event. That means that within the same
1250 * task, some events may be directly accessible and some other may not,
1251 * if the user changes the value of sysctl_perf_user_accesss in the
1252 * meantime.
1253 */
1254
1255 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
1256
1257 /*
1258 * We must enable userspace access *before* advertising in the user page
1259 * that it is possible to do so to avoid any race.
1260 * And we must notify all cpus here because threads that currently run
1261 * on other cpus will try to directly access the counter too without
1262 * calling pmu_sbi_ctr_start.
1263 */
1264 if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS)
1265 on_each_cpu_mask(mm_cpumask(mm),
1266 pmu_sbi_set_scounteren, (void *)event, 1);
1267 }
1268
pmu_sbi_event_unmapped(struct perf_event * event,struct mm_struct * mm)1269 static void pmu_sbi_event_unmapped(struct perf_event *event, struct mm_struct *mm)
1270 {
1271 if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS)
1272 return;
1273
1274 if (event->hw.flags & PERF_EVENT_FLAG_LEGACY) {
1275 if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&
1276 event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) {
1277 return;
1278 }
1279 }
1280
1281 /*
1282 * Here we can directly remove user access since the user does not have
1283 * access to the user page anymore so we avoid the racy window where the
1284 * user could have read cap_user_rdpmc to true right before we disable
1285 * it.
1286 */
1287 event->hw.flags &= ~PERF_EVENT_FLAG_USER_READ_CNT;
1288
1289 if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS)
1290 on_each_cpu_mask(mm_cpumask(mm),
1291 pmu_sbi_reset_scounteren, (void *)event, 1);
1292 }
1293
riscv_pmu_update_counter_access(void * info)1294 static void riscv_pmu_update_counter_access(void *info)
1295 {
1296 if (sysctl_perf_user_access == SYSCTL_LEGACY)
1297 csr_write(CSR_SCOUNTEREN, 0x7);
1298 else
1299 csr_write(CSR_SCOUNTEREN, 0x2);
1300 }
1301
riscv_pmu_proc_user_access_handler(const struct ctl_table * table,int write,void * buffer,size_t * lenp,loff_t * ppos)1302 static int riscv_pmu_proc_user_access_handler(const struct ctl_table *table,
1303 int write, void *buffer,
1304 size_t *lenp, loff_t *ppos)
1305 {
1306 int prev = sysctl_perf_user_access;
1307 int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
1308
1309 /*
1310 * Test against the previous value since we clear SCOUNTEREN when
1311 * sysctl_perf_user_access is set to SYSCTL_USER_ACCESS, but we should
1312 * not do that if that was already the case.
1313 */
1314 if (ret || !write || prev == sysctl_perf_user_access)
1315 return ret;
1316
1317 on_each_cpu(riscv_pmu_update_counter_access, NULL, 1);
1318
1319 return 0;
1320 }
1321
1322 static const struct ctl_table sbi_pmu_sysctl_table[] = {
1323 {
1324 .procname = "perf_user_access",
1325 .data = &sysctl_perf_user_access,
1326 .maxlen = sizeof(unsigned int),
1327 .mode = 0644,
1328 .proc_handler = riscv_pmu_proc_user_access_handler,
1329 .extra1 = SYSCTL_ZERO,
1330 .extra2 = SYSCTL_TWO,
1331 },
1332 };
1333
pmu_sbi_device_probe(struct platform_device * pdev)1334 static int pmu_sbi_device_probe(struct platform_device *pdev)
1335 {
1336 struct riscv_pmu *pmu = NULL;
1337 int ret = -ENODEV;
1338 int num_counters;
1339
1340 pr_info("SBI PMU extension is available\n");
1341 pmu = riscv_pmu_alloc();
1342 if (!pmu)
1343 return -ENOMEM;
1344
1345 num_counters = pmu_sbi_find_num_ctrs();
1346 if (num_counters < 0) {
1347 pr_err("SBI PMU extension doesn't provide any counters\n");
1348 goto out_free;
1349 }
1350
1351 /* It is possible to get from SBI more than max number of counters */
1352 if (num_counters > RISCV_MAX_COUNTERS) {
1353 num_counters = RISCV_MAX_COUNTERS;
1354 pr_info("SBI returned more than maximum number of counters. Limiting the number of counters to %d\n", num_counters);
1355 }
1356
1357 /* cache all the information about counters now */
1358 if (pmu_sbi_get_ctrinfo(num_counters, &cmask))
1359 goto out_free;
1360
1361 ret = pmu_sbi_setup_irqs(pmu, pdev);
1362 if (ret < 0) {
1363 pr_info("Perf sampling/filtering is not supported as sscof extension is not available\n");
1364 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1365 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
1366 }
1367
1368 pmu->pmu.attr_groups = riscv_pmu_attr_groups;
1369 pmu->pmu.parent = &pdev->dev;
1370 pmu->cmask = cmask;
1371 pmu->ctr_start = pmu_sbi_ctr_start;
1372 pmu->ctr_stop = pmu_sbi_ctr_stop;
1373 pmu->event_map = pmu_sbi_event_map;
1374 pmu->ctr_get_idx = pmu_sbi_ctr_get_idx;
1375 pmu->ctr_get_width = pmu_sbi_ctr_get_width;
1376 pmu->ctr_clear_idx = pmu_sbi_ctr_clear_idx;
1377 pmu->ctr_read = pmu_sbi_ctr_read;
1378 pmu->event_init = pmu_sbi_event_init;
1379 pmu->event_mapped = pmu_sbi_event_mapped;
1380 pmu->event_unmapped = pmu_sbi_event_unmapped;
1381 pmu->csr_index = pmu_sbi_csr_index;
1382
1383 ret = riscv_pm_pmu_register(pmu);
1384 if (ret)
1385 goto out_unregister;
1386
1387 ret = perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW);
1388 if (ret)
1389 goto out_unregister;
1390
1391 /* SBI PMU Snapsphot is only available in SBI v2.0 */
1392 if (sbi_v2_available) {
1393 int cpu;
1394
1395 ret = pmu_sbi_snapshot_alloc(pmu);
1396 if (ret)
1397 goto out_unregister;
1398
1399 cpu = get_cpu();
1400 ret = pmu_sbi_snapshot_setup(pmu, cpu);
1401 put_cpu();
1402
1403 if (ret) {
1404 /* Snapshot is an optional feature. Continue if not available */
1405 pmu_sbi_snapshot_free(pmu);
1406 } else {
1407 pr_info("SBI PMU snapshot detected\n");
1408 /*
1409 * We enable it once here for the boot cpu. If snapshot shmem setup
1410 * fails during cpu hotplug process, it will fail to start the cpu
1411 * as we can not handle hetergenous PMUs with different snapshot
1412 * capability.
1413 */
1414 static_branch_enable(&sbi_pmu_snapshot_available);
1415 }
1416 }
1417
1418 register_sysctl("kernel", sbi_pmu_sysctl_table);
1419
1420 ret = cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node);
1421 if (ret)
1422 goto out_unregister;
1423
1424 /* Asynchronously check which standard events are available */
1425 schedule_work(&check_std_events_work);
1426
1427 return 0;
1428
1429 out_unregister:
1430 riscv_pmu_destroy(pmu);
1431
1432 out_free:
1433 kfree(pmu);
1434 return ret;
1435 }
1436
1437 static struct platform_driver pmu_sbi_driver = {
1438 .probe = pmu_sbi_device_probe,
1439 .driver = {
1440 .name = RISCV_PMU_SBI_PDEV_NAME,
1441 },
1442 };
1443
pmu_sbi_devinit(void)1444 static int __init pmu_sbi_devinit(void)
1445 {
1446 int ret;
1447 struct platform_device *pdev;
1448
1449 if (sbi_spec_version < sbi_mk_version(0, 3) ||
1450 !sbi_probe_extension(SBI_EXT_PMU)) {
1451 return 0;
1452 }
1453
1454 if (sbi_spec_version >= sbi_mk_version(2, 0))
1455 sbi_v2_available = true;
1456
1457 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING,
1458 "perf/riscv/pmu:starting",
1459 pmu_sbi_starting_cpu, pmu_sbi_dying_cpu);
1460 if (ret) {
1461 pr_err("CPU hotplug notifier could not be registered: %d\n",
1462 ret);
1463 return ret;
1464 }
1465
1466 ret = platform_driver_register(&pmu_sbi_driver);
1467 if (ret)
1468 return ret;
1469
1470 pdev = platform_device_register_simple(RISCV_PMU_SBI_PDEV_NAME, -1, NULL, 0);
1471 if (IS_ERR(pdev)) {
1472 platform_driver_unregister(&pmu_sbi_driver);
1473 return PTR_ERR(pdev);
1474 }
1475
1476 /* Notify legacy implementation that SBI pmu is available*/
1477 riscv_pmu_legacy_skip_init();
1478
1479 return ret;
1480 }
1481 device_initcall(pmu_sbi_devinit)
1482