1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 *
25 * Copyright 2025 Oxide Computer Company
26 */
27
28 #include "rge.h"
29
30 #define REG32(rgep, reg) ((uint32_t *)(rgep->io_regs+(reg)))
31 #define REG16(rgep, reg) ((uint16_t *)(rgep->io_regs+(reg)))
32 #define REG8(rgep, reg) ((uint8_t *)(rgep->io_regs+(reg)))
33 #define PIO_ADDR(rgep, offset) ((void *)(rgep->io_regs+(offset)))
34
35 /*
36 * Patchable globals:
37 *
38 * rge_autorecover
39 * Enables/disables automatic recovery after fault detection
40 */
41 static uint32_t rge_autorecover = 1;
42
43 /*
44 * globals:
45 */
46 #define RGE_DBG RGE_DBG_REGS /* debug flag for this code */
47 static uint32_t rge_watchdog_count = 1 << 5;
48 static uint32_t rge_rx_watchdog_count = 1 << 3;
49
50 /*
51 * Operating register get/set access routines
52 */
53
54 static uint32_t rge_reg_get32(rge_t *rgep, uintptr_t regno);
55 #pragma inline(rge_reg_get32)
56
57 static uint32_t
rge_reg_get32(rge_t * rgep,uintptr_t regno)58 rge_reg_get32(rge_t *rgep, uintptr_t regno)
59 {
60 RGE_TRACE(("rge_reg_get32($%p, 0x%lx)",
61 (void *)rgep, regno));
62
63 return (ddi_get32(rgep->io_handle, REG32(rgep, regno)));
64 }
65
66 static void rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data);
67 #pragma inline(rge_reg_put32)
68
69 static void
rge_reg_put32(rge_t * rgep,uintptr_t regno,uint32_t data)70 rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data)
71 {
72 RGE_TRACE(("rge_reg_put32($%p, 0x%lx, 0x%x)",
73 (void *)rgep, regno, data));
74
75 ddi_put32(rgep->io_handle, REG32(rgep, regno), data);
76 }
77
78 static void rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits);
79 #pragma inline(rge_reg_set32)
80
81 static void
rge_reg_set32(rge_t * rgep,uintptr_t regno,uint32_t bits)82 rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits)
83 {
84 uint32_t regval;
85
86 RGE_TRACE(("rge_reg_set32($%p, 0x%lx, 0x%x)",
87 (void *)rgep, regno, bits));
88
89 regval = rge_reg_get32(rgep, regno);
90 regval |= bits;
91 rge_reg_put32(rgep, regno, regval);
92 }
93
94 static void rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits);
95 #pragma inline(rge_reg_clr32)
96
97 static void
rge_reg_clr32(rge_t * rgep,uintptr_t regno,uint32_t bits)98 rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits)
99 {
100 uint32_t regval;
101
102 RGE_TRACE(("rge_reg_clr32($%p, 0x%lx, 0x%x)",
103 (void *)rgep, regno, bits));
104
105 regval = rge_reg_get32(rgep, regno);
106 regval &= ~bits;
107 rge_reg_put32(rgep, regno, regval);
108 }
109
110 static uint16_t rge_reg_get16(rge_t *rgep, uintptr_t regno);
111 #pragma inline(rge_reg_get16)
112
113 static uint16_t
rge_reg_get16(rge_t * rgep,uintptr_t regno)114 rge_reg_get16(rge_t *rgep, uintptr_t regno)
115 {
116 RGE_TRACE(("rge_reg_get16($%p, 0x%lx)",
117 (void *)rgep, regno));
118
119 return (ddi_get16(rgep->io_handle, REG16(rgep, regno)));
120 }
121
122 static void rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data);
123 #pragma inline(rge_reg_put16)
124
125 static void
rge_reg_put16(rge_t * rgep,uintptr_t regno,uint16_t data)126 rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data)
127 {
128 RGE_TRACE(("rge_reg_put16($%p, 0x%lx, 0x%x)",
129 (void *)rgep, regno, data));
130
131 ddi_put16(rgep->io_handle, REG16(rgep, regno), data);
132 }
133
134 static uint8_t rge_reg_get8(rge_t *rgep, uintptr_t regno);
135 #pragma inline(rge_reg_get8)
136
137 static uint8_t
rge_reg_get8(rge_t * rgep,uintptr_t regno)138 rge_reg_get8(rge_t *rgep, uintptr_t regno)
139 {
140 RGE_TRACE(("rge_reg_get8($%p, 0x%lx)",
141 (void *)rgep, regno));
142
143 return (ddi_get8(rgep->io_handle, REG8(rgep, regno)));
144 }
145
146 static void rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data);
147 #pragma inline(rge_reg_put8)
148
149 static void
rge_reg_put8(rge_t * rgep,uintptr_t regno,uint8_t data)150 rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data)
151 {
152 RGE_TRACE(("rge_reg_put8($%p, 0x%lx, 0x%x)",
153 (void *)rgep, regno, data));
154
155 ddi_put8(rgep->io_handle, REG8(rgep, regno), data);
156 }
157
158 static void rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits);
159 #pragma inline(rge_reg_set8)
160
161 static void
rge_reg_set8(rge_t * rgep,uintptr_t regno,uint8_t bits)162 rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits)
163 {
164 uint8_t regval;
165
166 RGE_TRACE(("rge_reg_set8($%p, 0x%lx, 0x%x)",
167 (void *)rgep, regno, bits));
168
169 regval = rge_reg_get8(rgep, regno);
170 regval |= bits;
171 rge_reg_put8(rgep, regno, regval);
172 }
173
174 static void rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits);
175 #pragma inline(rge_reg_clr8)
176
177 static void
rge_reg_clr8(rge_t * rgep,uintptr_t regno,uint8_t bits)178 rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits)
179 {
180 uint8_t regval;
181
182 RGE_TRACE(("rge_reg_clr8($%p, 0x%lx, 0x%x)",
183 (void *)rgep, regno, bits));
184
185 regval = rge_reg_get8(rgep, regno);
186 regval &= ~bits;
187 rge_reg_put8(rgep, regno, regval);
188 }
189
190 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii);
191 #pragma no_inline(rge_mii_get16)
192
193 uint16_t
rge_mii_get16(rge_t * rgep,uintptr_t mii)194 rge_mii_get16(rge_t *rgep, uintptr_t mii)
195 {
196 uint32_t regval;
197 uint32_t val32;
198 uint32_t i;
199
200 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT;
201 rge_reg_put32(rgep, PHY_ACCESS_REG, regval);
202
203 /*
204 * Waiting for PHY reading OK
205 */
206 for (i = 0; i < PHY_RESET_LOOP; i++) {
207 drv_usecwait(1000);
208 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG);
209 if (val32 & PHY_ACCESS_WR_FLAG)
210 return ((uint16_t)(val32 & 0xffff));
211 }
212
213 RGE_REPORT((rgep, "rge_mii_get16(0x%x) fail, val = %x", mii, val32));
214 return ((uint16_t)~0u);
215 }
216
217 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data);
218 #pragma no_inline(rge_mii_put16)
219
220 void
rge_mii_put16(rge_t * rgep,uintptr_t mii,uint16_t data)221 rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data)
222 {
223 uint32_t regval;
224 uint32_t val32;
225 uint32_t i;
226
227 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT;
228 regval |= data & PHY_DATA_MASK;
229 regval |= PHY_ACCESS_WR_FLAG;
230 rge_reg_put32(rgep, PHY_ACCESS_REG, regval);
231
232 /*
233 * Waiting for PHY writing OK
234 */
235 for (i = 0; i < PHY_RESET_LOOP; i++) {
236 drv_usecwait(1000);
237 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG);
238 if (!(val32 & PHY_ACCESS_WR_FLAG))
239 return;
240 }
241 RGE_REPORT((rgep, "rge_mii_put16(0x%lx, 0x%x) fail",
242 mii, data));
243 }
244
245 void rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data);
246 #pragma no_inline(rge_ephy_put16)
247
248 void
rge_ephy_put16(rge_t * rgep,uintptr_t emii,uint16_t data)249 rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data)
250 {
251 uint32_t regval;
252 uint32_t val32;
253 uint32_t i;
254
255 regval = (emii & EPHY_REG_MASK) << EPHY_REG_SHIFT;
256 regval |= data & EPHY_DATA_MASK;
257 regval |= EPHY_ACCESS_WR_FLAG;
258 rge_reg_put32(rgep, EPHY_ACCESS_REG, regval);
259
260 /*
261 * Waiting for PHY writing OK
262 */
263 for (i = 0; i < PHY_RESET_LOOP; i++) {
264 drv_usecwait(1000);
265 val32 = rge_reg_get32(rgep, EPHY_ACCESS_REG);
266 if (!(val32 & EPHY_ACCESS_WR_FLAG))
267 return;
268 }
269 RGE_REPORT((rgep, "rge_ephy_put16(0x%lx, 0x%x) fail",
270 emii, data));
271 }
272
273 /*
274 * Atomically shift a 32-bit word left, returning
275 * the value it had *before* the shift was applied
276 */
277 static uint32_t rge_atomic_shl32(uint32_t *sp, uint_t count);
278 #pragma inline(rge_mii_put16)
279
280 static uint32_t
rge_atomic_shl32(uint32_t * sp,uint_t count)281 rge_atomic_shl32(uint32_t *sp, uint_t count)
282 {
283 uint32_t oldval;
284 uint32_t newval;
285
286 /* ATOMICALLY */
287 do {
288 oldval = *sp;
289 newval = oldval << count;
290 } while (atomic_cas_32(sp, oldval, newval) != oldval);
291
292 return (oldval);
293 }
294
295 /*
296 * PHY operation routines
297 */
298 #if RGE_DEBUGGING
299
300 void
rge_phydump(rge_t * rgep)301 rge_phydump(rge_t *rgep)
302 {
303 uint16_t regs[32];
304 int i;
305
306 ASSERT(mutex_owned(rgep->genlock));
307
308 for (i = 0; i < 32; ++i) {
309 regs[i] = rge_mii_get16(rgep, i);
310 }
311
312 for (i = 0; i < 32; i += 8)
313 RGE_DEBUG(("rge_phydump: "
314 "0x%04x %04x %04x %04x %04x %04x %04x %04x",
315 regs[i+0], regs[i+1], regs[i+2], regs[i+3],
316 regs[i+4], regs[i+5], regs[i+6], regs[i+7]));
317 }
318
319 #endif /* RGE_DEBUGGING */
320
321 static void
rge_phy_check(rge_t * rgep)322 rge_phy_check(rge_t *rgep)
323 {
324 uint16_t gig_ctl;
325
326 if (rgep->param_link_up == LINK_STATE_DOWN) {
327 /*
328 * RTL8169S/8110S PHY has the "PCS bug". Need reset PHY
329 * every 15 seconds whin link down & advertise is 1000.
330 */
331 if (rgep->chipid.phy_ver == PHY_VER_S) {
332 gig_ctl = rge_mii_get16(rgep, MII_1000BASE_T_CONTROL);
333 if (gig_ctl & MII_1000BT_CTL_ADV_FDX) {
334 rgep->link_down_count++;
335 if (rgep->link_down_count > 15) {
336 (void) rge_phy_reset(rgep);
337 rgep->stats.phy_reset++;
338 rgep->link_down_count = 0;
339 }
340 }
341 }
342 } else {
343 rgep->link_down_count = 0;
344 }
345 }
346
347 /*
348 * Basic low-level function to reset the PHY.
349 * Doesn't incorporate any special-case workarounds.
350 *
351 * Returns TRUE on success, FALSE if the RESET bit doesn't clear
352 */
353 boolean_t
rge_phy_reset(rge_t * rgep)354 rge_phy_reset(rge_t *rgep)
355 {
356 uint16_t control;
357 uint_t count;
358
359 /*
360 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear
361 */
362 control = rge_mii_get16(rgep, MII_CONTROL);
363 rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET);
364 for (count = 0; count < 5; count++) {
365 drv_usecwait(100);
366 control = rge_mii_get16(rgep, MII_CONTROL);
367 if (BIC(control, MII_CONTROL_RESET))
368 return (B_TRUE);
369 }
370
371 RGE_REPORT((rgep, "rge_phy_reset: FAILED, control now 0x%x", control));
372 return (B_FALSE);
373 }
374
375 /*
376 * Synchronise the PHY's speed/duplex/autonegotiation capabilities
377 * and advertisements with the required settings as specified by the various
378 * param_* variables that can be poked via the NDD interface.
379 *
380 * We always reset the PHY and reprogram *all* the relevant registers,
381 * not just those changed. This should cause the link to go down, and then
382 * back up again once the link is stable and autonegotiation (if enabled)
383 * is complete. We should get a link state change interrupt somewhere along
384 * the way ...
385 *
386 * NOTE: <genlock> must already be held by the caller
387 */
388 void
rge_phy_update(rge_t * rgep)389 rge_phy_update(rge_t *rgep)
390 {
391 boolean_t adv_autoneg;
392 boolean_t adv_pause;
393 boolean_t adv_asym_pause;
394 boolean_t adv_1000fdx;
395 boolean_t adv_1000hdx;
396 boolean_t adv_100fdx;
397 boolean_t adv_100hdx;
398 boolean_t adv_10fdx;
399 boolean_t adv_10hdx;
400
401 uint16_t control;
402 uint16_t gigctrl;
403 uint16_t anar;
404
405 ASSERT(mutex_owned(rgep->genlock));
406
407 RGE_DEBUG(("rge_phy_update: autoneg %d "
408 "pause %d asym_pause %d "
409 "1000fdx %d 1000hdx %d "
410 "100fdx %d 100hdx %d "
411 "10fdx %d 10hdx %d ",
412 rgep->param_adv_autoneg,
413 rgep->param_adv_pause, rgep->param_adv_asym_pause,
414 rgep->param_adv_1000fdx, rgep->param_adv_1000hdx,
415 rgep->param_adv_100fdx, rgep->param_adv_100hdx,
416 rgep->param_adv_10fdx, rgep->param_adv_10hdx));
417
418 control = gigctrl = anar = 0;
419
420 /*
421 * PHY settings are normally based on the param_* variables,
422 * but if any loopback mode is in effect, that takes precedence.
423 *
424 * RGE supports MAC-internal loopback, PHY-internal loopback,
425 * and External loopback at a variety of speeds (with a special
426 * cable). In all cases, autoneg is turned OFF, full-duplex
427 * is turned ON, and the speed/mastership is forced.
428 */
429 switch (rgep->param_loop_mode) {
430 case RGE_LOOP_NONE:
431 default:
432 adv_autoneg = rgep->param_adv_autoneg;
433 adv_pause = rgep->param_adv_pause;
434 adv_asym_pause = rgep->param_adv_asym_pause;
435 adv_1000fdx = rgep->param_adv_1000fdx;
436 adv_1000hdx = rgep->param_adv_1000hdx;
437 adv_100fdx = rgep->param_adv_100fdx;
438 adv_100hdx = rgep->param_adv_100hdx;
439 adv_10fdx = rgep->param_adv_10fdx;
440 adv_10hdx = rgep->param_adv_10hdx;
441 break;
442
443 case RGE_LOOP_INTERNAL_PHY:
444 case RGE_LOOP_INTERNAL_MAC:
445 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE;
446 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE;
447 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE;
448 rgep->param_link_duplex = LINK_DUPLEX_FULL;
449
450 switch (rgep->param_loop_mode) {
451 case RGE_LOOP_INTERNAL_PHY:
452 if (rgep->chipid.mac_ver != MAC_VER_8101E) {
453 rgep->param_link_speed = 1000;
454 adv_1000fdx = B_TRUE;
455 } else {
456 rgep->param_link_speed = 100;
457 adv_100fdx = B_TRUE;
458 }
459 control = MII_CONTROL_LOOPBACK;
460 break;
461
462 case RGE_LOOP_INTERNAL_MAC:
463 if (rgep->chipid.mac_ver != MAC_VER_8101E) {
464 rgep->param_link_speed = 1000;
465 adv_1000fdx = B_TRUE;
466 } else {
467 rgep->param_link_speed = 100;
468 adv_100fdx = B_TRUE;
469 }
470 break;
471 }
472 }
473
474 RGE_DEBUG(("rge_phy_update: autoneg %d "
475 "pause %d asym_pause %d "
476 "1000fdx %d 1000hdx %d "
477 "100fdx %d 100hdx %d "
478 "10fdx %d 10hdx %d ",
479 adv_autoneg,
480 adv_pause, adv_asym_pause,
481 adv_1000fdx, adv_1000hdx,
482 adv_100fdx, adv_100hdx,
483 adv_10fdx, adv_10hdx));
484
485 /*
486 * We should have at least one technology capability set;
487 * if not, we select a default of 1000Mb/s full-duplex
488 */
489 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx &&
490 !adv_1000hdx && !adv_100hdx && !adv_10hdx) {
491 if (rgep->chipid.mac_ver != MAC_VER_8101E) {
492 adv_1000fdx = B_TRUE;
493 } else {
494 adv_100fdx = B_TRUE;
495 }
496 }
497
498 /*
499 * Now transform the adv_* variables into the proper settings
500 * of the PHY registers ...
501 *
502 * If autonegotiation is (now) enabled, we want to trigger
503 * a new autonegotiation cycle once the PHY has been
504 * programmed with the capabilities to be advertised.
505 *
506 * RTL8169/8110 doesn't support 1000Mb/s half-duplex.
507 */
508 if (adv_autoneg)
509 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN;
510
511 if (adv_1000fdx)
512 control |= MII_CONTROL_1GB|MII_CONTROL_FDUPLEX;
513 else if (adv_1000hdx)
514 control |= MII_CONTROL_1GB;
515 else if (adv_100fdx)
516 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX;
517 else if (adv_100hdx)
518 control |= MII_CONTROL_100MB;
519 else if (adv_10fdx)
520 control |= MII_CONTROL_FDUPLEX;
521 else if (adv_10hdx)
522 control |= 0;
523 else
524 { _NOTE(EMPTY); } /* Can't get here anyway ... */
525
526 if (adv_1000fdx) {
527 gigctrl |= MII_1000BT_CTL_ADV_FDX;
528 /*
529 * Chipset limitation: need set other capabilities to true
530 */
531 if (rgep->chipid.is_pcie)
532 adv_1000hdx = B_TRUE;
533 adv_100fdx = B_TRUE;
534 adv_100hdx = B_TRUE;
535 adv_10fdx = B_TRUE;
536 adv_10hdx = B_TRUE;
537 }
538
539 if (adv_1000hdx)
540 gigctrl |= MII_1000BT_CTL_ADV_HDX;
541
542 if (adv_100fdx)
543 anar |= MII_ABILITY_100BASE_TX_FD;
544 if (adv_100hdx)
545 anar |= MII_ABILITY_100BASE_TX;
546 if (adv_10fdx)
547 anar |= MII_ABILITY_10BASE_T_FD;
548 if (adv_10hdx)
549 anar |= MII_ABILITY_10BASE_T;
550
551 if (adv_pause)
552 anar |= MII_ABILITY_PAUSE;
553 if (adv_asym_pause)
554 anar |= MII_ABILITY_ASMPAUSE;
555
556 /*
557 * Munge in any other fixed bits we require ...
558 */
559 anar |= MII_AN_SELECTOR_8023;
560
561 /*
562 * Restart the PHY and write the new values. Note the
563 * time, so that we can say whether subsequent link state
564 * changes can be attributed to our reprogramming the PHY
565 */
566 rge_phy_init(rgep);
567 if (rgep->chipid.mac_ver == MAC_VER_8168B_B ||
568 rgep->chipid.mac_ver == MAC_VER_8168B_C) {
569 /* power up PHY for RTL8168B chipset */
570 rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
571 rge_mii_put16(rgep, PHY_0E_REG, 0x0000);
572 rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
573 }
574 rge_mii_put16(rgep, MII_AN_ADVERT, anar);
575 rge_mii_put16(rgep, MII_1000BASE_T_CONTROL, gigctrl);
576 rge_mii_put16(rgep, MII_CONTROL, control);
577
578 RGE_DEBUG(("rge_phy_update: anar <- 0x%x", anar));
579 RGE_DEBUG(("rge_phy_update: control <- 0x%x", control));
580 RGE_DEBUG(("rge_phy_update: gigctrl <- 0x%x", gigctrl));
581 }
582
583 void rge_phy_init(rge_t *rgep);
584 #pragma no_inline(rge_phy_init)
585
586 void
rge_phy_init(rge_t * rgep)587 rge_phy_init(rge_t *rgep)
588 {
589 rgep->phy_mii_addr = 1;
590
591 /*
592 * Below phy config steps are copied from the Programming Guide
593 * (there's no detail comments for these steps.)
594 */
595 switch (rgep->chipid.mac_ver) {
596 case MAC_VER_8169S_D:
597 case MAC_VER_8169S_E:
598 rge_mii_put16(rgep, PHY_1F_REG, 0x0001);
599 rge_mii_put16(rgep, PHY_15_REG, 0x1000);
600 rge_mii_put16(rgep, PHY_18_REG, 0x65c7);
601 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000);
602 rge_mii_put16(rgep, PHY_ID_REG_2, 0x00a1);
603 rge_mii_put16(rgep, PHY_ID_REG_1, 0x0008);
604 rge_mii_put16(rgep, PHY_BMSR_REG, 0x1020);
605 rge_mii_put16(rgep, PHY_BMCR_REG, 0x1000);
606 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0800);
607 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000);
608 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000);
609 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41);
610 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde60);
611 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140);
612 rge_mii_put16(rgep, PHY_BMCR_REG, 0x0077);
613 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7800);
614 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000);
615 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000);
616 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01);
617 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20);
618 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95);
619 rge_mii_put16(rgep, PHY_BMCR_REG, 0xfa00);
620 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa800);
621 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000);
622 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000);
623 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41);
624 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde20);
625 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140);
626 rge_mii_put16(rgep, PHY_BMCR_REG, 0x00bb);
627 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb800);
628 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000);
629 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000);
630 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01);
631 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20);
632 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95);
633 rge_mii_put16(rgep, PHY_BMCR_REG, 0xbf00);
634 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf800);
635 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000);
636 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000);
637 rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
638 rge_mii_put16(rgep, PHY_0B_REG, 0x0000);
639 break;
640
641 case MAC_VER_8169SB:
642 rge_mii_put16(rgep, PHY_1F_REG, 0x0001);
643 rge_mii_put16(rgep, PHY_1B_REG, 0xD41E);
644 rge_mii_put16(rgep, PHY_0E_REG, 0x7bff);
645 rge_mii_put16(rgep, PHY_GBCR_REG, GBCR_DEFAULT);
646 rge_mii_put16(rgep, PHY_1F_REG, 0x0002);
647 rge_mii_put16(rgep, PHY_BMSR_REG, 0x90D0);
648 rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
649 break;
650
651 case MAC_VER_8169SC:
652 rge_mii_put16(rgep, PHY_1F_REG, 0x0001);
653 rge_mii_put16(rgep, PHY_ANER_REG, 0x0078);
654 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x05dc);
655 rge_mii_put16(rgep, PHY_GBCR_REG, 0x2672);
656 rge_mii_put16(rgep, PHY_GBSR_REG, 0x6a14);
657 rge_mii_put16(rgep, PHY_0B_REG, 0x7cb0);
658 rge_mii_put16(rgep, PHY_0C_REG, 0xdb80);
659 rge_mii_put16(rgep, PHY_1B_REG, 0xc414);
660 rge_mii_put16(rgep, PHY_1C_REG, 0xef03);
661 rge_mii_put16(rgep, PHY_1D_REG, 0x3dc8);
662 rge_mii_put16(rgep, PHY_1F_REG, 0x0003);
663 rge_mii_put16(rgep, PHY_13_REG, 0x0600);
664 rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
665 break;
666
667 case MAC_VER_8168:
668 rge_mii_put16(rgep, PHY_1F_REG, 0x0001);
669 rge_mii_put16(rgep, PHY_ANER_REG, 0x00aa);
670 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x3173);
671 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x08fc);
672 rge_mii_put16(rgep, PHY_GBCR_REG, 0xe2d0);
673 rge_mii_put16(rgep, PHY_0B_REG, 0x941a);
674 rge_mii_put16(rgep, PHY_18_REG, 0x65fe);
675 rge_mii_put16(rgep, PHY_1C_REG, 0x1e02);
676 rge_mii_put16(rgep, PHY_1F_REG, 0x0002);
677 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x103e);
678 rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
679 break;
680
681 case MAC_VER_8168B_B:
682 case MAC_VER_8168B_C:
683 rge_mii_put16(rgep, PHY_1F_REG, 0x0001);
684 rge_mii_put16(rgep, PHY_0B_REG, 0x94b0);
685 rge_mii_put16(rgep, PHY_1B_REG, 0xc416);
686 rge_mii_put16(rgep, PHY_1F_REG, 0x0003);
687 rge_mii_put16(rgep, PHY_12_REG, 0x6096);
688 rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
689 break;
690 }
691 }
692
693 void rge_chip_ident(rge_t *rgep);
694 #pragma no_inline(rge_chip_ident)
695
696 void
rge_chip_ident(rge_t * rgep)697 rge_chip_ident(rge_t *rgep)
698 {
699 chip_id_t *chip = &rgep->chipid;
700 uint32_t val32;
701 uint16_t val16;
702
703 /*
704 * Read and record MAC version
705 */
706 val32 = rge_reg_get32(rgep, TX_CONFIG_REG);
707 val32 &= HW_VERSION_ID_0 | HW_VERSION_ID_1;
708 chip->mac_ver = val32;
709 chip->is_pcie = pci_lcap_locate(rgep->cfg_handle,
710 PCI_CAP_ID_PCI_E, &val16) == DDI_SUCCESS;
711
712 /*
713 * Workaround for 8101E_C
714 */
715 chip->enable_mac_first = !chip->is_pcie;
716 if (chip->mac_ver == MAC_VER_8101E_C) {
717 chip->is_pcie = B_FALSE;
718 }
719
720 /*
721 * Read and record PHY version
722 */
723 val16 = rge_mii_get16(rgep, PHY_ID_REG_2);
724 val16 &= PHY_VER_MASK;
725 chip->phy_ver = val16;
726
727 /* set pci latency timer */
728 if (chip->mac_ver == MAC_VER_8169 ||
729 chip->mac_ver == MAC_VER_8169S_D ||
730 chip->mac_ver == MAC_VER_8169S_E ||
731 chip->mac_ver == MAC_VER_8169SC)
732 pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40);
733
734 if (chip->mac_ver == MAC_VER_8169SC) {
735 val16 = rge_reg_get16(rgep, RT_CONFIG_1_REG);
736 val16 &= 0x0300;
737 if (val16 == 0x1) /* 66Mhz PCI */
738 rge_reg_put32(rgep, 0x7c, 0x000700ff);
739 else if (val16 == 0x0) /* 33Mhz PCI */
740 rge_reg_put32(rgep, 0x7c, 0x0007ff00);
741 }
742
743 /*
744 * PCIE chipset require the Rx buffer start address must be
745 * 8-byte alignment and the Rx buffer size must be multiple of 8.
746 * We'll just use bcopy in receive procedure for the PCIE chipset.
747 */
748 if (chip->is_pcie) {
749 rgep->chip_flags |= CHIP_FLAG_FORCE_BCOPY;
750 if (rgep->default_mtu > ETHERMTU) {
751 rge_notice(rgep, "Jumbo packets not supported "
752 "for this PCIE chipset");
753 rgep->default_mtu = ETHERMTU;
754 }
755 }
756 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY)
757 rgep->head_room = 0;
758 else
759 rgep->head_room = RGE_HEADROOM;
760
761 /*
762 * Initialize other variables.
763 */
764 if (rgep->default_mtu < ETHERMTU || rgep->default_mtu > RGE_JUMBO_MTU)
765 rgep->default_mtu = ETHERMTU;
766 if (rgep->default_mtu > ETHERMTU) {
767 rgep->rxbuf_size = RGE_BUFF_SIZE_JUMBO;
768 rgep->txbuf_size = RGE_BUFF_SIZE_JUMBO;
769 rgep->ethmax_size = RGE_JUMBO_SIZE;
770 } else {
771 rgep->rxbuf_size = RGE_BUFF_SIZE_STD;
772 rgep->txbuf_size = RGE_BUFF_SIZE_STD;
773 rgep->ethmax_size = ETHERMAX;
774 }
775 chip->rxconfig = RX_CONFIG_DEFAULT;
776 chip->txconfig = TX_CONFIG_DEFAULT;
777
778 /* interval to update statistics for polling mode */
779 rgep->tick_delta = drv_usectohz(1000*1000/CLK_TICK);
780
781 /* ensure we are not in polling mode */
782 rgep->curr_tick = ddi_get_lbolt() - 2*rgep->tick_delta;
783 RGE_TRACE(("%s: MAC version = %x, PHY version = %x",
784 rgep->ifname, chip->mac_ver, chip->phy_ver));
785 }
786
787 /*
788 * Perform first-stage chip (re-)initialisation, using only config-space
789 * accesses:
790 *
791 * + Read the vendor/device/revision/subsystem/cache-line-size registers,
792 * returning the data in the structure pointed to by <idp>.
793 * + Enable Memory Space accesses.
794 * + Enable Bus Mastering according.
795 */
796 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp);
797 #pragma no_inline(rge_chip_cfg_init)
798
799 void
rge_chip_cfg_init(rge_t * rgep,chip_id_t * cidp)800 rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp)
801 {
802 ddi_acc_handle_t handle;
803 uint16_t commd;
804
805 handle = rgep->cfg_handle;
806
807 /*
808 * Save PCI cache line size and subsystem vendor ID
809 */
810 cidp->command = pci_config_get16(handle, PCI_CONF_COMM);
811 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID);
812 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID);
813 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID);
814 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID);
815 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID);
816 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ);
817 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER);
818
819 /*
820 * Turn on Master Enable (DMA) and IO Enable bits.
821 * Enable PCI Memory Space accesses
822 */
823 commd = cidp->command;
824 commd |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO;
825 pci_config_put16(handle, PCI_CONF_COMM, commd);
826
827 RGE_DEBUG(("rge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x",
828 cidp->vendor, cidp->device, cidp->revision));
829 RGE_DEBUG(("rge_chip_cfg_init: subven 0x%x subdev 0x%x",
830 cidp->subven, cidp->subdev));
831 RGE_DEBUG(("rge_chip_cfg_init: clsize %d latency %d command 0x%x",
832 cidp->clsize, cidp->latency, cidp->command));
833 }
834
835 int rge_chip_reset(rge_t *rgep);
836 #pragma no_inline(rge_chip_reset)
837
838 int
rge_chip_reset(rge_t * rgep)839 rge_chip_reset(rge_t *rgep)
840 {
841 int i;
842 uint8_t val8;
843
844 /*
845 * Chip should be in STOP state
846 */
847 rge_reg_clr8(rgep, RT_COMMAND_REG,
848 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
849
850 /*
851 * Disable interrupt
852 */
853 rgep->int_mask = INT_MASK_NONE;
854 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask);
855
856 /*
857 * Clear pended interrupt
858 */
859 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL);
860
861 /*
862 * Reset chip
863 */
864 rge_reg_set8(rgep, RT_COMMAND_REG, RT_COMMAND_RESET);
865
866 /*
867 * Wait for reset success
868 */
869 for (i = 0; i < CHIP_RESET_LOOP; i++) {
870 drv_usecwait(10);
871 val8 = rge_reg_get8(rgep, RT_COMMAND_REG);
872 if (!(val8 & RT_COMMAND_RESET)) {
873 rgep->rge_chip_state = RGE_CHIP_RESET;
874 return (0);
875 }
876 }
877 RGE_REPORT((rgep, "rge_chip_reset fail."));
878 return (-1);
879 }
880
881 void rge_chip_init(rge_t *rgep);
882 #pragma no_inline(rge_chip_init)
883
884 void
rge_chip_init(rge_t * rgep)885 rge_chip_init(rge_t *rgep)
886 {
887 uint32_t val32;
888 uint32_t val16;
889 uint32_t *hashp;
890 chip_id_t *chip = &rgep->chipid;
891
892 /*
893 * Increase the threshold voltage of RX sensitivity
894 */
895 if (chip->mac_ver == MAC_VER_8168B_B ||
896 chip->mac_ver == MAC_VER_8168B_C ||
897 chip->mac_ver == MAC_VER_8101E) {
898 rge_ephy_put16(rgep, 0x01, 0x1bd3);
899 }
900
901 if (chip->mac_ver == MAC_VER_8168 ||
902 chip->mac_ver == MAC_VER_8168B_B) {
903 val16 = rge_reg_get8(rgep, PHY_STATUS_REG);
904 val16 = 0x12<<8 | val16;
905 rge_reg_put16(rgep, PHY_STATUS_REG, val16);
906 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00021c01);
907 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f088);
908 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00004000);
909 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f0b0);
910 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x0000f068);
911 val32 = rge_reg_get32(rgep, RT_CSI_DATA_REG);
912 val32 |= 0x7000;
913 val32 &= 0xffff5fff;
914 rge_reg_put32(rgep, RT_CSI_DATA_REG, val32);
915 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f068);
916 }
917
918 /*
919 * Config MII register
920 */
921 rgep->param_link_up = LINK_STATE_DOWN;
922 rge_phy_update(rgep);
923
924 /*
925 * Enable Rx checksum offload.
926 * Then for vlan support, we must enable receive vlan de-tagging.
927 * Otherwise, there'll be checksum error.
928 */
929 val16 = rge_reg_get16(rgep, CPLUS_COMMAND_REG);
930 val16 |= RX_CKSM_OFFLOAD | RX_VLAN_DETAG;
931 if (chip->mac_ver == MAC_VER_8169S_D) {
932 val16 |= CPLUS_BIT14 | MUL_PCI_RW_ENABLE;
933 rge_reg_put8(rgep, RESV_82_REG, 0x01);
934 }
935 if (chip->mac_ver == MAC_VER_8169S_E ||
936 chip->mac_ver == MAC_VER_8169SC) {
937 val16 |= MUL_PCI_RW_ENABLE;
938 }
939 rge_reg_put16(rgep, CPLUS_COMMAND_REG, val16 & (~0x03));
940
941 /*
942 * Start transmit/receive before set tx/rx configuration register
943 */
944 if (chip->enable_mac_first)
945 rge_reg_set8(rgep, RT_COMMAND_REG,
946 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
947
948 /*
949 * Change to config register write enable mode
950 */
951 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
952
953 /*
954 * Set Tx/Rx maximum packet size
955 */
956 if (rgep->default_mtu > ETHERMTU) {
957 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_JUMBO);
958 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_JUMBO);
959 } else if (rgep->chipid.mac_ver != MAC_VER_8101E) {
960 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD);
961 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD);
962 } else {
963 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD_8101E);
964 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD_8101E);
965 }
966
967 /*
968 * Set receive configuration register
969 */
970 val32 = rge_reg_get32(rgep, RX_CONFIG_REG);
971 val32 &= RX_CONFIG_REG_RESV;
972 if (rgep->promisc)
973 val32 |= RX_ACCEPT_ALL_PKT;
974 rge_reg_put32(rgep, RX_CONFIG_REG, val32 | chip->rxconfig);
975
976 /*
977 * Set transmit configuration register
978 */
979 val32 = rge_reg_get32(rgep, TX_CONFIG_REG);
980 val32 &= TX_CONFIG_REG_RESV;
981 rge_reg_put32(rgep, TX_CONFIG_REG, val32 | chip->txconfig);
982
983 /*
984 * Set Tx/Rx descriptor register
985 */
986 val32 = rgep->tx_desc.cookie.dmac_laddress;
987 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_LO_REG, val32);
988 val32 = rgep->tx_desc.cookie.dmac_laddress >> 32;
989 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_HI_REG, val32);
990 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_LO_REG, 0);
991 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_HI_REG, 0);
992 val32 = rgep->rx_desc.cookie.dmac_laddress;
993 rge_reg_put32(rgep, RX_RING_ADDR_LO_REG, val32);
994 val32 = rgep->rx_desc.cookie.dmac_laddress >> 32;
995 rge_reg_put32(rgep, RX_RING_ADDR_HI_REG, val32);
996
997 /*
998 * Suggested setting from Realtek
999 */
1000 if (rgep->chipid.mac_ver != MAC_VER_8101E)
1001 rge_reg_put16(rgep, RESV_E2_REG, 0x282a);
1002 else
1003 rge_reg_put16(rgep, RESV_E2_REG, 0x0000);
1004
1005 /*
1006 * Set multicast register
1007 */
1008 hashp = (uint32_t *)rgep->mcast_hash;
1009 if (rgep->promisc) {
1010 rge_reg_put32(rgep, MULTICAST_0_REG, ~0U);
1011 rge_reg_put32(rgep, MULTICAST_4_REG, ~0U);
1012 } else {
1013 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0]));
1014 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1]));
1015 }
1016
1017 /*
1018 * Msic register setting:
1019 * -- Missed packet counter: clear it
1020 * -- TimerInt Register
1021 * -- Timer count register
1022 */
1023 rge_reg_put32(rgep, RX_PKT_MISS_COUNT_REG, 0);
1024 rge_reg_put32(rgep, TIMER_INT_REG, TIMER_INT_NONE);
1025 rge_reg_put32(rgep, TIMER_COUNT_REG, 0);
1026
1027 /*
1028 * disable the Unicast Wakeup Frame capability
1029 */
1030 rge_reg_clr8(rgep, RT_CONFIG_5_REG, RT_UNI_WAKE_FRAME);
1031
1032 /*
1033 * Return to normal network/host communication mode
1034 */
1035 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1036 drv_usecwait(20);
1037 }
1038
1039 /*
1040 * rge_chip_start() -- start the chip transmitting and/or receiving,
1041 * including enabling interrupts
1042 */
1043 void rge_chip_start(rge_t *rgep);
1044 #pragma no_inline(rge_chip_start)
1045
1046 void
rge_chip_start(rge_t * rgep)1047 rge_chip_start(rge_t *rgep)
1048 {
1049 /*
1050 * Clear statistics
1051 */
1052 bzero(&rgep->stats, sizeof (rge_stats_t));
1053 DMA_ZERO(rgep->dma_area_stats);
1054
1055 /*
1056 * Start transmit/receive
1057 */
1058 rge_reg_set8(rgep, RT_COMMAND_REG,
1059 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
1060
1061 /*
1062 * Enable interrupt
1063 */
1064 rgep->int_mask = RGE_INT_MASK;
1065 if (rgep->chipid.is_pcie) {
1066 rgep->int_mask |= NO_TXDESC_INT;
1067 }
1068 rgep->rx_fifo_ovf = 0;
1069 rgep->int_mask |= RX_FIFO_OVERFLOW_INT;
1070 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask);
1071
1072 /*
1073 * All done!
1074 */
1075 rgep->rge_chip_state = RGE_CHIP_RUNNING;
1076 }
1077
1078 /*
1079 * rge_chip_stop() -- stop board receiving
1080 *
1081 * Since this function is also invoked by rge_quiesce(), it
1082 * must not block; also, no tracing or logging takes place
1083 * when invoked by rge_quiesce().
1084 */
1085 void rge_chip_stop(rge_t *rgep, boolean_t fault);
1086 #pragma no_inline(rge_chip_stop)
1087
1088 void
rge_chip_stop(rge_t * rgep,boolean_t fault)1089 rge_chip_stop(rge_t *rgep, boolean_t fault)
1090 {
1091 /*
1092 * Disable interrupt
1093 */
1094 rgep->int_mask = INT_MASK_NONE;
1095 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask);
1096
1097 /*
1098 * Clear pended interrupt
1099 */
1100 if (!rgep->suspended) {
1101 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL);
1102 }
1103
1104 /*
1105 * Stop the board and disable transmit/receive
1106 */
1107 rge_reg_clr8(rgep, RT_COMMAND_REG,
1108 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
1109
1110 if (fault)
1111 rgep->rge_chip_state = RGE_CHIP_FAULT;
1112 else
1113 rgep->rge_chip_state = RGE_CHIP_STOPPED;
1114 }
1115
1116 /*
1117 * rge_get_mac_addr() -- get the MAC address on NIC
1118 */
1119 static void rge_get_mac_addr(rge_t *rgep);
1120 #pragma inline(rge_get_mac_addr)
1121
1122 static void
rge_get_mac_addr(rge_t * rgep)1123 rge_get_mac_addr(rge_t *rgep)
1124 {
1125 uint8_t *macaddr = rgep->netaddr;
1126 uint32_t val32;
1127
1128 /*
1129 * Read first 4-byte of mac address
1130 */
1131 val32 = rge_reg_get32(rgep, ID_0_REG);
1132 macaddr[0] = val32 & 0xff;
1133 val32 = val32 >> 8;
1134 macaddr[1] = val32 & 0xff;
1135 val32 = val32 >> 8;
1136 macaddr[2] = val32 & 0xff;
1137 val32 = val32 >> 8;
1138 macaddr[3] = val32 & 0xff;
1139
1140 /*
1141 * Read last 2-byte of mac address
1142 */
1143 val32 = rge_reg_get32(rgep, ID_4_REG);
1144 macaddr[4] = val32 & 0xff;
1145 val32 = val32 >> 8;
1146 macaddr[5] = val32 & 0xff;
1147 }
1148
1149 static void rge_set_mac_addr(rge_t *rgep);
1150 #pragma inline(rge_set_mac_addr)
1151
1152 static void
rge_set_mac_addr(rge_t * rgep)1153 rge_set_mac_addr(rge_t *rgep)
1154 {
1155 uint8_t *p = rgep->netaddr;
1156 uint32_t val32;
1157
1158 /*
1159 * Change to config register write enable mode
1160 */
1161 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1162
1163 /*
1164 * Get first 4 bytes of mac address
1165 */
1166 val32 = p[3];
1167 val32 = val32 << 8;
1168 val32 |= p[2];
1169 val32 = val32 << 8;
1170 val32 |= p[1];
1171 val32 = val32 << 8;
1172 val32 |= p[0];
1173
1174 /*
1175 * Set first 4 bytes of mac address
1176 */
1177 rge_reg_put32(rgep, ID_0_REG, val32);
1178
1179 /*
1180 * Get last 2 bytes of mac address
1181 */
1182 val32 = p[5];
1183 val32 = val32 << 8;
1184 val32 |= p[4];
1185
1186 /*
1187 * Set last 2 bytes of mac address
1188 */
1189 val32 |= rge_reg_get32(rgep, ID_4_REG) & ~0xffff;
1190 rge_reg_put32(rgep, ID_4_REG, val32);
1191
1192 /*
1193 * Return to normal network/host communication mode
1194 */
1195 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1196 }
1197
1198 static void rge_set_multi_addr(rge_t *rgep);
1199 #pragma inline(rge_set_multi_addr)
1200
1201 static void
rge_set_multi_addr(rge_t * rgep)1202 rge_set_multi_addr(rge_t *rgep)
1203 {
1204 uint32_t *hashp;
1205
1206 hashp = (uint32_t *)rgep->mcast_hash;
1207
1208 /*
1209 * Change to config register write enable mode
1210 */
1211 if (rgep->chipid.mac_ver == MAC_VER_8169SC) {
1212 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1213 }
1214 if (rgep->promisc) {
1215 rge_reg_put32(rgep, MULTICAST_0_REG, ~0U);
1216 rge_reg_put32(rgep, MULTICAST_4_REG, ~0U);
1217 } else {
1218 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0]));
1219 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1]));
1220 }
1221
1222 /*
1223 * Return to normal network/host communication mode
1224 */
1225 if (rgep->chipid.mac_ver == MAC_VER_8169SC) {
1226 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1227 }
1228 }
1229
1230 static void rge_set_promisc(rge_t *rgep);
1231 #pragma inline(rge_set_promisc)
1232
1233 static void
rge_set_promisc(rge_t * rgep)1234 rge_set_promisc(rge_t *rgep)
1235 {
1236 if (rgep->promisc)
1237 rge_reg_set32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT);
1238 else
1239 rge_reg_clr32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT);
1240 }
1241
1242 /*
1243 * rge_chip_sync() -- program the chip with the unicast MAC address,
1244 * the multicast hash table, the required level of promiscuity, and
1245 * the current loopback mode ...
1246 */
1247 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo);
1248 #pragma no_inline(rge_chip_sync)
1249
1250 void
rge_chip_sync(rge_t * rgep,enum rge_sync_op todo)1251 rge_chip_sync(rge_t *rgep, enum rge_sync_op todo)
1252 {
1253 switch (todo) {
1254 case RGE_GET_MAC:
1255 rge_get_mac_addr(rgep);
1256 break;
1257 case RGE_SET_MAC:
1258 /* Reprogram the unicast MAC address(es) ... */
1259 rge_set_mac_addr(rgep);
1260 break;
1261 case RGE_SET_MUL:
1262 /* Reprogram the hashed multicast address table ... */
1263 rge_set_multi_addr(rgep);
1264 break;
1265 case RGE_SET_PROMISC:
1266 /* Set or clear the PROMISCUOUS mode bit */
1267 rge_set_multi_addr(rgep);
1268 rge_set_promisc(rgep);
1269 break;
1270 default:
1271 break;
1272 }
1273 }
1274
1275 void rge_chip_blank(void *arg, time_t ticks, uint_t count, int flag);
1276 #pragma no_inline(rge_chip_blank)
1277
1278 /* ARGSUSED */
1279 void
rge_chip_blank(void * arg,time_t ticks,uint_t count,int flag)1280 rge_chip_blank(void *arg, time_t ticks, uint_t count, int flag)
1281 {
1282 _NOTE(ARGUNUSED(arg, ticks, count));
1283 }
1284
1285 void rge_tx_trigger(rge_t *rgep);
1286 #pragma no_inline(rge_tx_trigger)
1287
1288 void
rge_tx_trigger(rge_t * rgep)1289 rge_tx_trigger(rge_t *rgep)
1290 {
1291 rge_reg_put8(rgep, TX_RINGS_POLL_REG, NORMAL_TX_RING_POLL);
1292 }
1293
1294 void rge_hw_stats_dump(rge_t *rgep);
1295 #pragma no_inline(rge_tx_trigger)
1296
1297 void
rge_hw_stats_dump(rge_t * rgep)1298 rge_hw_stats_dump(rge_t *rgep)
1299 {
1300 uint32_t regval = 0;
1301
1302 if (rgep->rge_mac_state == RGE_MAC_STOPPED)
1303 return;
1304
1305 /*
1306 * Set the stats counter dump address. First, set the high part of the
1307 * address and read it back to ensure it's flushed out.
1308 */
1309 rge_reg_put32(rgep, DUMP_COUNTER_REG_1,
1310 rgep->dma_area_stats.cookie.dmac_laddress >> 32);
1311 (void) rge_reg_get32(rgep, DUMP_COUNTER_REG_1);
1312
1313 /*
1314 * Then set the low part of the address, preserving the reserved bits:
1315 */
1316 regval = rge_reg_get32(rgep, DUMP_COUNTER_REG_0);
1317 regval &= DUMP_COUNTER_REG_RESV;
1318 regval |= rgep->dma_area_stats.cookie.dmac_laddress;
1319 rge_reg_put32(rgep, DUMP_COUNTER_REG_0, regval);
1320
1321 /*
1322 * Set the command bit to start dumping statistics:
1323 */
1324 regval = rge_reg_get32(rgep, DUMP_COUNTER_REG_0);
1325 rge_reg_put32(rgep, DUMP_COUNTER_REG_0, regval | DUMP_START);
1326
1327 for (uint_t i = 0; i < STATS_DUMP_LOOP; i++) {
1328 drv_usecwait(100);
1329
1330 /*
1331 * Check to see if the dump has completed:
1332 */
1333 regval = rge_reg_get32(rgep, DUMP_COUNTER_REG_0);
1334 if ((regval & DUMP_START) == 0) {
1335 DMA_SYNC(rgep->dma_area_stats, DDI_DMA_SYNC_FORKERNEL);
1336 return;
1337 }
1338 }
1339
1340 RGE_DEBUG(("rge h/w statistics dump fail!"));
1341 rgep->rge_chip_state = RGE_CHIP_ERROR;
1342 }
1343
1344 /*
1345 * ========== Hardware interrupt handler ==========
1346 */
1347
1348 #undef RGE_DBG
1349 #define RGE_DBG RGE_DBG_INT /* debug flag for this code */
1350
1351 static void rge_wake_factotum(rge_t *rgep);
1352 #pragma inline(rge_wake_factotum)
1353
1354 static void
rge_wake_factotum(rge_t * rgep)1355 rge_wake_factotum(rge_t *rgep)
1356 {
1357 if (rgep->factotum_flag == 0) {
1358 rgep->factotum_flag = 1;
1359 (void) ddi_intr_trigger_softint(rgep->factotum_hdl, NULL);
1360 }
1361 }
1362
1363 /*
1364 * rge_intr() -- handle chip interrupts
1365 */
1366 uint_t rge_intr(caddr_t arg1, caddr_t arg2);
1367 #pragma no_inline(rge_intr)
1368
1369 uint_t
rge_intr(caddr_t arg1,caddr_t arg2)1370 rge_intr(caddr_t arg1, caddr_t arg2)
1371 {
1372 rge_t *rgep = (rge_t *)arg1;
1373 uint16_t int_status;
1374 clock_t now;
1375 uint32_t tx_pkts;
1376 uint32_t rx_pkts;
1377 uint32_t poll_rate;
1378 uint32_t opt_pkts;
1379 uint32_t opt_intrs;
1380 boolean_t update_int_mask = B_FALSE;
1381 uint32_t itimer;
1382
1383 _NOTE(ARGUNUSED(arg2))
1384
1385 mutex_enter(rgep->genlock);
1386
1387 if (rgep->suspended) {
1388 mutex_exit(rgep->genlock);
1389 return (DDI_INTR_UNCLAIMED);
1390 }
1391
1392 /*
1393 * Was this interrupt caused by our device...
1394 */
1395 int_status = rge_reg_get16(rgep, INT_STATUS_REG);
1396 if (!(int_status & rgep->int_mask)) {
1397 mutex_exit(rgep->genlock);
1398 return (DDI_INTR_UNCLAIMED);
1399 /* indicate it wasn't our interrupt */
1400 }
1401 rgep->stats.intr++;
1402
1403 /*
1404 * Clear interrupt
1405 * For PCIE chipset, we need disable interrupt first.
1406 */
1407 if (rgep->chipid.is_pcie) {
1408 rge_reg_put16(rgep, INT_MASK_REG, INT_MASK_NONE);
1409 update_int_mask = B_TRUE;
1410 }
1411 rge_reg_put16(rgep, INT_STATUS_REG, int_status);
1412
1413 /*
1414 * Calculate optimal polling interval
1415 */
1416 now = ddi_get_lbolt();
1417 if (now - rgep->curr_tick >= rgep->tick_delta &&
1418 (rgep->param_link_speed == RGE_SPEED_1000M ||
1419 rgep->param_link_speed == RGE_SPEED_100M)) {
1420 /* number of rx and tx packets in the last tick */
1421 tx_pkts = rgep->stats.opackets - rgep->last_opackets;
1422 rx_pkts = rgep->stats.rpackets - rgep->last_rpackets;
1423
1424 rgep->last_opackets = rgep->stats.opackets;
1425 rgep->last_rpackets = rgep->stats.rpackets;
1426
1427 /* restore interrupt mask */
1428 rgep->int_mask |= TX_OK_INT | RX_OK_INT;
1429 if (rgep->chipid.is_pcie) {
1430 rgep->int_mask |= NO_TXDESC_INT;
1431 }
1432
1433 /* optimal number of packets in a tick */
1434 if (rgep->param_link_speed == RGE_SPEED_1000M) {
1435 opt_pkts = (1000*1000*1000/8)/ETHERMTU/CLK_TICK;
1436 } else {
1437 opt_pkts = (100*1000*1000/8)/ETHERMTU/CLK_TICK;
1438 }
1439
1440 /*
1441 * calculate polling interval based on rx and tx packets
1442 * in the last tick
1443 */
1444 poll_rate = 0;
1445 if (now - rgep->curr_tick < 2*rgep->tick_delta) {
1446 opt_intrs = opt_pkts/TX_COALESC;
1447 if (tx_pkts > opt_intrs) {
1448 poll_rate = max(tx_pkts/TX_COALESC, opt_intrs);
1449 rgep->int_mask &= ~(TX_OK_INT | NO_TXDESC_INT);
1450 }
1451
1452 opt_intrs = opt_pkts/RX_COALESC;
1453 if (rx_pkts > opt_intrs) {
1454 opt_intrs = max(rx_pkts/RX_COALESC, opt_intrs);
1455 poll_rate = max(opt_intrs, poll_rate);
1456 rgep->int_mask &= ~RX_OK_INT;
1457 }
1458 /* ensure poll_rate reasonable */
1459 poll_rate = min(poll_rate, opt_pkts*4);
1460 }
1461
1462 if (poll_rate) {
1463 /* move to polling mode */
1464 if (rgep->chipid.is_pcie) {
1465 itimer = (TIMER_CLK_PCIE/CLK_TICK)/poll_rate;
1466 } else {
1467 itimer = (TIMER_CLK_PCI/CLK_TICK)/poll_rate;
1468 }
1469 } else {
1470 /* move to normal mode */
1471 itimer = 0;
1472 }
1473 RGE_DEBUG(("%s: poll: itimer:%d int_mask:0x%x",
1474 __func__, itimer, rgep->int_mask));
1475 rge_reg_put32(rgep, TIMER_INT_REG, itimer);
1476
1477 /* update timestamp for statistics */
1478 rgep->curr_tick = now;
1479
1480 /* reset timer */
1481 int_status |= TIME_OUT_INT;
1482
1483 update_int_mask = B_TRUE;
1484 }
1485
1486 if (int_status & TIME_OUT_INT) {
1487 rge_reg_put32(rgep, TIMER_COUNT_REG, 0);
1488 }
1489
1490 /* flush post writes */
1491 (void) rge_reg_get16(rgep, INT_STATUS_REG);
1492
1493 /*
1494 * Cable link change interrupt
1495 */
1496 if (int_status & LINK_CHANGE_INT) {
1497 rge_chip_cyclic(rgep);
1498 }
1499
1500 if (int_status & RX_FIFO_OVERFLOW_INT) {
1501 /* start rx watchdog timeout detection */
1502 rgep->rx_fifo_ovf = 1;
1503 if (rgep->int_mask & RX_FIFO_OVERFLOW_INT) {
1504 rgep->int_mask &= ~RX_FIFO_OVERFLOW_INT;
1505 update_int_mask = B_TRUE;
1506 }
1507 } else if (int_status & RGE_RX_INT) {
1508 /* stop rx watchdog timeout detection */
1509 rgep->rx_fifo_ovf = 0;
1510 if ((rgep->int_mask & RX_FIFO_OVERFLOW_INT) == 0) {
1511 rgep->int_mask |= RX_FIFO_OVERFLOW_INT;
1512 update_int_mask = B_TRUE;
1513 }
1514 }
1515
1516 mutex_exit(rgep->genlock);
1517
1518 /*
1519 * Receive interrupt
1520 */
1521 if (int_status & RGE_RX_INT)
1522 rge_receive(rgep);
1523
1524 /*
1525 * Transmit interrupt
1526 */
1527 if (int_status & TX_ERR_INT) {
1528 RGE_REPORT((rgep, "tx error happened, resetting the chip "));
1529 mutex_enter(rgep->genlock);
1530 rgep->rge_chip_state = RGE_CHIP_ERROR;
1531 mutex_exit(rgep->genlock);
1532 } else if ((rgep->chipid.is_pcie && (int_status & NO_TXDESC_INT)) ||
1533 ((int_status & TX_OK_INT) && rgep->tx_free < RGE_SEND_SLOTS/8)) {
1534 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL);
1535 }
1536
1537 /*
1538 * System error interrupt
1539 */
1540 if (int_status & SYS_ERR_INT) {
1541 RGE_REPORT((rgep, "sys error happened, resetting the chip "));
1542 mutex_enter(rgep->genlock);
1543 rgep->rge_chip_state = RGE_CHIP_ERROR;
1544 mutex_exit(rgep->genlock);
1545 }
1546
1547 /*
1548 * Re-enable interrupt for PCIE chipset or install new int_mask
1549 */
1550 if (update_int_mask)
1551 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask);
1552
1553 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */
1554 }
1555
1556 /*
1557 * ========== Factotum, implemented as a softint handler ==========
1558 */
1559
1560 #undef RGE_DBG
1561 #define RGE_DBG RGE_DBG_FACT /* debug flag for this code */
1562
1563 static boolean_t rge_factotum_link_check(rge_t *rgep);
1564 #pragma no_inline(rge_factotum_link_check)
1565
1566 static boolean_t
rge_factotum_link_check(rge_t * rgep)1567 rge_factotum_link_check(rge_t *rgep)
1568 {
1569 uint8_t media_status;
1570 int32_t link;
1571
1572 media_status = rge_reg_get8(rgep, PHY_STATUS_REG);
1573 link = (media_status & PHY_STATUS_LINK_UP) ?
1574 LINK_STATE_UP : LINK_STATE_DOWN;
1575 if (rgep->param_link_up != link) {
1576 /*
1577 * Link change.
1578 */
1579 rgep->param_link_up = link;
1580
1581 if (link == LINK_STATE_UP) {
1582 if (media_status & PHY_STATUS_1000MF) {
1583 rgep->param_link_speed = RGE_SPEED_1000M;
1584 rgep->param_link_duplex = LINK_DUPLEX_FULL;
1585 } else {
1586 rgep->param_link_speed =
1587 (media_status & PHY_STATUS_100M) ?
1588 RGE_SPEED_100M : RGE_SPEED_10M;
1589 rgep->param_link_duplex =
1590 (media_status & PHY_STATUS_DUPLEX_FULL) ?
1591 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF;
1592 }
1593 }
1594 return (B_TRUE);
1595 }
1596 return (B_FALSE);
1597 }
1598
1599 /*
1600 * Factotum routine to check for Tx stall, using the 'watchdog' counter
1601 */
1602 static boolean_t rge_factotum_stall_check(rge_t *rgep);
1603 #pragma no_inline(rge_factotum_stall_check)
1604
1605 static boolean_t
rge_factotum_stall_check(rge_t * rgep)1606 rge_factotum_stall_check(rge_t *rgep)
1607 {
1608 uint32_t dogval;
1609
1610 ASSERT(mutex_owned(rgep->genlock));
1611
1612 /*
1613 * Specific check for RX stall ...
1614 */
1615 rgep->rx_fifo_ovf <<= 1;
1616 if (rgep->rx_fifo_ovf > rge_rx_watchdog_count) {
1617 RGE_REPORT((rgep, "rx_hang detected"));
1618 return (B_TRUE);
1619 }
1620
1621 /*
1622 * Specific check for Tx stall ...
1623 *
1624 * The 'watchdog' counter is incremented whenever a packet
1625 * is queued, reset to 1 when some (but not all) buffers
1626 * are reclaimed, reset to 0 (disabled) when all buffers
1627 * are reclaimed, and shifted left here. If it exceeds the
1628 * threshold value, the chip is assumed to have stalled and
1629 * is put into the ERROR state. The factotum will then reset
1630 * it on the next pass.
1631 *
1632 * All of which should ensure that we don't get into a state
1633 * where packets are left pending indefinitely!
1634 */
1635 if (rgep->resched_needed)
1636 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL);
1637 dogval = rge_atomic_shl32(&rgep->watchdog, 1);
1638 if (dogval < rge_watchdog_count)
1639 return (B_FALSE);
1640
1641 RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval));
1642 return (B_TRUE);
1643
1644 }
1645
1646 /*
1647 * The factotum is woken up when there's something to do that we'd rather
1648 * not do from inside a hardware interrupt handler or high-level cyclic.
1649 * Its two main tasks are:
1650 * reset & restart the chip after an error
1651 * check the link status whenever necessary
1652 */
1653 uint_t rge_chip_factotum(caddr_t arg1, caddr_t arg2);
1654 #pragma no_inline(rge_chip_factotum)
1655
1656 uint_t
rge_chip_factotum(caddr_t arg1,caddr_t arg2)1657 rge_chip_factotum(caddr_t arg1, caddr_t arg2)
1658 {
1659 rge_t *rgep;
1660 uint_t result;
1661 boolean_t error;
1662 boolean_t linkchg;
1663
1664 rgep = (rge_t *)arg1;
1665 _NOTE(ARGUNUSED(arg2))
1666
1667 if (rgep->factotum_flag == 0)
1668 return (DDI_INTR_UNCLAIMED);
1669
1670 rgep->factotum_flag = 0;
1671 result = DDI_INTR_CLAIMED;
1672 error = B_FALSE;
1673 linkchg = B_FALSE;
1674
1675 mutex_enter(rgep->genlock);
1676 switch (rgep->rge_chip_state) {
1677 default:
1678 break;
1679
1680 case RGE_CHIP_RUNNING:
1681 linkchg = rge_factotum_link_check(rgep);
1682 error = rge_factotum_stall_check(rgep);
1683 break;
1684
1685 case RGE_CHIP_ERROR:
1686 error = B_TRUE;
1687 break;
1688
1689 case RGE_CHIP_FAULT:
1690 /*
1691 * Fault detected, time to reset ...
1692 */
1693 if (rge_autorecover) {
1694 RGE_REPORT((rgep, "automatic recovery activated"));
1695 rge_restart(rgep);
1696 }
1697 break;
1698 }
1699
1700 /*
1701 * If an error is detected, stop the chip now, marking it as
1702 * faulty, so that it will be reset next time through ...
1703 */
1704 if (error)
1705 rge_chip_stop(rgep, B_TRUE);
1706 mutex_exit(rgep->genlock);
1707
1708 /*
1709 * If the link state changed, tell the world about it.
1710 * Note: can't do this while still holding the mutex.
1711 */
1712 if (linkchg)
1713 mac_link_update(rgep->mh, rgep->param_link_up);
1714
1715 return (result);
1716 }
1717
1718 /*
1719 * High-level cyclic handler
1720 *
1721 * This routine schedules a (low-level) softint callback to the
1722 * factotum, and prods the chip to update the status block (which
1723 * will cause a hardware interrupt when complete).
1724 */
1725 void rge_chip_cyclic(void *arg);
1726 #pragma no_inline(rge_chip_cyclic)
1727
1728 void
rge_chip_cyclic(void * arg)1729 rge_chip_cyclic(void *arg)
1730 {
1731 rge_t *rgep;
1732
1733 rgep = arg;
1734
1735 switch (rgep->rge_chip_state) {
1736 default:
1737 return;
1738
1739 case RGE_CHIP_RUNNING:
1740 rge_phy_check(rgep);
1741 if (rgep->tx_free < RGE_SEND_SLOTS)
1742 rge_send_recycle(rgep);
1743 break;
1744
1745 case RGE_CHIP_FAULT:
1746 case RGE_CHIP_ERROR:
1747 break;
1748 }
1749
1750 rge_wake_factotum(rgep);
1751 }
1752
1753
1754 /*
1755 * ========== Ioctl subfunctions ==========
1756 */
1757
1758 #undef RGE_DBG
1759 #define RGE_DBG RGE_DBG_PPIO /* debug flag for this code */
1760
1761 #if RGE_DEBUGGING || RGE_DO_PPIO
1762
1763 static void rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd);
1764 #pragma no_inline(rge_chip_peek_cfg)
1765
1766 static void
rge_chip_peek_cfg(rge_t * rgep,rge_peekpoke_t * ppd)1767 rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd)
1768 {
1769 uint64_t regval;
1770 uint64_t regno;
1771
1772 RGE_TRACE(("rge_chip_peek_cfg($%p, $%p)",
1773 (void *)rgep, (void *)ppd));
1774
1775 regno = ppd->pp_acc_offset;
1776
1777 switch (ppd->pp_acc_size) {
1778 case 1:
1779 regval = pci_config_get8(rgep->cfg_handle, regno);
1780 break;
1781
1782 case 2:
1783 regval = pci_config_get16(rgep->cfg_handle, regno);
1784 break;
1785
1786 case 4:
1787 regval = pci_config_get32(rgep->cfg_handle, regno);
1788 break;
1789
1790 case 8:
1791 regval = pci_config_get64(rgep->cfg_handle, regno);
1792 break;
1793 }
1794
1795 ppd->pp_acc_data = regval;
1796 }
1797
1798 static void rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd);
1799 #pragma no_inline(rge_chip_poke_cfg)
1800
1801 static void
rge_chip_poke_cfg(rge_t * rgep,rge_peekpoke_t * ppd)1802 rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd)
1803 {
1804 uint64_t regval;
1805 uint64_t regno;
1806
1807 RGE_TRACE(("rge_chip_poke_cfg($%p, $%p)",
1808 (void *)rgep, (void *)ppd));
1809
1810 regno = ppd->pp_acc_offset;
1811 regval = ppd->pp_acc_data;
1812
1813 switch (ppd->pp_acc_size) {
1814 case 1:
1815 pci_config_put8(rgep->cfg_handle, regno, regval);
1816 break;
1817
1818 case 2:
1819 pci_config_put16(rgep->cfg_handle, regno, regval);
1820 break;
1821
1822 case 4:
1823 pci_config_put32(rgep->cfg_handle, regno, regval);
1824 break;
1825
1826 case 8:
1827 pci_config_put64(rgep->cfg_handle, regno, regval);
1828 break;
1829 }
1830 }
1831
1832 static void rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd);
1833 #pragma no_inline(rge_chip_peek_reg)
1834
1835 static void
rge_chip_peek_reg(rge_t * rgep,rge_peekpoke_t * ppd)1836 rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd)
1837 {
1838 uint64_t regval;
1839 void *regaddr;
1840
1841 RGE_TRACE(("rge_chip_peek_reg($%p, $%p)",
1842 (void *)rgep, (void *)ppd));
1843
1844 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset);
1845
1846 switch (ppd->pp_acc_size) {
1847 case 1:
1848 regval = ddi_get8(rgep->io_handle, regaddr);
1849 break;
1850
1851 case 2:
1852 regval = ddi_get16(rgep->io_handle, regaddr);
1853 break;
1854
1855 case 4:
1856 regval = ddi_get32(rgep->io_handle, regaddr);
1857 break;
1858
1859 case 8:
1860 regval = ddi_get64(rgep->io_handle, regaddr);
1861 break;
1862 }
1863
1864 ppd->pp_acc_data = regval;
1865 }
1866
1867 static void rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd);
1868 #pragma no_inline(rge_chip_peek_reg)
1869
1870 static void
rge_chip_poke_reg(rge_t * rgep,rge_peekpoke_t * ppd)1871 rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd)
1872 {
1873 uint64_t regval;
1874 void *regaddr;
1875
1876 RGE_TRACE(("rge_chip_poke_reg($%p, $%p)",
1877 (void *)rgep, (void *)ppd));
1878
1879 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset);
1880 regval = ppd->pp_acc_data;
1881
1882 switch (ppd->pp_acc_size) {
1883 case 1:
1884 ddi_put8(rgep->io_handle, regaddr, regval);
1885 break;
1886
1887 case 2:
1888 ddi_put16(rgep->io_handle, regaddr, regval);
1889 break;
1890
1891 case 4:
1892 ddi_put32(rgep->io_handle, regaddr, regval);
1893 break;
1894
1895 case 8:
1896 ddi_put64(rgep->io_handle, regaddr, regval);
1897 break;
1898 }
1899 }
1900
1901 static void rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd);
1902 #pragma no_inline(rge_chip_peek_mii)
1903
1904 static void
rge_chip_peek_mii(rge_t * rgep,rge_peekpoke_t * ppd)1905 rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd)
1906 {
1907 RGE_TRACE(("rge_chip_peek_mii($%p, $%p)",
1908 (void *)rgep, (void *)ppd));
1909
1910 ppd->pp_acc_data = rge_mii_get16(rgep, ppd->pp_acc_offset/2);
1911 }
1912
1913 static void rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd);
1914 #pragma no_inline(rge_chip_poke_mii)
1915
1916 static void
rge_chip_poke_mii(rge_t * rgep,rge_peekpoke_t * ppd)1917 rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd)
1918 {
1919 RGE_TRACE(("rge_chip_poke_mii($%p, $%p)",
1920 (void *)rgep, (void *)ppd));
1921
1922 rge_mii_put16(rgep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
1923 }
1924
1925 static void rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd);
1926 #pragma no_inline(rge_chip_peek_mem)
1927
1928 static void
rge_chip_peek_mem(rge_t * rgep,rge_peekpoke_t * ppd)1929 rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd)
1930 {
1931 uint64_t regval;
1932 void *vaddr;
1933
1934 RGE_TRACE(("rge_chip_peek_rge($%p, $%p)",
1935 (void *)rgep, (void *)ppd));
1936
1937 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
1938
1939 switch (ppd->pp_acc_size) {
1940 case 1:
1941 regval = *(uint8_t *)vaddr;
1942 break;
1943
1944 case 2:
1945 regval = *(uint16_t *)vaddr;
1946 break;
1947
1948 case 4:
1949 regval = *(uint32_t *)vaddr;
1950 break;
1951
1952 case 8:
1953 regval = *(uint64_t *)vaddr;
1954 break;
1955 }
1956
1957 RGE_DEBUG(("rge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p",
1958 (void *)rgep, (void *)ppd, regval, vaddr));
1959
1960 ppd->pp_acc_data = regval;
1961 }
1962
1963 static void rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd);
1964 #pragma no_inline(rge_chip_poke_mem)
1965
1966 static void
rge_chip_poke_mem(rge_t * rgep,rge_peekpoke_t * ppd)1967 rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd)
1968 {
1969 uint64_t regval;
1970 void *vaddr;
1971
1972 RGE_TRACE(("rge_chip_poke_mem($%p, $%p)",
1973 (void *)rgep, (void *)ppd));
1974
1975 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
1976 regval = ppd->pp_acc_data;
1977
1978 RGE_DEBUG(("rge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p",
1979 (void *)rgep, (void *)ppd, regval, vaddr));
1980
1981 switch (ppd->pp_acc_size) {
1982 case 1:
1983 *(uint8_t *)vaddr = (uint8_t)regval;
1984 break;
1985
1986 case 2:
1987 *(uint16_t *)vaddr = (uint16_t)regval;
1988 break;
1989
1990 case 4:
1991 *(uint32_t *)vaddr = (uint32_t)regval;
1992 break;
1993
1994 case 8:
1995 *(uint64_t *)vaddr = (uint64_t)regval;
1996 break;
1997 }
1998 }
1999
2000 static enum ioc_reply rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp,
2001 struct iocblk *iocp);
2002 #pragma no_inline(rge_pp_ioctl)
2003
2004 static enum ioc_reply
rge_pp_ioctl(rge_t * rgep,int cmd,mblk_t * mp,struct iocblk * iocp)2005 rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp)
2006 {
2007 void (*ppfn)(rge_t *rgep, rge_peekpoke_t *ppd);
2008 rge_peekpoke_t *ppd;
2009 dma_area_t *areap;
2010 uint64_t sizemask;
2011 uint64_t mem_va;
2012 uint64_t maxoff;
2013 boolean_t peek;
2014
2015 switch (cmd) {
2016 default:
2017 /* NOTREACHED */
2018 rge_error(rgep, "rge_pp_ioctl: invalid cmd 0x%x", cmd);
2019 return (IOC_INVAL);
2020
2021 case RGE_PEEK:
2022 peek = B_TRUE;
2023 break;
2024
2025 case RGE_POKE:
2026 peek = B_FALSE;
2027 break;
2028 }
2029
2030 /*
2031 * Validate format of ioctl
2032 */
2033 if (iocp->ioc_count != sizeof (rge_peekpoke_t))
2034 return (IOC_INVAL);
2035 if (mp->b_cont == NULL)
2036 return (IOC_INVAL);
2037 ppd = (rge_peekpoke_t *)mp->b_cont->b_rptr;
2038
2039 /*
2040 * Validate request parameters
2041 */
2042 switch (ppd->pp_acc_space) {
2043 default:
2044 return (IOC_INVAL);
2045
2046 case RGE_PP_SPACE_CFG:
2047 /*
2048 * Config space
2049 */
2050 sizemask = 8|4|2|1;
2051 mem_va = 0;
2052 maxoff = PCI_CONF_HDR_SIZE;
2053 ppfn = peek ? rge_chip_peek_cfg : rge_chip_poke_cfg;
2054 break;
2055
2056 case RGE_PP_SPACE_REG:
2057 /*
2058 * Memory-mapped I/O space
2059 */
2060 sizemask = 8|4|2|1;
2061 mem_va = 0;
2062 maxoff = RGE_REGISTER_MAX;
2063 ppfn = peek ? rge_chip_peek_reg : rge_chip_poke_reg;
2064 break;
2065
2066 case RGE_PP_SPACE_MII:
2067 /*
2068 * PHY's MII registers
2069 * NB: all PHY registers are two bytes, but the
2070 * addresses increment in ones (word addressing).
2071 * So we scale the address here, then undo the
2072 * transformation inside the peek/poke functions.
2073 */
2074 ppd->pp_acc_offset *= 2;
2075 sizemask = 2;
2076 mem_va = 0;
2077 maxoff = (MII_MAXREG+1)*2;
2078 ppfn = peek ? rge_chip_peek_mii : rge_chip_poke_mii;
2079 break;
2080
2081 case RGE_PP_SPACE_RGE:
2082 /*
2083 * RGE data structure!
2084 */
2085 sizemask = 8|4|2|1;
2086 mem_va = (uintptr_t)rgep;
2087 maxoff = sizeof (*rgep);
2088 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem;
2089 break;
2090
2091 case RGE_PP_SPACE_STATISTICS:
2092 case RGE_PP_SPACE_TXDESC:
2093 case RGE_PP_SPACE_TXBUFF:
2094 case RGE_PP_SPACE_RXDESC:
2095 case RGE_PP_SPACE_RXBUFF:
2096 /*
2097 * Various DMA_AREAs
2098 */
2099 switch (ppd->pp_acc_space) {
2100 case RGE_PP_SPACE_TXDESC:
2101 areap = &rgep->dma_area_txdesc;
2102 break;
2103 case RGE_PP_SPACE_RXDESC:
2104 areap = &rgep->dma_area_rxdesc;
2105 break;
2106 case RGE_PP_SPACE_STATISTICS:
2107 areap = &rgep->dma_area_stats;
2108 break;
2109 }
2110
2111 sizemask = 8|4|2|1;
2112 mem_va = (uintptr_t)areap->mem_va;
2113 maxoff = areap->alength;
2114 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem;
2115 break;
2116 }
2117
2118 switch (ppd->pp_acc_size) {
2119 default:
2120 return (IOC_INVAL);
2121
2122 case 8:
2123 case 4:
2124 case 2:
2125 case 1:
2126 if ((ppd->pp_acc_size & sizemask) == 0)
2127 return (IOC_INVAL);
2128 break;
2129 }
2130
2131 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
2132 return (IOC_INVAL);
2133
2134 if (ppd->pp_acc_offset >= maxoff)
2135 return (IOC_INVAL);
2136
2137 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff)
2138 return (IOC_INVAL);
2139
2140 /*
2141 * All OK - go do it!
2142 */
2143 ppd->pp_acc_offset += mem_va;
2144 (*ppfn)(rgep, ppd);
2145 return (peek ? IOC_REPLY : IOC_ACK);
2146 }
2147
2148 static enum ioc_reply rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp,
2149 struct iocblk *iocp);
2150 #pragma no_inline(rge_diag_ioctl)
2151
2152 static enum ioc_reply
rge_diag_ioctl(rge_t * rgep,int cmd,mblk_t * mp,struct iocblk * iocp)2153 rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp)
2154 {
2155 ASSERT(mutex_owned(rgep->genlock));
2156
2157 switch (cmd) {
2158 default:
2159 /* NOTREACHED */
2160 rge_error(rgep, "rge_diag_ioctl: invalid cmd 0x%x", cmd);
2161 return (IOC_INVAL);
2162
2163 case RGE_DIAG:
2164 /*
2165 * Currently a no-op
2166 */
2167 return (IOC_ACK);
2168
2169 case RGE_PEEK:
2170 case RGE_POKE:
2171 return (rge_pp_ioctl(rgep, cmd, mp, iocp));
2172
2173 case RGE_PHY_RESET:
2174 return (IOC_RESTART_ACK);
2175
2176 case RGE_SOFT_RESET:
2177 case RGE_HARD_RESET:
2178 /*
2179 * Reset and reinitialise the 570x hardware
2180 */
2181 rge_restart(rgep);
2182 return (IOC_ACK);
2183 }
2184
2185 /* NOTREACHED */
2186 }
2187
2188 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */
2189
2190 static enum ioc_reply rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp,
2191 struct iocblk *iocp);
2192 #pragma no_inline(rge_mii_ioctl)
2193
2194 static enum ioc_reply
rge_mii_ioctl(rge_t * rgep,int cmd,mblk_t * mp,struct iocblk * iocp)2195 rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp)
2196 {
2197 struct rge_mii_rw *miirwp;
2198
2199 /*
2200 * Validate format of ioctl
2201 */
2202 if (iocp->ioc_count != sizeof (struct rge_mii_rw))
2203 return (IOC_INVAL);
2204 if (mp->b_cont == NULL)
2205 return (IOC_INVAL);
2206 miirwp = (struct rge_mii_rw *)mp->b_cont->b_rptr;
2207
2208 /*
2209 * Validate request parameters ...
2210 */
2211 if (miirwp->mii_reg > MII_MAXREG)
2212 return (IOC_INVAL);
2213
2214 switch (cmd) {
2215 default:
2216 /* NOTREACHED */
2217 rge_error(rgep, "rge_mii_ioctl: invalid cmd 0x%x", cmd);
2218 return (IOC_INVAL);
2219
2220 case RGE_MII_READ:
2221 miirwp->mii_data = rge_mii_get16(rgep, miirwp->mii_reg);
2222 return (IOC_REPLY);
2223
2224 case RGE_MII_WRITE:
2225 rge_mii_put16(rgep, miirwp->mii_reg, miirwp->mii_data);
2226 return (IOC_ACK);
2227 }
2228
2229 /* NOTREACHED */
2230 }
2231
2232 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp,
2233 struct iocblk *iocp);
2234 #pragma no_inline(rge_chip_ioctl)
2235
2236 enum ioc_reply
rge_chip_ioctl(rge_t * rgep,queue_t * wq,mblk_t * mp,struct iocblk * iocp)2237 rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
2238 {
2239 int cmd;
2240
2241 RGE_TRACE(("rge_chip_ioctl($%p, $%p, $%p, $%p)",
2242 (void *)rgep, (void *)wq, (void *)mp, (void *)iocp));
2243
2244 ASSERT(mutex_owned(rgep->genlock));
2245
2246 cmd = iocp->ioc_cmd;
2247 switch (cmd) {
2248 default:
2249 /* NOTREACHED */
2250 rge_error(rgep, "rge_chip_ioctl: invalid cmd 0x%x", cmd);
2251 return (IOC_INVAL);
2252
2253 case RGE_DIAG:
2254 case RGE_PEEK:
2255 case RGE_POKE:
2256 case RGE_PHY_RESET:
2257 case RGE_SOFT_RESET:
2258 case RGE_HARD_RESET:
2259 #if RGE_DEBUGGING || RGE_DO_PPIO
2260 return (rge_diag_ioctl(rgep, cmd, mp, iocp));
2261 #else
2262 return (IOC_INVAL);
2263 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */
2264
2265 case RGE_MII_READ:
2266 case RGE_MII_WRITE:
2267 return (rge_mii_ioctl(rgep, cmd, mp, iocp));
2268
2269 }
2270
2271 /* NOTREACHED */
2272 }
2273