1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019, 2020, 2023-2025 Kevin Lo <kevlo@openbsd.org>
5 * Copyright (c) 2025 Adrian Chadd <adrian@FreeBSD.org>
6 *
7 * Hardware programming portions from Realtek Semiconductor.
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 */
21
22 /* $OpenBSD: if_rge.c,v 1.38 2025/09/19 00:41:14 kevlo Exp $ */
23
24 #include <sys/param.h>
25 #include <sys/systm.h>
26 #include <sys/sockio.h>
27 #include <sys/mbuf.h>
28 #include <sys/malloc.h>
29 #include <sys/endian.h>
30 #include <sys/socket.h>
31 #include <net/if.h>
32 #include <net/if_media.h>
33 #include <sys/queue.h>
34 #include <sys/taskqueue.h>
35 #include <sys/bus.h>
36 #include <sys/module.h>
37 #include <sys/rman.h>
38
39 #include <netinet/in.h>
40 #include <netinet/if_ether.h>
41
42 #include <net/bpf.h>
43 #include <net/ethernet.h>
44 #include <net/if.h>
45 #include <net/if_var.h>
46 #include <net/if_arp.h>
47 #include <net/if_dl.h>
48 #include <net/if_media.h>
49 #include <net/if_types.h>
50 #include <net/if_vlan_var.h>
51
52 #include <machine/bus.h>
53 #include <machine/resource.h>
54
55 #include <dev/mii/mii.h>
56
57 #include <dev/pci/pcivar.h>
58 #include <dev/pci/pcireg.h>
59
60 #include "if_rge_vendor.h"
61 #include "if_rgereg.h"
62 #include "if_rgevar.h"
63 #include "if_rge_microcode.h"
64 #include "if_rge_debug.h"
65
66 #include "if_rge_hw.h"
67
68 static int rge_reset(struct rge_softc *sc);
69 static void rge_set_phy_power(struct rge_softc *sc, int on);
70 static uint64_t rge_mcu_get_bin_version(uint16_t entries);
71 static void rge_mcu_set_version(struct rge_softc *sc, uint64_t mcodever);
72 static void rge_ephy_config_mac_r25(struct rge_softc *sc);
73 static void rge_ephy_config_mac_r25b(struct rge_softc *sc);
74 static void rge_ephy_config_mac_r27(struct rge_softc *sc);
75 static void rge_phy_config_mac_r27(struct rge_softc *sc);
76 static void rge_phy_config_mac_r26(struct rge_softc *sc);
77 static void rge_phy_config_mac_r25(struct rge_softc *sc);
78 static void rge_phy_config_mac_r25b(struct rge_softc *sc);
79 static void rge_phy_config_mac_r25d(struct rge_softc *sc);
80 static void rge_phy_config_mcu(struct rge_softc *sc, uint16_t rcodever);
81 static void rge_hw_init(struct rge_softc *sc);
82 static void rge_disable_phy_ocp_pwrsave(struct rge_softc *sc);
83 static void rge_patch_phy_mcu(struct rge_softc *sc, int set);
84 static void rge_disable_hw_im(struct rge_softc *sc);
85 static void rge_disable_sim_im(struct rge_softc *sc);
86 static void rge_setup_sim_im(struct rge_softc *sc);
87 static void rge_switch_mcu_ram_page(struct rge_softc *sc, int page);
88 static int rge_exit_oob(struct rge_softc *sc);
89 static void rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val);
90 static uint16_t rge_read_ephy(struct rge_softc *sc, uint16_t reg);
91 static uint16_t rge_check_ephy_ext_add(struct rge_softc *sc, uint16_t reg);
92 static void rge_r27_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val);
93
94 static int
rge_reset(struct rge_softc * sc)95 rge_reset(struct rge_softc *sc)
96 {
97 int i;
98
99 RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV |
100 RGE_RXCFG_MULTI | RGE_RXCFG_BROAD | RGE_RXCFG_RUNT |
101 RGE_RXCFG_ERRPKT);
102
103 /* Enable RXDV gate. */
104 RGE_SETBIT_1(sc, RGE_PPSW, 0x08);
105
106 RGE_SETBIT_1(sc, RGE_CMD, RGE_CMD_STOPREQ);
107 if (sc->rge_type == MAC_R25) {
108 for (i = 0; i < 20; i++) {
109 DELAY(10);
110 if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_STOPREQ))
111 break;
112 }
113 if (i == 20) {
114 RGE_PRINT_ERROR(sc, "failed to stop all requests\n");
115 return ETIMEDOUT;
116 }
117 } else
118 DELAY(200);
119
120 for (i = 0; i < 3000; i++) {
121 DELAY(50);
122 if ((RGE_READ_1(sc, RGE_MCUCMD) & (RGE_MCUCMD_RXFIFO_EMPTY |
123 RGE_MCUCMD_TXFIFO_EMPTY)) == (RGE_MCUCMD_RXFIFO_EMPTY |
124 RGE_MCUCMD_TXFIFO_EMPTY))
125 break;
126 }
127 if (sc->rge_type != MAC_R25) {
128 for (i = 0; i < 3000; i++) {
129 DELAY(50);
130 if ((RGE_READ_2(sc, RGE_IM) & 0x0103) == 0x0103)
131 break;
132 }
133 }
134
135 RGE_WRITE_1(sc, RGE_CMD,
136 RGE_READ_1(sc, RGE_CMD) & (RGE_CMD_TXENB | RGE_CMD_RXENB));
137
138 /* Soft reset. */
139 RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_RESET);
140
141 for (i = 0; i < RGE_TIMEOUT; i++) {
142 DELAY(100);
143 if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_RESET))
144 break;
145 }
146 if (i == RGE_TIMEOUT) {
147 RGE_PRINT_ERROR(sc, "reset never completed!\n");
148 return ETIMEDOUT;
149 }
150
151 return 0;
152 }
153
154 /**
155 * @brief Do initial chip power-on and setup.
156 *
157 * Must be called with the driver lock held.
158 */
159 int
rge_chipinit(struct rge_softc * sc)160 rge_chipinit(struct rge_softc *sc)
161 {
162 int error;
163
164 RGE_ASSERT_LOCKED(sc);
165
166 if ((error = rge_exit_oob(sc)) != 0)
167 return error;
168 rge_set_phy_power(sc, 1);
169 rge_hw_init(sc);
170 rge_hw_reset(sc);
171
172 return 0;
173 }
174
175 static void
rge_set_phy_power(struct rge_softc * sc,int on)176 rge_set_phy_power(struct rge_softc *sc, int on)
177 {
178 int i;
179
180 if (on) {
181 RGE_SETBIT_1(sc, RGE_PMCH, 0xc0);
182
183 rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN);
184
185 for (i = 0; i < RGE_TIMEOUT; i++) {
186 if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 3)
187 break;
188 DELAY(1000);
189 }
190 } else {
191 rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN | BMCR_PDOWN);
192 RGE_CLRBIT_1(sc, RGE_PMCH, 0x80);
193 RGE_CLRBIT_1(sc, RGE_PPSW, 0x40);
194 }
195 }
196
197 void
rge_mac_config_mcu(struct rge_softc * sc,enum rge_mac_type type)198 rge_mac_config_mcu(struct rge_softc *sc, enum rge_mac_type type)
199 {
200 uint64_t mcodever;
201 uint16_t reg;
202 int i, npages;
203
204 if (type == MAC_R25) {
205 for (npages = 0; npages < 3; npages++) {
206 rge_switch_mcu_ram_page(sc, npages);
207 for (i = 0; i < nitems(rtl8125_mac_bps); i++) {
208 if (npages == 0)
209 rge_write_mac_ocp(sc,
210 rtl8125_mac_bps[i].reg,
211 rtl8125_mac_bps[i].val);
212 else if (npages == 1)
213 rge_write_mac_ocp(sc,
214 rtl8125_mac_bps[i].reg, 0);
215 else {
216 if (rtl8125_mac_bps[i].reg < 0xf9f8)
217 rge_write_mac_ocp(sc,
218 rtl8125_mac_bps[i].reg, 0);
219 }
220 }
221 if (npages == 2) {
222 rge_write_mac_ocp(sc, 0xf9f8, 0x6486);
223 rge_write_mac_ocp(sc, 0xf9fa, 0x0b15);
224 rge_write_mac_ocp(sc, 0xf9fc, 0x090e);
225 rge_write_mac_ocp(sc, 0xf9fe, 0x1139);
226 }
227 }
228 rge_write_mac_ocp(sc, 0xfc26, 0x8000);
229 rge_write_mac_ocp(sc, 0xfc2a, 0x0540);
230 rge_write_mac_ocp(sc, 0xfc2e, 0x0a06);
231 rge_write_mac_ocp(sc, 0xfc30, 0x0eb8);
232 rge_write_mac_ocp(sc, 0xfc32, 0x3a5c);
233 rge_write_mac_ocp(sc, 0xfc34, 0x10a8);
234 rge_write_mac_ocp(sc, 0xfc40, 0x0d54);
235 rge_write_mac_ocp(sc, 0xfc42, 0x0e24);
236 rge_write_mac_ocp(sc, 0xfc48, 0x307a);
237 } else if (type == MAC_R25B) {
238 rge_switch_mcu_ram_page(sc, 0);
239 for (i = 0; i < nitems(rtl8125b_mac_bps); i++) {
240 rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg,
241 rtl8125b_mac_bps[i].val);
242 }
243 } else if (type == MAC_R25D) {
244 for (npages = 0; npages < 3; npages++) {
245 rge_switch_mcu_ram_page(sc, npages);
246
247 rge_write_mac_ocp(sc, 0xf800,
248 (npages == 0) ? 0xe002 : 0);
249 rge_write_mac_ocp(sc, 0xf802,
250 (npages == 0) ? 0xe006 : 0);
251 rge_write_mac_ocp(sc, 0xf804,
252 (npages == 0) ? 0x4166 : 0);
253 rge_write_mac_ocp(sc, 0xf806,
254 (npages == 0) ? 0x9cf6 : 0);
255 rge_write_mac_ocp(sc, 0xf808,
256 (npages == 0) ? 0xc002 : 0);
257 rge_write_mac_ocp(sc, 0xf80a,
258 (npages == 0) ? 0xb800 : 0);
259 rge_write_mac_ocp(sc, 0xf80c,
260 (npages == 0) ? 0x14a4 : 0);
261 rge_write_mac_ocp(sc, 0xf80e,
262 (npages == 0) ? 0xc102 : 0);
263 rge_write_mac_ocp(sc, 0xf810,
264 (npages == 0) ? 0xb900 : 0);
265
266 for (reg = 0xf812; reg <= 0xf9f6; reg += 2)
267 rge_write_mac_ocp(sc, reg, 0);
268
269 rge_write_mac_ocp(sc, 0xf9f8,
270 (npages == 2) ? 0x6938 : 0);
271 rge_write_mac_ocp(sc, 0xf9fa,
272 (npages == 2) ? 0x0a18 : 0);
273 rge_write_mac_ocp(sc, 0xf9fc,
274 (npages == 2) ? 0x0217 : 0);
275 rge_write_mac_ocp(sc, 0xf9fe,
276 (npages == 2) ? 0x0d2a : 0);
277 }
278 rge_write_mac_ocp(sc, 0xfc26, 0x8000);
279 rge_write_mac_ocp(sc, 0xfc28, 0x14a2);
280 rge_write_mac_ocp(sc, 0xfc48, 0x0001);
281 } else if (type == MAC_R27) {
282 mcodever = rge_mcu_get_bin_version(nitems(rtl8127_mac_bps));
283 if (sc->rge_mcodever != mcodever) {
284 /* Switch to page 0. */
285 rge_switch_mcu_ram_page(sc, 0);
286 for (i = 0; i < 256; i++)
287 rge_write_mac_ocp(sc, rtl8127_mac_bps[i].reg,
288 rtl8127_mac_bps[i].val);
289 /* Switch to page 1. */
290 rge_switch_mcu_ram_page(sc, 1);
291 for (; i < nitems(rtl8127_mac_bps); i++)
292 rge_write_mac_ocp(sc, rtl8127_mac_bps[i].reg,
293 rtl8127_mac_bps[i].val);
294 }
295 rge_write_mac_ocp(sc, 0xfc26, 0x8000);
296 rge_write_mac_ocp(sc, 0xfc28, 0x1520);
297 rge_write_mac_ocp(sc, 0xfc2a, 0x41e0);
298 rge_write_mac_ocp(sc, 0xfc2c, 0x508c);
299 rge_write_mac_ocp(sc, 0xfc2e, 0x50f6);
300 rge_write_mac_ocp(sc, 0xfc30, 0x34fa);
301 rge_write_mac_ocp(sc, 0xfc32, 0x0166);
302 rge_write_mac_ocp(sc, 0xfc34, 0x1a6a);
303 rge_write_mac_ocp(sc, 0xfc36, 0x1a2c);
304 rge_write_mac_ocp(sc, 0xfc48, 0x00ff);
305
306 /* Write microcode version. */
307 rge_mcu_set_version(sc, mcodever);
308 }
309 }
310
311 static uint64_t
rge_mcu_get_bin_version(uint16_t entries)312 rge_mcu_get_bin_version(uint16_t entries)
313 {
314 uint64_t binver = 0;
315 int i;
316
317 for (i = 0; i < 4; i++) {
318 binver <<= 16;
319 binver |= rtl8127_mac_bps[entries - 4 + i].val;
320 }
321
322 return binver;
323 }
324
325 static void
rge_mcu_set_version(struct rge_softc * sc,uint64_t mcodever)326 rge_mcu_set_version(struct rge_softc *sc, uint64_t mcodever)
327 {
328 int i;
329
330 /* Switch to page 2. */
331 rge_switch_mcu_ram_page(sc, 2);
332
333 for (i = 0; i < 8; i += 2) {
334 rge_write_mac_ocp(sc, 0xf9f8 + 6 - i, (uint16_t)mcodever);
335 mcodever >>= 16;
336 }
337
338 /* Switch back to page 0. */
339 rge_switch_mcu_ram_page(sc, 0);
340 }
341
342 void
rge_ephy_config(struct rge_softc * sc)343 rge_ephy_config(struct rge_softc *sc)
344 {
345 switch (sc->rge_type) {
346 case MAC_R25:
347 rge_ephy_config_mac_r25(sc);
348 break;
349 case MAC_R25B:
350 rge_ephy_config_mac_r25b(sc);
351 break;
352 case MAC_R27:
353 rge_ephy_config_mac_r27(sc);
354 break;
355 default:
356 break; /* Nothing to do. */
357 }
358 }
359
360 static void
rge_ephy_config_mac_r25(struct rge_softc * sc)361 rge_ephy_config_mac_r25(struct rge_softc *sc)
362 {
363 uint16_t val;
364 int i;
365
366 for (i = 0; i < nitems(mac_r25_ephy); i++)
367 rge_write_ephy(sc, mac_r25_ephy[i].reg, mac_r25_ephy[i].val);
368
369 val = rge_read_ephy(sc, 0x002a) & ~0x7000;
370 rge_write_ephy(sc, 0x002a, val | 0x3000);
371 RGE_EPHY_CLRBIT(sc, 0x0019, 0x0040);
372 RGE_EPHY_SETBIT(sc, 0x001b, 0x0e00);
373 RGE_EPHY_CLRBIT(sc, 0x001b, 0x7000);
374 rge_write_ephy(sc, 0x0002, 0x6042);
375 rge_write_ephy(sc, 0x0006, 0x0014);
376 val = rge_read_ephy(sc, 0x006a) & ~0x7000;
377 rge_write_ephy(sc, 0x006a, val | 0x3000);
378 RGE_EPHY_CLRBIT(sc, 0x0059, 0x0040);
379 RGE_EPHY_SETBIT(sc, 0x005b, 0x0e00);
380 RGE_EPHY_CLRBIT(sc, 0x005b, 0x7000);
381 rge_write_ephy(sc, 0x0042, 0x6042);
382 rge_write_ephy(sc, 0x0046, 0x0014);
383 }
384
385 static void
rge_ephy_config_mac_r25b(struct rge_softc * sc)386 rge_ephy_config_mac_r25b(struct rge_softc *sc)
387 {
388 int i;
389
390 for (i = 0; i < nitems(mac_r25b_ephy); i++)
391 rge_write_ephy(sc, mac_r25b_ephy[i].reg, mac_r25b_ephy[i].val);
392 }
393
394 static void
rge_ephy_config_mac_r27(struct rge_softc * sc)395 rge_ephy_config_mac_r27(struct rge_softc *sc)
396 {
397 int i;
398
399 for (i = 0; i < nitems(mac_r27_ephy); i++)
400 rge_r27_write_ephy(sc, mac_r27_ephy[i].reg,
401 mac_r27_ephy[i].val);
402
403 /* Clear extended address. */
404 rge_write_ephy(sc, RGE_EPHYAR_EXT_ADDR, 0);
405 }
406
407 int
rge_phy_config(struct rge_softc * sc)408 rge_phy_config(struct rge_softc *sc)
409 {
410 uint16_t val = 0;
411 int i;
412
413 rge_ephy_config(sc);
414
415 /* PHY reset. */
416 rge_write_phy(sc, 0, MII_ANAR,
417 rge_read_phy(sc, 0, MII_ANAR) &
418 ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10));
419 rge_write_phy(sc, 0, MII_100T2CR,
420 rge_read_phy(sc, 0, MII_100T2CR) &
421 ~(GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX));
422 switch (sc->rge_type) {
423 case MAC_R27:
424 val |= RGE_ADV_10000TFDX;
425 /* fallthrough */
426 case MAC_R26:
427 val |= RGE_ADV_5000TFDX;
428 /* fallthrough */
429 default:
430 val |= RGE_ADV_2500TFDX;
431 break;
432 }
433 RGE_PHY_CLRBIT(sc, 0xa5d4, val);
434 rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN |
435 BMCR_STARTNEG);
436 for (i = 0; i < 2500; i++) {
437 if (!(rge_read_phy(sc, 0, MII_BMCR) & BMCR_RESET))
438 break;
439 DELAY(1000);
440 }
441 if (i == 2500) {
442 RGE_PRINT_ERROR(sc, "PHY reset failed\n");
443 return (ETIMEDOUT);
444 }
445
446 /* Read ram code version. */
447 rge_write_phy_ocp(sc, 0xa436, 0x801e);
448 sc->rge_rcodever = rge_read_phy_ocp(sc, 0xa438);
449
450 switch (sc->rge_type) {
451 case MAC_R25:
452 rge_phy_config_mac_r25(sc);
453 break;
454 case MAC_R25B:
455 rge_phy_config_mac_r25b(sc);
456 break;
457 case MAC_R25D:
458 rge_phy_config_mac_r25d(sc);
459 break;
460 case MAC_R26:
461 rge_phy_config_mac_r26(sc);
462 break;
463 case MAC_R27:
464 rge_phy_config_mac_r27(sc);
465 break;
466 default:
467 break; /* Can't happen. */
468 }
469
470 RGE_PHY_CLRBIT(sc, 0xa5b4, 0x8000);
471
472 /* Disable EEE. */
473 RGE_MAC_CLRBIT(sc, 0xe040, 0x0003);
474 if (sc->rge_type == MAC_R25) {
475 RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006);
476 RGE_PHY_CLRBIT(sc, 0xa432, 0x0010);
477 } else if (sc->rge_type == MAC_R25B || sc->rge_type == MAC_R25D)
478 RGE_PHY_SETBIT(sc, 0xa432, 0x0010);
479
480 RGE_PHY_CLRBIT(sc, 0xa5d0, (sc->rge_type == MAC_R27) ? 0x000e : 0x0006);
481 RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001);
482 if (sc->rge_type == MAC_R26 || sc->rge_type == MAC_R27)
483 RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0002);
484 RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010);
485 RGE_PHY_CLRBIT(sc, 0xa428, 0x0080);
486 RGE_PHY_CLRBIT(sc, 0xa4a2, 0x0200);
487
488 /* Disable advanced EEE. */
489 RGE_MAC_CLRBIT(sc, 0xe052, 0x0001);
490 RGE_PHY_CLRBIT(sc, 0xa442, 0x3000);
491 RGE_PHY_CLRBIT(sc, 0xa430, 0x8000);
492
493 return (0);
494 }
495
496 static void
rge_phy_config_mac_r27(struct rge_softc * sc)497 rge_phy_config_mac_r27(struct rge_softc *sc)
498 {
499 uint16_t val;
500 int i;
501 static const uint16_t mac_cfg_value[] =
502 { 0x815a, 0x0150, 0x81f4, 0x0150, 0x828e, 0x0150, 0x81b1, 0x0000,
503 0x824b, 0x0000, 0x82e5, 0x0000 };
504
505 static const uint16_t mac_cfg2_value[] =
506 { 0x88d7, 0x01a0, 0x88d9, 0x01a0, 0x8ffa, 0x002a, 0x8fee, 0xffdf,
507 0x8ff0, 0xffff, 0x8ff2, 0x0a4a, 0x8ff4, 0xaa5a, 0x8ff6, 0x0a4a,
508 0x8ff8, 0xaa5a };
509
510 static const uint16_t mac_cfg_a438_value[] =
511 { 0x003b, 0x0086, 0x00b7, 0x00db, 0x00fe, 0x00fe, 0x00fe, 0x00fe,
512 0x00c3, 0x0078, 0x0047, 0x0023 };
513
514 rge_phy_config_mcu(sc, RGE_MAC_R27_RCODE_VER);
515
516 rge_write_phy_ocp(sc, 0xa4d2, 0x0000);
517 rge_read_phy_ocp(sc, 0xa4d4);
518
519 RGE_PHY_CLRBIT(sc, 0xa442, 0x0800);
520 rge_write_phy_ocp(sc, 0xa436, 0x8415);
521 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
522 rge_write_phy_ocp(sc, 0xa438, val | 0x9300);
523 rge_write_phy_ocp(sc, 0xa436, 0x81a3);
524 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
525 rge_write_phy_ocp(sc, 0xa438, val | 0x0f00);
526 rge_write_phy_ocp(sc, 0xa436, 0x81ae);
527 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
528 rge_write_phy_ocp(sc, 0xa438, val | 0x0f00);
529 rge_write_phy_ocp(sc, 0xa436, 0x81b9);
530 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
531 rge_write_phy_ocp(sc, 0xa438, val | 0xb900);
532 rge_write_phy_ocp(sc, 0xb87c, 0x83b0);
533 RGE_PHY_CLRBIT(sc,0xb87e, 0x0e00);
534 rge_write_phy_ocp(sc, 0xb87c, 0x83c5);
535 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0e00);
536 rge_write_phy_ocp(sc, 0xb87c, 0x83da);
537 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0e00);
538 rge_write_phy_ocp(sc, 0xb87c, 0x83ef);
539 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0e00);
540 val = rge_read_phy_ocp(sc, 0xbf38) & ~0x01f0;
541 rge_write_phy_ocp(sc, 0xbf38, val | 0x0160);
542 val = rge_read_phy_ocp(sc, 0xbf3a) & ~0x001f;
543 rge_write_phy_ocp(sc, 0xbf3a, val | 0x0014);
544 RGE_PHY_CLRBIT(sc, 0xbf28, 0x6000);
545 RGE_PHY_CLRBIT(sc, 0xbf2c, 0xc000);
546 val = rge_read_phy_ocp(sc, 0xbf28) & ~0x1fff;
547 rge_write_phy_ocp(sc, 0xbf28, val | 0x0187);
548 val = rge_read_phy_ocp(sc, 0xbf2a) & ~0x003f;
549 rge_write_phy_ocp(sc, 0xbf2a, val | 0x0003);
550 rge_write_phy_ocp(sc, 0xa436, 0x8173);
551 rge_write_phy_ocp(sc, 0xa438, 0x8620);
552 rge_write_phy_ocp(sc, 0xa436, 0x8175);
553 rge_write_phy_ocp(sc, 0xa438, 0x8671);
554 rge_write_phy_ocp(sc, 0xa436, 0x817c);
555 RGE_PHY_SETBIT(sc, 0xa438, 0x2000);
556 rge_write_phy_ocp(sc, 0xa436, 0x8187);
557 RGE_PHY_SETBIT(sc, 0xa438, 0x2000);
558 rge_write_phy_ocp(sc, 0xA436, 0x8192);
559 RGE_PHY_SETBIT(sc, 0xA438, 0x2000);
560 rge_write_phy_ocp(sc, 0xA436, 0x819D);
561 RGE_PHY_SETBIT(sc, 0xA438, 0x2000);
562 rge_write_phy_ocp(sc, 0xA436, 0x81A8);
563 RGE_PHY_CLRBIT(sc, 0xA438, 0x2000);
564 rge_write_phy_ocp(sc, 0xA436, 0x81B3);
565 RGE_PHY_CLRBIT(sc, 0xA438, 0x2000);
566 rge_write_phy_ocp(sc, 0xA436, 0x81BE);
567 RGE_PHY_SETBIT(sc, 0xA438, 0x2000);
568 rge_write_phy_ocp(sc, 0xa436, 0x817d);
569 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
570 rge_write_phy_ocp(sc, 0xa438, val | 0xa600);
571 rge_write_phy_ocp(sc, 0xa436, 0x8188);
572 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
573 rge_write_phy_ocp(sc, 0xa438, val | 0xa600);
574 rge_write_phy_ocp(sc, 0xa436, 0x8193);
575 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
576 rge_write_phy_ocp(sc, 0xa438, val | 0xa600);
577 rge_write_phy_ocp(sc, 0xa436, 0x819e);
578 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
579 rge_write_phy_ocp(sc, 0xa438, val | 0xa600);
580 rge_write_phy_ocp(sc, 0xa436, 0x81a9);
581 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
582 rge_write_phy_ocp(sc, 0xa438, val | 0x1400);
583 rge_write_phy_ocp(sc, 0xa436, 0x81b4);
584 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
585 rge_write_phy_ocp(sc, 0xa438, val | 0x1400);
586 rge_write_phy_ocp(sc, 0xa436, 0x81bf);
587 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
588 rge_write_phy_ocp(sc, 0xa438, val | 0xa600);
589 RGE_PHY_CLRBIT(sc, 0xaeaa, 0x0028);
590 rge_write_phy_ocp(sc, 0xb87c, 0x84f0);
591 rge_write_phy_ocp(sc, 0xb87e, 0x201c);
592 rge_write_phy_ocp(sc, 0xb87c, 0x84f2);
593 rge_write_phy_ocp(sc, 0xb87e, 0x3117);
594 rge_write_phy_ocp(sc, 0xaec6, 0x0000);
595 rge_write_phy_ocp(sc, 0xae20, 0xffff);
596 rge_write_phy_ocp(sc, 0xaece, 0xffff);
597 rge_write_phy_ocp(sc, 0xaed2, 0xffff);
598 rge_write_phy_ocp(sc, 0xaec8, 0x0000);
599 RGE_PHY_CLRBIT(sc, 0xaed0, 0x0001);
600 rge_write_phy_ocp(sc, 0xadb8, 0x0150);
601 rge_write_phy_ocp(sc, 0xb87c, 0x8197);
602 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
603 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000);
604 rge_write_phy_ocp(sc, 0xb87c, 0x8231);
605 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
606 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000);
607 rge_write_phy_ocp(sc, 0xb87c, 0x82cb);
608 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
609 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000);
610 rge_write_phy_ocp(sc, 0xb87c, 0x82cd);
611 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
612 rge_write_phy_ocp(sc, 0xb87e, val | 0x5700);
613 rge_write_phy_ocp(sc, 0xb87c, 0x8233);
614 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
615 rge_write_phy_ocp(sc, 0xb87e, val | 0x5700);
616 rge_write_phy_ocp(sc, 0xb87c, 0x8199);
617 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
618 rge_write_phy_ocp(sc, 0xb87e, val | 0x5700);
619 for (i = 0; i < nitems(mac_cfg_value); i+=2) {
620 rge_write_phy_ocp(sc, 0xb87c, mac_cfg_value[i]);
621 rge_write_phy_ocp(sc, 0xb87e, mac_cfg_value[i + 1]);
622 }
623 rge_write_phy_ocp(sc, 0xb87c, 0x84f7);
624 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
625 rge_write_phy_ocp(sc, 0xb87e, val | 0x2800);
626 RGE_PHY_SETBIT(sc, 0xaec2, 0x1000);
627 rge_write_phy_ocp(sc, 0xb87c, 0x81b3);
628 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
629 rge_write_phy_ocp(sc, 0xb87e, val | 0xad00);
630 rge_write_phy_ocp(sc, 0xb87c, 0x824d);
631 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
632 rge_write_phy_ocp(sc, 0xb87e, val | 0xad00);
633 rge_write_phy_ocp(sc, 0xb87c, 0x82e7);
634 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
635 rge_write_phy_ocp(sc, 0xb87e, val | 0xad00);
636 val = rge_read_phy_ocp(sc, 0xae4e) & ~0x000f;
637 rge_write_phy_ocp(sc, 0xae4e, val | 0x0001);
638 rge_write_phy_ocp(sc, 0xb87c, 0x82ce);
639 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xf000;
640 rge_write_phy_ocp(sc, 0xb87e, val | 0x4000);
641 rge_write_phy_ocp(sc, 0xb87c, 0x84ac);
642 rge_write_phy_ocp(sc, 0xb87e, 0x0000);
643 rge_write_phy_ocp(sc, 0xb87c, 0x84ae);
644 rge_write_phy_ocp(sc, 0xb87e, 0x0000);
645 rge_write_phy_ocp(sc, 0xb87c, 0x84b0);
646 rge_write_phy_ocp(sc, 0xb87e, 0xf818);
647 rge_write_phy_ocp(sc, 0xb87c, 0x84b2);
648 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
649 rge_write_phy_ocp(sc, 0xb87e, val | 0x6000);
650 rge_write_phy_ocp(sc, 0xb87c, 0x8ffc);
651 rge_write_phy_ocp(sc, 0xb87e, 0x6008);
652 rge_write_phy_ocp(sc, 0xb87c, 0x8ffe);
653 rge_write_phy_ocp(sc, 0xb87e, 0xf450);
654 rge_write_phy_ocp(sc, 0xb87c, 0x8015);
655 RGE_PHY_SETBIT(sc, 0xb87e, 0x0200);
656 rge_write_phy_ocp(sc, 0xb87c, 0x8016);
657 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0800);
658 rge_write_phy_ocp(sc, 0xb87c, 0x8fe6);
659 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
660 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
661 rge_write_phy_ocp(sc, 0xb87c, 0x8fe4);
662 rge_write_phy_ocp(sc, 0xb87e, 0x2114);
663 rge_write_phy_ocp(sc, 0xb87c, 0x8647);
664 rge_write_phy_ocp(sc, 0xb87e, 0xa7B1);
665 rge_write_phy_ocp(sc, 0xb87c, 0x8649);
666 rge_write_phy_ocp(sc, 0xb87e, 0xbbca);
667 rge_write_phy_ocp(sc, 0xb87c, 0x864b);
668 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
669 rge_write_phy_ocp(sc, 0xb87e, val | 0xdc00);
670 rge_write_phy_ocp(sc, 0xb87c, 0x8154);
671 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xc000;
672 rge_write_phy_ocp(sc, 0xb87e, val | 0x4000);
673 rge_write_phy_ocp(sc, 0xb87c, 0x8158);
674 RGE_PHY_CLRBIT(sc, 0xb87e, 0xc000);
675 rge_write_phy_ocp(sc, 0xb87c, 0x826c);
676 rge_write_phy_ocp(sc, 0xb87e, 0xffff);
677 rge_write_phy_ocp(sc, 0xb87c, 0x826e);
678 rge_write_phy_ocp(sc, 0xb87e, 0xffff);
679 rge_write_phy_ocp(sc, 0xb87c, 0x8872);
680 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
681 rge_write_phy_ocp(sc, 0xb87e, val | 0x0e00);
682 rge_write_phy_ocp(sc, 0xa436, 0x8012);
683 RGE_PHY_SETBIT(sc, 0xa438, 0x0800);
684 rge_write_phy_ocp(sc, 0xa436, 0x8012);
685 RGE_PHY_SETBIT(sc, 0xa438, 0x4000);
686 RGE_PHY_SETBIT(sc, 0xb576, 0x0001);
687 rge_write_phy_ocp(sc, 0xa436, 0x834a);
688 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
689 rge_write_phy_ocp(sc, 0xa438, val | 0x0700);
690 rge_write_phy_ocp(sc, 0xb87c, 0x8217);
691 val = rge_read_phy_ocp(sc, 0xb87e) & ~0x3f00;
692 rge_write_phy_ocp(sc, 0xb87e, val | 0x2a00);
693 rge_write_phy_ocp(sc, 0xa436, 0x81b1);
694 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
695 rge_write_phy_ocp(sc, 0xa438, val | 0x0b00);
696 rge_write_phy_ocp(sc, 0xb87c, 0x8fed);
697 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
698 rge_write_phy_ocp(sc, 0xb87e, val | 0x4e00);
699 rge_write_phy_ocp(sc, 0xb87c, 0x88ac);
700 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
701 rge_write_phy_ocp(sc, 0xb87e, val | 0x2300);
702 RGE_PHY_SETBIT(sc, 0xbf0c, 0x3800);
703 rge_write_phy_ocp(sc, 0xb87c, 0x88de);
704 RGE_PHY_CLRBIT(sc, 0xb87e, 0xFF00);
705 rge_write_phy_ocp(sc, 0xb87c, 0x80B4);
706 rge_write_phy_ocp(sc, 0xb87e, 0x5195);
707 rge_write_phy_ocp(sc, 0xa436, 0x8370);
708 rge_write_phy_ocp(sc, 0xa438, 0x8671);
709 rge_write_phy_ocp(sc, 0xa436, 0x8372);
710 rge_write_phy_ocp(sc, 0xa438, 0x86c8);
711 rge_write_phy_ocp(sc, 0xa436, 0x8401);
712 rge_write_phy_ocp(sc, 0xa438, 0x86c8);
713 rge_write_phy_ocp(sc, 0xa436, 0x8403);
714 rge_write_phy_ocp(sc, 0xa438, 0x86da);
715 rge_write_phy_ocp(sc, 0xa436, 0x8406);
716 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
717 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
718 rge_write_phy_ocp(sc, 0xa436, 0x8408);
719 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
720 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
721 rge_write_phy_ocp(sc, 0xa436, 0x840a);
722 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
723 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
724 rge_write_phy_ocp(sc, 0xa436, 0x840c);
725 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
726 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
727 rge_write_phy_ocp(sc, 0xa436, 0x840e);
728 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
729 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
730 rge_write_phy_ocp(sc, 0xa436, 0x8410);
731 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
732 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
733 rge_write_phy_ocp(sc, 0xa436, 0x8412);
734 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
735 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
736 rge_write_phy_ocp(sc, 0xa436, 0x8414);
737 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
738 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
739 rge_write_phy_ocp(sc, 0xa436, 0x8416);
740 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
741 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
742 rge_write_phy_ocp(sc, 0xa436, 0x82bd);
743 rge_write_phy_ocp(sc, 0xa438, 0x1f40);
744 val = rge_read_phy_ocp(sc, 0xbfb4) & ~0x07ff;
745 rge_write_phy_ocp(sc, 0xbfb4, val | 0x0328);
746 rge_write_phy_ocp(sc, 0xbfb6, 0x3e14);
747 rge_write_phy_ocp(sc, 0xa436, 0x81c4);
748 for (i = 0; i < nitems(mac_cfg_a438_value); i++)
749 rge_write_phy_ocp(sc, 0xa438, mac_cfg_a438_value[i]);
750 for (i = 0; i < nitems(mac_cfg2_value); i+=2) {
751 rge_write_phy_ocp(sc, 0xb87c, mac_cfg2_value[i]);
752 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_value[i + 1]);
753 }
754 rge_write_phy_ocp(sc, 0xb87c, 0x88d5);
755 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
756 rge_write_phy_ocp(sc, 0xb87e, val | 0x0200);
757 rge_write_phy_ocp(sc, 0xa436, 0x84bb);
758 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
759 rge_write_phy_ocp(sc, 0xa438, val | 0x0a00);
760 rge_write_phy_ocp(sc, 0xa436, 0x84c0);
761 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
762 rge_write_phy_ocp(sc, 0xa438, val | 0x1600);
763 RGE_PHY_SETBIT(sc, 0xa430, 0x0003);
764 }
765
766 static void
rge_phy_config_mac_r26(struct rge_softc * sc)767 rge_phy_config_mac_r26(struct rge_softc *sc)
768 {
769 uint16_t val;
770 int i;
771 static const uint16_t mac_cfg2_a438_value[] =
772 { 0x0044, 0x00a8, 0x00d6, 0x00ec, 0x00f6, 0x00fc, 0x00fe,
773 0x00fe, 0x00bc, 0x0058, 0x002a, 0x003f, 0x3f02, 0x023c,
774 0x3b0a, 0x1c00, 0x0000, 0x0000, 0x0000, 0x0000 };
775
776 static const uint16_t mac_cfg2_b87e_value[] =
777 { 0x03ed, 0x03ff, 0x0009, 0x03fe, 0x000b, 0x0021, 0x03f7,
778 0x03b8, 0x03e0, 0x0049, 0x0049, 0x03e0, 0x03b8, 0x03f7,
779 0x0021, 0x000b, 0x03fe, 0x0009, 0x03ff, 0x03ed, 0x000e,
780 0x03fe, 0x03ed, 0x0006, 0x001a, 0x03f1, 0x03d8, 0x0023,
781 0x0054, 0x0322, 0x00dd, 0x03ab, 0x03dc, 0x0027, 0x000e,
782 0x03e5, 0x03f9, 0x0012, 0x0001, 0x03f1 };
783
784 rge_phy_config_mcu(sc, RGE_MAC_R26_RCODE_VER);
785
786 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
787 rge_write_phy_ocp(sc, 0xa436, 0x80bf);
788 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
789 rge_write_phy_ocp(sc, 0xa438, val | 0xed00);
790 rge_write_phy_ocp(sc, 0xa436, 0x80cd);
791 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
792 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
793 rge_write_phy_ocp(sc, 0xa436, 0x80d1);
794 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
795 rge_write_phy_ocp(sc, 0xa438, val | 0xc800);
796 rge_write_phy_ocp(sc, 0xa436, 0x80d4);
797 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
798 rge_write_phy_ocp(sc, 0xa438, val | 0xc800);
799 rge_write_phy_ocp(sc, 0xa436, 0x80e1);
800 rge_write_phy_ocp(sc, 0xa438, 0x10cc);
801 rge_write_phy_ocp(sc, 0xa436, 0x80e5);
802 rge_write_phy_ocp(sc, 0xa438, 0x4f0c);
803 rge_write_phy_ocp(sc, 0xa436, 0x8387);
804 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
805 rge_write_phy_ocp(sc, 0xa438, val | 0x4700);
806 val = rge_read_phy_ocp(sc, 0xa80c) & ~0x00c0;
807 rge_write_phy_ocp(sc, 0xa80c, val | 0x0080);
808 RGE_PHY_CLRBIT(sc, 0xac90, 0x0010);
809 RGE_PHY_CLRBIT(sc, 0xad2c, 0x8000);
810 rge_write_phy_ocp(sc, 0xb87c, 0x8321);
811 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
812 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
813 RGE_PHY_SETBIT(sc, 0xacf8, 0x000c);
814 rge_write_phy_ocp(sc, 0xa436, 0x8183);
815 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
816 rge_write_phy_ocp(sc, 0xa438, val | 0x5900);
817 RGE_PHY_SETBIT(sc, 0xad94, 0x0020);
818 RGE_PHY_CLRBIT(sc, 0xa654, 0x0800);
819 RGE_PHY_SETBIT(sc, 0xb648, 0x4000);
820 rge_write_phy_ocp(sc, 0xb87c, 0x839e);
821 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
822 rge_write_phy_ocp(sc, 0xb87e, val | 0x2f00);
823 rge_write_phy_ocp(sc, 0xb87c, 0x83f2);
824 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
825 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
826 RGE_PHY_SETBIT(sc, 0xada0, 0x0002);
827 rge_write_phy_ocp(sc, 0xb87c, 0x80f3);
828 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
829 rge_write_phy_ocp(sc, 0xb87e, val | 0x9900);
830 rge_write_phy_ocp(sc, 0xb87c, 0x8126);
831 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
832 rge_write_phy_ocp(sc, 0xb87e, val | 0xc100);
833 rge_write_phy_ocp(sc, 0xb87c, 0x893a);
834 rge_write_phy_ocp(sc, 0xb87e, 0x8080);
835 rge_write_phy_ocp(sc, 0xb87c, 0x8647);
836 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
837 rge_write_phy_ocp(sc, 0xb87e, val | 0xe600);
838 rge_write_phy_ocp(sc, 0xb87c, 0x862c);
839 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
840 rge_write_phy_ocp(sc, 0xb87e, val | 0x1200);
841 rge_write_phy_ocp(sc, 0xb87c, 0x864a);
842 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
843 rge_write_phy_ocp(sc, 0xb87e, val | 0xe600);
844 rge_write_phy_ocp(sc, 0xb87c, 0x80a0);
845 rge_write_phy_ocp(sc, 0xb87e, 0xbcbc);
846 rge_write_phy_ocp(sc, 0xb87c, 0x805e);
847 rge_write_phy_ocp(sc, 0xb87e, 0xbcbc);
848 rge_write_phy_ocp(sc, 0xb87c, 0x8056);
849 rge_write_phy_ocp(sc, 0xb87e, 0x3077);
850 rge_write_phy_ocp(sc, 0xb87c, 0x8058);
851 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
852 rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00);
853 rge_write_phy_ocp(sc, 0xb87c, 0x8098);
854 rge_write_phy_ocp(sc, 0xb87e, 0x3077);
855 rge_write_phy_ocp(sc, 0xb87c, 0x809a);
856 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
857 rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00);
858 rge_write_phy_ocp(sc, 0xb87c, 0x8052);
859 rge_write_phy_ocp(sc, 0xb87e, 0x3733);
860 rge_write_phy_ocp(sc, 0xb87c, 0x8094);
861 rge_write_phy_ocp(sc, 0xb87e, 0x3733);
862 rge_write_phy_ocp(sc, 0xb87c, 0x807f);
863 rge_write_phy_ocp(sc, 0xb87e, 0x7c75);
864 rge_write_phy_ocp(sc, 0xb87c, 0x803d);
865 rge_write_phy_ocp(sc, 0xb87e, 0x7c75);
866 rge_write_phy_ocp(sc, 0xb87c, 0x8036);
867 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
868 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000);
869 rge_write_phy_ocp(sc, 0xb87c, 0x8078);
870 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
871 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000);
872 rge_write_phy_ocp(sc, 0xb87c, 0x8031);
873 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
874 rge_write_phy_ocp(sc, 0xb87e, val | 0x3300);
875 rge_write_phy_ocp(sc, 0xb87c, 0x8073);
876 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
877 rge_write_phy_ocp(sc, 0xb87e, val | 0x3300);
878 val = rge_read_phy_ocp(sc, 0xae06) & ~0xfc00;
879 rge_write_phy_ocp(sc, 0xae06, val | 0x7c00);
880 rge_write_phy_ocp(sc, 0xb87c, 0x89D1);
881 rge_write_phy_ocp(sc, 0xb87e, 0x0004);
882 rge_write_phy_ocp(sc, 0xa436, 0x8fbd);
883 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
884 rge_write_phy_ocp(sc, 0xa438, val | 0x0a00);
885 rge_write_phy_ocp(sc, 0xa436, 0x8fbe);
886 rge_write_phy_ocp(sc, 0xa438, 0x0d09);
887 rge_write_phy_ocp(sc, 0xb87c, 0x89cd);
888 rge_write_phy_ocp(sc, 0xb87e, 0x0f0f);
889 rge_write_phy_ocp(sc, 0xb87c, 0x89cf);
890 rge_write_phy_ocp(sc, 0xb87e, 0x0f0f);
891 rge_write_phy_ocp(sc, 0xb87c, 0x83a4);
892 rge_write_phy_ocp(sc, 0xb87e, 0x6600);
893 rge_write_phy_ocp(sc, 0xb87c, 0x83a6);
894 rge_write_phy_ocp(sc, 0xb87e, 0x6601);
895 rge_write_phy_ocp(sc, 0xb87c, 0x83c0);
896 rge_write_phy_ocp(sc, 0xb87e, 0x6600);
897 rge_write_phy_ocp(sc, 0xb87c, 0x83c2);
898 rge_write_phy_ocp(sc, 0xb87e, 0x6601);
899 rge_write_phy_ocp(sc, 0xb87c, 0x8414);
900 rge_write_phy_ocp(sc, 0xb87e, 0x6600);
901 rge_write_phy_ocp(sc, 0xb87c, 0x8416);
902 rge_write_phy_ocp(sc, 0xb87e, 0x6601);
903 rge_write_phy_ocp(sc, 0xb87c, 0x83f8);
904 rge_write_phy_ocp(sc, 0xb87e, 0x6600);
905 rge_write_phy_ocp(sc, 0xb87c, 0x83fa);
906 rge_write_phy_ocp(sc, 0xb87e, 0x6601);
907
908 rge_patch_phy_mcu(sc, 1);
909 val = rge_read_phy_ocp(sc, 0xbd96) & ~0x1f00;
910 rge_write_phy_ocp(sc, 0xbd96, val | 0x1000);
911 val = rge_read_phy_ocp(sc, 0xbf1c) & ~0x0007;
912 rge_write_phy_ocp(sc, 0xbf1c, val | 0x0007);
913 RGE_PHY_CLRBIT(sc, 0xbfbe, 0x8000);
914 val = rge_read_phy_ocp(sc, 0xbf40) & ~0x0380;
915 rge_write_phy_ocp(sc, 0xbf40, val | 0x0280);
916 val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0080;
917 rge_write_phy_ocp(sc, 0xbf90, val | 0x0060);
918 val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0010;
919 rge_write_phy_ocp(sc, 0xbf90, val | 0x000c);
920 rge_patch_phy_mcu(sc, 0);
921
922 rge_write_phy_ocp(sc, 0xa436, 0x843b);
923 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
924 rge_write_phy_ocp(sc, 0xa438, val | 0x2000);
925 rge_write_phy_ocp(sc, 0xa436, 0x843d);
926 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
927 rge_write_phy_ocp(sc, 0xa438, val | 0x2000);
928 RGE_PHY_CLRBIT(sc, 0xb516, 0x007f);
929 RGE_PHY_CLRBIT(sc, 0xbf80, 0x0030);
930
931 rge_write_phy_ocp(sc, 0xa436, 0x8188);
932 for (i = 0; i < 11; i++)
933 rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]);
934
935 rge_write_phy_ocp(sc, 0xb87c, 0x8015);
936 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
937 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
938 rge_write_phy_ocp(sc, 0xb87c, 0x8ffd);
939 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
940 rge_write_phy_ocp(sc, 0xb87e, val | 0);
941 rge_write_phy_ocp(sc, 0xb87c, 0x8fff);
942 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
943 rge_write_phy_ocp(sc, 0xb87e, val | 0x7f00);
944 rge_write_phy_ocp(sc, 0xb87c, 0x8ffb);
945 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
946 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
947 rge_write_phy_ocp(sc, 0xb87c, 0x8fe9);
948 rge_write_phy_ocp(sc, 0xb87e, 0x0002);
949 rge_write_phy_ocp(sc, 0xb87c, 0x8fef);
950 rge_write_phy_ocp(sc, 0xb87e, 0x00a5);
951 rge_write_phy_ocp(sc, 0xb87c, 0x8ff1);
952 rge_write_phy_ocp(sc, 0xb87e, 0x0106);
953 rge_write_phy_ocp(sc, 0xb87c, 0x8fe1);
954 rge_write_phy_ocp(sc, 0xb87e, 0x0102);
955 rge_write_phy_ocp(sc, 0xb87c, 0x8fe3);
956 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
957 rge_write_phy_ocp(sc, 0xb87e, val | 0x0400);
958 RGE_PHY_SETBIT(sc, 0xa654, 0x0800);
959 RGE_PHY_CLRBIT(sc, 0xa654, 0x0003);
960 rge_write_phy_ocp(sc, 0xac3a, 0x5851);
961 val = rge_read_phy_ocp(sc, 0xac3c) & ~0xd000;
962 rge_write_phy_ocp(sc, 0xac3c, val | 0x2000);
963 val = rge_read_phy_ocp(sc, 0xac42) & ~0x0200;
964 rge_write_phy_ocp(sc, 0xac42, val | 0x01c0);
965 RGE_PHY_CLRBIT(sc, 0xac3e, 0xe000);
966 RGE_PHY_CLRBIT(sc, 0xac42, 0x0038);
967 val = rge_read_phy_ocp(sc, 0xac42) & ~0x0002;
968 rge_write_phy_ocp(sc, 0xac42, val | 0x0005);
969 rge_write_phy_ocp(sc, 0xac1a, 0x00db);
970 rge_write_phy_ocp(sc, 0xade4, 0x01b5);
971 RGE_PHY_CLRBIT(sc, 0xad9c, 0x0c00);
972 rge_write_phy_ocp(sc, 0xb87c, 0x814b);
973 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
974 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
975 rge_write_phy_ocp(sc, 0xb87c, 0x814d);
976 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
977 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
978 rge_write_phy_ocp(sc, 0xb87c, 0x814f);
979 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
980 rge_write_phy_ocp(sc, 0xb87e, val | 0x0b00);
981 rge_write_phy_ocp(sc, 0xb87c, 0x8142);
982 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
983 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
984 rge_write_phy_ocp(sc, 0xb87c, 0x8144);
985 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
986 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
987 rge_write_phy_ocp(sc, 0xb87c, 0x8150);
988 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
989 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
990 rge_write_phy_ocp(sc, 0xb87c, 0x8118);
991 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
992 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
993 rge_write_phy_ocp(sc, 0xb87c, 0x811a);
994 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
995 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
996 rge_write_phy_ocp(sc, 0xb87c, 0x811c);
997 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
998 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
999 rge_write_phy_ocp(sc, 0xb87c, 0x810f);
1000 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1001 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1002 rge_write_phy_ocp(sc, 0xb87c, 0x8111);
1003 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1004 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1005 rge_write_phy_ocp(sc, 0xb87c, 0x811d);
1006 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1007 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1008 RGE_PHY_SETBIT(sc, 0xac36, 0x1000);
1009 RGE_PHY_CLRBIT(sc, 0xad1c, 0x0100);
1010 val = rge_read_phy_ocp(sc, 0xade8) & ~0xffc0;
1011 rge_write_phy_ocp(sc, 0xade8, val | 0x1400);
1012 rge_write_phy_ocp(sc, 0xb87c, 0x864b);
1013 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1014 rge_write_phy_ocp(sc, 0xb87e, val | 0x9d00);
1015
1016 rge_write_phy_ocp(sc, 0xa436, 0x8f97);
1017 for (; i < nitems(mac_cfg2_a438_value); i++)
1018 rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]);
1019
1020 RGE_PHY_SETBIT(sc, 0xad9c, 0x0020);
1021 rge_write_phy_ocp(sc, 0xb87c, 0x8122);
1022 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1023 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00);
1024
1025 rge_write_phy_ocp(sc, 0xb87c, 0x82c8);
1026 for (i = 0; i < 20; i++)
1027 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]);
1028
1029 rge_write_phy_ocp(sc, 0xb87c, 0x80ef);
1030 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1031 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00);
1032
1033 rge_write_phy_ocp(sc, 0xb87c, 0x82a0);
1034 for (; i < nitems(mac_cfg2_b87e_value); i++)
1035 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]);
1036
1037 rge_write_phy_ocp(sc, 0xa436, 0x8018);
1038 RGE_PHY_SETBIT(sc, 0xa438, 0x2000);
1039 rge_write_phy_ocp(sc, 0xb87c, 0x8fe4);
1040 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1041 rge_write_phy_ocp(sc, 0xb87e, val | 0);
1042 val = rge_read_phy_ocp(sc, 0xb54c) & ~0xffc0;
1043 rge_write_phy_ocp(sc, 0xb54c, val | 0x3700);
1044 }
1045
1046 static void
rge_phy_config_mac_r25(struct rge_softc * sc)1047 rge_phy_config_mac_r25(struct rge_softc *sc)
1048 {
1049 uint16_t val;
1050 int i;
1051 static const uint16_t mac_cfg3_a438_value[] =
1052 { 0x0043, 0x00a7, 0x00d6, 0x00ec, 0x00f6, 0x00fb, 0x00fd, 0x00ff,
1053 0x00bb, 0x0058, 0x0029, 0x0013, 0x0009, 0x0004, 0x0002 };
1054
1055 static const uint16_t mac_cfg3_b88e_value[] =
1056 { 0xc091, 0x6e12, 0xc092, 0x1214, 0xc094, 0x1516, 0xc096, 0x171b,
1057 0xc098, 0x1b1c, 0xc09a, 0x1f1f, 0xc09c, 0x2021, 0xc09e, 0x2224,
1058 0xc0a0, 0x2424, 0xc0a2, 0x2424, 0xc0a4, 0x2424, 0xc018, 0x0af2,
1059 0xc01a, 0x0d4a, 0xc01c, 0x0f26, 0xc01e, 0x118d, 0xc020, 0x14f3,
1060 0xc022, 0x175a, 0xc024, 0x19c0, 0xc026, 0x1c26, 0xc089, 0x6050,
1061 0xc08a, 0x5f6e, 0xc08c, 0x6e6e, 0xc08e, 0x6e6e, 0xc090, 0x6e12 };
1062
1063 rge_phy_config_mcu(sc, RGE_MAC_R25_RCODE_VER);
1064
1065 RGE_PHY_SETBIT(sc, 0xad4e, 0x0010);
1066 val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff;
1067 rge_write_phy_ocp(sc, 0xad16, val | 0x03ff);
1068 val = rge_read_phy_ocp(sc, 0xad32) & ~0x003f;
1069 rge_write_phy_ocp(sc, 0xad32, val | 0x0006);
1070 RGE_PHY_CLRBIT(sc, 0xac08, 0x1000);
1071 RGE_PHY_CLRBIT(sc, 0xac08, 0x0100);
1072 val = rge_read_phy_ocp(sc, 0xacc0) & ~0x0003;
1073 rge_write_phy_ocp(sc, 0xacc0, val | 0x0002);
1074 val = rge_read_phy_ocp(sc, 0xad40) & ~0x00e0;
1075 rge_write_phy_ocp(sc, 0xad40, val | 0x0040);
1076 val = rge_read_phy_ocp(sc, 0xad40) & ~0x0007;
1077 rge_write_phy_ocp(sc, 0xad40, val | 0x0004);
1078 RGE_PHY_CLRBIT(sc, 0xac14, 0x0080);
1079 RGE_PHY_CLRBIT(sc, 0xac80, 0x0300);
1080 val = rge_read_phy_ocp(sc, 0xac5e) & ~0x0007;
1081 rge_write_phy_ocp(sc, 0xac5e, val | 0x0002);
1082 rge_write_phy_ocp(sc, 0xad4c, 0x00a8);
1083 rge_write_phy_ocp(sc, 0xac5c, 0x01ff);
1084 val = rge_read_phy_ocp(sc, 0xac8a) & ~0x00f0;
1085 rge_write_phy_ocp(sc, 0xac8a, val | 0x0030);
1086 rge_write_phy_ocp(sc, 0xb87c, 0x8157);
1087 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1088 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
1089 rge_write_phy_ocp(sc, 0xb87c, 0x8159);
1090 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1091 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
1092 rge_write_phy_ocp(sc, 0xb87c, 0x80a2);
1093 rge_write_phy_ocp(sc, 0xb87e, 0x0153);
1094 rge_write_phy_ocp(sc, 0xb87c, 0x809c);
1095 rge_write_phy_ocp(sc, 0xb87e, 0x0153);
1096
1097 rge_write_phy_ocp(sc, 0xa436, 0x81b3);
1098 for (i = 0; i < nitems(mac_cfg3_a438_value); i++)
1099 rge_write_phy_ocp(sc, 0xa438, mac_cfg3_a438_value[i]);
1100 for (i = 0; i < 26; i++)
1101 rge_write_phy_ocp(sc, 0xa438, 0);
1102 rge_write_phy_ocp(sc, 0xa436, 0x8257);
1103 rge_write_phy_ocp(sc, 0xa438, 0x020f);
1104 rge_write_phy_ocp(sc, 0xa436, 0x80ea);
1105 rge_write_phy_ocp(sc, 0xa438, 0x7843);
1106
1107 rge_patch_phy_mcu(sc, 1);
1108 RGE_PHY_CLRBIT(sc, 0xb896, 0x0001);
1109 RGE_PHY_CLRBIT(sc, 0xb892, 0xff00);
1110 for (i = 0; i < nitems(mac_cfg3_b88e_value); i += 2) {
1111 rge_write_phy_ocp(sc, 0xb88e, mac_cfg3_b88e_value[i]);
1112 rge_write_phy_ocp(sc, 0xb890, mac_cfg3_b88e_value[i + 1]);
1113 }
1114 RGE_PHY_SETBIT(sc, 0xb896, 0x0001);
1115 rge_patch_phy_mcu(sc, 0);
1116
1117 RGE_PHY_SETBIT(sc, 0xd068, 0x2000);
1118 rge_write_phy_ocp(sc, 0xa436, 0x81a2);
1119 RGE_PHY_SETBIT(sc, 0xa438, 0x0100);
1120 val = rge_read_phy_ocp(sc, 0xb54c) & ~0xff00;
1121 rge_write_phy_ocp(sc, 0xb54c, val | 0xdb00);
1122 RGE_PHY_CLRBIT(sc, 0xa454, 0x0001);
1123 RGE_PHY_SETBIT(sc, 0xa5d4, 0x0020);
1124 RGE_PHY_CLRBIT(sc, 0xad4e, 0x0010);
1125 RGE_PHY_CLRBIT(sc, 0xa86a, 0x0001);
1126 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
1127 RGE_PHY_SETBIT(sc, 0xa424, 0x0008);
1128 }
1129
1130 static void
rge_phy_config_mac_r25b(struct rge_softc * sc)1131 rge_phy_config_mac_r25b(struct rge_softc *sc)
1132 {
1133 uint16_t val;
1134 int i;
1135
1136 rge_phy_config_mcu(sc, RGE_MAC_R25B_RCODE_VER);
1137
1138 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
1139 val = rge_read_phy_ocp(sc, 0xac46) & ~0x00f0;
1140 rge_write_phy_ocp(sc, 0xac46, val | 0x0090);
1141 val = rge_read_phy_ocp(sc, 0xad30) & ~0x0003;
1142 rge_write_phy_ocp(sc, 0xad30, val | 0x0001);
1143 rge_write_phy_ocp(sc, 0xb87c, 0x80f5);
1144 rge_write_phy_ocp(sc, 0xb87e, 0x760e);
1145 rge_write_phy_ocp(sc, 0xb87c, 0x8107);
1146 rge_write_phy_ocp(sc, 0xb87e, 0x360e);
1147 rge_write_phy_ocp(sc, 0xb87c, 0x8551);
1148 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1149 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
1150 val = rge_read_phy_ocp(sc, 0xbf00) & ~0xe000;
1151 rge_write_phy_ocp(sc, 0xbf00, val | 0xa000);
1152 val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00;
1153 rge_write_phy_ocp(sc, 0xbf46, val | 0x0300);
1154 for (i = 0; i < 10; i++) {
1155 rge_write_phy_ocp(sc, 0xa436, 0x8044 + i * 6);
1156 rge_write_phy_ocp(sc, 0xa438, 0x2417);
1157 }
1158 RGE_PHY_SETBIT(sc, 0xa4ca, 0x0040);
1159 val = rge_read_phy_ocp(sc, 0xbf84) & ~0xe000;
1160 rge_write_phy_ocp(sc, 0xbf84, val | 0xa000);
1161 rge_write_phy_ocp(sc, 0xa436, 0x8170);
1162 val = rge_read_phy_ocp(sc, 0xa438) & ~0x2700;
1163 rge_write_phy_ocp(sc, 0xa438, val | 0xd800);
1164 RGE_PHY_SETBIT(sc, 0xa424, 0x0008);
1165 }
1166
1167 static void
rge_phy_config_mac_r25d(struct rge_softc * sc)1168 rge_phy_config_mac_r25d(struct rge_softc *sc)
1169 {
1170 uint16_t val;
1171 int i;
1172
1173 rge_phy_config_mcu(sc, RGE_MAC_R25D_RCODE_VER);
1174
1175 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
1176
1177 rge_patch_phy_mcu(sc, 1);
1178 RGE_PHY_SETBIT(sc, 0xbf96, 0x8000);
1179 val = rge_read_phy_ocp(sc, 0xbf94) & ~0x0007;
1180 rge_write_phy_ocp(sc, 0xbf94, val | 0x0005);
1181 val = rge_read_phy_ocp(sc, 0xbf8e) & ~0x3c00;
1182 rge_write_phy_ocp(sc, 0xbf8e, val | 0x2800);
1183 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
1184 rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000);
1185 RGE_PHY_SETBIT(sc, 0xbcd8, 0xc000);
1186 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
1187 rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000);
1188 val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f;
1189 rge_write_phy_ocp(sc, 0xbc80, val | 0x0004);
1190 RGE_PHY_SETBIT(sc, 0xbc82, 0xe000);
1191 RGE_PHY_SETBIT(sc, 0xbc82, 0x1c00);
1192 val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f;
1193 rge_write_phy_ocp(sc, 0xbc80, val | 0x0005);
1194 val = rge_read_phy_ocp(sc, 0xbc82) & ~0x00e0;
1195 rge_write_phy_ocp(sc, 0xbc82, val | 0x0040);
1196 RGE_PHY_SETBIT(sc, 0xbc82, 0x001c);
1197 RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000);
1198 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
1199 rge_write_phy_ocp(sc, 0xbcd8, val | 0x8000);
1200 RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000);
1201 RGE_PHY_CLRBIT(sc, 0xbd70, 0x0100);
1202 RGE_PHY_SETBIT(sc, 0xa466, 0x0002);
1203 rge_write_phy_ocp(sc, 0xa436, 0x836a);
1204 RGE_PHY_CLRBIT(sc, 0xa438, 0xff00);
1205 rge_patch_phy_mcu(sc, 0);
1206
1207 rge_write_phy_ocp(sc, 0xb87c, 0x832c);
1208 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1209 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
1210 val = rge_read_phy_ocp(sc, 0xb106) & ~0x0700;
1211 rge_write_phy_ocp(sc, 0xb106, val | 0x0100);
1212 val = rge_read_phy_ocp(sc, 0xb206) & ~0x0700;
1213 rge_write_phy_ocp(sc, 0xb206, val | 0x0200);
1214 val = rge_read_phy_ocp(sc, 0xb306) & ~0x0700;
1215 rge_write_phy_ocp(sc, 0xb306, val | 0x0300);
1216 rge_write_phy_ocp(sc, 0xb87c, 0x80cb);
1217 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1218 rge_write_phy_ocp(sc, 0xb87e, val | 0x0300);
1219 rge_write_phy_ocp(sc, 0xbcf4, 0x0000);
1220 rge_write_phy_ocp(sc, 0xbcf6, 0x0000);
1221 rge_write_phy_ocp(sc, 0xbc12, 0x0000);
1222 rge_write_phy_ocp(sc, 0xb87c, 0x844d);
1223 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1224 rge_write_phy_ocp(sc, 0xb87e, val | 0x0200);
1225
1226 rge_write_phy_ocp(sc, 0xb87c, 0x8feb);
1227 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1228 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1229 rge_write_phy_ocp(sc, 0xb87c, 0x8fe9);
1230 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1231 rge_write_phy_ocp(sc, 0xb87e, val | 0x0600);
1232
1233 val = rge_read_phy_ocp(sc, 0xac7e) & ~0x01fc;
1234 rge_write_phy_ocp(sc, 0xac7e, val | 0x00B4);
1235 rge_write_phy_ocp(sc, 0xb87c, 0x8105);
1236 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1237 rge_write_phy_ocp(sc, 0xb87e, val | 0x7a00);
1238 rge_write_phy_ocp(sc, 0xb87c, 0x8117);
1239 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1240 rge_write_phy_ocp(sc, 0xb87e, val | 0x3a00);
1241 rge_write_phy_ocp(sc, 0xb87c, 0x8103);
1242 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1243 rge_write_phy_ocp(sc, 0xb87e, val | 0x7400);
1244 rge_write_phy_ocp(sc, 0xb87c, 0x8115);
1245 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1246 rge_write_phy_ocp(sc, 0xb87e, val | 0x3400);
1247 RGE_PHY_CLRBIT(sc, 0xad40, 0x0030);
1248 val = rge_read_phy_ocp(sc, 0xad66) & ~0x000f;
1249 rge_write_phy_ocp(sc, 0xad66, val | 0x0007);
1250 val = rge_read_phy_ocp(sc, 0xad68) & ~0xf000;
1251 rge_write_phy_ocp(sc, 0xad68, val | 0x8000);
1252 val = rge_read_phy_ocp(sc, 0xad68) & ~0x0f00;
1253 rge_write_phy_ocp(sc, 0xad68, val | 0x0500);
1254 val = rge_read_phy_ocp(sc, 0xad68) & ~0x000f;
1255 rge_write_phy_ocp(sc, 0xad68, val | 0x0002);
1256 val = rge_read_phy_ocp(sc, 0xad6a) & ~0xf000;
1257 rge_write_phy_ocp(sc, 0xad6a, val | 0x7000);
1258 rge_write_phy_ocp(sc, 0xac50, 0x01e8);
1259 rge_write_phy_ocp(sc, 0xa436, 0x81fa);
1260 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1261 rge_write_phy_ocp(sc, 0xa438, val | 0x5400);
1262 val = rge_read_phy_ocp(sc, 0xa864) & ~0x00f0;
1263 rge_write_phy_ocp(sc, 0xa864, val | 0x00c0);
1264 val = rge_read_phy_ocp(sc, 0xa42c) & ~0x00ff;
1265 rge_write_phy_ocp(sc, 0xa42c, val | 0x0002);
1266 rge_write_phy_ocp(sc, 0xa436, 0x80e1);
1267 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1268 rge_write_phy_ocp(sc, 0xa438, val | 0x0f00);
1269 rge_write_phy_ocp(sc, 0xa436, 0x80de);
1270 val = rge_read_phy_ocp(sc, 0xa438) & ~0xf000;
1271 rge_write_phy_ocp(sc, 0xa438, val | 0x0700);
1272 RGE_PHY_SETBIT(sc, 0xa846, 0x0080);
1273 rge_write_phy_ocp(sc, 0xa436, 0x80ba);
1274 rge_write_phy_ocp(sc, 0xa438, 0x8a04);
1275 rge_write_phy_ocp(sc, 0xa436, 0x80bd);
1276 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1277 rge_write_phy_ocp(sc, 0xa438, val | 0xca00);
1278 rge_write_phy_ocp(sc, 0xa436, 0x80b7);
1279 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1280 rge_write_phy_ocp(sc, 0xa438, val | 0xb300);
1281 rge_write_phy_ocp(sc, 0xa436, 0x80ce);
1282 rge_write_phy_ocp(sc, 0xa438, 0x8a04);
1283 rge_write_phy_ocp(sc, 0xa436, 0x80d1);
1284 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1285 rge_write_phy_ocp(sc, 0xa438, val | 0xca00);
1286 rge_write_phy_ocp(sc, 0xa436, 0x80cb);
1287 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1288 rge_write_phy_ocp(sc, 0xa438, val | 0xbb00);
1289 rge_write_phy_ocp(sc, 0xa436, 0x80a6);
1290 rge_write_phy_ocp(sc, 0xa438, 0x4909);
1291 rge_write_phy_ocp(sc, 0xa436, 0x80a8);
1292 rge_write_phy_ocp(sc, 0xa438, 0x05b8);
1293 rge_write_phy_ocp(sc, 0xa436, 0x8200);
1294 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1295 rge_write_phy_ocp(sc, 0xa438, val | 0x5800);
1296 rge_write_phy_ocp(sc, 0xa436, 0x8ff1);
1297 rge_write_phy_ocp(sc, 0xa438, 0x7078);
1298 rge_write_phy_ocp(sc, 0xa436, 0x8ff3);
1299 rge_write_phy_ocp(sc, 0xa438, 0x5d78);
1300 rge_write_phy_ocp(sc, 0xa436, 0x8ff5);
1301 rge_write_phy_ocp(sc, 0xa438, 0x7862);
1302 rge_write_phy_ocp(sc, 0xa436, 0x8ff7);
1303 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1304 rge_write_phy_ocp(sc, 0xa438, val | 0x1400);
1305
1306 rge_write_phy_ocp(sc, 0xa436, 0x814c);
1307 rge_write_phy_ocp(sc, 0xa438, 0x8455);
1308 rge_write_phy_ocp(sc, 0xa436, 0x814e);
1309 rge_write_phy_ocp(sc, 0xa438, 0x84a6);
1310 rge_write_phy_ocp(sc, 0xa436, 0x8163);
1311 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1312 rge_write_phy_ocp(sc, 0xa438, val | 0x0600);
1313 rge_write_phy_ocp(sc, 0xa436, 0x816a);
1314 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1315 rge_write_phy_ocp(sc, 0xa438, val | 0x0500);
1316 rge_write_phy_ocp(sc, 0xa436, 0x8171);
1317 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1318 rge_write_phy_ocp(sc, 0xa438, val | 0x1f00);
1319
1320 val = rge_read_phy_ocp(sc, 0xbc3a) & ~0x000f;
1321 rge_write_phy_ocp(sc, 0xbc3a, val | 0x0006);
1322 for (i = 0; i < 10; i++) {
1323 rge_write_phy_ocp(sc, 0xa436, 0x8064 + i * 3);
1324 RGE_PHY_CLRBIT(sc, 0xa438, 0x0700);
1325 }
1326 val = rge_read_phy_ocp(sc, 0xbfa0) & ~0xff70;
1327 rge_write_phy_ocp(sc, 0xbfa0, val | 0x5500);
1328 rge_write_phy_ocp(sc, 0xbfa2, 0x9d00);
1329 rge_write_phy_ocp(sc, 0xa436, 0x8165);
1330 val = rge_read_phy_ocp(sc, 0xa438) & ~0x0700;
1331 rge_write_phy_ocp(sc, 0xa438, val | 0x0200);
1332
1333 rge_write_phy_ocp(sc, 0xa436, 0x8019);
1334 RGE_PHY_SETBIT(sc, 0xa438, 0x0100);
1335 rge_write_phy_ocp(sc, 0xa436, 0x8fe3);
1336 rge_write_phy_ocp(sc, 0xa438, 0x0005);
1337 rge_write_phy_ocp(sc, 0xa438, 0x0000);
1338 rge_write_phy_ocp(sc, 0xa438, 0x00ed);
1339 rge_write_phy_ocp(sc, 0xa438, 0x0502);
1340 rge_write_phy_ocp(sc, 0xa438, 0x0b00);
1341 rge_write_phy_ocp(sc, 0xa438, 0xd401);
1342 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1343 rge_write_phy_ocp(sc, 0xa438, val | 0x2900);
1344
1345 rge_write_phy_ocp(sc, 0xa436, 0x8018);
1346 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1347 rge_write_phy_ocp(sc, 0xa438, val | 0x1700);
1348
1349 rge_write_phy_ocp(sc, 0xa436, 0x815b);
1350 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1351 rge_write_phy_ocp(sc, 0xa438, val | 0x1700);
1352
1353 RGE_PHY_CLRBIT(sc, 0xa4e0, 0x8000);
1354 RGE_PHY_CLRBIT(sc, 0xa5d4, 0x0020);
1355 RGE_PHY_CLRBIT(sc, 0xa654, 0x0800);
1356 RGE_PHY_SETBIT(sc, 0xa430, 0x1001);
1357 RGE_PHY_SETBIT(sc, 0xa442, 0x0080);
1358 }
1359
1360 static void
rge_phy_config_mcu(struct rge_softc * sc,uint16_t rcodever)1361 rge_phy_config_mcu(struct rge_softc *sc, uint16_t rcodever)
1362 {
1363 if (sc->rge_rcodever != rcodever) {
1364 int i;
1365
1366 rge_patch_phy_mcu(sc, 1);
1367
1368 if (sc->rge_type == MAC_R25) {
1369 rge_write_phy_ocp(sc, 0xa436, 0x8024);
1370 rge_write_phy_ocp(sc, 0xa438, 0x8601);
1371 rge_write_phy_ocp(sc, 0xa436, 0xb82e);
1372 rge_write_phy_ocp(sc, 0xa438, 0x0001);
1373
1374 RGE_PHY_SETBIT(sc, 0xb820, 0x0080);
1375
1376 for (i = 0; i < nitems(mac_r25_mcu); i++)
1377 rge_write_phy_ocp(sc,
1378 mac_r25_mcu[i].reg, mac_r25_mcu[i].val);
1379
1380 RGE_PHY_CLRBIT(sc, 0xb820, 0x0080);
1381
1382 rge_write_phy_ocp(sc, 0xa436, 0);
1383 rge_write_phy_ocp(sc, 0xa438, 0);
1384 RGE_PHY_CLRBIT(sc, 0xb82e, 0x0001);
1385 rge_write_phy_ocp(sc, 0xa436, 0x8024);
1386 rge_write_phy_ocp(sc, 0xa438, 0);
1387 } else if (sc->rge_type == MAC_R25B) {
1388 for (i = 0; i < nitems(mac_r25b_mcu); i++)
1389 rge_write_phy_ocp(sc,
1390 mac_r25b_mcu[i].reg, mac_r25b_mcu[i].val);
1391 } else if (sc->rge_type == MAC_R25D) {
1392 for (i = 0; i < 2403; i++)
1393 rge_write_phy_ocp(sc,
1394 mac_r25d_mcu[i].reg, mac_r25d_mcu[i].val);
1395 rge_patch_phy_mcu(sc, 0);
1396
1397 rge_patch_phy_mcu(sc, 1);
1398 for (; i < 2528; i++)
1399 rge_write_phy_ocp(sc,
1400 mac_r25d_mcu[i].reg, mac_r25d_mcu[i].val);
1401 rge_patch_phy_mcu(sc, 0);
1402
1403 rge_patch_phy_mcu(sc, 1);
1404 for (; i < nitems(mac_r25d_mcu); i++)
1405 rge_write_phy_ocp(sc,
1406 mac_r25d_mcu[i].reg, mac_r25d_mcu[i].val);
1407 } else if (sc->rge_type == MAC_R26) {
1408 for (i = 0; i < nitems(mac_r26_mcu); i++)
1409 rge_write_phy_ocp(sc,
1410 mac_r26_mcu[i].reg, mac_r26_mcu[i].val);
1411 } else if (sc->rge_type == MAC_R27) {
1412 for (i = 0; i < 1887; i++)
1413 rge_write_phy_ocp(sc,
1414 mac_r27_mcu[i].reg, mac_r27_mcu[i].val);
1415 rge_patch_phy_mcu(sc, 0);
1416
1417 rge_patch_phy_mcu(sc, 1);
1418 for (; i < nitems(mac_r27_mcu); i++)
1419 rge_write_phy_ocp(sc,
1420 mac_r27_mcu[i].reg, mac_r27_mcu[i].val);
1421 }
1422
1423 rge_patch_phy_mcu(sc, 0);
1424
1425 /* Write ram code version. */
1426 rge_write_phy_ocp(sc, 0xa436, 0x801e);
1427 rge_write_phy_ocp(sc, 0xa438, rcodever);
1428 }
1429 }
1430
1431 void
rge_set_macaddr(struct rge_softc * sc,const uint8_t * addr)1432 rge_set_macaddr(struct rge_softc *sc, const uint8_t *addr)
1433 {
1434 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
1435 RGE_WRITE_4(sc, RGE_MAC0,
1436 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
1437 RGE_WRITE_4(sc, RGE_MAC4,
1438 addr[5] << 8 | addr[4]);
1439 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
1440 }
1441
1442 /**
1443 * @brief Read the mac address from the NIC EEPROM.
1444 *
1445 * Note this also calls rge_set_macaddr() which programs
1446 * it into the PPROM; I'm not sure why.
1447 *
1448 * Must be called with the driver lock held.
1449 */
1450 void
rge_get_macaddr(struct rge_softc * sc,uint8_t * addr)1451 rge_get_macaddr(struct rge_softc *sc, uint8_t *addr)
1452 {
1453 int i;
1454
1455 RGE_ASSERT_LOCKED(sc);
1456
1457 for (i = 0; i < ETHER_ADDR_LEN; i++)
1458 addr[i] = RGE_READ_1(sc, RGE_MAC0 + i);
1459
1460 *(uint32_t *)&addr[0] = RGE_READ_4(sc, RGE_ADDR0);
1461 *(uint16_t *)&addr[4] = RGE_READ_2(sc, RGE_ADDR1);
1462
1463 rge_set_macaddr(sc, addr);
1464 }
1465
1466 /**
1467 * @brief MAC hardware initialisation
1468 *
1469 * Must be called with the driver lock held.
1470 */
1471 static void
rge_hw_init(struct rge_softc * sc)1472 rge_hw_init(struct rge_softc *sc)
1473 {
1474 uint16_t reg;
1475 int i;
1476
1477 RGE_ASSERT_LOCKED(sc);
1478
1479 rge_disable_aspm_clkreq(sc);
1480 RGE_CLRBIT_1(sc, 0xf1, 0x80);
1481
1482 /* Disable UPS. */
1483 RGE_MAC_CLRBIT(sc, 0xd40a, 0x0010);
1484
1485 /* Disable MAC MCU. */
1486 rge_disable_aspm_clkreq(sc);
1487 rge_write_mac_ocp(sc, 0xfc48, 0);
1488 for (reg = 0xfc28; reg < 0xfc48; reg += 2)
1489 rge_write_mac_ocp(sc, reg, 0);
1490 DELAY(3000);
1491 rge_write_mac_ocp(sc, 0xfc26, 0);
1492
1493 /* Read microcode version. */
1494 rge_switch_mcu_ram_page(sc, 2);
1495 sc->rge_mcodever = 0;
1496 for (i = 0; i < 8; i += 2) {
1497 sc->rge_mcodever <<= 16;
1498 sc->rge_mcodever |= rge_read_mac_ocp(sc, 0xf9f8 + i);
1499 }
1500 rge_switch_mcu_ram_page(sc, 0);
1501
1502 rge_mac_config_mcu(sc, sc->rge_type);
1503
1504 /* Disable PHY power saving. */
1505 if (sc->rge_type == MAC_R25)
1506 rge_disable_phy_ocp_pwrsave(sc);
1507
1508 /* Set PCIe uncorrectable error status. */
1509 rge_write_csi(sc, 0x108,
1510 rge_read_csi(sc, 0x108) | 0x00100000);
1511 }
1512
1513 void
rge_hw_reset(struct rge_softc * sc)1514 rge_hw_reset(struct rge_softc *sc)
1515 {
1516 /* Disable interrupts */
1517 RGE_WRITE_4(sc, RGE_IMR, 0);
1518 RGE_WRITE_4(sc, RGE_ISR, RGE_READ_4(sc, RGE_ISR));
1519
1520 /* Clear timer interrupts. */
1521 RGE_WRITE_4(sc, RGE_TIMERINT0, 0);
1522 RGE_WRITE_4(sc, RGE_TIMERINT1, 0);
1523 RGE_WRITE_4(sc, RGE_TIMERINT2, 0);
1524 RGE_WRITE_4(sc, RGE_TIMERINT3, 0);
1525
1526 rge_reset(sc);
1527 }
1528
1529 static void
rge_disable_phy_ocp_pwrsave(struct rge_softc * sc)1530 rge_disable_phy_ocp_pwrsave(struct rge_softc *sc)
1531 {
1532 if (rge_read_phy_ocp(sc, 0xc416) != 0x0500) {
1533 rge_patch_phy_mcu(sc, 1);
1534 rge_write_phy_ocp(sc, 0xc416, 0);
1535 rge_write_phy_ocp(sc, 0xc416, 0x0500);
1536 rge_patch_phy_mcu(sc, 0);
1537 }
1538 }
1539
1540 static void
rge_patch_phy_mcu(struct rge_softc * sc,int set)1541 rge_patch_phy_mcu(struct rge_softc *sc, int set)
1542 {
1543 int i;
1544
1545 if (set)
1546 RGE_PHY_SETBIT(sc, 0xb820, 0x0010);
1547 else
1548 RGE_PHY_CLRBIT(sc, 0xb820, 0x0010);
1549
1550 for (i = 0; i < 1000; i++) {
1551 if (set) {
1552 if ((rge_read_phy_ocp(sc, 0xb800) & 0x0040) != 0)
1553 break;
1554 } else {
1555 if (!(rge_read_phy_ocp(sc, 0xb800) & 0x0040))
1556 break;
1557 }
1558 DELAY(100);
1559 }
1560 if (i == 1000)
1561 RGE_PRINT_ERROR(sc, "timeout waiting to patch phy mcu\n");
1562 }
1563
1564 void
rge_config_imtype(struct rge_softc * sc,int imtype)1565 rge_config_imtype(struct rge_softc *sc, int imtype)
1566 {
1567 switch (imtype) {
1568 case RGE_IMTYPE_NONE:
1569 sc->rge_intrs = RGE_INTRS;
1570 break;
1571 case RGE_IMTYPE_SIM:
1572 sc->rge_intrs = RGE_INTRS_TIMER;
1573 break;
1574 default:
1575 RGE_PRINT_ERROR(sc, "unknown imtype %d", imtype);
1576 }
1577 }
1578
1579 void
rge_disable_aspm_clkreq(struct rge_softc * sc)1580 rge_disable_aspm_clkreq(struct rge_softc *sc)
1581 {
1582 int unlock = 1;
1583
1584 if ((RGE_READ_1(sc, RGE_EECMD) & RGE_EECMD_WRITECFG) ==
1585 RGE_EECMD_WRITECFG)
1586 unlock = 0;
1587
1588 if (unlock)
1589 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
1590
1591 if (sc->rge_type == MAC_R26 || sc->rge_type == MAC_R27)
1592 RGE_CLRBIT_1(sc, RGE_INT_CFG0, 0x08);
1593 else
1594 RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN);
1595 RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS);
1596
1597 if (unlock)
1598 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
1599 }
1600
1601 static void
rge_disable_hw_im(struct rge_softc * sc)1602 rge_disable_hw_im(struct rge_softc *sc)
1603 {
1604 RGE_WRITE_2(sc, RGE_IM, 0);
1605 }
1606
1607 static void
rge_disable_sim_im(struct rge_softc * sc)1608 rge_disable_sim_im(struct rge_softc *sc)
1609 {
1610 RGE_WRITE_4(sc, RGE_TIMERINT0, 0);
1611 sc->rge_timerintr = 0;
1612 }
1613
1614 static void
rge_setup_sim_im(struct rge_softc * sc)1615 rge_setup_sim_im(struct rge_softc *sc)
1616 {
1617 RGE_WRITE_4(sc, RGE_TIMERINT0, 0x2600);
1618 RGE_WRITE_4(sc, RGE_TIMERCNT, 1);
1619 sc->rge_timerintr = 1;
1620 }
1621
1622 void
rge_setup_intr(struct rge_softc * sc,int imtype)1623 rge_setup_intr(struct rge_softc *sc, int imtype)
1624 {
1625 rge_config_imtype(sc, imtype);
1626
1627 /* Enable interrupts. */
1628 RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs);
1629
1630 switch (imtype) {
1631 case RGE_IMTYPE_NONE:
1632 rge_disable_sim_im(sc);
1633 rge_disable_hw_im(sc);
1634 break;
1635 case RGE_IMTYPE_SIM:
1636 rge_disable_hw_im(sc);
1637 rge_setup_sim_im(sc);
1638 break;
1639 default:
1640 RGE_PRINT_ERROR(sc, "unknown imtype %d", imtype);
1641 }
1642 }
1643
1644 static void
rge_switch_mcu_ram_page(struct rge_softc * sc,int page)1645 rge_switch_mcu_ram_page(struct rge_softc *sc, int page)
1646 {
1647 uint16_t val;
1648
1649 val = rge_read_mac_ocp(sc, 0xe446) & ~0x0003;
1650 val |= page;
1651 rge_write_mac_ocp(sc, 0xe446, val);
1652 }
1653
1654 static int
rge_exit_oob(struct rge_softc * sc)1655 rge_exit_oob(struct rge_softc *sc)
1656 {
1657 int error, i;
1658
1659 /* Disable RealWoW. */
1660 rge_write_mac_ocp(sc, 0xc0bc, 0x00ff);
1661
1662 if ((error = rge_reset(sc)) != 0)
1663 return error;
1664
1665 /* Disable OOB. */
1666 RGE_CLRBIT_1(sc, RGE_MCUCMD, RGE_MCUCMD_IS_OOB);
1667
1668 RGE_MAC_CLRBIT(sc, 0xe8de, 0x4000);
1669
1670 for (i = 0; i < 10; i++) {
1671 DELAY(100);
1672 if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200)
1673 break;
1674 }
1675
1676 rge_write_mac_ocp(sc, 0xc0aa, 0x07d0);
1677 rge_write_mac_ocp(sc, 0xc0a6, 0x01b5);
1678 rge_write_mac_ocp(sc, 0xc01e, 0x5555);
1679
1680 for (i = 0; i < 10; i++) {
1681 DELAY(100);
1682 if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200)
1683 break;
1684 }
1685
1686 if (rge_read_mac_ocp(sc, 0xd42c) & 0x0100) {
1687 for (i = 0; i < RGE_TIMEOUT; i++) {
1688 if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 2)
1689 break;
1690 DELAY(1000);
1691 }
1692 RGE_MAC_CLRBIT(sc, 0xd42c, 0x0100);
1693 if (sc->rge_type != MAC_R25)
1694 RGE_PHY_CLRBIT(sc, 0xa466, 0x0001);
1695 RGE_PHY_CLRBIT(sc, 0xa468, 0x000a);
1696 }
1697
1698 return 0;
1699 }
1700
1701 void
rge_write_csi(struct rge_softc * sc,uint32_t reg,uint32_t val)1702 rge_write_csi(struct rge_softc *sc, uint32_t reg, uint32_t val)
1703 {
1704 int i;
1705
1706 RGE_WRITE_4(sc, RGE_CSIDR, val);
1707 RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |
1708 (RGE_CSIAR_BYTE_EN << RGE_CSIAR_BYTE_EN_SHIFT) | RGE_CSIAR_BUSY);
1709
1710 for (i = 0; i < 20000; i++) {
1711 DELAY(1);
1712 if (!(RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY))
1713 break;
1714 }
1715
1716 DELAY(20);
1717 }
1718
1719 uint32_t
rge_read_csi(struct rge_softc * sc,uint32_t reg)1720 rge_read_csi(struct rge_softc *sc, uint32_t reg)
1721 {
1722 int i;
1723
1724 RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |
1725 (RGE_CSIAR_BYTE_EN << RGE_CSIAR_BYTE_EN_SHIFT));
1726
1727 for (i = 0; i < 20000; i++) {
1728 DELAY(1);
1729 if (RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY)
1730 break;
1731 }
1732
1733 DELAY(20);
1734
1735 return (RGE_READ_4(sc, RGE_CSIDR));
1736 }
1737
1738 void
rge_write_mac_ocp(struct rge_softc * sc,uint16_t reg,uint16_t val)1739 rge_write_mac_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)
1740 {
1741 uint32_t tmp;
1742
1743 tmp = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT;
1744 tmp += val;
1745 tmp |= RGE_MACOCP_BUSY;
1746 RGE_WRITE_4(sc, RGE_MACOCP, tmp);
1747 }
1748
1749 uint16_t
rge_read_mac_ocp(struct rge_softc * sc,uint16_t reg)1750 rge_read_mac_ocp(struct rge_softc *sc, uint16_t reg)
1751 {
1752 uint32_t val;
1753
1754 val = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT;
1755 RGE_WRITE_4(sc, RGE_MACOCP, val);
1756
1757 return (RGE_READ_4(sc, RGE_MACOCP) & RGE_MACOCP_DATA_MASK);
1758 }
1759
1760 static void
rge_write_ephy(struct rge_softc * sc,uint16_t reg,uint16_t val)1761 rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val)
1762 {
1763 uint32_t tmp;
1764 int i;
1765
1766 tmp = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT;
1767 tmp |= RGE_EPHYAR_BUSY | (val & RGE_EPHYAR_DATA_MASK);
1768 RGE_WRITE_4(sc, RGE_EPHYAR, tmp);
1769
1770 for (i = 0; i < 20000; i++) {
1771 DELAY(1);
1772 if (!(RGE_READ_4(sc, RGE_EPHYAR) & RGE_EPHYAR_BUSY))
1773 break;
1774 }
1775
1776 DELAY(20);
1777 }
1778
1779 static uint16_t
rge_read_ephy(struct rge_softc * sc,uint16_t reg)1780 rge_read_ephy(struct rge_softc *sc, uint16_t reg)
1781 {
1782 uint32_t val;
1783 int i;
1784
1785 val = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT;
1786 RGE_WRITE_4(sc, RGE_EPHYAR, val);
1787
1788 for (i = 0; i < 20000; i++) {
1789 DELAY(1);
1790 val = RGE_READ_4(sc, RGE_EPHYAR);
1791 if (val & RGE_EPHYAR_BUSY)
1792 break;
1793 }
1794
1795 DELAY(20);
1796
1797 return (val & RGE_EPHYAR_DATA_MASK);
1798 }
1799
1800 static uint16_t
rge_check_ephy_ext_add(struct rge_softc * sc,uint16_t reg)1801 rge_check_ephy_ext_add(struct rge_softc *sc, uint16_t reg)
1802 {
1803 uint16_t val;
1804
1805 val = (reg >> 12);
1806 rge_write_ephy(sc, RGE_EPHYAR_EXT_ADDR, val);
1807
1808 return reg & 0x0fff;
1809 }
1810
1811 static void
rge_r27_write_ephy(struct rge_softc * sc,uint16_t reg,uint16_t val)1812 rge_r27_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val)
1813 {
1814 rge_write_ephy(sc, rge_check_ephy_ext_add(sc, reg), val);
1815 }
1816
1817 void
rge_write_phy(struct rge_softc * sc,uint16_t addr,uint16_t reg,uint16_t val)1818 rge_write_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg, uint16_t val)
1819 {
1820 uint16_t off, phyaddr;
1821
1822 phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8);
1823 phyaddr <<= 4;
1824
1825 off = addr ? reg : 0x10 + (reg % 8);
1826
1827 phyaddr += (off - 16) << 1;
1828
1829 rge_write_phy_ocp(sc, phyaddr, val);
1830 }
1831
1832 uint16_t
rge_read_phy(struct rge_softc * sc,uint16_t addr,uint16_t reg)1833 rge_read_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg)
1834 {
1835 uint16_t off, phyaddr;
1836
1837 phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8);
1838 phyaddr <<= 4;
1839
1840 off = addr ? reg : 0x10 + (reg % 8);
1841
1842 phyaddr += (off - 16) << 1;
1843
1844 return (rge_read_phy_ocp(sc, phyaddr));
1845 }
1846
1847 void
rge_write_phy_ocp(struct rge_softc * sc,uint16_t reg,uint16_t val)1848 rge_write_phy_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)
1849 {
1850 uint32_t tmp;
1851 int i;
1852
1853 tmp = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT;
1854 tmp |= RGE_PHYOCP_BUSY | val;
1855 RGE_WRITE_4(sc, RGE_PHYOCP, tmp);
1856
1857 for (i = 0; i < 20000; i++) {
1858 DELAY(1);
1859 if (!(RGE_READ_4(sc, RGE_PHYOCP) & RGE_PHYOCP_BUSY))
1860 break;
1861 }
1862 }
1863
1864 uint16_t
rge_read_phy_ocp(struct rge_softc * sc,uint16_t reg)1865 rge_read_phy_ocp(struct rge_softc *sc, uint16_t reg)
1866 {
1867 uint32_t val;
1868 int i;
1869
1870 val = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT;
1871 RGE_WRITE_4(sc, RGE_PHYOCP, val);
1872
1873 for (i = 0; i < 20000; i++) {
1874 DELAY(1);
1875 val = RGE_READ_4(sc, RGE_PHYOCP);
1876 if (val & RGE_PHYOCP_BUSY)
1877 break;
1878 }
1879
1880 return (val & RGE_PHYOCP_DATA_MASK);
1881 }
1882
1883 int
rge_get_link_status(struct rge_softc * sc)1884 rge_get_link_status(struct rge_softc *sc)
1885 {
1886 return ((RGE_READ_2(sc, RGE_PHYSTAT) & RGE_PHYSTAT_LINK) ? 1 : 0);
1887 }
1888
1889 #if 0
1890 #ifndef SMALL_KERNEL
1891 int
1892 rge_wol(struct ifnet *ifp, int enable)
1893 {
1894 struct rge_softc *sc = ifp->if_softc;
1895
1896 if (enable) {
1897 if (!(RGE_READ_1(sc, RGE_CFG1) & RGE_CFG1_PM_EN)) {
1898 printf("%s: power management is disabled, "
1899 "cannot do WOL\n", sc->sc_dev.dv_xname);
1900 return (ENOTSUP);
1901 }
1902
1903 }
1904
1905 rge_iff(sc);
1906
1907 if (enable)
1908 RGE_MAC_SETBIT(sc, 0xc0b6, 0x0001);
1909 else
1910 RGE_MAC_CLRBIT(sc, 0xc0b6, 0x0001);
1911
1912 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
1913 RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE | RGE_CFG5_WOL_UCAST |
1914 RGE_CFG5_WOL_MCAST | RGE_CFG5_WOL_BCAST);
1915 RGE_CLRBIT_1(sc, RGE_CFG3, RGE_CFG3_WOL_LINK | RGE_CFG3_WOL_MAGIC);
1916 if (enable)
1917 RGE_SETBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE);
1918 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
1919
1920 return (0);
1921 }
1922
1923 void
1924 rge_wol_power(struct rge_softc *sc)
1925 {
1926 /* Disable RXDV gate. */
1927 RGE_CLRBIT_1(sc, RGE_PPSW, 0x08);
1928 DELAY(2000);
1929
1930 RGE_SETBIT_1(sc, RGE_CFG1, RGE_CFG1_PM_EN);
1931 RGE_SETBIT_1(sc, RGE_CFG2, RGE_CFG2_PMSTS_EN);
1932 }
1933 #endif
1934
1935 #endif
1936