1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 */
5
6 #ifndef _VNIC_WQ_H_
7 #define _VNIC_WQ_H_
8
9 #include "vnic_dev.h"
10 #include "vnic_cq.h"
11
12 /* Work queue control */
13 struct vnic_wq_ctrl {
14 u64 ring_base; /* 0x00 */
15 #define TX_RING_BASE 0x00
16 u32 ring_size; /* 0x08 */
17 #define TX_RING_SIZE 0x08
18 u32 pad0;
19 u32 posted_index; /* 0x10 */
20 #define TX_POSTED_INDEX 0x10
21 u32 pad1;
22 u32 cq_index; /* 0x18 */
23 #define TX_CQ_INDEX 0x18
24 u32 pad2;
25 u32 enable; /* 0x20 */
26 #define TX_ENABLE 0x20
27 u32 pad3;
28 u32 running; /* 0x28 */
29 #define TX_RUNNING 0x28
30 u32 pad4;
31 u32 fetch_index; /* 0x30 */
32 #define TX_FETCH_INDEX 0x30
33 u32 pad5;
34 u32 dca_value; /* 0x38 */
35 #define TX_DCA_VALUE 0x38
36 u32 pad6;
37 u32 error_interrupt_enable; /* 0x40 */
38 #define TX_ERROR_INTR_ENABLE 0x40
39 u32 pad7;
40 u32 error_interrupt_offset; /* 0x48 */
41 #define TX_ERROR_INTR_OFFSET 0x48
42 u32 pad8;
43 u32 error_status; /* 0x50 */
44 #define TX_ERROR_STATUS 0x50
45 u32 pad9;
46 };
47
48 struct vnic_wq {
49 unsigned int index;
50 uint64_t tx_offload_notsup_mask;
51 struct vnic_dev *vdev;
52 struct vnic_res *ctrl;
53 struct vnic_dev_ring ring;
54 unsigned int head_idx;
55 unsigned int cq_pend;
56 unsigned int tail_idx;
57 unsigned int socket_id;
58 unsigned int processed;
59 const struct rte_memzone *cqmsg_rz;
60 uint16_t last_completed_index;
61 uint64_t offloads;
62 };
63
64 struct devcmd2_controller {
65 struct vnic_res *wq_ctrl;
66 struct vnic_devcmd2 *cmd_ring;
67 struct devcmd2_result *result;
68 u16 next_result;
69 u16 result_size;
70 int color;
71 struct vnic_dev_ring results_ring;
72 struct vnic_res *results_ctrl;
73 struct vnic_wq wq;
74 u32 posted;
75 };
76
77
vnic_wq_desc_avail(struct vnic_wq * wq)78 static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)
79 {
80 /* how many does SW own? */
81 return wq->ring.desc_avail;
82 }
83
vnic_wq_desc_used(struct vnic_wq * wq)84 static inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)
85 {
86 /* how many does HW own? */
87 return wq->ring.desc_count - wq->ring.desc_avail - 1;
88 }
89
90 #define PI_LOG2_CACHE_LINE_SIZE 5
91 #define PI_INDEX_BITS 12
92 #define PI_INDEX_MASK ((1U << PI_INDEX_BITS) - 1)
93 #define PI_PREFETCH_LEN_MASK ((1U << PI_LOG2_CACHE_LINE_SIZE) - 1)
94 #define PI_PREFETCH_LEN_OFF 16
95 #define PI_PREFETCH_ADDR_BITS 43
96 #define PI_PREFETCH_ADDR_MASK ((1ULL << PI_PREFETCH_ADDR_BITS) - 1)
97 #define PI_PREFETCH_ADDR_OFF 21
98
99 static inline uint32_t
buf_idx_incr(uint32_t n_descriptors,uint32_t idx)100 buf_idx_incr(uint32_t n_descriptors, uint32_t idx)
101 {
102 idx++;
103 if (unlikely(idx == n_descriptors))
104 idx = 0;
105 return idx;
106 }
107
108 void vnic_wq_free(struct vnic_wq *wq);
109 void enic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,
110 unsigned int fetch_index, unsigned int posted_index,
111 unsigned int error_interrupt_enable,
112 unsigned int error_interrupt_offset);
113 void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
114 unsigned int error_interrupt_enable,
115 unsigned int error_interrupt_offset);
116 void vnic_wq_error_out(struct vnic_wq *wq, unsigned int error);
117 unsigned int vnic_wq_error_status(struct vnic_wq *wq);
118 void vnic_wq_enable(struct vnic_wq *wq);
119 int vnic_wq_disable(struct vnic_wq *wq);
120 void vnic_wq_clean(struct vnic_wq *wq);
121 int enic_wq_devcmd2_alloc(struct vnic_dev *vdev, struct vnic_wq *wq,
122 unsigned int desc_count, unsigned int desc_size);
123
124 #endif /* _VNIC_WQ_H_ */
125