1 /*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of Cavium, Inc. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * \brief Host Driver: This file defines the octeon device structure.
36 */
37
38 #ifndef _LIO_DEVICE_H_
39 #define _LIO_DEVICE_H_
40
41 #include <sys/endian.h> /* for BYTE_ORDER */
42
43 /* PCI VendorId Device Id */
44 #define LIO_CN23XX_PF_PCIID 0x9702177d
45 /*
46 * Driver identifies chips by these Ids, created by clubbing together
47 * DeviceId+RevisionId; Where Revision Id is not used to distinguish
48 * between chips, a value of 0 is used for revision id.
49 */
50 #define LIO_CN23XX_PF_VID 0x9702
51 #define LIO_CN2350_10G_SUBDEVICE 0x03
52 #define LIO_CN2350_10G_SUBDEVICE1 0x04
53 #define LIO_CN2360_10G_SUBDEVICE 0x05
54 #define LIO_CN2350_25G_SUBDEVICE 0x07
55 #define LIO_CN2360_25G_SUBDEVICE 0x06
56
57
58 /* Endian-swap modes supported by Octeon. */
59 enum lio_pci_swap_mode {
60 LIO_PCI_PASSTHROUGH = 0,
61 LIO_PCI_SWAP_64BIT = 1,
62 LIO_PCI_SWAP_32BIT = 2,
63 LIO_PCI_LW_SWAP_32BIT = 3
64 };
65
66 enum {
67 LIO_CFG_TYPE_DEFAULT = 0,
68 LIO_NUM_CFGS,
69 };
70
71 #define OCTEON_OUTPUT_INTR (2)
72 #define OCTEON_ALL_INTR 0xff
73
74 /*--------------- PCI BAR1 index registers -------------*/
75
76 /* BAR1 Mask */
77 #define LIO_PCI_BAR1_ENABLE_CA 1
78 #define LIO_PCI_BAR1_ENDIAN_MODE LIO_PCI_SWAP_64BIT
79 #define LIO_PCI_BAR1_ENTRY_VALID 1
80 #define LIO_PCI_BAR1_MASK ((LIO_PCI_BAR1_ENABLE_CA << 3) | \
81 (LIO_PCI_BAR1_ENDIAN_MODE << 1) | \
82 LIO_PCI_BAR1_ENTRY_VALID)
83
84 /*
85 * Octeon Device state.
86 * Each octeon device goes through each of these states
87 * as it is initialized.
88 */
89 #define LIO_DEV_BEGIN_STATE 0x0
90 #define LIO_DEV_PCI_ENABLE_DONE 0x1
91 #define LIO_DEV_PCI_MAP_DONE 0x2
92 #define LIO_DEV_DISPATCH_INIT_DONE 0x3
93 #define LIO_DEV_INSTR_QUEUE_INIT_DONE 0x4
94 #define LIO_DEV_SC_BUFF_POOL_INIT_DONE 0x5
95 #define LIO_DEV_MSIX_ALLOC_VECTOR_DONE 0x6
96 #define LIO_DEV_RESP_LIST_INIT_DONE 0x7
97 #define LIO_DEV_DROQ_INIT_DONE 0x8
98 #define LIO_DEV_INTR_SET_DONE 0xa
99 #define LIO_DEV_IO_QUEUES_DONE 0xb
100 #define LIO_DEV_CONSOLE_INIT_DONE 0xc
101 #define LIO_DEV_HOST_OK 0xd
102 #define LIO_DEV_CORE_OK 0xe
103 #define LIO_DEV_RUNNING 0xf
104 #define LIO_DEV_IN_RESET 0x10
105 #define LIO_DEV_STATE_INVALID 0x11
106
107 #define LIO_DEV_STATES LIO_DEV_STATE_INVALID
108
109 /*
110 * Octeon Device interrupts
111 * These interrupt bits are set in int_status filed of
112 * octeon_device structure
113 */
114 #define LIO_DEV_INTR_DMA0_FORCE 0x01
115 #define LIO_DEV_INTR_DMA1_FORCE 0x02
116 #define LIO_DEV_INTR_PKT_DATA 0x04
117
118 #define LIO_RESET_MSECS (3000)
119
120 /*---------------------------DISPATCH LIST-------------------------------*/
121
122 /*
123 * The dispatch list entry.
124 * The driver keeps a record of functions registered for each
125 * response header opcode in this structure. Since the opcode is
126 * hashed to index into the driver's list, more than one opcode
127 * can hash to the same entry, in which case the list field points
128 * to a linked list with the other entries.
129 */
130 struct lio_dispatch {
131 /* Singly-linked tail queue node for this entry */
132 struct lio_stailq_node node;
133
134 /* Singly-linked tail queue head for this entry */
135 struct lio_stailq_head head;
136
137 /* The opcode for which the dispatch function & arg should be used */
138 uint16_t opcode;
139
140 /* The function to be called for a packet received by the driver */
141 lio_dispatch_fn_t dispatch_fn;
142
143 /*
144 * The application specified argument to be passed to the above
145 * function along with the received packet
146 */
147 void *arg;
148 };
149
150 /* The dispatch list structure. */
151 struct lio_dispatch_list {
152 /* access to dispatch list must be atomic */
153 struct mtx lock;
154
155 /* Count of dispatch functions currently registered */
156 uint32_t count;
157
158 /* The list of dispatch functions */
159 struct lio_dispatch *dlist;
160 };
161
162 /*----------------------- THE OCTEON DEVICE ---------------------------*/
163
164 #define LIO_MEM_REGIONS 3
165 /*
166 * PCI address space information.
167 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of
168 * Octeon gets mapped to different physical address spaces in
169 * the kernel.
170 */
171 struct lio_mem_bus_space {
172 struct resource *pci_mem;
173 bus_space_tag_t tag;
174 bus_space_handle_t handle;
175 };
176
177 #define LIO_MAX_MAPS 32
178
179 struct lio_io_enable {
180 uint64_t iq;
181 uint64_t oq;
182 uint64_t iq64B;
183 };
184
185 struct lio_reg_list {
186 uint32_t pci_win_wr_addr;
187
188 uint32_t pci_win_rd_addr_hi;
189 uint32_t pci_win_rd_addr_lo;
190 uint32_t pci_win_rd_addr;
191
192 uint32_t pci_win_wr_data_hi;
193 uint32_t pci_win_wr_data_lo;
194 uint32_t pci_win_wr_data;
195
196 uint32_t pci_win_rd_data;
197 };
198
199 #define LIO_MAX_CONSOLE_READ_BYTES 512
200
201 typedef int (*octeon_console_print_fn)(struct octeon_device *oct,
202 uint32_t num, char *pre, char *suf);
203 struct lio_console {
204 uint32_t active;
205 uint32_t waiting;
206 uint64_t addr;
207 uint32_t buffer_size;
208 uint64_t input_base_addr;
209 uint64_t output_base_addr;
210 octeon_console_print_fn print;
211 char leftover[LIO_MAX_CONSOLE_READ_BYTES];
212 };
213
214 struct lio_board_info {
215 char name[LIO_BOARD_NAME];
216 char serial_number[LIO_SERIAL_NUM_LEN];
217 uint64_t major;
218 uint64_t minor;
219 };
220
221 struct lio_fn_list {
222 void (*setup_iq_regs) (struct octeon_device *, uint32_t);
223 void (*setup_oq_regs) (struct octeon_device *, uint32_t);
224
225 void (*process_interrupt_regs) (void *);
226 uint64_t (*msix_interrupt_handler) (void *);
227 int (*soft_reset) (struct octeon_device *);
228 int (*setup_device_regs) (struct octeon_device *);
229 void (*bar1_idx_setup) (struct octeon_device *, uint64_t,
230 uint32_t, int);
231 void (*bar1_idx_write) (struct octeon_device *, uint32_t,
232 uint32_t);
233 uint32_t (*bar1_idx_read) (struct octeon_device *, uint32_t);
234 uint32_t (*update_iq_read_idx) (struct lio_instr_queue *);
235
236 void (*enable_interrupt) (struct octeon_device *, uint8_t);
237 void (*disable_interrupt) (struct octeon_device *, uint8_t);
238
239 int (*enable_io_queues) (struct octeon_device *);
240 void (*disable_io_queues) (struct octeon_device *);
241 };
242
243 /* Must be multiple of 8, changing breaks ABI */
244 #define LIO_BOOTMEM_NAME_LEN 128
245
246 /*
247 * Structure for named memory blocks
248 * Number of descriptors
249 * available can be changed without affecting compatibility,
250 * but name length changes require a bump in the bootmem
251 * descriptor version
252 * Note: This structure must be naturally 64 bit aligned, as a single
253 * memory image will be used by both 32 and 64 bit programs.
254 */
255 struct cvmx_bootmem_named_block_desc {
256 /* Base address of named block */
257 uint64_t base_addr;
258
259 /* Size actually allocated for named block */
260 uint64_t size;
261
262 /* name of named block */
263 char name[LIO_BOOTMEM_NAME_LEN];
264 };
265
266 struct lio_fw_info {
267 uint32_t max_nic_ports; /* max nic ports for the device */
268 uint32_t num_gmx_ports; /* num gmx ports */
269 uint64_t app_cap_flags; /* firmware cap flags */
270
271 /*
272 * The core application is running in this mode.
273 * See octeon-drv-opcodes.h for values.
274 */
275 uint32_t app_mode;
276 char lio_firmware_version[32];
277 };
278
279 struct lio_callout {
280 struct callout timer;
281 void *ctxptr;
282 uint64_t ctxul;
283 };
284
285 #define LIO_NIC_STARTER_TIMEOUT 30000 /* 30000ms (30s) */
286
287 struct lio_tq {
288 struct taskqueue *tq;
289 struct timeout_task work;
290 void *ctxptr;
291 uint64_t ctxul;
292 };
293
294 struct lio_if_props {
295 /*
296 * Each interface in the Octeon device has a network
297 * device pointer (used for OS specific calls).
298 */
299 int rx_on;
300 int gmxport;
301 struct ifnet *ifp;
302 };
303
304 #define LIO_MSIX_PO_INT 0x1
305 #define LIO_MSIX_PI_INT 0x2
306
307 struct lio_pf_vf_hs_word {
308 #if BYTE_ORDER == LITTLE_ENDIAN
309 /* PKIND value assigned for the DPI interface */
310 uint64_t pkind:8;
311
312 /* OCTEON core clock multiplier */
313 uint64_t core_tics_per_us:16;
314
315 /* OCTEON coprocessor clock multiplier */
316 uint64_t coproc_tics_per_us:16;
317
318 /* app that currently running on OCTEON */
319 uint64_t app_mode:8;
320
321 /* RESERVED */
322 uint64_t reserved:16;
323
324 #else /* BYTE_ORDER != LITTLE_ENDIAN */
325
326 /* RESERVED */
327 uint64_t reserved:16;
328
329 /* app that currently running on OCTEON */
330 uint64_t app_mode:8;
331
332 /* OCTEON coprocessor clock multiplier */
333 uint64_t coproc_tics_per_us:16;
334
335 /* OCTEON core clock multiplier */
336 uint64_t core_tics_per_us:16;
337
338 /* PKIND value assigned for the DPI interface */
339 uint64_t pkind:8;
340 #endif /* BYTE_ORDER == LITTLE_ENDIAN */
341 };
342
343 struct lio_sriov_info {
344
345 /* Actual rings left for PF device */
346 uint32_t num_pf_rings;
347
348 /* SRN of PF usable IO queues */
349 uint32_t pf_srn;
350
351 /* total pf rings */
352 uint32_t trs;
353 };
354
355 struct lio_ioq_vector {
356 struct octeon_device *oct_dev;
357 struct resource *msix_res;
358 void *tag;
359 int droq_index;
360 int vector;
361 cpuset_t affinity_mask;
362 uint32_t ioq_num;
363 };
364
365 /*
366 * The Octeon device.
367 * Each Octeon device has this structure to represent all its
368 * components.
369 */
370 struct octeon_device {
371 /* Lock for PCI window configuration accesses */
372 struct mtx pci_win_lock;
373
374 /* Lock for memory accesses */
375 struct mtx mem_access_lock;
376
377 /* PCI device pointer */
378 device_t device;
379
380 /* Chip specific information. */
381 void *chip;
382
383 /* Number of interfaces detected in this octeon device. */
384 uint32_t ifcount;
385
386 struct lio_if_props props;
387
388 /* Octeon Chip type. */
389 uint16_t chip_id;
390
391 uint16_t rev_id;
392
393 uint16_t subdevice_id;
394
395 uint16_t pf_num;
396
397
398 /* This device's id - set by the driver. */
399 uint32_t octeon_id;
400
401 /* This device's PCIe port used for traffic. */
402 uint16_t pcie_port;
403
404 uint16_t flags;
405 #define LIO_FLAG_MSIX_ENABLED (uint32_t)(1 << 2)
406
407 /* The state of this device */
408 volatile int status;
409
410 /* memory mapped io range */
411 struct lio_mem_bus_space mem_bus_space[LIO_MEM_REGIONS];
412
413 struct lio_reg_list reg_list;
414
415 struct lio_fn_list fn_list;
416
417 struct lio_board_info boardinfo;
418
419 uint32_t num_iqs;
420
421 /* The pool containing pre allocated buffers used for soft commands */
422 struct lio_sc_buffer_pool sc_buf_pool;
423
424 /* The input instruction queues */
425 struct lio_instr_queue *instr_queue[LIO_MAX_POSSIBLE_INSTR_QUEUES];
426
427 /* The doubly-linked list of instruction response */
428 struct lio_response_list response_list[LIO_MAX_RESPONSE_LISTS];
429
430 uint32_t num_oqs;
431
432 /* The DROQ output queues */
433 struct lio_droq *droq[LIO_MAX_POSSIBLE_OUTPUT_QUEUES];
434
435 struct lio_io_enable io_qmask;
436
437 /* List of dispatch functions */
438 struct lio_dispatch_list dispatch;
439
440 uint32_t int_status;
441
442 /* Physical location of the cvmx_bootmem_desc_t in octeon memory */
443 uint64_t bootmem_desc_addr;
444
445 /*
446 * Placeholder memory for named blocks.
447 * Assumes single-threaded access
448 */
449 struct cvmx_bootmem_named_block_desc bootmem_named_block_desc;
450
451 /* Address of consoles descriptor */
452 uint64_t console_desc_addr;
453
454 /* Number of consoles available. 0 means they are inaccessible */
455 uint32_t num_consoles;
456
457 /* Console caches */
458 struct lio_console console[LIO_MAX_MAPS];
459
460 /* Console named block info */
461 struct {
462 uint64_t dram_region_base;
463 int bar1_index;
464 } console_nb_info;
465
466 /* Coprocessor clock rate. */
467 uint64_t coproc_clock_rate;
468
469 /*
470 * The core application is running in this mode. See lio_common.h
471 * for values.
472 */
473 uint32_t app_mode;
474
475 struct lio_fw_info fw_info;
476
477 /* The name given to this device. */
478 char device_name[32];
479
480 struct lio_tq dma_comp_tq;
481
482 /* Lock for dma response list */
483 struct mtx cmd_resp_wqlock;
484 uint32_t cmd_resp_state;
485
486 struct lio_tq check_db_tq[LIO_MAX_POSSIBLE_INSTR_QUEUES];
487
488 struct lio_callout console_timer[LIO_MAX_MAPS];
489
490 int num_msix_irqs;
491
492 /* For PF, there is one non-ioq interrupt handler */
493 struct resource *msix_res;
494 int aux_vector;
495 void *tag;
496
497 #define INTRNAMSIZ (32)
498 #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ)
499
500 struct lio_sriov_info sriov_info;
501
502 struct lio_pf_vf_hs_word pfvf_hsword;
503
504 int msix_on;
505
506 /* IOq information of it's corresponding MSI-X interrupt. */
507 struct lio_ioq_vector *ioq_vector;
508
509 int rx_pause;
510 int tx_pause;
511
512 /* TX/RX process pkt budget */
513 uint32_t rx_budget;
514 uint32_t tx_budget;
515
516 struct octeon_link_stats link_stats; /* stastics from firmware */
517
518 struct proc *watchdog_task;
519
520 volatile bool cores_crashed;
521
522 uint32_t rx_coalesce_usecs;
523 uint32_t rx_max_coalesced_frames;
524 uint32_t tx_max_coalesced_frames;
525
526 #define OCTEON_UBOOT_BUFFER_SIZE 512
527 char uboot_version[OCTEON_UBOOT_BUFFER_SIZE];
528 int uboot_len;
529 int uboot_sidx, uboot_eidx;
530
531 struct {
532 int bus;
533 int dev;
534 int func;
535 } loc;
536
537 volatile int *adapter_refcount; /* reference count of adapter */
538 };
539
540 #define LIO_DRV_ONLINE 1
541 #define LIO_DRV_OFFLINE 2
542 #define LIO_CN23XX_PF(oct) ((oct)->chip_id == LIO_CN23XX_PF_VID)
543 #define LIO_CHIP_CONF(oct, TYPE) \
544 (((struct lio_ ## TYPE *)((oct)->chip))->conf)
545 #define MAX_IO_PENDING_PKT_COUNT 100
546
547 /*------------------ Function Prototypes ----------------------*/
548
549 /* Initialize device list memory */
550 void lio_init_device_list(int conf_type);
551
552 /* Free memory for Input and Output queue structures for a octeon device */
553 void lio_free_device_mem(struct octeon_device *oct);
554
555 /*
556 * Look up a free entry in the octeon_device table and allocate resources
557 * for the octeon_device structure for an octeon device. Called at init
558 * time.
559 */
560 struct octeon_device *lio_allocate_device(device_t device);
561
562 /*
563 * Register a device's bus location at initialization time.
564 * @param oct - pointer to the octeon device structure.
565 * @param bus - PCIe bus #
566 * @param dev - PCIe device #
567 * @param func - PCIe function #
568 * @param is_pf - TRUE for PF, FALSE for VF
569 * @return reference count of device's adapter
570 */
571 int lio_register_device(struct octeon_device *oct, int bus, int dev,
572 int func, int is_pf);
573
574 /*
575 * Deregister a device at de-initialization time.
576 * @param oct - pointer to the octeon device structure.
577 * @return reference count of device's adapter
578 */
579 int lio_deregister_device(struct octeon_device *oct);
580
581 /*
582 * Initialize the driver's dispatch list which is a mix of a hash table
583 * and a linked list. This is done at driver load time.
584 * @param octeon_dev - pointer to the octeon device structure.
585 * @return 0 on success, else -ve error value
586 */
587 int lio_init_dispatch_list(struct octeon_device *octeon_dev);
588
589 /*
590 * Delete the driver's dispatch list and all registered entries.
591 * This is done at driver unload time.
592 * @param octeon_dev - pointer to the octeon device structure.
593 */
594 void lio_delete_dispatch_list(struct octeon_device *octeon_dev);
595
596 /*
597 * Initialize the core device fields with the info returned by the FW.
598 * @param recv_info - Receive info structure
599 * @param buf - Receive buffer
600 */
601 int lio_core_drv_init(struct lio_recv_info *recv_info, void *buf);
602
603 /*
604 * Gets the dispatch function registered to receive packets with a
605 * given opcode/subcode.
606 * @param octeon_dev - the octeon device pointer.
607 * @param opcode - the opcode for which the dispatch function
608 * is to checked.
609 * @param subcode - the subcode for which the dispatch function
610 * is to checked.
611 *
612 * @return Success: lio_dispatch_fn_t (dispatch function pointer)
613 * @return Failure: NULL
614 *
615 * Looks up the dispatch list to get the dispatch function for a
616 * given opcode.
617 */
618 lio_dispatch_fn_t lio_get_dispatch(struct octeon_device *octeon_dev,
619 uint16_t opcode, uint16_t subcode);
620
621 /*
622 * Get the octeon device pointer.
623 * @param octeon_id - The id for which the octeon device pointer is required.
624 * @return Success: Octeon device pointer.
625 * @return Failure: NULL.
626 */
627 struct octeon_device *lio_get_device(uint32_t octeon_id);
628
629 /*
630 * Get the octeon id assigned to the octeon device passed as argument.
631 * This function is exported to other modules.
632 * @param dev - octeon device pointer passed as a void *.
633 * @return octeon device id
634 */
635 int lio_get_device_id(void *dev);
636
637 static inline uint16_t
OCTEON_MAJOR_REV(struct octeon_device * oct)638 OCTEON_MAJOR_REV(struct octeon_device *oct)
639 {
640
641 uint16_t rev = (oct->rev_id & 0xC) >> 2;
642
643 return ((rev == 0) ? 1 : rev);
644 }
645
646 static inline uint16_t
OCTEON_MINOR_REV(struct octeon_device * oct)647 OCTEON_MINOR_REV(struct octeon_device *oct)
648 {
649
650 return (oct->rev_id & 0x3);
651 }
652
653 /*
654 * Read windowed register.
655 * @param oct - pointer to the Octeon device.
656 * @param addr - Address of the register to read.
657 *
658 * This routine is called to read from the indirectly accessed
659 * Octeon registers that are visible through a PCI BAR0 mapped window
660 * register.
661 * @return - 64 bit value read from the register.
662 */
663
664 uint64_t lio_pci_readq(struct octeon_device *oct, uint64_t addr);
665
666 /*
667 * Write windowed register.
668 * @param oct - pointer to the Octeon device.
669 * @param val - Value to write
670 * @param addr - Address of the register to write
671 *
672 * This routine is called to write to the indirectly accessed
673 * Octeon registers that are visible through a PCI BAR0 mapped window
674 * register.
675 * @return Nothing.
676 */
677 void lio_pci_writeq(struct octeon_device *oct, uint64_t val, uint64_t addr);
678
679 /*
680 * Checks if memory access is okay
681 *
682 * @param oct which octeon to send to
683 * @return Zero on success, negative on failure.
684 */
685 int lio_mem_access_ok(struct octeon_device *oct);
686
687 /*
688 * Waits for DDR initialization.
689 *
690 * @param oct which octeon to send to
691 * @param timeout_in_ms pointer to how long to wait until DDR is initialized
692 * in ms.
693 * If contents are 0, it waits until contents are non-zero
694 * before starting to check.
695 * @return Zero on success, negative on failure.
696 */
697 int lio_wait_for_ddr_init(struct octeon_device *oct,
698 unsigned long *timeout_in_ms);
699
700 /*
701 * Wait for u-boot to boot and be waiting for a command.
702 *
703 * @param wait_time_hundredths
704 * Maximum time to wait
705 *
706 * @return Zero on success, negative on failure.
707 */
708 int lio_wait_for_bootloader(struct octeon_device *oct,
709 uint32_t wait_time_hundredths);
710
711 /*
712 * Initialize console access
713 *
714 * @param oct which octeon initialize
715 * @return Zero on success, negative on failure.
716 */
717 int lio_init_consoles(struct octeon_device *oct);
718
719 /*
720 * Adds access to a console to the device.
721 *
722 * @param oct: which octeon to add to
723 * @param console_num: which console
724 * @param dbg_enb: ptr to debug enablement string, one of:
725 * * NULL for no debug output (i.e. disabled)
726 * * empty string enables debug output (via default method)
727 * * specific string to enable debug console output
728 *
729 * @return Zero on success, negative on failure.
730 */
731 int lio_add_console(struct octeon_device *oct, uint32_t console_num,
732 char *dbg_enb);
733
734 /* write or read from a console */
735 int lio_console_write(struct octeon_device *oct, uint32_t console_num,
736 char *buffer, uint32_t write_request_size,
737 uint32_t flags);
738
739 /* Removes all attached consoles. */
740 void lio_remove_consoles(struct octeon_device *oct);
741
742 /*
743 * Send a string to u-boot on console 0 as a command.
744 *
745 * @param oct which octeon to send to
746 * @param cmd_str String to send
747 * @param wait_hundredths Time to wait for u-boot to accept the command.
748 *
749 * @return Zero on success, negative on failure.
750 */
751 int lio_console_send_cmd(struct octeon_device *oct, char *cmd_str,
752 uint32_t wait_hundredths);
753
754 /*
755 * Parses, validates, and downloads firmware, then boots associated cores.
756 * @param oct which octeon to download firmware to
757 * @param data - The complete firmware file image
758 * @param size - The size of the data
759 *
760 * @return 0 if success.
761 * -EINVAL if file is incompatible or badly formatted.
762 * -ENODEV if no handler was found for the application type or an
763 * invalid octeon id was passed.
764 */
765 int lio_download_firmware(struct octeon_device *oct, const uint8_t *data,
766 size_t size);
767
768 char *lio_get_state_string(volatile int *state_ptr);
769
770 /*
771 * Sets up instruction queues for the device
772 * @param oct which octeon to setup
773 *
774 * @return 0 if success. 1 if fails
775 */
776 int lio_setup_instr_queue0(struct octeon_device *oct);
777
778 /*
779 * Sets up output queues for the device
780 * @param oct which octeon to setup
781 *
782 * @return 0 if success. 1 if fails
783 */
784 int lio_setup_output_queue0(struct octeon_device *oct);
785
786 int lio_get_tx_qsize(struct octeon_device *oct, uint32_t q_no);
787
788 int lio_get_rx_qsize(struct octeon_device *oct, uint32_t q_no);
789
790 /*
791 * Retrieve the config for the device
792 * @param oct which octeon
793 * @param card_type type of card
794 *
795 * @returns pointer to configuration
796 */
797 void *lio_get_config_info(struct octeon_device *oct, uint16_t card_type);
798
799 /*
800 * Gets the octeon device configuration
801 * @return - pointer to the octeon configuration structure
802 */
803 struct lio_config *lio_get_conf(struct octeon_device *oct);
804
805 void lio_free_ioq_vector(struct octeon_device *oct);
806 int lio_allocate_ioq_vector(struct octeon_device *oct);
807 void lio_enable_irq(struct lio_droq *droq, struct lio_instr_queue *iq);
808
809 static inline uint32_t
lio_read_pci_cfg(struct octeon_device * oct,uint32_t reg)810 lio_read_pci_cfg(struct octeon_device *oct, uint32_t reg)
811 {
812
813 return (pci_read_config(oct->device, reg, 4));
814 }
815
816 static inline void
lio_write_pci_cfg(struct octeon_device * oct,uint32_t reg,uint32_t value)817 lio_write_pci_cfg(struct octeon_device *oct, uint32_t reg, uint32_t value)
818 {
819
820 pci_write_config(oct->device, reg, value, 4);
821 }
822
823 static inline uint8_t
lio_read_csr8(struct octeon_device * oct,uint32_t reg)824 lio_read_csr8(struct octeon_device *oct, uint32_t reg)
825 {
826
827 return (bus_space_read_1(oct->mem_bus_space[0].tag,
828 oct->mem_bus_space[0].handle, reg));
829 }
830
831 static inline void
lio_write_csr8(struct octeon_device * oct,uint32_t reg,uint8_t val)832 lio_write_csr8(struct octeon_device *oct, uint32_t reg, uint8_t val)
833 {
834
835 bus_space_write_1(oct->mem_bus_space[0].tag,
836 oct->mem_bus_space[0].handle, reg, val);
837 }
838
839 static inline uint16_t
lio_read_csr16(struct octeon_device * oct,uint32_t reg)840 lio_read_csr16(struct octeon_device *oct, uint32_t reg)
841 {
842
843 return (bus_space_read_2(oct->mem_bus_space[0].tag,
844 oct->mem_bus_space[0].handle, reg));
845 }
846
847 static inline void
lio_write_csr16(struct octeon_device * oct,uint32_t reg,uint16_t val)848 lio_write_csr16(struct octeon_device *oct, uint32_t reg, uint16_t val)
849 {
850
851 bus_space_write_2(oct->mem_bus_space[0].tag,
852 oct->mem_bus_space[0].handle, reg, val);
853 }
854
855 static inline uint32_t
lio_read_csr32(struct octeon_device * oct,uint32_t reg)856 lio_read_csr32(struct octeon_device *oct, uint32_t reg)
857 {
858
859 return (bus_space_read_4(oct->mem_bus_space[0].tag,
860 oct->mem_bus_space[0].handle, reg));
861 }
862
863 static inline void
lio_write_csr32(struct octeon_device * oct,uint32_t reg,uint32_t val)864 lio_write_csr32(struct octeon_device *oct, uint32_t reg, uint32_t val)
865 {
866
867 bus_space_write_4(oct->mem_bus_space[0].tag,
868 oct->mem_bus_space[0].handle, reg, val);
869 }
870
871 static inline uint64_t
lio_read_csr64(struct octeon_device * oct,uint32_t reg)872 lio_read_csr64(struct octeon_device *oct, uint32_t reg)
873 {
874
875 #ifdef __i386__
876 return (lio_read_csr32(oct, reg) |
877 ((uint64_t)lio_read_csr32(oct, reg + 4) << 32));
878 #else
879 return (bus_space_read_8(oct->mem_bus_space[0].tag,
880 oct->mem_bus_space[0].handle, reg));
881 #endif
882 }
883
884 static inline void
lio_write_csr64(struct octeon_device * oct,uint32_t reg,uint64_t val)885 lio_write_csr64(struct octeon_device *oct, uint32_t reg, uint64_t val)
886 {
887
888 #ifdef __i386__
889 lio_write_csr32(oct, reg, (uint32_t)val);
890 lio_write_csr32(oct, reg + 4, val >> 32);
891 #else
892 bus_space_write_8(oct->mem_bus_space[0].tag,
893 oct->mem_bus_space[0].handle, reg, val);
894 #endif
895 }
896
897 #endif /* _LIO_DEVICE_H_ */
898