1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Resource Director Technology(RDT)
4 * - Cache Allocation code.
5 *
6 * Copyright (C) 2016 Intel Corporation
7 *
8 * Authors:
9 * Fenghua Yu <fenghua.yu@intel.com>
10 * Tony Luck <tony.luck@intel.com>
11 *
12 * More information about RDT be found in the Intel (R) x86 Architecture
13 * Software Developer Manual June 2016, volume 3, section 17.17.
14 */
15
16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
18 #include <linux/cpu.h>
19
20 #include "internal.h"
21
resctrl_arch_update_one(struct rdt_resource * r,struct rdt_ctrl_domain * d,u32 closid,enum resctrl_conf_type t,u32 cfg_val)22 int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_ctrl_domain *d,
23 u32 closid, enum resctrl_conf_type t, u32 cfg_val)
24 {
25 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(d);
26 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
27 u32 idx = resctrl_get_config_index(closid, t);
28 struct msr_param msr_param;
29
30 if (!cpumask_test_cpu(smp_processor_id(), &d->hdr.cpu_mask))
31 return -EINVAL;
32
33 hw_dom->ctrl_val[idx] = cfg_val;
34
35 msr_param.res = r;
36 msr_param.dom = d;
37 msr_param.low = idx;
38 msr_param.high = idx + 1;
39 hw_res->msr_update(&msr_param);
40
41 return 0;
42 }
43
resctrl_arch_update_domains(struct rdt_resource * r,u32 closid)44 int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid)
45 {
46 struct resctrl_staged_config *cfg;
47 struct rdt_hw_ctrl_domain *hw_dom;
48 struct msr_param msr_param;
49 struct rdt_ctrl_domain *d;
50 enum resctrl_conf_type t;
51 u32 idx;
52
53 /* Walking r->domains, ensure it can't race with cpuhp */
54 lockdep_assert_cpus_held();
55
56 list_for_each_entry(d, &r->ctrl_domains, hdr.list) {
57 hw_dom = resctrl_to_arch_ctrl_dom(d);
58 msr_param.res = NULL;
59 for (t = 0; t < CDP_NUM_TYPES; t++) {
60 cfg = &hw_dom->d_resctrl.staged_config[t];
61 if (!cfg->have_new_ctrl)
62 continue;
63
64 idx = resctrl_get_config_index(closid, t);
65 if (cfg->new_ctrl == hw_dom->ctrl_val[idx])
66 continue;
67 hw_dom->ctrl_val[idx] = cfg->new_ctrl;
68
69 if (!msr_param.res) {
70 msr_param.low = idx;
71 msr_param.high = msr_param.low + 1;
72 msr_param.res = r;
73 msr_param.dom = d;
74 } else {
75 msr_param.low = min(msr_param.low, idx);
76 msr_param.high = max(msr_param.high, idx + 1);
77 }
78 }
79 if (msr_param.res)
80 smp_call_function_any(&d->hdr.cpu_mask, rdt_ctrl_update, &msr_param, 1);
81 }
82
83 return 0;
84 }
85
resctrl_arch_get_config(struct rdt_resource * r,struct rdt_ctrl_domain * d,u32 closid,enum resctrl_conf_type type)86 u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_ctrl_domain *d,
87 u32 closid, enum resctrl_conf_type type)
88 {
89 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(d);
90 u32 idx = resctrl_get_config_index(closid, type);
91
92 return hw_dom->ctrl_val[idx];
93 }
94