1 /* 2 * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef __MLX5_ESWITCH_H__ 34 #define __MLX5_ESWITCH_H__ 35 36 #include <linux/if_ether.h> 37 #include <linux/if_link.h> 38 #include <linux/atomic.h> 39 #include <linux/wait.h> 40 #include <linux/xarray.h> 41 #include <net/devlink.h> 42 #include <linux/mlx5/device.h> 43 #include <linux/mlx5/eswitch.h> 44 #include <linux/mlx5/vport.h> 45 #include <linux/mlx5/fs.h> 46 #include "lib/mpfs.h" 47 #include "lib/fs_chains.h" 48 #include "sf/sf.h" 49 #include "en/tc_ct.h" 50 #include "en/tc/sample.h" 51 52 enum mlx5_mapped_obj_type { 53 MLX5_MAPPED_OBJ_CHAIN, 54 MLX5_MAPPED_OBJ_SAMPLE, 55 MLX5_MAPPED_OBJ_INT_PORT_METADATA, 56 MLX5_MAPPED_OBJ_ACT_MISS, 57 }; 58 59 struct mlx5_mapped_obj { 60 enum mlx5_mapped_obj_type type; 61 union { 62 u32 chain; 63 u64 act_miss_cookie; 64 struct { 65 u32 group_id; 66 u32 rate; 67 u32 trunc_size; 68 u32 tunnel_id; 69 } sample; 70 u32 int_port_metadata; 71 }; 72 }; 73 74 struct mlx5_esw_pf_info { 75 bool pf_not_exist; 76 bool pf_disabled; 77 u16 num_of_vfs; 78 u16 total_vfs; 79 u16 host_number; 80 u16 pf_num; 81 }; 82 83 #ifdef CONFIG_MLX5_ESWITCH 84 85 #define ESW_OFFLOADS_DEFAULT_NUM_GROUPS 15 86 87 #define MLX5_MAX_UC_PER_VPORT(dev) \ 88 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) 89 90 #define MLX5_MAX_MC_PER_VPORT(dev) \ 91 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) 92 93 #define mlx5_esw_has_fwd_fdb(dev) \ 94 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) 95 96 #define esw_chains(esw) \ 97 ((esw)->fdb_table.offloads.esw_chains_priv) 98 99 enum { 100 MAPPING_TYPE_CHAIN, 101 MAPPING_TYPE_TUNNEL, 102 MAPPING_TYPE_TUNNEL_ENC_OPTS, 103 MAPPING_TYPE_LABELS, 104 MAPPING_TYPE_ZONE, 105 MAPPING_TYPE_INT_PORT, 106 }; 107 108 struct vport_ingress { 109 struct mlx5_flow_table *acl; 110 struct mlx5_flow_handle *allow_rule; 111 struct { 112 struct mlx5_flow_group *allow_spoofchk_only_grp; 113 struct mlx5_flow_group *allow_untagged_spoofchk_grp; 114 struct mlx5_flow_group *allow_untagged_only_grp; 115 struct mlx5_flow_group *drop_grp; 116 struct mlx5_flow_handle *drop_rule; 117 struct mlx5_fc *drop_counter; 118 } legacy; 119 struct { 120 /* Optional group to add an FTE to do internal priority 121 * tagging on ingress packets. 122 */ 123 struct mlx5_flow_group *metadata_prio_tag_grp; 124 /* Group to add default match-all FTE entry to tag ingress 125 * packet with metadata. 126 */ 127 struct mlx5_flow_group *metadata_allmatch_grp; 128 /* Optional group to add a drop all rule */ 129 struct mlx5_flow_group *drop_grp; 130 struct mlx5_modify_hdr *modify_metadata; 131 struct mlx5_flow_handle *modify_metadata_rule; 132 struct mlx5_flow_handle *drop_rule; 133 } offloads; 134 }; 135 136 enum vport_egress_acl_type { 137 VPORT_EGRESS_ACL_TYPE_DEFAULT, 138 VPORT_EGRESS_ACL_TYPE_SHARED_FDB, 139 }; 140 141 struct vport_egress { 142 struct mlx5_flow_table *acl; 143 enum vport_egress_acl_type type; 144 struct mlx5_flow_handle *allowed_vlan; 145 struct mlx5_flow_group *vlan_grp; 146 union { 147 struct { 148 struct mlx5_flow_group *drop_grp; 149 struct mlx5_flow_handle *drop_rule; 150 struct mlx5_fc *drop_counter; 151 } legacy; 152 struct { 153 struct mlx5_flow_group *fwd_grp; 154 struct mlx5_flow_handle *fwd_rule; 155 struct xarray bounce_rules; 156 struct mlx5_flow_group *bounce_grp; 157 } offloads; 158 }; 159 }; 160 161 struct mlx5_vport_drop_stats { 162 u64 rx_dropped; 163 u64 tx_dropped; 164 }; 165 166 struct mlx5_vport_info { 167 u8 mac[ETH_ALEN]; 168 u16 vlan; 169 u64 node_guid; 170 int link_state; 171 u8 qos; 172 u8 spoofchk: 1; 173 u8 trusted: 1; 174 u8 roce_enabled: 1; 175 u8 mig_enabled: 1; 176 u8 ipsec_crypto_enabled: 1; 177 u8 ipsec_packet_enabled: 1; 178 }; 179 180 /* Vport context events */ 181 enum mlx5_eswitch_vport_event { 182 MLX5_VPORT_UC_ADDR_CHANGE = BIT(0), 183 MLX5_VPORT_MC_ADDR_CHANGE = BIT(1), 184 MLX5_VPORT_PROMISC_CHANGE = BIT(3), 185 }; 186 187 struct mlx5_vport; 188 189 struct mlx5_devlink_port { 190 struct devlink_port dl_port; 191 struct mlx5_vport *vport; 192 struct devlink_health_reporter *vnic_reporter; 193 }; 194 195 static inline void mlx5_devlink_port_init(struct mlx5_devlink_port *dl_port, 196 struct mlx5_vport *vport) 197 { 198 dl_port->vport = vport; 199 } 200 201 static inline struct mlx5_devlink_port *mlx5_devlink_port_get(struct devlink_port *dl_port) 202 { 203 return container_of(dl_port, struct mlx5_devlink_port, dl_port); 204 } 205 206 static inline struct mlx5_vport *mlx5_devlink_port_vport_get(struct devlink_port *dl_port) 207 { 208 return mlx5_devlink_port_get(dl_port)->vport; 209 } 210 211 #define MLX5_VHCA_ID_INVALID (-1) 212 213 #define MLX5_VPORT_INVAL_VHCA_ID(vport) \ 214 ((vport)->vhca_id == MLX5_VHCA_ID_INVALID) 215 216 struct mlx5_vport { 217 struct mlx5_core_dev *dev; 218 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; 219 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; 220 struct mlx5_flow_handle *promisc_rule; 221 struct mlx5_flow_handle *allmulti_rule; 222 struct work_struct vport_change_handler; 223 224 struct vport_ingress ingress; 225 struct vport_egress egress; 226 u32 default_metadata; 227 u32 metadata; 228 int vhca_id; 229 230 bool adjacent; /* delegated vhca from adjacent function */ 231 struct { 232 u16 parent_pci_devfn; /* Adjacent parent PCI device function */ 233 u16 function_id; /* Function ID of the delegated VPort */ 234 } adj_info; 235 236 struct mlx5_vport_info info; 237 238 /* Protected by either the shared devlink (dev->shd) lock or by 239 * esw->state_lock. See esw_assert_qos_lock_held() for more details. 240 * The Vport QoS can either be disabled (sched_node is NULL) or in one 241 * of three states: 242 * 1. Regular QoS (sched_node is a vport node). 243 * 2. TC QoS enabled on the vport (sched_node is a TC arbiter). 244 * 3. TC QoS enabled on the vport's parent node 245 * (sched_node is a rate limit node). 246 * When TC is enabled in either mode, the vport owns vport TC scheduling 247 * nodes. 248 */ 249 struct { 250 /* Vport scheduling node. */ 251 struct mlx5_esw_sched_node *sched_node; 252 /* Array of vport traffic class scheduling nodes. */ 253 struct mlx5_esw_sched_node **sched_nodes; 254 } qos; 255 256 u16 vport; 257 bool enabled; 258 bool max_eqs_set; 259 bool pf_activated; 260 enum mlx5_eswitch_vport_event enabled_events; 261 int index; 262 struct mlx5_devlink_port *dl_port; 263 u32 agg_max_tx_speed; 264 }; 265 266 struct mlx5_esw_indir_table; 267 268 struct mlx5_eswitch_fdb { 269 union { 270 struct legacy_fdb { 271 struct mlx5_flow_table *fdb; 272 struct mlx5_flow_group *addr_grp; 273 struct mlx5_flow_group *allmulti_grp; 274 struct mlx5_flow_group *promisc_grp; 275 struct mlx5_flow_table *vepa_fdb; 276 struct mlx5_flow_handle *vepa_uplink_rule; 277 struct mlx5_flow_handle *vepa_star_rule; 278 } legacy; 279 280 struct offloads_fdb { 281 struct mlx5_flow_namespace *ns; 282 struct mlx5_flow_table *drop_root; 283 struct mlx5_flow_handle *drop_root_rule; 284 struct mlx5_fc *drop_root_fc; 285 struct mlx5_flow_table *tc_miss_table; 286 struct mlx5_flow_table *slow_fdb; 287 struct mlx5_flow_group *send_to_vport_grp; 288 struct mlx5_flow_group *send_to_vport_meta_grp; 289 struct mlx5_flow_group *peer_miss_grp; 290 struct xarray peer_miss_rules; 291 struct mlx5_flow_group *miss_grp; 292 struct mlx5_flow_handle **send_to_vport_meta_rules; 293 struct mlx5_flow_handle *miss_rule_uni; 294 struct mlx5_flow_handle *miss_rule_multi; 295 296 struct mlx5_fs_chains *esw_chains_priv; 297 struct { 298 DECLARE_HASHTABLE(table, 8); 299 /* Protects vports.table */ 300 struct mutex lock; 301 } vports; 302 303 struct mlx5_esw_indir_table *indir; 304 305 } offloads; 306 }; 307 u32 flags; 308 }; 309 310 struct mlx5_esw_offload { 311 struct mlx5_flow_table *ft_offloads_restore; 312 struct mlx5_flow_group *restore_group; 313 struct mlx5_modify_hdr *restore_copy_hdr_id; 314 struct mapping_ctx *reg_c0_obj_pool; 315 316 struct mlx5_flow_table *ft_offloads; 317 struct mlx5_flow_group *vport_rx_group; 318 struct mlx5_flow_group *vport_rx_drop_group; 319 struct mlx5_flow_handle *vport_rx_drop_rule; 320 struct mlx5_flow_table *ft_ipsec_tx_pol; 321 struct xarray vport_reps; 322 struct list_head peer_flows[MLX5_MAX_PORTS]; 323 struct mutex peer_mutex; 324 struct mutex encap_tbl_lock; /* protects encap_tbl */ 325 DECLARE_HASHTABLE(encap_tbl, 8); 326 struct mutex decap_tbl_lock; /* protects decap_tbl */ 327 DECLARE_HASHTABLE(decap_tbl, 8); 328 struct mod_hdr_tbl mod_hdr; 329 DECLARE_HASHTABLE(termtbl_tbl, 8); 330 struct mutex termtbl_mutex; /* protects termtbl hash */ 331 struct xarray vhca_map; 332 struct mutex reps_lock; /* protects representor load/unload/register */ 333 const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES]; 334 u8 inline_mode; 335 atomic64_t num_flows; 336 u64 num_block_encap; 337 u64 num_block_mode; 338 enum devlink_eswitch_encap_mode encap; 339 struct ida vport_metadata_ida; 340 }; 341 342 /* E-Switch MC FDB table hash node */ 343 struct esw_mc_addr { /* SRIOV only */ 344 struct l2addr_node node; 345 struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ 346 u32 refcnt; 347 }; 348 349 struct mlx5_host_work { 350 struct work_struct work; 351 struct mlx5_eswitch *esw; 352 int work_gen; 353 void (*func)(struct mlx5_eswitch *esw); 354 }; 355 356 struct mlx5_esw_spf { 357 u16 vport_num; 358 u16 vhca_id; 359 u16 host_number; 360 u16 pf_num; 361 }; 362 363 struct mlx5_esw_functions { 364 struct mlx5_nb nb; 365 bool host_funcs_disabled; 366 u16 num_vfs; 367 u16 num_ec_vfs; 368 u16 hpf_host_number; 369 u16 hpf_pf_num; 370 bool has_spf_sfs; 371 struct mlx5_esw_spf *spfs; 372 int num_spfs; 373 }; 374 375 enum { 376 MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0), 377 MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED = BIT(1), 378 MLX5_ESWITCH_VPORT_ACL_NS_CREATED = BIT(2), 379 }; 380 381 struct mlx5_esw_bridge_offloads; 382 383 enum { 384 MLX5_ESW_FDB_CREATED = BIT(0), 385 }; 386 387 struct dentry; 388 389 struct mlx5_eswitch { 390 struct mlx5_core_dev *dev; 391 struct mlx5_nb nb; 392 struct mlx5_eswitch_fdb fdb_table; 393 /* legacy data structures */ 394 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; 395 struct esw_mc_addr mc_promisc; 396 /* end of legacy */ 397 struct dentry *debugfs_root; 398 struct workqueue_struct *work_queue; 399 struct xarray vports; 400 struct xarray vhca_type_map; 401 u32 flags; 402 int total_vports; 403 int enabled_vports; 404 /* Synchronize between vport change events 405 * and async SRIOV admin state changes 406 */ 407 struct mutex state_lock; 408 409 /* Protects eswitch mode change that occurs via one or more 410 * user commands, i.e. sriov state change, devlink commands. 411 */ 412 struct rw_semaphore mode_lock; 413 atomic64_t user_count; 414 wait_queue_head_t work_queue_wait; 415 416 /* QoS changes are serialized by either the shared devlink (dev->shd) 417 * lock or by esw->state_lock. See esw_assert_qos_lock_held() for more 418 * details. 419 */ 420 struct { 421 /* Initially 0, meaning no QoS users and QoS is disabled. */ 422 refcount_t refcnt; 423 /* The root node of the hierarchy. */ 424 struct mlx5_esw_sched_node *root; 425 } qos; 426 427 struct mlx5_esw_bridge_offloads *br_offloads; 428 struct mlx5_esw_offload offloads; 429 u32 last_vport_idx; 430 int mode; 431 bool offloads_inactive; 432 u16 manager_vport; 433 u16 first_host_vport; 434 u8 num_peers; 435 struct mlx5_esw_functions esw_funcs; 436 struct { 437 u32 large_group_num; 438 } params; 439 struct xarray paired; 440 struct mlx5_devcom_comp_dev *devcom; 441 u16 enabled_ipsec_vf_count; 442 bool eswitch_operation_in_progress; 443 atomic_t generation; 444 }; 445 446 void esw_offloads_disable(struct mlx5_eswitch *esw); 447 int esw_offloads_enable(struct mlx5_eswitch *esw); 448 int mlx5_esw_offloads_init_deferred_metadata(struct mlx5_eswitch *esw); 449 void esw_offloads_cleanup(struct mlx5_eswitch *esw); 450 int esw_offloads_init(struct mlx5_eswitch *esw); 451 452 struct mlx5_flow_handle * 453 mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch *esw, u16 vport_num); 454 void mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle *rule); 455 456 bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw); 457 u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw); 458 void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata); 459 460 int mlx5_esw_qos_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num, u32 rate_mbps); 461 462 /* E-Switch API */ 463 int mlx5_eswitch_init(struct mlx5_core_dev *dev); 464 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); 465 int mlx5_esw_vport_alloc(struct mlx5_eswitch *esw, int index, u16 vport_num); 466 void mlx5_esw_vport_free(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 467 468 #define MLX5_ESWITCH_IGNORE_NUM_VFS (-1) 469 int mlx5_eswitch_enable_locked(struct mlx5_eswitch *esw, int num_vfs); 470 int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs); 471 void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw, bool clear_vf); 472 void mlx5_eswitch_disable_locked(struct mlx5_eswitch *esw); 473 void mlx5_eswitch_disable(struct mlx5_eswitch *esw); 474 void mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw, 475 const struct mlx5_devcom_match_attr *attr); 476 void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw); 477 bool mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch *esw); 478 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, 479 u16 vport, const u8 *mac); 480 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, 481 u16 vport, int link_state); 482 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, 483 u16 vport, u16 vlan, u8 qos); 484 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, 485 u16 vport, bool spoofchk); 486 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, 487 u16 vport_num, bool setting); 488 int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport, 489 u32 max_rate, u32 min_rate); 490 int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting); 491 int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting); 492 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, 493 u16 vport, struct ifla_vf_info *ivi); 494 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, 495 u16 vport, 496 struct ifla_vf_stats *vf_stats); 497 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); 498 499 int mlx5_eswitch_modify_esw_vport_context(struct mlx5_core_dev *dev, u16 vport, 500 bool other_vport, void *in); 501 502 struct mlx5_flow_spec; 503 struct mlx5_esw_flow_attr; 504 struct mlx5_termtbl_handle; 505 506 bool 507 mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw, 508 struct mlx5_flow_attr *attr, 509 struct mlx5_flow_act *flow_act, 510 struct mlx5_flow_spec *spec); 511 512 struct mlx5_flow_handle * 513 mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw, 514 struct mlx5_flow_table *ft, 515 struct mlx5_flow_spec *spec, 516 struct mlx5_esw_flow_attr *attr, 517 struct mlx5_flow_act *flow_act, 518 struct mlx5_flow_destination *dest, 519 int num_dest); 520 521 void 522 mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw, 523 struct mlx5_termtbl_handle *tt); 524 525 void 526 mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec); 527 528 struct mlx5_flow_handle * 529 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, 530 struct mlx5_flow_spec *spec, 531 struct mlx5_flow_attr *attr); 532 struct mlx5_flow_handle * 533 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, 534 struct mlx5_flow_spec *spec, 535 struct mlx5_flow_attr *attr); 536 void 537 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, 538 struct mlx5_flow_handle *rule, 539 struct mlx5_flow_attr *attr); 540 void 541 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, 542 struct mlx5_flow_handle *rule, 543 struct mlx5_flow_attr *attr); 544 545 struct mlx5_flow_handle * 546 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport, 547 struct mlx5_flow_destination *dest); 548 549 enum { 550 SET_VLAN_STRIP = BIT(0), 551 SET_VLAN_INSERT = BIT(1) 552 }; 553 554 enum mlx5_flow_match_level { 555 MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, 556 MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, 557 MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, 558 MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, 559 }; 560 561 /* current maximum for flow based vport multicasting */ 562 #define MLX5_MAX_FLOW_FWD_VPORTS 32 563 564 enum { 565 MLX5_ESW_DEST_ENCAP = BIT(0), 566 MLX5_ESW_DEST_ENCAP_VALID = BIT(1), 567 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE = BIT(2), 568 }; 569 570 struct mlx5_esw_flow_attr { 571 struct mlx5_eswitch_rep *in_rep; 572 struct mlx5_core_dev *in_mdev; 573 struct mlx5_core_dev *counter_dev; 574 struct mlx5e_tc_int_port *dest_int_port; 575 struct mlx5e_tc_int_port *int_port; 576 577 int split_count; 578 int out_count; 579 580 __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; 581 u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; 582 u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; 583 u8 total_vlan; 584 struct { 585 u32 flags; 586 bool vport_valid; 587 u16 vport; 588 struct mlx5_pkt_reformat *pkt_reformat; 589 struct mlx5_core_dev *mdev; 590 struct mlx5_termtbl_handle *termtbl; 591 int src_port_rewrite_act_id; 592 } dests[MLX5_MAX_FLOW_FWD_VPORTS]; 593 struct mlx5_rx_tun_attr *rx_tun_attr; 594 struct ethhdr eth; 595 struct mlx5_pkt_reformat *decap_pkt_reformat; 596 }; 597 598 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, 599 struct netlink_ext_ack *extack); 600 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); 601 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, 602 struct netlink_ext_ack *extack); 603 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); 604 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, 605 enum devlink_eswitch_encap_mode encap, 606 struct netlink_ext_ack *extack); 607 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, 608 enum devlink_eswitch_encap_mode *encap); 609 int mlx5_devlink_port_fn_hw_addr_get(struct devlink_port *port, 610 u8 *hw_addr, int *hw_addr_len, 611 struct netlink_ext_ack *extack); 612 int mlx5_devlink_port_fn_hw_addr_set(struct devlink_port *port, 613 const u8 *hw_addr, int hw_addr_len, 614 struct netlink_ext_ack *extack); 615 int mlx5_devlink_port_fn_roce_get(struct devlink_port *port, bool *is_enabled, 616 struct netlink_ext_ack *extack); 617 int mlx5_devlink_port_fn_roce_set(struct devlink_port *port, bool enable, 618 struct netlink_ext_ack *extack); 619 int mlx5_devlink_port_fn_migratable_get(struct devlink_port *port, bool *is_enabled, 620 struct netlink_ext_ack *extack); 621 int mlx5_devlink_port_fn_migratable_set(struct devlink_port *port, bool enable, 622 struct netlink_ext_ack *extack); 623 int mlx5_devlink_pf_port_fn_state_get(struct devlink_port *port, 624 enum devlink_port_fn_state *state, 625 enum devlink_port_fn_opstate *opstate, 626 struct netlink_ext_ack *extack); 627 int mlx5_devlink_pf_port_fn_state_set(struct devlink_port *port, 628 enum devlink_port_fn_state state, 629 struct netlink_ext_ack *extack); 630 #ifdef CONFIG_XFRM_OFFLOAD 631 int mlx5_devlink_port_fn_ipsec_crypto_get(struct devlink_port *port, bool *is_enabled, 632 struct netlink_ext_ack *extack); 633 int mlx5_devlink_port_fn_ipsec_crypto_set(struct devlink_port *port, bool enable, 634 struct netlink_ext_ack *extack); 635 int mlx5_devlink_port_fn_ipsec_packet_get(struct devlink_port *port, bool *is_enabled, 636 struct netlink_ext_ack *extack); 637 int mlx5_devlink_port_fn_ipsec_packet_set(struct devlink_port *port, bool enable, 638 struct netlink_ext_ack *extack); 639 #endif /* CONFIG_XFRM_OFFLOAD */ 640 int mlx5_devlink_port_fn_max_io_eqs_get(struct devlink_port *port, 641 u32 *max_io_eqs, 642 struct netlink_ext_ack *extack); 643 int mlx5_devlink_port_fn_max_io_eqs_set(struct devlink_port *port, 644 u32 max_io_eqs, 645 struct netlink_ext_ack *extack); 646 int mlx5_devlink_port_fn_max_io_eqs_set_sf_default(struct devlink_port *port, 647 struct netlink_ext_ack *extack); 648 649 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); 650 651 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, 652 u16 vport, u16 vlan, u8 qos, u8 set_flags); 653 654 static inline bool esw_vst_mode_is_steering(struct mlx5_eswitch *esw) 655 { 656 return (MLX5_CAP_ESW_EGRESS_ACL(esw->dev, pop_vlan) && 657 MLX5_CAP_ESW_INGRESS_ACL(esw->dev, push_vlan)); 658 } 659 660 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, 661 u8 vlan_depth) 662 { 663 bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && 664 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); 665 666 if (vlan_depth == 1) 667 return ret; 668 669 return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && 670 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); 671 } 672 673 bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0, 674 struct mlx5_core_dev *dev1); 675 676 const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); 677 struct mlx5_esw_pf_info mlx5_esw_get_host_pf_info(struct mlx5_core_dev *dev, 678 const u32 *out); 679 bool mlx5_esw_get_spf_disabled(struct mlx5_core_dev *dev, const u32 *out, 680 u16 vhca_id); 681 int mlx5_esw_pf_enable_hca(struct mlx5_core_dev *dev, u16 vport_num); 682 int mlx5_esw_pf_disable_hca(struct mlx5_core_dev *dev, u16 vport_num); 683 int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev *dev); 684 int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev *dev); 685 686 void mlx5_esw_adjacent_vhcas_setup(struct mlx5_eswitch *esw); 687 void mlx5_esw_adjacent_vhcas_cleanup(struct mlx5_eswitch *esw); 688 int mlx5_esw_adj_vport_modify(struct mlx5_core_dev *dev, u16 vport, 689 bool connect); 690 int mlx5_esw_create_esw_vport(struct mlx5_core_dev *dev, u16 vhca_id, 691 u16 *vport_num); 692 void mlx5_esw_destroy_esw_vport(struct mlx5_core_dev *dev, u16 vport); 693 694 #define MLX5_DEBUG_ESWITCH_MASK BIT(3) 695 696 #define esw_info(__dev, format, ...) \ 697 dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) 698 699 #define esw_warn(__dev, format, ...) \ 700 dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) 701 702 #define esw_debug(dev, format, ...) \ 703 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) 704 705 static inline bool mlx5_esw_allowed(const struct mlx5_eswitch *esw) 706 { 707 return esw && MLX5_ESWITCH_MANAGER(esw->dev); 708 } 709 710 static inline bool 711 mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num) 712 { 713 return esw->manager_vport == vport_num; 714 } 715 716 static inline bool mlx5_esw_is_owner(struct mlx5_eswitch *esw, u16 vport_num, 717 u16 esw_owner_vhca_id) 718 { 719 return esw_owner_vhca_id == MLX5_CAP_GEN(esw->dev, vhca_id) || 720 (vport_num == MLX5_VPORT_UPLINK && mlx5_lag_is_master(esw->dev)); 721 } 722 723 static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev) 724 { 725 return mlx5_core_is_ecpf_esw_manager(dev) ? 726 MLX5_VPORT_HOST_PF : MLX5_VPORT_FIRST_HOST_VF; 727 } 728 729 static inline bool mlx5_eswitch_is_funcs_handler(const struct mlx5_core_dev *dev) 730 { 731 return mlx5_core_is_ecpf_esw_manager(dev); 732 } 733 734 static inline unsigned int 735 mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev, 736 u16 vport_num) 737 { 738 return (MLX5_CAP_GEN(dev, vhca_id) << 16) | vport_num; 739 } 740 741 static inline u16 742 mlx5_esw_devlink_port_index_to_vport_num(unsigned int dl_port_index) 743 { 744 return dl_port_index & 0xffff; 745 } 746 747 static inline bool mlx5_esw_is_fdb_created(struct mlx5_eswitch *esw) 748 { 749 return esw->fdb_table.flags & MLX5_ESW_FDB_CREATED; 750 } 751 752 /* TODO: This mlx5e_tc function shouldn't be called by eswitch */ 753 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw); 754 755 /* Each mark identifies eswitch vport type. 756 * MLX5_ESW_VPT_HOST_FN is used to identify both PF and VF ports using 757 * a single mark. 758 * MLX5_ESW_VPT_VF identifies a SRIOV VF vport. 759 * MLX5_ESW_VPT_SF identifies SF vport. 760 */ 761 #define MLX5_ESW_VPT_HOST_FN XA_MARK_0 762 #define MLX5_ESW_VPT_VF XA_MARK_1 763 #define MLX5_ESW_VPT_SF XA_MARK_2 764 765 /* The vport iterator is valid only after vport are initialized in mlx5_eswitch_init. 766 * Borrowed the idea from xa_for_each_marked() but with support for desired last element. 767 */ 768 769 #define mlx5_esw_for_each_vport(esw, index, vport) \ 770 xa_for_each(&((esw)->vports), index, vport) 771 772 #define mlx5_esw_for_each_entry_marked(xa, index, entry, last, filter) \ 773 for (index = 0, entry = xa_find(xa, &index, last, filter); \ 774 entry; entry = xa_find_after(xa, &index, last, filter)) 775 776 #define mlx5_esw_for_each_vport_marked(esw, index, vport, last, filter) \ 777 mlx5_esw_for_each_entry_marked(&((esw)->vports), index, vport, last, filter) 778 779 #define mlx5_esw_for_each_vf_vport(esw, index, vport, last) \ 780 mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_VF) 781 782 #define mlx5_esw_for_each_host_func_vport(esw, index, vport, last) \ 783 mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_HOST_FN) 784 785 /* This macro should only be used if EC SRIOV is enabled. 786 * 787 * Because there were no more marks available on the xarray this uses a 788 * for_each_range approach. The range is only valid when EC SRIOV is enabled 789 */ 790 #define mlx5_esw_for_each_ec_vf_vport(esw, index, vport, last) \ 791 xa_for_each_range(&((esw)->vports), \ 792 index, \ 793 vport, \ 794 MLX5_CAP_GEN_2((esw->dev), ec_vf_vport_base), \ 795 MLX5_CAP_GEN_2((esw->dev), ec_vf_vport_base) +\ 796 (last) - 1) 797 798 /* SPF vport numbers are not contiguous, iterate via the spfs array 799 * and look up each vport in the xarray. 800 */ 801 #define mlx5_esw_for_each_spf_vport(esw, index, vport) \ 802 for ((index) = 0; \ 803 (index) < (esw)->esw_funcs.num_spfs && \ 804 ((vport) = xa_load(&(esw)->vports, \ 805 (esw)->esw_funcs.spfs[(index)].vport_num)); \ 806 (index)++) 807 808 #define mlx5_esw_for_each_rep(esw, i, rep) \ 809 xa_for_each(&((esw)->offloads.vport_reps), i, rep) 810 811 struct mlx5_eswitch *__must_check 812 mlx5_devlink_eswitch_get(struct devlink *devlink); 813 814 struct mlx5_eswitch *mlx5_devlink_eswitch_nocheck_get(struct devlink *devlink); 815 816 struct mlx5_vport *__must_check 817 mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num); 818 819 bool mlx5_eswitch_is_vf_vport(struct mlx5_eswitch *esw, u16 vport_num); 820 int mlx5_esw_spf_vport_to_idx(struct mlx5_eswitch *esw, u16 vport_num); 821 bool mlx5_esw_is_spf_vport(struct mlx5_eswitch *esw, u16 vport_num); 822 bool mlx5_eswitch_is_pf_vf_vport(struct mlx5_eswitch *esw, u16 vport_num); 823 bool mlx5_esw_is_sf_vport(struct mlx5_eswitch *esw, u16 vport_num); 824 825 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data); 826 827 int 828 mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw, 829 enum mlx5_eswitch_vport_event enabled_events); 830 void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw); 831 832 int mlx5_esw_vport_enable(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 833 enum mlx5_eswitch_vport_event enabled_events); 834 void mlx5_esw_vport_disable(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 835 836 int 837 esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw, 838 struct mlx5_vport *vport); 839 void 840 esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw, 841 struct mlx5_vport *vport); 842 843 struct esw_vport_tbl_namespace { 844 int max_fte; 845 int max_num_groups; 846 u32 flags; 847 }; 848 849 struct mlx5_vport_tbl_attr { 850 u32 chain; 851 u16 prio; 852 u16 vport; 853 struct esw_vport_tbl_namespace *vport_ns; 854 }; 855 856 struct mlx5_flow_table * 857 mlx5_esw_vporttbl_get(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr); 858 void 859 mlx5_esw_vporttbl_put(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr); 860 861 struct mlx5_flow_handle * 862 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag); 863 864 void mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch *esw, 865 u32 *flow_group_in, 866 int match_params); 867 868 void mlx5_esw_set_spec_source_port(struct mlx5_eswitch *esw, 869 u16 vport, 870 struct mlx5_flow_spec *spec); 871 872 int mlx5_esw_offloads_init_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 873 void mlx5_esw_offloads_cleanup_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 874 875 int mlx5_esw_offloads_init_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 876 struct mlx5_devlink_port *dl_port, 877 u32 controller, u32 sfnum); 878 void mlx5_esw_offloads_cleanup_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 879 880 int mlx5_esw_offloads_load_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 881 void mlx5_esw_offloads_unload_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 882 883 int mlx5_eswitch_load_sf_vport(struct mlx5_eswitch *esw, u16 vport_num, 884 enum mlx5_eswitch_vport_event enabled_events, 885 struct mlx5_devlink_port *dl_port, u32 controller, u32 sfnum); 886 void mlx5_eswitch_unload_sf_vport(struct mlx5_eswitch *esw, u16 vport_num); 887 888 int mlx5_eswitch_load_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs, 889 enum mlx5_eswitch_vport_event enabled_events); 890 void mlx5_eswitch_unload_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs); 891 892 int mlx5_esw_offloads_pf_vf_devlink_port_init(struct mlx5_eswitch *esw, 893 struct mlx5_vport *vport); 894 void mlx5_esw_offloads_pf_vf_devlink_port_cleanup(struct mlx5_eswitch *esw, 895 struct mlx5_vport *vport); 896 897 int mlx5_esw_offloads_sf_devlink_port_init(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 898 struct mlx5_devlink_port *dl_port, 899 u32 controller, u32 sfnum); 900 void mlx5_esw_offloads_sf_devlink_port_cleanup(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 901 902 int mlx5_esw_offloads_devlink_port_register(struct mlx5_eswitch *esw, struct mlx5_vport *vport); 903 void mlx5_esw_offloads_devlink_port_unregister(struct mlx5_vport *vport); 904 struct devlink_port *mlx5_esw_offloads_devlink_port(struct mlx5_eswitch *esw, u16 vport_num); 905 906 int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_dev *dev, u16 *max_sfs, u16 *sf_base_id); 907 int mlx5_esw_sf_max_spf_functions(struct mlx5_core_dev *dev, int spf_idx, 908 u16 *max_sfs, u16 *sf_base_id); 909 910 int mlx5_esw_get_num_spfs(struct mlx5_core_dev *dev); 911 int mlx5_esw_spf_get_host_number(struct mlx5_core_dev *dev, int spf_idx, 912 u16 *host_number); 913 u16 mlx5_esw_get_hpf_host_number(struct mlx5_core_dev *dev); 914 u16 mlx5_esw_get_hpf_pf_num(struct mlx5_core_dev *dev); 915 u16 mlx5_esw_sf_controller_to_pfnum(struct mlx5_core_dev *dev, u32 controller); 916 bool mlx5_esw_has_spf_sfs(struct mlx5_core_dev *dev); 917 918 int mlx5_esw_vport_vhca_id_map(struct mlx5_eswitch *esw, 919 struct mlx5_vport *vport); 920 void mlx5_esw_vport_vhca_id_unmap(struct mlx5_eswitch *esw, 921 struct mlx5_vport *vport); 922 int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num); 923 bool mlx5_esw_vport_vhca_id(struct mlx5_eswitch *esw, u16 vportn, u16 *vhca_id); 924 u16 mlx5_esw_vhca_id_to_func_type(struct mlx5_core_dev *dev, u16 vhca_id); 925 926 void mlx5_esw_offloads_rep_remove(struct mlx5_eswitch *esw, 927 const struct mlx5_vport *vport); 928 int mlx5_esw_offloads_rep_add(struct mlx5_eswitch *esw, 929 const struct mlx5_vport *vport); 930 931 /** 932 * struct mlx5_esw_event_info - Indicates eswitch mode changed/changing. 933 * 934 * @new_mode: New mode of eswitch. 935 */ 936 struct mlx5_esw_event_info { 937 u16 new_mode; 938 }; 939 940 int mlx5_esw_event_notifier_register(struct mlx5_core_dev *dev, 941 struct notifier_block *n); 942 void mlx5_esw_event_notifier_unregister(struct mlx5_core_dev *dev, 943 struct notifier_block *n); 944 945 bool mlx5_esw_hold(struct mlx5_core_dev *dev); 946 void mlx5_esw_release(struct mlx5_core_dev *dev); 947 void mlx5_esw_get(struct mlx5_core_dev *dev); 948 void mlx5_esw_put(struct mlx5_core_dev *dev); 949 int mlx5_esw_try_lock(struct mlx5_eswitch *esw); 950 int mlx5_esw_lock(struct mlx5_eswitch *esw); 951 void mlx5_esw_unlock(struct mlx5_eswitch *esw); 952 953 void esw_vport_change_handle_locked(struct mlx5_vport *vport); 954 955 bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller); 956 957 int mlx5_eswitch_offloads_vport_lag_add_one(struct mlx5_eswitch *master_esw, 958 struct mlx5_eswitch *slave_esw); 959 void mlx5_eswitch_offloads_vport_lag_del_one(struct mlx5_eswitch *master_esw, 960 struct mlx5_eswitch *slave_esw); 961 int mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw, 962 struct mlx5_eswitch *slave_esw, int max_slaves); 963 void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw, 964 struct mlx5_eswitch *slave_esw); 965 int mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw); 966 void mlx5_eswitch_unload_reps(struct mlx5_eswitch *esw); 967 bool mlx5_eswitch_is_peer(struct mlx5_eswitch *esw, 968 struct mlx5_eswitch *peer_esw); 969 970 bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb); 971 void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev); 972 973 int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev); 974 void mlx5_eswitch_unblock_mode(struct mlx5_core_dev *dev); 975 976 static inline int mlx5_eswitch_num_vfs(struct mlx5_eswitch *esw) 977 { 978 if (mlx5_esw_allowed(esw)) 979 return esw->esw_funcs.num_vfs; 980 981 return 0; 982 } 983 984 static inline struct mlx5_flow_table * 985 mlx5_eswitch_get_slow_fdb(struct mlx5_eswitch *esw) 986 { 987 return esw->fdb_table.offloads.slow_fdb; 988 } 989 990 int mlx5_eswitch_restore_ipsec_rule(struct mlx5_eswitch *esw, struct mlx5_flow_handle *rule, 991 struct mlx5_esw_flow_attr *esw_attr, int attr_idx); 992 bool mlx5_eswitch_block_ipsec(struct mlx5_core_dev *dev); 993 void mlx5_eswitch_unblock_ipsec(struct mlx5_core_dev *dev); 994 bool mlx5_esw_ipsec_vf_offload_supported(struct mlx5_core_dev *dev); 995 int mlx5_esw_ipsec_vf_offload_get(struct mlx5_core_dev *dev, 996 struct mlx5_vport *vport); 997 int mlx5_esw_ipsec_vf_crypto_offload_supported(struct mlx5_core_dev *dev, 998 u16 vport_num); 999 int mlx5_esw_ipsec_vf_crypto_offload_set(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 1000 bool enable); 1001 int mlx5_esw_ipsec_vf_packet_offload_set(struct mlx5_eswitch *esw, struct mlx5_vport *vport, 1002 bool enable); 1003 int mlx5_esw_ipsec_vf_packet_offload_supported(struct mlx5_core_dev *dev, 1004 u16 vport_num); 1005 bool mlx5_esw_host_functions_enabled(const struct mlx5_core_dev *dev); 1006 void mlx5_eswitch_safe_aux_devs_remove(struct mlx5_core_dev *dev); 1007 struct mlx5_flow_group * 1008 mlx5_esw_lag_demux_fg_create(struct mlx5_eswitch *esw, 1009 struct mlx5_flow_table *ft); 1010 struct mlx5_flow_handle * 1011 mlx5_esw_lag_demux_rule_create(struct mlx5_eswitch *esw, u16 vport_num, 1012 struct mlx5_flow_table *lag_ft); 1013 void mlx5_esw_reps_block(struct mlx5_eswitch *esw); 1014 void mlx5_esw_reps_unblock(struct mlx5_eswitch *esw); 1015 #else /* CONFIG_MLX5_ESWITCH */ 1016 /* eswitch API stubs */ 1017 static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } 1018 static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} 1019 static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs) { return 0; } 1020 static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw, bool clear_vf) {} 1021 static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw) {} 1022 static inline void 1023 mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw, 1024 const struct mlx5_devcom_match_attr *attr) {} 1025 static inline void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw) {} 1026 static inline bool mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch *esw) { return false; } 1027 static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; } 1028 static inline 1029 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, u16 vport, int link_state) { return 0; } 1030 static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev) 1031 { 1032 return ERR_PTR(-EOPNOTSUPP); 1033 } 1034 1035 static inline struct mlx5_esw_pf_info 1036 mlx5_esw_get_host_pf_info(struct mlx5_core_dev *dev, const u32 *out) 1037 { 1038 return (struct mlx5_esw_pf_info) {}; 1039 } 1040 1041 static inline struct mlx5_flow_handle * 1042 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag) 1043 { 1044 return ERR_PTR(-EOPNOTSUPP); 1045 } 1046 1047 static inline unsigned int 1048 mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev, 1049 u16 vport_num) 1050 { 1051 return vport_num; 1052 } 1053 1054 static inline int 1055 mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw, 1056 struct mlx5_eswitch *slave_esw, int max_slaves) 1057 { 1058 return 0; 1059 } 1060 1061 static inline void 1062 mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw, 1063 struct mlx5_eswitch *slave_esw) {} 1064 1065 static inline int 1066 mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw) 1067 { 1068 return 0; 1069 } 1070 1071 static inline void 1072 mlx5_eswitch_unload_reps(struct mlx5_eswitch *esw) {} 1073 1074 static inline bool 1075 mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb) 1076 { 1077 return true; 1078 } 1079 1080 static inline void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev) 1081 { 1082 } 1083 1084 static inline int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev) { return 0; } 1085 static inline void mlx5_eswitch_unblock_mode(struct mlx5_core_dev *dev) {} 1086 static inline bool mlx5_eswitch_block_ipsec(struct mlx5_core_dev *dev) 1087 { 1088 return false; 1089 } 1090 1091 static inline void mlx5_eswitch_unblock_ipsec(struct mlx5_core_dev *dev) {} 1092 1093 static inline bool 1094 mlx5_esw_host_functions_enabled(const struct mlx5_core_dev *dev) 1095 { 1096 return true; 1097 } 1098 1099 static inline void mlx5_esw_reps_block(struct mlx5_eswitch *esw) {} 1100 static inline void mlx5_esw_reps_unblock(struct mlx5_eswitch *esw) {} 1101 1102 static inline bool 1103 mlx5_esw_vport_vhca_id(struct mlx5_eswitch *esw, u16 vportn, u16 *vhca_id) 1104 { 1105 return false; 1106 } 1107 1108 static inline u16 1109 mlx5_esw_vhca_id_to_func_type(struct mlx5_core_dev *dev, u16 vhca_id) 1110 { 1111 return MLX5_FUNC_TYPE_NONE; 1112 } 1113 1114 static inline void 1115 mlx5_eswitch_safe_aux_devs_remove(struct mlx5_core_dev *dev) {} 1116 static inline struct mlx5_flow_handle * 1117 mlx5_esw_lag_demux_rule_create(struct mlx5_eswitch *esw, u16 vport_num, 1118 struct mlx5_flow_table *lag_ft) 1119 { 1120 return ERR_PTR(-EOPNOTSUPP); 1121 } 1122 1123 #endif /* CONFIG_MLX5_ESWITCH */ 1124 1125 #endif /* __MLX5_ESWITCH_H__ */ 1126