1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AD7293 driver 4 * 5 * Copyright 2021 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/iio/iio.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/module.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/spi/spi.h> 18 19 #include <linux/unaligned.h> 20 21 #define AD7293_R1B BIT(16) 22 #define AD7293_R2B BIT(17) 23 #define AD7293_PAGE_ADDR_MSK GENMASK(15, 8) 24 #define AD7293_PAGE(x) FIELD_PREP(AD7293_PAGE_ADDR_MSK, x) 25 26 /* AD7293 Register Map Common */ 27 #define AD7293_REG_NO_OP (AD7293_R1B | AD7293_PAGE(0x0) | 0x0) 28 #define AD7293_REG_PAGE_SELECT (AD7293_R1B | AD7293_PAGE(0x0) | 0x1) 29 #define AD7293_REG_CONV_CMD (AD7293_R2B | AD7293_PAGE(0x0) | 0x2) 30 #define AD7293_REG_RESULT (AD7293_R1B | AD7293_PAGE(0x0) | 0x3) 31 #define AD7293_REG_DAC_EN (AD7293_R1B | AD7293_PAGE(0x0) | 0x4) 32 #define AD7293_REG_DEVICE_ID (AD7293_R2B | AD7293_PAGE(0x0) | 0xC) 33 #define AD7293_REG_SOFT_RESET (AD7293_R2B | AD7293_PAGE(0x0) | 0xF) 34 35 /* AD7293 Register Map Page 0x0 */ 36 #define AD7293_REG_VIN0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x10) 37 #define AD7293_REG_VIN1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x11) 38 #define AD7293_REG_VIN2 (AD7293_R2B | AD7293_PAGE(0x0) | 0x12) 39 #define AD7293_REG_VIN3 (AD7293_R2B | AD7293_PAGE(0x0) | 0x13) 40 #define AD7293_REG_TSENSE_INT (AD7293_R2B | AD7293_PAGE(0x0) | 0x20) 41 #define AD7293_REG_TSENSE_D0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x21) 42 #define AD7293_REG_TSENSE_D1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x22) 43 #define AD7293_REG_ISENSE_0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x28) 44 #define AD7293_REG_ISENSE_1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x29) 45 #define AD7293_REG_ISENSE_2 (AD7293_R2B | AD7293_PAGE(0x0) | 0x2A) 46 #define AD7293_REG_ISENSE_3 (AD7293_R2B | AD7293_PAGE(0x0) | 0x2B) 47 #define AD7293_REG_UNI_VOUT0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x30) 48 #define AD7293_REG_UNI_VOUT1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x31) 49 #define AD7293_REG_UNI_VOUT2 (AD7293_R2B | AD7293_PAGE(0x0) | 0x32) 50 #define AD7293_REG_UNI_VOUT3 (AD7293_R2B | AD7293_PAGE(0x0) | 0x33) 51 #define AD7293_REG_BI_VOUT0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x34) 52 #define AD7293_REG_BI_VOUT1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x35) 53 #define AD7293_REG_BI_VOUT2 (AD7293_R2B | AD7293_PAGE(0x0) | 0x36) 54 #define AD7293_REG_BI_VOUT3 (AD7293_R2B | AD7293_PAGE(0x0) | 0x37) 55 56 /* AD7293 Register Map Page 0x2 */ 57 #define AD7293_REG_DIGITAL_OUT_EN (AD7293_R2B | AD7293_PAGE(0x2) | 0x11) 58 #define AD7293_REG_DIGITAL_INOUT_FUNC (AD7293_R2B | AD7293_PAGE(0x2) | 0x12) 59 #define AD7293_REG_DIGITAL_FUNC_POL (AD7293_R2B | AD7293_PAGE(0x2) | 0x13) 60 #define AD7293_REG_GENERAL (AD7293_R2B | AD7293_PAGE(0x2) | 0x14) 61 #define AD7293_REG_VINX_RANGE0 (AD7293_R2B | AD7293_PAGE(0x2) | 0x15) 62 #define AD7293_REG_VINX_RANGE1 (AD7293_R2B | AD7293_PAGE(0x2) | 0x16) 63 #define AD7293_REG_VINX_DIFF_SE (AD7293_R2B | AD7293_PAGE(0x2) | 0x17) 64 #define AD7293_REG_VINX_FILTER (AD7293_R2B | AD7293_PAGE(0x2) | 0x18) 65 #define AD7293_REG_BG_EN (AD7293_R2B | AD7293_PAGE(0x2) | 0x19) 66 #define AD7293_REG_CONV_DELAY (AD7293_R2B | AD7293_PAGE(0x2) | 0x1A) 67 #define AD7293_REG_TSENSE_BG_EN (AD7293_R2B | AD7293_PAGE(0x2) | 0x1B) 68 #define AD7293_REG_ISENSE_BG_EN (AD7293_R2B | AD7293_PAGE(0x2) | 0x1C) 69 #define AD7293_REG_ISENSE_GAIN (AD7293_R2B | AD7293_PAGE(0x2) | 0x1D) 70 #define AD7293_REG_DAC_SNOOZE_O (AD7293_R2B | AD7293_PAGE(0x2) | 0x1F) 71 #define AD7293_REG_DAC_SNOOZE_1 (AD7293_R2B | AD7293_PAGE(0x2) | 0x20) 72 #define AD7293_REG_RSX_MON_BG_EN (AD7293_R2B | AD7293_PAGE(0x2) | 0x23) 73 #define AD7293_REG_INTEGR_CL (AD7293_R2B | AD7293_PAGE(0x2) | 0x28) 74 #define AD7293_REG_PA_ON_CTRL (AD7293_R2B | AD7293_PAGE(0x2) | 0x29) 75 #define AD7293_REG_RAMP_TIME_0 (AD7293_R2B | AD7293_PAGE(0x2) | 0x2A) 76 #define AD7293_REG_RAMP_TIME_1 (AD7293_R2B | AD7293_PAGE(0x2) | 0x2B) 77 #define AD7293_REG_RAMP_TIME_2 (AD7293_R2B | AD7293_PAGE(0x2) | 0x2C) 78 #define AD7293_REG_RAMP_TIME_3 (AD7293_R2B | AD7293_PAGE(0x2) | 0x2D) 79 #define AD7293_REG_CL_FR_IT (AD7293_R2B | AD7293_PAGE(0x2) | 0x2E) 80 #define AD7293_REG_INTX_AVSS_AVDD (AD7293_R2B | AD7293_PAGE(0x2) | 0x2F) 81 82 /* AD7293 Register Map Page 0x3 */ 83 #define AD7293_REG_VINX_SEQ (AD7293_R2B | AD7293_PAGE(0x3) | 0x10) 84 #define AD7293_REG_ISENSEX_TSENSEX_SEQ (AD7293_R2B | AD7293_PAGE(0x3) | 0x11) 85 #define AD7293_REG_RSX_MON_BI_VOUTX_SEQ (AD7293_R2B | AD7293_PAGE(0x3) | 0x12) 86 87 /* AD7293 Register Map Page 0xE */ 88 #define AD7293_REG_VIN0_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x10) 89 #define AD7293_REG_VIN1_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x11) 90 #define AD7293_REG_VIN2_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x12) 91 #define AD7293_REG_VIN3_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x13) 92 #define AD7293_REG_TSENSE_INT_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x20) 93 #define AD7293_REG_TSENSE_D0_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x21) 94 #define AD7293_REG_TSENSE_D1_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x22) 95 #define AD7293_REG_ISENSE0_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x28) 96 #define AD7293_REG_ISENSE1_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x29) 97 #define AD7293_REG_ISENSE2_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x2A) 98 #define AD7293_REG_ISENSE3_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x2B) 99 #define AD7293_REG_UNI_VOUT0_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x30) 100 #define AD7293_REG_UNI_VOUT1_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x31) 101 #define AD7293_REG_UNI_VOUT2_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x32) 102 #define AD7293_REG_UNI_VOUT3_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x33) 103 #define AD7293_REG_BI_VOUT0_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x34) 104 #define AD7293_REG_BI_VOUT1_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x35) 105 #define AD7293_REG_BI_VOUT2_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x36) 106 #define AD7293_REG_BI_VOUT3_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x37) 107 108 /* AD7293 Miscellaneous Definitions */ 109 #define AD7293_READ BIT(7) 110 #define AD7293_TRANSF_LEN_MSK GENMASK(17, 16) 111 112 #define AD7293_REG_ADDR_MSK GENMASK(7, 0) 113 #define AD7293_REG_VOUT_OFFSET_MSK GENMASK(5, 4) 114 #define AD7293_REG_DATA_RAW_MSK GENMASK(15, 4) 115 #define AD7293_REG_VINX_RANGE_GET_CH_MSK(x, ch) (((x) >> (ch)) & 0x1) 116 #define AD7293_REG_VINX_RANGE_SET_CH_MSK(x, ch) (((x) & 0x1) << (ch)) 117 #define AD7293_CHIP_ID 0x18 118 119 enum ad7293_ch_type { 120 AD7293_ADC_VINX, 121 AD7293_ADC_TSENSE, 122 AD7293_ADC_ISENSE, 123 AD7293_DAC, 124 }; 125 126 enum ad7293_max_offset { 127 AD7293_TSENSE_MIN_OFFSET_CH = 4, 128 AD7293_ISENSE_MIN_OFFSET_CH = 7, 129 AD7293_VOUT_MIN_OFFSET_CH = 11, 130 AD7293_VOUT_MAX_OFFSET_CH = 18, 131 }; 132 133 static const int dac_offset_table[] = {0, 1, 2}; 134 135 static const int isense_gain_table[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}; 136 137 static const int adc_range_table[] = {0, 1, 2, 3}; 138 139 struct ad7293_state { 140 struct spi_device *spi; 141 /* Protect against concurrent accesses to the device, page selection and data content */ 142 struct mutex lock; 143 struct gpio_desc *gpio_reset; 144 u8 page_select; 145 u8 data[3] __aligned(IIO_DMA_MINALIGN); 146 }; 147 148 static int ad7293_page_select(struct ad7293_state *st, unsigned int reg) 149 { 150 int ret; 151 152 if (st->page_select != FIELD_GET(AD7293_PAGE_ADDR_MSK, reg)) { 153 st->data[0] = FIELD_GET(AD7293_REG_ADDR_MSK, AD7293_REG_PAGE_SELECT); 154 st->data[1] = FIELD_GET(AD7293_PAGE_ADDR_MSK, reg); 155 156 ret = spi_write(st->spi, &st->data[0], 2); 157 if (ret) 158 return ret; 159 160 st->page_select = FIELD_GET(AD7293_PAGE_ADDR_MSK, reg); 161 } 162 163 return 0; 164 } 165 166 static int __ad7293_spi_read(struct ad7293_state *st, unsigned int reg, 167 u16 *val) 168 { 169 int ret; 170 unsigned int length; 171 struct spi_transfer t = {0}; 172 173 length = FIELD_GET(AD7293_TRANSF_LEN_MSK, reg); 174 175 ret = ad7293_page_select(st, reg); 176 if (ret) 177 return ret; 178 179 st->data[0] = AD7293_READ | FIELD_GET(AD7293_REG_ADDR_MSK, reg); 180 st->data[1] = 0x0; 181 st->data[2] = 0x0; 182 183 t.tx_buf = &st->data[0]; 184 t.rx_buf = &st->data[0]; 185 t.len = length + 1; 186 187 ret = spi_sync_transfer(st->spi, &t, 1); 188 if (ret) 189 return ret; 190 191 if (length == 1) 192 *val = st->data[1]; 193 else 194 *val = get_unaligned_be16(&st->data[1]); 195 196 return 0; 197 } 198 199 static int ad7293_spi_read(struct ad7293_state *st, unsigned int reg, 200 u16 *val) 201 { 202 int ret; 203 204 mutex_lock(&st->lock); 205 ret = __ad7293_spi_read(st, reg, val); 206 mutex_unlock(&st->lock); 207 208 return ret; 209 } 210 211 static int __ad7293_spi_write(struct ad7293_state *st, unsigned int reg, 212 u16 val) 213 { 214 int ret; 215 unsigned int length; 216 217 length = FIELD_GET(AD7293_TRANSF_LEN_MSK, reg); 218 219 ret = ad7293_page_select(st, reg); 220 if (ret) 221 return ret; 222 223 st->data[0] = FIELD_GET(AD7293_REG_ADDR_MSK, reg); 224 225 if (length == 1) 226 st->data[1] = val; 227 else 228 put_unaligned_be16(val, &st->data[1]); 229 230 return spi_write(st->spi, &st->data[0], length + 1); 231 } 232 233 static int ad7293_spi_write(struct ad7293_state *st, unsigned int reg, 234 u16 val) 235 { 236 int ret; 237 238 mutex_lock(&st->lock); 239 ret = __ad7293_spi_write(st, reg, val); 240 mutex_unlock(&st->lock); 241 242 return ret; 243 } 244 245 static int __ad7293_spi_update_bits(struct ad7293_state *st, unsigned int reg, 246 u16 mask, u16 val) 247 { 248 int ret; 249 u16 data, temp; 250 251 ret = __ad7293_spi_read(st, reg, &data); 252 if (ret) 253 return ret; 254 255 temp = (data & ~mask) | (val & mask); 256 257 return __ad7293_spi_write(st, reg, temp); 258 } 259 260 static int ad7293_spi_update_bits(struct ad7293_state *st, unsigned int reg, 261 u16 mask, u16 val) 262 { 263 int ret; 264 265 mutex_lock(&st->lock); 266 ret = __ad7293_spi_update_bits(st, reg, mask, val); 267 mutex_unlock(&st->lock); 268 269 return ret; 270 } 271 272 static int ad7293_adc_get_scale(struct ad7293_state *st, unsigned int ch, 273 u16 *range) 274 { 275 int ret; 276 u16 data; 277 278 mutex_lock(&st->lock); 279 280 ret = __ad7293_spi_read(st, AD7293_REG_VINX_RANGE1, &data); 281 if (ret) 282 goto exit; 283 284 *range = AD7293_REG_VINX_RANGE_GET_CH_MSK(data, ch); 285 286 ret = __ad7293_spi_read(st, AD7293_REG_VINX_RANGE0, &data); 287 if (ret) 288 goto exit; 289 290 *range |= AD7293_REG_VINX_RANGE_GET_CH_MSK(data, ch) << 1; 291 292 exit: 293 mutex_unlock(&st->lock); 294 295 return ret; 296 } 297 298 static int ad7293_adc_set_scale(struct ad7293_state *st, unsigned int ch, 299 u16 range) 300 { 301 int ret; 302 unsigned int ch_msk = BIT(ch); 303 304 mutex_lock(&st->lock); 305 ret = __ad7293_spi_update_bits(st, AD7293_REG_VINX_RANGE1, ch_msk, 306 AD7293_REG_VINX_RANGE_SET_CH_MSK(range, ch)); 307 if (ret) 308 goto exit; 309 310 ret = __ad7293_spi_update_bits(st, AD7293_REG_VINX_RANGE0, ch_msk, 311 AD7293_REG_VINX_RANGE_SET_CH_MSK((range >> 1), ch)); 312 313 exit: 314 mutex_unlock(&st->lock); 315 316 return ret; 317 } 318 319 static int ad7293_get_offset(struct ad7293_state *st, unsigned int ch, 320 u16 *offset) 321 { 322 if (ch < AD7293_TSENSE_MIN_OFFSET_CH) 323 return ad7293_spi_read(st, AD7293_REG_VIN0_OFFSET + ch, offset); 324 else if (ch < AD7293_ISENSE_MIN_OFFSET_CH) 325 return ad7293_spi_read(st, AD7293_REG_TSENSE_INT_OFFSET + (ch - 4), offset); 326 else if (ch < AD7293_VOUT_MIN_OFFSET_CH) 327 return ad7293_spi_read(st, AD7293_REG_ISENSE0_OFFSET + (ch - 7), offset); 328 else if (ch <= AD7293_VOUT_MAX_OFFSET_CH) 329 return ad7293_spi_read(st, AD7293_REG_UNI_VOUT0_OFFSET + (ch - 11), offset); 330 331 return -EINVAL; 332 } 333 334 static int ad7293_set_offset(struct ad7293_state *st, unsigned int ch, 335 u16 offset) 336 { 337 if (ch < AD7293_TSENSE_MIN_OFFSET_CH) 338 return ad7293_spi_write(st, AD7293_REG_VIN0_OFFSET + ch, 339 offset); 340 else if (ch < AD7293_ISENSE_MIN_OFFSET_CH) 341 return ad7293_spi_write(st, 342 AD7293_REG_TSENSE_INT_OFFSET + 343 (ch - AD7293_TSENSE_MIN_OFFSET_CH), 344 offset); 345 else if (ch < AD7293_VOUT_MIN_OFFSET_CH) 346 return ad7293_spi_write(st, 347 AD7293_REG_ISENSE0_OFFSET + 348 (ch - AD7293_ISENSE_MIN_OFFSET_CH), 349 offset); 350 else if (ch <= AD7293_VOUT_MAX_OFFSET_CH) 351 return ad7293_spi_update_bits(st, 352 AD7293_REG_UNI_VOUT0_OFFSET + 353 (ch - AD7293_VOUT_MIN_OFFSET_CH), 354 AD7293_REG_VOUT_OFFSET_MSK, 355 FIELD_PREP(AD7293_REG_VOUT_OFFSET_MSK, offset)); 356 357 return -EINVAL; 358 } 359 360 static int ad7293_isense_set_scale(struct ad7293_state *st, unsigned int ch, 361 u16 gain) 362 { 363 unsigned int ch_msk = (0xf << (4 * ch)); 364 365 return ad7293_spi_update_bits(st, AD7293_REG_ISENSE_GAIN, ch_msk, 366 gain << (4 * ch)); 367 } 368 369 static int ad7293_isense_get_scale(struct ad7293_state *st, unsigned int ch, 370 u16 *gain) 371 { 372 int ret; 373 374 ret = ad7293_spi_read(st, AD7293_REG_ISENSE_GAIN, gain); 375 if (ret) 376 return ret; 377 378 *gain = (*gain >> (4 * ch)) & 0xf; 379 380 return ret; 381 } 382 383 static int ad7293_dac_write_raw(struct ad7293_state *st, unsigned int ch, 384 u16 raw) 385 { 386 int ret; 387 388 mutex_lock(&st->lock); 389 390 ret = __ad7293_spi_update_bits(st, AD7293_REG_DAC_EN, BIT(ch), BIT(ch)); 391 if (ret) 392 goto exit; 393 394 ret = __ad7293_spi_write(st, AD7293_REG_UNI_VOUT0 + ch, 395 FIELD_PREP(AD7293_REG_DATA_RAW_MSK, raw)); 396 397 exit: 398 mutex_unlock(&st->lock); 399 400 return ret; 401 } 402 403 static int ad7293_ch_read_raw(struct ad7293_state *st, enum ad7293_ch_type type, 404 unsigned int ch, u16 *raw) 405 { 406 int ret; 407 unsigned int reg_wr, reg_rd, data_wr; 408 409 switch (type) { 410 case AD7293_ADC_VINX: 411 reg_wr = AD7293_REG_VINX_SEQ; 412 reg_rd = AD7293_REG_VIN0 + ch; 413 data_wr = BIT(ch); 414 415 break; 416 case AD7293_ADC_TSENSE: 417 reg_wr = AD7293_REG_ISENSEX_TSENSEX_SEQ; 418 reg_rd = AD7293_REG_TSENSE_INT + ch; 419 data_wr = BIT(ch); 420 421 break; 422 case AD7293_ADC_ISENSE: 423 reg_wr = AD7293_REG_ISENSEX_TSENSEX_SEQ; 424 reg_rd = AD7293_REG_ISENSE_0 + ch; 425 data_wr = BIT(ch) << 8; 426 427 break; 428 case AD7293_DAC: 429 reg_rd = AD7293_REG_UNI_VOUT0 + ch; 430 431 break; 432 default: 433 return -EINVAL; 434 } 435 436 mutex_lock(&st->lock); 437 438 if (type != AD7293_DAC) { 439 if (type == AD7293_ADC_TSENSE) { 440 ret = __ad7293_spi_write(st, AD7293_REG_TSENSE_BG_EN, 441 BIT(ch)); 442 if (ret) 443 goto exit; 444 445 usleep_range(9000, 9900); 446 } else if (type == AD7293_ADC_ISENSE) { 447 ret = __ad7293_spi_write(st, AD7293_REG_ISENSE_BG_EN, 448 BIT(ch)); 449 if (ret) 450 goto exit; 451 452 usleep_range(2000, 7000); 453 } 454 455 ret = __ad7293_spi_write(st, reg_wr, data_wr); 456 if (ret) 457 goto exit; 458 459 ret = __ad7293_spi_write(st, AD7293_REG_CONV_CMD, 0x82); 460 if (ret) 461 goto exit; 462 } 463 464 ret = __ad7293_spi_read(st, reg_rd, raw); 465 466 *raw = FIELD_GET(AD7293_REG_DATA_RAW_MSK, *raw); 467 468 exit: 469 mutex_unlock(&st->lock); 470 471 return ret; 472 } 473 474 static int ad7293_read_raw(struct iio_dev *indio_dev, 475 struct iio_chan_spec const *chan, 476 int *val, int *val2, long info) 477 { 478 struct ad7293_state *st = iio_priv(indio_dev); 479 int ret; 480 u16 data; 481 482 switch (info) { 483 case IIO_CHAN_INFO_RAW: 484 switch (chan->type) { 485 case IIO_VOLTAGE: 486 if (chan->output) 487 ret = ad7293_ch_read_raw(st, AD7293_DAC, 488 chan->channel, &data); 489 else 490 ret = ad7293_ch_read_raw(st, AD7293_ADC_VINX, 491 chan->channel, &data); 492 493 break; 494 case IIO_CURRENT: 495 ret = ad7293_ch_read_raw(st, AD7293_ADC_ISENSE, 496 chan->channel, &data); 497 498 break; 499 case IIO_TEMP: 500 ret = ad7293_ch_read_raw(st, AD7293_ADC_TSENSE, 501 chan->channel, &data); 502 503 break; 504 default: 505 return -EINVAL; 506 } 507 508 if (ret) 509 return ret; 510 511 *val = data; 512 513 return IIO_VAL_INT; 514 case IIO_CHAN_INFO_OFFSET: 515 switch (chan->type) { 516 case IIO_VOLTAGE: 517 if (chan->output) { 518 ret = ad7293_get_offset(st, 519 chan->channel + AD7293_VOUT_MIN_OFFSET_CH, 520 &data); 521 522 data = FIELD_GET(AD7293_REG_VOUT_OFFSET_MSK, data); 523 } else { 524 ret = ad7293_get_offset(st, chan->channel, &data); 525 } 526 527 break; 528 case IIO_CURRENT: 529 ret = ad7293_get_offset(st, 530 chan->channel + AD7293_ISENSE_MIN_OFFSET_CH, 531 &data); 532 533 break; 534 case IIO_TEMP: 535 ret = ad7293_get_offset(st, 536 chan->channel + AD7293_TSENSE_MIN_OFFSET_CH, 537 &data); 538 539 break; 540 default: 541 return -EINVAL; 542 } 543 if (ret) 544 return ret; 545 546 *val = data; 547 548 return IIO_VAL_INT; 549 case IIO_CHAN_INFO_SCALE: 550 switch (chan->type) { 551 case IIO_VOLTAGE: 552 ret = ad7293_adc_get_scale(st, chan->channel, &data); 553 if (ret) 554 return ret; 555 556 *val = data; 557 558 return IIO_VAL_INT; 559 case IIO_CURRENT: 560 ret = ad7293_isense_get_scale(st, chan->channel, &data); 561 if (ret) 562 return ret; 563 564 *val = data; 565 566 return IIO_VAL_INT; 567 case IIO_TEMP: 568 *val = 1; 569 *val2 = 8; 570 571 return IIO_VAL_FRACTIONAL; 572 default: 573 return -EINVAL; 574 } 575 default: 576 return -EINVAL; 577 } 578 } 579 580 static int ad7293_write_raw(struct iio_dev *indio_dev, 581 struct iio_chan_spec const *chan, 582 int val, int val2, long info) 583 { 584 struct ad7293_state *st = iio_priv(indio_dev); 585 586 switch (info) { 587 case IIO_CHAN_INFO_RAW: 588 switch (chan->type) { 589 case IIO_VOLTAGE: 590 if (!chan->output) 591 return -EINVAL; 592 593 return ad7293_dac_write_raw(st, chan->channel, val); 594 default: 595 return -EINVAL; 596 } 597 case IIO_CHAN_INFO_OFFSET: 598 switch (chan->type) { 599 case IIO_VOLTAGE: 600 if (chan->output) 601 return ad7293_set_offset(st, 602 chan->channel + 603 AD7293_VOUT_MIN_OFFSET_CH, 604 val); 605 else 606 return ad7293_set_offset(st, chan->channel, val); 607 case IIO_CURRENT: 608 return ad7293_set_offset(st, 609 chan->channel + 610 AD7293_ISENSE_MIN_OFFSET_CH, 611 val); 612 case IIO_TEMP: 613 return ad7293_set_offset(st, 614 chan->channel + 615 AD7293_TSENSE_MIN_OFFSET_CH, 616 val); 617 default: 618 return -EINVAL; 619 } 620 case IIO_CHAN_INFO_SCALE: 621 switch (chan->type) { 622 case IIO_VOLTAGE: 623 return ad7293_adc_set_scale(st, chan->channel, val); 624 case IIO_CURRENT: 625 return ad7293_isense_set_scale(st, chan->channel, val); 626 default: 627 return -EINVAL; 628 } 629 default: 630 return -EINVAL; 631 } 632 } 633 634 static int ad7293_reg_access(struct iio_dev *indio_dev, 635 unsigned int reg, 636 unsigned int write_val, 637 unsigned int *read_val) 638 { 639 struct ad7293_state *st = iio_priv(indio_dev); 640 int ret; 641 642 if (read_val) { 643 u16 temp; 644 ret = ad7293_spi_read(st, reg, &temp); 645 *read_val = temp; 646 } else { 647 ret = ad7293_spi_write(st, reg, (u16)write_val); 648 } 649 650 return ret; 651 } 652 653 static int ad7293_read_avail(struct iio_dev *indio_dev, 654 struct iio_chan_spec const *chan, 655 const int **vals, int *type, int *length, 656 long info) 657 { 658 switch (info) { 659 case IIO_CHAN_INFO_OFFSET: 660 *vals = dac_offset_table; 661 *type = IIO_VAL_INT; 662 *length = ARRAY_SIZE(dac_offset_table); 663 664 return IIO_AVAIL_LIST; 665 case IIO_CHAN_INFO_SCALE: 666 *type = IIO_VAL_INT; 667 668 switch (chan->type) { 669 case IIO_VOLTAGE: 670 *vals = adc_range_table; 671 *length = ARRAY_SIZE(adc_range_table); 672 return IIO_AVAIL_LIST; 673 case IIO_CURRENT: 674 *vals = isense_gain_table; 675 *length = ARRAY_SIZE(isense_gain_table); 676 return IIO_AVAIL_LIST; 677 default: 678 return -EINVAL; 679 } 680 default: 681 return -EINVAL; 682 } 683 } 684 685 #define AD7293_CHAN_ADC(_channel) { \ 686 .type = IIO_VOLTAGE, \ 687 .output = 0, \ 688 .indexed = 1, \ 689 .channel = _channel, \ 690 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 691 BIT(IIO_CHAN_INFO_SCALE) | \ 692 BIT(IIO_CHAN_INFO_OFFSET), \ 693 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) \ 694 } 695 696 #define AD7293_CHAN_DAC(_channel) { \ 697 .type = IIO_VOLTAGE, \ 698 .output = 1, \ 699 .indexed = 1, \ 700 .channel = _channel, \ 701 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 702 BIT(IIO_CHAN_INFO_OFFSET), \ 703 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OFFSET) \ 704 } 705 706 #define AD7293_CHAN_ISENSE(_channel) { \ 707 .type = IIO_CURRENT, \ 708 .output = 0, \ 709 .indexed = 1, \ 710 .channel = _channel, \ 711 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 712 BIT(IIO_CHAN_INFO_OFFSET) | \ 713 BIT(IIO_CHAN_INFO_SCALE), \ 714 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) \ 715 } 716 717 #define AD7293_CHAN_TEMP(_channel) { \ 718 .type = IIO_TEMP, \ 719 .output = 0, \ 720 .indexed = 1, \ 721 .channel = _channel, \ 722 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 723 BIT(IIO_CHAN_INFO_OFFSET), \ 724 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ 725 } 726 727 static const struct iio_chan_spec ad7293_channels[] = { 728 AD7293_CHAN_ADC(0), 729 AD7293_CHAN_ADC(1), 730 AD7293_CHAN_ADC(2), 731 AD7293_CHAN_ADC(3), 732 AD7293_CHAN_ISENSE(0), 733 AD7293_CHAN_ISENSE(1), 734 AD7293_CHAN_ISENSE(2), 735 AD7293_CHAN_ISENSE(3), 736 AD7293_CHAN_TEMP(0), 737 AD7293_CHAN_TEMP(1), 738 AD7293_CHAN_TEMP(2), 739 AD7293_CHAN_DAC(0), 740 AD7293_CHAN_DAC(1), 741 AD7293_CHAN_DAC(2), 742 AD7293_CHAN_DAC(3), 743 AD7293_CHAN_DAC(4), 744 AD7293_CHAN_DAC(5), 745 AD7293_CHAN_DAC(6), 746 AD7293_CHAN_DAC(7) 747 }; 748 749 static int ad7293_soft_reset(struct ad7293_state *st) 750 { 751 int ret; 752 753 ret = __ad7293_spi_write(st, AD7293_REG_SOFT_RESET, 0x7293); 754 if (ret) 755 return ret; 756 757 return __ad7293_spi_write(st, AD7293_REG_SOFT_RESET, 0x0000); 758 } 759 760 static int ad7293_reset(struct ad7293_state *st) 761 { 762 if (st->gpio_reset) { 763 gpiod_set_value(st->gpio_reset, 0); 764 usleep_range(100, 1000); 765 gpiod_set_value(st->gpio_reset, 1); 766 usleep_range(100, 1000); 767 768 return 0; 769 } 770 771 /* Perform a software reset */ 772 return ad7293_soft_reset(st); 773 } 774 775 static int ad7293_properties_parse(struct ad7293_state *st) 776 { 777 struct spi_device *spi = st->spi; 778 int ret; 779 780 ret = devm_regulator_get_enable(&spi->dev, "avdd"); 781 if (ret) 782 return dev_err_probe(&spi->dev, ret, "failed to enable AVDD\n"); 783 784 ret = devm_regulator_get_enable(&spi->dev, "vdrive"); 785 if (ret) 786 return dev_err_probe(&spi->dev, ret, "failed to enable VDRIVE\n"); 787 788 st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset", 789 GPIOD_OUT_HIGH); 790 if (IS_ERR(st->gpio_reset)) 791 return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_reset), 792 "failed to get the reset GPIO\n"); 793 794 return 0; 795 } 796 797 static int ad7293_init(struct ad7293_state *st) 798 { 799 int ret; 800 u16 chip_id; 801 struct spi_device *spi = st->spi; 802 803 ret = ad7293_properties_parse(st); 804 if (ret) 805 return ret; 806 807 ret = ad7293_reset(st); 808 if (ret) 809 return ret; 810 811 /* Check Chip ID */ 812 ret = __ad7293_spi_read(st, AD7293_REG_DEVICE_ID, &chip_id); 813 if (ret) 814 return ret; 815 816 if (chip_id != AD7293_CHIP_ID) { 817 dev_err(&spi->dev, "Invalid Chip ID.\n"); 818 return -EINVAL; 819 } 820 821 return 0; 822 } 823 824 static const struct iio_info ad7293_info = { 825 .read_raw = ad7293_read_raw, 826 .write_raw = ad7293_write_raw, 827 .read_avail = &ad7293_read_avail, 828 .debugfs_reg_access = &ad7293_reg_access, 829 }; 830 831 static int ad7293_probe(struct spi_device *spi) 832 { 833 struct iio_dev *indio_dev; 834 struct ad7293_state *st; 835 int ret; 836 837 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 838 if (!indio_dev) 839 return -ENOMEM; 840 841 st = iio_priv(indio_dev); 842 843 indio_dev->info = &ad7293_info; 844 indio_dev->name = "ad7293"; 845 indio_dev->channels = ad7293_channels; 846 indio_dev->num_channels = ARRAY_SIZE(ad7293_channels); 847 848 st->spi = spi; 849 st->page_select = 0; 850 851 mutex_init(&st->lock); 852 853 ret = ad7293_init(st); 854 if (ret) 855 return ret; 856 857 return devm_iio_device_register(&spi->dev, indio_dev); 858 } 859 860 static const struct spi_device_id ad7293_id[] = { 861 { "ad7293", 0 }, 862 {} 863 }; 864 MODULE_DEVICE_TABLE(spi, ad7293_id); 865 866 static const struct of_device_id ad7293_of_match[] = { 867 { .compatible = "adi,ad7293" }, 868 {} 869 }; 870 MODULE_DEVICE_TABLE(of, ad7293_of_match); 871 872 static struct spi_driver ad7293_driver = { 873 .driver = { 874 .name = "ad7293", 875 .of_match_table = ad7293_of_match, 876 }, 877 .probe = ad7293_probe, 878 .id_table = ad7293_id, 879 }; 880 module_spi_driver(ad7293_driver); 881 882 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com"); 883 MODULE_DESCRIPTION("Analog Devices AD7293"); 884 MODULE_LICENSE("GPL v2"); 885