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Searched defs:reg (Results 1 – 25 of 436) sorted by relevance

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/titanic_51/usr/src/uts/common/io/
H A Dvgasubr.c79 vga_get_hardware_settings(struct vgaregmap *reg, int *width, int *height) in vga_get_hardware_settings() argument
86 #define PUTB(reg, off, v) ddi_put8(reg->handle, reg->addr + (off), v) argument
87 #define GETB(reg, off) ddi_get8(reg->handle, reg argument
90 vga_get_reg(struct vgaregmap * reg,int indexreg) vga_get_reg() argument
96 vga_set_reg(struct vgaregmap * reg,int indexreg,int v) vga_set_reg() argument
102 vga_get_crtc(struct vgaregmap * reg,int i) vga_get_crtc() argument
108 vga_set_crtc(struct vgaregmap * reg,int i,int v) vga_set_crtc() argument
114 vga_get_seq(struct vgaregmap * reg,int i) vga_get_seq() argument
120 vga_set_seq(struct vgaregmap * reg,int i,int v) vga_set_seq() argument
126 vga_get_grc(struct vgaregmap * reg,int i) vga_get_grc() argument
132 vga_set_grc(struct vgaregmap * reg,int i,int v) vga_set_grc() argument
138 vga_get_atr(struct vgaregmap * reg,int i) vga_get_atr() argument
153 vga_set_atr(struct vgaregmap * reg,int i,int v) vga_set_atr() argument
165 vga_set_indexed(struct vgaregmap * reg,int indexreg,int datareg,unsigned char index,unsigned char val) vga_set_indexed() argument
177 vga_get_indexed(struct vgaregmap * reg,int indexreg,int datareg,unsigned char index) vga_get_indexed() argument
193 vga_put_cmap(struct vgaregmap * reg,int index,unsigned char r,unsigned char g,unsigned char b) vga_put_cmap() argument
208 vga_get_cmap(struct vgaregmap * reg,int index,unsigned char * r,unsigned char * g,unsigned char * b) vga_get_cmap() argument
223 vga_dump_regs(struct vgaregmap * reg,int maxseq,int maxcrtc,int maxatr,int maxgrc) vga_dump_regs() argument
[all...]
/titanic_51/usr/src/uts/common/io/cxgbe/t4nex/
H A Dadapter.c26 t4_read_reg(struct adapter *sc, uint32_t reg) in t4_read_reg() argument
33 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) in t4_write_reg() argument
40 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) in t4_os_pci_read_cfg1() argument
46 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) in t4_os_pci_write_cfg1() argument
52 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) in t4_os_pci_read_cfg2() argument
58 t4_os_pci_write_cfg2(struct adapter * sc,int reg,uint16_t val) t4_os_pci_write_cfg2() argument
64 t4_os_pci_read_cfg4(struct adapter * sc,int reg,uint32_t * val) t4_os_pci_read_cfg4() argument
70 t4_os_pci_write_cfg4(struct adapter * sc,int reg,uint32_t val) t4_os_pci_write_cfg4() argument
76 t4_read_reg64(struct adapter * sc,uint32_t reg) t4_read_reg64() argument
83 t4_write_reg64(struct adapter * sc,uint32_t reg,uint64_t val) t4_write_reg64() argument
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/titanic_51/usr/src/uts/common/io/i40e/
H A Di40e_intr.c213 uint32_t reg; in i40e_intr_adminq_enable() local
226 uint32_t reg; in i40e_intr_adminq_disable() local
242 uint32_t reg; in i40e_intr_io_enable() local
255 uint32_t reg; in i40e_intr_io_disable() local
278 uint32_t reg; i40e_intr_io_enable_all() local
306 uint32_t reg; i40e_intr_io_disable_all() local
333 uint32_t reg; i40e_intr_io_clear_cause() local
340 uint32_t reg; i40e_intr_io_clear_cause() local
357 uint32_t reg; i40e_intr_chip_fini() local
387 uint32_t reg; i40e_set_lnklstn() local
406 uint32_t reg; i40e_set_rqctl() local
428 uint32_t reg; i40e_set_tqctl() local
495 uint32_t reg; i40e_intr_init_queue_shared() local
529 uint32_t reg; i40e_intr_rx_queue_enable() local
550 uint32_t reg; i40e_intr_rx_queue_disable() local
573 uint32_t reg; i40e_intr_chip_init() local
701 uint32_t reg; i40e_intr_other_work() local
777 uint32_t reg; i40e_intr_notx() local
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/titanic_51/usr/src/uts/intel/io/intel_nhm/
H A Dintel_nhm.h62 #define MC_SCRUB_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, \ argument
65 #define MC_SSR_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, 0x48, \ argument
102 #define MC_CONTROL_CHANNEL_ACTIVE(reg, channel) \ argument
104 #define MC_CONTROL_ECCEN(reg) (((reg) >> 1) & 1) argument
105 #define MC_CONTROL_CLOSED_PAGE(reg) ((reg) argument
106 MC_CONTROL_DIVBY3(reg) global() argument
113 CHANNEL_DISABLED(reg,channel) global() argument
126 RANKOFFSET(reg) global() argument
127 DIMMPRESENT(reg) global() argument
128 NUMBANK(reg) global() argument
129 NUMRANK(reg) global() argument
130 NUMROW(reg) global() argument
131 NUMCOL(reg) global() argument
133 DIMMSIZE(reg) global() argument
139 DIVBY3(reg) global() argument
140 REMOVE_6(reg) global() argument
141 REMOVE_7(reg) global() argument
142 REMOVE_8(reg) global() argument
143 CH_ADDRESS_OFFSET(reg) global() argument
145 CH_ADDRESS_SOFFSET(reg) global() argument
158 RIR_LIMIT(reg) global() argument
162 RIR_OFFSET(reg) global() argument
163 RIR_SOFFSET(reg) global() argument
165 RIR_DIMM_RANK(reg) global() argument
166 RIR_RANK(reg) global() argument
167 RIR_DIMM(reg) global() argument
182 RAS_LOCKSTEP_ENABLE(reg) global() argument
183 RAS_MIRROR_MEM_ENABLE(reg) global() argument
187 REDUNDANCY_LOSS(reg) global() argument
191 SPAREING_IN_PROGRESS(reg) global() argument
192 SPAREING_COMPLETE(reg) global() argument
197 SSR_MODE(reg) global() argument
209 MAX_DIMM_CLK_RATIO(reg) global() argument
311 CHANNEL_MAP(reg,channel,write) global() argument
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H A Dnhm_pci_cfg.c45 pci_regspec_t reg; in nhm_pci_cfg_setup() local
108 nhm_pci_getb(int bus,int dev,int func,int reg,int * interpose) nhm_pci_getb() argument
117 nhm_pci_getw(int bus,int dev,int func,int reg,int * interpose) nhm_pci_getw() argument
126 nhm_pci_getl(int bus,int dev,int func,int reg,int * interpose) nhm_pci_getl() argument
135 nhm_pci_putb(int bus,int dev,int func,int reg,uint8_t val) nhm_pci_putb() argument
144 nhm_pci_putw(int bus,int dev,int func,int reg,uint16_t val) nhm_pci_putw() argument
153 nhm_pci_putl(int bus,int dev,int func,int reg,uint32_t val) nhm_pci_putl() argument
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/titanic_51/usr/src/uts/sun4/brand/common/
H A Dbrand_solaris.s59 #define GLOBALS_SWAP(reg) \ argument
67 #define GLOBALS_RESTORE(reg) \ argument
72 #define GLOBALS_SWAP(reg) \ argument
80 #define GLOBALS_RESTORE(reg) \ argument
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/titanic_51/usr/src/uts/i86pc/os/
H A Dpci_mech1.c48 pci_mech1_getb(int bus, int device, int function, int reg) in pci_mech1_getb() argument
64 pci_mech1_getw(int bus, int device, int function, int reg) in pci_mech1_getw() argument
81 pci_mech1_getl(int bus, int device, int function, int reg) in pci_mech1_getl() argument
98 pci_mech1_putb(int bus, int device, int function, int reg, uint8_ argument
112 pci_mech1_putw(int bus,int device,int function,int reg,uint16_t val) pci_mech1_putw() argument
126 pci_mech1_putl(int bus,int device,int function,int reg,uint32_t val) pci_mech1_putl() argument
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H A Dpci_neptune.c140 pci_neptune_getb(int bus, int device, int function, int reg) in pci_neptune_getb() argument
153 pci_neptune_getw(int bus, int device, int function, int reg) in pci_neptune_getw() argument
166 pci_neptune_getl(int bus, int device, int function, int reg) in pci_neptune_getl() argument
179 pci_neptune_putb(int bus, int device, int function, int reg, uint8_t val) in pci_neptune_putb() argument
189 pci_neptune_putw(int bus, int device, int function, int reg, uint16_t val) in pci_neptune_putw() argument
199 pci_neptune_putl(int bus,int device,int function,int reg,uint32_t val) pci_neptune_putl() argument
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H A Dpci_mech1_amd.c95 pci_mech1_amd_getb(int bus, int device, int function, int reg) in pci_mech1_amd_getb() argument
112 pci_mech1_amd_getw(int bus, int device, int function, int reg) in pci_mech1_amd_getw() argument
129 pci_mech1_amd_getl(int bus, int device, int function, int reg) in pci_mech1_amd_getl() argument
146 pci_mech1_amd_putb(int bus, int device, int function, int reg, uint8_ argument
160 pci_mech1_amd_putw(int bus,int device,int function,int reg,uint16_t val) pci_mech1_amd_putw() argument
174 pci_mech1_amd_putl(int bus,int device,int function,int reg,uint32_t val) pci_mech1_amd_putl() argument
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H A Dpci_mech2.c73 pci_mech2_getb(int bus, int device, int function, int reg) in pci_mech2_getb() argument
89 pci_mech2_getw(int bus, int device, int function, int reg) in pci_mech2_getw() argument
105 pci_mech2_getl(int bus, int device, int function, int reg) in pci_mech2_getl() argument
121 pci_mech2_putb(int bus, int device, int function, int reg, uint8_t val) in pci_mech2_putb() argument
134 pci_mech2_putw(int bus, int device, int function, int reg, uint16_t val) in pci_mech2_putw() argument
147 pci_mech2_putl(int bus,int device,int function,int reg,uint32_t val) pci_mech2_putl() argument
[all...]
H A Dpci_orion.c181 pci_orion_getb(int bus, int device, int function, int reg) in pci_orion_getb() argument
194 pci_orion_getw(int bus, int device, int function, int reg) in pci_orion_getw() argument
207 pci_orion_getl(int bus, int device, int function, int reg) in pci_orion_getl() argument
220 pci_orion_putb(int bus, int device, int function, int reg, uint8_t val) in pci_orion_putb() argument
230 pci_orion_putw(int bus, int device, int function, int reg, uint16_t val) in pci_orion_putw() argument
240 pci_orion_putl(int bus,int device,int function,int reg,uint32_t val) pci_orion_putl() argument
[all...]
/titanic_51/usr/src/uts/common/io/atge/
H A Datge_mii.c64 atge_mii_read(void *arg, uint8_t phy, uint8_t reg) in atge_mii_read() argument
107 atge_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val) in atge_mii_write() argument
187 uint16_t reg, p in atge_l1_mii_reset() local
272 uint16_t reg; atge_l1c_mii_reset() local
350 atge_l1c_mii_read(void * arg,uint8_t phy,uint8_t reg) atge_l1c_mii_read() argument
362 atge_l1c_mii_write(void * arg,uint8_t phy,uint8_t reg,uint16_t val) atge_l1c_mii_write() argument
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/titanic_51/usr/src/uts/intel/io/intel_nb5000/
H A Dnb_pci_cfg.c49 pci_regspec_t reg; in nb_pci_cfg_setup() local
149 nb_pci_getb(int bus,int dev,int func,int reg,int * interpose) nb_pci_getb() argument
158 nb_pci_getw(int bus,int dev,int func,int reg,int * interpose) nb_pci_getw() argument
167 nb_pci_getl(int bus,int dev,int func,int reg,int * interpose) nb_pci_getl() argument
176 nb_pci_putb(int bus,int dev,int func,int reg,uint8_t val) nb_pci_putb() argument
185 nb_pci_putw(int bus,int dev,int func,int reg,uint16_t val) nb_pci_putw() argument
194 nb_pci_putl(int bus,int dev,int func,int reg,uint32_t val) nb_pci_putl() argument
[all...]
/titanic_51/usr/src/uts/common/io/e1000g/
H A De1000g_osdep.c46 e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) in e1000_write_pci_cfg() argument
52 e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) in e1000_read_pci_cfg() argument
69 uint16_t reg; /* register contents */ in phy_spd_state() local
109 e1000_read_pcie_cap_reg(struct e1000_hw * hw,uint32_t reg,uint16_t * value) e1000_read_pcie_cap_reg() argument
123 e1000_write_pcie_cap_reg(struct e1000_hw * hw,uint32_t reg,uint16_t * value) e1000_write_pcie_cap_reg() argument
[all...]
H A De1000_osdep.h123 #define E1000_WRITE_REG(hw, reg, value) \ argument
136 #define E1000_READ_REG(hw, reg) (\ argument
144 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ argument
158 #define E1000_READ_REG_ARRAY(hw, reg, offse argument
169 E1000_WRITE_REG_ARRAY_DWORD(a,reg,offset,value) global() argument
171 E1000_READ_REG_ARRAY_DWORD(a,reg,offset) global() argument
175 E1000_READ_FLASH_REG(hw,reg) global() argument
179 E1000_READ_FLASH_REG16(hw,reg) global() argument
183 E1000_WRITE_FLASH_REG(hw,reg,value) global() argument
187 E1000_WRITE_FLASH_REG16(hw,reg,value) global() argument
233 E1000_WRITE_REG_IO(a,reg,val) global() argument
[all...]
/titanic_51/usr/src/uts/common/io/igb/
H A De1000_osdep.h113 #define E1000_WRITE_REG(hw, reg, value) \ argument
117 #define E1000_READ_REG(hw, reg) \ argument
121 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ argument
126 #define E1000_READ_REG_ARRAY(hw, reg, offset) \ argument
130 #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) \ argument
132 E1000_READ_REG_ARRAY_DWORD(a,reg,offset) global() argument
136 E1000_READ_FLASH_REG(hw,reg) global() argument
140 E1000_READ_FLASH_REG16(hw,reg) global() argument
144 E1000_WRITE_FLASH_REG(hw,reg,value) global() argument
148 E1000_WRITE_FLASH_REG16(hw,reg,value) global() argument
200 E1000_WRITE_REG_IO(a,reg,val) global() argument
[all...]
H A Digb_osdep.c49 e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) in e1000_write_pci_cfg() argument
55 e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) in e1000_read_pci_cfg() argument
67 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) in e1000_read_pcie_cap_reg() argument
91 e1000_write_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) in e1000_write_pcie_cap_reg() argument
[all...]
/titanic_51/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_dcb_82599.c121 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599() local
179 u32 reg, max_credits; ixgbe_dcb_config_tx_desc_arbiter_82599() local
225 u32 reg; ixgbe_dcb_config_tx_data_arbiter_82599() local
285 u32 i, j, fcrtl, reg; ixgbe_dcb_config_pfc_82599() local
372 u32 reg = 0; ixgbe_dcb_config_tc_stats_82599() local
498 u32 reg; ixgbe_dcb_config_82599() local
[all...]
H A Dixgbe_dcb_82598.c121 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local
177 u32 reg, max_credits; ixgbe_dcb_config_tx_desc_arbiter_82598() local
221 u32 reg; ixgbe_dcb_config_tx_data_arbiter_82598() local
264 u32 fcrtl, reg; ixgbe_dcb_config_pfc_82598() local
316 u32 reg = 0; ixgbe_dcb_config_tc_stats_82598() local
[all...]
/titanic_51/usr/src/uts/intel/brand/common/
H A Dbrand_asm.h153 #define GET_V(sp, pcnt, var, reg) \ argument
156 #define SET_V(sp, pcnt, var, reg) \ argument
159 #define GET_PROCP(sp, pcnt, reg) \ argument
163 #define GET_P_BRAND_DATA(sp, pcnt, reg) \ argument
194 CHECK_FOR_NATIVE(reg) global() argument
[all...]
/titanic_51/usr/src/uts/common/io/nxge/npi/
H A Dnpi_txc.h67 #define TXC_FZC_REG_READ64(handle, reg, cn, val_p) \ argument
71 #define TXC_FZC_REG_WRITE64(handle, reg, cn, data) \ argument
75 #define TXC_FZC_CNTL_REG_READ64(handle, reg, port, val_p) \ argument
79 #define TXC_FZC_CNTL_REG_WRITE64(handle, reg, port, data) \ argument
/titanic_51/usr/src/uts/common/io/mii/
H A Dmii_marvell.c151 uint16_t reg; in mvphy_reset_88e3016() local
184 uint16_t reg; in mvphy_loop_88e3016() local
210 uint16_t reg; mvphy_reset_88e3082() local
227 uint16_t reg; mvphy_reset_88e1149() local
289 uint16_t reg; mvphy_reset_88e1116() local
324 uint16_t reg; mvphy_reset_88e1118() local
340 uint16_t reg; mvphy_reset_88e1111() local
362 uint16_t reg, page; mvphy_reset_88e1112() local
397 uint16_t reg; mvphy_reset_88e1011() local
420 uint16_t reg; mvphy_reset() local
[all...]
/titanic_51/usr/src/uts/common/io/1394/adapters/
H A Dhci1394_ohci.c1017 uint_t reg; in hci1394_ohci_bus_reset() local
1071 uint_t reg; in hci1394_ohci_bus_reset_nroot() local
1189 uint_t reg; hci1394_ohci_phy_set() local
1239 uint_t reg; hci1394_ohci_phy_clr() local
1535 uint32_t reg; hci1394_ohci_phy_info() local
1648 uint32_t reg; hci1394_ohci_current_busgen() local
1724 uint32_t reg; hci1394_ohci_postwr_addr() local
1758 uint32_t reg; hci1394_ohci_guid() local
2233 uint32_t reg; hci1394_ohci_nodeid_get() local
2256 uint32_t reg; hci1394_ohci_nodeid_set() local
2282 uint32_t reg; hci1394_ohci_nodeid_info() local
2414 uint32_t reg; hci1394_ohci_atreq_retries_get() local
2436 uint32_t reg; hci1394_ohci_atreq_retries_set() local
2580 uint32_t reg; hci1394_ohci_root_check() local
2609 uint32_t reg; hci1394_ohci_cmc_check() local
2857 uint32_t reg; hci1394_ohci_selfid_info() local
2890 uint32_t reg; hci1394_ohci_selfid_buf_current() local
3012 uint32_t reg; hci1394_ohci_at_active() local
3311 uint32_t reg; hci1394_ohci_1394a_init() local
3348 uint32_t reg; hci1394_ohci_1394a_resume() local
[all...]
/titanic_51/usr/src/lib/libc/amd64/threads/
H A Dasm_subr.s114 #define REGOFF(reg) ( reg * CLONGSIZE ) argument
116 #define REGOFF(reg) [ reg \* CLONGSIZE ] argument
/titanic_51/usr/src/lib/libdtrace/common/
H A Ddt_regset.c78 int reg; in dt_regset_assert_free() local
110 int reg; in dt_regset_alloc() local
127 dt_regset_free(dt_regset_t * drp,int reg) dt_regset_free() argument
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