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/titanic_41/usr/src/uts/common/io/
H A Dvgasubr.c79 vga_get_hardware_settings(struct vgaregmap *reg, int *width, int *height) in vga_get_hardware_settings()
86 #define PUTB(reg, off, v) ddi_put8(reg->handle, reg->addr + (off), v) argument
87 #define GETB(reg, off) ddi_get8(reg->handle, reg->addr + (off)) argument
90 vga_get_reg(struct vgaregmap *reg, int indexreg) in vga_get_reg()
96 vga_set_reg(struct vgaregmap *reg, int indexreg, int v) in vga_set_reg()
102 vga_get_crtc(struct vgaregmap *reg, int i) in vga_get_crtc()
108 vga_set_crtc(struct vgaregmap *reg, int i, int v) in vga_set_crtc()
114 vga_get_seq(struct vgaregmap *reg, int i) in vga_get_seq()
120 vga_set_seq(struct vgaregmap *reg, int i, int v) in vga_set_seq()
126 vga_get_grc(struct vgaregmap *reg, int i) in vga_get_grc()
[all …]
/titanic_41/usr/src/uts/common/io/cxgbe/t4nex/
H A Dadapter.c26 t4_read_reg(struct adapter *sc, uint32_t reg) in t4_read_reg()
33 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) in t4_write_reg()
40 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) in t4_os_pci_read_cfg1()
46 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) in t4_os_pci_write_cfg1()
52 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) in t4_os_pci_read_cfg2()
58 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) in t4_os_pci_write_cfg2()
64 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) in t4_os_pci_read_cfg4()
70 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) in t4_os_pci_write_cfg4()
76 t4_read_reg64(struct adapter *sc, uint32_t reg) in t4_read_reg64()
83 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) in t4_write_reg64()
/titanic_41/usr/src/uts/common/io/i40e/
H A Di40e_intr.c213 uint32_t reg; in i40e_intr_adminq_enable() local
226 uint32_t reg; in i40e_intr_adminq_disable() local
235 uint32_t reg; in i40e_intr_io_enable() local
247 uint32_t reg; in i40e_intr_io_disable() local
269 uint32_t reg; in i40e_intr_io_enable_all() local
297 uint32_t reg; in i40e_intr_io_disable_all() local
324 uint32_t reg; in i40e_intr_io_clear_cause() local
331 uint32_t reg; in i40e_intr_io_clear_cause() local
355 uint32_t reg; in i40e_intr_chip_fini() local
386 uint32_t reg; in i40e_intr_init_queue_msix() local
[all …]
/titanic_41/usr/src/uts/intel/io/intel_nhm/
H A Dintel_nhm.h62 #define MC_SCRUB_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, \ argument
65 #define MC_SSR_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, 0x48, \ argument
102 #define MC_CONTROL_CHANNEL_ACTIVE(reg, channel) \ argument
104 #define MC_CONTROL_ECCEN(reg) (((reg) >> 1) & 1) argument
105 #define MC_CONTROL_CLOSED_PAGE(reg) ((reg) & 1) argument
106 #define MC_CONTROL_DIVBY3(reg) ((reg >> 6) &1) argument
113 #define CHANNEL_DISABLED(reg, channel) ((reg) & (1 << (channel))) argument
126 #define RANKOFFSET(reg) (((reg) >> 10) & 7) argument
127 #define DIMMPRESENT(reg) (((reg) & (1 << 9)) != 0) argument
128 #define NUMBANK(reg) (((reg) & (3 << 7)) == 0 ? 4 : (((reg) >> 7) & 3) * 8) argument
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H A Dnhm_pci_cfg.c45 pci_regspec_t reg; in nhm_pci_cfg_setup() local
108 nhm_pci_getb(int bus, int dev, int func, int reg, int *interpose) in nhm_pci_getb()
117 nhm_pci_getw(int bus, int dev, int func, int reg, int *interpose) in nhm_pci_getw()
126 nhm_pci_getl(int bus, int dev, int func, int reg, int *interpose) in nhm_pci_getl()
135 nhm_pci_putb(int bus, int dev, int func, int reg, uint8_t val) in nhm_pci_putb()
144 nhm_pci_putw(int bus, int dev, int func, int reg, uint16_t val) in nhm_pci_putw()
153 nhm_pci_putl(int bus, int dev, int func, int reg, uint32_t val) in nhm_pci_putl()
/titanic_41/usr/src/uts/sun4/brand/common/
H A Dbrand_solaris.s59 #define GLOBALS_SWAP(reg) \ argument
67 #define GLOBALS_RESTORE(reg) \ argument
72 #define GLOBALS_SWAP(reg) \ argument
80 #define GLOBALS_RESTORE(reg) \ argument
/titanic_41/usr/src/uts/i86pc/os/
H A Dpci_mech1.c48 pci_mech1_getb(int bus, int device, int function, int reg) in pci_mech1_getb()
64 pci_mech1_getw(int bus, int device, int function, int reg) in pci_mech1_getw()
81 pci_mech1_getl(int bus, int device, int function, int reg) in pci_mech1_getl()
98 pci_mech1_putb(int bus, int device, int function, int reg, uint8_t val) in pci_mech1_putb()
112 pci_mech1_putw(int bus, int device, int function, int reg, uint16_t val) in pci_mech1_putw()
126 pci_mech1_putl(int bus, int device, int function, int reg, uint32_t val) in pci_mech1_putl()
H A Dpci_neptune.c140 pci_neptune_getb(int bus, int device, int function, int reg) in pci_neptune_getb()
153 pci_neptune_getw(int bus, int device, int function, int reg) in pci_neptune_getw()
166 pci_neptune_getl(int bus, int device, int function, int reg) in pci_neptune_getl()
179 pci_neptune_putb(int bus, int device, int function, int reg, uint8_t val) in pci_neptune_putb()
189 pci_neptune_putw(int bus, int device, int function, int reg, uint16_t val) in pci_neptune_putw()
199 pci_neptune_putl(int bus, int device, int function, int reg, uint32_t val) in pci_neptune_putl()
H A Dpci_mech1_amd.c95 pci_mech1_amd_getb(int bus, int device, int function, int reg) in pci_mech1_amd_getb()
112 pci_mech1_amd_getw(int bus, int device, int function, int reg) in pci_mech1_amd_getw()
129 pci_mech1_amd_getl(int bus, int device, int function, int reg) in pci_mech1_amd_getl()
146 pci_mech1_amd_putb(int bus, int device, int function, int reg, uint8_t val) in pci_mech1_amd_putb()
160 pci_mech1_amd_putw(int bus, int device, int function, int reg, uint16_t val) in pci_mech1_amd_putw()
174 pci_mech1_amd_putl(int bus, int device, int function, int reg, uint32_t val) in pci_mech1_amd_putl()
H A Dpci_mech2.c73 pci_mech2_getb(int bus, int device, int function, int reg) in pci_mech2_getb()
89 pci_mech2_getw(int bus, int device, int function, int reg) in pci_mech2_getw()
105 pci_mech2_getl(int bus, int device, int function, int reg) in pci_mech2_getl()
121 pci_mech2_putb(int bus, int device, int function, int reg, uint8_t val) in pci_mech2_putb()
134 pci_mech2_putw(int bus, int device, int function, int reg, uint16_t val) in pci_mech2_putw()
147 pci_mech2_putl(int bus, int device, int function, int reg, uint32_t val) in pci_mech2_putl()
H A Dpci_orion.c181 pci_orion_getb(int bus, int device, int function, int reg) in pci_orion_getb()
194 pci_orion_getw(int bus, int device, int function, int reg) in pci_orion_getw()
207 pci_orion_getl(int bus, int device, int function, int reg) in pci_orion_getl()
220 pci_orion_putb(int bus, int device, int function, int reg, uint8_t val) in pci_orion_putb()
230 pci_orion_putw(int bus, int device, int function, int reg, uint16_t val) in pci_orion_putw()
240 pci_orion_putl(int bus, int device, int function, int reg, uint32_t val) in pci_orion_putl()
/titanic_41/usr/src/uts/common/io/atge/
H A Datge_mii.c64 atge_mii_read(void *arg, uint8_t phy, uint8_t reg) in atge_mii_read()
107 atge_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val) in atge_mii_write()
187 uint16_t reg, pn; in atge_l1_mii_reset() local
272 uint16_t reg; in atge_l1c_mii_reset() local
350 atge_l1c_mii_read(void *arg, uint8_t phy, uint8_t reg) in atge_l1c_mii_read()
362 atge_l1c_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val) in atge_l1c_mii_write()
/titanic_41/usr/src/uts/intel/io/intel_nb5000/
H A Dnb_pci_cfg.c49 pci_regspec_t reg; in nb_pci_cfg_setup() local
149 nb_pci_getb(int bus, int dev, int func, int reg, int *interpose) in nb_pci_getb()
158 nb_pci_getw(int bus, int dev, int func, int reg, int *interpose) in nb_pci_getw()
167 nb_pci_getl(int bus, int dev, int func, int reg, int *interpose) in nb_pci_getl()
176 nb_pci_putb(int bus, int dev, int func, int reg, uint8_t val) in nb_pci_putb()
185 nb_pci_putw(int bus, int dev, int func, int reg, uint16_t val) in nb_pci_putw()
194 nb_pci_putl(int bus, int dev, int func, int reg, uint32_t val) in nb_pci_putl()
/titanic_41/usr/src/uts/common/io/e1000g/
H A De1000g_osdep.c46 e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) in e1000_write_pci_cfg()
52 e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) in e1000_read_pci_cfg()
69 uint16_t reg; /* register contents */ in phy_spd_state() local
109 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) in e1000_read_pcie_cap_reg()
123 e1000_write_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) in e1000_write_pcie_cap_reg()
H A De1000_osdep.h106 #define E1000_WRITE_REG(hw, reg, value) \ argument
119 #define E1000_READ_REG(hw, reg) (\ argument
127 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ argument
141 #define E1000_READ_REG_ARRAY(hw, reg, offset) (\ argument
152 #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) \ argument
154 #define E1000_READ_REG_ARRAY_DWORD(a, reg, offset) \ argument
158 #define E1000_READ_FLASH_REG(hw, reg) \ argument
162 #define E1000_READ_FLASH_REG16(hw, reg) \ argument
166 #define E1000_WRITE_FLASH_REG(hw, reg, value) \ argument
170 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \ argument
[all …]
/titanic_41/usr/src/lib/libc/amd64/threads/
H A Dasm_subr.s114 #define REGOFF(reg) ( reg * CLONGSIZE ) argument
116 #define REGOFF(reg) [ reg \* CLONGSIZE ] argument
/titanic_41/usr/src/uts/common/io/igb/
H A De1000_osdep.h116 #define E1000_WRITE_REG(hw, reg, value) \ argument
120 #define E1000_READ_REG(hw, reg) \ argument
124 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ argument
129 #define E1000_READ_REG_ARRAY(hw, reg, offset) \ argument
133 #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) \ argument
135 #define E1000_READ_REG_ARRAY_DWORD(a, reg, offset) \ argument
139 #define E1000_READ_FLASH_REG(hw, reg) \ argument
143 #define E1000_READ_FLASH_REG16(hw, reg) \ argument
147 #define E1000_WRITE_FLASH_REG(hw, reg, value) \ argument
151 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \ argument
[all …]
H A Digb_osdep.c49 e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) in e1000_write_pci_cfg()
55 e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) in e1000_read_pci_cfg()
67 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) in e1000_read_pcie_cap_reg()
91 e1000_write_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) in e1000_write_pcie_cap_reg()
/titanic_41/usr/src/uts/common/io/nxge/npi/
H A Dnpi_txc.h67 #define TXC_FZC_REG_READ64(handle, reg, cn, val_p) \ argument
71 #define TXC_FZC_REG_WRITE64(handle, reg, cn, data) \ argument
75 #define TXC_FZC_CNTL_REG_READ64(handle, reg, port, val_p) \ argument
79 #define TXC_FZC_CNTL_REG_WRITE64(handle, reg, port, data) \ argument
/titanic_41/usr/src/uts/intel/brand/common/
H A Dbrand_asm.h152 #define GET_V(sp, pcnt, var, reg) \ argument
155 #define SET_V(sp, pcnt, var, reg) \ argument
158 #define GET_PROCP(sp, pcnt, reg) \ argument
162 #define GET_P_BRAND_DATA(sp, pcnt, reg) \ argument
193 #define CHECK_FOR_NATIVE(reg) \ argument
/titanic_41/usr/src/uts/common/io/mii/
H A Dmii_marvell.c151 uint16_t reg; in mvphy_reset_88e3016() local
184 uint16_t reg; in mvphy_loop_88e3016() local
210 uint16_t reg; in mvphy_reset_88e3082() local
227 uint16_t reg; in mvphy_reset_88e1149() local
289 uint16_t reg; in mvphy_reset_88e1116() local
324 uint16_t reg; in mvphy_reset_88e1118() local
340 uint16_t reg; in mvphy_reset_88e1111() local
362 uint16_t reg, page; in mvphy_reset_88e1112() local
397 uint16_t reg; in mvphy_reset_88e1011() local
420 uint16_t reg; in mvphy_reset() local
/titanic_41/usr/src/uts/common/io/ixgbe/
H A Dixgbe_osdep.c33 ixgbe_read_pci_cfg(struct ixgbe_hw *hw, uint32_t reg) in ixgbe_read_pci_cfg()
39 ixgbe_write_pci_cfg(struct ixgbe_hw *hw, uint32_t reg, uint32_t val) in ixgbe_write_pci_cfg()
H A Dixgbe_common.h41 #define IXGBE_WRITE_REG64(hw, reg, value) hw = hw argument
43 #define IXGBE_WRITE_REG64(hw, reg, value) \ argument
/titanic_41/usr/src/uts/common/io/1394/adapters/
H A Dhci1394_ohci.c1017 uint_t reg; in hci1394_ohci_bus_reset() local
1071 uint_t reg; in hci1394_ohci_bus_reset_nroot() local
1189 uint_t reg; in hci1394_ohci_phy_set() local
1239 uint_t reg; in hci1394_ohci_phy_clr() local
1535 uint32_t reg; in hci1394_ohci_phy_info() local
1648 uint32_t reg; in hci1394_ohci_current_busgen() local
1724 uint32_t reg; in hci1394_ohci_postwr_addr() local
1758 uint32_t reg; in hci1394_ohci_guid() local
2233 uint32_t reg; in hci1394_ohci_nodeid_get() local
2256 uint32_t reg; in hci1394_ohci_nodeid_set() local
[all …]
/titanic_41/usr/src/lib/libdtrace/common/
H A Ddt_regset.c78 int reg; in dt_regset_assert_free() local
110 int reg; in dt_regset_alloc() local
127 dt_regset_free(dt_regset_t *drp, int reg) in dt_regset_free()

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