xref: /linux/sound/hda/codecs/ca0132.c (revision 05a54fa773284d1a7923cdfdd8f0c8dabb98bd26)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * HD audio codec driver for Creative CA0132 chip
4  *
5  * Copyright (c) 2011, Creative Technology Ltd.
6  *
7  * Based on ca0110.c
8  * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
9  */
10 
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/mutex.h>
15 #include <linux/module.h>
16 #include <linux/firmware.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/io.h>
20 #include <linux/pci.h>
21 #include <asm/io.h>
22 #include <sound/core.h>
23 #include <sound/hda_codec.h>
24 #include "hda_local.h"
25 #include "hda_auto_parser.h"
26 #include "hda_jack.h"
27 
28 #include "ca0132_regs.h"
29 
30 /* Enable this to see controls for tuning purpose. */
31 #define ENABLE_TUNING_CONTROLS
32 
33 #ifdef ENABLE_TUNING_CONTROLS
34 #include <sound/tlv.h>
35 #endif
36 
37 #define FLOAT_ZERO	0x00000000
38 #define FLOAT_ONE	0x3f800000
39 #define FLOAT_TWO	0x40000000
40 #define FLOAT_THREE     0x40400000
41 #define FLOAT_FIVE	0x40a00000
42 #define FLOAT_SIX       0x40c00000
43 #define FLOAT_EIGHT     0x41000000
44 #define FLOAT_MINUS_5	0xc0a00000
45 
46 #define UNSOL_TAG_DSP	0x16
47 
48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
50 
51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS		8
52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS	32
53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS		2
54 
55 #define MASTERCONTROL				0x80
56 #define MASTERCONTROL_ALLOC_DMA_CHAN		10
57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS	60
58 
59 #define WIDGET_CHIP_CTRL      0x15
60 #define WIDGET_DSP_CTRL       0x16
61 
62 #define MEM_CONNID_MICIN1     3
63 #define MEM_CONNID_MICIN2     5
64 #define MEM_CONNID_MICOUT1    12
65 #define MEM_CONNID_MICOUT2    14
66 #define MEM_CONNID_WUH        10
67 #define MEM_CONNID_DSP        16
68 #define MEM_CONNID_DMIC       100
69 
70 #define SCP_SET    0
71 #define SCP_GET    1
72 
73 #define EFX_FILE   "ctefx.bin"
74 #define DESKTOP_EFX_FILE   "ctefx-desktop.bin"
75 #define R3DI_EFX_FILE  "ctefx-r3di.bin"
76 
77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
78 MODULE_FIRMWARE(EFX_FILE);
79 MODULE_FIRMWARE(DESKTOP_EFX_FILE);
80 MODULE_FIRMWARE(R3DI_EFX_FILE);
81 #endif
82 
83 static const char *const dirstr[2] = { "Playback", "Capture" };
84 
85 #define NUM_OF_OUTPUTS 2
86 static const char *const out_type_str[2] = { "Speakers", "Headphone" };
87 enum {
88 	SPEAKER_OUT,
89 	HEADPHONE_OUT,
90 };
91 
92 enum {
93 	DIGITAL_MIC,
94 	LINE_MIC_IN
95 };
96 
97 /* Strings for Input Source Enum Control */
98 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" };
99 #define IN_SRC_NUM_OF_INPUTS 3
100 enum {
101 	REAR_MIC,
102 	REAR_LINE_IN,
103 	FRONT_MIC,
104 };
105 
106 enum {
107 #define VNODE_START_NID    0x80
108 	VNID_SPK = VNODE_START_NID,			/* Speaker vnid */
109 	VNID_MIC,
110 	VNID_HP_SEL,
111 	VNID_AMIC1_SEL,
112 	VNID_HP_ASEL,
113 	VNID_AMIC1_ASEL,
114 	VNODE_END_NID,
115 #define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)
116 
117 #define EFFECT_START_NID    0x90
118 #define OUT_EFFECT_START_NID    EFFECT_START_NID
119 	SURROUND = OUT_EFFECT_START_NID,
120 	CRYSTALIZER,
121 	DIALOG_PLUS,
122 	SMART_VOLUME,
123 	X_BASS,
124 	EQUALIZER,
125 	OUT_EFFECT_END_NID,
126 #define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
127 
128 #define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
129 	ECHO_CANCELLATION = IN_EFFECT_START_NID,
130 	VOICE_FOCUS,
131 	MIC_SVM,
132 	NOISE_REDUCTION,
133 	IN_EFFECT_END_NID,
134 #define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
135 
136 	VOICEFX = IN_EFFECT_END_NID,
137 	PLAY_ENHANCEMENT,
138 	CRYSTAL_VOICE,
139 	EFFECT_END_NID,
140 	OUTPUT_SOURCE_ENUM,
141 	INPUT_SOURCE_ENUM,
142 	XBASS_XOVER,
143 	EQ_PRESET_ENUM,
144 	SMART_VOLUME_ENUM,
145 	MIC_BOOST_ENUM,
146 	AE5_HEADPHONE_GAIN_ENUM,
147 	AE5_SOUND_FILTER_ENUM,
148 	ZXR_HEADPHONE_GAIN,
149 	SPEAKER_CHANNEL_CFG_ENUM,
150 	SPEAKER_FULL_RANGE_FRONT,
151 	SPEAKER_FULL_RANGE_REAR,
152 	BASS_REDIRECTION,
153 	BASS_REDIRECTION_XOVER,
154 #define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
155 };
156 
157 /* Effects values size*/
158 #define EFFECT_VALS_MAX_COUNT 12
159 
160 /*
161  * Default values for the effect slider controls, they are in order of their
162  * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
163  * X-bass.
164  */
165 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
166 /* Amount of effect level sliders for ca0132_alt controls. */
167 #define EFFECT_LEVEL_SLIDERS 5
168 
169 /* Latency introduced by DSP blocks in milliseconds. */
170 #define DSP_CAPTURE_INIT_LATENCY        0
171 #define DSP_CRYSTAL_VOICE_LATENCY       124
172 #define DSP_PLAYBACK_INIT_LATENCY       13
173 #define DSP_PLAY_ENHANCEMENT_LATENCY    30
174 #define DSP_SPEAKER_OUT_LATENCY         7
175 
176 struct ct_effect {
177 	const char *name;
178 	hda_nid_t nid;
179 	int mid; /*effect module ID*/
180 	int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
181 	int direct; /* 0:output; 1:input*/
182 	int params; /* number of default non-on/off params */
183 	/*effect default values, 1st is on/off. */
184 	unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
185 };
186 
187 #define EFX_DIR_OUT 0
188 #define EFX_DIR_IN  1
189 
190 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
191 	{ .name = "Surround",
192 	  .nid = SURROUND,
193 	  .mid = 0x96,
194 	  .reqs = {0, 1},
195 	  .direct = EFX_DIR_OUT,
196 	  .params = 1,
197 	  .def_vals = {0x3F800000, 0x3F2B851F}
198 	},
199 	{ .name = "Crystalizer",
200 	  .nid = CRYSTALIZER,
201 	  .mid = 0x96,
202 	  .reqs = {7, 8},
203 	  .direct = EFX_DIR_OUT,
204 	  .params = 1,
205 	  .def_vals = {0x3F800000, 0x3F266666}
206 	},
207 	{ .name = "Dialog Plus",
208 	  .nid = DIALOG_PLUS,
209 	  .mid = 0x96,
210 	  .reqs = {2, 3},
211 	  .direct = EFX_DIR_OUT,
212 	  .params = 1,
213 	  .def_vals = {0x00000000, 0x3F000000}
214 	},
215 	{ .name = "Smart Volume",
216 	  .nid = SMART_VOLUME,
217 	  .mid = 0x96,
218 	  .reqs = {4, 5, 6},
219 	  .direct = EFX_DIR_OUT,
220 	  .params = 2,
221 	  .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
222 	},
223 	{ .name = "X-Bass",
224 	  .nid = X_BASS,
225 	  .mid = 0x96,
226 	  .reqs = {24, 23, 25},
227 	  .direct = EFX_DIR_OUT,
228 	  .params = 2,
229 	  .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
230 	},
231 	{ .name = "Equalizer",
232 	  .nid = EQUALIZER,
233 	  .mid = 0x96,
234 	  .reqs = {9, 10, 11, 12, 13, 14,
235 			15, 16, 17, 18, 19, 20},
236 	  .direct = EFX_DIR_OUT,
237 	  .params = 11,
238 	  .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
239 		       0x00000000, 0x00000000, 0x00000000, 0x00000000,
240 		       0x00000000, 0x00000000, 0x00000000, 0x00000000}
241 	},
242 	{ .name = "Echo Cancellation",
243 	  .nid = ECHO_CANCELLATION,
244 	  .mid = 0x95,
245 	  .reqs = {0, 1, 2, 3},
246 	  .direct = EFX_DIR_IN,
247 	  .params = 3,
248 	  .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
249 	},
250 	{ .name = "Voice Focus",
251 	  .nid = VOICE_FOCUS,
252 	  .mid = 0x95,
253 	  .reqs = {6, 7, 8, 9},
254 	  .direct = EFX_DIR_IN,
255 	  .params = 3,
256 	  .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
257 	},
258 	{ .name = "Mic SVM",
259 	  .nid = MIC_SVM,
260 	  .mid = 0x95,
261 	  .reqs = {44, 45},
262 	  .direct = EFX_DIR_IN,
263 	  .params = 1,
264 	  .def_vals = {0x00000000, 0x3F3D70A4}
265 	},
266 	{ .name = "Noise Reduction",
267 	  .nid = NOISE_REDUCTION,
268 	  .mid = 0x95,
269 	  .reqs = {4, 5},
270 	  .direct = EFX_DIR_IN,
271 	  .params = 1,
272 	  .def_vals = {0x3F800000, 0x3F000000}
273 	},
274 	{ .name = "VoiceFX",
275 	  .nid = VOICEFX,
276 	  .mid = 0x95,
277 	  .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
278 	  .direct = EFX_DIR_IN,
279 	  .params = 8,
280 	  .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
281 		       0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
282 		       0x00000000}
283 	}
284 };
285 
286 /* Tuning controls */
287 #ifdef ENABLE_TUNING_CONTROLS
288 
289 enum {
290 #define TUNING_CTL_START_NID  0xC0
291 	WEDGE_ANGLE = TUNING_CTL_START_NID,
292 	SVM_LEVEL,
293 	EQUALIZER_BAND_0,
294 	EQUALIZER_BAND_1,
295 	EQUALIZER_BAND_2,
296 	EQUALIZER_BAND_3,
297 	EQUALIZER_BAND_4,
298 	EQUALIZER_BAND_5,
299 	EQUALIZER_BAND_6,
300 	EQUALIZER_BAND_7,
301 	EQUALIZER_BAND_8,
302 	EQUALIZER_BAND_9,
303 	TUNING_CTL_END_NID
304 #define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
305 };
306 
307 struct ct_tuning_ctl {
308 	const char *name;
309 	hda_nid_t parent_nid;
310 	hda_nid_t nid;
311 	int mid; /*effect module ID*/
312 	int req; /*effect module request*/
313 	int direct; /* 0:output; 1:input*/
314 	unsigned int def_val;/*effect default values*/
315 };
316 
317 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
318 	{ .name = "Wedge Angle",
319 	  .parent_nid = VOICE_FOCUS,
320 	  .nid = WEDGE_ANGLE,
321 	  .mid = 0x95,
322 	  .req = 8,
323 	  .direct = EFX_DIR_IN,
324 	  .def_val = 0x41F00000
325 	},
326 	{ .name = "SVM Level",
327 	  .parent_nid = MIC_SVM,
328 	  .nid = SVM_LEVEL,
329 	  .mid = 0x95,
330 	  .req = 45,
331 	  .direct = EFX_DIR_IN,
332 	  .def_val = 0x3F3D70A4
333 	},
334 	{ .name = "EQ Band0",
335 	  .parent_nid = EQUALIZER,
336 	  .nid = EQUALIZER_BAND_0,
337 	  .mid = 0x96,
338 	  .req = 11,
339 	  .direct = EFX_DIR_OUT,
340 	  .def_val = 0x00000000
341 	},
342 	{ .name = "EQ Band1",
343 	  .parent_nid = EQUALIZER,
344 	  .nid = EQUALIZER_BAND_1,
345 	  .mid = 0x96,
346 	  .req = 12,
347 	  .direct = EFX_DIR_OUT,
348 	  .def_val = 0x00000000
349 	},
350 	{ .name = "EQ Band2",
351 	  .parent_nid = EQUALIZER,
352 	  .nid = EQUALIZER_BAND_2,
353 	  .mid = 0x96,
354 	  .req = 13,
355 	  .direct = EFX_DIR_OUT,
356 	  .def_val = 0x00000000
357 	},
358 	{ .name = "EQ Band3",
359 	  .parent_nid = EQUALIZER,
360 	  .nid = EQUALIZER_BAND_3,
361 	  .mid = 0x96,
362 	  .req = 14,
363 	  .direct = EFX_DIR_OUT,
364 	  .def_val = 0x00000000
365 	},
366 	{ .name = "EQ Band4",
367 	  .parent_nid = EQUALIZER,
368 	  .nid = EQUALIZER_BAND_4,
369 	  .mid = 0x96,
370 	  .req = 15,
371 	  .direct = EFX_DIR_OUT,
372 	  .def_val = 0x00000000
373 	},
374 	{ .name = "EQ Band5",
375 	  .parent_nid = EQUALIZER,
376 	  .nid = EQUALIZER_BAND_5,
377 	  .mid = 0x96,
378 	  .req = 16,
379 	  .direct = EFX_DIR_OUT,
380 	  .def_val = 0x00000000
381 	},
382 	{ .name = "EQ Band6",
383 	  .parent_nid = EQUALIZER,
384 	  .nid = EQUALIZER_BAND_6,
385 	  .mid = 0x96,
386 	  .req = 17,
387 	  .direct = EFX_DIR_OUT,
388 	  .def_val = 0x00000000
389 	},
390 	{ .name = "EQ Band7",
391 	  .parent_nid = EQUALIZER,
392 	  .nid = EQUALIZER_BAND_7,
393 	  .mid = 0x96,
394 	  .req = 18,
395 	  .direct = EFX_DIR_OUT,
396 	  .def_val = 0x00000000
397 	},
398 	{ .name = "EQ Band8",
399 	  .parent_nid = EQUALIZER,
400 	  .nid = EQUALIZER_BAND_8,
401 	  .mid = 0x96,
402 	  .req = 19,
403 	  .direct = EFX_DIR_OUT,
404 	  .def_val = 0x00000000
405 	},
406 	{ .name = "EQ Band9",
407 	  .parent_nid = EQUALIZER,
408 	  .nid = EQUALIZER_BAND_9,
409 	  .mid = 0x96,
410 	  .req = 20,
411 	  .direct = EFX_DIR_OUT,
412 	  .def_val = 0x00000000
413 	}
414 };
415 #endif
416 
417 /* Voice FX Presets */
418 #define VOICEFX_MAX_PARAM_COUNT 9
419 
420 struct ct_voicefx {
421 	const char *name;
422 	hda_nid_t nid;
423 	int mid;
424 	int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
425 };
426 
427 struct ct_voicefx_preset {
428 	const char *name; /*preset name*/
429 	unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
430 };
431 
432 static const struct ct_voicefx ca0132_voicefx = {
433 	.name = "VoiceFX Capture Switch",
434 	.nid = VOICEFX,
435 	.mid = 0x95,
436 	.reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
437 };
438 
439 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
440 	{ .name = "Neutral",
441 	  .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
442 		    0x44FA0000, 0x3F800000, 0x3F800000,
443 		    0x3F800000, 0x00000000, 0x00000000 }
444 	},
445 	{ .name = "Female2Male",
446 	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
447 		    0x44FA0000, 0x3F19999A, 0x3F866666,
448 		    0x3F800000, 0x00000000, 0x00000000 }
449 	},
450 	{ .name = "Male2Female",
451 	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
452 		    0x450AC000, 0x4017AE14, 0x3F6B851F,
453 		    0x3F800000, 0x00000000, 0x00000000 }
454 	},
455 	{ .name = "ScrappyKid",
456 	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
457 		    0x44FA0000, 0x40400000, 0x3F28F5C3,
458 		    0x3F800000, 0x00000000, 0x00000000 }
459 	},
460 	{ .name = "Elderly",
461 	  .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
462 		    0x44E10000, 0x3FB33333, 0x3FB9999A,
463 		    0x3F800000, 0x3E3A2E43, 0x00000000 }
464 	},
465 	{ .name = "Orc",
466 	  .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
467 		    0x45098000, 0x3F266666, 0x3FC00000,
468 		    0x3F800000, 0x00000000, 0x00000000 }
469 	},
470 	{ .name = "Elf",
471 	  .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
472 		    0x45193000, 0x3F8E147B, 0x3F75C28F,
473 		    0x3F800000, 0x00000000, 0x00000000 }
474 	},
475 	{ .name = "Dwarf",
476 	  .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
477 		    0x45007000, 0x3F451EB8, 0x3F7851EC,
478 		    0x3F800000, 0x00000000, 0x00000000 }
479 	},
480 	{ .name = "AlienBrute",
481 	  .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
482 		    0x451F6000, 0x3F266666, 0x3FA7D945,
483 		    0x3F800000, 0x3CF5C28F, 0x00000000 }
484 	},
485 	{ .name = "Robot",
486 	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
487 		    0x44FA0000, 0x3FB2718B, 0x3F800000,
488 		    0xBC07010E, 0x00000000, 0x00000000 }
489 	},
490 	{ .name = "Marine",
491 	  .vals = { 0x3F800000, 0x43C20000, 0x44906000,
492 		    0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
493 		    0x3F0A3D71, 0x00000000, 0x00000000 }
494 	},
495 	{ .name = "Emo",
496 	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
497 		    0x44FA0000, 0x3F800000, 0x3F800000,
498 		    0x3E4CCCCD, 0x00000000, 0x00000000 }
499 	},
500 	{ .name = "DeepVoice",
501 	  .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
502 		    0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
503 		    0x3F800000, 0x00000000, 0x00000000 }
504 	},
505 	{ .name = "Munchkin",
506 	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
507 		    0x44FA0000, 0x3F800000, 0x3F1A043C,
508 		    0x3F800000, 0x00000000, 0x00000000 }
509 	}
510 };
511 
512 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
513 
514 #define EQ_PRESET_MAX_PARAM_COUNT 11
515 
516 struct ct_eq {
517 	const char *name;
518 	hda_nid_t nid;
519 	int mid;
520 	int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
521 };
522 
523 struct ct_eq_preset {
524 	const char *name; /*preset name*/
525 	unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
526 };
527 
528 static const struct ct_eq ca0132_alt_eq_enum = {
529 	.name = "FX: Equalizer Preset Switch",
530 	.nid = EQ_PRESET_ENUM,
531 	.mid = 0x96,
532 	.reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
533 };
534 
535 
536 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
537 	{ .name = "Flat",
538 	 .vals = { 0x00000000, 0x00000000, 0x00000000,
539 		   0x00000000, 0x00000000, 0x00000000,
540 		   0x00000000, 0x00000000, 0x00000000,
541 		   0x00000000, 0x00000000	     }
542 	},
543 	{ .name = "Acoustic",
544 	 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
545 		   0x40000000, 0x00000000, 0x00000000,
546 		   0x00000000, 0x00000000, 0x40000000,
547 		   0x40000000, 0x40000000	     }
548 	},
549 	{ .name = "Classical",
550 	 .vals = { 0x00000000, 0x00000000, 0x40C00000,
551 		   0x40C00000, 0x40466666, 0x00000000,
552 		   0x00000000, 0x00000000, 0x00000000,
553 		   0x40466666, 0x40466666	     }
554 	},
555 	{ .name = "Country",
556 	 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
557 		   0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
558 		   0x00000000, 0x00000000, 0x40000000,
559 		   0x40466666, 0x40800000	     }
560 	},
561 	{ .name = "Dance",
562 	 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
563 		   0x40466666, 0x40866666, 0xBF99999A,
564 		   0xBF99999A, 0x00000000, 0x00000000,
565 		   0x40800000, 0x40800000	     }
566 	},
567 	{ .name = "Jazz",
568 	 .vals = { 0x00000000, 0x00000000, 0x00000000,
569 		   0x3F8CCCCD, 0x40800000, 0x40800000,
570 		   0x40800000, 0x00000000, 0x3F8CCCCD,
571 		   0x40466666, 0x40466666	     }
572 	},
573 	{ .name = "New Age",
574 	 .vals = { 0x00000000, 0x00000000, 0x40000000,
575 		   0x40000000, 0x00000000, 0x00000000,
576 		   0x00000000, 0x3F8CCCCD, 0x40000000,
577 		   0x40000000, 0x40000000	     }
578 	},
579 	{ .name = "Pop",
580 	 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
581 		   0x40000000, 0x40000000, 0x00000000,
582 		   0xBF99999A, 0xBF99999A, 0x00000000,
583 		   0x40466666, 0x40C00000	     }
584 	},
585 	{ .name = "Rock",
586 	 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
587 		   0x3F8CCCCD, 0x40000000, 0xBF99999A,
588 		   0xBF99999A, 0x00000000, 0x00000000,
589 		   0x40800000, 0x40800000	     }
590 	},
591 	{ .name = "Vocal",
592 	 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
593 		   0xBF99999A, 0x00000000, 0x40466666,
594 		   0x40800000, 0x40466666, 0x00000000,
595 		   0x00000000, 0x3F8CCCCD	     }
596 	}
597 };
598 
599 /*
600  * DSP reqs for handling full-range speakers/bass redirection. If a speaker is
601  * set as not being full range, and bass redirection is enabled, all
602  * frequencies below the crossover frequency are redirected to the LFE
603  * channel. If the surround configuration has no LFE channel, this can't be
604  * enabled. X-Bass must be disabled when using these.
605  */
606 enum speaker_range_reqs {
607 	SPEAKER_BASS_REDIRECT            = 0x15,
608 	SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
609 	/* Between 0x16-0x1a are the X-Bass reqs. */
610 	SPEAKER_FULL_RANGE_FRONT_L_R     = 0x1a,
611 	SPEAKER_FULL_RANGE_CENTER_LFE    = 0x1b,
612 	SPEAKER_FULL_RANGE_REAR_L_R      = 0x1c,
613 	SPEAKER_FULL_RANGE_SURROUND_L_R  = 0x1d,
614 	SPEAKER_BASS_REDIRECT_SUB_GAIN   = 0x1e,
615 };
616 
617 /*
618  * Definitions for the DSP req's to handle speaker tuning. These all belong to
619  * module ID 0x96, the output effects module.
620  */
621 enum speaker_tuning_reqs {
622 	/*
623 	 * Currently, this value is always set to 0.0f. However, on Windows,
624 	 * when selecting certain headphone profiles on the new Sound Blaster
625 	 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
626 	 * sent. This gets the speaker EQ address area, which is then used to
627 	 * send over (presumably) an equalizer profile for the specific
628 	 * headphone setup. It is sent using the same method the DSP
629 	 * firmware is uploaded with, which I believe is why the 'ctspeq.bin'
630 	 * file exists in linux firmware tree but goes unused. It would also
631 	 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused.
632 	 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is
633 	 * set to 1.0f.
634 	 */
635 	SPEAKER_TUNING_USE_SPEAKER_EQ           = 0x1f,
636 	SPEAKER_TUNING_ENABLE_CENTER_EQ         = 0x20,
637 	SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL     = 0x21,
638 	SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL    = 0x22,
639 	SPEAKER_TUNING_CENTER_VOL_LEVEL         = 0x23,
640 	SPEAKER_TUNING_LFE_VOL_LEVEL            = 0x24,
641 	SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL      = 0x25,
642 	SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL     = 0x26,
643 	SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL  = 0x27,
644 	SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
645 	/*
646 	 * Inversion is used when setting headphone virtualization to line
647 	 * out. Not sure why this is, but it's the only place it's ever used.
648 	 */
649 	SPEAKER_TUNING_FRONT_LEFT_INVERT        = 0x29,
650 	SPEAKER_TUNING_FRONT_RIGHT_INVERT       = 0x2a,
651 	SPEAKER_TUNING_CENTER_INVERT            = 0x2b,
652 	SPEAKER_TUNING_LFE_INVERT               = 0x2c,
653 	SPEAKER_TUNING_REAR_LEFT_INVERT         = 0x2d,
654 	SPEAKER_TUNING_REAR_RIGHT_INVERT        = 0x2e,
655 	SPEAKER_TUNING_SURROUND_LEFT_INVERT     = 0x2f,
656 	SPEAKER_TUNING_SURROUND_RIGHT_INVERT    = 0x30,
657 	/* Delay is used when setting surround speaker distance in Windows. */
658 	SPEAKER_TUNING_FRONT_LEFT_DELAY         = 0x31,
659 	SPEAKER_TUNING_FRONT_RIGHT_DELAY        = 0x32,
660 	SPEAKER_TUNING_CENTER_DELAY             = 0x33,
661 	SPEAKER_TUNING_LFE_DELAY                = 0x34,
662 	SPEAKER_TUNING_REAR_LEFT_DELAY          = 0x35,
663 	SPEAKER_TUNING_REAR_RIGHT_DELAY         = 0x36,
664 	SPEAKER_TUNING_SURROUND_LEFT_DELAY      = 0x37,
665 	SPEAKER_TUNING_SURROUND_RIGHT_DELAY     = 0x38,
666 	/* Of these two, only mute seems to ever be used. */
667 	SPEAKER_TUNING_MAIN_VOLUME              = 0x39,
668 	SPEAKER_TUNING_MUTE                     = 0x3a,
669 };
670 
671 /* Surround output channel count configuration structures. */
672 #define SPEAKER_CHANNEL_CFG_COUNT 5
673 enum {
674 	SPEAKER_CHANNELS_2_0,
675 	SPEAKER_CHANNELS_2_1,
676 	SPEAKER_CHANNELS_4_0,
677 	SPEAKER_CHANNELS_4_1,
678 	SPEAKER_CHANNELS_5_1,
679 };
680 
681 struct ca0132_alt_speaker_channel_cfg {
682 	const char *name;
683 	unsigned int val;
684 };
685 
686 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = {
687 	{ .name = "2.0",
688 	  .val = FLOAT_ONE
689 	},
690 	{ .name = "2.1",
691 	  .val = FLOAT_TWO
692 	},
693 	{ .name = "4.0",
694 	  .val = FLOAT_FIVE
695 	},
696 	{ .name = "4.1",
697 	  .val = FLOAT_SIX
698 	},
699 	{ .name = "5.1",
700 	  .val = FLOAT_EIGHT
701 	}
702 };
703 
704 /*
705  * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
706  * and I don't know what the third req is, but it's always zero. I assume it's
707  * some sort of update or set command to tell the DSP there's new volume info.
708  */
709 #define DSP_VOL_OUT 0
710 #define DSP_VOL_IN  1
711 
712 struct ct_dsp_volume_ctl {
713 	hda_nid_t vnid;
714 	int mid; /* module ID*/
715 	unsigned int reqs[3]; /* scp req ID */
716 };
717 
718 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
719 	{ .vnid = VNID_SPK,
720 	  .mid = 0x32,
721 	  .reqs = {3, 4, 2}
722 	},
723 	{ .vnid = VNID_MIC,
724 	  .mid = 0x37,
725 	  .reqs = {2, 3, 1}
726 	}
727 };
728 
729 /* Values for ca0113_mmio_command_set for selecting output. */
730 #define AE_CA0113_OUT_SET_COMMANDS 6
731 struct ae_ca0113_output_set {
732 	unsigned int group[AE_CA0113_OUT_SET_COMMANDS];
733 	unsigned int target[AE_CA0113_OUT_SET_COMMANDS];
734 	unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS];
735 };
736 
737 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = {
738 	.group =  { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
739 	.target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
740 		    /* Speakers. */
741 	.vals =   { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
742 		    /* Headphones. */
743 		    { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
744 };
745 
746 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = {
747 	.group  = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
748 	.target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
749 		    /* Speakers. */
750 	.vals   = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
751 		    /* Headphones. */
752 		    { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
753 };
754 
755 /* ae5 ca0113 command sequences to set headphone gain levels. */
756 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
757 struct ae5_headphone_gain_set {
758 	const char *name;
759 	unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
760 };
761 
762 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
763 	{ .name = "Low (16-31",
764 	  .vals = { 0xff, 0x2c, 0xf5, 0x32 }
765 	},
766 	{ .name = "Medium (32-149",
767 	  .vals = { 0x38, 0xa8, 0x3e, 0x4c }
768 	},
769 	{ .name = "High (150-600",
770 	  .vals = { 0xff, 0xff, 0xff, 0x7f }
771 	}
772 };
773 
774 struct ae5_filter_set {
775 	const char *name;
776 	unsigned int val;
777 };
778 
779 static const struct ae5_filter_set ae5_filter_presets[] = {
780 	{ .name = "Slow Roll Off",
781 	  .val = 0xa0
782 	},
783 	{ .name = "Minimum Phase",
784 	  .val = 0xc0
785 	},
786 	{ .name = "Fast Roll Off",
787 	  .val = 0x80
788 	}
789 };
790 
791 /*
792  * Data structures for storing audio router remapping data. These are used to
793  * remap a currently active streams ports.
794  */
795 struct chipio_stream_remap_data {
796 	unsigned int stream_id;
797 	unsigned int count;
798 
799 	unsigned int offset[16];
800 	unsigned int value[16];
801 };
802 
803 static const struct chipio_stream_remap_data stream_remap_data[] = {
804 	{ .stream_id = 0x14,
805 	  .count     = 0x04,
806 	  .offset    = { 0x00, 0x04, 0x08, 0x0c },
807 	  .value     = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 },
808 	},
809 	{ .stream_id = 0x0c,
810 	  .count     = 0x0c,
811 	  .offset    = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c,
812 			 0x20, 0x24, 0x28, 0x2c },
813 	  .value     = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3,
814 			 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7,
815 			 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb },
816 	},
817 	{ .stream_id = 0x0c,
818 	  .count     = 0x08,
819 	  .offset    = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c },
820 	  .value     = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5,
821 			 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb },
822 	}
823 };
824 
825 enum hda_cmd_vendor_io {
826 	/* for DspIO node */
827 	VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
828 	VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,
829 
830 	VENDOR_DSPIO_STATUS                  = 0xF01,
831 	VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
832 	VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
833 	VENDOR_DSPIO_DSP_INIT                = 0x703,
834 	VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
835 	VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,
836 
837 	/* for ChipIO node */
838 	VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
839 	VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
840 	VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
841 	VENDOR_CHIPIO_DATA_LOW               = 0x300,
842 	VENDOR_CHIPIO_DATA_HIGH              = 0x400,
843 
844 	VENDOR_CHIPIO_8051_WRITE_DIRECT      = 0x500,
845 	VENDOR_CHIPIO_8051_READ_DIRECT       = 0xD00,
846 
847 	VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
848 	VENDOR_CHIPIO_STATUS                 = 0xF01,
849 	VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
850 	VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,
851 
852 	VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
853 	VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
854 	VENDOR_CHIPIO_8051_PMEM_READ         = 0xF08,
855 	VENDOR_CHIPIO_8051_IRAM_WRITE        = 0x709,
856 	VENDOR_CHIPIO_8051_IRAM_READ         = 0xF09,
857 
858 	VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
859 	VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
860 
861 	VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
862 	VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
863 	VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
864 	VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
865 	VENDOR_CHIPIO_FLAG_SET               = 0x70F,
866 	VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
867 	VENDOR_CHIPIO_PARAM_SET              = 0x710,
868 	VENDOR_CHIPIO_PARAM_GET              = 0xF10,
869 
870 	VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
871 	VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
872 	VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
873 	VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,
874 
875 	VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
876 	VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
877 	VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
878 	VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,
879 
880 	VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
881 	VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
882 	VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
883 	VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
884 	VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
885 	VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,
886 
887 	VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
888 };
889 
890 /*
891  *  Control flag IDs
892  */
893 enum control_flag_id {
894 	/* Connection manager stream setup is bypassed/enabled */
895 	CONTROL_FLAG_C_MGR                  = 0,
896 	/* DSP DMA is bypassed/enabled */
897 	CONTROL_FLAG_DMA                    = 1,
898 	/* 8051 'idle' mode is disabled/enabled */
899 	CONTROL_FLAG_IDLE_ENABLE            = 2,
900 	/* Tracker for the SPDIF-in path is bypassed/enabled */
901 	CONTROL_FLAG_TRACKER                = 3,
902 	/* DigitalOut to Spdif2Out connection is disabled/enabled */
903 	CONTROL_FLAG_SPDIF2OUT              = 4,
904 	/* Digital Microphone is disabled/enabled */
905 	CONTROL_FLAG_DMIC                   = 5,
906 	/* ADC_B rate is 48 kHz/96 kHz */
907 	CONTROL_FLAG_ADC_B_96KHZ            = 6,
908 	/* ADC_C rate is 48 kHz/96 kHz */
909 	CONTROL_FLAG_ADC_C_96KHZ            = 7,
910 	/* DAC rate is 48 kHz/96 kHz (affects all DACs) */
911 	CONTROL_FLAG_DAC_96KHZ              = 8,
912 	/* DSP rate is 48 kHz/96 kHz */
913 	CONTROL_FLAG_DSP_96KHZ              = 9,
914 	/* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
915 	CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
916 	/* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
917 	CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
918 	/* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
919 	CONTROL_FLAG_DECODE_LOOP            = 12,
920 	/* De-emphasis filter on DAC-1 disabled/enabled */
921 	CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
922 	/* De-emphasis filter on DAC-2 disabled/enabled */
923 	CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
924 	/* De-emphasis filter on DAC-3 disabled/enabled */
925 	CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
926 	/* High-pass filter on ADC_B disabled/enabled */
927 	CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
928 	/* High-pass filter on ADC_C disabled/enabled */
929 	CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
930 	/* Common mode on Port_A disabled/enabled */
931 	CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
932 	/* Common mode on Port_D disabled/enabled */
933 	CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
934 	/* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
935 	CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
936 	/* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
937 	CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
938 	/* ASI rate is 48kHz/96kHz */
939 	CONTROL_FLAG_ASI_96KHZ              = 22,
940 	/* DAC power settings able to control attached ports no/yes */
941 	CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
942 	/* Clock Stop OK reporting is disabled/enabled */
943 	CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
944 	/* Number of control flags */
945 	CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
946 };
947 
948 /*
949  * Control parameter IDs
950  */
951 enum control_param_id {
952 	/* 0: None, 1: Mic1In*/
953 	CONTROL_PARAM_VIP_SOURCE               = 1,
954 	/* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
955 	CONTROL_PARAM_SPDIF1_SOURCE            = 2,
956 	/* Port A output stage gain setting to use when 16 Ohm output
957 	 * impedance is selected*/
958 	CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
959 	/* Port D output stage gain setting to use when 16 Ohm output
960 	 * impedance is selected*/
961 	CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
962 
963 	/*
964 	 * This control param name was found in the 8051 memory, and makes
965 	 * sense given the fact the AE-5 uses it and has the ASI flag set.
966 	 */
967 	CONTROL_PARAM_ASI                      = 23,
968 
969 	/* Stream Control */
970 
971 	/* Select stream with the given ID */
972 	CONTROL_PARAM_STREAM_ID                = 24,
973 	/* Source connection point for the selected stream */
974 	CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
975 	/* Destination connection point for the selected stream */
976 	CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
977 	/* Number of audio channels in the selected stream */
978 	CONTROL_PARAM_STREAMS_CHANNELS         = 27,
979 	/*Enable control for the selected stream */
980 	CONTROL_PARAM_STREAM_CONTROL           = 28,
981 
982 	/* Connection Point Control */
983 
984 	/* Select connection point with the given ID */
985 	CONTROL_PARAM_CONN_POINT_ID            = 29,
986 	/* Connection point sample rate */
987 	CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,
988 
989 	/* Node Control */
990 
991 	/* Select HDA node with the given ID */
992 	CONTROL_PARAM_NODE_ID                  = 31
993 };
994 
995 /*
996  *  Dsp Io Status codes
997  */
998 enum hda_vendor_status_dspio {
999 	/* Success */
1000 	VENDOR_STATUS_DSPIO_OK                       = 0x00,
1001 	/* Busy, unable to accept new command, the host must retry */
1002 	VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
1003 	/* SCP command queue is full */
1004 	VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
1005 	/* SCP response queue is empty */
1006 	VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
1007 };
1008 
1009 /*
1010  *  Chip Io Status codes
1011  */
1012 enum hda_vendor_status_chipio {
1013 	/* Success */
1014 	VENDOR_STATUS_CHIPIO_OK   = 0x00,
1015 	/* Busy, unable to accept new command, the host must retry */
1016 	VENDOR_STATUS_CHIPIO_BUSY = 0x01
1017 };
1018 
1019 /*
1020  *  CA0132 sample rate
1021  */
1022 enum ca0132_sample_rate {
1023 	SR_6_000        = 0x00,
1024 	SR_8_000        = 0x01,
1025 	SR_9_600        = 0x02,
1026 	SR_11_025       = 0x03,
1027 	SR_16_000       = 0x04,
1028 	SR_22_050       = 0x05,
1029 	SR_24_000       = 0x06,
1030 	SR_32_000       = 0x07,
1031 	SR_44_100       = 0x08,
1032 	SR_48_000       = 0x09,
1033 	SR_88_200       = 0x0A,
1034 	SR_96_000       = 0x0B,
1035 	SR_144_000      = 0x0C,
1036 	SR_176_400      = 0x0D,
1037 	SR_192_000      = 0x0E,
1038 	SR_384_000      = 0x0F,
1039 
1040 	SR_COUNT        = 0x10,
1041 
1042 	SR_RATE_UNKNOWN = 0x1F
1043 };
1044 
1045 enum dsp_download_state {
1046 	DSP_DOWNLOAD_FAILED = -1,
1047 	DSP_DOWNLOAD_INIT   = 0,
1048 	DSP_DOWNLOADING     = 1,
1049 	DSP_DOWNLOADED      = 2
1050 };
1051 
1052 /* retrieve parameters from hda format */
1053 #define get_hdafmt_chs(fmt)	(fmt & 0xf)
1054 #define get_hdafmt_bits(fmt)	((fmt >> 4) & 0x7)
1055 #define get_hdafmt_rate(fmt)	((fmt >> 8) & 0x7f)
1056 #define get_hdafmt_type(fmt)	((fmt >> 15) & 0x1)
1057 
1058 /*
1059  * CA0132 specific
1060  */
1061 
1062 struct ca0132_spec {
1063 	const struct snd_kcontrol_new *mixers[5];
1064 	unsigned int num_mixers;
1065 	const struct hda_verb *base_init_verbs;
1066 	const struct hda_verb *base_exit_verbs;
1067 	const struct hda_verb *chip_init_verbs;
1068 	const struct hda_verb *desktop_init_verbs;
1069 	struct hda_verb *spec_init_verbs;
1070 	struct auto_pin_cfg autocfg;
1071 
1072 	/* Nodes configurations */
1073 	struct hda_multi_out multiout;
1074 	hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
1075 	hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
1076 	unsigned int num_outputs;
1077 	hda_nid_t input_pins[AUTO_PIN_LAST];
1078 	hda_nid_t adcs[AUTO_PIN_LAST];
1079 	hda_nid_t dig_out;
1080 	hda_nid_t dig_in;
1081 	unsigned int num_inputs;
1082 	hda_nid_t shared_mic_nid;
1083 	hda_nid_t shared_out_nid;
1084 	hda_nid_t unsol_tag_hp;
1085 	hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
1086 	hda_nid_t unsol_tag_amic1;
1087 
1088 	/* chip access */
1089 	struct mutex chipio_mutex; /* chip access mutex */
1090 	u32 curr_chip_addx;
1091 
1092 	/* DSP download related */
1093 	enum dsp_download_state dsp_state;
1094 	unsigned int dsp_stream_id;
1095 	unsigned int wait_scp;
1096 	unsigned int wait_scp_header;
1097 	unsigned int wait_num_data;
1098 	unsigned int scp_resp_header;
1099 	unsigned int scp_resp_data[4];
1100 	unsigned int scp_resp_count;
1101 	bool startup_check_entered;
1102 	bool dsp_reload;
1103 
1104 	/* mixer and effects related */
1105 	unsigned char dmic_ctl;
1106 	int cur_out_type;
1107 	int cur_mic_type;
1108 	long vnode_lvol[VNODES_COUNT];
1109 	long vnode_rvol[VNODES_COUNT];
1110 	long vnode_lswitch[VNODES_COUNT];
1111 	long vnode_rswitch[VNODES_COUNT];
1112 	long effects_switch[EFFECTS_COUNT];
1113 	long voicefx_val;
1114 	long cur_mic_boost;
1115 	/* ca0132_alt control related values */
1116 	unsigned char in_enum_val;
1117 	unsigned char out_enum_val;
1118 	unsigned char channel_cfg_val;
1119 	unsigned char speaker_range_val[2];
1120 	unsigned char mic_boost_enum_val;
1121 	unsigned char smart_volume_setting;
1122 	unsigned char bass_redirection_val;
1123 	long bass_redirect_xover_freq;
1124 	long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1125 	long xbass_xover_freq;
1126 	long eq_preset_val;
1127 	unsigned int tlv[4];
1128 	struct hda_vmaster_mute_hook vmaster_mute;
1129 	/* AE-5 Control values */
1130 	unsigned char ae5_headphone_gain_val;
1131 	unsigned char ae5_filter_val;
1132 	/* ZxR Control Values */
1133 	unsigned char zxr_gain_set;
1134 
1135 	struct hda_codec *codec;
1136 	struct delayed_work unsol_hp_work;
1137 
1138 #ifdef ENABLE_TUNING_CONTROLS
1139 	long cur_ctl_vals[TUNING_CTLS_COUNT];
1140 #endif
1141 	/*
1142 	 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1143 	 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1144 	 * things.
1145 	 */
1146 	bool use_pci_mmio;
1147 	void __iomem *mem_base;
1148 
1149 	/*
1150 	 * Whether or not to use the alt functions like alt_select_out,
1151 	 * alt_select_in, etc. Only used on desktop codecs for now, because of
1152 	 * surround sound support.
1153 	 */
1154 	bool use_alt_functions;
1155 
1156 	/*
1157 	 * Whether or not to use alt controls:	volume effect sliders, EQ
1158 	 * presets, smart volume presets, and new control names with FX prefix.
1159 	 * Renames PlayEnhancement and CrystalVoice too.
1160 	 */
1161 	bool use_alt_controls;
1162 };
1163 
1164 /*
1165  * CA0132 quirks table
1166  */
1167 enum {
1168 	QUIRK_ALIENWARE,
1169 	QUIRK_ALIENWARE_M17XR4,
1170 	QUIRK_SBZ,
1171 	QUIRK_ZXR,
1172 	QUIRK_ZXR_DBPRO,
1173 	QUIRK_R3DI,
1174 	QUIRK_R3D,
1175 	QUIRK_AE5,
1176 	QUIRK_AE7,
1177 	QUIRK_NONE = HDA_FIXUP_ID_NOT_SET,
1178 };
1179 
1180 #ifdef CONFIG_PCI
1181 #define ca0132_quirk(spec)		((spec)->codec->fixup_id)
1182 #define ca0132_use_pci_mmio(spec)	((spec)->use_pci_mmio)
1183 #define ca0132_use_alt_functions(spec)	((spec)->use_alt_functions)
1184 #define ca0132_use_alt_controls(spec)	((spec)->use_alt_controls)
1185 #else
1186 #define ca0132_quirk(spec)		({ (void)(spec); QUIRK_NONE; })
1187 #define ca0132_use_alt_functions(spec)	({ (void)(spec); false; })
1188 #define ca0132_use_pci_mmio(spec)	({ (void)(spec); false; })
1189 #define ca0132_use_alt_controls(spec)	({ (void)(spec); false; })
1190 #endif
1191 
1192 static const struct hda_pintbl alienware_pincfgs[] = {
1193 	{ 0x0b, 0x90170110 }, /* Builtin Speaker */
1194 	{ 0x0c, 0x411111f0 }, /* N/A */
1195 	{ 0x0d, 0x411111f0 }, /* N/A */
1196 	{ 0x0e, 0x411111f0 }, /* N/A */
1197 	{ 0x0f, 0x0321101f }, /* HP */
1198 	{ 0x10, 0x411111f0 }, /* Headset?  disabled for now */
1199 	{ 0x11, 0x03a11021 }, /* Mic */
1200 	{ 0x12, 0xd5a30140 }, /* Builtin Mic */
1201 	{ 0x13, 0x411111f0 }, /* N/A */
1202 	{ 0x18, 0x411111f0 }, /* N/A */
1203 	{}
1204 };
1205 
1206 /* Sound Blaster Z pin configs taken from Windows Driver */
1207 static const struct hda_pintbl sbz_pincfgs[] = {
1208 	{ 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1209 	{ 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1210 	{ 0x0d, 0x014510f0 }, /* Digital Out */
1211 	{ 0x0e, 0x01c510f0 }, /* SPDIF In */
1212 	{ 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1213 	{ 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1214 	{ 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1215 	{ 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1216 	{ 0x13, 0x908700f0 }, /* What U Hear In*/
1217 	{ 0x18, 0x50d000f0 }, /* N/A */
1218 	{}
1219 };
1220 
1221 /* Sound Blaster ZxR pin configs taken from Windows Driver */
1222 static const struct hda_pintbl zxr_pincfgs[] = {
1223 	{ 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1224 	{ 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1225 	{ 0x0d, 0x014510f0 }, /* Digital Out */
1226 	{ 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1227 	{ 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1228 	{ 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1229 	{ 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1230 	{ 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1231 	{ 0x13, 0x908700f0 }, /* What U Hear In*/
1232 	{ 0x18, 0x50d000f0 }, /* N/A */
1233 	{}
1234 };
1235 
1236 /* Recon3D pin configs taken from Windows Driver */
1237 static const struct hda_pintbl r3d_pincfgs[] = {
1238 	{ 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1239 	{ 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1240 	{ 0x0d, 0x014510f0 }, /* Digital Out */
1241 	{ 0x0e, 0x01c520f0 }, /* SPDIF In */
1242 	{ 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1243 	{ 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1244 	{ 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1245 	{ 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1246 	{ 0x13, 0x908700f0 }, /* What U Hear In*/
1247 	{ 0x18, 0x50d000f0 }, /* N/A */
1248 	{}
1249 };
1250 
1251 /* Sound Blaster AE-5 pin configs taken from Windows Driver */
1252 static const struct hda_pintbl ae5_pincfgs[] = {
1253 	{ 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1254 	{ 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1255 	{ 0x0d, 0x014510f0 }, /* Digital Out */
1256 	{ 0x0e, 0x01c510f0 }, /* SPDIF In */
1257 	{ 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1258 	{ 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1259 	{ 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1260 	{ 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1261 	{ 0x13, 0x908700f0 }, /* What U Hear In*/
1262 	{ 0x18, 0x50d000f0 }, /* N/A */
1263 	{}
1264 };
1265 
1266 /* Recon3D integrated pin configs taken from Windows Driver */
1267 static const struct hda_pintbl r3di_pincfgs[] = {
1268 	{ 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1269 	{ 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1270 	{ 0x0d, 0x014510f0 }, /* Digital Out */
1271 	{ 0x0e, 0x41c520f0 }, /* SPDIF In */
1272 	{ 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1273 	{ 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1274 	{ 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1275 	{ 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1276 	{ 0x13, 0x908700f0 }, /* What U Hear In*/
1277 	{ 0x18, 0x500000f0 }, /* N/A */
1278 	{}
1279 };
1280 
1281 static const struct hda_pintbl ae7_pincfgs[] = {
1282 	{ 0x0b, 0x01017010 },
1283 	{ 0x0c, 0x014510f0 },
1284 	{ 0x0d, 0x414510f0 },
1285 	{ 0x0e, 0x01c520f0 },
1286 	{ 0x0f, 0x01017114 },
1287 	{ 0x10, 0x01017011 },
1288 	{ 0x11, 0x018170ff },
1289 	{ 0x12, 0x01a170f0 },
1290 	{ 0x13, 0x908700f0 },
1291 	{ 0x18, 0x500000f0 },
1292 	{}
1293 };
1294 
1295 static const struct hda_quirk ca0132_quirks[] = {
1296 	SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1297 	SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1298 	SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1299 	SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1300 	SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1301 	SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1302 	SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1303 	SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1304 	SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1305 	SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1306 	SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1307 	SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1308 	SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI),
1309 	SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1310 	SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1311 	SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1312 	SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1313 	SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1314 	SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1315 	{}
1316 };
1317 
1318 static const struct hda_model_fixup ca0132_quirk_models[] = {
1319 	{ .id = QUIRK_ALIENWARE, .name = "alienware" },
1320 	{ .id = QUIRK_ALIENWARE_M17XR4, .name = "alienware-m17xr4" },
1321 	{ .id = QUIRK_SBZ, .name = "sbz" },
1322 	{ .id = QUIRK_ZXR, .name = "zxr" },
1323 	{ .id = QUIRK_ZXR_DBPRO, .name = "zxr-dbpro" },
1324 	{ .id = QUIRK_R3DI, .name = "r3di" },
1325 	{ .id = QUIRK_R3D, .name = "r3d" },
1326 	{ .id = QUIRK_AE5, .name = "ae5" },
1327 	{ .id = QUIRK_AE7, .name = "ae7" },
1328 	{}
1329 };
1330 
1331 /* Output selection quirk info structures. */
1332 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3
1333 #define MAX_QUIRK_SCP_SET_VALS 2
1334 struct ca0132_alt_out_set_info {
1335 	unsigned int dac2port; /* ParamID 0x0d value. */
1336 
1337 	bool has_hda_gpio;
1338 	char hda_gpio_pin;
1339 	char hda_gpio_set;
1340 
1341 	unsigned int mmio_gpio_count;
1342 	char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1343 	char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1344 
1345 	unsigned int scp_cmds_count;
1346 	unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS];
1347 	unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS];
1348 	unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS];
1349 
1350 	bool has_chipio_write;
1351 	unsigned int chipio_write_addr;
1352 	unsigned int chipio_write_data;
1353 };
1354 
1355 struct ca0132_alt_out_set_quirk_data {
1356 	int quirk_id;
1357 
1358 	bool has_headphone_gain;
1359 	bool is_ae_series;
1360 
1361 	struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS];
1362 };
1363 
1364 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = {
1365 	{ .quirk_id = QUIRK_R3DI,
1366 	  .has_headphone_gain = false,
1367 	  .is_ae_series       = false,
1368 	  .out_set_info = {
1369 		/* Speakers. */
1370 		{ .dac2port         = 0x24,
1371 		  .has_hda_gpio     = true,
1372 		  .hda_gpio_pin     = 2,
1373 		  .hda_gpio_set     = 1,
1374 		  .mmio_gpio_count  = 0,
1375 		  .scp_cmds_count   = 0,
1376 		  .has_chipio_write = false,
1377 		},
1378 		/* Headphones. */
1379 		{ .dac2port         = 0x21,
1380 		  .has_hda_gpio     = true,
1381 		  .hda_gpio_pin     = 2,
1382 		  .hda_gpio_set     = 0,
1383 		  .mmio_gpio_count  = 0,
1384 		  .scp_cmds_count   = 0,
1385 		  .has_chipio_write = false,
1386 		} },
1387 	},
1388 	{ .quirk_id = QUIRK_R3D,
1389 	  .has_headphone_gain = false,
1390 	  .is_ae_series       = false,
1391 	  .out_set_info = {
1392 		/* Speakers. */
1393 		{ .dac2port         = 0x24,
1394 		  .has_hda_gpio     = false,
1395 		  .mmio_gpio_count  = 1,
1396 		  .mmio_gpio_pin    = { 1 },
1397 		  .mmio_gpio_set    = { 1 },
1398 		  .scp_cmds_count   = 0,
1399 		  .has_chipio_write = false,
1400 		},
1401 		/* Headphones. */
1402 		{ .dac2port         = 0x21,
1403 		  .has_hda_gpio     = false,
1404 		  .mmio_gpio_count  = 1,
1405 		  .mmio_gpio_pin    = { 1 },
1406 		  .mmio_gpio_set    = { 0 },
1407 		  .scp_cmds_count   = 0,
1408 		  .has_chipio_write = false,
1409 		} },
1410 	},
1411 	{ .quirk_id = QUIRK_SBZ,
1412 	  .has_headphone_gain = false,
1413 	  .is_ae_series       = false,
1414 	  .out_set_info = {
1415 		/* Speakers. */
1416 		{ .dac2port         = 0x18,
1417 		  .has_hda_gpio     = false,
1418 		  .mmio_gpio_count  = 3,
1419 		  .mmio_gpio_pin    = { 7, 4, 1 },
1420 		  .mmio_gpio_set    = { 0, 1, 1 },
1421 		  .scp_cmds_count   = 0,
1422 		  .has_chipio_write = false, },
1423 		/* Headphones. */
1424 		{ .dac2port         = 0x12,
1425 		  .has_hda_gpio     = false,
1426 		  .mmio_gpio_count  = 3,
1427 		  .mmio_gpio_pin    = { 7, 4, 1 },
1428 		  .mmio_gpio_set    = { 1, 1, 0 },
1429 		  .scp_cmds_count   = 0,
1430 		  .has_chipio_write = false,
1431 		} },
1432 	},
1433 	{ .quirk_id = QUIRK_ZXR,
1434 	  .has_headphone_gain = true,
1435 	  .is_ae_series       = false,
1436 	  .out_set_info = {
1437 		/* Speakers. */
1438 		{ .dac2port         = 0x24,
1439 		  .has_hda_gpio     = false,
1440 		  .mmio_gpio_count  = 3,
1441 		  .mmio_gpio_pin    = { 2, 3, 5 },
1442 		  .mmio_gpio_set    = { 1, 1, 0 },
1443 		  .scp_cmds_count   = 0,
1444 		  .has_chipio_write = false,
1445 		},
1446 		/* Headphones. */
1447 		{ .dac2port         = 0x21,
1448 		  .has_hda_gpio     = false,
1449 		  .mmio_gpio_count  = 3,
1450 		  .mmio_gpio_pin    = { 2, 3, 5 },
1451 		  .mmio_gpio_set    = { 0, 1, 1 },
1452 		  .scp_cmds_count   = 0,
1453 		  .has_chipio_write = false,
1454 		} },
1455 	},
1456 	{ .quirk_id = QUIRK_AE5,
1457 	  .has_headphone_gain = true,
1458 	  .is_ae_series       = true,
1459 	  .out_set_info = {
1460 		/* Speakers. */
1461 		{ .dac2port          = 0xa4,
1462 		  .has_hda_gpio      = false,
1463 		  .mmio_gpio_count   = 0,
1464 		  .scp_cmds_count    = 2,
1465 		  .scp_cmd_mid       = { 0x96, 0x96 },
1466 		  .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1467 					 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1468 		  .scp_cmd_val       = { FLOAT_ZERO, FLOAT_ZERO },
1469 		  .has_chipio_write  = true,
1470 		  .chipio_write_addr = 0x0018b03c,
1471 		  .chipio_write_data = 0x00000012
1472 		},
1473 		/* Headphones. */
1474 		{ .dac2port          = 0xa1,
1475 		  .has_hda_gpio      = false,
1476 		  .mmio_gpio_count   = 0,
1477 		  .scp_cmds_count    = 2,
1478 		  .scp_cmd_mid       = { 0x96, 0x96 },
1479 		  .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1480 					 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1481 		  .scp_cmd_val       = { FLOAT_ONE, FLOAT_ONE },
1482 		  .has_chipio_write  = true,
1483 		  .chipio_write_addr = 0x0018b03c,
1484 		  .chipio_write_data = 0x00000012
1485 		} },
1486 	},
1487 	{ .quirk_id = QUIRK_AE7,
1488 	  .has_headphone_gain = true,
1489 	  .is_ae_series       = true,
1490 	  .out_set_info = {
1491 		/* Speakers. */
1492 		{ .dac2port          = 0x58,
1493 		  .has_hda_gpio      = false,
1494 		  .mmio_gpio_count   = 1,
1495 		  .mmio_gpio_pin     = { 0 },
1496 		  .mmio_gpio_set     = { 1 },
1497 		  .scp_cmds_count    = 2,
1498 		  .scp_cmd_mid       = { 0x96, 0x96 },
1499 		  .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1500 					 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1501 		  .scp_cmd_val       = { FLOAT_ZERO, FLOAT_ZERO },
1502 		  .has_chipio_write  = true,
1503 		  .chipio_write_addr = 0x0018b03c,
1504 		  .chipio_write_data = 0x00000000
1505 		},
1506 		/* Headphones. */
1507 		{ .dac2port          = 0x58,
1508 		  .has_hda_gpio      = false,
1509 		  .mmio_gpio_count   = 1,
1510 		  .mmio_gpio_pin     = { 0 },
1511 		  .mmio_gpio_set     = { 1 },
1512 		  .scp_cmds_count    = 2,
1513 		  .scp_cmd_mid       = { 0x96, 0x96 },
1514 		  .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1515 					 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1516 		  .scp_cmd_val       = { FLOAT_ONE, FLOAT_ONE },
1517 		  .has_chipio_write  = true,
1518 		  .chipio_write_addr = 0x0018b03c,
1519 		  .chipio_write_data = 0x00000010
1520 		} },
1521 	}
1522 };
1523 
1524 /*
1525  * CA0132 codec access
1526  */
1527 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1528 		unsigned int verb, unsigned int parm, unsigned int *res)
1529 {
1530 	unsigned int response;
1531 	response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1532 	*res = response;
1533 
1534 	return ((response == -1) ? -1 : 0);
1535 }
1536 
1537 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1538 		unsigned short converter_format, unsigned int *res)
1539 {
1540 	return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1541 				converter_format & 0xffff, res);
1542 }
1543 
1544 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1545 				hda_nid_t nid, unsigned char stream,
1546 				unsigned char channel, unsigned int *res)
1547 {
1548 	unsigned char converter_stream_channel = 0;
1549 
1550 	converter_stream_channel = (stream << 4) | (channel & 0x0f);
1551 	return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1552 				converter_stream_channel, res);
1553 }
1554 
1555 /* Chip access helper function */
1556 static int chipio_send(struct hda_codec *codec,
1557 		       unsigned int reg,
1558 		       unsigned int data)
1559 {
1560 	unsigned int res;
1561 	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1562 
1563 	/* send bits of data specified by reg */
1564 	do {
1565 		res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1566 					 reg, data);
1567 		if (res == VENDOR_STATUS_CHIPIO_OK)
1568 			return 0;
1569 		msleep(20);
1570 	} while (time_before(jiffies, timeout));
1571 
1572 	return -EIO;
1573 }
1574 
1575 /*
1576  * Write chip address through the vendor widget -- NOT protected by the Mutex!
1577  */
1578 static int chipio_write_address(struct hda_codec *codec,
1579 				unsigned int chip_addx)
1580 {
1581 	struct ca0132_spec *spec = codec->spec;
1582 	int res;
1583 
1584 	if (spec->curr_chip_addx == chip_addx)
1585 			return 0;
1586 
1587 	/* send low 16 bits of the address */
1588 	res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1589 			  chip_addx & 0xffff);
1590 
1591 	if (res != -EIO) {
1592 		/* send high 16 bits of the address */
1593 		res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1594 				  chip_addx >> 16);
1595 	}
1596 
1597 	spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1598 
1599 	return res;
1600 }
1601 
1602 /*
1603  * Write data through the vendor widget -- NOT protected by the Mutex!
1604  */
1605 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1606 {
1607 	struct ca0132_spec *spec = codec->spec;
1608 	int res;
1609 
1610 	/* send low 16 bits of the data */
1611 	res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1612 
1613 	if (res != -EIO) {
1614 		/* send high 16 bits of the data */
1615 		res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1616 				  data >> 16);
1617 	}
1618 
1619 	/*If no error encountered, automatically increment the address
1620 	as per chip behaviour*/
1621 	spec->curr_chip_addx = (res != -EIO) ?
1622 					(spec->curr_chip_addx + 4) : ~0U;
1623 	return res;
1624 }
1625 
1626 /*
1627  * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1628  */
1629 static int chipio_write_data_multiple(struct hda_codec *codec,
1630 				      const u32 *data,
1631 				      unsigned int count)
1632 {
1633 	int status = 0;
1634 
1635 	if (data == NULL) {
1636 		codec_dbg(codec, "chipio_write_data null ptr\n");
1637 		return -EINVAL;
1638 	}
1639 
1640 	while ((count-- != 0) && (status == 0))
1641 		status = chipio_write_data(codec, *data++);
1642 
1643 	return status;
1644 }
1645 
1646 
1647 /*
1648  * Read data through the vendor widget -- NOT protected by the Mutex!
1649  */
1650 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1651 {
1652 	struct ca0132_spec *spec = codec->spec;
1653 	int res;
1654 
1655 	/* post read */
1656 	res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1657 
1658 	if (res != -EIO) {
1659 		/* read status */
1660 		res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1661 	}
1662 
1663 	if (res != -EIO) {
1664 		/* read data */
1665 		*data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1666 					   VENDOR_CHIPIO_HIC_READ_DATA,
1667 					   0);
1668 	}
1669 
1670 	/*If no error encountered, automatically increment the address
1671 	as per chip behaviour*/
1672 	spec->curr_chip_addx = (res != -EIO) ?
1673 					(spec->curr_chip_addx + 4) : ~0U;
1674 	return res;
1675 }
1676 
1677 /*
1678  * Write given value to the given address through the chip I/O widget.
1679  * protected by the Mutex
1680  */
1681 static int chipio_write(struct hda_codec *codec,
1682 		unsigned int chip_addx, const unsigned int data)
1683 {
1684 	struct ca0132_spec *spec = codec->spec;
1685 	int err;
1686 
1687 	guard(mutex)(&spec->chipio_mutex);
1688 
1689 	/* write the address, and if successful proceed to write data */
1690 	err = chipio_write_address(codec, chip_addx);
1691 	if (err < 0)
1692 		return err;
1693 
1694 	return chipio_write_data(codec, data);
1695 }
1696 
1697 /*
1698  * Write given value to the given address through the chip I/O widget.
1699  * not protected by the Mutex
1700  */
1701 static int chipio_write_no_mutex(struct hda_codec *codec,
1702 		unsigned int chip_addx, const unsigned int data)
1703 {
1704 	int err;
1705 
1706 
1707 	/* write the address, and if successful proceed to write data */
1708 	err = chipio_write_address(codec, chip_addx);
1709 	if (err < 0)
1710 		goto exit;
1711 
1712 	err = chipio_write_data(codec, data);
1713 	if (err < 0)
1714 		goto exit;
1715 
1716 exit:
1717 	return err;
1718 }
1719 
1720 /*
1721  * Write multiple values to the given address through the chip I/O widget.
1722  * protected by the Mutex
1723  */
1724 static int chipio_write_multiple(struct hda_codec *codec,
1725 				 u32 chip_addx,
1726 				 const u32 *data,
1727 				 unsigned int count)
1728 {
1729 	struct ca0132_spec *spec = codec->spec;
1730 	int status;
1731 
1732 	guard(mutex)(&spec->chipio_mutex);
1733 	status = chipio_write_address(codec, chip_addx);
1734 	if (status < 0)
1735 		return status;
1736 
1737 	return chipio_write_data_multiple(codec, data, count);
1738 }
1739 
1740 /*
1741  * Read the given address through the chip I/O widget
1742  * protected by the Mutex
1743  */
1744 static int chipio_read(struct hda_codec *codec,
1745 		unsigned int chip_addx, unsigned int *data)
1746 {
1747 	struct ca0132_spec *spec = codec->spec;
1748 	int err;
1749 
1750 	guard(mutex)(&spec->chipio_mutex);
1751 
1752 	/* write the address, and if successful proceed to write data */
1753 	err = chipio_write_address(codec, chip_addx);
1754 	if (err < 0)
1755 		return err;
1756 
1757 	return chipio_read_data(codec, data);
1758 }
1759 
1760 /*
1761  * Set chip control flags through the chip I/O widget.
1762  */
1763 static void chipio_set_control_flag(struct hda_codec *codec,
1764 				    enum control_flag_id flag_id,
1765 				    bool flag_state)
1766 {
1767 	unsigned int val;
1768 	unsigned int flag_bit;
1769 
1770 	flag_bit = (flag_state ? 1 : 0);
1771 	val = (flag_bit << 7) | (flag_id);
1772 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1773 			    VENDOR_CHIPIO_FLAG_SET, val);
1774 }
1775 
1776 /*
1777  * Set chip parameters through the chip I/O widget.
1778  */
1779 static void chipio_set_control_param(struct hda_codec *codec,
1780 		enum control_param_id param_id, int param_val)
1781 {
1782 	struct ca0132_spec *spec = codec->spec;
1783 	int val;
1784 
1785 	if ((param_id < 32) && (param_val < 8)) {
1786 		val = (param_val << 5) | (param_id);
1787 		snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1788 				    VENDOR_CHIPIO_PARAM_SET, val);
1789 	} else {
1790 		guard(mutex)(&spec->chipio_mutex);
1791 		if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1792 			snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1793 					    VENDOR_CHIPIO_PARAM_EX_ID_SET,
1794 					    param_id);
1795 			snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1796 					    VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1797 					    param_val);
1798 		}
1799 	}
1800 }
1801 
1802 /*
1803  * Set chip parameters through the chip I/O widget. NO MUTEX.
1804  */
1805 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1806 		enum control_param_id param_id, int param_val)
1807 {
1808 	int val;
1809 
1810 	if ((param_id < 32) && (param_val < 8)) {
1811 		val = (param_val << 5) | (param_id);
1812 		snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1813 				    VENDOR_CHIPIO_PARAM_SET, val);
1814 	} else {
1815 		if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1816 			snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1817 					    VENDOR_CHIPIO_PARAM_EX_ID_SET,
1818 					    param_id);
1819 			snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1820 					    VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1821 					    param_val);
1822 		}
1823 	}
1824 }
1825 /*
1826  * Connect stream to a source point, and then connect
1827  * that source point to a destination point.
1828  */
1829 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1830 				int streamid, int source_point, int dest_point)
1831 {
1832 	chipio_set_control_param_no_mutex(codec,
1833 			CONTROL_PARAM_STREAM_ID, streamid);
1834 	chipio_set_control_param_no_mutex(codec,
1835 			CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1836 	chipio_set_control_param_no_mutex(codec,
1837 			CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1838 }
1839 
1840 /*
1841  * Set number of channels in the selected stream.
1842  */
1843 static void chipio_set_stream_channels(struct hda_codec *codec,
1844 				int streamid, unsigned int channels)
1845 {
1846 	chipio_set_control_param_no_mutex(codec,
1847 			CONTROL_PARAM_STREAM_ID, streamid);
1848 	chipio_set_control_param_no_mutex(codec,
1849 			CONTROL_PARAM_STREAMS_CHANNELS, channels);
1850 }
1851 
1852 /*
1853  * Enable/Disable audio stream.
1854  */
1855 static void chipio_set_stream_control(struct hda_codec *codec,
1856 				int streamid, int enable)
1857 {
1858 	chipio_set_control_param_no_mutex(codec,
1859 			CONTROL_PARAM_STREAM_ID, streamid);
1860 	chipio_set_control_param_no_mutex(codec,
1861 			CONTROL_PARAM_STREAM_CONTROL, enable);
1862 }
1863 
1864 /*
1865  * Get ChipIO audio stream's status.
1866  */
1867 static void chipio_get_stream_control(struct hda_codec *codec,
1868 				int streamid, unsigned int *enable)
1869 {
1870 	chipio_set_control_param_no_mutex(codec,
1871 			CONTROL_PARAM_STREAM_ID, streamid);
1872 	*enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1873 			   VENDOR_CHIPIO_PARAM_GET,
1874 			   CONTROL_PARAM_STREAM_CONTROL);
1875 }
1876 
1877 /*
1878  * Set sampling rate of the connection point. NO MUTEX.
1879  */
1880 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1881 				int connid, enum ca0132_sample_rate rate)
1882 {
1883 	chipio_set_control_param_no_mutex(codec,
1884 			CONTROL_PARAM_CONN_POINT_ID, connid);
1885 	chipio_set_control_param_no_mutex(codec,
1886 			CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1887 }
1888 
1889 /*
1890  * Set sampling rate of the connection point.
1891  */
1892 static void chipio_set_conn_rate(struct hda_codec *codec,
1893 				int connid, enum ca0132_sample_rate rate)
1894 {
1895 	chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1896 	chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1897 				 rate);
1898 }
1899 
1900 /*
1901  * Writes to the 8051's internal address space directly instead of indirectly,
1902  * giving access to the special function registers located at addresses
1903  * 0x80-0xFF.
1904  */
1905 static void chipio_8051_write_direct(struct hda_codec *codec,
1906 		unsigned int addr, unsigned int data)
1907 {
1908 	unsigned int verb;
1909 
1910 	verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1911 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1912 }
1913 
1914 /*
1915  * Writes to the 8051's exram, which has 16-bits of address space.
1916  * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff.
1917  * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by
1918  * setting the pmem bank selection SFR.
1919  * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff
1920  * being writable.
1921  */
1922 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr)
1923 {
1924 	unsigned int tmp;
1925 
1926 	/* Lower 8-bits. */
1927 	tmp = addr & 0xff;
1928 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1929 			    VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp);
1930 
1931 	/* Upper 8-bits. */
1932 	tmp = (addr >> 8) & 0xff;
1933 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1934 			    VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp);
1935 }
1936 
1937 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data)
1938 {
1939 	/* 8-bits of data. */
1940 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1941 			    VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff);
1942 }
1943 
1944 static unsigned int chipio_8051_get_data(struct hda_codec *codec)
1945 {
1946 	return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1947 				   VENDOR_CHIPIO_8051_DATA_READ, 0);
1948 }
1949 
1950 /* PLL_PMU writes share the lower address register of the 8051 exram writes. */
1951 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data)
1952 {
1953 	/* 8-bits of data. */
1954 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1955 			    VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff);
1956 }
1957 
1958 static void chipio_8051_write_exram(struct hda_codec *codec,
1959 		unsigned int addr, unsigned int data)
1960 {
1961 	struct ca0132_spec *spec = codec->spec;
1962 
1963 	guard(mutex)(&spec->chipio_mutex);
1964 
1965 	chipio_8051_set_address(codec, addr);
1966 	chipio_8051_set_data(codec, data);
1967 }
1968 
1969 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec,
1970 		unsigned int addr, unsigned int data)
1971 {
1972 	chipio_8051_set_address(codec, addr);
1973 	chipio_8051_set_data(codec, data);
1974 }
1975 
1976 /* Readback data from the 8051's exram. No mutex. */
1977 static void chipio_8051_read_exram(struct hda_codec *codec,
1978 		unsigned int addr, unsigned int *data)
1979 {
1980 	chipio_8051_set_address(codec, addr);
1981 	*data = chipio_8051_get_data(codec);
1982 }
1983 
1984 static void chipio_8051_write_pll_pmu(struct hda_codec *codec,
1985 		unsigned int addr, unsigned int data)
1986 {
1987 	struct ca0132_spec *spec = codec->spec;
1988 
1989 	guard(mutex)(&spec->chipio_mutex);
1990 
1991 	chipio_8051_set_address(codec, addr & 0xff);
1992 	chipio_8051_set_data_pll(codec, data);
1993 }
1994 
1995 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec,
1996 		unsigned int addr, unsigned int data)
1997 {
1998 	chipio_8051_set_address(codec, addr & 0xff);
1999 	chipio_8051_set_data_pll(codec, data);
2000 }
2001 
2002 /*
2003  * Enable clocks.
2004  */
2005 static void chipio_enable_clocks(struct hda_codec *codec)
2006 {
2007 	struct ca0132_spec *spec = codec->spec;
2008 
2009 	guard(mutex)(&spec->chipio_mutex);
2010 
2011 	chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff);
2012 	chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b);
2013 	chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff);
2014 }
2015 
2016 /*
2017  * CA0132 DSP IO stuffs
2018  */
2019 static int dspio_send(struct hda_codec *codec, unsigned int reg,
2020 		      unsigned int data)
2021 {
2022 	int res;
2023 	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2024 
2025 	/* send bits of data specified by reg to dsp */
2026 	do {
2027 		res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
2028 		if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
2029 			return res;
2030 		msleep(20);
2031 	} while (time_before(jiffies, timeout));
2032 
2033 	return -EIO;
2034 }
2035 
2036 /*
2037  * Wait for DSP to be ready for commands
2038  */
2039 static void dspio_write_wait(struct hda_codec *codec)
2040 {
2041 	int status;
2042 	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2043 
2044 	do {
2045 		status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2046 						VENDOR_DSPIO_STATUS, 0);
2047 		if ((status == VENDOR_STATUS_DSPIO_OK) ||
2048 		    (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
2049 			break;
2050 		msleep(1);
2051 	} while (time_before(jiffies, timeout));
2052 }
2053 
2054 /*
2055  * Write SCP data to DSP
2056  */
2057 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
2058 {
2059 	struct ca0132_spec *spec = codec->spec;
2060 	int status;
2061 
2062 	dspio_write_wait(codec);
2063 
2064 	guard(mutex)(&spec->chipio_mutex);
2065 	status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
2066 			    scp_data & 0xffff);
2067 	if (status < 0)
2068 		return status;
2069 
2070 	status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
2071 				    scp_data >> 16);
2072 	if (status < 0)
2073 		return status;
2074 
2075 	/* OK, now check if the write itself has executed*/
2076 	status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2077 				    VENDOR_DSPIO_STATUS, 0);
2078 
2079 	return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
2080 			-EIO : 0;
2081 }
2082 
2083 /*
2084  * Write multiple SCP data to DSP
2085  */
2086 static int dspio_write_multiple(struct hda_codec *codec,
2087 				unsigned int *buffer, unsigned int size)
2088 {
2089 	int status = 0;
2090 	unsigned int count;
2091 
2092 	if (buffer == NULL)
2093 		return -EINVAL;
2094 
2095 	count = 0;
2096 	while (count < size) {
2097 		status = dspio_write(codec, *buffer++);
2098 		if (status != 0)
2099 			break;
2100 		count++;
2101 	}
2102 
2103 	return status;
2104 }
2105 
2106 static int dspio_read(struct hda_codec *codec, unsigned int *data)
2107 {
2108 	int status;
2109 
2110 	status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
2111 	if (status == -EIO)
2112 		return status;
2113 
2114 	status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
2115 	if (status == -EIO ||
2116 	    status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
2117 		return -EIO;
2118 
2119 	*data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2120 				   VENDOR_DSPIO_SCP_READ_DATA, 0);
2121 
2122 	return 0;
2123 }
2124 
2125 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
2126 			       unsigned int *buf_size, unsigned int size_count)
2127 {
2128 	int status = 0;
2129 	unsigned int size = *buf_size;
2130 	unsigned int count;
2131 	unsigned int skip_count;
2132 	unsigned int dummy;
2133 
2134 	if (buffer == NULL)
2135 		return -1;
2136 
2137 	count = 0;
2138 	while (count < size && count < size_count) {
2139 		status = dspio_read(codec, buffer++);
2140 		if (status != 0)
2141 			break;
2142 		count++;
2143 	}
2144 
2145 	skip_count = count;
2146 	if (status == 0) {
2147 		while (skip_count < size) {
2148 			status = dspio_read(codec, &dummy);
2149 			if (status != 0)
2150 				break;
2151 			skip_count++;
2152 		}
2153 	}
2154 	*buf_size = count;
2155 
2156 	return status;
2157 }
2158 
2159 /*
2160  * Construct the SCP header using corresponding fields
2161  */
2162 static inline unsigned int
2163 make_scp_header(unsigned int target_id, unsigned int source_id,
2164 		unsigned int get_flag, unsigned int req,
2165 		unsigned int device_flag, unsigned int resp_flag,
2166 		unsigned int error_flag, unsigned int data_size)
2167 {
2168 	unsigned int header = 0;
2169 
2170 	header = (data_size & 0x1f) << 27;
2171 	header |= (error_flag & 0x01) << 26;
2172 	header |= (resp_flag & 0x01) << 25;
2173 	header |= (device_flag & 0x01) << 24;
2174 	header |= (req & 0x7f) << 17;
2175 	header |= (get_flag & 0x01) << 16;
2176 	header |= (source_id & 0xff) << 8;
2177 	header |= target_id & 0xff;
2178 
2179 	return header;
2180 }
2181 
2182 /*
2183  * Extract corresponding fields from SCP header
2184  */
2185 static inline void
2186 extract_scp_header(unsigned int header,
2187 		   unsigned int *target_id, unsigned int *source_id,
2188 		   unsigned int *get_flag, unsigned int *req,
2189 		   unsigned int *device_flag, unsigned int *resp_flag,
2190 		   unsigned int *error_flag, unsigned int *data_size)
2191 {
2192 	if (data_size)
2193 		*data_size = (header >> 27) & 0x1f;
2194 	if (error_flag)
2195 		*error_flag = (header >> 26) & 0x01;
2196 	if (resp_flag)
2197 		*resp_flag = (header >> 25) & 0x01;
2198 	if (device_flag)
2199 		*device_flag = (header >> 24) & 0x01;
2200 	if (req)
2201 		*req = (header >> 17) & 0x7f;
2202 	if (get_flag)
2203 		*get_flag = (header >> 16) & 0x01;
2204 	if (source_id)
2205 		*source_id = (header >> 8) & 0xff;
2206 	if (target_id)
2207 		*target_id = header & 0xff;
2208 }
2209 
2210 #define SCP_MAX_DATA_WORDS  (16)
2211 
2212 /* Structure to contain any SCP message */
2213 struct scp_msg {
2214 	unsigned int hdr;
2215 	unsigned int data[SCP_MAX_DATA_WORDS];
2216 };
2217 
2218 static void dspio_clear_response_queue(struct hda_codec *codec)
2219 {
2220 	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2221 	unsigned int dummy = 0;
2222 	int status;
2223 
2224 	/* clear all from the response queue */
2225 	do {
2226 		status = dspio_read(codec, &dummy);
2227 	} while (status == 0 && time_before(jiffies, timeout));
2228 }
2229 
2230 static int dspio_get_response_data(struct hda_codec *codec)
2231 {
2232 	struct ca0132_spec *spec = codec->spec;
2233 	unsigned int data = 0;
2234 	unsigned int count;
2235 
2236 	if (dspio_read(codec, &data) < 0)
2237 		return -EIO;
2238 
2239 	if ((data & 0x00ffffff) == spec->wait_scp_header) {
2240 		spec->scp_resp_header = data;
2241 		spec->scp_resp_count = data >> 27;
2242 		count = spec->wait_num_data;
2243 		dspio_read_multiple(codec, spec->scp_resp_data,
2244 				    &spec->scp_resp_count, count);
2245 		return 0;
2246 	}
2247 
2248 	return -EIO;
2249 }
2250 
2251 /*
2252  * Send SCP message to DSP
2253  */
2254 static int dspio_send_scp_message(struct hda_codec *codec,
2255 				  unsigned char *send_buf,
2256 				  unsigned int send_buf_size,
2257 				  unsigned char *return_buf,
2258 				  unsigned int return_buf_size,
2259 				  unsigned int *bytes_returned)
2260 {
2261 	struct ca0132_spec *spec = codec->spec;
2262 	int status;
2263 	unsigned int scp_send_size = 0;
2264 	unsigned int total_size;
2265 	bool waiting_for_resp = false;
2266 	unsigned int header;
2267 	struct scp_msg *ret_msg;
2268 	unsigned int resp_src_id, resp_target_id;
2269 	unsigned int data_size, src_id, target_id, get_flag, device_flag;
2270 
2271 	if (bytes_returned)
2272 		*bytes_returned = 0;
2273 
2274 	/* get scp header from buffer */
2275 	header = *((unsigned int *)send_buf);
2276 	extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
2277 			   &device_flag, NULL, NULL, &data_size);
2278 	scp_send_size = data_size + 1;
2279 	total_size = (scp_send_size * 4);
2280 
2281 	if (send_buf_size < total_size)
2282 		return -EINVAL;
2283 
2284 	if (get_flag || device_flag) {
2285 		if (!return_buf || return_buf_size < 4 || !bytes_returned)
2286 			return -EINVAL;
2287 
2288 		spec->wait_scp_header = *((unsigned int *)send_buf);
2289 
2290 		/* swap source id with target id */
2291 		resp_target_id = src_id;
2292 		resp_src_id = target_id;
2293 		spec->wait_scp_header &= 0xffff0000;
2294 		spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
2295 		spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
2296 		spec->wait_scp = 1;
2297 		waiting_for_resp = true;
2298 	}
2299 
2300 	status = dspio_write_multiple(codec, (unsigned int *)send_buf,
2301 				      scp_send_size);
2302 	if (status < 0) {
2303 		spec->wait_scp = 0;
2304 		return status;
2305 	}
2306 
2307 	if (waiting_for_resp) {
2308 		unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2309 		memset(return_buf, 0, return_buf_size);
2310 		do {
2311 			msleep(20);
2312 		} while (spec->wait_scp && time_before(jiffies, timeout));
2313 		waiting_for_resp = false;
2314 		if (!spec->wait_scp) {
2315 			ret_msg = (struct scp_msg *)return_buf;
2316 			memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
2317 			memcpy(&ret_msg->data, spec->scp_resp_data,
2318 			       spec->wait_num_data);
2319 			*bytes_returned = (spec->scp_resp_count + 1) * 4;
2320 			status = 0;
2321 		} else {
2322 			status = -EIO;
2323 		}
2324 		spec->wait_scp = 0;
2325 	}
2326 
2327 	return status;
2328 }
2329 
2330 /**
2331  * dspio_scp - Prepare and send the SCP message to DSP
2332  * @codec: the HDA codec
2333  * @mod_id: ID of the DSP module to send the command
2334  * @src_id: ID of the source
2335  * @req: ID of request to send to the DSP module
2336  * @dir: SET or GET
2337  * @data: pointer to the data to send with the request, request specific
2338  * @len: length of the data, in bytes
2339  * @reply: point to the buffer to hold data returned for a reply
2340  * @reply_len: length of the reply buffer returned from GET
2341  *
2342  * Returns zero or a negative error code.
2343  */
2344 static int dspio_scp(struct hda_codec *codec,
2345 		int mod_id, int src_id, int req, int dir, const void *data,
2346 		unsigned int len, void *reply, unsigned int *reply_len)
2347 {
2348 	int status = 0;
2349 	struct scp_msg scp_send, scp_reply;
2350 	unsigned int ret_bytes, send_size, ret_size;
2351 	unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
2352 	unsigned int reply_data_size;
2353 
2354 	memset(&scp_send, 0, sizeof(scp_send));
2355 	memset(&scp_reply, 0, sizeof(scp_reply));
2356 
2357 	if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
2358 		return -EINVAL;
2359 
2360 	if (dir == SCP_GET && reply == NULL) {
2361 		codec_dbg(codec, "dspio_scp get but has no buffer\n");
2362 		return -EINVAL;
2363 	}
2364 
2365 	if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
2366 		codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
2367 		return -EINVAL;
2368 	}
2369 
2370 	scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
2371 				       0, 0, 0, len/sizeof(unsigned int));
2372 	if (data != NULL && len > 0) {
2373 		len = min((unsigned int)(sizeof(scp_send.data)), len);
2374 		memcpy(scp_send.data, data, len);
2375 	}
2376 
2377 	ret_bytes = 0;
2378 	send_size = sizeof(unsigned int) + len;
2379 	status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
2380 					send_size, (unsigned char *)&scp_reply,
2381 					sizeof(scp_reply), &ret_bytes);
2382 
2383 	if (status < 0) {
2384 		codec_dbg(codec, "dspio_scp: send scp msg failed\n");
2385 		return status;
2386 	}
2387 
2388 	/* extract send and reply headers members */
2389 	extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
2390 			   NULL, NULL, NULL, NULL, NULL);
2391 	extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
2392 			   &reply_resp_flag, &reply_error_flag,
2393 			   &reply_data_size);
2394 
2395 	if (!send_get_flag)
2396 		return 0;
2397 
2398 	if (reply_resp_flag && !reply_error_flag) {
2399 		ret_size = (ret_bytes - sizeof(scp_reply.hdr))
2400 					/ sizeof(unsigned int);
2401 
2402 		if (*reply_len < ret_size*sizeof(unsigned int)) {
2403 			codec_dbg(codec, "reply too long for buf\n");
2404 			return -EINVAL;
2405 		} else if (ret_size != reply_data_size) {
2406 			codec_dbg(codec, "RetLen and HdrLen .NE.\n");
2407 			return -EINVAL;
2408 		} else if (!reply) {
2409 			codec_dbg(codec, "NULL reply\n");
2410 			return -EINVAL;
2411 		} else {
2412 			*reply_len = ret_size*sizeof(unsigned int);
2413 			memcpy(reply, scp_reply.data, *reply_len);
2414 		}
2415 	} else {
2416 		codec_dbg(codec, "reply ill-formed or errflag set\n");
2417 		return -EIO;
2418 	}
2419 
2420 	return status;
2421 }
2422 
2423 /*
2424  * Set DSP parameters
2425  */
2426 static int dspio_set_param(struct hda_codec *codec, int mod_id,
2427 			int src_id, int req, const void *data, unsigned int len)
2428 {
2429 	return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2430 			NULL);
2431 }
2432 
2433 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
2434 			int req, const unsigned int data)
2435 {
2436 	return dspio_set_param(codec, mod_id, 0x20, req, &data,
2437 			sizeof(unsigned int));
2438 }
2439 
2440 /*
2441  * Allocate a DSP DMA channel via an SCP message
2442  */
2443 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2444 {
2445 	int status = 0;
2446 	unsigned int size = sizeof(*dma_chan);
2447 
2448 	codec_dbg(codec, "     dspio_alloc_dma_chan() -- begin\n");
2449 	status = dspio_scp(codec, MASTERCONTROL, 0x20,
2450 			MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2451 			dma_chan, &size);
2452 
2453 	if (status < 0) {
2454 		codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
2455 		return status;
2456 	}
2457 
2458 	if ((*dma_chan + 1) == 0) {
2459 		codec_dbg(codec, "no free dma channels to allocate\n");
2460 		return -EBUSY;
2461 	}
2462 
2463 	codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2464 	codec_dbg(codec, "     dspio_alloc_dma_chan() -- complete\n");
2465 
2466 	return status;
2467 }
2468 
2469 /*
2470  * Free a DSP DMA via an SCP message
2471  */
2472 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2473 {
2474 	int status = 0;
2475 	unsigned int dummy = 0;
2476 
2477 	codec_dbg(codec, "     dspio_free_dma_chan() -- begin\n");
2478 	codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
2479 
2480 	status = dspio_scp(codec, MASTERCONTROL, 0x20,
2481 			MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2482 			sizeof(dma_chan), NULL, &dummy);
2483 
2484 	if (status < 0) {
2485 		codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
2486 		return status;
2487 	}
2488 
2489 	codec_dbg(codec, "     dspio_free_dma_chan() -- complete\n");
2490 
2491 	return status;
2492 }
2493 
2494 /*
2495  * (Re)start the DSP
2496  */
2497 static int dsp_set_run_state(struct hda_codec *codec)
2498 {
2499 	unsigned int dbg_ctrl_reg;
2500 	unsigned int halt_state;
2501 	int err;
2502 
2503 	err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2504 	if (err < 0)
2505 		return err;
2506 
2507 	halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2508 		      DSP_DBGCNTL_STATE_LOBIT;
2509 
2510 	if (halt_state != 0) {
2511 		dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2512 				  DSP_DBGCNTL_SS_MASK);
2513 		err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2514 				   dbg_ctrl_reg);
2515 		if (err < 0)
2516 			return err;
2517 
2518 		dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2519 				DSP_DBGCNTL_EXEC_MASK;
2520 		err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2521 				   dbg_ctrl_reg);
2522 		if (err < 0)
2523 			return err;
2524 	}
2525 
2526 	return 0;
2527 }
2528 
2529 /*
2530  * Reset the DSP
2531  */
2532 static int dsp_reset(struct hda_codec *codec)
2533 {
2534 	unsigned int res;
2535 	int retry = 20;
2536 
2537 	codec_dbg(codec, "dsp_reset\n");
2538 	do {
2539 		res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2540 		retry--;
2541 	} while (res == -EIO && retry);
2542 
2543 	if (!retry) {
2544 		codec_dbg(codec, "dsp_reset timeout\n");
2545 		return -EIO;
2546 	}
2547 
2548 	return 0;
2549 }
2550 
2551 /*
2552  * Convert chip address to DSP address
2553  */
2554 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2555 					bool *code, bool *yram)
2556 {
2557 	*code = *yram = false;
2558 
2559 	if (UC_RANGE(chip_addx, 1)) {
2560 		*code = true;
2561 		return UC_OFF(chip_addx);
2562 	} else if (X_RANGE_ALL(chip_addx, 1)) {
2563 		return X_OFF(chip_addx);
2564 	} else if (Y_RANGE_ALL(chip_addx, 1)) {
2565 		*yram = true;
2566 		return Y_OFF(chip_addx);
2567 	}
2568 
2569 	return INVALID_CHIP_ADDRESS;
2570 }
2571 
2572 /*
2573  * Check if the DSP DMA is active
2574  */
2575 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2576 {
2577 	unsigned int dma_chnlstart_reg;
2578 
2579 	chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2580 
2581 	return ((dma_chnlstart_reg & (1 <<
2582 			(DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2583 }
2584 
2585 static int dsp_dma_setup_common(struct hda_codec *codec,
2586 				unsigned int chip_addx,
2587 				unsigned int dma_chan,
2588 				unsigned int port_map_mask,
2589 				bool ovly)
2590 {
2591 	int status = 0;
2592 	unsigned int chnl_prop;
2593 	unsigned int dsp_addx;
2594 	unsigned int active;
2595 	bool code, yram;
2596 
2597 	codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2598 
2599 	if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2600 		codec_dbg(codec, "dma chan num invalid\n");
2601 		return -EINVAL;
2602 	}
2603 
2604 	if (dsp_is_dma_active(codec, dma_chan)) {
2605 		codec_dbg(codec, "dma already active\n");
2606 		return -EBUSY;
2607 	}
2608 
2609 	dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2610 
2611 	if (dsp_addx == INVALID_CHIP_ADDRESS) {
2612 		codec_dbg(codec, "invalid chip addr\n");
2613 		return -ENXIO;
2614 	}
2615 
2616 	chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2617 	active = 0;
2618 
2619 	codec_dbg(codec, "   dsp_dma_setup_common()    start reg pgm\n");
2620 
2621 	if (ovly) {
2622 		status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2623 				     &chnl_prop);
2624 
2625 		if (status < 0) {
2626 			codec_dbg(codec, "read CHNLPROP Reg fail\n");
2627 			return status;
2628 		}
2629 		codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2630 	}
2631 
2632 	if (!code)
2633 		chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2634 	else
2635 		chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2636 
2637 	chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2638 
2639 	status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2640 	if (status < 0) {
2641 		codec_dbg(codec, "write CHNLPROP Reg fail\n");
2642 		return status;
2643 	}
2644 	codec_dbg(codec, "   dsp_dma_setup_common()    Write CHNLPROP\n");
2645 
2646 	if (ovly) {
2647 		status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2648 				     &active);
2649 
2650 		if (status < 0) {
2651 			codec_dbg(codec, "read ACTIVE Reg fail\n");
2652 			return status;
2653 		}
2654 		codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2655 	}
2656 
2657 	active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2658 		DSPDMAC_ACTIVE_AAR_MASK;
2659 
2660 	status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2661 	if (status < 0) {
2662 		codec_dbg(codec, "write ACTIVE Reg fail\n");
2663 		return status;
2664 	}
2665 
2666 	codec_dbg(codec, "   dsp_dma_setup_common()    Write ACTIVE\n");
2667 
2668 	status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2669 			      port_map_mask);
2670 	if (status < 0) {
2671 		codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2672 		return status;
2673 	}
2674 	codec_dbg(codec, "   dsp_dma_setup_common()    Write AUDCHSEL\n");
2675 
2676 	status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2677 			DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2678 	if (status < 0) {
2679 		codec_dbg(codec, "write IRQCNT Reg fail\n");
2680 		return status;
2681 	}
2682 	codec_dbg(codec, "   dsp_dma_setup_common()    Write IRQCNT\n");
2683 
2684 	codec_dbg(codec,
2685 		   "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2686 		   "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2687 		   chip_addx, dsp_addx, dma_chan,
2688 		   port_map_mask, chnl_prop, active);
2689 
2690 	codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2691 
2692 	return 0;
2693 }
2694 
2695 /*
2696  * Setup the DSP DMA per-transfer-specific registers
2697  */
2698 static int dsp_dma_setup(struct hda_codec *codec,
2699 			unsigned int chip_addx,
2700 			unsigned int count,
2701 			unsigned int dma_chan)
2702 {
2703 	int status = 0;
2704 	bool code, yram;
2705 	unsigned int dsp_addx;
2706 	unsigned int addr_field;
2707 	unsigned int incr_field;
2708 	unsigned int base_cnt;
2709 	unsigned int cur_cnt;
2710 	unsigned int dma_cfg = 0;
2711 	unsigned int adr_ofs = 0;
2712 	unsigned int xfr_cnt = 0;
2713 	const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2714 						DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2715 
2716 	codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2717 
2718 	if (count > max_dma_count) {
2719 		codec_dbg(codec, "count too big\n");
2720 		return -EINVAL;
2721 	}
2722 
2723 	dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2724 	if (dsp_addx == INVALID_CHIP_ADDRESS) {
2725 		codec_dbg(codec, "invalid chip addr\n");
2726 		return -ENXIO;
2727 	}
2728 
2729 	codec_dbg(codec, "   dsp_dma_setup()    start reg pgm\n");
2730 
2731 	addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2732 	incr_field   = 0;
2733 
2734 	if (!code) {
2735 		addr_field <<= 1;
2736 		if (yram)
2737 			addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2738 
2739 		incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2740 	}
2741 
2742 	dma_cfg = addr_field + incr_field;
2743 	status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2744 				dma_cfg);
2745 	if (status < 0) {
2746 		codec_dbg(codec, "write DMACFG Reg fail\n");
2747 		return status;
2748 	}
2749 	codec_dbg(codec, "   dsp_dma_setup()    Write DMACFG\n");
2750 
2751 	adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2752 							(code ? 0 : 1));
2753 
2754 	status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2755 				adr_ofs);
2756 	if (status < 0) {
2757 		codec_dbg(codec, "write DSPADROFS Reg fail\n");
2758 		return status;
2759 	}
2760 	codec_dbg(codec, "   dsp_dma_setup()    Write DSPADROFS\n");
2761 
2762 	base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2763 
2764 	cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2765 
2766 	xfr_cnt = base_cnt | cur_cnt;
2767 
2768 	status = chipio_write(codec,
2769 				DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2770 	if (status < 0) {
2771 		codec_dbg(codec, "write XFRCNT Reg fail\n");
2772 		return status;
2773 	}
2774 	codec_dbg(codec, "   dsp_dma_setup()    Write XFRCNT\n");
2775 
2776 	codec_dbg(codec,
2777 		   "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2778 		   "ADROFS=0x%x, XFRCNT=0x%x\n",
2779 		   chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2780 
2781 	codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2782 
2783 	return 0;
2784 }
2785 
2786 /*
2787  * Start the DSP DMA
2788  */
2789 static int dsp_dma_start(struct hda_codec *codec,
2790 			 unsigned int dma_chan, bool ovly)
2791 {
2792 	unsigned int reg = 0;
2793 	int status = 0;
2794 
2795 	codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2796 
2797 	if (ovly) {
2798 		status = chipio_read(codec,
2799 				     DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2800 
2801 		if (status < 0) {
2802 			codec_dbg(codec, "read CHNLSTART reg fail\n");
2803 			return status;
2804 		}
2805 		codec_dbg(codec, "-- dsp_dma_start()    Read CHNLSTART\n");
2806 
2807 		reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2808 				DSPDMAC_CHNLSTART_DIS_MASK);
2809 	}
2810 
2811 	status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2812 			reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2813 	if (status < 0) {
2814 		codec_dbg(codec, "write CHNLSTART reg fail\n");
2815 		return status;
2816 	}
2817 	codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2818 
2819 	return status;
2820 }
2821 
2822 /*
2823  * Stop the DSP DMA
2824  */
2825 static int dsp_dma_stop(struct hda_codec *codec,
2826 			unsigned int dma_chan, bool ovly)
2827 {
2828 	unsigned int reg = 0;
2829 	int status = 0;
2830 
2831 	codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2832 
2833 	if (ovly) {
2834 		status = chipio_read(codec,
2835 				     DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2836 
2837 		if (status < 0) {
2838 			codec_dbg(codec, "read CHNLSTART reg fail\n");
2839 			return status;
2840 		}
2841 		codec_dbg(codec, "-- dsp_dma_stop()    Read CHNLSTART\n");
2842 		reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2843 				DSPDMAC_CHNLSTART_DIS_MASK);
2844 	}
2845 
2846 	status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2847 			reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2848 	if (status < 0) {
2849 		codec_dbg(codec, "write CHNLSTART reg fail\n");
2850 		return status;
2851 	}
2852 	codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2853 
2854 	return status;
2855 }
2856 
2857 /**
2858  * dsp_allocate_router_ports - Allocate router ports
2859  *
2860  * @codec: the HDA codec
2861  * @num_chans: number of channels in the stream
2862  * @ports_per_channel: number of ports per channel
2863  * @start_device: start device
2864  * @port_map: pointer to the port list to hold the allocated ports
2865  *
2866  * Returns zero or a negative error code.
2867  */
2868 static int dsp_allocate_router_ports(struct hda_codec *codec,
2869 				     unsigned int num_chans,
2870 				     unsigned int ports_per_channel,
2871 				     unsigned int start_device,
2872 				     unsigned int *port_map)
2873 {
2874 	int status = 0;
2875 	int res;
2876 	u8 val;
2877 
2878 	status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2879 	if (status < 0)
2880 		return status;
2881 
2882 	val = start_device << 6;
2883 	val |= (ports_per_channel - 1) << 4;
2884 	val |= num_chans - 1;
2885 
2886 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2887 			    VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2888 			    val);
2889 
2890 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2891 			    VENDOR_CHIPIO_PORT_ALLOC_SET,
2892 			    MEM_CONNID_DSP);
2893 
2894 	status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2895 	if (status < 0)
2896 		return status;
2897 
2898 	res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2899 				VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2900 
2901 	*port_map = res;
2902 
2903 	return (res < 0) ? res : 0;
2904 }
2905 
2906 /*
2907  * Free router ports
2908  */
2909 static int dsp_free_router_ports(struct hda_codec *codec)
2910 {
2911 	int status = 0;
2912 
2913 	status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2914 	if (status < 0)
2915 		return status;
2916 
2917 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2918 			    VENDOR_CHIPIO_PORT_FREE_SET,
2919 			    MEM_CONNID_DSP);
2920 
2921 	status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2922 
2923 	return status;
2924 }
2925 
2926 /*
2927  * Allocate DSP ports for the download stream
2928  */
2929 static int dsp_allocate_ports(struct hda_codec *codec,
2930 			unsigned int num_chans,
2931 			unsigned int rate_multi, unsigned int *port_map)
2932 {
2933 	int status;
2934 
2935 	codec_dbg(codec, "     dsp_allocate_ports() -- begin\n");
2936 
2937 	if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2938 		codec_dbg(codec, "bad rate multiple\n");
2939 		return -EINVAL;
2940 	}
2941 
2942 	status = dsp_allocate_router_ports(codec, num_chans,
2943 					   rate_multi, 0, port_map);
2944 
2945 	codec_dbg(codec, "     dsp_allocate_ports() -- complete\n");
2946 
2947 	return status;
2948 }
2949 
2950 static int dsp_allocate_ports_format(struct hda_codec *codec,
2951 			const unsigned short fmt,
2952 			unsigned int *port_map)
2953 {
2954 	unsigned int num_chans;
2955 
2956 	unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2957 	unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2958 	unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2959 
2960 	if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2961 		codec_dbg(codec, "bad rate multiple\n");
2962 		return -EINVAL;
2963 	}
2964 
2965 	num_chans = get_hdafmt_chs(fmt) + 1;
2966 
2967 	return dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2968 }
2969 
2970 /*
2971  * free DSP ports
2972  */
2973 static int dsp_free_ports(struct hda_codec *codec)
2974 {
2975 	int status;
2976 
2977 	codec_dbg(codec, "     dsp_free_ports() -- begin\n");
2978 
2979 	status = dsp_free_router_ports(codec);
2980 	if (status < 0) {
2981 		codec_dbg(codec, "free router ports fail\n");
2982 		return status;
2983 	}
2984 	codec_dbg(codec, "     dsp_free_ports() -- complete\n");
2985 
2986 	return status;
2987 }
2988 
2989 /*
2990  *  HDA DMA engine stuffs for DSP code download
2991  */
2992 struct dma_engine {
2993 	struct hda_codec *codec;
2994 	unsigned short m_converter_format;
2995 	struct snd_dma_buffer *dmab;
2996 	unsigned int buf_size;
2997 };
2998 
2999 
3000 enum dma_state {
3001 	DMA_STATE_STOP  = 0,
3002 	DMA_STATE_RUN   = 1
3003 };
3004 
3005 static int dma_convert_to_hda_format(struct hda_codec *codec,
3006 		unsigned int sample_rate,
3007 		unsigned short channels,
3008 		unsigned short *hda_format)
3009 {
3010 	unsigned int format_val;
3011 
3012 	format_val = snd_hdac_stream_format(channels, 32, sample_rate);
3013 
3014 	if (hda_format)
3015 		*hda_format = (unsigned short)format_val;
3016 
3017 	return 0;
3018 }
3019 
3020 /*
3021  *  Reset DMA for DSP download
3022  */
3023 static int dma_reset(struct dma_engine *dma)
3024 {
3025 	struct hda_codec *codec = dma->codec;
3026 	struct ca0132_spec *spec = codec->spec;
3027 	int status;
3028 
3029 	if (dma->dmab->area)
3030 		snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
3031 
3032 	status = snd_hda_codec_load_dsp_prepare(codec,
3033 			dma->m_converter_format,
3034 			dma->buf_size,
3035 			dma->dmab);
3036 	if (status < 0)
3037 		return status;
3038 	spec->dsp_stream_id = status;
3039 	return 0;
3040 }
3041 
3042 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
3043 {
3044 	bool cmd;
3045 
3046 	switch (state) {
3047 	case DMA_STATE_STOP:
3048 		cmd = false;
3049 		break;
3050 	case DMA_STATE_RUN:
3051 		cmd = true;
3052 		break;
3053 	default:
3054 		return 0;
3055 	}
3056 
3057 	snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
3058 	return 0;
3059 }
3060 
3061 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
3062 {
3063 	return dma->dmab->bytes;
3064 }
3065 
3066 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
3067 {
3068 	return dma->dmab->area;
3069 }
3070 
3071 static int dma_xfer(struct dma_engine *dma,
3072 		const unsigned int *data,
3073 		unsigned int count)
3074 {
3075 	memcpy(dma->dmab->area, data, count);
3076 	return 0;
3077 }
3078 
3079 static void dma_get_converter_format(
3080 		struct dma_engine *dma,
3081 		unsigned short *format)
3082 {
3083 	if (format)
3084 		*format = dma->m_converter_format;
3085 }
3086 
3087 static unsigned int dma_get_stream_id(struct dma_engine *dma)
3088 {
3089 	struct ca0132_spec *spec = dma->codec->spec;
3090 
3091 	return spec->dsp_stream_id;
3092 }
3093 
3094 struct dsp_image_seg {
3095 	u32 magic;
3096 	u32 chip_addr;
3097 	u32 count;
3098 	u32 data[];
3099 };
3100 
3101 static const u32 g_magic_value = 0x4c46584d;
3102 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
3103 
3104 static bool is_valid(const struct dsp_image_seg *p)
3105 {
3106 	return p->magic == g_magic_value;
3107 }
3108 
3109 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
3110 {
3111 	return g_chip_addr_magic_value == p->chip_addr;
3112 }
3113 
3114 static bool is_last(const struct dsp_image_seg *p)
3115 {
3116 	return p->count == 0;
3117 }
3118 
3119 static size_t dsp_sizeof(const struct dsp_image_seg *p)
3120 {
3121 	return struct_size(p, data, p->count);
3122 }
3123 
3124 static const struct dsp_image_seg *get_next_seg_ptr(
3125 				const struct dsp_image_seg *p)
3126 {
3127 	return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
3128 }
3129 
3130 /*
3131  * CA0132 chip DSP transfer stuffs.  For DSP download.
3132  */
3133 #define INVALID_DMA_CHANNEL (~0U)
3134 
3135 /*
3136  * Program a list of address/data pairs via the ChipIO widget.
3137  * The segment data is in the format of successive pairs of words.
3138  * These are repeated as indicated by the segment's count field.
3139  */
3140 static int dspxfr_hci_write(struct hda_codec *codec,
3141 			const struct dsp_image_seg *fls)
3142 {
3143 	int status;
3144 	const u32 *data;
3145 	unsigned int count;
3146 
3147 	if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
3148 		codec_dbg(codec, "hci_write invalid params\n");
3149 		return -EINVAL;
3150 	}
3151 
3152 	count = fls->count;
3153 	data = (u32 *)(fls->data);
3154 	while (count >= 2) {
3155 		status = chipio_write(codec, data[0], data[1]);
3156 		if (status < 0) {
3157 			codec_dbg(codec, "hci_write chipio failed\n");
3158 			return status;
3159 		}
3160 		count -= 2;
3161 		data  += 2;
3162 	}
3163 	return 0;
3164 }
3165 
3166 /**
3167  * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine.
3168  *
3169  * @codec: the HDA codec
3170  * @fls: pointer to a fast load image
3171  * @reloc: Relocation address for loading single-segment overlays, or 0 for
3172  *	   no relocation
3173  * @dma_engine: pointer to DMA engine to be used for DSP download
3174  * @dma_chan: The number of DMA channels used for DSP download
3175  * @port_map_mask: port mapping
3176  * @ovly: TRUE if overlay format is required
3177  *
3178  * Returns zero or a negative error code.
3179  */
3180 static int dspxfr_one_seg(struct hda_codec *codec,
3181 			const struct dsp_image_seg *fls,
3182 			unsigned int reloc,
3183 			struct dma_engine *dma_engine,
3184 			unsigned int dma_chan,
3185 			unsigned int port_map_mask,
3186 			bool ovly)
3187 {
3188 	int status = 0;
3189 	bool comm_dma_setup_done = false;
3190 	const unsigned int *data;
3191 	unsigned int chip_addx;
3192 	unsigned int words_to_write;
3193 	unsigned int buffer_size_words;
3194 	unsigned char *buffer_addx;
3195 	unsigned short hda_format;
3196 	unsigned int sample_rate_div;
3197 	unsigned int sample_rate_mul;
3198 	unsigned int num_chans;
3199 	unsigned int hda_frame_size_words;
3200 	unsigned int remainder_words;
3201 	const u32 *data_remainder;
3202 	u32 chip_addx_remainder;
3203 	unsigned int run_size_words;
3204 	const struct dsp_image_seg *hci_write = NULL;
3205 	unsigned long timeout;
3206 	bool dma_active;
3207 
3208 	if (fls == NULL)
3209 		return -EINVAL;
3210 	if (is_hci_prog_list_seg(fls)) {
3211 		hci_write = fls;
3212 		fls = get_next_seg_ptr(fls);
3213 	}
3214 
3215 	if (hci_write && (!fls || is_last(fls))) {
3216 		codec_dbg(codec, "hci_write\n");
3217 		return dspxfr_hci_write(codec, hci_write);
3218 	}
3219 
3220 	if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
3221 		codec_dbg(codec, "Invalid Params\n");
3222 		return -EINVAL;
3223 	}
3224 
3225 	data = fls->data;
3226 	chip_addx = fls->chip_addr;
3227 	words_to_write = fls->count;
3228 
3229 	if (!words_to_write)
3230 		return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
3231 	if (reloc)
3232 		chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
3233 
3234 	if (!UC_RANGE(chip_addx, words_to_write) &&
3235 	    !X_RANGE_ALL(chip_addx, words_to_write) &&
3236 	    !Y_RANGE_ALL(chip_addx, words_to_write)) {
3237 		codec_dbg(codec, "Invalid chip_addx Params\n");
3238 		return -EINVAL;
3239 	}
3240 
3241 	buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
3242 					sizeof(u32);
3243 
3244 	buffer_addx = dma_get_buffer_addr(dma_engine);
3245 
3246 	if (buffer_addx == NULL) {
3247 		codec_dbg(codec, "dma_engine buffer NULL\n");
3248 		return -EINVAL;
3249 	}
3250 
3251 	dma_get_converter_format(dma_engine, &hda_format);
3252 	sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
3253 	sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
3254 	num_chans = get_hdafmt_chs(hda_format) + 1;
3255 
3256 	hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
3257 			(num_chans * sample_rate_mul / sample_rate_div));
3258 
3259 	if (hda_frame_size_words == 0) {
3260 		codec_dbg(codec, "frmsz zero\n");
3261 		return -EINVAL;
3262 	}
3263 
3264 	buffer_size_words = min(buffer_size_words,
3265 				(unsigned int)(UC_RANGE(chip_addx, 1) ?
3266 				65536 : 32768));
3267 	buffer_size_words -= buffer_size_words % hda_frame_size_words;
3268 	codec_dbg(codec,
3269 		   "chpadr=0x%08x frmsz=%u nchan=%u "
3270 		   "rate_mul=%u div=%u bufsz=%u\n",
3271 		   chip_addx, hda_frame_size_words, num_chans,
3272 		   sample_rate_mul, sample_rate_div, buffer_size_words);
3273 
3274 	if (buffer_size_words < hda_frame_size_words) {
3275 		codec_dbg(codec, "dspxfr_one_seg:failed\n");
3276 		return -EINVAL;
3277 	}
3278 
3279 	remainder_words = words_to_write % hda_frame_size_words;
3280 	data_remainder = data;
3281 	chip_addx_remainder = chip_addx;
3282 
3283 	data += remainder_words;
3284 	chip_addx += remainder_words*sizeof(u32);
3285 	words_to_write -= remainder_words;
3286 
3287 	while (words_to_write != 0) {
3288 		run_size_words = min(buffer_size_words, words_to_write);
3289 		codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
3290 			    words_to_write, run_size_words, remainder_words);
3291 		dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
3292 		if (!comm_dma_setup_done) {
3293 			status = dsp_dma_stop(codec, dma_chan, ovly);
3294 			if (status < 0)
3295 				return status;
3296 			status = dsp_dma_setup_common(codec, chip_addx,
3297 						dma_chan, port_map_mask, ovly);
3298 			if (status < 0)
3299 				return status;
3300 			comm_dma_setup_done = true;
3301 		}
3302 
3303 		status = dsp_dma_setup(codec, chip_addx,
3304 						run_size_words, dma_chan);
3305 		if (status < 0)
3306 			return status;
3307 		status = dsp_dma_start(codec, dma_chan, ovly);
3308 		if (status < 0)
3309 			return status;
3310 		if (!dsp_is_dma_active(codec, dma_chan)) {
3311 			codec_dbg(codec, "dspxfr:DMA did not start\n");
3312 			return -EIO;
3313 		}
3314 		status = dma_set_state(dma_engine, DMA_STATE_RUN);
3315 		if (status < 0)
3316 			return status;
3317 		if (remainder_words != 0) {
3318 			status = chipio_write_multiple(codec,
3319 						chip_addx_remainder,
3320 						data_remainder,
3321 						remainder_words);
3322 			if (status < 0)
3323 				return status;
3324 			remainder_words = 0;
3325 		}
3326 		if (hci_write) {
3327 			status = dspxfr_hci_write(codec, hci_write);
3328 			if (status < 0)
3329 				return status;
3330 			hci_write = NULL;
3331 		}
3332 
3333 		timeout = jiffies + msecs_to_jiffies(2000);
3334 		do {
3335 			dma_active = dsp_is_dma_active(codec, dma_chan);
3336 			if (!dma_active)
3337 				break;
3338 			msleep(20);
3339 		} while (time_before(jiffies, timeout));
3340 		if (dma_active)
3341 			break;
3342 
3343 		codec_dbg(codec, "+++++ DMA complete\n");
3344 		dma_set_state(dma_engine, DMA_STATE_STOP);
3345 		status = dma_reset(dma_engine);
3346 
3347 		if (status < 0)
3348 			return status;
3349 
3350 		data += run_size_words;
3351 		chip_addx += run_size_words*sizeof(u32);
3352 		words_to_write -= run_size_words;
3353 	}
3354 
3355 	if (remainder_words != 0) {
3356 		status = chipio_write_multiple(codec, chip_addx_remainder,
3357 					data_remainder, remainder_words);
3358 	}
3359 
3360 	return status;
3361 }
3362 
3363 /**
3364  * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories
3365  *
3366  * @codec: the HDA codec
3367  * @fls_data: pointer to a fast load image
3368  * @reloc: Relocation address for loading single-segment overlays, or 0 for
3369  *	   no relocation
3370  * @sample_rate: sampling rate of the stream used for DSP download
3371  * @channels: channels of the stream used for DSP download
3372  * @ovly: TRUE if overlay format is required
3373  *
3374  * Returns zero or a negative error code.
3375  */
3376 static int dspxfr_image(struct hda_codec *codec,
3377 			const struct dsp_image_seg *fls_data,
3378 			unsigned int reloc,
3379 			unsigned int sample_rate,
3380 			unsigned short channels,
3381 			bool ovly)
3382 {
3383 	struct ca0132_spec *spec = codec->spec;
3384 	int status;
3385 	unsigned short hda_format = 0;
3386 	unsigned int response;
3387 	unsigned char stream_id = 0;
3388 	struct dma_engine *dma_engine;
3389 	unsigned int dma_chan;
3390 	unsigned int port_map_mask;
3391 
3392 	if (fls_data == NULL)
3393 		return -EINVAL;
3394 
3395 	dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
3396 	if (!dma_engine)
3397 		return -ENOMEM;
3398 
3399 	dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3400 	if (!dma_engine->dmab) {
3401 		kfree(dma_engine);
3402 		return -ENOMEM;
3403 	}
3404 
3405 	dma_engine->codec = codec;
3406 	dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
3407 	dma_engine->m_converter_format = hda_format;
3408 	dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3409 			DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3410 
3411 	dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3412 
3413 	status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3414 					hda_format, &response);
3415 
3416 	if (status < 0) {
3417 		codec_dbg(codec, "set converter format fail\n");
3418 		goto exit;
3419 	}
3420 
3421 	status = snd_hda_codec_load_dsp_prepare(codec,
3422 				dma_engine->m_converter_format,
3423 				dma_engine->buf_size,
3424 				dma_engine->dmab);
3425 	if (status < 0)
3426 		goto exit;
3427 	spec->dsp_stream_id = status;
3428 
3429 	if (ovly) {
3430 		status = dspio_alloc_dma_chan(codec, &dma_chan);
3431 		if (status < 0) {
3432 			codec_dbg(codec, "alloc dmachan fail\n");
3433 			dma_chan = INVALID_DMA_CHANNEL;
3434 			goto exit;
3435 		}
3436 	}
3437 
3438 	port_map_mask = 0;
3439 	status = dsp_allocate_ports_format(codec, hda_format,
3440 					&port_map_mask);
3441 	if (status < 0) {
3442 		codec_dbg(codec, "alloc ports fail\n");
3443 		goto exit;
3444 	}
3445 
3446 	stream_id = dma_get_stream_id(dma_engine);
3447 	status = codec_set_converter_stream_channel(codec,
3448 			WIDGET_CHIP_CTRL, stream_id, 0, &response);
3449 	if (status < 0) {
3450 		codec_dbg(codec, "set stream chan fail\n");
3451 		goto exit;
3452 	}
3453 
3454 	while ((fls_data != NULL) && !is_last(fls_data)) {
3455 		if (!is_valid(fls_data)) {
3456 			codec_dbg(codec, "FLS check fail\n");
3457 			status = -EINVAL;
3458 			goto exit;
3459 		}
3460 		status = dspxfr_one_seg(codec, fls_data, reloc,
3461 					dma_engine, dma_chan,
3462 					port_map_mask, ovly);
3463 		if (status < 0)
3464 			break;
3465 
3466 		if (is_hci_prog_list_seg(fls_data))
3467 			fls_data = get_next_seg_ptr(fls_data);
3468 
3469 		if ((fls_data != NULL) && !is_last(fls_data))
3470 			fls_data = get_next_seg_ptr(fls_data);
3471 	}
3472 
3473 	if (port_map_mask != 0)
3474 		status = dsp_free_ports(codec);
3475 
3476 	if (status < 0)
3477 		goto exit;
3478 
3479 	status = codec_set_converter_stream_channel(codec,
3480 				WIDGET_CHIP_CTRL, 0, 0, &response);
3481 
3482 exit:
3483 	if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3484 		dspio_free_dma_chan(codec, dma_chan);
3485 
3486 	if (dma_engine->dmab->area)
3487 		snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3488 	kfree(dma_engine->dmab);
3489 	kfree(dma_engine);
3490 
3491 	return status;
3492 }
3493 
3494 /*
3495  * CA0132 DSP download stuffs.
3496  */
3497 static void dspload_post_setup(struct hda_codec *codec)
3498 {
3499 	struct ca0132_spec *spec = codec->spec;
3500 	codec_dbg(codec, "---- dspload_post_setup ------\n");
3501 	if (!ca0132_use_alt_functions(spec)) {
3502 		/*set DSP speaker to 2.0 configuration*/
3503 		chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3504 		chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3505 
3506 		/*update write pointer*/
3507 		chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3508 	}
3509 }
3510 
3511 /**
3512  * dspload_image - Download DSP from a DSP Image Fast Load structure.
3513  *
3514  * @codec: the HDA codec
3515  * @fls: pointer to a fast load image
3516  * @ovly: TRUE if overlay format is required
3517  * @reloc: Relocation address for loading single-segment overlays, or 0 for
3518  *	   no relocation
3519  * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3520  * @router_chans: number of audio router channels to be allocated (0 means use
3521  *		  internal defaults; max is 32)
3522  *
3523  * Download DSP from a DSP Image Fast Load structure. This structure is a
3524  * linear, non-constant sized element array of structures, each of which
3525  * contain the count of the data to be loaded, the data itself, and the
3526  * corresponding starting chip address of the starting data location.
3527  * Returns zero or a negative error code.
3528  */
3529 static int dspload_image(struct hda_codec *codec,
3530 			const struct dsp_image_seg *fls,
3531 			bool ovly,
3532 			unsigned int reloc,
3533 			bool autostart,
3534 			int router_chans)
3535 {
3536 	int status = 0;
3537 	unsigned int sample_rate;
3538 	unsigned short channels;
3539 
3540 	codec_dbg(codec, "---- dspload_image begin ------\n");
3541 	if (router_chans == 0) {
3542 		if (!ovly)
3543 			router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3544 		else
3545 			router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3546 	}
3547 
3548 	sample_rate = 48000;
3549 	channels = (unsigned short)router_chans;
3550 
3551 	while (channels > 16) {
3552 		sample_rate *= 2;
3553 		channels /= 2;
3554 	}
3555 
3556 	do {
3557 		codec_dbg(codec, "Ready to program DMA\n");
3558 		if (!ovly)
3559 			status = dsp_reset(codec);
3560 
3561 		if (status < 0)
3562 			break;
3563 
3564 		codec_dbg(codec, "dsp_reset() complete\n");
3565 		status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3566 				      ovly);
3567 
3568 		if (status < 0)
3569 			break;
3570 
3571 		codec_dbg(codec, "dspxfr_image() complete\n");
3572 		if (autostart && !ovly) {
3573 			dspload_post_setup(codec);
3574 			status = dsp_set_run_state(codec);
3575 		}
3576 
3577 		codec_dbg(codec, "LOAD FINISHED\n");
3578 	} while (0);
3579 
3580 	return status;
3581 }
3582 
3583 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
3584 static bool dspload_is_loaded(struct hda_codec *codec)
3585 {
3586 	unsigned int data = 0;
3587 	int status = 0;
3588 
3589 	status = chipio_read(codec, 0x40004, &data);
3590 	if ((status < 0) || (data != 1))
3591 		return false;
3592 
3593 	return true;
3594 }
3595 #else
3596 #define dspload_is_loaded(codec)	false
3597 #endif
3598 
3599 static bool dspload_wait_loaded(struct hda_codec *codec)
3600 {
3601 	unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3602 
3603 	do {
3604 		if (dspload_is_loaded(codec)) {
3605 			codec_info(codec, "ca0132 DSP downloaded and running\n");
3606 			return true;
3607 		}
3608 		msleep(20);
3609 	} while (time_before(jiffies, timeout));
3610 
3611 	codec_err(codec, "ca0132 failed to download DSP\n");
3612 	return false;
3613 }
3614 
3615 /*
3616  * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3617  * based cards, and has a second mmio region, region2, that's used for special
3618  * commands.
3619  */
3620 
3621 /*
3622  * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3623  * the mmio address 0x320 is used to set GPIO pins. The format for the data
3624  * The first eight bits are just the number of the pin. So far, I've only seen
3625  * this number go to 7.
3626  * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3627  * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3628  * then off to send that bit.
3629  */
3630 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3631 		bool enable)
3632 {
3633 	struct ca0132_spec *spec = codec->spec;
3634 	unsigned short gpio_data;
3635 
3636 	gpio_data = gpio_pin & 0xF;
3637 	gpio_data |= ((enable << 8) & 0x100);
3638 
3639 	writew(gpio_data, spec->mem_base + 0x320);
3640 }
3641 
3642 /*
3643  * Special pci region2 commands that are only used by the AE-5. They follow
3644  * a set format, and require reads at certain points to seemingly 'clear'
3645  * the response data. My first tests didn't do these reads, and would cause
3646  * the card to get locked up until the memory was read. These commands
3647  * seem to work with three distinct values that I've taken to calling group,
3648  * target-id, and value.
3649  */
3650 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3651 		unsigned int target, unsigned int value)
3652 {
3653 	struct ca0132_spec *spec = codec->spec;
3654 	unsigned int write_val;
3655 
3656 	writel(0x0000007e, spec->mem_base + 0x210);
3657 	readl(spec->mem_base + 0x210);
3658 	writel(0x0000005a, spec->mem_base + 0x210);
3659 	readl(spec->mem_base + 0x210);
3660 	readl(spec->mem_base + 0x210);
3661 
3662 	writel(0x00800005, spec->mem_base + 0x20c);
3663 	writel(group, spec->mem_base + 0x804);
3664 
3665 	writel(0x00800005, spec->mem_base + 0x20c);
3666 	write_val = (target & 0xff);
3667 	write_val |= (value << 8);
3668 
3669 
3670 	writel(write_val, spec->mem_base + 0x204);
3671 	/*
3672 	 * Need delay here or else it goes too fast and works inconsistently.
3673 	 */
3674 	msleep(20);
3675 
3676 	readl(spec->mem_base + 0x860);
3677 	readl(spec->mem_base + 0x854);
3678 	readl(spec->mem_base + 0x840);
3679 
3680 	writel(0x00800004, spec->mem_base + 0x20c);
3681 	writel(0x00000000, spec->mem_base + 0x210);
3682 	readl(spec->mem_base + 0x210);
3683 	readl(spec->mem_base + 0x210);
3684 }
3685 
3686 /*
3687  * This second type of command is used for setting the sound filter type.
3688  */
3689 static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3690 		unsigned int group, unsigned int target, unsigned int value)
3691 {
3692 	struct ca0132_spec *spec = codec->spec;
3693 	unsigned int write_val;
3694 
3695 	writel(0x0000007e, spec->mem_base + 0x210);
3696 	readl(spec->mem_base + 0x210);
3697 	writel(0x0000005a, spec->mem_base + 0x210);
3698 	readl(spec->mem_base + 0x210);
3699 	readl(spec->mem_base + 0x210);
3700 
3701 	writel(0x00800003, spec->mem_base + 0x20c);
3702 	writel(group, spec->mem_base + 0x804);
3703 
3704 	writel(0x00800005, spec->mem_base + 0x20c);
3705 	write_val = (target & 0xff);
3706 	write_val |= (value << 8);
3707 
3708 
3709 	writel(write_val, spec->mem_base + 0x204);
3710 	msleep(20);
3711 	readl(spec->mem_base + 0x860);
3712 	readl(spec->mem_base + 0x854);
3713 	readl(spec->mem_base + 0x840);
3714 
3715 	writel(0x00800004, spec->mem_base + 0x20c);
3716 	writel(0x00000000, spec->mem_base + 0x210);
3717 	readl(spec->mem_base + 0x210);
3718 	readl(spec->mem_base + 0x210);
3719 }
3720 
3721 /*
3722  * Setup GPIO for the other variants of Core3D.
3723  */
3724 
3725 /*
3726  * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3727  * the card shows as having no GPIO pins.
3728  */
3729 static void ca0132_gpio_init(struct hda_codec *codec)
3730 {
3731 	struct ca0132_spec *spec = codec->spec;
3732 
3733 	switch (ca0132_quirk(spec)) {
3734 	case QUIRK_SBZ:
3735 	case QUIRK_AE5:
3736 	case QUIRK_AE7:
3737 		snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3738 		snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3739 		snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3740 		break;
3741 	case QUIRK_R3DI:
3742 		snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3743 		snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3744 		break;
3745 	default:
3746 		break;
3747 	}
3748 
3749 }
3750 
3751 /* Sets the GPIO for audio output. */
3752 static void ca0132_gpio_setup(struct hda_codec *codec)
3753 {
3754 	struct ca0132_spec *spec = codec->spec;
3755 
3756 	switch (ca0132_quirk(spec)) {
3757 	case QUIRK_SBZ:
3758 		snd_hda_codec_write(codec, 0x01, 0,
3759 				AC_VERB_SET_GPIO_DIRECTION, 0x07);
3760 		snd_hda_codec_write(codec, 0x01, 0,
3761 				AC_VERB_SET_GPIO_MASK, 0x07);
3762 		snd_hda_codec_write(codec, 0x01, 0,
3763 				AC_VERB_SET_GPIO_DATA, 0x04);
3764 		snd_hda_codec_write(codec, 0x01, 0,
3765 				AC_VERB_SET_GPIO_DATA, 0x06);
3766 		break;
3767 	case QUIRK_R3DI:
3768 		snd_hda_codec_write(codec, 0x01, 0,
3769 				AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3770 		snd_hda_codec_write(codec, 0x01, 0,
3771 				AC_VERB_SET_GPIO_MASK, 0x1F);
3772 		snd_hda_codec_write(codec, 0x01, 0,
3773 				AC_VERB_SET_GPIO_DATA, 0x0C);
3774 		break;
3775 	default:
3776 		break;
3777 	}
3778 }
3779 
3780 /*
3781  * GPIO control functions for the Recon3D integrated.
3782  */
3783 
3784 enum r3di_gpio_bit {
3785 	/* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3786 	R3DI_MIC_SELECT_BIT = 1,
3787 	/* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3788 	R3DI_OUT_SELECT_BIT = 2,
3789 	/*
3790 	 * I dunno what this actually does, but it stays on until the dsp
3791 	 * is downloaded.
3792 	 */
3793 	R3DI_GPIO_DSP_DOWNLOADING = 3,
3794 	/*
3795 	 * Same as above, no clue what it does, but it comes on after the dsp
3796 	 * is downloaded.
3797 	 */
3798 	R3DI_GPIO_DSP_DOWNLOADED = 4
3799 };
3800 
3801 enum r3di_mic_select {
3802 	/* Set GPIO bit 1 to 0 for rear mic */
3803 	R3DI_REAR_MIC = 0,
3804 	/* Set GPIO bit 1 to 1 for front microphone*/
3805 	R3DI_FRONT_MIC = 1
3806 };
3807 
3808 enum r3di_out_select {
3809 	/* Set GPIO bit 2 to 0 for headphone */
3810 	R3DI_HEADPHONE_OUT = 0,
3811 	/* Set GPIO bit 2 to 1 for speaker */
3812 	R3DI_LINE_OUT = 1
3813 };
3814 enum r3di_dsp_status {
3815 	/* Set GPIO bit 3 to 1 until DSP is downloaded */
3816 	R3DI_DSP_DOWNLOADING = 0,
3817 	/* Set GPIO bit 4 to 1 once DSP is downloaded */
3818 	R3DI_DSP_DOWNLOADED = 1
3819 };
3820 
3821 
3822 static void r3di_gpio_mic_set(struct hda_codec *codec,
3823 		enum r3di_mic_select cur_mic)
3824 {
3825 	unsigned int cur_gpio;
3826 
3827 	/* Get the current GPIO Data setup */
3828 	cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3829 
3830 	switch (cur_mic) {
3831 	case R3DI_REAR_MIC:
3832 		cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3833 		break;
3834 	case R3DI_FRONT_MIC:
3835 		cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3836 		break;
3837 	}
3838 	snd_hda_codec_write(codec, codec->core.afg, 0,
3839 			    AC_VERB_SET_GPIO_DATA, cur_gpio);
3840 }
3841 
3842 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3843 		enum r3di_dsp_status dsp_status)
3844 {
3845 	unsigned int cur_gpio;
3846 
3847 	/* Get the current GPIO Data setup */
3848 	cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3849 
3850 	switch (dsp_status) {
3851 	case R3DI_DSP_DOWNLOADING:
3852 		cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3853 		snd_hda_codec_write(codec, codec->core.afg, 0,
3854 				AC_VERB_SET_GPIO_DATA, cur_gpio);
3855 		break;
3856 	case R3DI_DSP_DOWNLOADED:
3857 		/* Set DOWNLOADING bit to 0. */
3858 		cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3859 
3860 		snd_hda_codec_write(codec, codec->core.afg, 0,
3861 				AC_VERB_SET_GPIO_DATA, cur_gpio);
3862 
3863 		cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3864 		break;
3865 	}
3866 
3867 	snd_hda_codec_write(codec, codec->core.afg, 0,
3868 			    AC_VERB_SET_GPIO_DATA, cur_gpio);
3869 }
3870 
3871 /*
3872  * PCM callbacks
3873  */
3874 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3875 			struct hda_codec *codec,
3876 			unsigned int stream_tag,
3877 			unsigned int format,
3878 			struct snd_pcm_substream *substream)
3879 {
3880 	struct ca0132_spec *spec = codec->spec;
3881 
3882 	snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3883 
3884 	return 0;
3885 }
3886 
3887 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3888 			struct hda_codec *codec,
3889 			struct snd_pcm_substream *substream)
3890 {
3891 	struct ca0132_spec *spec = codec->spec;
3892 
3893 	if (spec->dsp_state == DSP_DOWNLOADING)
3894 		return 0;
3895 
3896 	/*If Playback effects are on, allow stream some time to flush
3897 	 *effects tail*/
3898 	if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3899 		msleep(50);
3900 
3901 	snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3902 
3903 	return 0;
3904 }
3905 
3906 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3907 			struct hda_codec *codec,
3908 			struct snd_pcm_substream *substream)
3909 {
3910 	struct ca0132_spec *spec = codec->spec;
3911 	unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3912 	struct snd_pcm_runtime *runtime = substream->runtime;
3913 
3914 	if (spec->dsp_state != DSP_DOWNLOADED)
3915 		return 0;
3916 
3917 	/* Add latency if playback enhancement and either effect is enabled. */
3918 	if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3919 		if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3920 		    (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3921 			latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3922 	}
3923 
3924 	/* Applying Speaker EQ adds latency as well. */
3925 	if (spec->cur_out_type == SPEAKER_OUT)
3926 		latency += DSP_SPEAKER_OUT_LATENCY;
3927 
3928 	return (latency * runtime->rate) / 1000;
3929 }
3930 
3931 /*
3932  * Digital out
3933  */
3934 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3935 					struct hda_codec *codec,
3936 					struct snd_pcm_substream *substream)
3937 {
3938 	struct ca0132_spec *spec = codec->spec;
3939 	return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3940 }
3941 
3942 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3943 			struct hda_codec *codec,
3944 			unsigned int stream_tag,
3945 			unsigned int format,
3946 			struct snd_pcm_substream *substream)
3947 {
3948 	struct ca0132_spec *spec = codec->spec;
3949 	return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3950 					     stream_tag, format, substream);
3951 }
3952 
3953 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3954 			struct hda_codec *codec,
3955 			struct snd_pcm_substream *substream)
3956 {
3957 	struct ca0132_spec *spec = codec->spec;
3958 	return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3959 }
3960 
3961 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3962 					 struct hda_codec *codec,
3963 					 struct snd_pcm_substream *substream)
3964 {
3965 	struct ca0132_spec *spec = codec->spec;
3966 	return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3967 }
3968 
3969 /*
3970  * Analog capture
3971  */
3972 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3973 					struct hda_codec *codec,
3974 					unsigned int stream_tag,
3975 					unsigned int format,
3976 					struct snd_pcm_substream *substream)
3977 {
3978 	snd_hda_codec_setup_stream(codec, hinfo->nid,
3979 				   stream_tag, 0, format);
3980 
3981 	return 0;
3982 }
3983 
3984 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3985 			struct hda_codec *codec,
3986 			struct snd_pcm_substream *substream)
3987 {
3988 	struct ca0132_spec *spec = codec->spec;
3989 
3990 	if (spec->dsp_state == DSP_DOWNLOADING)
3991 		return 0;
3992 
3993 	snd_hda_codec_cleanup_stream(codec, hinfo->nid);
3994 	return 0;
3995 }
3996 
3997 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3998 			struct hda_codec *codec,
3999 			struct snd_pcm_substream *substream)
4000 {
4001 	struct ca0132_spec *spec = codec->spec;
4002 	unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
4003 	struct snd_pcm_runtime *runtime = substream->runtime;
4004 
4005 	if (spec->dsp_state != DSP_DOWNLOADED)
4006 		return 0;
4007 
4008 	if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4009 		latency += DSP_CRYSTAL_VOICE_LATENCY;
4010 
4011 	return (latency * runtime->rate) / 1000;
4012 }
4013 
4014 /*
4015  * Controls stuffs.
4016  */
4017 
4018 /*
4019  * Mixer controls helpers.
4020  */
4021 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
4022 	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4023 	  .name = xname, \
4024 	  .subdevice = HDA_SUBDEV_AMP_FLAG, \
4025 	  .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4026 			SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4027 			SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4028 	  .info = ca0132_volume_info, \
4029 	  .get = ca0132_volume_get, \
4030 	  .put = ca0132_volume_put, \
4031 	  .tlv = { .c = ca0132_volume_tlv }, \
4032 	  .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4033 
4034 /*
4035  * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
4036  * volume put, which is used for setting the DSP volume. This was done because
4037  * the ca0132 functions were taking too much time and causing lag.
4038  */
4039 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
4040 	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4041 	  .name = xname, \
4042 	  .subdevice = HDA_SUBDEV_AMP_FLAG, \
4043 	  .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4044 			SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4045 			SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4046 	  .info = snd_hda_mixer_amp_volume_info, \
4047 	  .get = snd_hda_mixer_amp_volume_get, \
4048 	  .put = ca0132_alt_volume_put, \
4049 	  .tlv = { .c = snd_hda_mixer_amp_tlv }, \
4050 	  .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4051 
4052 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
4053 	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4054 	  .name = xname, \
4055 	  .subdevice = HDA_SUBDEV_AMP_FLAG, \
4056 	  .info = snd_hda_mixer_amp_switch_info, \
4057 	  .get = ca0132_switch_get, \
4058 	  .put = ca0132_switch_put, \
4059 	  .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4060 
4061 /* stereo */
4062 #define CA0132_CODEC_VOL(xname, nid, dir) \
4063 	CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
4064 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
4065 	CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
4066 #define CA0132_CODEC_MUTE(xname, nid, dir) \
4067 	CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
4068 
4069 /* lookup tables */
4070 /*
4071  * Lookup table with decibel values for the DSP. When volume is changed in
4072  * Windows, the DSP is also sent the dB value in floating point. In Windows,
4073  * these values have decimal points, probably because the Windows driver
4074  * actually uses floating point. We can't here, so I made a lookup table of
4075  * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
4076  * DAC's, and 9 is the maximum.
4077  */
4078 static const unsigned int float_vol_db_lookup[] = {
4079 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
4080 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
4081 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
4082 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
4083 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
4084 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
4085 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
4086 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
4087 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
4088 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
4089 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
4090 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4091 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4092 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4093 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4094 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4095 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
4096 };
4097 
4098 /*
4099  * This table counts from float 0 to 1 in increments of .01, which is
4100  * useful for a few different sliders.
4101  */
4102 static const unsigned int float_zero_to_one_lookup[] = {
4103 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4104 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4105 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4106 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4107 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4108 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4109 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4110 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4111 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4112 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4113 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4114 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4115 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4116 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4117 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4118 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4119 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4120 };
4121 
4122 /*
4123  * This table counts from float 10 to 1000, which is the range of the x-bass
4124  * crossover slider in Windows.
4125  */
4126 static const unsigned int float_xbass_xover_lookup[] = {
4127 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
4128 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
4129 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
4130 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
4131 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
4132 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
4133 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
4134 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
4135 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
4136 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
4137 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
4138 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
4139 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
4140 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
4141 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
4142 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
4143 0x44728000, 0x44750000, 0x44778000, 0x447A0000
4144 };
4145 
4146 /* The following are for tuning of products */
4147 #ifdef ENABLE_TUNING_CONTROLS
4148 
4149 static const unsigned int voice_focus_vals_lookup[] = {
4150 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
4151 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
4152 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
4153 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
4154 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
4155 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
4156 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
4157 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
4158 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
4159 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
4160 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
4161 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
4162 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
4163 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
4164 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
4165 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
4166 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
4167 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
4168 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
4169 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
4170 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
4171 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
4172 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
4173 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
4174 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
4175 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
4176 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
4177 };
4178 
4179 static const unsigned int mic_svm_vals_lookup[] = {
4180 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4181 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4182 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4183 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4184 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4185 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4186 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4187 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4188 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4189 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4190 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4191 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4192 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4193 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4194 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4195 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4196 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4197 };
4198 
4199 static const unsigned int equalizer_vals_lookup[] = {
4200 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4201 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4202 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4203 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4204 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4205 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
4206 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
4207 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
4208 0x41C00000
4209 };
4210 
4211 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4212 			  const unsigned int *lookup, int idx)
4213 {
4214 	int i;
4215 
4216 	for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4217 		if (nid == ca0132_tuning_ctls[i].nid) {
4218 			CLASS(snd_hda_power, pm)(codec);
4219 			dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
4220 					ca0132_tuning_ctls[i].req,
4221 					&(lookup[idx]), sizeof(unsigned int));
4222 			return 1;
4223 		}
4224 	}
4225 
4226 	return -EINVAL;
4227 }
4228 
4229 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
4230 			  struct snd_ctl_elem_value *ucontrol)
4231 {
4232 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4233 	struct ca0132_spec *spec = codec->spec;
4234 	hda_nid_t nid = get_amp_nid(kcontrol);
4235 	long *valp = ucontrol->value.integer.value;
4236 	int idx = nid - TUNING_CTL_START_NID;
4237 
4238 	*valp = spec->cur_ctl_vals[idx];
4239 	return 0;
4240 }
4241 
4242 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
4243 			      struct snd_ctl_elem_info *uinfo)
4244 {
4245 	int chs = get_amp_channels(kcontrol);
4246 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4247 	uinfo->count = chs == 3 ? 2 : 1;
4248 	uinfo->value.integer.min = 20;
4249 	uinfo->value.integer.max = 180;
4250 	uinfo->value.integer.step = 1;
4251 
4252 	return 0;
4253 }
4254 
4255 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
4256 				struct snd_ctl_elem_value *ucontrol)
4257 {
4258 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4259 	struct ca0132_spec *spec = codec->spec;
4260 	hda_nid_t nid = get_amp_nid(kcontrol);
4261 	long *valp = ucontrol->value.integer.value;
4262 	int idx;
4263 
4264 	idx = nid - TUNING_CTL_START_NID;
4265 	/* any change? */
4266 	if (spec->cur_ctl_vals[idx] == *valp)
4267 		return 0;
4268 
4269 	spec->cur_ctl_vals[idx] = *valp;
4270 
4271 	idx = *valp - 20;
4272 	tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
4273 
4274 	return 1;
4275 }
4276 
4277 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
4278 			      struct snd_ctl_elem_info *uinfo)
4279 {
4280 	int chs = get_amp_channels(kcontrol);
4281 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4282 	uinfo->count = chs == 3 ? 2 : 1;
4283 	uinfo->value.integer.min = 0;
4284 	uinfo->value.integer.max = 100;
4285 	uinfo->value.integer.step = 1;
4286 
4287 	return 0;
4288 }
4289 
4290 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
4291 				struct snd_ctl_elem_value *ucontrol)
4292 {
4293 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4294 	struct ca0132_spec *spec = codec->spec;
4295 	hda_nid_t nid = get_amp_nid(kcontrol);
4296 	long *valp = ucontrol->value.integer.value;
4297 	int idx;
4298 
4299 	idx = nid - TUNING_CTL_START_NID;
4300 	/* any change? */
4301 	if (spec->cur_ctl_vals[idx] == *valp)
4302 		return 0;
4303 
4304 	spec->cur_ctl_vals[idx] = *valp;
4305 
4306 	idx = *valp;
4307 	tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
4308 
4309 	return 0;
4310 }
4311 
4312 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
4313 			      struct snd_ctl_elem_info *uinfo)
4314 {
4315 	int chs = get_amp_channels(kcontrol);
4316 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4317 	uinfo->count = chs == 3 ? 2 : 1;
4318 	uinfo->value.integer.min = 0;
4319 	uinfo->value.integer.max = 48;
4320 	uinfo->value.integer.step = 1;
4321 
4322 	return 0;
4323 }
4324 
4325 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
4326 				struct snd_ctl_elem_value *ucontrol)
4327 {
4328 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4329 	struct ca0132_spec *spec = codec->spec;
4330 	hda_nid_t nid = get_amp_nid(kcontrol);
4331 	long *valp = ucontrol->value.integer.value;
4332 	int idx;
4333 
4334 	idx = nid - TUNING_CTL_START_NID;
4335 	/* any change? */
4336 	if (spec->cur_ctl_vals[idx] == *valp)
4337 		return 0;
4338 
4339 	spec->cur_ctl_vals[idx] = *valp;
4340 
4341 	idx = *valp;
4342 	tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
4343 
4344 	return 1;
4345 }
4346 
4347 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
4348 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
4349 
4350 static int add_tuning_control(struct hda_codec *codec,
4351 				hda_nid_t pnid, hda_nid_t nid,
4352 				const char *name, int dir)
4353 {
4354 	char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4355 	int type = dir ? HDA_INPUT : HDA_OUTPUT;
4356 	struct snd_kcontrol_new knew =
4357 		HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
4358 
4359 	knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
4360 			SNDRV_CTL_ELEM_ACCESS_TLV_READ;
4361 	knew.tlv.c = NULL;
4362 	knew.tlv.p = NULL;
4363 	switch (pnid) {
4364 	case VOICE_FOCUS:
4365 		knew.info = voice_focus_ctl_info;
4366 		knew.get = tuning_ctl_get;
4367 		knew.put = voice_focus_ctl_put;
4368 		knew.tlv.p = voice_focus_db_scale;
4369 		break;
4370 	case MIC_SVM:
4371 		knew.info = mic_svm_ctl_info;
4372 		knew.get = tuning_ctl_get;
4373 		knew.put = mic_svm_ctl_put;
4374 		break;
4375 	case EQUALIZER:
4376 		knew.info = equalizer_ctl_info;
4377 		knew.get = tuning_ctl_get;
4378 		knew.put = equalizer_ctl_put;
4379 		knew.tlv.p = eq_db_scale;
4380 		break;
4381 	default:
4382 		return 0;
4383 	}
4384 	knew.private_value =
4385 		HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4386 	snprintf(namestr, sizeof(namestr), "%s %s Volume", name, dirstr[dir]);
4387 	return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4388 }
4389 
4390 static int add_tuning_ctls(struct hda_codec *codec)
4391 {
4392 	int i;
4393 	int err;
4394 
4395 	for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4396 		err = add_tuning_control(codec,
4397 					ca0132_tuning_ctls[i].parent_nid,
4398 					ca0132_tuning_ctls[i].nid,
4399 					ca0132_tuning_ctls[i].name,
4400 					ca0132_tuning_ctls[i].direct);
4401 		if (err < 0)
4402 			return err;
4403 	}
4404 
4405 	return 0;
4406 }
4407 
4408 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4409 {
4410 	struct ca0132_spec *spec = codec->spec;
4411 	int i;
4412 
4413 	/* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
4414 	spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4415 	/* SVM level defaults to 0.74. */
4416 	spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4417 
4418 	/* EQ defaults to 0dB. */
4419 	for (i = 2; i < TUNING_CTLS_COUNT; i++)
4420 		spec->cur_ctl_vals[i] = 24;
4421 }
4422 #endif /*ENABLE_TUNING_CONTROLS*/
4423 
4424 /*
4425  * Select the active output.
4426  * If autodetect is enabled, output will be selected based on jack detection.
4427  * If jack inserted, headphone will be selected, else built-in speakers
4428  * If autodetect is disabled, output will be selected based on selection.
4429  */
4430 static int ca0132_select_out(struct hda_codec *codec)
4431 {
4432 	struct ca0132_spec *spec = codec->spec;
4433 	unsigned int pin_ctl;
4434 	int jack_present;
4435 	int auto_jack;
4436 	unsigned int tmp;
4437 	int err;
4438 
4439 	codec_dbg(codec, "ca0132_select_out\n");
4440 
4441 	CLASS(snd_hda_power_pm, pm)(codec);
4442 
4443 	auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4444 
4445 	if (auto_jack)
4446 		jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
4447 	else
4448 		jack_present =
4449 			spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4450 
4451 	if (jack_present)
4452 		spec->cur_out_type = HEADPHONE_OUT;
4453 	else
4454 		spec->cur_out_type = SPEAKER_OUT;
4455 
4456 	if (spec->cur_out_type == SPEAKER_OUT) {
4457 		codec_dbg(codec, "ca0132_select_out speaker\n");
4458 		/*speaker out config*/
4459 		tmp = FLOAT_ONE;
4460 		err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4461 		if (err < 0)
4462 			return err;
4463 		/*enable speaker EQ*/
4464 		tmp = FLOAT_ONE;
4465 		err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4466 		if (err < 0)
4467 			return err;
4468 
4469 		/* Setup EAPD */
4470 		snd_hda_codec_write(codec, spec->out_pins[1], 0,
4471 				    VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4472 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
4473 				    AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4474 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
4475 				    VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4476 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
4477 				    AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4478 
4479 		/* disable headphone node */
4480 		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4481 					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4482 		snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4483 				    pin_ctl & ~PIN_HP);
4484 		/* enable speaker node */
4485 		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4486 				AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4487 		snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4488 				    pin_ctl | PIN_OUT);
4489 	} else {
4490 		codec_dbg(codec, "ca0132_select_out hp\n");
4491 		/*headphone out config*/
4492 		tmp = FLOAT_ZERO;
4493 		err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4494 		if (err < 0)
4495 			return err;
4496 		/*disable speaker EQ*/
4497 		tmp = FLOAT_ZERO;
4498 		err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4499 		if (err < 0)
4500 			return err;
4501 
4502 		/* Setup EAPD */
4503 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
4504 				    VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4505 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
4506 				    AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4507 		snd_hda_codec_write(codec, spec->out_pins[1], 0,
4508 				    VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4509 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
4510 				    AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4511 
4512 		/* disable speaker*/
4513 		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4514 					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4515 		snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4516 				    pin_ctl & ~PIN_HP);
4517 		/* enable headphone*/
4518 		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4519 					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4520 		snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4521 				    pin_ctl | PIN_HP);
4522 	}
4523 
4524 	return 0;
4525 }
4526 
4527 static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4528 static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
4529 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4530 
4531 static void ae5_mmio_select_out(struct hda_codec *codec)
4532 {
4533 	struct ca0132_spec *spec = codec->spec;
4534 	const struct ae_ca0113_output_set *out_cmds;
4535 	unsigned int i;
4536 
4537 	if (ca0132_quirk(spec) == QUIRK_AE5)
4538 		out_cmds = &ae5_ca0113_output_presets;
4539 	else
4540 		out_cmds = &ae7_ca0113_output_presets;
4541 
4542 	for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++)
4543 		ca0113_mmio_command_set(codec, out_cmds->group[i],
4544 				out_cmds->target[i],
4545 				out_cmds->vals[spec->cur_out_type][i]);
4546 }
4547 
4548 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)
4549 {
4550 	struct ca0132_spec *spec = codec->spec;
4551 	int quirk = ca0132_quirk(spec);
4552 	unsigned int tmp;
4553 	int err;
4554 
4555 	/* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */
4556 	if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0
4557 			|| spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4558 		return 0;
4559 
4560 	/* Set front L/R full range. Zero for full-range, one for redirection. */
4561 	tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
4562 	err = dspio_set_uint_param(codec, 0x96,
4563 			SPEAKER_FULL_RANGE_FRONT_L_R, tmp);
4564 	if (err < 0)
4565 		return err;
4566 
4567 	/* When setting full-range rear, both rear and center/lfe are set. */
4568 	tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE;
4569 	err = dspio_set_uint_param(codec, 0x96,
4570 			SPEAKER_FULL_RANGE_CENTER_LFE, tmp);
4571 	if (err < 0)
4572 		return err;
4573 
4574 	err = dspio_set_uint_param(codec, 0x96,
4575 			SPEAKER_FULL_RANGE_REAR_L_R, tmp);
4576 	if (err < 0)
4577 		return err;
4578 
4579 	/*
4580 	 * Only the AE series cards set this value when setting full-range,
4581 	 * and it's always 1.0f.
4582 	 */
4583 	if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) {
4584 		err = dspio_set_uint_param(codec, 0x96,
4585 				SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE);
4586 		if (err < 0)
4587 			return err;
4588 	}
4589 
4590 	return 0;
4591 }
4592 
4593 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec,
4594 		bool val)
4595 {
4596 	struct ca0132_spec *spec = codec->spec;
4597 	unsigned int tmp;
4598 	int err;
4599 
4600 	if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 &&
4601 			spec->channel_cfg_val != SPEAKER_CHANNELS_2_0)
4602 		tmp = FLOAT_ONE;
4603 	else
4604 		tmp = FLOAT_ZERO;
4605 
4606 	err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
4607 	if (err < 0)
4608 		return err;
4609 
4610 	/* If it is enabled, make sure to set the crossover frequency. */
4611 	if (tmp) {
4612 		tmp = float_xbass_xover_lookup[spec->xbass_xover_freq];
4613 		err = dspio_set_uint_param(codec, 0x96,
4614 				SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp);
4615 		if (err < 0)
4616 			return err;
4617 	}
4618 
4619 	return 0;
4620 }
4621 
4622 /*
4623  * These are the commands needed to setup output on each of the different card
4624  * types.
4625  */
4626 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec,
4627 		const struct ca0132_alt_out_set_quirk_data **quirk_data)
4628 {
4629 	struct ca0132_spec *spec = codec->spec;
4630 	int quirk = ca0132_quirk(spec);
4631 	unsigned int i;
4632 
4633 	*quirk_data = NULL;
4634 	for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) {
4635 		if (quirk_out_set_data[i].quirk_id == quirk) {
4636 			*quirk_data = &quirk_out_set_data[i];
4637 			return;
4638 		}
4639 	}
4640 }
4641 
4642 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)
4643 {
4644 	const struct ca0132_alt_out_set_quirk_data *quirk_data;
4645 	const struct ca0132_alt_out_set_info *out_info;
4646 	struct ca0132_spec *spec = codec->spec;
4647 	unsigned int i, gpio_data;
4648 	int err;
4649 
4650 	ca0132_alt_select_out_get_quirk_data(codec, &quirk_data);
4651 	if (!quirk_data)
4652 		return 0;
4653 
4654 	out_info = &quirk_data->out_set_info[spec->cur_out_type];
4655 	if (quirk_data->is_ae_series)
4656 		ae5_mmio_select_out(codec);
4657 
4658 	if (out_info->has_hda_gpio) {
4659 		gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
4660 				AC_VERB_GET_GPIO_DATA, 0);
4661 
4662 		if (out_info->hda_gpio_set)
4663 			gpio_data |= (1 << out_info->hda_gpio_pin);
4664 		else
4665 			gpio_data &= ~(1 << out_info->hda_gpio_pin);
4666 
4667 		snd_hda_codec_write(codec, codec->core.afg, 0,
4668 				    AC_VERB_SET_GPIO_DATA, gpio_data);
4669 	}
4670 
4671 	if (out_info->mmio_gpio_count) {
4672 		for (i = 0; i < out_info->mmio_gpio_count; i++) {
4673 			ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i],
4674 					out_info->mmio_gpio_set[i]);
4675 		}
4676 	}
4677 
4678 	if (out_info->scp_cmds_count) {
4679 		for (i = 0; i < out_info->scp_cmds_count; i++) {
4680 			err = dspio_set_uint_param(codec,
4681 					out_info->scp_cmd_mid[i],
4682 					out_info->scp_cmd_req[i],
4683 					out_info->scp_cmd_val[i]);
4684 			if (err < 0)
4685 				return err;
4686 		}
4687 	}
4688 
4689 	chipio_set_control_param(codec, 0x0d, out_info->dac2port);
4690 
4691 	if (out_info->has_chipio_write) {
4692 		chipio_write(codec, out_info->chipio_write_addr,
4693 				out_info->chipio_write_data);
4694 	}
4695 
4696 	if (quirk_data->has_headphone_gain) {
4697 		if (spec->cur_out_type != HEADPHONE_OUT) {
4698 			if (quirk_data->is_ae_series)
4699 				ae5_headphone_gain_set(codec, 2);
4700 			else
4701 				zxr_headphone_gain_set(codec, 0);
4702 		} else {
4703 			if (quirk_data->is_ae_series)
4704 				ae5_headphone_gain_set(codec,
4705 						spec->ae5_headphone_gain_val);
4706 			else
4707 				zxr_headphone_gain_set(codec,
4708 						spec->zxr_gain_set);
4709 		}
4710 	}
4711 
4712 	return 0;
4713 }
4714 
4715 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid,
4716 		bool out_enable, bool hp_enable)
4717 {
4718 	unsigned int pin_ctl;
4719 
4720 	pin_ctl = snd_hda_codec_read(codec, nid, 0,
4721 			AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4722 
4723 	pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP;
4724 	pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT;
4725 	snd_hda_set_pin_ctl(codec, nid, pin_ctl);
4726 }
4727 
4728 /*
4729  * This function behaves similarly to the ca0132_select_out funciton above,
4730  * except with a few differences. It adds the ability to select the current
4731  * output with an enumerated control "output source" if the auto detect
4732  * mute switch is set to off. If the auto detect mute switch is enabled, it
4733  * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4734  * It also adds the ability to auto-detect the front headphone port.
4735  */
4736 static int ca0132_alt_select_out(struct hda_codec *codec)
4737 {
4738 	struct ca0132_spec *spec = codec->spec;
4739 	unsigned int tmp, outfx_set;
4740 	int jack_present;
4741 	int auto_jack;
4742 	int err;
4743 	/* Default Headphone is rear headphone */
4744 	hda_nid_t headphone_nid = spec->out_pins[1];
4745 
4746 	codec_dbg(codec, "%s\n", __func__);
4747 
4748 	CLASS(snd_hda_power_pm, pm)(codec);
4749 
4750 	auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4751 
4752 	/*
4753 	 * If headphone rear or front is plugged in, set to headphone.
4754 	 * If neither is plugged in, set to rear line out. Only if
4755 	 * hp/speaker auto detect is enabled.
4756 	 */
4757 	if (auto_jack) {
4758 		jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4759 			   snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4760 
4761 		if (jack_present)
4762 			spec->cur_out_type = HEADPHONE_OUT;
4763 		else
4764 			spec->cur_out_type = SPEAKER_OUT;
4765 	} else
4766 		spec->cur_out_type = spec->out_enum_val;
4767 
4768 	outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID];
4769 
4770 	/* Begin DSP output switch, mute DSP volume. */
4771 	err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);
4772 	if (err < 0)
4773 		return err;
4774 
4775 	err = ca0132_alt_select_out_quirk_set(codec);
4776 	if (err < 0)
4777 		return err;
4778 
4779 	switch (spec->cur_out_type) {
4780 	case SPEAKER_OUT:
4781 		codec_dbg(codec, "%s speaker\n", __func__);
4782 
4783 		/* Enable EAPD */
4784 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
4785 			AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4786 
4787 		/* Disable headphone node. */
4788 		ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);
4789 		/* Set front L-R to output. */
4790 		ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);
4791 		/* Set Center/LFE to output. */
4792 		ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);
4793 		/* Set rear surround to output. */
4794 		ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);
4795 
4796 		/*
4797 		 * Without PlayEnhancement being enabled, if we've got a 2.0
4798 		 * setup, set it to floating point eight to disable any DSP
4799 		 * processing effects.
4800 		 */
4801 		if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4802 			tmp = FLOAT_EIGHT;
4803 		else
4804 			tmp = speaker_channel_cfgs[spec->channel_cfg_val].val;
4805 
4806 		err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4807 		if (err < 0)
4808 			return err;
4809 
4810 		break;
4811 	case HEADPHONE_OUT:
4812 		codec_dbg(codec, "%s hp\n", __func__);
4813 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
4814 			AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4815 
4816 		/* Disable all speaker nodes. */
4817 		ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);
4818 		ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);
4819 		ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);
4820 
4821 		/* enable headphone, either front or rear */
4822 		if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4823 			headphone_nid = spec->out_pins[2];
4824 		else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4825 			headphone_nid = spec->out_pins[1];
4826 
4827 		ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1);
4828 
4829 		if (outfx_set)
4830 			err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4831 		else
4832 			err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4833 
4834 		if (err < 0)
4835 			return err;
4836 		break;
4837 	}
4838 	/*
4839 	 * If output effects are enabled, set the X-Bass effect value again to
4840 	 * make sure that it's properly enabled/disabled for speaker
4841 	 * configurations with an LFE channel.
4842 	 */
4843 	if (outfx_set)
4844 		ca0132_effects_set(codec, X_BASS,
4845 			spec->effects_switch[X_BASS - EFFECT_START_NID]);
4846 
4847 	/* Set speaker EQ bypass attenuation to 0. */
4848 	err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);
4849 	if (err < 0)
4850 		return err;
4851 
4852 	/*
4853 	 * Although unused on all cards but the AE series, this is always set
4854 	 * to zero when setting the output.
4855 	 */
4856 	err = dspio_set_uint_param(codec, 0x96,
4857 			SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO);
4858 	if (err < 0)
4859 		return err;
4860 
4861 	if (spec->cur_out_type == SPEAKER_OUT)
4862 		err = ca0132_alt_surround_set_bass_redirection(codec,
4863 				spec->bass_redirection_val);
4864 	else
4865 		err = ca0132_alt_surround_set_bass_redirection(codec, 0);
4866 	if (err < 0)
4867 		return err;
4868 
4869 	/* Unmute DSP now that we're done with output selection. */
4870 	err = dspio_set_uint_param(codec, 0x96,
4871 			SPEAKER_TUNING_MUTE, FLOAT_ZERO);
4872 	if (err < 0)
4873 		return err;
4874 
4875 	if (spec->cur_out_type == SPEAKER_OUT) {
4876 		err = ca0132_alt_set_full_range_speaker(codec);
4877 		if (err < 0)
4878 			return err;
4879 	}
4880 
4881 	return 0;
4882 }
4883 
4884 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4885 {
4886 	struct ca0132_spec *spec = container_of(
4887 		to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4888 	struct hda_jack_tbl *jack;
4889 
4890 	if (ca0132_use_alt_functions(spec))
4891 		ca0132_alt_select_out(spec->codec);
4892 	else
4893 		ca0132_select_out(spec->codec);
4894 
4895 	jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4896 	if (jack) {
4897 		jack->block_report = 0;
4898 		snd_hda_jack_report_sync(spec->codec);
4899 	}
4900 }
4901 
4902 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4903 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4904 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4905 static int stop_mic1(struct hda_codec *codec);
4906 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4907 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4908 
4909 /*
4910  * Select the active VIP source
4911  */
4912 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4913 {
4914 	struct ca0132_spec *spec = codec->spec;
4915 	unsigned int tmp;
4916 
4917 	if (spec->dsp_state != DSP_DOWNLOADED)
4918 		return 0;
4919 
4920 	/* if CrystalVoice if off, vipsource should be 0 */
4921 	if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4922 	    (val == 0)) {
4923 		chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4924 		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4925 		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4926 		if (spec->cur_mic_type == DIGITAL_MIC)
4927 			tmp = FLOAT_TWO;
4928 		else
4929 			tmp = FLOAT_ONE;
4930 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4931 		tmp = FLOAT_ZERO;
4932 		dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4933 	} else {
4934 		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4935 		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4936 		if (spec->cur_mic_type == DIGITAL_MIC)
4937 			tmp = FLOAT_TWO;
4938 		else
4939 			tmp = FLOAT_ONE;
4940 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4941 		tmp = FLOAT_ONE;
4942 		dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4943 		msleep(20);
4944 		chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4945 	}
4946 
4947 	return 1;
4948 }
4949 
4950 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4951 {
4952 	struct ca0132_spec *spec = codec->spec;
4953 	unsigned int tmp;
4954 
4955 	if (spec->dsp_state != DSP_DOWNLOADED)
4956 		return 0;
4957 
4958 	codec_dbg(codec, "%s\n", __func__);
4959 
4960 	chipio_set_stream_control(codec, 0x03, 0);
4961 	chipio_set_stream_control(codec, 0x04, 0);
4962 
4963 	/* if CrystalVoice is off, vipsource should be 0 */
4964 	if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4965 	    (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4966 		codec_dbg(codec, "%s: off.", __func__);
4967 		chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4968 
4969 		tmp = FLOAT_ZERO;
4970 		dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4971 
4972 		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4973 		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4974 		if (ca0132_quirk(spec) == QUIRK_R3DI)
4975 			chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4976 
4977 
4978 		if (spec->in_enum_val == REAR_LINE_IN)
4979 			tmp = FLOAT_ZERO;
4980 		else {
4981 			if (ca0132_quirk(spec) == QUIRK_SBZ)
4982 				tmp = FLOAT_THREE;
4983 			else
4984 				tmp = FLOAT_ONE;
4985 		}
4986 
4987 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4988 
4989 	} else {
4990 		codec_dbg(codec, "%s: on.", __func__);
4991 		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4992 		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4993 		if (ca0132_quirk(spec) == QUIRK_R3DI)
4994 			chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4995 
4996 		if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4997 			tmp = FLOAT_TWO;
4998 		else
4999 			tmp = FLOAT_ONE;
5000 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5001 
5002 		tmp = FLOAT_ONE;
5003 		dspio_set_uint_param(codec, 0x80, 0x05, tmp);
5004 
5005 		msleep(20);
5006 		chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
5007 	}
5008 
5009 	chipio_set_stream_control(codec, 0x03, 1);
5010 	chipio_set_stream_control(codec, 0x04, 1);
5011 
5012 	return 1;
5013 }
5014 
5015 /*
5016  * Select the active microphone.
5017  * If autodetect is enabled, mic will be selected based on jack detection.
5018  * If jack inserted, ext.mic will be selected, else built-in mic
5019  * If autodetect is disabled, mic will be selected based on selection.
5020  */
5021 static int ca0132_select_mic(struct hda_codec *codec)
5022 {
5023 	struct ca0132_spec *spec = codec->spec;
5024 	int jack_present;
5025 	int auto_jack;
5026 
5027 	codec_dbg(codec, "ca0132_select_mic\n");
5028 
5029 	CLASS(snd_hda_power_pm, pm)(codec);
5030 
5031 	auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5032 
5033 	if (auto_jack)
5034 		jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5035 	else
5036 		jack_present =
5037 			spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
5038 
5039 	if (jack_present)
5040 		spec->cur_mic_type = LINE_MIC_IN;
5041 	else
5042 		spec->cur_mic_type = DIGITAL_MIC;
5043 
5044 	if (spec->cur_mic_type == DIGITAL_MIC) {
5045 		/* enable digital Mic */
5046 		chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
5047 		ca0132_set_dmic(codec, 1);
5048 		ca0132_mic_boost_set(codec, 0);
5049 		/* set voice focus */
5050 		ca0132_effects_set(codec, VOICE_FOCUS,
5051 				   spec->effects_switch
5052 				   [VOICE_FOCUS - EFFECT_START_NID]);
5053 	} else {
5054 		/* disable digital Mic */
5055 		chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
5056 		ca0132_set_dmic(codec, 0);
5057 		ca0132_mic_boost_set(codec, spec->cur_mic_boost);
5058 		/* disable voice focus */
5059 		ca0132_effects_set(codec, VOICE_FOCUS, 0);
5060 	}
5061 
5062 	return 0;
5063 }
5064 
5065 /*
5066  * Select the active input.
5067  * Mic detection isn't used, because it's kind of pointless on the SBZ.
5068  * The front mic has no jack-detection, so the only way to switch to it
5069  * is to do it manually in alsamixer.
5070  */
5071 static int ca0132_alt_select_in(struct hda_codec *codec)
5072 {
5073 	struct ca0132_spec *spec = codec->spec;
5074 	unsigned int tmp;
5075 
5076 	codec_dbg(codec, "%s\n", __func__);
5077 
5078 	CLASS(snd_hda_power_pm, pm)(codec);
5079 
5080 	chipio_set_stream_control(codec, 0x03, 0);
5081 	chipio_set_stream_control(codec, 0x04, 0);
5082 
5083 	spec->cur_mic_type = spec->in_enum_val;
5084 
5085 	switch (spec->cur_mic_type) {
5086 	case REAR_MIC:
5087 		switch (ca0132_quirk(spec)) {
5088 		case QUIRK_SBZ:
5089 		case QUIRK_R3D:
5090 			ca0113_mmio_gpio_set(codec, 0, false);
5091 			tmp = FLOAT_THREE;
5092 			break;
5093 		case QUIRK_ZXR:
5094 			tmp = FLOAT_THREE;
5095 			break;
5096 		case QUIRK_R3DI:
5097 			r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5098 			tmp = FLOAT_ONE;
5099 			break;
5100 		case QUIRK_AE5:
5101 			ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5102 			tmp = FLOAT_THREE;
5103 			break;
5104 		case QUIRK_AE7:
5105 			ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5106 			tmp = FLOAT_THREE;
5107 			chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5108 					SR_96_000);
5109 			chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5110 					SR_96_000);
5111 			dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5112 			break;
5113 		default:
5114 			tmp = FLOAT_ONE;
5115 			break;
5116 		}
5117 
5118 		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5119 		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5120 		if (ca0132_quirk(spec) == QUIRK_R3DI)
5121 			chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5122 
5123 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5124 
5125 		chipio_set_stream_control(codec, 0x03, 1);
5126 		chipio_set_stream_control(codec, 0x04, 1);
5127 		switch (ca0132_quirk(spec)) {
5128 		case QUIRK_SBZ:
5129 			chipio_write(codec, 0x18B098, 0x0000000C);
5130 			chipio_write(codec, 0x18B09C, 0x0000000C);
5131 			break;
5132 		case QUIRK_ZXR:
5133 			chipio_write(codec, 0x18B098, 0x0000000C);
5134 			chipio_write(codec, 0x18B09C, 0x000000CC);
5135 			break;
5136 		case QUIRK_AE5:
5137 			chipio_write(codec, 0x18B098, 0x0000000C);
5138 			chipio_write(codec, 0x18B09C, 0x0000004C);
5139 			break;
5140 		default:
5141 			break;
5142 		}
5143 		ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5144 		break;
5145 	case REAR_LINE_IN:
5146 		ca0132_mic_boost_set(codec, 0);
5147 		switch (ca0132_quirk(spec)) {
5148 		case QUIRK_SBZ:
5149 		case QUIRK_R3D:
5150 			ca0113_mmio_gpio_set(codec, 0, false);
5151 			break;
5152 		case QUIRK_R3DI:
5153 			r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5154 			break;
5155 		case QUIRK_AE5:
5156 			ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5157 			break;
5158 		case QUIRK_AE7:
5159 			ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5160 			chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5161 					SR_96_000);
5162 			chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5163 					SR_96_000);
5164 			dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5165 			break;
5166 		default:
5167 			break;
5168 		}
5169 
5170 		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5171 		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5172 		if (ca0132_quirk(spec) == QUIRK_R3DI)
5173 			chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5174 
5175 		if (ca0132_quirk(spec) == QUIRK_AE7)
5176 			tmp = FLOAT_THREE;
5177 		else
5178 			tmp = FLOAT_ZERO;
5179 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5180 
5181 		switch (ca0132_quirk(spec)) {
5182 		case QUIRK_SBZ:
5183 		case QUIRK_AE5:
5184 			chipio_write(codec, 0x18B098, 0x00000000);
5185 			chipio_write(codec, 0x18B09C, 0x00000000);
5186 			break;
5187 		default:
5188 			break;
5189 		}
5190 		chipio_set_stream_control(codec, 0x03, 1);
5191 		chipio_set_stream_control(codec, 0x04, 1);
5192 		break;
5193 	case FRONT_MIC:
5194 		switch (ca0132_quirk(spec)) {
5195 		case QUIRK_SBZ:
5196 		case QUIRK_R3D:
5197 			ca0113_mmio_gpio_set(codec, 0, true);
5198 			ca0113_mmio_gpio_set(codec, 5, false);
5199 			tmp = FLOAT_THREE;
5200 			break;
5201 		case QUIRK_R3DI:
5202 			r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
5203 			tmp = FLOAT_ONE;
5204 			break;
5205 		case QUIRK_AE5:
5206 			ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5207 			tmp = FLOAT_THREE;
5208 			break;
5209 		default:
5210 			tmp = FLOAT_ONE;
5211 			break;
5212 		}
5213 
5214 		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5215 		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5216 		if (ca0132_quirk(spec) == QUIRK_R3DI)
5217 			chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5218 
5219 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5220 
5221 		chipio_set_stream_control(codec, 0x03, 1);
5222 		chipio_set_stream_control(codec, 0x04, 1);
5223 
5224 		switch (ca0132_quirk(spec)) {
5225 		case QUIRK_SBZ:
5226 			chipio_write(codec, 0x18B098, 0x0000000C);
5227 			chipio_write(codec, 0x18B09C, 0x000000CC);
5228 			break;
5229 		case QUIRK_AE5:
5230 			chipio_write(codec, 0x18B098, 0x0000000C);
5231 			chipio_write(codec, 0x18B09C, 0x0000004C);
5232 			break;
5233 		default:
5234 			break;
5235 		}
5236 		ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5237 		break;
5238 	}
5239 	ca0132_cvoice_switch_set(codec);
5240 
5241 	return 0;
5242 }
5243 
5244 /*
5245  * Check if VNODE settings take effect immediately.
5246  */
5247 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
5248 				     hda_nid_t vnid,
5249 				     hda_nid_t *shared_nid)
5250 {
5251 	struct ca0132_spec *spec = codec->spec;
5252 	hda_nid_t nid;
5253 
5254 	switch (vnid) {
5255 	case VNID_SPK:
5256 		nid = spec->shared_out_nid;
5257 		break;
5258 	case VNID_MIC:
5259 		nid = spec->shared_mic_nid;
5260 		break;
5261 	default:
5262 		return false;
5263 	}
5264 
5265 	if (shared_nid)
5266 		*shared_nid = nid;
5267 
5268 	return true;
5269 }
5270 
5271 /*
5272 * The following functions are control change helpers.
5273 * They return 0 if no changed.  Return 1 if changed.
5274 */
5275 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
5276 {
5277 	struct ca0132_spec *spec = codec->spec;
5278 	unsigned int tmp;
5279 
5280 	/* based on CrystalVoice state to enable VoiceFX. */
5281 	if (enable) {
5282 		tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
5283 			FLOAT_ONE : FLOAT_ZERO;
5284 	} else {
5285 		tmp = FLOAT_ZERO;
5286 	}
5287 
5288 	dspio_set_uint_param(codec, ca0132_voicefx.mid,
5289 			     ca0132_voicefx.reqs[0], tmp);
5290 
5291 	return 1;
5292 }
5293 
5294 /*
5295  * Set the effects parameters
5296  */
5297 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
5298 {
5299 	struct ca0132_spec *spec = codec->spec;
5300 	unsigned int on, tmp, channel_cfg;
5301 	int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5302 	int err = 0;
5303 	int idx = nid - EFFECT_START_NID;
5304 
5305 	if ((idx < 0) || (idx >= num_fx))
5306 		return 0; /* no changed */
5307 
5308 	/* for out effect, qualify with PE */
5309 	if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
5310 		/* if PE if off, turn off out effects. */
5311 		if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
5312 			val = 0;
5313 		if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) {
5314 			channel_cfg = spec->channel_cfg_val;
5315 			if (channel_cfg != SPEAKER_CHANNELS_2_0 &&
5316 					channel_cfg != SPEAKER_CHANNELS_4_0)
5317 				val = 0;
5318 		}
5319 	}
5320 
5321 	/* for in effect, qualify with CrystalVoice */
5322 	if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
5323 		/* if CrystalVoice if off, turn off in effects. */
5324 		if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
5325 			val = 0;
5326 
5327 		/* Voice Focus applies to 2-ch Mic, Digital Mic */
5328 		if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
5329 			val = 0;
5330 
5331 		/* If Voice Focus on SBZ, set to two channel. */
5332 		if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)
5333 				&& (spec->cur_mic_type != REAR_LINE_IN)) {
5334 			if (spec->effects_switch[CRYSTAL_VOICE -
5335 						 EFFECT_START_NID]) {
5336 
5337 				if (spec->effects_switch[VOICE_FOCUS -
5338 							 EFFECT_START_NID]) {
5339 					tmp = FLOAT_TWO;
5340 					val = 1;
5341 				} else
5342 					tmp = FLOAT_ONE;
5343 
5344 				dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5345 			}
5346 		}
5347 		/*
5348 		 * For SBZ noise reduction, there's an extra command
5349 		 * to module ID 0x47. No clue why.
5350 		 */
5351 		if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)
5352 				&& (spec->cur_mic_type != REAR_LINE_IN)) {
5353 			if (spec->effects_switch[CRYSTAL_VOICE -
5354 						 EFFECT_START_NID]) {
5355 				if (spec->effects_switch[NOISE_REDUCTION -
5356 							 EFFECT_START_NID])
5357 					tmp = FLOAT_ONE;
5358 				else
5359 					tmp = FLOAT_ZERO;
5360 			} else
5361 				tmp = FLOAT_ZERO;
5362 
5363 			dspio_set_uint_param(codec, 0x47, 0x00, tmp);
5364 		}
5365 
5366 		/* If rear line in disable effects. */
5367 		if (ca0132_use_alt_functions(spec) &&
5368 				spec->in_enum_val == REAR_LINE_IN)
5369 			val = 0;
5370 	}
5371 
5372 	codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5373 		    nid, val);
5374 
5375 	on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
5376 	err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5377 				   ca0132_effects[idx].reqs[0], on);
5378 
5379 	if (err < 0)
5380 		return 0; /* no changed */
5381 
5382 	return 1;
5383 }
5384 
5385 /*
5386  * Turn on/off Playback Enhancements
5387  */
5388 static int ca0132_pe_switch_set(struct hda_codec *codec)
5389 {
5390 	struct ca0132_spec *spec = codec->spec;
5391 	hda_nid_t nid;
5392 	int i, ret = 0;
5393 
5394 	codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
5395 		    spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
5396 
5397 	if (ca0132_use_alt_functions(spec))
5398 		ca0132_alt_select_out(codec);
5399 
5400 	i = OUT_EFFECT_START_NID - EFFECT_START_NID;
5401 	nid = OUT_EFFECT_START_NID;
5402 	/* PE affects all out effects */
5403 	for (; nid < OUT_EFFECT_END_NID; nid++, i++)
5404 		ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5405 
5406 	return ret;
5407 }
5408 
5409 /* Check if Mic1 is streaming, if so, stop streaming */
5410 static int stop_mic1(struct hda_codec *codec)
5411 {
5412 	struct ca0132_spec *spec = codec->spec;
5413 	unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
5414 						 AC_VERB_GET_CONV, 0);
5415 	if (oldval != 0)
5416 		snd_hda_codec_write(codec, spec->adcs[0], 0,
5417 				    AC_VERB_SET_CHANNEL_STREAMID,
5418 				    0);
5419 	return oldval;
5420 }
5421 
5422 /* Resume Mic1 streaming if it was stopped. */
5423 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
5424 {
5425 	struct ca0132_spec *spec = codec->spec;
5426 	/* Restore the previous stream and channel */
5427 	if (oldval != 0)
5428 		snd_hda_codec_write(codec, spec->adcs[0], 0,
5429 				    AC_VERB_SET_CHANNEL_STREAMID,
5430 				    oldval);
5431 }
5432 
5433 /*
5434  * Turn on/off CrystalVoice
5435  */
5436 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
5437 {
5438 	struct ca0132_spec *spec = codec->spec;
5439 	hda_nid_t nid;
5440 	int i, ret = 0;
5441 	unsigned int oldval;
5442 
5443 	codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
5444 		    spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
5445 
5446 	i = IN_EFFECT_START_NID - EFFECT_START_NID;
5447 	nid = IN_EFFECT_START_NID;
5448 	/* CrystalVoice affects all in effects */
5449 	for (; nid < IN_EFFECT_END_NID; nid++, i++)
5450 		ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5451 
5452 	/* including VoiceFX */
5453 	ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5454 
5455 	/* set correct vipsource */
5456 	oldval = stop_mic1(codec);
5457 	if (ca0132_use_alt_functions(spec))
5458 		ret |= ca0132_alt_set_vipsource(codec, 1);
5459 	else
5460 		ret |= ca0132_set_vipsource(codec, 1);
5461 	resume_mic1(codec, oldval);
5462 	return ret;
5463 }
5464 
5465 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5466 {
5467 	struct ca0132_spec *spec = codec->spec;
5468 	int ret = 0;
5469 
5470 	if (val) /* on */
5471 		ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5472 					HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5473 	else /* off */
5474 		ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5475 					HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5476 
5477 	return ret;
5478 }
5479 
5480 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5481 {
5482 	struct ca0132_spec *spec = codec->spec;
5483 	int ret = 0;
5484 
5485 	ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5486 				HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5487 	return ret;
5488 }
5489 
5490 static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5491 {
5492 	unsigned int i;
5493 
5494 	for (i = 0; i < 4; i++)
5495 		ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5496 				ae5_headphone_gain_presets[val].vals[i]);
5497 	return 0;
5498 }
5499 
5500 /*
5501  * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5502  * amplifier to handle a 600 ohm load.
5503  */
5504 static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5505 {
5506 	ca0113_mmio_gpio_set(codec, 1, val);
5507 
5508 	return 0;
5509 }
5510 
5511 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5512 				struct snd_ctl_elem_value *ucontrol)
5513 {
5514 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5515 	hda_nid_t nid = get_amp_nid(kcontrol);
5516 	hda_nid_t shared_nid = 0;
5517 	bool effective;
5518 	int ret = 0;
5519 	struct ca0132_spec *spec = codec->spec;
5520 	int auto_jack;
5521 
5522 	if (nid == VNID_HP_SEL) {
5523 		auto_jack =
5524 			spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5525 		if (!auto_jack) {
5526 			if (ca0132_use_alt_functions(spec))
5527 				ca0132_alt_select_out(codec);
5528 			else
5529 				ca0132_select_out(codec);
5530 		}
5531 		return 1;
5532 	}
5533 
5534 	if (nid == VNID_AMIC1_SEL) {
5535 		auto_jack =
5536 			spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5537 		if (!auto_jack)
5538 			ca0132_select_mic(codec);
5539 		return 1;
5540 	}
5541 
5542 	if (nid == VNID_HP_ASEL) {
5543 		if (ca0132_use_alt_functions(spec))
5544 			ca0132_alt_select_out(codec);
5545 		else
5546 			ca0132_select_out(codec);
5547 		return 1;
5548 	}
5549 
5550 	if (nid == VNID_AMIC1_ASEL) {
5551 		ca0132_select_mic(codec);
5552 		return 1;
5553 	}
5554 
5555 	/* if effective conditions, then update hw immediately. */
5556 	effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5557 	if (effective) {
5558 		int dir = get_amp_direction(kcontrol);
5559 		int ch = get_amp_channels(kcontrol);
5560 		unsigned long pval;
5561 
5562 		guard(mutex)(&codec->control_mutex);
5563 		pval = kcontrol->private_value;
5564 		kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5565 								0, dir);
5566 		ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5567 		kcontrol->private_value = pval;
5568 	}
5569 
5570 	return ret;
5571 }
5572 /* End of control change helpers. */
5573 
5574 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec,
5575 		long idx)
5576 {
5577 	CLASS(snd_hda_power, pm)(codec);
5578 
5579 	dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ,
5580 			&(float_xbass_xover_lookup[idx]), sizeof(unsigned int));
5581 }
5582 
5583 /*
5584  * Below I've added controls to mess with the effect levels, I've only enabled
5585  * them on the Sound Blaster Z, but they would probably also work on the
5586  * Chromebook. I figured they were probably tuned specifically for it, and left
5587  * out for a reason.
5588  */
5589 
5590 /* Sets DSP effect level from the sliders above the controls */
5591 
5592 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5593 			  const unsigned int *lookup, int idx)
5594 {
5595 	int i = 0;
5596 	unsigned int y;
5597 	/*
5598 	 * For X_BASS, req 2 is actually crossover freq instead of
5599 	 * effect level
5600 	 */
5601 	if (nid == X_BASS)
5602 		y = 2;
5603 	else
5604 		y = 1;
5605 
5606 	CLASS(snd_hda_power, pm)(codec);
5607 	if (nid == XBASS_XOVER) {
5608 		for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5609 			if (ca0132_effects[i].nid == X_BASS)
5610 				break;
5611 
5612 		dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5613 				ca0132_effects[i].reqs[1],
5614 				&(lookup[idx - 1]), sizeof(unsigned int));
5615 	} else {
5616 		/* Find the actual effect structure */
5617 		for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5618 			if (nid == ca0132_effects[i].nid)
5619 				break;
5620 
5621 		dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5622 				ca0132_effects[i].reqs[y],
5623 				&(lookup[idx]), sizeof(unsigned int));
5624 	}
5625 
5626 	return 0;
5627 }
5628 
5629 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5630 			  struct snd_ctl_elem_value *ucontrol)
5631 {
5632 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5633 	struct ca0132_spec *spec = codec->spec;
5634 	long *valp = ucontrol->value.integer.value;
5635 	hda_nid_t nid = get_amp_nid(kcontrol);
5636 
5637 	if (nid == BASS_REDIRECTION_XOVER)
5638 		*valp = spec->bass_redirect_xover_freq;
5639 	else
5640 		*valp = spec->xbass_xover_freq;
5641 
5642 	return 0;
5643 }
5644 
5645 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5646 			  struct snd_ctl_elem_value *ucontrol)
5647 {
5648 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5649 	struct ca0132_spec *spec = codec->spec;
5650 	hda_nid_t nid = get_amp_nid(kcontrol);
5651 	long *valp = ucontrol->value.integer.value;
5652 	int idx = nid - OUT_EFFECT_START_NID;
5653 
5654 	*valp = spec->fx_ctl_val[idx];
5655 	return 0;
5656 }
5657 
5658 /*
5659  * The X-bass crossover starts at 10hz, so the min is 1. The
5660  * frequency is set in multiples of 10.
5661  */
5662 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5663 		struct snd_ctl_elem_info *uinfo)
5664 {
5665 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5666 	uinfo->count = 1;
5667 	uinfo->value.integer.min = 1;
5668 	uinfo->value.integer.max = 100;
5669 	uinfo->value.integer.step = 1;
5670 
5671 	return 0;
5672 }
5673 
5674 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5675 		struct snd_ctl_elem_info *uinfo)
5676 {
5677 	int chs = get_amp_channels(kcontrol);
5678 
5679 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5680 	uinfo->count = chs == 3 ? 2 : 1;
5681 	uinfo->value.integer.min = 0;
5682 	uinfo->value.integer.max = 100;
5683 	uinfo->value.integer.step = 1;
5684 
5685 	return 0;
5686 }
5687 
5688 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5689 				struct snd_ctl_elem_value *ucontrol)
5690 {
5691 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5692 	struct ca0132_spec *spec = codec->spec;
5693 	hda_nid_t nid = get_amp_nid(kcontrol);
5694 	long *valp = ucontrol->value.integer.value;
5695 	long *cur_val;
5696 	int idx;
5697 
5698 	if (nid == BASS_REDIRECTION_XOVER)
5699 		cur_val = &spec->bass_redirect_xover_freq;
5700 	else
5701 		cur_val = &spec->xbass_xover_freq;
5702 
5703 	/* any change? */
5704 	if (*cur_val == *valp)
5705 		return 0;
5706 
5707 	*cur_val = *valp;
5708 
5709 	idx = *valp;
5710 	if (nid == BASS_REDIRECTION_XOVER)
5711 		ca0132_alt_bass_redirection_xover_set(codec, *cur_val);
5712 	else
5713 		ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5714 
5715 	return 0;
5716 }
5717 
5718 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5719 				struct snd_ctl_elem_value *ucontrol)
5720 {
5721 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5722 	struct ca0132_spec *spec = codec->spec;
5723 	hda_nid_t nid = get_amp_nid(kcontrol);
5724 	long *valp = ucontrol->value.integer.value;
5725 	int idx;
5726 
5727 	idx = nid - EFFECT_START_NID;
5728 	/* any change? */
5729 	if (spec->fx_ctl_val[idx] == *valp)
5730 		return 0;
5731 
5732 	spec->fx_ctl_val[idx] = *valp;
5733 
5734 	idx = *valp;
5735 	ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5736 
5737 	return 0;
5738 }
5739 
5740 
5741 /*
5742  * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5743  * only has off or full 30 dB, and didn't like making a volume slider that has
5744  * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5745  */
5746 #define MIC_BOOST_NUM_OF_STEPS 4
5747 #define MIC_BOOST_ENUM_MAX_STRLEN 10
5748 
5749 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5750 				 struct snd_ctl_elem_info *uinfo)
5751 {
5752 	const char *sfx = "dB";
5753 	char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5754 
5755 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5756 	uinfo->count = 1;
5757 	uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5758 	if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5759 		uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5760 	sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5761 	strscpy(uinfo->value.enumerated.name, namestr);
5762 	return 0;
5763 }
5764 
5765 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5766 				struct snd_ctl_elem_value *ucontrol)
5767 {
5768 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5769 	struct ca0132_spec *spec = codec->spec;
5770 
5771 	ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5772 	return 0;
5773 }
5774 
5775 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5776 				struct snd_ctl_elem_value *ucontrol)
5777 {
5778 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5779 	struct ca0132_spec *spec = codec->spec;
5780 	int sel = ucontrol->value.enumerated.item[0];
5781 	unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5782 
5783 	if (sel >= items)
5784 		return 0;
5785 
5786 	codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5787 		    sel);
5788 
5789 	spec->mic_boost_enum_val = sel;
5790 
5791 	if (spec->in_enum_val != REAR_LINE_IN)
5792 		ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5793 
5794 	return 1;
5795 }
5796 
5797 /*
5798  * Sound BlasterX AE-5 Headphone Gain Controls.
5799  */
5800 #define AE5_HEADPHONE_GAIN_MAX 3
5801 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5802 				 struct snd_ctl_elem_info *uinfo)
5803 {
5804 	const char *sfx = " Ohms)";
5805 	char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5806 
5807 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5808 	uinfo->count = 1;
5809 	uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5810 	if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5811 		uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5812 	sprintf(namestr, "%s %s",
5813 		ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5814 		sfx);
5815 	strscpy(uinfo->value.enumerated.name, namestr);
5816 	return 0;
5817 }
5818 
5819 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5820 				struct snd_ctl_elem_value *ucontrol)
5821 {
5822 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5823 	struct ca0132_spec *spec = codec->spec;
5824 
5825 	ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5826 	return 0;
5827 }
5828 
5829 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5830 				struct snd_ctl_elem_value *ucontrol)
5831 {
5832 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5833 	struct ca0132_spec *spec = codec->spec;
5834 	int sel = ucontrol->value.enumerated.item[0];
5835 	unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5836 
5837 	if (sel >= items)
5838 		return 0;
5839 
5840 	codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5841 		    sel);
5842 
5843 	spec->ae5_headphone_gain_val = sel;
5844 
5845 	if (spec->out_enum_val == HEADPHONE_OUT)
5846 		ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5847 
5848 	return 1;
5849 }
5850 
5851 /*
5852  * Sound BlasterX AE-5 sound filter enumerated control.
5853  */
5854 #define AE5_SOUND_FILTER_MAX 3
5855 
5856 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5857 				 struct snd_ctl_elem_info *uinfo)
5858 {
5859 	char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5860 
5861 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5862 	uinfo->count = 1;
5863 	uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5864 	if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5865 		uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5866 	sprintf(namestr, "%s",
5867 			ae5_filter_presets[uinfo->value.enumerated.item].name);
5868 	strscpy(uinfo->value.enumerated.name, namestr);
5869 	return 0;
5870 }
5871 
5872 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5873 				struct snd_ctl_elem_value *ucontrol)
5874 {
5875 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5876 	struct ca0132_spec *spec = codec->spec;
5877 
5878 	ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5879 	return 0;
5880 }
5881 
5882 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5883 				struct snd_ctl_elem_value *ucontrol)
5884 {
5885 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5886 	struct ca0132_spec *spec = codec->spec;
5887 	int sel = ucontrol->value.enumerated.item[0];
5888 	unsigned int items = AE5_SOUND_FILTER_MAX;
5889 
5890 	if (sel >= items)
5891 		return 0;
5892 
5893 	codec_dbg(codec, "ae5_sound_filter: %s\n",
5894 			ae5_filter_presets[sel].name);
5895 
5896 	spec->ae5_filter_val = sel;
5897 
5898 	ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5899 			ae5_filter_presets[sel].val);
5900 
5901 	return 1;
5902 }
5903 
5904 /*
5905  * Input Select Control for alternative ca0132 codecs. This exists because
5906  * front microphone has no auto-detect, and we need a way to set the rear
5907  * as line-in
5908  */
5909 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5910 				 struct snd_ctl_elem_info *uinfo)
5911 {
5912 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5913 	uinfo->count = 1;
5914 	uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5915 	if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5916 		uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5917 	strscpy(uinfo->value.enumerated.name,
5918 			in_src_str[uinfo->value.enumerated.item]);
5919 	return 0;
5920 }
5921 
5922 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5923 				struct snd_ctl_elem_value *ucontrol)
5924 {
5925 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5926 	struct ca0132_spec *spec = codec->spec;
5927 
5928 	ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5929 	return 0;
5930 }
5931 
5932 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5933 				struct snd_ctl_elem_value *ucontrol)
5934 {
5935 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5936 	struct ca0132_spec *spec = codec->spec;
5937 	int sel = ucontrol->value.enumerated.item[0];
5938 	unsigned int items = IN_SRC_NUM_OF_INPUTS;
5939 
5940 	/*
5941 	 * The AE-7 has no front microphone, so limit items to 2: rear mic and
5942 	 * line-in.
5943 	 */
5944 	if (ca0132_quirk(spec) == QUIRK_AE7)
5945 		items = 2;
5946 
5947 	if (sel >= items)
5948 		return 0;
5949 
5950 	codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5951 		    sel, in_src_str[sel]);
5952 
5953 	spec->in_enum_val = sel;
5954 
5955 	ca0132_alt_select_in(codec);
5956 
5957 	return 1;
5958 }
5959 
5960 /* Sound Blaster Z Output Select Control */
5961 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5962 				 struct snd_ctl_elem_info *uinfo)
5963 {
5964 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5965 	uinfo->count = 1;
5966 	uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5967 	if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5968 		uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5969 	strscpy(uinfo->value.enumerated.name,
5970 			out_type_str[uinfo->value.enumerated.item]);
5971 	return 0;
5972 }
5973 
5974 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5975 				struct snd_ctl_elem_value *ucontrol)
5976 {
5977 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5978 	struct ca0132_spec *spec = codec->spec;
5979 
5980 	ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5981 	return 0;
5982 }
5983 
5984 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5985 				struct snd_ctl_elem_value *ucontrol)
5986 {
5987 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5988 	struct ca0132_spec *spec = codec->spec;
5989 	int sel = ucontrol->value.enumerated.item[0];
5990 	unsigned int items = NUM_OF_OUTPUTS;
5991 	unsigned int auto_jack;
5992 
5993 	if (sel >= items)
5994 		return 0;
5995 
5996 	codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5997 		    sel, out_type_str[sel]);
5998 
5999 	spec->out_enum_val = sel;
6000 
6001 	auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
6002 
6003 	if (!auto_jack)
6004 		ca0132_alt_select_out(codec);
6005 
6006 	return 1;
6007 }
6008 
6009 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */
6010 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol,
6011 				 struct snd_ctl_elem_info *uinfo)
6012 {
6013 	unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
6014 
6015 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6016 	uinfo->count = 1;
6017 	uinfo->value.enumerated.items = items;
6018 	if (uinfo->value.enumerated.item >= items)
6019 		uinfo->value.enumerated.item = items - 1;
6020 	strscpy(uinfo->value.enumerated.name,
6021 			speaker_channel_cfgs[uinfo->value.enumerated.item].name);
6022 	return 0;
6023 }
6024 
6025 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol,
6026 				struct snd_ctl_elem_value *ucontrol)
6027 {
6028 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6029 	struct ca0132_spec *spec = codec->spec;
6030 
6031 	ucontrol->value.enumerated.item[0] = spec->channel_cfg_val;
6032 	return 0;
6033 }
6034 
6035 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol,
6036 				struct snd_ctl_elem_value *ucontrol)
6037 {
6038 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6039 	struct ca0132_spec *spec = codec->spec;
6040 	int sel = ucontrol->value.enumerated.item[0];
6041 	unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
6042 
6043 	if (sel >= items)
6044 		return 0;
6045 
6046 	codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n",
6047 		    sel, speaker_channel_cfgs[sel].name);
6048 
6049 	spec->channel_cfg_val = sel;
6050 
6051 	if (spec->out_enum_val == SPEAKER_OUT)
6052 		ca0132_alt_select_out(codec);
6053 
6054 	return 1;
6055 }
6056 
6057 /*
6058  * Smart Volume output setting control. Three different settings, Normal,
6059  * which takes the value from the smart volume slider. The two others, loud
6060  * and night, disregard the slider value and have uneditable values.
6061  */
6062 #define NUM_OF_SVM_SETTINGS 3
6063 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
6064 
6065 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
6066 				 struct snd_ctl_elem_info *uinfo)
6067 {
6068 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6069 	uinfo->count = 1;
6070 	uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
6071 	if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
6072 		uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
6073 	strscpy(uinfo->value.enumerated.name,
6074 			out_svm_set_enum_str[uinfo->value.enumerated.item]);
6075 	return 0;
6076 }
6077 
6078 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
6079 				struct snd_ctl_elem_value *ucontrol)
6080 {
6081 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6082 	struct ca0132_spec *spec = codec->spec;
6083 
6084 	ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
6085 	return 0;
6086 }
6087 
6088 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
6089 				struct snd_ctl_elem_value *ucontrol)
6090 {
6091 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6092 	struct ca0132_spec *spec = codec->spec;
6093 	int sel = ucontrol->value.enumerated.item[0];
6094 	unsigned int items = NUM_OF_SVM_SETTINGS;
6095 	unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
6096 	unsigned int tmp;
6097 
6098 	if (sel >= items)
6099 		return 0;
6100 
6101 	codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
6102 		    sel, out_svm_set_enum_str[sel]);
6103 
6104 	spec->smart_volume_setting = sel;
6105 
6106 	switch (sel) {
6107 	case 0:
6108 		tmp = FLOAT_ZERO;
6109 		break;
6110 	case 1:
6111 		tmp = FLOAT_ONE;
6112 		break;
6113 	case 2:
6114 		tmp = FLOAT_TWO;
6115 		break;
6116 	default:
6117 		tmp = FLOAT_ZERO;
6118 		break;
6119 	}
6120 	/* Req 2 is the Smart Volume Setting req. */
6121 	dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6122 			ca0132_effects[idx].reqs[2], tmp);
6123 	return 1;
6124 }
6125 
6126 /* Sound Blaster Z EQ preset controls */
6127 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
6128 				 struct snd_ctl_elem_info *uinfo)
6129 {
6130 	unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6131 
6132 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6133 	uinfo->count = 1;
6134 	uinfo->value.enumerated.items = items;
6135 	if (uinfo->value.enumerated.item >= items)
6136 		uinfo->value.enumerated.item = items - 1;
6137 	strscpy(uinfo->value.enumerated.name,
6138 		ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
6139 	return 0;
6140 }
6141 
6142 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
6143 				struct snd_ctl_elem_value *ucontrol)
6144 {
6145 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6146 	struct ca0132_spec *spec = codec->spec;
6147 
6148 	ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
6149 	return 0;
6150 }
6151 
6152 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
6153 				struct snd_ctl_elem_value *ucontrol)
6154 {
6155 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6156 	struct ca0132_spec *spec = codec->spec;
6157 	int i, err = 0;
6158 	int sel = ucontrol->value.enumerated.item[0];
6159 	unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6160 
6161 	if (sel >= items)
6162 		return 0;
6163 
6164 	codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
6165 			ca0132_alt_eq_presets[sel].name);
6166 	/*
6167 	 * Idx 0 is default.
6168 	 * Default needs to qualify with CrystalVoice state.
6169 	 */
6170 	for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
6171 		err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
6172 				ca0132_alt_eq_enum.reqs[i],
6173 				ca0132_alt_eq_presets[sel].vals[i]);
6174 		if (err < 0)
6175 			break;
6176 	}
6177 
6178 	if (err >= 0)
6179 		spec->eq_preset_val = sel;
6180 
6181 	return 1;
6182 }
6183 
6184 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
6185 				 struct snd_ctl_elem_info *uinfo)
6186 {
6187 	unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
6188 
6189 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6190 	uinfo->count = 1;
6191 	uinfo->value.enumerated.items = items;
6192 	if (uinfo->value.enumerated.item >= items)
6193 		uinfo->value.enumerated.item = items - 1;
6194 	strscpy(uinfo->value.enumerated.name,
6195 	       ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
6196 	return 0;
6197 }
6198 
6199 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
6200 				struct snd_ctl_elem_value *ucontrol)
6201 {
6202 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6203 	struct ca0132_spec *spec = codec->spec;
6204 
6205 	ucontrol->value.enumerated.item[0] = spec->voicefx_val;
6206 	return 0;
6207 }
6208 
6209 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
6210 				struct snd_ctl_elem_value *ucontrol)
6211 {
6212 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6213 	struct ca0132_spec *spec = codec->spec;
6214 	int i, err = 0;
6215 	int sel = ucontrol->value.enumerated.item[0];
6216 
6217 	if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
6218 		return 0;
6219 
6220 	codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
6221 		    sel, ca0132_voicefx_presets[sel].name);
6222 
6223 	/*
6224 	 * Idx 0 is default.
6225 	 * Default needs to qualify with CrystalVoice state.
6226 	 */
6227 	for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
6228 		err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
6229 				ca0132_voicefx.reqs[i],
6230 				ca0132_voicefx_presets[sel].vals[i]);
6231 		if (err < 0)
6232 			break;
6233 	}
6234 
6235 	if (err >= 0) {
6236 		spec->voicefx_val = sel;
6237 		/* enable voice fx */
6238 		ca0132_voicefx_set(codec, (sel ? 1 : 0));
6239 	}
6240 
6241 	return 1;
6242 }
6243 
6244 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
6245 				struct snd_ctl_elem_value *ucontrol)
6246 {
6247 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6248 	struct ca0132_spec *spec = codec->spec;
6249 	hda_nid_t nid = get_amp_nid(kcontrol);
6250 	int ch = get_amp_channels(kcontrol);
6251 	long *valp = ucontrol->value.integer.value;
6252 
6253 	/* vnode */
6254 	if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6255 		if (ch & 1) {
6256 			*valp = spec->vnode_lswitch[nid - VNODE_START_NID];
6257 			valp++;
6258 		}
6259 		if (ch & 2) {
6260 			*valp = spec->vnode_rswitch[nid - VNODE_START_NID];
6261 			valp++;
6262 		}
6263 		return 0;
6264 	}
6265 
6266 	/* effects, include PE and CrystalVoice */
6267 	if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
6268 		*valp = spec->effects_switch[nid - EFFECT_START_NID];
6269 		return 0;
6270 	}
6271 
6272 	/* mic boost */
6273 	if (nid == spec->input_pins[0]) {
6274 		*valp = spec->cur_mic_boost;
6275 		return 0;
6276 	}
6277 
6278 	if (nid == ZXR_HEADPHONE_GAIN) {
6279 		*valp = spec->zxr_gain_set;
6280 		return 0;
6281 	}
6282 
6283 	if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6284 		*valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT];
6285 		return 0;
6286 	}
6287 
6288 	if (nid == BASS_REDIRECTION) {
6289 		*valp = spec->bass_redirection_val;
6290 		return 0;
6291 	}
6292 
6293 	return 0;
6294 }
6295 
6296 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
6297 			     struct snd_ctl_elem_value *ucontrol)
6298 {
6299 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6300 	struct ca0132_spec *spec = codec->spec;
6301 	hda_nid_t nid = get_amp_nid(kcontrol);
6302 	int ch = get_amp_channels(kcontrol);
6303 	long *valp = ucontrol->value.integer.value;
6304 
6305 	codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
6306 		    nid, *valp);
6307 
6308 	CLASS(snd_hda_power, pm)(codec);
6309 	/* vnode */
6310 	if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6311 		if (ch & 1) {
6312 			spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
6313 			valp++;
6314 		}
6315 		if (ch & 2) {
6316 			spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
6317 			valp++;
6318 		}
6319 		return ca0132_vnode_switch_set(kcontrol, ucontrol);
6320 	}
6321 
6322 	/* PE */
6323 	if (nid == PLAY_ENHANCEMENT) {
6324 		spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6325 		return ca0132_pe_switch_set(codec);
6326 	}
6327 
6328 	/* CrystalVoice */
6329 	if (nid == CRYSTAL_VOICE) {
6330 		spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6331 		return ca0132_cvoice_switch_set(codec);
6332 	}
6333 
6334 	/* out and in effects */
6335 	if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
6336 	    ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
6337 		spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6338 		return ca0132_effects_set(codec, nid, *valp);
6339 	}
6340 
6341 	/* mic boost */
6342 	if (nid == spec->input_pins[0]) {
6343 		spec->cur_mic_boost = *valp;
6344 		if (ca0132_use_alt_functions(spec)) {
6345 			if (spec->in_enum_val != REAR_LINE_IN)
6346 				return ca0132_mic_boost_set(codec, *valp);
6347 		} else {
6348 			/* Mic boost does not apply to Digital Mic */
6349 			if (spec->cur_mic_type != DIGITAL_MIC)
6350 				return ca0132_mic_boost_set(codec, *valp);
6351 		}
6352 
6353 		return 1;
6354 	}
6355 
6356 	if (nid == ZXR_HEADPHONE_GAIN) {
6357 		spec->zxr_gain_set = *valp;
6358 		if (spec->cur_out_type == HEADPHONE_OUT)
6359 			return zxr_headphone_gain_set(codec, *valp);
6360 		else
6361 			return 0;
6362 	}
6363 
6364 	if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6365 		spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp;
6366 		if (spec->cur_out_type == SPEAKER_OUT)
6367 			ca0132_alt_set_full_range_speaker(codec);
6368 
6369 		return 0;
6370 	}
6371 
6372 	if (nid == BASS_REDIRECTION) {
6373 		spec->bass_redirection_val = *valp;
6374 		if (spec->cur_out_type == SPEAKER_OUT)
6375 			ca0132_alt_surround_set_bass_redirection(codec, *valp);
6376 
6377 		return 0;
6378 	}
6379 
6380 	return 1;
6381 }
6382 
6383 /*
6384  * Volume related
6385  */
6386 /*
6387  * Sets the internal DSP decibel level to match the DAC for output, and the
6388  * ADC for input. Currently only the SBZ sets dsp capture volume level, and
6389  * all alternative codecs set DSP playback volume.
6390  */
6391 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
6392 {
6393 	struct ca0132_spec *spec = codec->spec;
6394 	unsigned int dsp_dir;
6395 	unsigned int lookup_val;
6396 
6397 	if (nid == VNID_SPK)
6398 		dsp_dir = DSP_VOL_OUT;
6399 	else
6400 		dsp_dir = DSP_VOL_IN;
6401 
6402 	lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
6403 
6404 	dspio_set_uint_param(codec,
6405 		ca0132_alt_vol_ctls[dsp_dir].mid,
6406 		ca0132_alt_vol_ctls[dsp_dir].reqs[0],
6407 		float_vol_db_lookup[lookup_val]);
6408 
6409 	lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
6410 
6411 	dspio_set_uint_param(codec,
6412 		ca0132_alt_vol_ctls[dsp_dir].mid,
6413 		ca0132_alt_vol_ctls[dsp_dir].reqs[1],
6414 		float_vol_db_lookup[lookup_val]);
6415 
6416 	dspio_set_uint_param(codec,
6417 		ca0132_alt_vol_ctls[dsp_dir].mid,
6418 		ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
6419 }
6420 
6421 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
6422 			      struct snd_ctl_elem_info *uinfo)
6423 {
6424 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6425 	struct ca0132_spec *spec = codec->spec;
6426 	hda_nid_t nid = get_amp_nid(kcontrol);
6427 	int ch = get_amp_channels(kcontrol);
6428 	int dir = get_amp_direction(kcontrol);
6429 	unsigned long pval;
6430 	int err;
6431 
6432 	switch (nid) {
6433 	case VNID_SPK:
6434 		/* follow shared_out info */
6435 		nid = spec->shared_out_nid;
6436 		scoped_guard(mutex, &codec->control_mutex) {
6437 			pval = kcontrol->private_value;
6438 			kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6439 			err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6440 			kcontrol->private_value = pval;
6441 		}
6442 		break;
6443 	case VNID_MIC:
6444 		/* follow shared_mic info */
6445 		nid = spec->shared_mic_nid;
6446 		scoped_guard(mutex, &codec->control_mutex) {
6447 			pval = kcontrol->private_value;
6448 			kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6449 			err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6450 			kcontrol->private_value = pval;
6451 		}
6452 		break;
6453 	default:
6454 		err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6455 	}
6456 	return err;
6457 }
6458 
6459 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
6460 				struct snd_ctl_elem_value *ucontrol)
6461 {
6462 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6463 	struct ca0132_spec *spec = codec->spec;
6464 	hda_nid_t nid = get_amp_nid(kcontrol);
6465 	int ch = get_amp_channels(kcontrol);
6466 	long *valp = ucontrol->value.integer.value;
6467 
6468 	/* store the left and right volume */
6469 	if (ch & 1) {
6470 		*valp = spec->vnode_lvol[nid - VNODE_START_NID];
6471 		valp++;
6472 	}
6473 	if (ch & 2) {
6474 		*valp = spec->vnode_rvol[nid - VNODE_START_NID];
6475 		valp++;
6476 	}
6477 	return 0;
6478 }
6479 
6480 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
6481 				struct snd_ctl_elem_value *ucontrol)
6482 {
6483 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6484 	struct ca0132_spec *spec = codec->spec;
6485 	hda_nid_t nid = get_amp_nid(kcontrol);
6486 	int ch = get_amp_channels(kcontrol);
6487 	long *valp = ucontrol->value.integer.value;
6488 	hda_nid_t shared_nid = 0;
6489 	bool effective;
6490 	int changed = 1;
6491 
6492 	/* store the left and right volume */
6493 	if (ch & 1) {
6494 		spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
6495 		valp++;
6496 	}
6497 	if (ch & 2) {
6498 		spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
6499 		valp++;
6500 	}
6501 
6502 	/* if effective conditions, then update hw immediately. */
6503 	effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
6504 	if (effective) {
6505 		int dir = get_amp_direction(kcontrol);
6506 		unsigned long pval;
6507 
6508 		CLASS(snd_hda_power, pm)(codec);
6509 		guard(mutex)(&codec->control_mutex);
6510 		pval = kcontrol->private_value;
6511 		kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
6512 								0, dir);
6513 		changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6514 		kcontrol->private_value = pval;
6515 	}
6516 
6517 	return changed;
6518 }
6519 
6520 /*
6521  * This function is the same as the one above, because using an if statement
6522  * inside of the above volume control for the DSP volume would cause too much
6523  * lag. This is a lot more smooth.
6524  */
6525 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
6526 				struct snd_ctl_elem_value *ucontrol)
6527 {
6528 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6529 	struct ca0132_spec *spec = codec->spec;
6530 	hda_nid_t nid = get_amp_nid(kcontrol);
6531 	int ch = get_amp_channels(kcontrol);
6532 	long *valp = ucontrol->value.integer.value;
6533 	hda_nid_t vnid = 0;
6534 
6535 	switch (nid) {
6536 	case 0x02:
6537 		vnid = VNID_SPK;
6538 		break;
6539 	case 0x07:
6540 		vnid = VNID_MIC;
6541 		break;
6542 	}
6543 
6544 	/* store the left and right volume */
6545 	if (ch & 1) {
6546 		spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
6547 		valp++;
6548 	}
6549 	if (ch & 2) {
6550 		spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6551 		valp++;
6552 	}
6553 
6554 	CLASS(snd_hda_power, pm)(codec);
6555 	ca0132_alt_dsp_volume_put(codec, vnid);
6556 	guard(mutex)(&codec->control_mutex);
6557 	return snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6558 }
6559 
6560 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
6561 			     unsigned int size, unsigned int __user *tlv)
6562 {
6563 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6564 	struct ca0132_spec *spec = codec->spec;
6565 	hda_nid_t nid = get_amp_nid(kcontrol);
6566 	int ch = get_amp_channels(kcontrol);
6567 	int dir = get_amp_direction(kcontrol);
6568 	unsigned long pval;
6569 	int err;
6570 
6571 	switch (nid) {
6572 	case VNID_SPK:
6573 		/* follow shared_out tlv */
6574 		nid = spec->shared_out_nid;
6575 		scoped_guard(mutex, &codec->control_mutex) {
6576 			pval = kcontrol->private_value;
6577 			kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6578 			err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6579 			kcontrol->private_value = pval;
6580 		}
6581 		break;
6582 	case VNID_MIC:
6583 		/* follow shared_mic tlv */
6584 		nid = spec->shared_mic_nid;
6585 		scoped_guard(mutex, &codec->control_mutex) {
6586 			pval = kcontrol->private_value;
6587 			kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6588 			err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6589 			kcontrol->private_value = pval;
6590 		}
6591 		break;
6592 	default:
6593 		err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6594 	}
6595 	return err;
6596 }
6597 
6598 /* Add volume slider control for effect level */
6599 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6600 					const char *pfx, int dir)
6601 {
6602 	char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6603 	int type = dir ? HDA_INPUT : HDA_OUTPUT;
6604 	struct snd_kcontrol_new knew =
6605 		HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6606 
6607 	sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
6608 
6609 	knew.tlv.c = NULL;
6610 
6611 	switch (nid) {
6612 	case XBASS_XOVER:
6613 		knew.info = ca0132_alt_xbass_xover_slider_info;
6614 		knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6615 		knew.put = ca0132_alt_xbass_xover_slider_put;
6616 		break;
6617 	default:
6618 		knew.info = ca0132_alt_effect_slider_info;
6619 		knew.get = ca0132_alt_slider_ctl_get;
6620 		knew.put = ca0132_alt_effect_slider_put;
6621 		knew.private_value =
6622 			HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6623 		break;
6624 	}
6625 
6626 	return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6627 }
6628 
6629 /*
6630  * Added FX: prefix for the alternative codecs, because otherwise the surround
6631  * effect would conflict with the Surround sound volume control. Also seems more
6632  * clear as to what the switches do. Left alone for others.
6633  */
6634 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6635 			 const char *pfx, int dir)
6636 {
6637 	struct ca0132_spec *spec = codec->spec;
6638 	char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6639 	int type = dir ? HDA_INPUT : HDA_OUTPUT;
6640 	struct snd_kcontrol_new knew =
6641 		CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
6642 	/* If using alt_controls, add FX: prefix. But, don't add FX:
6643 	 * prefix to OutFX or InFX enable controls.
6644 	 */
6645 	if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID))
6646 		sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
6647 	else
6648 		sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6649 
6650 	return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6651 }
6652 
6653 static int add_voicefx(struct hda_codec *codec)
6654 {
6655 	struct snd_kcontrol_new knew =
6656 		HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6657 				    VOICEFX, 1, 0, HDA_INPUT);
6658 	knew.info = ca0132_voicefx_info;
6659 	knew.get = ca0132_voicefx_get;
6660 	knew.put = ca0132_voicefx_put;
6661 	return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
6662 }
6663 
6664 /* Create the EQ Preset control */
6665 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6666 {
6667 	struct snd_kcontrol_new knew =
6668 		HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6669 				    EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6670 	knew.info = ca0132_alt_eq_preset_info;
6671 	knew.get = ca0132_alt_eq_preset_get;
6672 	knew.put = ca0132_alt_eq_preset_put;
6673 	return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6674 				snd_ctl_new1(&knew, codec));
6675 }
6676 
6677 /*
6678  * Add enumerated control for the three different settings of the smart volume
6679  * output effect. Normal just uses the slider value, and loud and night are
6680  * their own things that ignore that value.
6681  */
6682 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6683 {
6684 	struct snd_kcontrol_new knew =
6685 		HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6686 				    SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6687 	knew.info = ca0132_alt_svm_setting_info;
6688 	knew.get = ca0132_alt_svm_setting_get;
6689 	knew.put = ca0132_alt_svm_setting_put;
6690 	return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6691 				snd_ctl_new1(&knew, codec));
6692 
6693 }
6694 
6695 /*
6696  * Create an Output Select enumerated control for codecs with surround
6697  * out capabilities.
6698  */
6699 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6700 {
6701 	struct snd_kcontrol_new knew =
6702 		HDA_CODEC_MUTE_MONO("Output Select",
6703 				    OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6704 	knew.info = ca0132_alt_output_select_get_info;
6705 	knew.get = ca0132_alt_output_select_get;
6706 	knew.put = ca0132_alt_output_select_put;
6707 	return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6708 				snd_ctl_new1(&knew, codec));
6709 }
6710 
6711 /*
6712  * Add a control for selecting channel count on speaker output. Setting this
6713  * allows the DSP to do bass redirection and channel upmixing on surround
6714  * configurations.
6715  */
6716 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec)
6717 {
6718 	struct snd_kcontrol_new knew =
6719 		HDA_CODEC_MUTE_MONO("Surround Channel Config",
6720 				    SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT);
6721 	knew.info = ca0132_alt_speaker_channel_cfg_get_info;
6722 	knew.get = ca0132_alt_speaker_channel_cfg_get;
6723 	knew.put = ca0132_alt_speaker_channel_cfg_put;
6724 	return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM,
6725 				snd_ctl_new1(&knew, codec));
6726 }
6727 
6728 /*
6729  * Full range front stereo and rear surround switches. When these are set to
6730  * full range, the lower frequencies from these channels are no longer
6731  * redirected to the LFE channel.
6732  */
6733 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec)
6734 {
6735 	struct snd_kcontrol_new knew =
6736 		CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers",
6737 				    SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT);
6738 
6739 	return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT,
6740 				snd_ctl_new1(&knew, codec));
6741 }
6742 
6743 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec)
6744 {
6745 	struct snd_kcontrol_new knew =
6746 		CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers",
6747 				    SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT);
6748 
6749 	return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR,
6750 				snd_ctl_new1(&knew, codec));
6751 }
6752 
6753 /*
6754  * Bass redirection redirects audio below the crossover frequency to the LFE
6755  * channel on speakers that are set as not being full-range. On configurations
6756  * without an LFE channel, it does nothing. Bass redirection seems to be the
6757  * replacement for X-Bass on configurations with an LFE channel.
6758  */
6759 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec)
6760 {
6761 	const char *namestr = "Bass Redirection Crossover";
6762 	struct snd_kcontrol_new knew =
6763 		HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0,
6764 				HDA_OUTPUT);
6765 
6766 	knew.tlv.c = NULL;
6767 	knew.info = ca0132_alt_xbass_xover_slider_info;
6768 	knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6769 	knew.put = ca0132_alt_xbass_xover_slider_put;
6770 
6771 	return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER,
6772 			snd_ctl_new1(&knew, codec));
6773 }
6774 
6775 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec)
6776 {
6777 	const char *namestr = "Bass Redirection";
6778 	struct snd_kcontrol_new knew =
6779 		CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1,
6780 				HDA_OUTPUT);
6781 
6782 	return snd_hda_ctl_add(codec, BASS_REDIRECTION,
6783 			snd_ctl_new1(&knew, codec));
6784 }
6785 
6786 /*
6787  * Create an Input Source enumerated control for the alternate ca0132 codecs
6788  * because the front microphone has no auto-detect, and Line-in has to be set
6789  * somehow.
6790  */
6791 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6792 {
6793 	struct snd_kcontrol_new knew =
6794 		HDA_CODEC_MUTE_MONO("Input Source",
6795 				    INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6796 	knew.info = ca0132_alt_input_source_info;
6797 	knew.get = ca0132_alt_input_source_get;
6798 	knew.put = ca0132_alt_input_source_put;
6799 	return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6800 				snd_ctl_new1(&knew, codec));
6801 }
6802 
6803 /*
6804  * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6805  * more control than the original mic boost, which is either full 30dB or off.
6806  */
6807 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6808 {
6809 	struct snd_kcontrol_new knew =
6810 		HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6811 				    MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6812 	knew.info = ca0132_alt_mic_boost_info;
6813 	knew.get = ca0132_alt_mic_boost_get;
6814 	knew.put = ca0132_alt_mic_boost_put;
6815 	return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6816 				snd_ctl_new1(&knew, codec));
6817 
6818 }
6819 
6820 /*
6821  * Add headphone gain enumerated control for the AE-5. This switches between
6822  * three modes, low, medium, and high. When non-headphone outputs are selected,
6823  * it is automatically set to high. This is the same behavior as Windows.
6824  */
6825 static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6826 {
6827 	struct snd_kcontrol_new knew =
6828 		HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
6829 				    AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6830 	knew.info = ae5_headphone_gain_info;
6831 	knew.get = ae5_headphone_gain_get;
6832 	knew.put = ae5_headphone_gain_put;
6833 	return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6834 				snd_ctl_new1(&knew, codec));
6835 }
6836 
6837 /*
6838  * Add sound filter enumerated control for the AE-5. This adds three different
6839  * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6840  * read into it, it changes the DAC's interpolation filter.
6841  */
6842 static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6843 {
6844 	struct snd_kcontrol_new knew =
6845 		HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
6846 				    AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6847 	knew.info = ae5_sound_filter_info;
6848 	knew.get = ae5_sound_filter_get;
6849 	knew.put = ae5_sound_filter_put;
6850 	return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6851 				snd_ctl_new1(&knew, codec));
6852 }
6853 
6854 static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6855 {
6856 	struct snd_kcontrol_new knew =
6857 		CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6858 				    ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6859 
6860 	return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6861 				snd_ctl_new1(&knew, codec));
6862 }
6863 
6864 /*
6865  * Need to create follower controls for the alternate codecs that have surround
6866  * capabilities.
6867  */
6868 static const char * const ca0132_alt_follower_pfxs[] = {
6869 	"Front", "Surround", "Center", "LFE", NULL,
6870 };
6871 
6872 /*
6873  * Also need special channel map, because the default one is incorrect.
6874  * I think this has to do with the pin for rear surround being 0x11,
6875  * and the center/lfe being 0x10. Usually the pin order is the opposite.
6876  */
6877 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
6878 	{ .channels = 2,
6879 	  .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6880 	{ .channels = 4,
6881 	  .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6882 		   SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6883 	{ .channels = 6,
6884 	  .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6885 		   SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6886 		   SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6887 	{ }
6888 };
6889 
6890 /* Add the correct chmap for streams with 6 channels. */
6891 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6892 {
6893 	int err = 0;
6894 	struct hda_pcm *pcm;
6895 
6896 	list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6897 		struct hda_pcm_stream *hinfo =
6898 			&pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6899 		struct snd_pcm_chmap *chmap;
6900 		const struct snd_pcm_chmap_elem *elem;
6901 
6902 		elem = ca0132_alt_chmaps;
6903 		if (hinfo->channels_max == 6) {
6904 			err = snd_pcm_add_chmap_ctls(pcm->pcm,
6905 					SNDRV_PCM_STREAM_PLAYBACK,
6906 					elem, hinfo->channels_max, 0, &chmap);
6907 			if (err < 0)
6908 				codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6909 		}
6910 	}
6911 }
6912 
6913 /*
6914  * When changing Node IDs for Mixer Controls below, make sure to update
6915  * Node IDs in ca0132_config() as well.
6916  */
6917 static const struct snd_kcontrol_new ca0132_mixer[] = {
6918 	CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6919 	CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6920 	CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6921 	CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6922 	HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6923 	HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6924 	HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6925 	HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6926 	CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6927 			       0x12, 1, HDA_INPUT),
6928 	CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6929 			       VNID_HP_SEL, 1, HDA_OUTPUT),
6930 	CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6931 			       VNID_AMIC1_SEL, 1, HDA_INPUT),
6932 	CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6933 			       VNID_HP_ASEL, 1, HDA_OUTPUT),
6934 	CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6935 			       VNID_AMIC1_ASEL, 1, HDA_INPUT),
6936 	{ } /* end */
6937 };
6938 
6939 /*
6940  * Desktop specific control mixer. Removes auto-detect for mic, and adds
6941  * surround controls. Also sets both the Front Playback and Capture Volume
6942  * controls to alt so they set the DSP's decibel level.
6943  */
6944 static const struct snd_kcontrol_new desktop_mixer[] = {
6945 	CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6946 	CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6947 	HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6948 	HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6949 	HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6950 	HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6951 	HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6952 	HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6953 	CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6954 	CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6955 	HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6956 	HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6957 	CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6958 				VNID_HP_ASEL, 1, HDA_OUTPUT),
6959 	{ } /* end */
6960 };
6961 
6962 /*
6963  * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
6964  * because it doesn't set decibel levels for the DSP for capture.
6965  */
6966 static const struct snd_kcontrol_new r3di_mixer[] = {
6967 	CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6968 	CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6969 	HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6970 	HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6971 	HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6972 	HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6973 	HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6974 	HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6975 	CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6976 	CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6977 	HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6978 	HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6979 	CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6980 				VNID_HP_ASEL, 1, HDA_OUTPUT),
6981 	{ } /* end */
6982 };
6983 
6984 static int ca0132_build_controls(struct hda_codec *codec)
6985 {
6986 	struct ca0132_spec *spec = codec->spec;
6987 	int i, num_fx, num_sliders;
6988 	int err = 0;
6989 
6990 	/* Add Mixer controls */
6991 	for (i = 0; i < spec->num_mixers; i++) {
6992 		err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
6993 		if (err < 0)
6994 			return err;
6995 	}
6996 	/* Setup vmaster with surround followers for desktop ca0132 devices */
6997 	if (ca0132_use_alt_functions(spec)) {
6998 		snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
6999 					spec->tlv);
7000 		snd_hda_add_vmaster(codec, "Master Playback Volume",
7001 					spec->tlv, ca0132_alt_follower_pfxs,
7002 					"Playback Volume", 0);
7003 		err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
7004 					    NULL, ca0132_alt_follower_pfxs,
7005 					    "Playback Switch",
7006 					    true, 0, &spec->vmaster_mute.sw_kctl);
7007 		if (err < 0)
7008 			return err;
7009 	}
7010 
7011 	/* Add in and out effects controls.
7012 	 * VoiceFX, PE and CrystalVoice are added separately.
7013 	 */
7014 	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7015 	for (i = 0; i < num_fx; i++) {
7016 		/* Desktop cards break if Echo Cancellation is used. */
7017 		if (ca0132_use_pci_mmio(spec)) {
7018 			if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
7019 						OUT_EFFECTS_COUNT))
7020 				continue;
7021 		}
7022 
7023 		err = add_fx_switch(codec, ca0132_effects[i].nid,
7024 				    ca0132_effects[i].name,
7025 				    ca0132_effects[i].direct);
7026 		if (err < 0)
7027 			return err;
7028 	}
7029 	/*
7030 	 * If codec has use_alt_controls set to true, add effect level sliders,
7031 	 * EQ presets, and Smart Volume presets. Also, change names to add FX
7032 	 * prefix, and change PlayEnhancement and CrystalVoice to match.
7033 	 */
7034 	if (ca0132_use_alt_controls(spec)) {
7035 		err = ca0132_alt_add_svm_enum(codec);
7036 		if (err < 0)
7037 			return err;
7038 
7039 		err = add_ca0132_alt_eq_presets(codec);
7040 		if (err < 0)
7041 			return err;
7042 
7043 		err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7044 					"Enable OutFX", 0);
7045 		if (err < 0)
7046 			return err;
7047 
7048 		err = add_fx_switch(codec, CRYSTAL_VOICE,
7049 					"Enable InFX", 1);
7050 		if (err < 0)
7051 			return err;
7052 
7053 		num_sliders = OUT_EFFECTS_COUNT - 1;
7054 		for (i = 0; i < num_sliders; i++) {
7055 			err = ca0132_alt_add_effect_slider(codec,
7056 					    ca0132_effects[i].nid,
7057 					    ca0132_effects[i].name,
7058 					    ca0132_effects[i].direct);
7059 			if (err < 0)
7060 				return err;
7061 		}
7062 
7063 		err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
7064 					"X-Bass Crossover", EFX_DIR_OUT);
7065 
7066 		if (err < 0)
7067 			return err;
7068 	} else {
7069 		err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7070 					"PlayEnhancement", 0);
7071 		if (err < 0)
7072 			return err;
7073 
7074 		err = add_fx_switch(codec, CRYSTAL_VOICE,
7075 					"CrystalVoice", 1);
7076 		if (err < 0)
7077 			return err;
7078 	}
7079 	err = add_voicefx(codec);
7080 	if (err < 0)
7081 		return err;
7082 
7083 	/*
7084 	 * If the codec uses alt_functions, you need the enumerated controls
7085 	 * to select the new outputs and inputs, plus add the new mic boost
7086 	 * setting control.
7087 	 */
7088 	if (ca0132_use_alt_functions(spec)) {
7089 		err = ca0132_alt_add_output_enum(codec);
7090 		if (err < 0)
7091 			return err;
7092 		err = ca0132_alt_add_speaker_channel_cfg_enum(codec);
7093 		if (err < 0)
7094 			return err;
7095 		err = ca0132_alt_add_front_full_range_switch(codec);
7096 		if (err < 0)
7097 			return err;
7098 		err = ca0132_alt_add_rear_full_range_switch(codec);
7099 		if (err < 0)
7100 			return err;
7101 		err = ca0132_alt_add_bass_redirection_crossover(codec);
7102 		if (err < 0)
7103 			return err;
7104 		err = ca0132_alt_add_bass_redirection_switch(codec);
7105 		if (err < 0)
7106 			return err;
7107 		err = ca0132_alt_add_mic_boost_enum(codec);
7108 		if (err < 0)
7109 			return err;
7110 		/*
7111 		 * ZxR only has microphone input, there is no front panel
7112 		 * header on the card, and aux-in is handled by the DBPro board.
7113 		 */
7114 		if (ca0132_quirk(spec) != QUIRK_ZXR) {
7115 			err = ca0132_alt_add_input_enum(codec);
7116 			if (err < 0)
7117 				return err;
7118 		}
7119 	}
7120 
7121 	switch (ca0132_quirk(spec)) {
7122 	case QUIRK_AE5:
7123 	case QUIRK_AE7:
7124 		err = ae5_add_headphone_gain_enum(codec);
7125 		if (err < 0)
7126 			return err;
7127 		err = ae5_add_sound_filter_enum(codec);
7128 		if (err < 0)
7129 			return err;
7130 		break;
7131 	case QUIRK_ZXR:
7132 		err = zxr_add_headphone_gain_switch(codec);
7133 		if (err < 0)
7134 			return err;
7135 		break;
7136 	default:
7137 		break;
7138 	}
7139 
7140 #ifdef ENABLE_TUNING_CONTROLS
7141 	add_tuning_ctls(codec);
7142 #endif
7143 
7144 	err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
7145 	if (err < 0)
7146 		return err;
7147 
7148 	if (spec->dig_out) {
7149 		err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7150 						    spec->dig_out);
7151 		if (err < 0)
7152 			return err;
7153 		err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
7154 		if (err < 0)
7155 			return err;
7156 		/* spec->multiout.share_spdif = 1; */
7157 	}
7158 
7159 	if (spec->dig_in) {
7160 		err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7161 		if (err < 0)
7162 			return err;
7163 	}
7164 
7165 	if (ca0132_use_alt_functions(spec))
7166 		ca0132_alt_add_chmap_ctls(codec);
7167 
7168 	return 0;
7169 }
7170 
7171 static int dbpro_build_controls(struct hda_codec *codec)
7172 {
7173 	struct ca0132_spec *spec = codec->spec;
7174 	int err = 0;
7175 
7176 	if (spec->dig_out) {
7177 		err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7178 				spec->dig_out);
7179 		if (err < 0)
7180 			return err;
7181 	}
7182 
7183 	if (spec->dig_in) {
7184 		err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7185 		if (err < 0)
7186 			return err;
7187 	}
7188 
7189 	return 0;
7190 }
7191 
7192 /*
7193  * PCM
7194  */
7195 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
7196 	.substreams = 1,
7197 	.channels_min = 2,
7198 	.channels_max = 6,
7199 	.ops = {
7200 		.prepare = ca0132_playback_pcm_prepare,
7201 		.cleanup = ca0132_playback_pcm_cleanup,
7202 		.get_delay = ca0132_playback_pcm_delay,
7203 	},
7204 };
7205 
7206 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
7207 	.substreams = 1,
7208 	.channels_min = 2,
7209 	.channels_max = 2,
7210 	.ops = {
7211 		.prepare = ca0132_capture_pcm_prepare,
7212 		.cleanup = ca0132_capture_pcm_cleanup,
7213 		.get_delay = ca0132_capture_pcm_delay,
7214 	},
7215 };
7216 
7217 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
7218 	.substreams = 1,
7219 	.channels_min = 2,
7220 	.channels_max = 2,
7221 	.ops = {
7222 		.open = ca0132_dig_playback_pcm_open,
7223 		.close = ca0132_dig_playback_pcm_close,
7224 		.prepare = ca0132_dig_playback_pcm_prepare,
7225 		.cleanup = ca0132_dig_playback_pcm_cleanup
7226 	},
7227 };
7228 
7229 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
7230 	.substreams = 1,
7231 	.channels_min = 2,
7232 	.channels_max = 2,
7233 };
7234 
7235 static int ca0132_build_pcms(struct hda_codec *codec)
7236 {
7237 	struct ca0132_spec *spec = codec->spec;
7238 	struct hda_pcm *info;
7239 
7240 	info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
7241 	if (!info)
7242 		return -ENOMEM;
7243 	if (ca0132_use_alt_functions(spec)) {
7244 		info->own_chmap = true;
7245 		info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
7246 			= ca0132_alt_chmaps;
7247 	}
7248 	info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
7249 	info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
7250 	info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
7251 		spec->multiout.max_channels;
7252 	info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7253 	info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7254 	info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7255 
7256 	/* With the DSP enabled, desktops don't use this ADC. */
7257 	if (!ca0132_use_alt_functions(spec)) {
7258 		info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
7259 		if (!info)
7260 			return -ENOMEM;
7261 		info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7262 			ca0132_pcm_analog_capture;
7263 		info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7264 		info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
7265 	}
7266 
7267 	info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
7268 	if (!info)
7269 		return -ENOMEM;
7270 	info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7271 	info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7272 	info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
7273 
7274 	if (!spec->dig_out && !spec->dig_in)
7275 		return 0;
7276 
7277 	info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7278 	if (!info)
7279 		return -ENOMEM;
7280 	info->pcm_type = HDA_PCM_TYPE_SPDIF;
7281 	if (spec->dig_out) {
7282 		info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7283 			ca0132_pcm_digital_playback;
7284 		info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7285 	}
7286 	if (spec->dig_in) {
7287 		info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7288 			ca0132_pcm_digital_capture;
7289 		info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7290 	}
7291 
7292 	return 0;
7293 }
7294 
7295 static int dbpro_build_pcms(struct hda_codec *codec)
7296 {
7297 	struct ca0132_spec *spec = codec->spec;
7298 	struct hda_pcm *info;
7299 
7300 	info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
7301 	if (!info)
7302 		return -ENOMEM;
7303 	info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7304 	info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7305 	info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7306 
7307 
7308 	if (!spec->dig_out && !spec->dig_in)
7309 		return 0;
7310 
7311 	info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7312 	if (!info)
7313 		return -ENOMEM;
7314 	info->pcm_type = HDA_PCM_TYPE_SPDIF;
7315 	if (spec->dig_out) {
7316 		info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7317 			ca0132_pcm_digital_playback;
7318 		info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7319 	}
7320 	if (spec->dig_in) {
7321 		info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7322 			ca0132_pcm_digital_capture;
7323 		info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7324 	}
7325 
7326 	return 0;
7327 }
7328 
7329 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
7330 {
7331 	if (pin) {
7332 		snd_hda_set_pin_ctl(codec, pin, PIN_HP);
7333 		if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
7334 			snd_hda_codec_write(codec, pin, 0,
7335 					    AC_VERB_SET_AMP_GAIN_MUTE,
7336 					    AMP_OUT_UNMUTE);
7337 	}
7338 	if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
7339 		snd_hda_codec_write(codec, dac, 0,
7340 				    AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
7341 }
7342 
7343 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
7344 {
7345 	if (pin) {
7346 		snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
7347 		if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
7348 			snd_hda_codec_write(codec, pin, 0,
7349 					    AC_VERB_SET_AMP_GAIN_MUTE,
7350 					    AMP_IN_UNMUTE(0));
7351 	}
7352 	if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
7353 		snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
7354 				    AMP_IN_UNMUTE(0));
7355 
7356 		/* init to 0 dB and unmute. */
7357 		snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7358 					 HDA_AMP_VOLMASK, 0x5a);
7359 		snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7360 					 HDA_AMP_MUTE, 0);
7361 	}
7362 }
7363 
7364 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
7365 {
7366 	unsigned int caps;
7367 
7368 	caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
7369 				  AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
7370 	snd_hda_override_amp_caps(codec, nid, dir, caps);
7371 }
7372 
7373 /*
7374  * Switch between Digital built-in mic and analog mic.
7375  */
7376 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
7377 {
7378 	struct ca0132_spec *spec = codec->spec;
7379 	unsigned int tmp;
7380 	u8 val;
7381 	unsigned int oldval;
7382 
7383 	codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
7384 
7385 	oldval = stop_mic1(codec);
7386 	ca0132_set_vipsource(codec, 0);
7387 	if (enable) {
7388 		/* set DMic input as 2-ch */
7389 		tmp = FLOAT_TWO;
7390 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7391 
7392 		val = spec->dmic_ctl;
7393 		val |= 0x80;
7394 		snd_hda_codec_write(codec, spec->input_pins[0], 0,
7395 				    VENDOR_CHIPIO_DMIC_CTL_SET, val);
7396 
7397 		if (!(spec->dmic_ctl & 0x20))
7398 			chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
7399 	} else {
7400 		/* set AMic input as mono */
7401 		tmp = FLOAT_ONE;
7402 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7403 
7404 		val = spec->dmic_ctl;
7405 		/* clear bit7 and bit5 to disable dmic */
7406 		val &= 0x5f;
7407 		snd_hda_codec_write(codec, spec->input_pins[0], 0,
7408 				    VENDOR_CHIPIO_DMIC_CTL_SET, val);
7409 
7410 		if (!(spec->dmic_ctl & 0x20))
7411 			chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
7412 	}
7413 	ca0132_set_vipsource(codec, 1);
7414 	resume_mic1(codec, oldval);
7415 }
7416 
7417 /*
7418  * Initialization for Digital Mic.
7419  */
7420 static void ca0132_init_dmic(struct hda_codec *codec)
7421 {
7422 	struct ca0132_spec *spec = codec->spec;
7423 	u8 val;
7424 
7425 	/* Setup Digital Mic here, but don't enable.
7426 	 * Enable based on jack detect.
7427 	 */
7428 
7429 	/* MCLK uses MPIO1, set to enable.
7430 	 * Bit 2-0: MPIO select
7431 	 * Bit   3: set to disable
7432 	 * Bit 7-4: reserved
7433 	 */
7434 	val = 0x01;
7435 	snd_hda_codec_write(codec, spec->input_pins[0], 0,
7436 			    VENDOR_CHIPIO_DMIC_MCLK_SET, val);
7437 
7438 	/* Data1 uses MPIO3. Data2 not use
7439 	 * Bit 2-0: Data1 MPIO select
7440 	 * Bit   3: set disable Data1
7441 	 * Bit 6-4: Data2 MPIO select
7442 	 * Bit   7: set disable Data2
7443 	 */
7444 	val = 0x83;
7445 	snd_hda_codec_write(codec, spec->input_pins[0], 0,
7446 			    VENDOR_CHIPIO_DMIC_PIN_SET, val);
7447 
7448 	/* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
7449 	 * Bit 3-0: Channel mask
7450 	 * Bit   4: set for 48KHz, clear for 32KHz
7451 	 * Bit   5: mode
7452 	 * Bit   6: set to select Data2, clear for Data1
7453 	 * Bit   7: set to enable DMic, clear for AMic
7454 	 */
7455 	if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4)
7456 		val = 0x33;
7457 	else
7458 		val = 0x23;
7459 	/* keep a copy of dmic ctl val for enable/disable dmic purpuse */
7460 	spec->dmic_ctl = val;
7461 	snd_hda_codec_write(codec, spec->input_pins[0], 0,
7462 			    VENDOR_CHIPIO_DMIC_CTL_SET, val);
7463 }
7464 
7465 /*
7466  * Initialization for Analog Mic 2
7467  */
7468 static void ca0132_init_analog_mic2(struct hda_codec *codec)
7469 {
7470 	struct ca0132_spec *spec = codec->spec;
7471 
7472 	guard(mutex)(&spec->chipio_mutex);
7473 
7474 	chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00);
7475 	chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00);
7476 }
7477 
7478 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
7479 {
7480 	struct ca0132_spec *spec = codec->spec;
7481 	int i;
7482 
7483 	codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7484 	snd_hda_codec_update_widgets(codec);
7485 
7486 	for (i = 0; i < spec->multiout.num_dacs; i++)
7487 		refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
7488 
7489 	for (i = 0; i < spec->num_outputs; i++)
7490 		refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
7491 
7492 	for (i = 0; i < spec->num_inputs; i++) {
7493 		refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
7494 		refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
7495 	}
7496 }
7497 
7498 
7499 /* If there is an active channel for some reason, find it and free it. */
7500 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec)
7501 {
7502 	unsigned int i, tmp;
7503 	int status;
7504 
7505 	/* Read active DSPDMAC channel register. */
7506 	status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp);
7507 	if (status >= 0) {
7508 		/* AND against 0xfff to get the active channel bits. */
7509 		tmp = tmp & 0xfff;
7510 
7511 		/* If there are no active channels, nothing to free. */
7512 		if (!tmp)
7513 			return;
7514 	} else {
7515 		codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n",
7516 				__func__);
7517 		return;
7518 	}
7519 
7520 	/*
7521 	 * Check each DSP DMA channel for activity, and if the channel is
7522 	 * active, free it.
7523 	 */
7524 	for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) {
7525 		if (dsp_is_dma_active(codec, i)) {
7526 			status = dspio_free_dma_chan(codec, i);
7527 			if (status < 0)
7528 				codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n",
7529 						__func__, i);
7530 		}
7531 	}
7532 }
7533 
7534 /*
7535  * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in
7536  * use, audio is no longer routed directly to the DAC/ADC from the HDA stream.
7537  * Instead, audio is now routed through the DSP's DMA controllers, which
7538  * the DSP is tasked with setting up itself. Through debugging, it seems the
7539  * cause of most of the no-audio on startup issues were due to improperly
7540  * configured DSP DMA channels.
7541  *
7542  * Normally, the DSP configures these the first time an HDA audio stream is
7543  * started post DSP firmware download. That is why creating a 'dummy' stream
7544  * worked in fixing the audio in some cases. This works most of the time, but
7545  * sometimes if a stream is started/stopped before the DSP can setup the DMA
7546  * configuration registers, it ends up in a broken state. Issues can also
7547  * arise if streams are started in an unusual order, i.e the audio output dma
7548  * channel being sandwiched between the mic1 and mic2 dma channels.
7549  *
7550  * The solution to this is to make sure that the DSP has no DMA channels
7551  * in use post DSP firmware download, and then to manually start each default
7552  * DSP stream that uses the DMA channels. These are 0x0c, the audio output
7553  * stream, 0x03, analog mic 1, and 0x04, analog mic 2.
7554  */
7555 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec)
7556 {
7557 	static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 };
7558 	struct ca0132_spec *spec = codec->spec;
7559 	unsigned int i, tmp;
7560 
7561 	/*
7562 	 * Check if any of the default streams are active, and if they are,
7563 	 * stop them.
7564 	 */
7565 	scoped_guard(mutex, &spec->chipio_mutex) {
7566 		for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7567 			chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp);
7568 
7569 			if (tmp) {
7570 				chipio_set_stream_control(codec,
7571 							  dsp_dma_stream_ids[i], 0);
7572 			}
7573 		}
7574 	}
7575 
7576 	/*
7577 	 * If all DSP streams are inactive, there should be no active DSP DMA
7578 	 * channels. Check and make sure this is the case, and if it isn't,
7579 	 * free any active channels.
7580 	 */
7581 	ca0132_alt_free_active_dma_channels(codec);
7582 
7583 	guard(mutex)(&spec->chipio_mutex);
7584 
7585 	/* Make sure stream 0x0c is six channels. */
7586 	chipio_set_stream_channels(codec, 0x0c, 6);
7587 
7588 	for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7589 		chipio_set_stream_control(codec,
7590 				dsp_dma_stream_ids[i], 1);
7591 
7592 		/* Give the DSP some time to setup the DMA channel. */
7593 		msleep(75);
7594 	}
7595 }
7596 
7597 /*
7598  * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio
7599  * router', where each entry represents a 48khz audio channel, with a format
7600  * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number
7601  * value. The 2-bit number value is seemingly 0 if inactive, 1 if active,
7602  * and 3 if it's using Sample Rate Converter ports.
7603  * An example is:
7604  * 0x0001f8c0
7605  * In this case, f8 is the destination, and c0 is the source. The number value
7606  * is 1.
7607  * This region of memory is normally managed internally by the 8051, where
7608  * the region of exram memory from 0x1477-0x1575 has each byte represent an
7609  * entry within the 0x190000 range, and when a range of entries is in use, the
7610  * ending value is overwritten with 0xff.
7611  * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO
7612  * streamID's, where each entry is a starting 0x190000 port offset.
7613  * 0x159d in exram is the same as 0x1578, except it contains the ending port
7614  * offset for the corresponding streamID.
7615  *
7616  * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by
7617  * the 8051, then manually overwritten to remap the ports to work with the
7618  * new DACs.
7619  *
7620  * Currently known portID's:
7621  * 0x00-0x1f: HDA audio stream input/output ports.
7622  * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to
7623  *            have the lower-nibble set to 0x1, 0x2, and 0x9.
7624  * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned.
7625  * 0xe0-0xff: DAC/ADC audio input/output ports.
7626  *
7627  * Currently known streamID's:
7628  * 0x03: Mic1 ADC to DSP.
7629  * 0x04: Mic2 ADC to DSP.
7630  * 0x05: HDA node 0x02 audio stream to DSP.
7631  * 0x0f: DSP Mic exit to HDA node 0x07.
7632  * 0x0c: DSP processed audio to DACs.
7633  * 0x14: DAC0, front L/R.
7634  *
7635  * It is possible to route the HDA audio streams directly to the DAC and
7636  * bypass the DSP entirely, with the only downside being that since the DSP
7637  * does volume control, the only volume control you'll get is through PCM on
7638  * the PC side, in the same way volume is handled for optical out. This may be
7639  * useful for debugging.
7640  */
7641 static void chipio_remap_stream(struct hda_codec *codec,
7642 		const struct chipio_stream_remap_data *remap_data)
7643 {
7644 	unsigned int i, stream_offset;
7645 
7646 	/* Get the starting port for the stream to be remapped. */
7647 	chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7648 			&stream_offset);
7649 
7650 	/*
7651 	 * Check if the stream's port value is 0xff, because the 8051 may not
7652 	 * have gotten around to setting up the stream yet. Wait until it's
7653 	 * setup to remap it's ports.
7654 	 */
7655 	if (stream_offset == 0xff) {
7656 		for (i = 0; i < 5; i++) {
7657 			msleep(25);
7658 
7659 			chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7660 					&stream_offset);
7661 
7662 			if (stream_offset != 0xff)
7663 				break;
7664 		}
7665 	}
7666 
7667 	if (stream_offset == 0xff) {
7668 		codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n",
7669 				__func__, remap_data->stream_id);
7670 		return;
7671 	}
7672 
7673 	/* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */
7674 	stream_offset *= 0x04;
7675 	stream_offset += 0x190000;
7676 
7677 	for (i = 0; i < remap_data->count; i++) {
7678 		chipio_write_no_mutex(codec,
7679 				stream_offset + remap_data->offset[i],
7680 				remap_data->value[i]);
7681 	}
7682 
7683 	/* Update stream map configuration. */
7684 	chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7685 }
7686 
7687 /*
7688  * Default speaker tuning values setup for alternative codecs.
7689  */
7690 static const unsigned int sbz_default_delay_values[] = {
7691 	/* Non-zero values are floating point 0.000198. */
7692 	0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000
7693 };
7694 
7695 static const unsigned int zxr_default_delay_values[] = {
7696 	/* Non-zero values are floating point 0.000220. */
7697 	0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd
7698 };
7699 
7700 static const unsigned int ae5_default_delay_values[] = {
7701 	/* Non-zero values are floating point 0.000100. */
7702 	0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717
7703 };
7704 
7705 /*
7706  * If we never change these, probably only need them on initialization.
7707  */
7708 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec)
7709 {
7710 	struct ca0132_spec *spec = codec->spec;
7711 	unsigned int i, tmp, start_req, end_req;
7712 	const unsigned int *values;
7713 
7714 	switch (ca0132_quirk(spec)) {
7715 	case QUIRK_SBZ:
7716 		values = sbz_default_delay_values;
7717 		break;
7718 	case QUIRK_ZXR:
7719 		values = zxr_default_delay_values;
7720 		break;
7721 	case QUIRK_AE5:
7722 	case QUIRK_AE7:
7723 		values = ae5_default_delay_values;
7724 		break;
7725 	default:
7726 		values = sbz_default_delay_values;
7727 		break;
7728 	}
7729 
7730 	tmp = FLOAT_ZERO;
7731 	dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp);
7732 
7733 	start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL;
7734 	end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL;
7735 	for (i = start_req; i < end_req + 1; i++)
7736 		dspio_set_uint_param(codec, 0x96, i, tmp);
7737 
7738 	start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT;
7739 	end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT;
7740 	for (i = start_req; i < end_req + 1; i++)
7741 		dspio_set_uint_param(codec, 0x96, i, tmp);
7742 
7743 
7744 	for (i = 0; i < 6; i++)
7745 		dspio_set_uint_param(codec, 0x96,
7746 				SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]);
7747 }
7748 
7749 /*
7750  * Initialize mic for non-chromebook ca0132 implementations.
7751  */
7752 static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
7753 {
7754 	struct ca0132_spec *spec = codec->spec;
7755 	unsigned int tmp;
7756 
7757 	/* Mic 1 Setup */
7758 	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7759 	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7760 	if (ca0132_quirk(spec) == QUIRK_R3DI) {
7761 		chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7762 		tmp = FLOAT_ONE;
7763 	} else
7764 		tmp = FLOAT_THREE;
7765 	dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7766 
7767 	/* Mic 2 setup (not present on desktop cards) */
7768 	chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
7769 	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
7770 	if (ca0132_quirk(spec) == QUIRK_R3DI)
7771 		chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7772 	tmp = FLOAT_ZERO;
7773 	dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7774 }
7775 
7776 /*
7777  * Sets the source of stream 0x14 to connpointID 0x48, and the destination
7778  * connpointID to 0x91. If this isn't done, the destination is 0x71, and
7779  * you get no sound. I'm guessing this has to do with the Sound Blaster Z
7780  * having an updated DAC, which changes the destination to that DAC.
7781  */
7782 static void sbz_connect_streams(struct hda_codec *codec)
7783 {
7784 	struct ca0132_spec *spec = codec->spec;
7785 
7786 	guard(mutex)(&spec->chipio_mutex);
7787 
7788 	codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
7789 
7790 	/* This value is 0x43 for 96khz, and 0x83 for 192khz. */
7791 	chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
7792 
7793 	/* Setup stream 0x14 with it's source and destination points */
7794 	chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
7795 	chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
7796 	chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
7797 	chipio_set_stream_channels(codec, 0x14, 2);
7798 	chipio_set_stream_control(codec, 0x14, 1);
7799 
7800 	codec_dbg(codec, "Connect Streams exited, mutex released.\n");
7801 }
7802 
7803 /*
7804  * Write data through ChipIO to setup proper stream destinations.
7805  * Not sure how it exactly works, but it seems to direct data
7806  * to different destinations. Example is f8 to c0, e0 to c0.
7807  * All I know is, if you don't set these, you get no sound.
7808  */
7809 static void sbz_chipio_startup_data(struct hda_codec *codec)
7810 {
7811 	const struct chipio_stream_remap_data *dsp_out_remap_data;
7812 	struct ca0132_spec *spec = codec->spec;
7813 
7814 	guard(mutex)(&spec->chipio_mutex);
7815 	codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
7816 
7817 	/* Remap DAC0's output ports. */
7818 	chipio_remap_stream(codec, &stream_remap_data[0]);
7819 
7820 	/* Remap DSP audio output stream ports. */
7821 	switch (ca0132_quirk(spec)) {
7822 	case QUIRK_SBZ:
7823 		dsp_out_remap_data = &stream_remap_data[1];
7824 		break;
7825 
7826 	case QUIRK_ZXR:
7827 		dsp_out_remap_data = &stream_remap_data[2];
7828 		break;
7829 
7830 	default:
7831 		dsp_out_remap_data = NULL;
7832 		break;
7833 	}
7834 
7835 	if (dsp_out_remap_data)
7836 		chipio_remap_stream(codec, dsp_out_remap_data);
7837 
7838 	codec_dbg(codec, "Startup Data exited, mutex released.\n");
7839 }
7840 
7841 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
7842 {
7843 	struct ca0132_spec *spec = codec->spec;
7844 	unsigned int tmp;
7845 
7846 	chipio_set_stream_control(codec, 0x03, 0);
7847 	chipio_set_stream_control(codec, 0x04, 0);
7848 
7849 	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7850 	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7851 
7852 	tmp = FLOAT_THREE;
7853 	dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7854 
7855 	chipio_set_stream_control(codec, 0x03, 1);
7856 	chipio_set_stream_control(codec, 0x04, 1);
7857 
7858 	switch (ca0132_quirk(spec)) {
7859 	case QUIRK_SBZ:
7860 		chipio_write(codec, 0x18b098, 0x0000000c);
7861 		chipio_write(codec, 0x18b09C, 0x0000000c);
7862 		break;
7863 	case QUIRK_AE5:
7864 		chipio_write(codec, 0x18b098, 0x0000000c);
7865 		chipio_write(codec, 0x18b09c, 0x0000004c);
7866 		break;
7867 	default:
7868 		break;
7869 	}
7870 }
7871 
7872 static void ae5_post_dsp_register_set(struct hda_codec *codec)
7873 {
7874 	struct ca0132_spec *spec = codec->spec;
7875 
7876 	chipio_8051_write_direct(codec, 0x93, 0x10);
7877 	chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
7878 
7879 	writeb(0xff, spec->mem_base + 0x304);
7880 	writeb(0xff, spec->mem_base + 0x304);
7881 	writeb(0xff, spec->mem_base + 0x304);
7882 	writeb(0xff, spec->mem_base + 0x304);
7883 	writeb(0x00, spec->mem_base + 0x100);
7884 	writeb(0xff, spec->mem_base + 0x304);
7885 	writeb(0x00, spec->mem_base + 0x100);
7886 	writeb(0xff, spec->mem_base + 0x304);
7887 	writeb(0x00, spec->mem_base + 0x100);
7888 	writeb(0xff, spec->mem_base + 0x304);
7889 	writeb(0x00, spec->mem_base + 0x100);
7890 	writeb(0xff, spec->mem_base + 0x304);
7891 
7892 	ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7893 	ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7894 	ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7895 }
7896 
7897 static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7898 {
7899 	/*
7900 	 * Param3 in the 8051's memory is represented by the ascii string 'mch'
7901 	 * which seems to be 'multichannel'. This is also mentioned in the
7902 	 * AE-5's registry values in Windows.
7903 	 */
7904 	chipio_set_control_param(codec, 3, 0);
7905 	/*
7906 	 * I believe ASI is 'audio serial interface' and that it's used to
7907 	 * change colors on the external LED strip connected to the AE-5.
7908 	 */
7909 	chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7910 
7911 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7912 	chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7913 
7914 	chipio_8051_write_exram(codec, 0xfa92, 0x22);
7915 }
7916 
7917 static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7918 {
7919 	chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
7920 	chipio_8051_write_pll_pmu(codec, 0x45, 0xcc);
7921 	chipio_8051_write_pll_pmu(codec, 0x40, 0xcb);
7922 	chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
7923 	chipio_8051_write_pll_pmu(codec, 0x51, 0x8d);
7924 }
7925 
7926 static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7927 {
7928 	struct ca0132_spec *spec = codec->spec;
7929 
7930 	guard(mutex)(&spec->chipio_mutex);
7931 
7932 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7933 
7934 	chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7935 
7936 	chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7937 
7938 	chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7939 	chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7940 	chipio_set_stream_channels(codec, 0x18, 6);
7941 	chipio_set_stream_control(codec, 0x18, 1);
7942 
7943 	chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7944 
7945 	chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
7946 
7947 	ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7948 }
7949 
7950 static void ae5_post_dsp_startup_data(struct hda_codec *codec)
7951 {
7952 	struct ca0132_spec *spec = codec->spec;
7953 
7954 	guard(mutex)(&spec->chipio_mutex);
7955 
7956 	chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7957 	chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7958 	chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7959 	chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7960 
7961 	ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7962 	chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7963 	ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
7964 	ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
7965 	ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
7966 	ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7967 	ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7968 	ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7969 	ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7970 	ca0113_mmio_gpio_set(codec, 0, true);
7971 	ca0113_mmio_gpio_set(codec, 1, true);
7972 	ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
7973 
7974 	chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
7975 
7976 	ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7977 	ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7978 }
7979 
7980 static void ae7_post_dsp_setup_ports(struct hda_codec *codec)
7981 {
7982 	struct ca0132_spec *spec = codec->spec;
7983 
7984 	guard(mutex)(&spec->chipio_mutex);
7985 
7986 	/* Seems to share the same port remapping as the SBZ. */
7987 	chipio_remap_stream(codec, &stream_remap_data[1]);
7988 
7989 	ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
7990 	ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
7991 	ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00);
7992 	ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00);
7993 	ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff);
7994 	ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff);
7995 	ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff);
7996 	ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f);
7997 }
7998 
7999 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec)
8000 {
8001 	struct ca0132_spec *spec = codec->spec;
8002 
8003 	guard(mutex)(&spec->chipio_mutex);
8004 
8005 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
8006 	ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8007 
8008 	chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
8009 
8010 	chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8011 	chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8012 
8013 	chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8014 	chipio_set_stream_channels(codec, 0x18, 6);
8015 	chipio_set_stream_control(codec, 0x18, 1);
8016 
8017 	chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
8018 }
8019 
8020 static void ae7_post_dsp_pll_setup(struct hda_codec *codec)
8021 {
8022 	static const unsigned int addr[] = {
8023 		0x41, 0x45, 0x40, 0x43, 0x51
8024 	};
8025 	static const unsigned int data[] = {
8026 		0xc8, 0xcc, 0xcb, 0xc7, 0x8d
8027 	};
8028 	unsigned int i;
8029 
8030 	for (i = 0; i < ARRAY_SIZE(addr); i++)
8031 		chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]);
8032 }
8033 
8034 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec)
8035 {
8036 	struct ca0132_spec *spec = codec->spec;
8037 	static const unsigned int target[] = {
8038 		0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14
8039 	};
8040 	static const unsigned int data[] = {
8041 		0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f
8042 	};
8043 	unsigned int i;
8044 
8045 	guard(mutex)(&spec->chipio_mutex);
8046 
8047 	chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
8048 
8049 	chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8050 	chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8051 	chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8052 	chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8053 
8054 	ae7_post_dsp_pll_setup(codec);
8055 	chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8056 
8057 	for (i = 0; i < ARRAY_SIZE(target); i++)
8058 		ca0113_mmio_command_set(codec, 0x48, target[i], data[i]);
8059 
8060 	ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8061 	ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8062 	ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8063 
8064 	chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56);
8065 	chipio_set_stream_channels(codec, 0x21, 2);
8066 	chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000);
8067 
8068 	chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09);
8069 	/*
8070 	 * In the 8051's memory, this param is referred to as 'n2sid', which I
8071 	 * believe is 'node to streamID'. It seems to be a way to assign a
8072 	 * stream to a given HDA node.
8073 	 */
8074 	chipio_set_control_param_no_mutex(codec, 0x20, 0x21);
8075 
8076 	chipio_write_no_mutex(codec, 0x18b038, 0x00000088);
8077 
8078 	/*
8079 	 * Now, at this point on Windows, an actual stream is setup and
8080 	 * seemingly sends data to the HDA node 0x09, which is the digital
8081 	 * audio input node. This is left out here, because obviously I don't
8082 	 * know what data is being sent. Interestingly, the AE-5 seems to go
8083 	 * through the motions of getting here and never actually takes this
8084 	 * step, but the AE-7 does.
8085 	 */
8086 
8087 	ca0113_mmio_gpio_set(codec, 0, 1);
8088 	ca0113_mmio_gpio_set(codec, 1, 1);
8089 
8090 	ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8091 	chipio_write_no_mutex(codec, 0x18b03c, 0x00000000);
8092 	ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8093 	ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8094 
8095 	chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8096 	chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8097 
8098 	chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8099 	chipio_set_stream_channels(codec, 0x18, 6);
8100 
8101 	/*
8102 	 * Runs again, this has been repeated a few times, but I'm just
8103 	 * following what the Windows driver does.
8104 	 */
8105 	ae7_post_dsp_pll_setup(codec);
8106 	chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8107 }
8108 
8109 /*
8110  * The Windows driver has commands that seem to setup ASI, which I believe to
8111  * be some sort of audio serial interface. My current speculation is that it's
8112  * related to communicating with the new DAC.
8113  */
8114 static void ae7_post_dsp_asi_setup(struct hda_codec *codec)
8115 {
8116 	chipio_8051_write_direct(codec, 0x93, 0x10);
8117 
8118 	chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
8119 
8120 	ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8121 	ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8122 
8123 	chipio_set_control_param(codec, 3, 3);
8124 	chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
8125 
8126 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
8127 	chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8128 	snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);
8129 
8130 	chipio_8051_write_exram(codec, 0xfa92, 0x22);
8131 
8132 	ae7_post_dsp_pll_setup(codec);
8133 	ae7_post_dsp_asi_stream_setup(codec);
8134 
8135 	chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
8136 
8137 	ae7_post_dsp_asi_setup_ports(codec);
8138 }
8139 
8140 /*
8141  * Setup default parameters for DSP
8142  */
8143 static void ca0132_setup_defaults(struct hda_codec *codec)
8144 {
8145 	struct ca0132_spec *spec = codec->spec;
8146 	unsigned int tmp;
8147 	int num_fx;
8148 	int idx, i;
8149 
8150 	if (spec->dsp_state != DSP_DOWNLOADED)
8151 		return;
8152 
8153 	/* out, in effects + voicefx */
8154 	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8155 	for (idx = 0; idx < num_fx; idx++) {
8156 		for (i = 0; i <= ca0132_effects[idx].params; i++) {
8157 			dspio_set_uint_param(codec, ca0132_effects[idx].mid,
8158 					     ca0132_effects[idx].reqs[i],
8159 					     ca0132_effects[idx].def_vals[i]);
8160 		}
8161 	}
8162 
8163 	/*remove DSP headroom*/
8164 	tmp = FLOAT_ZERO;
8165 	dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8166 
8167 	/*set speaker EQ bypass attenuation*/
8168 	dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
8169 
8170 	/* set AMic1 and AMic2 as mono mic */
8171 	tmp = FLOAT_ONE;
8172 	dspio_set_uint_param(codec, 0x80, 0x00, tmp);
8173 	dspio_set_uint_param(codec, 0x80, 0x01, tmp);
8174 
8175 	/* set AMic1 as CrystalVoice input */
8176 	tmp = FLOAT_ONE;
8177 	dspio_set_uint_param(codec, 0x80, 0x05, tmp);
8178 
8179 	/* set WUH source */
8180 	tmp = FLOAT_TWO;
8181 	dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8182 }
8183 
8184 /*
8185  * Setup default parameters for Recon3D/Recon3Di DSP.
8186  */
8187 
8188 static void r3d_setup_defaults(struct hda_codec *codec)
8189 {
8190 	struct ca0132_spec *spec = codec->spec;
8191 	unsigned int tmp;
8192 	int num_fx;
8193 	int idx, i;
8194 
8195 	if (spec->dsp_state != DSP_DOWNLOADED)
8196 		return;
8197 
8198 	ca0132_alt_init_analog_mics(codec);
8199 	ca0132_alt_start_dsp_audio_streams(codec);
8200 
8201 	/*remove DSP headroom*/
8202 	tmp = FLOAT_ZERO;
8203 	dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8204 
8205 	/* set WUH source */
8206 	tmp = FLOAT_TWO;
8207 	dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8208 	chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8209 
8210 	/* Set speaker source? */
8211 	dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8212 
8213 	if (ca0132_quirk(spec) == QUIRK_R3DI)
8214 		r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
8215 
8216 	/* Disable mute on Center/LFE. */
8217 	if (ca0132_quirk(spec) == QUIRK_R3D) {
8218 		ca0113_mmio_gpio_set(codec, 2, false);
8219 		ca0113_mmio_gpio_set(codec, 4, true);
8220 	}
8221 
8222 	/* Setup effect defaults */
8223 	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8224 	for (idx = 0; idx < num_fx; idx++) {
8225 		for (i = 0; i <= ca0132_effects[idx].params; i++) {
8226 			dspio_set_uint_param(codec,
8227 					ca0132_effects[idx].mid,
8228 					ca0132_effects[idx].reqs[i],
8229 					ca0132_effects[idx].def_vals[i]);
8230 		}
8231 	}
8232 }
8233 
8234 /*
8235  * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
8236  * than the Chromebook setup.
8237  */
8238 static void sbz_setup_defaults(struct hda_codec *codec)
8239 {
8240 	struct ca0132_spec *spec = codec->spec;
8241 	unsigned int tmp;
8242 	int num_fx;
8243 	int idx, i;
8244 
8245 	if (spec->dsp_state != DSP_DOWNLOADED)
8246 		return;
8247 
8248 	ca0132_alt_init_analog_mics(codec);
8249 	ca0132_alt_start_dsp_audio_streams(codec);
8250 	sbz_connect_streams(codec);
8251 	sbz_chipio_startup_data(codec);
8252 
8253 	/*
8254 	 * Sets internal input loopback to off, used to have a switch to
8255 	 * enable input loopback, but turned out to be way too buggy.
8256 	 */
8257 	tmp = FLOAT_ONE;
8258 	dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8259 	dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8260 
8261 	/*remove DSP headroom*/
8262 	tmp = FLOAT_ZERO;
8263 	dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8264 
8265 	/* set WUH source */
8266 	tmp = FLOAT_TWO;
8267 	dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8268 	chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8269 
8270 	/* Set speaker source? */
8271 	dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8272 
8273 	ca0132_alt_dsp_initial_mic_setup(codec);
8274 
8275 	/* out, in effects + voicefx */
8276 	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8277 	for (idx = 0; idx < num_fx; idx++) {
8278 		for (i = 0; i <= ca0132_effects[idx].params; i++) {
8279 			dspio_set_uint_param(codec,
8280 					ca0132_effects[idx].mid,
8281 					ca0132_effects[idx].reqs[i],
8282 					ca0132_effects[idx].def_vals[i]);
8283 		}
8284 	}
8285 
8286 	ca0132_alt_init_speaker_tuning(codec);
8287 }
8288 
8289 /*
8290  * Setup default parameters for the Sound BlasterX AE-5 DSP.
8291  */
8292 static void ae5_setup_defaults(struct hda_codec *codec)
8293 {
8294 	struct ca0132_spec *spec = codec->spec;
8295 	unsigned int tmp;
8296 	int num_fx;
8297 	int idx, i;
8298 
8299 	if (spec->dsp_state != DSP_DOWNLOADED)
8300 		return;
8301 
8302 	ca0132_alt_init_analog_mics(codec);
8303 	ca0132_alt_start_dsp_audio_streams(codec);
8304 
8305 	/* New, unknown SCP req's */
8306 	tmp = FLOAT_ZERO;
8307 	dspio_set_uint_param(codec, 0x96, 0x29, tmp);
8308 	dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
8309 	dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8310 	dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8311 
8312 	ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8313 	ca0113_mmio_gpio_set(codec, 0, false);
8314 	ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8315 
8316 	/* Internal loopback off */
8317 	tmp = FLOAT_ONE;
8318 	dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8319 	dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8320 
8321 	/*remove DSP headroom*/
8322 	tmp = FLOAT_ZERO;
8323 	dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8324 
8325 	/* set WUH source */
8326 	tmp = FLOAT_TWO;
8327 	dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8328 	chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8329 
8330 	/* Set speaker source? */
8331 	dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8332 
8333 	ca0132_alt_dsp_initial_mic_setup(codec);
8334 	ae5_post_dsp_register_set(codec);
8335 	ae5_post_dsp_param_setup(codec);
8336 	ae5_post_dsp_pll_setup(codec);
8337 	ae5_post_dsp_stream_setup(codec);
8338 	ae5_post_dsp_startup_data(codec);
8339 
8340 	/* out, in effects + voicefx */
8341 	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8342 	for (idx = 0; idx < num_fx; idx++) {
8343 		for (i = 0; i <= ca0132_effects[idx].params; i++) {
8344 			dspio_set_uint_param(codec,
8345 					ca0132_effects[idx].mid,
8346 					ca0132_effects[idx].reqs[i],
8347 					ca0132_effects[idx].def_vals[i]);
8348 		}
8349 	}
8350 
8351 	ca0132_alt_init_speaker_tuning(codec);
8352 }
8353 
8354 /*
8355  * Setup default parameters for the Sound Blaster AE-7 DSP.
8356  */
8357 static void ae7_setup_defaults(struct hda_codec *codec)
8358 {
8359 	struct ca0132_spec *spec = codec->spec;
8360 	unsigned int tmp;
8361 	int num_fx;
8362 	int idx, i;
8363 
8364 	if (spec->dsp_state != DSP_DOWNLOADED)
8365 		return;
8366 
8367 	ca0132_alt_init_analog_mics(codec);
8368 	ca0132_alt_start_dsp_audio_streams(codec);
8369 	ae7_post_dsp_setup_ports(codec);
8370 
8371 	tmp = FLOAT_ZERO;
8372 	dspio_set_uint_param(codec, 0x96,
8373 			SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp);
8374 	dspio_set_uint_param(codec, 0x96,
8375 			SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp);
8376 
8377 	ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8378 
8379 	/* New, unknown SCP req's */
8380 	dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8381 	dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8382 
8383 	ca0113_mmio_gpio_set(codec, 0, false);
8384 
8385 	/* Internal loopback off */
8386 	tmp = FLOAT_ONE;
8387 	dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8388 	dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8389 
8390 	/*remove DSP headroom*/
8391 	tmp = FLOAT_ZERO;
8392 	dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8393 
8394 	/* set WUH source */
8395 	tmp = FLOAT_TWO;
8396 	dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8397 	chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8398 
8399 	/* Set speaker source? */
8400 	dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8401 	ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8402 
8403 	/*
8404 	 * This is the second time we've called this, but this is seemingly
8405 	 * what Windows does.
8406 	 */
8407 	ca0132_alt_init_analog_mics(codec);
8408 
8409 	ae7_post_dsp_asi_setup(codec);
8410 
8411 	/*
8412 	 * Not sure why, but these are both set to 1. They're only set to 0
8413 	 * upon shutdown.
8414 	 */
8415 	ca0113_mmio_gpio_set(codec, 0, true);
8416 	ca0113_mmio_gpio_set(codec, 1, true);
8417 
8418 	/* Volume control related. */
8419 	ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04);
8420 	ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04);
8421 	ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80);
8422 
8423 	/* out, in effects + voicefx */
8424 	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8425 	for (idx = 0; idx < num_fx; idx++) {
8426 		for (i = 0; i <= ca0132_effects[idx].params; i++) {
8427 			dspio_set_uint_param(codec,
8428 					ca0132_effects[idx].mid,
8429 					ca0132_effects[idx].reqs[i],
8430 					ca0132_effects[idx].def_vals[i]);
8431 		}
8432 	}
8433 
8434 	ca0132_alt_init_speaker_tuning(codec);
8435 }
8436 
8437 /*
8438  * Initialization of flags in chip
8439  */
8440 static void ca0132_init_flags(struct hda_codec *codec)
8441 {
8442 	struct ca0132_spec *spec = codec->spec;
8443 
8444 	if (ca0132_use_alt_functions(spec)) {
8445 		chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
8446 		chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
8447 		chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
8448 		chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
8449 		chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
8450 		chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8451 		chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
8452 		chipio_set_control_flag(codec,
8453 				CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8454 		chipio_set_control_flag(codec,
8455 				CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
8456 	} else {
8457 		chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8458 		chipio_set_control_flag(codec,
8459 				CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
8460 		chipio_set_control_flag(codec,
8461 				CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
8462 		chipio_set_control_flag(codec,
8463 				CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
8464 		chipio_set_control_flag(codec,
8465 				CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8466 		chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
8467 	}
8468 }
8469 
8470 /*
8471  * Initialization of parameters in chip
8472  */
8473 static void ca0132_init_params(struct hda_codec *codec)
8474 {
8475 	struct ca0132_spec *spec = codec->spec;
8476 
8477 	if (ca0132_use_alt_functions(spec)) {
8478 		chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8479 		chipio_set_conn_rate(codec, 0x0B, SR_48_000);
8480 		chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
8481 		chipio_set_control_param(codec, 0, 0);
8482 		chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
8483 	}
8484 
8485 	chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
8486 	chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
8487 }
8488 
8489 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
8490 {
8491 	chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
8492 	chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
8493 	chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
8494 	chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
8495 	chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
8496 	chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
8497 
8498 	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
8499 	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
8500 	chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8501 }
8502 
8503 static bool ca0132_download_dsp_images(struct hda_codec *codec)
8504 {
8505 	bool dsp_loaded = false;
8506 	struct ca0132_spec *spec = codec->spec;
8507 	const struct dsp_image_seg *dsp_os_image;
8508 	const struct firmware *fw_entry = NULL;
8509 	/*
8510 	 * Alternate firmwares for different variants. The Recon3Di apparently
8511 	 * can use the default firmware, but I'll leave the option in case
8512 	 * it needs it again.
8513 	 */
8514 	switch (ca0132_quirk(spec)) {
8515 	case QUIRK_SBZ:
8516 	case QUIRK_R3D:
8517 	case QUIRK_AE5:
8518 		if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
8519 					codec->card->dev) != 0)
8520 			codec_dbg(codec, "Desktop firmware not found.");
8521 		else
8522 			codec_dbg(codec, "Desktop firmware selected.");
8523 		break;
8524 	case QUIRK_R3DI:
8525 		if (request_firmware(&fw_entry, R3DI_EFX_FILE,
8526 					codec->card->dev) != 0)
8527 			codec_dbg(codec, "Recon3Di alt firmware not detected.");
8528 		else
8529 			codec_dbg(codec, "Recon3Di firmware selected.");
8530 		break;
8531 	default:
8532 		break;
8533 	}
8534 	/*
8535 	 * Use default ctefx.bin if no alt firmware is detected, or if none
8536 	 * exists for your particular codec.
8537 	 */
8538 	if (!fw_entry) {
8539 		codec_dbg(codec, "Default firmware selected.");
8540 		if (request_firmware(&fw_entry, EFX_FILE,
8541 					codec->card->dev) != 0)
8542 			return false;
8543 	}
8544 
8545 	dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
8546 	if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
8547 		codec_err(codec, "ca0132 DSP load image failed\n");
8548 		goto exit_download;
8549 	}
8550 
8551 	dsp_loaded = dspload_wait_loaded(codec);
8552 
8553 exit_download:
8554 	release_firmware(fw_entry);
8555 
8556 	return dsp_loaded;
8557 }
8558 
8559 static void ca0132_download_dsp(struct hda_codec *codec)
8560 {
8561 	struct ca0132_spec *spec = codec->spec;
8562 
8563 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
8564 	return; /* NOP */
8565 #endif
8566 
8567 	if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
8568 		return; /* don't retry failures */
8569 
8570 	chipio_enable_clocks(codec);
8571 	if (spec->dsp_state != DSP_DOWNLOADED) {
8572 		spec->dsp_state = DSP_DOWNLOADING;
8573 
8574 		if (!ca0132_download_dsp_images(codec))
8575 			spec->dsp_state = DSP_DOWNLOAD_FAILED;
8576 		else
8577 			spec->dsp_state = DSP_DOWNLOADED;
8578 	}
8579 
8580 	/* For codecs using alt functions, this is already done earlier */
8581 	if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
8582 		ca0132_set_dsp_msr(codec, true);
8583 }
8584 
8585 static void ca0132_process_dsp_response(struct hda_codec *codec,
8586 					struct hda_jack_callback *callback)
8587 {
8588 	struct ca0132_spec *spec = codec->spec;
8589 
8590 	codec_dbg(codec, "ca0132_process_dsp_response\n");
8591 	CLASS(snd_hda_power_pm, pm)(codec);
8592 	if (spec->wait_scp) {
8593 		if (dspio_get_response_data(codec) >= 0)
8594 			spec->wait_scp = 0;
8595 	}
8596 
8597 	dspio_clear_response_queue(codec);
8598 }
8599 
8600 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8601 {
8602 	struct ca0132_spec *spec = codec->spec;
8603 	struct hda_jack_tbl *tbl;
8604 
8605 	/* Delay enabling the HP amp, to let the mic-detection
8606 	 * state machine run.
8607 	 */
8608 	tbl = snd_hda_jack_tbl_get(codec, cb->nid);
8609 	if (tbl)
8610 		tbl->block_report = 1;
8611 	schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
8612 }
8613 
8614 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8615 {
8616 	struct ca0132_spec *spec = codec->spec;
8617 
8618 	if (ca0132_use_alt_functions(spec))
8619 		ca0132_alt_select_in(codec);
8620 	else
8621 		ca0132_select_mic(codec);
8622 }
8623 
8624 static void ca0132_setup_unsol(struct hda_codec *codec)
8625 {
8626 	struct ca0132_spec *spec = codec->spec;
8627 	snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
8628 	snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
8629 					    amic_callback);
8630 	snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
8631 					    ca0132_process_dsp_response);
8632 	/* Front headphone jack detection */
8633 	if (ca0132_use_alt_functions(spec))
8634 		snd_hda_jack_detect_enable_callback(codec,
8635 			spec->unsol_tag_front_hp, hp_callback);
8636 }
8637 
8638 /*
8639  * Verbs tables.
8640  */
8641 
8642 /* Sends before DSP download. */
8643 static const struct hda_verb ca0132_base_init_verbs[] = {
8644 	/*enable ct extension*/
8645 	{0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
8646 	{}
8647 };
8648 
8649 /* Send at exit. */
8650 static const struct hda_verb ca0132_base_exit_verbs[] = {
8651 	/*set afg to D3*/
8652 	{0x01, AC_VERB_SET_POWER_STATE, 0x03},
8653 	/*disable ct extension*/
8654 	{0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
8655 	{}
8656 };
8657 
8658 /* Other verbs tables. Sends after DSP download. */
8659 
8660 static const struct hda_verb ca0132_init_verbs0[] = {
8661 	/* chip init verbs */
8662 	{0x15, 0x70D, 0xF0},
8663 	{0x15, 0x70E, 0xFE},
8664 	{0x15, 0x707, 0x75},
8665 	{0x15, 0x707, 0xD3},
8666 	{0x15, 0x707, 0x09},
8667 	{0x15, 0x707, 0x53},
8668 	{0x15, 0x707, 0xD4},
8669 	{0x15, 0x707, 0xEF},
8670 	{0x15, 0x707, 0x75},
8671 	{0x15, 0x707, 0xD3},
8672 	{0x15, 0x707, 0x09},
8673 	{0x15, 0x707, 0x02},
8674 	{0x15, 0x707, 0x37},
8675 	{0x15, 0x707, 0x78},
8676 	{0x15, 0x53C, 0xCE},
8677 	{0x15, 0x575, 0xC9},
8678 	{0x15, 0x53D, 0xCE},
8679 	{0x15, 0x5B7, 0xC9},
8680 	{0x15, 0x70D, 0xE8},
8681 	{0x15, 0x70E, 0xFE},
8682 	{0x15, 0x707, 0x02},
8683 	{0x15, 0x707, 0x68},
8684 	{0x15, 0x707, 0x62},
8685 	{0x15, 0x53A, 0xCE},
8686 	{0x15, 0x546, 0xC9},
8687 	{0x15, 0x53B, 0xCE},
8688 	{0x15, 0x5E8, 0xC9},
8689 	{}
8690 };
8691 
8692 /* Extra init verbs for desktop cards. */
8693 static const struct hda_verb ca0132_init_verbs1[] = {
8694 	{0x15, 0x70D, 0x20},
8695 	{0x15, 0x70E, 0x19},
8696 	{0x15, 0x707, 0x00},
8697 	{0x15, 0x539, 0xCE},
8698 	{0x15, 0x546, 0xC9},
8699 	{0x15, 0x70D, 0xB7},
8700 	{0x15, 0x70E, 0x09},
8701 	{0x15, 0x707, 0x10},
8702 	{0x15, 0x70D, 0xAF},
8703 	{0x15, 0x70E, 0x09},
8704 	{0x15, 0x707, 0x01},
8705 	{0x15, 0x707, 0x05},
8706 	{0x15, 0x70D, 0x73},
8707 	{0x15, 0x70E, 0x09},
8708 	{0x15, 0x707, 0x14},
8709 	{0x15, 0x6FF, 0xC4},
8710 	{}
8711 };
8712 
8713 static void ca0132_init_chip(struct hda_codec *codec)
8714 {
8715 	struct ca0132_spec *spec = codec->spec;
8716 	int num_fx;
8717 	int i;
8718 	unsigned int on;
8719 
8720 	mutex_init(&spec->chipio_mutex);
8721 
8722 	/*
8723 	 * The Windows driver always does this upon startup, which seems to
8724 	 * clear out any previous configuration. This should help issues where
8725 	 * a boot into Windows prior to a boot into Linux breaks things. Also,
8726 	 * Windows always sends the reset twice.
8727 	 */
8728 	if (ca0132_use_alt_functions(spec)) {
8729 		chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8730 		chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2);
8731 
8732 		snd_hda_codec_write(codec, codec->core.afg, 0,
8733 			    AC_VERB_SET_CODEC_RESET, 0);
8734 		snd_hda_codec_write(codec, codec->core.afg, 0,
8735 			    AC_VERB_SET_CODEC_RESET, 0);
8736 	}
8737 
8738 	spec->cur_out_type = SPEAKER_OUT;
8739 	if (!ca0132_use_alt_functions(spec))
8740 		spec->cur_mic_type = DIGITAL_MIC;
8741 	else
8742 		spec->cur_mic_type = REAR_MIC;
8743 
8744 	spec->cur_mic_boost = 0;
8745 
8746 	for (i = 0; i < VNODES_COUNT; i++) {
8747 		spec->vnode_lvol[i] = 0x5a;
8748 		spec->vnode_rvol[i] = 0x5a;
8749 		spec->vnode_lswitch[i] = 0;
8750 		spec->vnode_rswitch[i] = 0;
8751 	}
8752 
8753 	/*
8754 	 * Default states for effects are in ca0132_effects[].
8755 	 */
8756 	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
8757 	for (i = 0; i < num_fx; i++) {
8758 		on = (unsigned int)ca0132_effects[i].reqs[0];
8759 		spec->effects_switch[i] = on ? 1 : 0;
8760 	}
8761 	/*
8762 	 * Sets defaults for the effect slider controls, only for alternative
8763 	 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
8764 	 */
8765 	if (ca0132_use_alt_controls(spec)) {
8766 		/* Set speakers to default to full range. */
8767 		spec->speaker_range_val[0] = 1;
8768 		spec->speaker_range_val[1] = 1;
8769 
8770 		spec->xbass_xover_freq = 8;
8771 		for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
8772 			spec->fx_ctl_val[i] = effect_slider_defaults[i];
8773 
8774 		spec->bass_redirect_xover_freq = 8;
8775 	}
8776 
8777 	spec->voicefx_val = 0;
8778 	spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
8779 	spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
8780 
8781 	/*
8782 	 * The ZxR doesn't have a front panel header, and it's line-in is on
8783 	 * the daughter board. So, there is no input enum control, and we need
8784 	 * to make sure that spec->in_enum_val is set properly.
8785 	 */
8786 	if (ca0132_quirk(spec) == QUIRK_ZXR)
8787 		spec->in_enum_val = REAR_MIC;
8788 
8789 #ifdef ENABLE_TUNING_CONTROLS
8790 	ca0132_init_tuning_defaults(codec);
8791 #endif
8792 }
8793 
8794 /*
8795  * Recon3Di exit specific commands.
8796  */
8797 /* prevents popping noise on shutdown */
8798 static void r3di_gpio_shutdown(struct hda_codec *codec)
8799 {
8800 	snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
8801 }
8802 
8803 /*
8804  * Sound Blaster Z exit specific commands.
8805  */
8806 static void sbz_region2_exit(struct hda_codec *codec)
8807 {
8808 	struct ca0132_spec *spec = codec->spec;
8809 	unsigned int i;
8810 
8811 	for (i = 0; i < 4; i++)
8812 		writeb(0x0, spec->mem_base + 0x100);
8813 	for (i = 0; i < 8; i++)
8814 		writeb(0xb3, spec->mem_base + 0x304);
8815 
8816 	ca0113_mmio_gpio_set(codec, 0, false);
8817 	ca0113_mmio_gpio_set(codec, 1, false);
8818 	ca0113_mmio_gpio_set(codec, 4, true);
8819 	ca0113_mmio_gpio_set(codec, 5, false);
8820 	ca0113_mmio_gpio_set(codec, 7, false);
8821 }
8822 
8823 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
8824 {
8825 	static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
8826 	unsigned int i;
8827 
8828 	snd_hda_codec_write(codec, 0x11, 0,
8829 			AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
8830 
8831 	for (i = 0; i < ARRAY_SIZE(pins); i++)
8832 		snd_hda_codec_write(codec, pins[i], 0,
8833 				AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
8834 }
8835 
8836 static void ca0132_clear_unsolicited(struct hda_codec *codec)
8837 {
8838 	static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
8839 	unsigned int i;
8840 
8841 	for (i = 0; i < ARRAY_SIZE(pins); i++) {
8842 		snd_hda_codec_write(codec, pins[i], 0,
8843 				AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
8844 	}
8845 }
8846 
8847 /* On shutdown, sends commands in sets of three */
8848 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
8849 							int mask, int data)
8850 {
8851 	if (dir >= 0)
8852 		snd_hda_codec_write(codec, 0x01, 0,
8853 				AC_VERB_SET_GPIO_DIRECTION, dir);
8854 	if (mask >= 0)
8855 		snd_hda_codec_write(codec, 0x01, 0,
8856 				AC_VERB_SET_GPIO_MASK, mask);
8857 
8858 	if (data >= 0)
8859 		snd_hda_codec_write(codec, 0x01, 0,
8860 				AC_VERB_SET_GPIO_DATA, data);
8861 }
8862 
8863 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
8864 {
8865 	static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
8866 	unsigned int i;
8867 
8868 	for (i = 0; i < ARRAY_SIZE(pins); i++)
8869 		snd_hda_codec_write(codec, pins[i], 0,
8870 				AC_VERB_SET_POWER_STATE, 0x03);
8871 }
8872 
8873 static void sbz_exit_chip(struct hda_codec *codec)
8874 {
8875 	chipio_set_stream_control(codec, 0x03, 0);
8876 	chipio_set_stream_control(codec, 0x04, 0);
8877 
8878 	/* Mess with GPIO */
8879 	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
8880 	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
8881 	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
8882 
8883 	chipio_set_stream_control(codec, 0x14, 0);
8884 	chipio_set_stream_control(codec, 0x0C, 0);
8885 
8886 	chipio_set_conn_rate(codec, 0x41, SR_192_000);
8887 	chipio_set_conn_rate(codec, 0x91, SR_192_000);
8888 
8889 	chipio_write(codec, 0x18a020, 0x00000083);
8890 
8891 	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
8892 	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
8893 	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
8894 
8895 	chipio_set_stream_control(codec, 0x0C, 0);
8896 
8897 	chipio_set_control_param(codec, 0x0D, 0x24);
8898 
8899 	ca0132_clear_unsolicited(codec);
8900 	sbz_set_pin_ctl_default(codec);
8901 
8902 	snd_hda_codec_write(codec, 0x0B, 0,
8903 		AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8904 
8905 	sbz_region2_exit(codec);
8906 }
8907 
8908 static void r3d_exit_chip(struct hda_codec *codec)
8909 {
8910 	ca0132_clear_unsolicited(codec);
8911 	snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8912 	snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
8913 }
8914 
8915 static void ae5_exit_chip(struct hda_codec *codec)
8916 {
8917 	chipio_set_stream_control(codec, 0x03, 0);
8918 	chipio_set_stream_control(codec, 0x04, 0);
8919 
8920 	ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8921 	ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8922 	ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8923 	ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8924 	ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8925 	ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
8926 	ca0113_mmio_gpio_set(codec, 0, false);
8927 	ca0113_mmio_gpio_set(codec, 1, false);
8928 
8929 	snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8930 	snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8931 
8932 	chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8933 
8934 	chipio_set_stream_control(codec, 0x18, 0);
8935 	chipio_set_stream_control(codec, 0x0c, 0);
8936 
8937 	snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
8938 }
8939 
8940 static void ae7_exit_chip(struct hda_codec *codec)
8941 {
8942 	chipio_set_stream_control(codec, 0x18, 0);
8943 	chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);
8944 	chipio_set_stream_channels(codec, 0x21, 0);
8945 	chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);
8946 	chipio_set_control_param(codec, 0x20, 0x01);
8947 
8948 	chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8949 
8950 	chipio_set_stream_control(codec, 0x18, 0);
8951 	chipio_set_stream_control(codec, 0x0c, 0);
8952 
8953 	ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8954 	snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);
8955 	ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8956 	ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8957 	ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);
8958 	ca0113_mmio_gpio_set(codec, 0, false);
8959 	ca0113_mmio_gpio_set(codec, 1, false);
8960 	ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8961 
8962 	snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8963 	snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8964 }
8965 
8966 static void zxr_exit_chip(struct hda_codec *codec)
8967 {
8968 	chipio_set_stream_control(codec, 0x03, 0);
8969 	chipio_set_stream_control(codec, 0x04, 0);
8970 	chipio_set_stream_control(codec, 0x14, 0);
8971 	chipio_set_stream_control(codec, 0x0C, 0);
8972 
8973 	chipio_set_conn_rate(codec, 0x41, SR_192_000);
8974 	chipio_set_conn_rate(codec, 0x91, SR_192_000);
8975 
8976 	chipio_write(codec, 0x18a020, 0x00000083);
8977 
8978 	snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8979 	snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8980 
8981 	ca0132_clear_unsolicited(codec);
8982 	sbz_set_pin_ctl_default(codec);
8983 	snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8984 
8985 	ca0113_mmio_gpio_set(codec, 5, false);
8986 	ca0113_mmio_gpio_set(codec, 2, false);
8987 	ca0113_mmio_gpio_set(codec, 3, false);
8988 	ca0113_mmio_gpio_set(codec, 0, false);
8989 	ca0113_mmio_gpio_set(codec, 4, true);
8990 	ca0113_mmio_gpio_set(codec, 0, true);
8991 	ca0113_mmio_gpio_set(codec, 5, true);
8992 	ca0113_mmio_gpio_set(codec, 2, false);
8993 	ca0113_mmio_gpio_set(codec, 3, false);
8994 }
8995 
8996 static void ca0132_exit_chip(struct hda_codec *codec)
8997 {
8998 	/* put any chip cleanup stuffs here. */
8999 
9000 	if (dspload_is_loaded(codec))
9001 		dsp_reset(codec);
9002 }
9003 
9004 /*
9005  * This fixes a problem that was hard to reproduce. Very rarely, I would
9006  * boot up, and there would be no sound, but the DSP indicated it had loaded
9007  * properly. I did a few memory dumps to see if anything was different, and
9008  * there were a few areas of memory uninitialized with a1a2a3a4. This function
9009  * checks if those areas are uninitialized, and if they are, it'll attempt to
9010  * reload the card 3 times. Usually it fixes by the second.
9011  */
9012 static void sbz_dsp_startup_check(struct hda_codec *codec)
9013 {
9014 	struct ca0132_spec *spec = codec->spec;
9015 	unsigned int dsp_data_check[4];
9016 	unsigned int cur_address = 0x390;
9017 	unsigned int i;
9018 	unsigned int failure = 0;
9019 	unsigned int reload = 3;
9020 
9021 	if (spec->startup_check_entered)
9022 		return;
9023 
9024 	spec->startup_check_entered = true;
9025 
9026 	for (i = 0; i < 4; i++) {
9027 		chipio_read(codec, cur_address, &dsp_data_check[i]);
9028 		cur_address += 0x4;
9029 	}
9030 	for (i = 0; i < 4; i++) {
9031 		if (dsp_data_check[i] == 0xa1a2a3a4)
9032 			failure = 1;
9033 	}
9034 
9035 	codec_dbg(codec, "Startup Check: %d ", failure);
9036 	if (failure)
9037 		codec_info(codec, "DSP not initialized properly. Attempting to fix.");
9038 	/*
9039 	 * While the failure condition is true, and we haven't reached our
9040 	 * three reload limit, continue trying to reload the driver and
9041 	 * fix the issue.
9042 	 */
9043 	while (failure && (reload != 0)) {
9044 		codec_info(codec, "Reloading... Tries left: %d", reload);
9045 		sbz_exit_chip(codec);
9046 		spec->dsp_state = DSP_DOWNLOAD_INIT;
9047 		snd_hda_codec_init(codec);
9048 		failure = 0;
9049 		for (i = 0; i < 4; i++) {
9050 			chipio_read(codec, cur_address, &dsp_data_check[i]);
9051 			cur_address += 0x4;
9052 		}
9053 		for (i = 0; i < 4; i++) {
9054 			if (dsp_data_check[i] == 0xa1a2a3a4)
9055 				failure = 1;
9056 		}
9057 		reload--;
9058 	}
9059 
9060 	if (!failure && reload < 3)
9061 		codec_info(codec, "DSP fixed.");
9062 
9063 	if (!failure)
9064 		return;
9065 
9066 	codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
9067 }
9068 
9069 /*
9070  * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
9071  * extra precision for decibel values. If you had the dB value in floating point
9072  * you would take the value after the decimal point, multiply by 64, and divide
9073  * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
9074  * implement fixed point or floating point dB volumes. For now, I'll set them
9075  * to 0 just incase a value has lingered from a boot into Windows.
9076  */
9077 static void ca0132_alt_vol_setup(struct hda_codec *codec)
9078 {
9079 	snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
9080 	snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
9081 	snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
9082 	snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
9083 	snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
9084 	snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
9085 	snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
9086 	snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
9087 }
9088 
9089 /*
9090  * Extra commands that don't really fit anywhere else.
9091  */
9092 static void sbz_pre_dsp_setup(struct hda_codec *codec)
9093 {
9094 	struct ca0132_spec *spec = codec->spec;
9095 
9096 	writel(0x00820680, spec->mem_base + 0x01C);
9097 	writel(0x00820680, spec->mem_base + 0x01C);
9098 
9099 	chipio_write(codec, 0x18b0a4, 0x000000c2);
9100 
9101 	snd_hda_codec_write(codec, 0x11, 0,
9102 			AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9103 }
9104 
9105 static void r3d_pre_dsp_setup(struct hda_codec *codec)
9106 {
9107 	chipio_write(codec, 0x18b0a4, 0x000000c2);
9108 
9109 	chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9110 
9111 	snd_hda_codec_write(codec, 0x11, 0,
9112 			AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9113 }
9114 
9115 static void r3di_pre_dsp_setup(struct hda_codec *codec)
9116 {
9117 	chipio_write(codec, 0x18b0a4, 0x000000c2);
9118 
9119 	chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9120 	chipio_8051_write_exram(codec, 0x1920, 0x00);
9121 	chipio_8051_write_exram(codec, 0x1921, 0x40);
9122 
9123 	snd_hda_codec_write(codec, 0x11, 0,
9124 			AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
9125 }
9126 
9127 /*
9128  * The ZxR seems to use alternative DAC's for the surround channels, which
9129  * require PLL PMU setup for the clock rate, I'm guessing. Without setting
9130  * this up, we get no audio out of the surround jacks.
9131  */
9132 static void zxr_pre_dsp_setup(struct hda_codec *codec)
9133 {
9134 	static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 };
9135 	static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d };
9136 	unsigned int i;
9137 
9138 	chipio_write(codec, 0x189000, 0x0001f100);
9139 	msleep(50);
9140 	chipio_write(codec, 0x18900c, 0x0001f100);
9141 	msleep(50);
9142 
9143 	/*
9144 	 * This writes a RET instruction at the entry point of the function at
9145 	 * 0xfa92 in exram. This function seems to have something to do with
9146 	 * ASI. Might be some way to prevent the card from reconfiguring the
9147 	 * ASI stuff itself.
9148 	 */
9149 	chipio_8051_write_exram(codec, 0xfa92, 0x22);
9150 
9151 	chipio_8051_write_pll_pmu(codec, 0x51, 0x98);
9152 
9153 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82);
9154 	chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3);
9155 
9156 	chipio_write(codec, 0x18902c, 0x00000000);
9157 	msleep(50);
9158 	chipio_write(codec, 0x18902c, 0x00000003);
9159 	msleep(50);
9160 
9161 	for (i = 0; i < ARRAY_SIZE(addr); i++)
9162 		chipio_8051_write_pll_pmu(codec, addr[i], data[i]);
9163 }
9164 
9165 /*
9166  * These are sent before the DSP is downloaded. Not sure
9167  * what they do, or if they're necessary. Could possibly
9168  * be removed. Figure they're better to leave in.
9169  */
9170 static const unsigned int ca0113_mmio_init_address_sbz[] = {
9171 	0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c,
9172 	0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04
9173 };
9174 
9175 static const unsigned int ca0113_mmio_init_data_sbz[] = {
9176 	0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9177 	0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7,
9178 	0x000000c1, 0x00000080
9179 };
9180 
9181 static const unsigned int ca0113_mmio_init_data_zxr[] = {
9182 	0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003,
9183 	0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7,
9184 	0x000000c1, 0x00000080
9185 };
9186 
9187 static const unsigned int ca0113_mmio_init_address_ae5[] = {
9188 	0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408,
9189 	0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800,
9190 	0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c,
9191 	0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c
9192 };
9193 
9194 static const unsigned int ca0113_mmio_init_data_ae5[] = {
9195 	0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9196 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
9197 	0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f,
9198 	0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b,
9199 	0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030,
9200 	0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9201 	0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1,
9202 	0x00000080, 0x00880680
9203 };
9204 
9205 static void ca0132_mmio_init_sbz(struct hda_codec *codec)
9206 {
9207 	struct ca0132_spec *spec = codec->spec;
9208 	unsigned int tmp[2], i, count, cur_addr;
9209 	const unsigned int *addr, *data;
9210 
9211 	addr = ca0113_mmio_init_address_sbz;
9212 	for (i = 0; i < 3; i++)
9213 		writel(0x00000000, spec->mem_base + addr[i]);
9214 
9215 	cur_addr = i;
9216 	switch (ca0132_quirk(spec)) {
9217 	case QUIRK_ZXR:
9218 		tmp[0] = 0x00880480;
9219 		tmp[1] = 0x00000080;
9220 		break;
9221 	case QUIRK_SBZ:
9222 		tmp[0] = 0x00820680;
9223 		tmp[1] = 0x00000083;
9224 		break;
9225 	case QUIRK_R3D:
9226 		tmp[0] = 0x00880680;
9227 		tmp[1] = 0x00000083;
9228 		break;
9229 	default:
9230 		tmp[0] = 0x00000000;
9231 		tmp[1] = 0x00000000;
9232 		break;
9233 	}
9234 
9235 	for (i = 0; i < 2; i++)
9236 		writel(tmp[i], spec->mem_base + addr[cur_addr + i]);
9237 
9238 	cur_addr += i;
9239 
9240 	switch (ca0132_quirk(spec)) {
9241 	case QUIRK_ZXR:
9242 		count = ARRAY_SIZE(ca0113_mmio_init_data_zxr);
9243 		data = ca0113_mmio_init_data_zxr;
9244 		break;
9245 	default:
9246 		count = ARRAY_SIZE(ca0113_mmio_init_data_sbz);
9247 		data = ca0113_mmio_init_data_sbz;
9248 		break;
9249 	}
9250 
9251 	for (i = 0; i < count; i++)
9252 		writel(data[i], spec->mem_base + addr[cur_addr + i]);
9253 }
9254 
9255 static void ca0132_mmio_init_ae5(struct hda_codec *codec)
9256 {
9257 	struct ca0132_spec *spec = codec->spec;
9258 	const unsigned int *addr, *data;
9259 	unsigned int i, count;
9260 
9261 	addr = ca0113_mmio_init_address_ae5;
9262 	data = ca0113_mmio_init_data_ae5;
9263 	count = ARRAY_SIZE(ca0113_mmio_init_data_ae5);
9264 
9265 	if (ca0132_quirk(spec) == QUIRK_AE7) {
9266 		writel(0x00000680, spec->mem_base + 0x1c);
9267 		writel(0x00880680, spec->mem_base + 0x1c);
9268 	}
9269 
9270 	for (i = 0; i < count; i++) {
9271 		/*
9272 		 * AE-7 shares all writes with the AE-5, except that it writes
9273 		 * a different value to 0x20c.
9274 		 */
9275 		if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) {
9276 			writel(0x00800001, spec->mem_base + addr[i]);
9277 			continue;
9278 		}
9279 
9280 		writel(data[i], spec->mem_base + addr[i]);
9281 	}
9282 
9283 	if (ca0132_quirk(spec) == QUIRK_AE5)
9284 		writel(0x00880680, spec->mem_base + 0x1c);
9285 }
9286 
9287 static void ca0132_mmio_init(struct hda_codec *codec)
9288 {
9289 	struct ca0132_spec *spec = codec->spec;
9290 
9291 	switch (ca0132_quirk(spec)) {
9292 	case QUIRK_R3D:
9293 	case QUIRK_SBZ:
9294 	case QUIRK_ZXR:
9295 		ca0132_mmio_init_sbz(codec);
9296 		break;
9297 	case QUIRK_AE5:
9298 		ca0132_mmio_init_ae5(codec);
9299 		break;
9300 	default:
9301 		break;
9302 	}
9303 }
9304 
9305 static const unsigned int ca0132_ae5_register_set_addresses[] = {
9306 	0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304,
9307 	0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804
9308 };
9309 
9310 static const unsigned char ca0132_ae5_register_set_data[] = {
9311 	0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b,
9312 	0x01, 0x6b, 0x57
9313 };
9314 
9315 /*
9316  * This function writes to some SFR's, does some region2 writes, and then
9317  * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
9318  * what it does.
9319  */
9320 static void ae5_register_set(struct hda_codec *codec)
9321 {
9322 	struct ca0132_spec *spec = codec->spec;
9323 	unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses);
9324 	const unsigned int *addr = ca0132_ae5_register_set_addresses;
9325 	const unsigned char *data = ca0132_ae5_register_set_data;
9326 	unsigned int i, cur_addr;
9327 	unsigned char tmp[3];
9328 
9329 	if (ca0132_quirk(spec) == QUIRK_AE7)
9330 		chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
9331 
9332 	chipio_8051_write_direct(codec, 0x93, 0x10);
9333 	chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
9334 
9335 	if (ca0132_quirk(spec) == QUIRK_AE7) {
9336 		tmp[0] = 0x03;
9337 		tmp[1] = 0x03;
9338 		tmp[2] = 0x07;
9339 	} else {
9340 		tmp[0] = 0x0f;
9341 		tmp[1] = 0x0f;
9342 		tmp[2] = 0x0f;
9343 	}
9344 
9345 	for (i = cur_addr = 0; i < 3; i++, cur_addr++)
9346 		writeb(tmp[i], spec->mem_base + addr[cur_addr]);
9347 
9348 	/*
9349 	 * First writes are in single bytes, final are in 4 bytes. So, we use
9350 	 * writeb, then writel.
9351 	 */
9352 	for (i = 0; cur_addr < 12; i++, cur_addr++)
9353 		writeb(data[i], spec->mem_base + addr[cur_addr]);
9354 
9355 	for (; cur_addr < count; i++, cur_addr++)
9356 		writel(data[i], spec->mem_base + addr[cur_addr]);
9357 
9358 	writel(0x00800001, spec->mem_base + 0x20c);
9359 
9360 	if (ca0132_quirk(spec) == QUIRK_AE7) {
9361 		ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9362 		ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
9363 	} else {
9364 		ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
9365 	}
9366 
9367 	chipio_8051_write_direct(codec, 0x90, 0x00);
9368 	chipio_8051_write_direct(codec, 0x90, 0x10);
9369 
9370 	if (ca0132_quirk(spec) == QUIRK_AE5)
9371 		ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
9372 }
9373 
9374 /*
9375  * Extra init functions for alternative ca0132 codecs. Done
9376  * here so they don't clutter up the main ca0132_init function
9377  * anymore than they have to.
9378  */
9379 static void ca0132_alt_init(struct hda_codec *codec)
9380 {
9381 	struct ca0132_spec *spec = codec->spec;
9382 
9383 	ca0132_alt_vol_setup(codec);
9384 
9385 	switch (ca0132_quirk(spec)) {
9386 	case QUIRK_SBZ:
9387 		codec_dbg(codec, "SBZ alt_init");
9388 		ca0132_gpio_init(codec);
9389 		sbz_pre_dsp_setup(codec);
9390 		snd_hda_sequence_write(codec, spec->chip_init_verbs);
9391 		snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9392 		break;
9393 	case QUIRK_R3DI:
9394 		codec_dbg(codec, "R3DI alt_init");
9395 		ca0132_gpio_init(codec);
9396 		ca0132_gpio_setup(codec);
9397 		r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
9398 		r3di_pre_dsp_setup(codec);
9399 		snd_hda_sequence_write(codec, spec->chip_init_verbs);
9400 		snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
9401 		break;
9402 	case QUIRK_R3D:
9403 		r3d_pre_dsp_setup(codec);
9404 		snd_hda_sequence_write(codec, spec->chip_init_verbs);
9405 		snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9406 		break;
9407 	case QUIRK_AE5:
9408 		ca0132_gpio_init(codec);
9409 		chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9410 		chipio_write(codec, 0x18b030, 0x00000020);
9411 		snd_hda_sequence_write(codec, spec->chip_init_verbs);
9412 		snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9413 		ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9414 		break;
9415 	case QUIRK_AE7:
9416 		ca0132_gpio_init(codec);
9417 		chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9418 		snd_hda_sequence_write(codec, spec->chip_init_verbs);
9419 		snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9420 		chipio_write(codec, 0x18b008, 0x000000f8);
9421 		chipio_write(codec, 0x18b008, 0x000000f0);
9422 		chipio_write(codec, 0x18b030, 0x00000020);
9423 		ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9424 		break;
9425 	case QUIRK_ZXR:
9426 		chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9427 		snd_hda_sequence_write(codec, spec->chip_init_verbs);
9428 		snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9429 		zxr_pre_dsp_setup(codec);
9430 		break;
9431 	default:
9432 		break;
9433 	}
9434 }
9435 
9436 static int ca0132_init(struct hda_codec *codec)
9437 {
9438 	struct ca0132_spec *spec = codec->spec;
9439 	struct auto_pin_cfg *cfg = &spec->autocfg;
9440 	int i;
9441 	bool dsp_loaded;
9442 
9443 	/*
9444 	 * If the DSP is already downloaded, and init has been entered again,
9445 	 * there's only two reasons for it. One, the codec has awaken from a
9446 	 * suspended state, and in that case dspload_is_loaded will return
9447 	 * false, and the init will be ran again. The other reason it gets
9448 	 * re entered is on startup for some reason it triggers a suspend and
9449 	 * resume state. In this case, it will check if the DSP is downloaded,
9450 	 * and not run the init function again. For codecs using alt_functions,
9451 	 * it will check if the DSP is loaded properly.
9452 	 */
9453 	if (spec->dsp_state == DSP_DOWNLOADED) {
9454 		dsp_loaded = dspload_is_loaded(codec);
9455 		if (!dsp_loaded) {
9456 			spec->dsp_reload = true;
9457 			spec->dsp_state = DSP_DOWNLOAD_INIT;
9458 		} else {
9459 			if (ca0132_quirk(spec) == QUIRK_SBZ)
9460 				sbz_dsp_startup_check(codec);
9461 			return 0;
9462 		}
9463 	}
9464 
9465 	if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
9466 		spec->dsp_state = DSP_DOWNLOAD_INIT;
9467 	spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
9468 
9469 	if (ca0132_use_pci_mmio(spec))
9470 		ca0132_mmio_init(codec);
9471 
9472 	CLASS(snd_hda_power_pm, pm)(codec);
9473 
9474 	if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7)
9475 		ae5_register_set(codec);
9476 
9477 	ca0132_init_params(codec);
9478 	ca0132_init_flags(codec);
9479 
9480 	snd_hda_sequence_write(codec, spec->base_init_verbs);
9481 
9482 	if (ca0132_use_alt_functions(spec))
9483 		ca0132_alt_init(codec);
9484 
9485 	ca0132_download_dsp(codec);
9486 
9487 	ca0132_refresh_widget_caps(codec);
9488 
9489 	switch (ca0132_quirk(spec)) {
9490 	case QUIRK_R3DI:
9491 	case QUIRK_R3D:
9492 		r3d_setup_defaults(codec);
9493 		break;
9494 	case QUIRK_SBZ:
9495 	case QUIRK_ZXR:
9496 		sbz_setup_defaults(codec);
9497 		break;
9498 	case QUIRK_AE5:
9499 		ae5_setup_defaults(codec);
9500 		break;
9501 	case QUIRK_AE7:
9502 		ae7_setup_defaults(codec);
9503 		break;
9504 	default:
9505 		ca0132_setup_defaults(codec);
9506 		ca0132_init_analog_mic2(codec);
9507 		ca0132_init_dmic(codec);
9508 		break;
9509 	}
9510 
9511 	for (i = 0; i < spec->num_outputs; i++)
9512 		init_output(codec, spec->out_pins[i], spec->dacs[0]);
9513 
9514 	init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9515 
9516 	for (i = 0; i < spec->num_inputs; i++)
9517 		init_input(codec, spec->input_pins[i], spec->adcs[i]);
9518 
9519 	init_input(codec, cfg->dig_in_pin, spec->dig_in);
9520 
9521 	if (!ca0132_use_alt_functions(spec)) {
9522 		snd_hda_sequence_write(codec, spec->chip_init_verbs);
9523 		snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9524 			    VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
9525 		snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9526 			    VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
9527 	}
9528 
9529 	if (ca0132_quirk(spec) == QUIRK_SBZ)
9530 		ca0132_gpio_setup(codec);
9531 
9532 	snd_hda_sequence_write(codec, spec->spec_init_verbs);
9533 	if (ca0132_use_alt_functions(spec)) {
9534 		ca0132_alt_select_out(codec);
9535 		ca0132_alt_select_in(codec);
9536 	} else {
9537 		ca0132_select_out(codec);
9538 		ca0132_select_mic(codec);
9539 	}
9540 
9541 	snd_hda_jack_report_sync(codec);
9542 
9543 	/*
9544 	 * Re set the PlayEnhancement switch on a resume event, because the
9545 	 * controls will not be reloaded.
9546 	 */
9547 	if (spec->dsp_reload) {
9548 		spec->dsp_reload = false;
9549 		ca0132_pe_switch_set(codec);
9550 	}
9551 
9552 	return 0;
9553 }
9554 
9555 static int dbpro_init(struct hda_codec *codec)
9556 {
9557 	struct ca0132_spec *spec = codec->spec;
9558 	struct auto_pin_cfg *cfg = &spec->autocfg;
9559 	unsigned int i;
9560 
9561 	init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9562 	init_input(codec, cfg->dig_in_pin, spec->dig_in);
9563 
9564 	for (i = 0; i < spec->num_inputs; i++)
9565 		init_input(codec, spec->input_pins[i], spec->adcs[i]);
9566 
9567 	return 0;
9568 }
9569 
9570 static void ca0132_free(struct hda_codec *codec)
9571 {
9572 	struct ca0132_spec *spec = codec->spec;
9573 
9574 	cancel_delayed_work_sync(&spec->unsol_hp_work);
9575 	snd_hda_power_up(codec);
9576 	switch (ca0132_quirk(spec)) {
9577 	case QUIRK_SBZ:
9578 		sbz_exit_chip(codec);
9579 		break;
9580 	case QUIRK_ZXR:
9581 		zxr_exit_chip(codec);
9582 		break;
9583 	case QUIRK_R3D:
9584 		r3d_exit_chip(codec);
9585 		break;
9586 	case QUIRK_AE5:
9587 		ae5_exit_chip(codec);
9588 		break;
9589 	case QUIRK_AE7:
9590 		ae7_exit_chip(codec);
9591 		break;
9592 	case QUIRK_R3DI:
9593 		r3di_gpio_shutdown(codec);
9594 		break;
9595 	default:
9596 		break;
9597 	}
9598 
9599 	snd_hda_sequence_write(codec, spec->base_exit_verbs);
9600 	ca0132_exit_chip(codec);
9601 
9602 	snd_hda_power_down(codec);
9603 #ifdef CONFIG_PCI
9604 	if (spec->mem_base)
9605 		pci_iounmap(codec->bus->pci, spec->mem_base);
9606 #endif
9607 	kfree(spec->spec_init_verbs);
9608 	kfree(codec->spec);
9609 }
9610 
9611 static void dbpro_free(struct hda_codec *codec)
9612 {
9613 	struct ca0132_spec *spec = codec->spec;
9614 
9615 	zxr_dbpro_power_state_shutdown(codec);
9616 
9617 	kfree(spec->spec_init_verbs);
9618 	kfree(codec->spec);
9619 }
9620 
9621 static void ca0132_config(struct hda_codec *codec)
9622 {
9623 	struct ca0132_spec *spec = codec->spec;
9624 
9625 	spec->dacs[0] = 0x2;
9626 	spec->dacs[1] = 0x3;
9627 	spec->dacs[2] = 0x4;
9628 
9629 	spec->multiout.dac_nids = spec->dacs;
9630 	spec->multiout.num_dacs = 3;
9631 
9632 	if (!ca0132_use_alt_functions(spec))
9633 		spec->multiout.max_channels = 2;
9634 	else
9635 		spec->multiout.max_channels = 6;
9636 
9637 	switch (ca0132_quirk(spec)) {
9638 	case QUIRK_ALIENWARE:
9639 		codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
9640 		snd_hda_apply_pincfgs(codec, alienware_pincfgs);
9641 		break;
9642 	case QUIRK_SBZ:
9643 		codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
9644 		snd_hda_apply_pincfgs(codec, sbz_pincfgs);
9645 		break;
9646 	case QUIRK_ZXR:
9647 		codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
9648 		snd_hda_apply_pincfgs(codec, zxr_pincfgs);
9649 		break;
9650 	case QUIRK_R3D:
9651 		codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
9652 		snd_hda_apply_pincfgs(codec, r3d_pincfgs);
9653 		break;
9654 	case QUIRK_R3DI:
9655 		codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
9656 		snd_hda_apply_pincfgs(codec, r3di_pincfgs);
9657 		break;
9658 	case QUIRK_AE5:
9659 		codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
9660 		snd_hda_apply_pincfgs(codec, ae5_pincfgs);
9661 		break;
9662 	case QUIRK_AE7:
9663 		codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__);
9664 		snd_hda_apply_pincfgs(codec, ae7_pincfgs);
9665 		break;
9666 	default:
9667 		break;
9668 	}
9669 
9670 	switch (ca0132_quirk(spec)) {
9671 	case QUIRK_ALIENWARE:
9672 		spec->num_outputs = 2;
9673 		spec->out_pins[0] = 0x0b; /* speaker out */
9674 		spec->out_pins[1] = 0x0f;
9675 		spec->shared_out_nid = 0x2;
9676 		spec->unsol_tag_hp = 0x0f;
9677 
9678 		spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9679 		spec->adcs[1] = 0x8; /* analog mic2 */
9680 		spec->adcs[2] = 0xa; /* what u hear */
9681 
9682 		spec->num_inputs = 3;
9683 		spec->input_pins[0] = 0x12;
9684 		spec->input_pins[1] = 0x11;
9685 		spec->input_pins[2] = 0x13;
9686 		spec->shared_mic_nid = 0x7;
9687 		spec->unsol_tag_amic1 = 0x11;
9688 		break;
9689 	case QUIRK_SBZ:
9690 	case QUIRK_R3D:
9691 		spec->num_outputs = 2;
9692 		spec->out_pins[0] = 0x0B; /* Line out */
9693 		spec->out_pins[1] = 0x0F; /* Rear headphone out */
9694 		spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9695 		spec->out_pins[3] = 0x11; /* Rear surround */
9696 		spec->shared_out_nid = 0x2;
9697 		spec->unsol_tag_hp = spec->out_pins[1];
9698 		spec->unsol_tag_front_hp = spec->out_pins[2];
9699 
9700 		spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9701 		spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9702 		spec->adcs[2] = 0xa; /* what u hear */
9703 
9704 		spec->num_inputs = 2;
9705 		spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9706 		spec->input_pins[1] = 0x13; /* What U Hear */
9707 		spec->shared_mic_nid = 0x7;
9708 		spec->unsol_tag_amic1 = spec->input_pins[0];
9709 
9710 		/* SPDIF I/O */
9711 		spec->dig_out = 0x05;
9712 		spec->multiout.dig_out_nid = spec->dig_out;
9713 		spec->dig_in = 0x09;
9714 		break;
9715 	case QUIRK_ZXR:
9716 		spec->num_outputs = 2;
9717 		spec->out_pins[0] = 0x0B; /* Line out */
9718 		spec->out_pins[1] = 0x0F; /* Rear headphone out */
9719 		spec->out_pins[2] = 0x10; /* Center/LFE */
9720 		spec->out_pins[3] = 0x11; /* Rear surround */
9721 		spec->shared_out_nid = 0x2;
9722 		spec->unsol_tag_hp = spec->out_pins[1];
9723 		spec->unsol_tag_front_hp = spec->out_pins[2];
9724 
9725 		spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9726 		spec->adcs[1] = 0x8; /* Not connected, no front mic */
9727 		spec->adcs[2] = 0xa; /* what u hear */
9728 
9729 		spec->num_inputs = 2;
9730 		spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9731 		spec->input_pins[1] = 0x13; /* What U Hear */
9732 		spec->shared_mic_nid = 0x7;
9733 		spec->unsol_tag_amic1 = spec->input_pins[0];
9734 		break;
9735 	case QUIRK_ZXR_DBPRO:
9736 		spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
9737 
9738 		spec->num_inputs = 1;
9739 		spec->input_pins[0] = 0x11; /* RCA Line-in */
9740 
9741 		spec->dig_out = 0x05;
9742 		spec->multiout.dig_out_nid = spec->dig_out;
9743 
9744 		spec->dig_in = 0x09;
9745 		break;
9746 	case QUIRK_AE5:
9747 	case QUIRK_AE7:
9748 		spec->num_outputs = 2;
9749 		spec->out_pins[0] = 0x0B; /* Line out */
9750 		spec->out_pins[1] = 0x11; /* Rear headphone out */
9751 		spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9752 		spec->out_pins[3] = 0x0F; /* Rear surround */
9753 		spec->shared_out_nid = 0x2;
9754 		spec->unsol_tag_hp = spec->out_pins[1];
9755 		spec->unsol_tag_front_hp = spec->out_pins[2];
9756 
9757 		spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9758 		spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9759 		spec->adcs[2] = 0xa; /* what u hear */
9760 
9761 		spec->num_inputs = 2;
9762 		spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9763 		spec->input_pins[1] = 0x13; /* What U Hear */
9764 		spec->shared_mic_nid = 0x7;
9765 		spec->unsol_tag_amic1 = spec->input_pins[0];
9766 
9767 		/* SPDIF I/O */
9768 		spec->dig_out = 0x05;
9769 		spec->multiout.dig_out_nid = spec->dig_out;
9770 		break;
9771 	case QUIRK_R3DI:
9772 		spec->num_outputs = 2;
9773 		spec->out_pins[0] = 0x0B; /* Line out */
9774 		spec->out_pins[1] = 0x0F; /* Rear headphone out */
9775 		spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9776 		spec->out_pins[3] = 0x11; /* Rear surround */
9777 		spec->shared_out_nid = 0x2;
9778 		spec->unsol_tag_hp = spec->out_pins[1];
9779 		spec->unsol_tag_front_hp = spec->out_pins[2];
9780 
9781 		spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
9782 		spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
9783 		spec->adcs[2] = 0x0a; /* what u hear */
9784 
9785 		spec->num_inputs = 2;
9786 		spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9787 		spec->input_pins[1] = 0x13; /* What U Hear */
9788 		spec->shared_mic_nid = 0x7;
9789 		spec->unsol_tag_amic1 = spec->input_pins[0];
9790 
9791 		/* SPDIF I/O */
9792 		spec->dig_out = 0x05;
9793 		spec->multiout.dig_out_nid = spec->dig_out;
9794 		break;
9795 	default:
9796 		spec->num_outputs = 2;
9797 		spec->out_pins[0] = 0x0b; /* speaker out */
9798 		spec->out_pins[1] = 0x10; /* headphone out */
9799 		spec->shared_out_nid = 0x2;
9800 		spec->unsol_tag_hp = spec->out_pins[1];
9801 
9802 		spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9803 		spec->adcs[1] = 0x8; /* analog mic2 */
9804 		spec->adcs[2] = 0xa; /* what u hear */
9805 
9806 		spec->num_inputs = 3;
9807 		spec->input_pins[0] = 0x12;
9808 		spec->input_pins[1] = 0x11;
9809 		spec->input_pins[2] = 0x13;
9810 		spec->shared_mic_nid = 0x7;
9811 		spec->unsol_tag_amic1 = spec->input_pins[0];
9812 
9813 		/* SPDIF I/O */
9814 		spec->dig_out = 0x05;
9815 		spec->multiout.dig_out_nid = spec->dig_out;
9816 		spec->dig_in = 0x09;
9817 		break;
9818 	}
9819 }
9820 
9821 static int ca0132_prepare_verbs(struct hda_codec *codec)
9822 {
9823 /* Verbs + terminator (an empty element) */
9824 #define NUM_SPEC_VERBS 2
9825 	struct ca0132_spec *spec = codec->spec;
9826 
9827 	spec->chip_init_verbs = ca0132_init_verbs0;
9828 	/*
9829 	 * Since desktop cards use pci_mmio, this can be used to determine
9830 	 * whether or not to use these verbs instead of a separate bool.
9831 	 */
9832 	if (ca0132_use_pci_mmio(spec))
9833 		spec->desktop_init_verbs = ca0132_init_verbs1;
9834 	spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
9835 					sizeof(struct hda_verb),
9836 					GFP_KERNEL);
9837 	if (!spec->spec_init_verbs)
9838 		return -ENOMEM;
9839 
9840 	/* config EAPD */
9841 	spec->spec_init_verbs[0].nid = 0x0b;
9842 	spec->spec_init_verbs[0].param = 0x78D;
9843 	spec->spec_init_verbs[0].verb = 0x00;
9844 
9845 	/* Previously commented configuration */
9846 	/*
9847 	spec->spec_init_verbs[2].nid = 0x0b;
9848 	spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
9849 	spec->spec_init_verbs[2].verb = 0x02;
9850 
9851 	spec->spec_init_verbs[3].nid = 0x10;
9852 	spec->spec_init_verbs[3].param = 0x78D;
9853 	spec->spec_init_verbs[3].verb = 0x02;
9854 
9855 	spec->spec_init_verbs[4].nid = 0x10;
9856 	spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
9857 	spec->spec_init_verbs[4].verb = 0x02;
9858 	*/
9859 
9860 	/* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
9861 	return 0;
9862 }
9863 
9864 /*
9865  * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
9866  * Sound Blaster Z cards. However, they have different HDA codec subsystem
9867  * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
9868  * daughter boards ID.
9869  */
9870 static void sbz_detect_quirk(struct hda_codec *codec)
9871 {
9872 	switch (codec->core.subsystem_id) {
9873 	case 0x11020033:
9874 		codec->fixup_id = QUIRK_ZXR;
9875 		break;
9876 	case 0x1102003f:
9877 		codec->fixup_id = QUIRK_ZXR_DBPRO;
9878 		break;
9879 	default:
9880 		codec->fixup_id = QUIRK_SBZ;
9881 		break;
9882 	}
9883 }
9884 
9885 static void ca0132_codec_remove(struct hda_codec *codec)
9886 {
9887 	struct ca0132_spec *spec = codec->spec;
9888 
9889 	if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
9890 		return dbpro_free(codec);
9891 	else
9892 		return ca0132_free(codec);
9893 }
9894 
9895 static int ca0132_codec_probe(struct hda_codec *codec,
9896 			      const struct hda_device_id *id)
9897 {
9898 	struct ca0132_spec *spec;
9899 	int err;
9900 
9901 	codec_dbg(codec, "%s\n", __func__);
9902 
9903 	spec = kzalloc(sizeof(*spec), GFP_KERNEL);
9904 	if (!spec)
9905 		return -ENOMEM;
9906 	codec->spec = spec;
9907 	spec->codec = codec;
9908 
9909 	/* Detect codec quirk */
9910 	snd_hda_pick_fixup(codec, ca0132_quirk_models, ca0132_quirks, NULL);
9911 	if (ca0132_quirk(spec) == QUIRK_SBZ)
9912 		sbz_detect_quirk(codec);
9913 
9914 	codec->pcm_format_first = 1;
9915 	codec->no_sticky_stream = 1;
9916 
9917 
9918 	spec->dsp_state = DSP_DOWNLOAD_INIT;
9919 	spec->num_mixers = 1;
9920 
9921 	/* Set which mixers each quirk uses. */
9922 	switch (ca0132_quirk(spec)) {
9923 	case QUIRK_SBZ:
9924 		spec->mixers[0] = desktop_mixer;
9925 		snd_hda_codec_set_name(codec, "Sound Blaster Z");
9926 		break;
9927 	case QUIRK_ZXR:
9928 		spec->mixers[0] = desktop_mixer;
9929 		snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
9930 		break;
9931 	case QUIRK_ZXR_DBPRO:
9932 		break;
9933 	case QUIRK_R3D:
9934 		spec->mixers[0] = desktop_mixer;
9935 		snd_hda_codec_set_name(codec, "Recon3D");
9936 		break;
9937 	case QUIRK_R3DI:
9938 		spec->mixers[0] = r3di_mixer;
9939 		snd_hda_codec_set_name(codec, "Recon3Di");
9940 		break;
9941 	case QUIRK_AE5:
9942 		spec->mixers[0] = desktop_mixer;
9943 		snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
9944 		break;
9945 	case QUIRK_AE7:
9946 		spec->mixers[0] = desktop_mixer;
9947 		snd_hda_codec_set_name(codec, "Sound Blaster AE-7");
9948 		break;
9949 	default:
9950 		spec->mixers[0] = ca0132_mixer;
9951 		break;
9952 	}
9953 
9954 	/* Setup whether or not to use alt functions/controls/pci_mmio */
9955 	switch (ca0132_quirk(spec)) {
9956 	case QUIRK_SBZ:
9957 	case QUIRK_R3D:
9958 	case QUIRK_AE5:
9959 	case QUIRK_AE7:
9960 	case QUIRK_ZXR:
9961 		spec->use_alt_controls = true;
9962 		spec->use_alt_functions = true;
9963 		spec->use_pci_mmio = true;
9964 		break;
9965 	case QUIRK_R3DI:
9966 		spec->use_alt_controls = true;
9967 		spec->use_alt_functions = true;
9968 		spec->use_pci_mmio = false;
9969 		break;
9970 	default:
9971 		spec->use_alt_controls = false;
9972 		spec->use_alt_functions = false;
9973 		spec->use_pci_mmio = false;
9974 		break;
9975 	}
9976 
9977 #ifdef CONFIG_PCI
9978 	if (spec->use_pci_mmio) {
9979 		spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
9980 		if (spec->mem_base == NULL) {
9981 			codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
9982 			codec->fixup_id = QUIRK_NONE;
9983 		}
9984 	}
9985 #endif
9986 
9987 	spec->base_init_verbs = ca0132_base_init_verbs;
9988 	spec->base_exit_verbs = ca0132_base_exit_verbs;
9989 
9990 	INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
9991 
9992 	ca0132_init_chip(codec);
9993 
9994 	ca0132_config(codec);
9995 
9996 	err = ca0132_prepare_verbs(codec);
9997 	if (err < 0)
9998 		goto error;
9999 
10000 	err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
10001 	if (err < 0)
10002 		goto error;
10003 
10004 	ca0132_setup_unsol(codec);
10005 
10006 	return 0;
10007 
10008  error:
10009 	ca0132_codec_remove(codec);
10010 	return err;
10011 }
10012 
10013 static int ca0132_codec_build_controls(struct hda_codec *codec)
10014 {
10015 	struct ca0132_spec *spec = codec->spec;
10016 
10017 	if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
10018 		return dbpro_build_controls(codec);
10019 	else
10020 		return ca0132_build_controls(codec);
10021 }
10022 
10023 static int ca0132_codec_build_pcms(struct hda_codec *codec)
10024 {
10025 	struct ca0132_spec *spec = codec->spec;
10026 
10027 	if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
10028 		return dbpro_build_pcms(codec);
10029 	else
10030 		return ca0132_build_pcms(codec);
10031 }
10032 
10033 static int ca0132_codec_init(struct hda_codec *codec)
10034 {
10035 	struct ca0132_spec *spec = codec->spec;
10036 
10037 	if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
10038 		return dbpro_init(codec);
10039 	else
10040 		return ca0132_init(codec);
10041 }
10042 
10043 static int ca0132_codec_suspend(struct hda_codec *codec)
10044 {
10045 	struct ca0132_spec *spec = codec->spec;
10046 
10047 	cancel_delayed_work_sync(&spec->unsol_hp_work);
10048 	return 0;
10049 }
10050 
10051 static const struct hda_codec_ops ca0132_codec_ops = {
10052 	.probe = ca0132_codec_probe,
10053 	.remove = ca0132_codec_remove,
10054 	.build_controls = ca0132_codec_build_controls,
10055 	.build_pcms = ca0132_codec_build_pcms,
10056 	.init = ca0132_codec_init,
10057 	.unsol_event = snd_hda_jack_unsol_event,
10058 	.suspend = ca0132_codec_suspend,
10059 };
10060 
10061 /*
10062  * driver entries
10063  */
10064 static const struct hda_device_id snd_hda_id_ca0132[] = {
10065 	HDA_CODEC_ID(0x11020011, "CA0132"),
10066 	{} /* terminator */
10067 };
10068 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
10069 
10070 MODULE_LICENSE("GPL");
10071 MODULE_DESCRIPTION("Creative Sound Core3D codec");
10072 
10073 static struct hda_codec_driver ca0132_driver = {
10074 	.id = snd_hda_id_ca0132,
10075 	.ops = &ca0132_codec_ops,
10076 };
10077 
10078 module_hda_codec_driver(ca0132_driver);
10079