1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2012-2022, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
5 */
6
7 #ifndef _MEI_INTERFACE_H_
8 #define _MEI_INTERFACE_H_
9
10 #include <linux/irqreturn.h>
11 #include <linux/pci.h>
12 #include <linux/mei.h>
13
14 #include "mei_dev.h"
15 #include "client.h"
16
17 /*
18 * mei_cfg - mei device configuration
19 *
20 * @fw_status: FW status
21 * @quirk_probe: device exclusion quirk
22 * @kind: MEI head kind
23 * @dma_size: device DMA buffers size
24 * @fw_ver_supported: is fw version retrievable from FW
25 * @hw_trc_supported: does the hw support trc register
26 */
27 struct mei_cfg {
28 const struct mei_fw_status fw_status;
29 bool (*quirk_probe)(const struct pci_dev *pdev);
30 const char *kind;
31 size_t dma_size[DMA_DSCR_NUM];
32 u32 fw_ver_supported:1;
33 u32 hw_trc_supported:1;
34 };
35
36 #define MEI_ME_RPM_TIMEOUT 500 /* ms */
37
38 /**
39 * struct mei_me_hw - me hw specific data
40 *
41 * @cfg: per device generation config and ops
42 * @mem_addr: io memory address
43 * @irq: irq number
44 * @pg_state: power gating state
45 * @d0i3_supported: di03 support
46 * @hbuf_depth: depth of hardware host/write buffer in slots
47 * @read_fws: read FW status register handler
48 * @polling_thread: interrupt polling thread
49 * @wait_active: the polling thread activity wait queue
50 * @is_active: the device is active
51 */
52 struct mei_me_hw {
53 const struct mei_cfg *cfg;
54 void __iomem *mem_addr;
55 int irq;
56 enum mei_pg_state pg_state;
57 bool d0i3_supported;
58 u8 hbuf_depth;
59 int (*read_fws)(const struct mei_device *dev, int where, const char *name, u32 *val);
60 /* polling */
61 struct task_struct *polling_thread;
62 wait_queue_head_t wait_active;
63 bool is_active;
64 };
65
66 #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
67
mei_me_hw_use_polling(const struct mei_me_hw * hw)68 static inline bool mei_me_hw_use_polling(const struct mei_me_hw *hw)
69 {
70 return hw->irq < 0;
71 }
72
73 /**
74 * enum mei_cfg_idx - indices to platform specific configurations.
75 *
76 * Note: has to be synchronized with mei_cfg_list[]
77 *
78 * @MEI_ME_UNDEF_CFG: Lower sentinel.
79 * @MEI_ME_ICH_CFG: I/O Controller Hub legacy devices.
80 * @MEI_ME_ICH10_CFG: I/O Controller Hub platforms Gen10
81 * @MEI_ME_PCH6_CFG: Platform Controller Hub platforms (Gen6).
82 * @MEI_ME_PCH7_CFG: Platform Controller Hub platforms (Gen7).
83 * @MEI_ME_PCH_CPT_PBG_CFG:Platform Controller Hub workstations
84 * with quirk for Node Manager exclusion.
85 * @MEI_ME_PCH8_CFG: Platform Controller Hub Gen8 and newer
86 * client platforms.
87 * @MEI_ME_PCH8_ITOUCH_CFG:Platform Controller Hub Gen8 and newer
88 * client platforms (iTouch).
89 * @MEI_ME_PCH8_SPS_4_CFG: Platform Controller Hub Gen8 and newer
90 * servers platforms with quirk for
91 * SPS firmware exclusion.
92 * @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer
93 * @MEI_ME_PCH12_SPS_4_CFG:Platform Controller Hub Gen12 up to 4.0
94 * servers platforms with quirk for
95 * SPS firmware exclusion.
96 * @MEI_ME_PCH12_SPS_CFG: Platform Controller Hub Gen12 5.0 and newer
97 * servers platforms with quirk for
98 * SPS firmware exclusion.
99 * @MEI_ME_PCH12_SPS_ITOUCH_CFG: Platform Controller Hub Gen12
100 * client platforms (iTouch)
101 * @MEI_ME_PCH15_CFG: Platform Controller Hub Gen15 and newer
102 * @MEI_ME_PCH15_SPS_CFG: Platform Controller Hub Gen15 and newer
103 * servers platforms with quirk for
104 * SPS firmware exclusion.
105 * @MEI_ME_GSC_CFG: Graphics System Controller
106 * @MEI_ME_GSCFI_CFG: Graphics System Controller Firmware Interface
107 * @MEI_ME_CSC_CFG: Chassis System Controller Firmware Interface
108 * @MEI_ME_NUM_CFG: Upper Sentinel.
109 */
110 enum mei_cfg_idx {
111 MEI_ME_UNDEF_CFG,
112 MEI_ME_ICH_CFG,
113 MEI_ME_ICH10_CFG,
114 MEI_ME_PCH6_CFG,
115 MEI_ME_PCH7_CFG,
116 MEI_ME_PCH_CPT_PBG_CFG,
117 MEI_ME_PCH8_CFG,
118 MEI_ME_PCH8_ITOUCH_CFG,
119 MEI_ME_PCH8_SPS_4_CFG,
120 MEI_ME_PCH12_CFG,
121 MEI_ME_PCH12_SPS_4_CFG,
122 MEI_ME_PCH12_SPS_CFG,
123 MEI_ME_PCH12_SPS_ITOUCH_CFG,
124 MEI_ME_PCH15_CFG,
125 MEI_ME_PCH15_SPS_CFG,
126 MEI_ME_GSC_CFG,
127 MEI_ME_GSCFI_CFG,
128 MEI_ME_CSC_CFG,
129 MEI_ME_NUM_CFG,
130 };
131
132 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx);
133
134 struct mei_device *mei_me_dev_init(struct device *parent,
135 const struct mei_cfg *cfg, bool slow_fw);
136
137 int mei_me_pg_enter_sync(struct mei_device *dev);
138 int mei_me_pg_exit_sync(struct mei_device *dev);
139
140 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id);
141 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id);
142 int mei_me_polling_thread(void *_dev);
143
144 #endif /* _MEI_INTERFACE_H_ */
145