xref: /freebsd/sys/dev/qlxgbe/ql_hw.h (revision 95ee2897e98f5d444f26ed2334cc7c439f9c16c6)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2013-2016 Qlogic Corporation
5  * All rights reserved.
6  *
7  *  Redistribution and use in source and binary forms, with or without
8  *  modification, are permitted provided that the following conditions
9  *  are met:
10  *
11  *  1. Redistributions of source code must retain the above copyright
12  *     notice, this list of conditions and the following disclaimer.
13  *  2. Redistributions in binary form must reproduce the above copyright
14  *     notice, this list of conditions and the following disclaimer in the
15  *     documentation and/or other materials provided with the distribution.
16  *
17  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27  *  POSSIBILITY OF SUCH DAMAGE.
28  */
29 /*
30  * File: ql_hw.h
31  * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
32  */
33 #ifndef _QL_HW_H_
34 #define _QL_HW_H_
35 
36 /*
37  * PCIe Registers; Direct Mapped; Offsets from BAR0
38  */
39 
40 /*
41  * Register offsets for QLE8030
42  */
43 
44 /*
45  * Firmware Mailbox Registers
46  *	0 thru 511; offsets 0x800 thru 0xFFC; 32bits each
47  */
48 #define Q8_FW_MBOX0			0x00000800
49 #define Q8_FW_MBOX511			0x00000FFC
50 
51 /*
52  * Host Mailbox Registers
53  *	0 thru 511; offsets 0x000 thru 0x7FC; 32bits each
54  */
55 #define Q8_HOST_MBOX0			0x00000000
56 #define Q8_HOST_MBOX511			0x000007FC
57 
58 #define Q8_MBOX_INT_ENABLE		0x00001000
59 #define Q8_MBOX_INT_MASK_MSIX		0x00001200
60 #define Q8_MBOX_INT_LEGACY		0x00003010
61 
62 #define Q8_HOST_MBOX_CNTRL		0x00003038
63 #define Q8_FW_MBOX_CNTRL		0x0000303C
64 
65 #define Q8_PEG_HALT_STATUS1		0x000034A8
66 #define Q8_PEG_HALT_STATUS2		0x000034AC
67 #define Q8_FIRMWARE_HEARTBEAT		0x000034B0
68 
69 #define Q8_FLASH_LOCK_ID		0x00003500
70 #define Q8_DRIVER_LOCK_ID		0x00003504
71 #define Q8_FW_CAPABILITIES		0x00003528
72 
73 #define Q8_FW_VER_MAJOR			0x00003550
74 #define Q8_FW_VER_MINOR			0x00003554
75 #define Q8_FW_VER_SUB			0x00003558
76 
77 #define Q8_BOOTLD_ADDR			0x0000355C
78 #define Q8_BOOTLD_SIZE			0x00003560
79 
80 #define Q8_FW_IMAGE_ADDR		0x00003564
81 #define Q8_FW_BUILD_NUMBER		0x00003568
82 #define Q8_FW_IMAGE_VALID		0x000035FC
83 
84 #define Q8_CMDPEG_STATE			0x00003650
85 
86 #define Q8_LINK_STATE			0x00003698
87 #define Q8_LINK_STATE_2			0x0000369C
88 
89 #define Q8_LINK_SPEED_0			0x000036E0
90 #define Q8_LINK_SPEED_1			0x000036E4
91 #define Q8_LINK_SPEED_2			0x000036E8
92 #define Q8_LINK_SPEED_3			0x000036EC
93 
94 #define Q8_MAX_LINK_SPEED_0		0x000036F0
95 #define Q8_MAX_LINK_SPEED_1		0x000036F4
96 #define Q8_MAX_LINK_SPEED_2		0x000036F8
97 #define Q8_MAX_LINK_SPEED_3		0x000036FC
98 
99 #define Q8_ASIC_TEMPERATURE		0x000037B4
100 
101 /*
102  * CRB Window Registers
103  *	0 thru 15; offsets 0x3800 thru 0x383C; 32bits each
104  */
105 #define Q8_CRB_WINDOW_PF0		0x00003800
106 #define Q8_CRB_WINDOW_PF15		0x0000383C
107 
108 #define Q8_FLASH_LOCK			0x00003850
109 #define Q8_FLASH_UNLOCK			0x00003854
110 
111 #define Q8_DRIVER_LOCK			0x00003868
112 #define Q8_DRIVER_UNLOCK		0x0000386C
113 
114 #define Q8_LEGACY_INT_PTR		0x000038C0
115 #define Q8_LEGACY_INT_TRIG		0x000038C4
116 #define Q8_LEGACY_INT_MASK		0x000038C8
117 
118 #define Q8_WILD_CARD			0x000038F0
119 #define Q8_INFORMANT			0x000038FC
120 
121 /*
122  * Ethernet Interface Specific Registers
123  */
124 #define Q8_DRIVER_OP_MODE		0x00003570
125 #define Q8_API_VERSION			0x0000356C
126 #define Q8_NPAR_STATE			0x0000359C
127 
128 /*
129  * End of PCIe Registers; Direct Mapped; Offsets from BAR0
130  */
131 
132 /*
133  * Indirect Registers
134  */
135 #define Q8_LED_DUAL_0			0x28084C80
136 #define Q8_LED_SINGLE_0			0x28084C90
137 
138 #define Q8_LED_DUAL_1			0x28084CA0
139 #define Q8_LED_SINGLE_1			0x28084CB0
140 
141 #define Q8_LED_DUAL_2			0x28084CC0
142 #define Q8_LED_SINGLE_2			0x28084CD0
143 
144 #define Q8_LED_DUAL_3			0x28084CE0
145 #define Q8_LED_SINGLE_3			0x28084CF0
146 
147 #define Q8_GPIO_1			0x28084D00
148 #define Q8_GPIO_2			0x28084D10
149 #define Q8_GPIO_3			0x28084D20
150 #define Q8_GPIO_4			0x28084D40
151 #define Q8_GPIO_5			0x28084D50
152 #define Q8_GPIO_6			0x28084D60
153 #define Q8_GPIO_7			0x42100060
154 #define Q8_GPIO_8			0x42100064
155 
156 #define Q8_FLASH_SPI_STATUS		0x2808E010
157 #define Q8_FLASH_SPI_CONTROL		0x2808E014
158 
159 #define Q8_FLASH_STATUS			0x42100004
160 #define Q8_FLASH_CONTROL		0x42110004
161 #define Q8_FLASH_ADDRESS		0x42110008
162 #define Q8_FLASH_WR_DATA		0x4211000C
163 #define Q8_FLASH_RD_DATA		0x42110018
164 
165 #define Q8_FLASH_DIRECT_WINDOW		0x42110030
166 #define Q8_FLASH_DIRECT_DATA		0x42150000
167 
168 #define Q8_MS_CNTRL			0x41000090
169 
170 #define Q8_MS_ADDR_LO			0x41000094
171 #define Q8_MS_ADDR_HI			0x41000098
172 
173 #define Q8_MS_WR_DATA_0_31		0x410000A0
174 #define Q8_MS_WR_DATA_32_63		0x410000A4
175 #define Q8_MS_WR_DATA_64_95		0x410000B0
176 #define Q8_MS_WR_DATA_96_127		0x410000B4
177 
178 #define Q8_MS_RD_DATA_0_31		0x410000A8
179 #define Q8_MS_RD_DATA_32_63		0x410000AC
180 #define Q8_MS_RD_DATA_64_95		0x410000B8
181 #define Q8_MS_RD_DATA_96_127		0x410000BC
182 
183 #define Q8_CRB_PEG_0			0x3400003c
184 #define Q8_CRB_PEG_1			0x3410003c
185 #define Q8_CRB_PEG_2			0x3420003c
186 #define Q8_CRB_PEG_3			0x3430003c
187 #define Q8_CRB_PEG_4			0x34B0003c
188 
189 /*
190  * Macros for reading and writing registers
191  */
192 
193 #if defined(__i386__) || defined(__amd64__)
194 #define Q8_MB()    __asm volatile("mfence" ::: "memory")
195 #define Q8_WMB()   __asm volatile("sfence" ::: "memory")
196 #define Q8_RMB()   __asm volatile("lfence" ::: "memory")
197 #else
198 #define Q8_MB()
199 #define Q8_WMB()
200 #define Q8_RMB()
201 #endif
202 
203 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)
204 
205 #define WRITE_REG32(ha, reg, val) \
206 	{\
207 		bus_write_4((ha->pci_reg), reg, val);\
208 		bus_read_4((ha->pci_reg), reg);\
209 	}
210 
211 #define Q8_NUM_MBOX	512
212 
213 #define Q8_MAX_NUM_MULTICAST_ADDRS	1022
214 #define Q8_MAC_ADDR_LEN			6
215 
216 /*
217  * Firmware Interface
218  */
219 
220 /*
221  * Command Response Interface - Commands
222  */
223 
224 #define Q8_MBX_CONFIG_IP_ADDRESS		0x0001
225 #define Q8_MBX_CONFIG_INTR			0x0002
226 #define Q8_MBX_MAP_INTR_SRC			0x0003
227 #define Q8_MBX_MAP_SDS_TO_RDS			0x0006
228 #define Q8_MBX_CREATE_RX_CNTXT			0x0007
229 #define Q8_MBX_DESTROY_RX_CNTXT			0x0008
230 #define Q8_MBX_CREATE_TX_CNTXT			0x0009
231 #define Q8_MBX_DESTROY_TX_CNTXT			0x000A
232 #define Q8_MBX_ADD_RX_RINGS			0x000B
233 #define Q8_MBX_CONFIG_LRO_FLOW			0x000C
234 #define Q8_MBX_CONFIG_MAC_LEARNING		0x000D
235 #define Q8_MBX_GET_STATS			0x000F
236 #define Q8_MBX_GENERATE_INTR			0x0011
237 #define Q8_MBX_SET_MAX_MTU			0x0012
238 #define Q8_MBX_MAC_ADDR_CNTRL			0x001F
239 #define Q8_MBX_GET_PCI_CONFIG			0x0020
240 #define Q8_MBX_GET_NIC_PARTITION		0x0021
241 #define Q8_MBX_SET_NIC_PARTITION		0x0022
242 #define Q8_MBX_QUERY_WOL_CAP			0x002C
243 #define Q8_MBX_SET_WOL_CONFIG			0x002D
244 #define Q8_MBX_GET_MINIDUMP_TMPLT_SIZE		0x002F
245 #define Q8_MBX_GET_MINIDUMP_TMPLT		0x0030
246 #define Q8_MBX_GET_FW_DCBX_CAPS			0x0034
247 #define Q8_MBX_QUERY_DCBX_SETTINGS		0x0035
248 #define Q8_MBX_CONFIG_RSS			0x0041
249 #define Q8_MBX_CONFIG_RSS_TABLE			0x0042
250 #define Q8_MBX_CONFIG_INTR_COALESCE		0x0043
251 #define Q8_MBX_CONFIG_LED			0x0044
252 #define Q8_MBX_CONFIG_MAC_ADDR			0x0045
253 #define Q8_MBX_CONFIG_STATISTICS		0x0046
254 #define Q8_MBX_CONFIG_LOOPBACK			0x0047
255 #define Q8_MBX_LINK_EVENT_REQ			0x0048
256 #define Q8_MBX_CONFIG_MAC_RX_MODE		0x0049
257 #define Q8_MBX_CONFIG_FW_LRO			0x004A
258 #define Q8_MBX_HW_CONFIG			0x004C
259 #define Q8_MBX_INIT_NIC_FUNC			0x0060
260 #define Q8_MBX_STOP_NIC_FUNC			0x0061
261 #define Q8_MBX_IDC_REQ				0x0062
262 #define Q8_MBX_IDC_ACK				0x0063
263 #define Q8_MBX_SET_PORT_CONFIG			0x0066
264 #define Q8_MBX_GET_PORT_CONFIG			0x0067
265 #define Q8_MBX_GET_LINK_STATUS			0x0068
266 
267 /*
268  * Mailbox Command Response
269  */
270 #define Q8_MBX_RSP_SUCCESS			0x0001
271 #define Q8_MBX_RSP_RESPONSE_FAILURE		0x0002
272 #define Q8_MBX_RSP_NO_CARD_CRB			0x0003
273 #define Q8_MBX_RSP_NO_CARD_MEM			0x0004
274 #define Q8_MBX_RSP_NO_CARD_RSRC			0x0005
275 #define Q8_MBX_RSP_INVALID_ARGS			0x0006
276 #define Q8_MBX_RSP_INVALID_ACTION		0x0007
277 #define Q8_MBX_RSP_INVALID_STATE		0x0008
278 #define Q8_MBX_RSP_NOT_SUPPORTED		0x0009
279 #define Q8_MBX_RSP_NOT_PERMITTED		0x000A
280 #define Q8_MBX_RSP_NOT_READY			0x000B
281 #define Q8_MBX_RSP_DOES_NOT_EXIST		0x000C
282 #define Q8_MBX_RSP_ALREADY_EXISTS		0x000D
283 #define Q8_MBX_RSP_BAD_SIGNATURE		0x000E
284 #define Q8_MBX_RSP_CMD_NOT_IMPLEMENTED		0x000F
285 #define Q8_MBX_RSP_CMD_INVALID			0x0010
286 #define Q8_MBX_RSP_TIMEOUT			0x0011
287 #define Q8_MBX_RSP_CMD_FAILED			0x0012
288 #define Q8_MBX_RSP_FATAL_TEMP			0x0013
289 #define Q8_MBX_RSP_MAX_EXCEEDED			0x0014
290 #define Q8_MBX_RSP_UNSPECIFIED			0x0015
291 #define Q8_MBX_RSP_INTR_CREATE_FAILED		0x0017
292 #define Q8_MBX_RSP_INTR_DELETE_FAILED		0x0018
293 #define Q8_MBX_RSP_INTR_INVALID_OP		0x0019
294 #define Q8_MBX_RSP_IDC_INTRMD_RSP		0x001A
295 
296 #define Q8_MBX_CMD_VERSION	(0x2 << 13)
297 #define Q8_MBX_RSP_STATUS(x) (((!(x >> 9)) || ((x >> 9) == 1)) ? 0: (x >> 9))
298 /*
299  * Configure IP Address
300  */
301 typedef struct _q80_config_ip_addr {
302 	uint16_t	opcode;
303 	uint16_t 	count_version;
304 
305 	uint8_t		cmd;
306 #define		Q8_MBX_CONFIG_IP_ADD_IP	0x1
307 #define		Q8_MBX_CONFIG_IP_DEL_IP	0x2
308 
309 	uint8_t		ip_type;
310 #define		Q8_MBX_CONFIG_IP_V4	0x0
311 #define		Q8_MBX_CONFIG_IP_V6	0x1
312 
313 	uint16_t	rsrvd;
314 	union {
315 		struct {
316 			uint32_t addr;
317 			uint32_t rsrvd[3];
318 		} ipv4;
319 		uint8_t	ipv6_addr[16];
320 	} u;
321 } __packed q80_config_ip_addr_t;
322 
323 typedef struct _q80_config_ip_addr_rsp {
324         uint16_t	opcode;
325         uint16_t	regcnt_status;
326 } __packed q80_config_ip_addr_rsp_t;
327 
328 /*
329  * Configure Interrupt Command
330  */
331 typedef struct _q80_intr {
332 	uint8_t		cmd_type;
333 #define		Q8_MBX_CONFIG_INTR_CREATE	0x1
334 #define		Q8_MBX_CONFIG_INTR_DELETE	0x2
335 #define		Q8_MBX_CONFIG_INTR_TYPE_LINE	(0x1 << 4)
336 #define		Q8_MBX_CONFIG_INTR_TYPE_MSI_X	(0x3 << 4)
337 
338 	uint8_t		rsrvd;
339 	uint16_t	msix_index;
340 } __packed q80_intr_t;
341 
342 #define Q8_MAX_INTR_VECTORS	16
343 typedef struct _q80_config_intr {
344 	uint16_t	opcode;
345 	uint16_t 	count_version;
346 	uint8_t		nentries;
347 	uint8_t		rsrvd[3];
348 	q80_intr_t	intr[Q8_MAX_INTR_VECTORS];
349 } __packed q80_config_intr_t;
350 
351 typedef struct _q80_intr_rsp {
352 	uint8_t		status;
353 	uint8_t		cmd;
354 	uint16_t	intr_id;
355 	uint32_t	intr_src;
356 } q80_intr_rsp_t;
357 
358 typedef struct _q80_config_intr_rsp {
359         uint16_t	opcode;
360         uint16_t	regcnt_status;
361 	uint8_t		nentries;
362 	uint8_t		rsrvd[3];
363 	q80_intr_rsp_t	intr[Q8_MAX_INTR_VECTORS];
364 } __packed q80_config_intr_rsp_t;
365 
366 /*
367  * Configure LRO Flow Command
368  */
369 typedef struct _q80_config_lro_flow {
370 	uint16_t	opcode;
371 	uint16_t 	count_version;
372 
373 	uint8_t		cmd;
374 #define Q8_MBX_CONFIG_LRO_FLOW_ADD	0x01
375 #define Q8_MBX_CONFIG_LRO_FLOW_DELETE	0x02
376 
377 	uint8_t		type_ts;
378 #define Q8_MBX_CONFIG_LRO_FLOW_IPV4		0x00
379 #define Q8_MBX_CONFIG_LRO_FLOW_IPV6		0x01
380 #define Q8_MBX_CONFIG_LRO_FLOW_TS_ABSENT	0x00
381 #define Q8_MBX_CONFIG_LRO_FLOW_TS_PRESENT	0x02
382 
383 	uint16_t	rsrvd;
384 	union {
385 		struct {
386 			uint32_t addr;
387 			uint32_t rsrvd[3];
388 		} ipv4;
389 		uint8_t	ipv6_addr[16];
390 	} dst;
391 	union {
392 		struct {
393 			uint32_t addr;
394 			uint32_t rsrvd[3];
395 		} ipv4;
396 		uint8_t	ipv6_addr[16];
397 	} src;
398 	uint16_t	dst_port;
399 	uint16_t	src_port;
400 } __packed q80_config_lro_flow_t;
401 
402 typedef struct _q80_config_lro_flow_rsp {
403         uint16_t	opcode;
404         uint16_t	regcnt_status;
405 } __packed q80_config_lro_flow_rsp_t;
406 
407 typedef struct _q80_set_max_mtu {
408 	uint16_t	opcode;
409 	uint16_t 	count_version;
410 	uint32_t	cntxt_id;
411 	uint32_t	mtu;
412 } __packed q80_set_max_mtu_t;
413 
414 typedef struct _q80_set_max_mtu_rsp {
415         uint16_t	opcode;
416         uint16_t	regcnt_status;
417 } __packed q80_set_max_mtu_rsp_t;
418 
419 /*
420  * Configure RSS
421  */
422 typedef struct _q80_config_rss {
423 	uint16_t	opcode;
424 	uint16_t 	count_version;
425 
426 	uint16_t	cntxt_id;
427 	uint16_t	rsrvd;
428 
429 	uint8_t		hash_type;
430 #define Q8_MBX_RSS_HASH_TYPE_IPV4_IP		(0x1 << 4)
431 #define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP		(0x2 << 4)
432 #define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP	(0x3 << 4)
433 #define Q8_MBX_RSS_HASH_TYPE_IPV6_IP		(0x1 << 6)
434 #define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP		(0x2 << 6)
435 #define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP	(0x3 << 6)
436 
437 	uint8_t		flags;
438 #define Q8_MBX_RSS_FLAGS_ENABLE_RSS		(0x1)
439 #define Q8_MBX_RSS_FLAGS_USE_IND_TABLE		(0x2)
440 #define Q8_MBX_RSS_FLAGS_TYPE_CRSS		(0x4)
441 
442 	uint16_t	indtbl_mask;
443 #define Q8_MBX_RSS_INDTBL_MASK			0x7F
444 #define Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID	0x8000
445 
446 	uint32_t	multi_rss;
447 #define Q8_MBX_RSS_MULTI_RSS_ENGINE_ASSIGN	BIT_30
448 #define Q8_MBX_RSS_USE_MULTI_RSS_ENGINES	BIT_31
449 
450 	uint64_t	rss_key[5];
451 } __packed q80_config_rss_t;
452 
453 typedef struct _q80_config_rss_rsp {
454         uint16_t	opcode;
455         uint16_t	regcnt_status;
456 } __packed q80_config_rss_rsp_t;
457 
458 /*
459  * Configure RSS Indirection Table
460  */
461 #define Q8_RSS_IND_TBL_SIZE	40
462 #define Q8_RSS_IND_TBL_MIN_IDX	0
463 #define Q8_RSS_IND_TBL_MAX_IDX	127
464 
465 typedef struct _q80_config_rss_ind_table {
466 	uint16_t	opcode;
467 	uint16_t 	count_version;
468 	uint8_t		start_idx;
469 	uint8_t		end_idx;
470 	uint16_t 	cntxt_id;
471 	uint8_t		ind_table[Q8_RSS_IND_TBL_SIZE];
472 } __packed q80_config_rss_ind_table_t;
473 
474 typedef struct _q80_config_rss_ind_table_rsp {
475         uint16_t	opcode;
476         uint16_t	regcnt_status;
477 } __packed q80_config_rss_ind_table_rsp_t;
478 
479 /*
480  * Configure Interrupt Coalescing and Generation
481  */
482 typedef struct _q80_config_intr_coalesc {
483 	uint16_t	opcode;
484 	uint16_t 	count_version;
485         uint16_t	flags;
486 #define Q8_MBX_INTRC_FLAGS_RCV		1
487 #define Q8_MBX_INTRC_FLAGS_XMT		2
488 #define Q8_MBX_INTRC_FLAGS_PERIODIC	(1 << 3)
489 
490         uint16_t	cntxt_id;
491         uint16_t	max_pkts;
492         uint16_t	max_mswait;
493         uint8_t		timer_type;
494 #define Q8_MBX_INTRC_TIMER_NONE			0
495 #define Q8_MBX_INTRC_TIMER_SINGLE		1
496 #define Q8_MBX_INTRC_TIMER_PERIODIC		2
497 
498         uint16_t	sds_ring_mask;
499 
500         uint8_t		rsrvd;
501         uint32_t	ms_timeout;
502 } __packed q80_config_intr_coalesc_t;
503 
504 typedef struct _q80_config_intr_coalesc_rsp {
505         uint16_t	opcode;
506         uint16_t	regcnt_status;
507 } __packed q80_config_intr_coalesc_rsp_t;
508 
509 /*
510  * Configure MAC Address
511  */
512 #define Q8_ETHER_ADDR_LEN		6
513 typedef struct _q80_mac_addr {
514 	uint8_t		addr[Q8_ETHER_ADDR_LEN];
515 	uint16_t	vlan_tci;
516 } __packed q80_mac_addr_t;
517 
518 #define Q8_MAX_MAC_ADDRS	64
519 
520 typedef struct _q80_config_mac_addr {
521 	uint16_t	opcode;
522 	uint16_t 	count_version;
523 	uint8_t		cmd;
524 #define Q8_MBX_CMAC_CMD_ADD_MAC_ADDR	1
525 #define Q8_MBX_CMAC_CMD_DEL_MAC_ADDR	2
526 
527 #define Q8_MBX_CMAC_CMD_CAM_BOTH	(0x0 << 6)
528 #define Q8_MBX_CMAC_CMD_CAM_INGRESS	(0x1 << 6)
529 #define Q8_MBX_CMAC_CMD_CAM_EGRESS	(0x2 << 6)
530 
531 	uint8_t		nmac_entries;
532 	uint16_t	cntxt_id;
533 	q80_mac_addr_t	mac_addr[Q8_MAX_MAC_ADDRS];
534 } __packed q80_config_mac_addr_t;
535 
536 typedef struct _q80_config_mac_addr_rsp {
537         uint16_t	opcode;
538         uint16_t	regcnt_status;
539 	uint8_t		cmd;
540 	uint8_t		nmac_entries;
541 	uint16_t	cntxt_id;
542 	uint32_t	status[Q8_MAX_MAC_ADDRS];
543 } __packed q80_config_mac_addr_rsp_t;
544 
545 /*
546  * Configure MAC Receive Mode
547  */
548 typedef struct _q80_config_mac_rcv_mode {
549 	uint16_t	opcode;
550 	uint16_t 	count_version;
551 
552 	uint8_t		mode;
553 #define Q8_MBX_MAC_RCV_PROMISC_ENABLE	0x1
554 #define Q8_MBX_MAC_ALL_MULTI_ENABLE	0x2
555 
556 	uint8_t		rsrvd;
557 	uint16_t	cntxt_id;
558 } __packed q80_config_mac_rcv_mode_t;
559 
560 typedef struct _q80_config_mac_rcv_mode_rsp {
561         uint16_t	opcode;
562         uint16_t	regcnt_status;
563 } __packed q80_config_mac_rcv_mode_rsp_t;
564 
565 /*
566  * Configure Firmware Controlled LRO
567  */
568 typedef struct _q80_config_fw_lro {
569 	uint16_t	opcode;
570 	uint16_t 	count_version;
571 
572 	uint8_t		flags;
573 #define Q8_MBX_FW_LRO_IPV4                     0x1
574 #define Q8_MBX_FW_LRO_IPV6                     0x2
575 #define Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK       0x4
576 #define Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK       0x8
577 #define Q8_MBX_FW_LRO_LOW_THRESHOLD            0x10
578 
579 	uint8_t		rsrvd;
580 	uint16_t	cntxt_id;
581 
582 	uint16_t	low_threshold;
583 	uint16_t	rsrvd0;
584 } __packed q80_config_fw_lro_t;
585 
586 typedef struct _q80_config_fw_lro_rsp {
587         uint16_t	opcode;
588         uint16_t	regcnt_status;
589 } __packed q80_config_fw_lro_rsp_t;
590 
591 /*
592  * Minidump mailbox commands
593  */
594 typedef struct _q80_config_md_templ_size {
595 	uint16_t	opcode;
596 	uint16_t	count_version;
597 } __packed q80_config_md_templ_size_t;
598 
599 typedef struct _q80_config_md_templ_size_rsp {
600 	uint16_t	opcode;
601 	uint16_t	regcnt_status;
602 	uint32_t	rsrvd;
603 	uint32_t	templ_size;
604 	uint32_t	templ_version;
605 } __packed q80_config_md_templ_size_rsp_t;
606 
607 typedef struct _q80_config_md_templ_cmd {
608 	uint16_t	opcode;
609 	uint16_t	count_version;
610 	uint64_t	buf_addr; /* physical address of buffer */
611 	uint32_t	buff_size;
612 	uint32_t	offset;
613 } __packed q80_config_md_templ_cmd_t;
614 
615 typedef struct _q80_config_md_templ_cmd_rsp {
616 	uint16_t	opcode;
617 	uint16_t	regcnt_status;
618 	uint32_t	rsrvd;
619 	uint32_t	templ_size;
620 	uint32_t	buff_size;
621 	uint32_t	offset;
622 } __packed q80_config_md_templ_cmd_rsp_t;
623 
624 /*
625  * Hardware Configuration Commands
626  */
627 
628 typedef struct _q80_hw_config {
629        uint16_t        opcode;
630        uint16_t        count_version;
631 #define Q8_HW_CONFIG_SET_MDIO_REG_COUNT                0x06
632 #define Q8_HW_CONFIG_GET_MDIO_REG_COUNT                0x05
633 #define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT 0x03
634 #define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT 0x02
635 #define Q8_HW_CONFIG_SET_TEMP_THRESHOLD_COUNT  0x03
636 #define Q8_HW_CONFIG_GET_TEMP_THRESHOLD_COUNT  0x02
637 #define Q8_HW_CONFIG_GET_ECC_COUNTS_COUNT      0x02
638 
639        uint32_t        cmd;
640 #define Q8_HW_CONFIG_SET_MDIO_REG              0x01
641 #define Q8_HW_CONFIG_GET_MDIO_REG              0x02
642 #define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE       0x03
643 #define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE       0x04
644 #define Q8_HW_CONFIG_SET_TEMP_THRESHOLD                0x07
645 #define Q8_HW_CONFIG_GET_TEMP_THRESHOLD                0x08
646 #define Q8_HW_CONFIG_GET_ECC_COUNTS            0x0A
647 
648        union {
649                struct {
650                        uint32_t phys_port_number;
651                        uint32_t phy_dev_addr;
652                        uint32_t reg_addr;
653                        uint32_t data;
654                } set_mdio;
655 
656                struct {
657                        uint32_t phys_port_number;
658                        uint32_t phy_dev_addr;
659                        uint32_t reg_addr;
660                } get_mdio;
661 
662                struct {
663                        uint32_t mode;
664 #define Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL  0x1
665 #define Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO      0x2
666 
667                } set_cam_search_mode;
668 
669                struct {
670                        uint32_t value;
671                } set_temp_threshold;
672        } u;
673 } __packed q80_hw_config_t;
674 
675 typedef struct _q80_hw_config_rsp {
676         uint16_t       opcode;
677         uint16_t       regcnt_status;
678 
679        union {
680                struct {
681                        uint32_t value;
682                } get_mdio;
683 
684                struct {
685                        uint32_t mode;
686                } get_cam_search_mode;
687 
688                struct {
689                        uint32_t temp_warn;
690                        uint32_t curr_temp;
691                        uint32_t osc_ring_rate;
692                        uint32_t core_voltage;
693                } get_temp_threshold;
694 
695                struct {
696                        uint32_t ddr_ecc_error_count;
697                        uint32_t ocm_ecc_error_count;
698                        uint32_t l2_dcache_ecc_error_count;
699                        uint32_t l2_icache_ecc_error_count;
700                        uint32_t eport_ecc_error_count;
701                } get_ecc_counts;
702        } u;
703 } __packed q80_hw_config_rsp_t;
704 
705 /*
706  * Link Event Request Command
707  */
708 typedef struct _q80_link_event {
709 	uint16_t	opcode;
710 	uint16_t 	count_version;
711 	uint8_t		cmd;
712 #define Q8_LINK_EVENT_CMD_STOP_PERIODIC	0
713 #define Q8_LINK_EVENT_CMD_ENABLE_ASYNC	1
714 
715 	uint8_t		flags;
716 #define Q8_LINK_EVENT_FLAGS_SEND_RSP	1
717 
718 	uint16_t	cntxt_id;
719 } __packed q80_link_event_t;
720 
721 typedef struct _q80_link_event_rsp {
722         uint16_t	opcode;
723         uint16_t	regcnt_status;
724 } __packed q80_link_event_rsp_t;
725 
726 /*
727  * Get Statistics Command
728  */
729 typedef struct _q80_rcv_stats {
730 	uint64_t	total_bytes;
731 	uint64_t	total_pkts;
732 	uint64_t	lro_pkt_count;
733 	uint64_t	sw_pkt_count;
734 	uint64_t	ip_chksum_err;
735 	uint64_t	pkts_wo_acntxts;
736 	uint64_t	pkts_dropped_no_sds_card;
737 	uint64_t	pkts_dropped_no_sds_host;
738 	uint64_t	oversized_pkts;
739 	uint64_t	pkts_dropped_no_rds;
740 	uint64_t	unxpctd_mcast_pkts;
741 	uint64_t	re1_fbq_error;
742 	uint64_t	invalid_mac_addr;
743 	uint64_t	rds_prime_trys;
744 	uint64_t	rds_prime_success;
745 	uint64_t	lro_flows_added;
746 	uint64_t	lro_flows_deleted;
747 	uint64_t	lro_flows_active;
748 	uint64_t	pkts_droped_unknown;
749 	uint64_t	pkts_cnt_oversized;
750 } __packed q80_rcv_stats_t;
751 
752 typedef struct _q80_xmt_stats {
753 	uint64_t	total_bytes;
754 	uint64_t	total_pkts;
755 	uint64_t	errors;
756 	uint64_t	pkts_dropped;
757 	uint64_t	switch_pkts;
758 	uint64_t	num_buffers;
759 } __packed q80_xmt_stats_t;
760 
761 typedef struct _q80_mac_stats {
762 	uint64_t	xmt_frames;
763 	uint64_t	xmt_bytes;
764 	uint64_t	xmt_mcast_pkts;
765 	uint64_t	xmt_bcast_pkts;
766 	uint64_t	xmt_pause_frames;
767 	uint64_t	xmt_cntrl_pkts;
768 	uint64_t	xmt_pkt_lt_64bytes;
769 	uint64_t	xmt_pkt_lt_127bytes;
770 	uint64_t	xmt_pkt_lt_255bytes;
771 	uint64_t	xmt_pkt_lt_511bytes;
772 	uint64_t	xmt_pkt_lt_1023bytes;
773 	uint64_t	xmt_pkt_lt_1518bytes;
774 	uint64_t	xmt_pkt_gt_1518bytes;
775 	uint64_t	rsrvd0[3];
776 	uint64_t	rcv_frames;
777 	uint64_t	rcv_bytes;
778 	uint64_t	rcv_mcast_pkts;
779 	uint64_t	rcv_bcast_pkts;
780 	uint64_t	rcv_pause_frames;
781 	uint64_t	rcv_cntrl_pkts;
782 	uint64_t	rcv_pkt_lt_64bytes;
783 	uint64_t	rcv_pkt_lt_127bytes;
784 	uint64_t	rcv_pkt_lt_255bytes;
785 	uint64_t	rcv_pkt_lt_511bytes;
786 	uint64_t	rcv_pkt_lt_1023bytes;
787 	uint64_t	rcv_pkt_lt_1518bytes;
788 	uint64_t	rcv_pkt_gt_1518bytes;
789 	uint64_t	rsrvd1[3];
790 	uint64_t	rcv_len_error;
791 	uint64_t	rcv_len_small;
792 	uint64_t	rcv_len_large;
793 	uint64_t	rcv_jabber;
794 	uint64_t	rcv_dropped;
795 	uint64_t	fcs_error;
796 	uint64_t	align_error;
797 	uint64_t	eswitched_frames;
798 	uint64_t	eswitched_bytes;
799 	uint64_t	eswitched_mcast_frames;
800 	uint64_t	eswitched_bcast_frames;
801 	uint64_t	eswitched_ucast_frames;
802 	uint64_t	eswitched_err_free_frames;
803 	uint64_t	eswitched_err_free_bytes;
804 } __packed q80_mac_stats_t;
805 
806 typedef struct _q80_get_stats {
807 	uint16_t	opcode;
808 	uint16_t 	count_version;
809 
810 	uint32_t 	cmd;
811 #define Q8_GET_STATS_CMD_CLEAR		0x01
812 #define Q8_GET_STATS_CMD_RCV		0x00
813 #define Q8_GET_STATS_CMD_XMT		0x02
814 #define Q8_GET_STATS_CMD_TYPE_CNTXT	0x00
815 #define Q8_GET_STATS_CMD_TYPE_MAC	0x04
816 #define Q8_GET_STATS_CMD_TYPE_FUNC	0x08
817 #define Q8_GET_STATS_CMD_TYPE_VPORT	0x0C
818 #define Q8_GET_STATS_CMD_TYPE_ALL      (0x7 << 2)
819 
820 } __packed q80_get_stats_t;
821 
822 typedef struct _q80_get_stats_rsp {
823         uint16_t	opcode;
824         uint16_t	regcnt_status;
825 	uint32_t 	cmd;
826 	union {
827 		q80_rcv_stats_t rcv;
828 		q80_xmt_stats_t xmt;
829 		q80_mac_stats_t mac;
830 	} u;
831 } __packed q80_get_stats_rsp_t;
832 
833 typedef struct _q80_get_mac_rcv_xmt_stats_rsp {
834 	uint16_t	opcode;
835 	uint16_t	regcnt_status;
836 	uint32_t	cmd;
837 	q80_mac_stats_t mac;
838 	q80_rcv_stats_t rcv;
839 	q80_xmt_stats_t xmt;
840 } __packed q80_get_mac_rcv_xmt_stats_rsp_t;
841 
842 /*
843  * Init NIC Function
844  * Used to Register DCBX Configuration Change AEN
845  */
846 typedef struct _q80_init_nic_func {
847         uint16_t        opcode;
848         uint16_t        count_version;
849 
850         uint32_t        options;
851 #define Q8_INIT_NIC_REG_IDC_AEN		0x01
852 #define Q8_INIT_NIC_REG_DCBX_CHNG_AEN	0x02
853 #define Q8_INIT_NIC_REG_SFP_CHNG_AEN	0x04
854 
855 } __packed q80_init_nic_func_t;
856 
857 typedef struct _q80_init_nic_func_rsp {
858         uint16_t        opcode;
859         uint16_t        regcnt_status;
860 } __packed q80_init_nic_func_rsp_t;
861 
862 /*
863  * Stop NIC Function
864  * Used to DeRegister DCBX Configuration Change AEN
865  */
866 typedef struct _q80_stop_nic_func {
867         uint16_t        opcode;
868         uint16_t        count_version;
869 
870         uint32_t        options;
871 #define Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN 0x02
872 #define Q8_STOP_NIC_DEREG_SFP_CHNG_AEN	0x04
873 
874 } __packed q80_stop_nic_func_t;
875 
876 typedef struct _q80_stop_nic_func_rsp {
877         uint16_t        opcode;
878         uint16_t        regcnt_status;
879 } __packed q80_stop_nic_func_rsp_t;
880 
881 /*
882  * Query Firmware DCBX Capabilities
883  */
884 typedef struct _q80_query_fw_dcbx_caps {
885         uint16_t        opcode;
886         uint16_t        count_version;
887 } __packed q80_query_fw_dcbx_caps_t;
888 
889 typedef struct _q80_query_fw_dcbx_caps_rsp {
890         uint16_t        opcode;
891         uint16_t        regcnt_status;
892 
893         uint32_t        dcbx_caps;
894 #define Q8_QUERY_FW_DCBX_CAPS_TSA               0x00000001
895 #define Q8_QUERY_FW_DCBX_CAPS_ETS               0x00000002
896 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_CEE_1_01     0x00000004
897 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_IEEE_1_0     0x00000008
898 #define Q8_QUERY_FW_DCBX_MAX_TC_MASK            0x00F00000
899 #define Q8_QUERY_FW_DCBX_MAX_ETS_TC_MASK        0x0F000000
900 #define Q8_QUERY_FW_DCBX_MAX_PFC_TC_MASK        0xF0000000
901 
902 } __packed q80_query_fw_dcbx_caps_rsp_t;
903 
904 /*
905  * IDC Ack Cmd
906  */
907 
908 typedef struct _q80_idc_ack {
909 	uint16_t	opcode;
910 	uint16_t	count_version;
911 
912 	uint32_t	aen_mb1;
913 	uint32_t	aen_mb2;
914 	uint32_t	aen_mb3;
915 	uint32_t	aen_mb4;
916 
917 } __packed q80_idc_ack_t;
918 
919 typedef struct _q80_idc_ack_rsp {
920 	uint16_t	opcode;
921 	uint16_t	regcnt_status;
922 } __packed q80_idc_ack_rsp_t;
923 
924 /*
925  * Set Port Configuration command
926  * Used to set Ethernet Standard Pause values
927  */
928 
929 typedef struct _q80_set_port_cfg {
930 	uint16_t	opcode;
931 	uint16_t	count_version;
932 
933 	uint32_t	cfg_bits;
934 
935 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_MASK	(0x7 << 1)
936 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE	(0x0 << 1)
937 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS	(0x2 << 1)
938 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_PHY	(0x3 << 1)
939 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT	(0x4 << 1)
940 
941 #define Q8_VALID_LOOPBACK_MODE(mode) \
942              (((mode) == Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE) || \
943 		(((mode) >= Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS) && \
944 		 ((mode) <= Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT)))
945 
946 #define Q8_PORT_CFG_BITS_DCBX_ENABLE		BIT_4
947 
948 #define Q8_PORT_CFG_BITS_PAUSE_CFG_MASK		(0x3 << 5)
949 #define Q8_PORT_CFG_BITS_PAUSE_DISABLED		(0x0 << 5)
950 #define Q8_PORT_CFG_BITS_PAUSE_STD		(0x1 << 5)
951 #define Q8_PORT_CFG_BITS_PAUSE_PPM		(0x2 << 5)
952 
953 #define Q8_PORT_CFG_BITS_LNKCAP_10MB		BIT_8
954 #define Q8_PORT_CFG_BITS_LNKCAP_100MB		BIT_9
955 #define Q8_PORT_CFG_BITS_LNKCAP_1GB		BIT_10
956 #define Q8_PORT_CFG_BITS_LNKCAP_10GB		BIT_11
957 
958 #define Q8_PORT_CFG_BITS_AUTONEG		BIT_15
959 #define Q8_PORT_CFG_BITS_XMT_DISABLE		BIT_17
960 #define Q8_PORT_CFG_BITS_FEC_RQSTD		BIT_18
961 #define Q8_PORT_CFG_BITS_EEE_RQSTD		BIT_19
962 
963 #define Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK	(0x3 << 20)
964 #define Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV	(0x0 << 20)
965 #define Q8_PORT_CFG_BITS_STDPAUSE_XMT		(0x1 << 20)
966 #define Q8_PORT_CFG_BITS_STDPAUSE_RCV		(0x2 << 20)
967 
968 } __packed q80_set_port_cfg_t;
969 
970 typedef struct _q80_set_port_cfg_rsp {
971 	uint16_t	opcode;
972 	uint16_t	regcnt_status;
973 } __packed q80_set_port_cfg_rsp_t;
974 
975 /*
976  * Get Port Configuration Command
977  */
978 
979 typedef struct _q80_get_port_cfg {
980 	uint16_t	opcode;
981 	uint16_t	count_version;
982 } __packed q80_get_port_cfg_t;
983 
984 typedef struct _q80_get_port_cfg_rsp {
985 	uint16_t	opcode;
986 	uint16_t	regcnt_status;
987 
988 	uint32_t	cfg_bits; /* same as in q80_set_port_cfg_t */
989 
990 	uint8_t		phys_port_type;
991 	uint8_t		rsvd[3];
992 } __packed q80_get_port_cfg_rsp_t;
993 
994 /*
995  * Get Link Status Command
996  * Used to get current PAUSE values for the port
997  */
998 
999 typedef struct _q80_get_link_status {
1000         uint16_t        opcode;
1001         uint16_t        count_version;
1002 } __packed q80_get_link_status_t;
1003 
1004 typedef struct _q80_get_link_status_rsp {
1005         uint16_t        opcode;
1006         uint16_t        regcnt_status;
1007 
1008 	uint32_t	cfg_bits;
1009 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_UP		BIT_0
1010 
1011 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_MASK	(0x7 << 3)
1012 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_UNKNOWN	(0x0 << 3)
1013 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10MB	(0x1 << 3)
1014 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_100MB	(0x2 << 3)
1015 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_1GB	(0x3 << 3)
1016 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10GB	(0x4 << 3)
1017 
1018 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_MASK	(0x3 << 6)
1019 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_DISABLE	(0x0 << 6)
1020 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_STD		(0x1 << 6)
1021 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_PPM		(0x2 << 6)
1022 
1023 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_MASK		(0x7 << 8)
1024 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_NONE		(0x0 << 6)
1025 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_HSS		(0x2 << 6)
1026 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_PHY		(0x3 << 6)
1027 
1028 #define Q8_GET_LINK_STAT_CFG_BITS_FEC_ENABLED		BIT_12
1029 #define Q8_GET_LINK_STAT_CFG_BITS_EEE_ENABLED		BIT_13
1030 
1031 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_DIR_MASK	(0x3 << 20)
1032 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_NONE		(0x0 << 20)
1033 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT		(0x1 << 20)
1034 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_RCV		(0x2 << 20)
1035 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT_RCV	(0x3 << 20)
1036 
1037 	uint32_t	link_state;
1038 #define Q8_GET_LINK_STAT_LOSS_OF_SIGNAL			BIT_0
1039 #define Q8_GET_LINK_STAT_PORT_RST_DONE			BIT_3
1040 #define Q8_GET_LINK_STAT_PHY_LINK_DOWN			BIT_4
1041 #define Q8_GET_LINK_STAT_PCS_LINK_DOWN			BIT_5
1042 #define Q8_GET_LINK_STAT_MAC_LOCAL_FAULT		BIT_6
1043 #define Q8_GET_LINK_STAT_MAC_REMOTE_FAULT		BIT_7
1044 #define Q8_GET_LINK_STAT_XMT_DISABLED			BIT_9
1045 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT			BIT_10
1046 
1047 	uint32_t	sfp_info;
1048 #define Q8_GET_LINK_STAT_SFP_TRNCVR_MASK		0x3
1049 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NOT_EXPECTED	0x0
1050 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NONE		0x1
1051 #define Q8_GET_LINK_STAT_SFP_TRNCVR_INVALID		0x2
1052 #define Q8_GET_LINK_STAT_SFP_TRNCVR_VALID		0x3
1053 
1054 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_MASK		(0x3 << 2)
1055 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_UNREC_TRSVR	(0x0 << 2)
1056 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_NOT_QLOGIC	(0x1 << 2)
1057 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_SPEED_FAILED	(0x2 << 2)
1058 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_ACCESS_ERROR	(0x3 << 2)
1059 
1060 #define Q8_GET_LINK_STAT_SFP_MOD_TYPE_MASK		(0x1F << 4)
1061 #define Q8_GET_LINK_STAT_SFP_MOD_NONE			(0x00 << 4)
1062 #define Q8_GET_LINK_STAT_SFP_MOD_10GBLRM		(0x01 << 4)
1063 #define Q8_GET_LINK_STAT_SFP_MOD_10GBLR			(0x02 << 4)
1064 #define Q8_GET_LINK_STAT_SFP_MOD_10GBSR			(0x03 << 4)
1065 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_P		(0x04 << 4)
1066 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_AL		(0x05 << 4)
1067 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_PL		(0x06 << 4)
1068 #define Q8_GET_LINK_STAT_SFP_MOD_1GBSX			(0x07 << 4)
1069 #define Q8_GET_LINK_STAT_SFP_MOD_1GBLX			(0x08 << 4)
1070 #define Q8_GET_LINK_STAT_SFP_MOD_1GBCX			(0x09 << 4)
1071 #define Q8_GET_LINK_STAT_SFP_MOD_1GBT			(0x0A << 4)
1072 #define Q8_GET_LINK_STAT_SFP_MOD_1GBC_PL		(0x0B << 4)
1073 #define Q8_GET_LINK_STAT_SFP_MOD_UNKNOWN		(0x0F << 4)
1074 
1075 #define Q8_GET_LINK_STAT_SFP_MULTI_RATE_MOD		BIT_9
1076 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT			BIT_10
1077 #define Q8_GET_LINK_STAT_SFP_COPPER_CBL_LENGTH_MASK	(0xFF << 16)
1078 
1079 } __packed q80_get_link_status_rsp_t;
1080 
1081 /*
1082  * Transmit Related Definitions
1083  */
1084 /* Max# of TX Rings per Tx Create Cntxt Mbx Cmd*/
1085 #define MAX_TCNTXT_RINGS           8
1086 
1087 /*
1088  * Transmit Context - Q8_CMD_CREATE_TX_CNTXT Command Configuration Data
1089  */
1090 
1091 typedef struct _q80_rq_tx_ring {
1092 	uint64_t	paddr;
1093 	uint64_t	tx_consumer;
1094 	uint16_t	nentries;
1095 	uint16_t	intr_id;
1096 	uint8_t 	intr_src_bit;
1097 	uint8_t 	rsrvd[3];
1098 } __packed q80_rq_tx_ring_t;
1099 
1100 typedef struct _q80_rq_tx_cntxt {
1101 	uint16_t		opcode;
1102 	uint16_t 		count_version;
1103 
1104 	uint32_t		cap0;
1105 #define Q8_TX_CNTXT_CAP0_BASEFW		(1 << 0)
1106 #define Q8_TX_CNTXT_CAP0_LSO		(1 << 6)
1107 #define Q8_TX_CNTXT_CAP0_TC		(1 << 25)
1108 
1109 	uint32_t		cap1;
1110 	uint32_t		cap2;
1111 	uint32_t		cap3;
1112 	uint8_t			ntx_rings;
1113 	uint8_t			traffic_class; /* bits 8-10; others reserved */
1114 	uint16_t		tx_vpid;
1115 	q80_rq_tx_ring_t	tx_ring[MAX_TCNTXT_RINGS];
1116 } __packed q80_rq_tx_cntxt_t;
1117 
1118 typedef struct _q80_rsp_tx_ring {
1119 	uint32_t		prod_index;
1120 	uint16_t		cntxt_id;
1121 	uint8_t			state;
1122 	uint8_t			rsrvd;
1123 } q80_rsp_tx_ring_t;
1124 
1125 typedef struct _q80_rsp_tx_cntxt {
1126         uint16_t                opcode;
1127         uint16_t                regcnt_status;
1128 	uint8_t			ntx_rings;
1129         uint8_t                 phy_port;
1130         uint8_t                 virt_port;
1131 	uint8_t                 rsrvd;
1132 	q80_rsp_tx_ring_t	tx_ring[MAX_TCNTXT_RINGS];
1133 } __packed q80_rsp_tx_cntxt_t;
1134 
1135 typedef struct _q80_tx_cntxt_destroy {
1136         uint16_t        opcode;
1137 	uint16_t 	count_version;
1138         uint32_t        cntxt_id;
1139 } __packed q80_tx_cntxt_destroy_t;
1140 
1141 typedef struct _q80_tx_cntxt_destroy_rsp {
1142 	uint16_t	opcode;
1143 	uint16_t	regcnt_status;
1144 } __packed q80_tx_cntxt_destroy_rsp_t;
1145 
1146 /*
1147  * Transmit Command Descriptor
1148  * These commands are issued on the Transmit Ring associated with a Transmit
1149  * context
1150  */
1151 typedef struct _q80_tx_cmd {
1152 	uint8_t		tcp_hdr_off;	/* TCP Header Offset */
1153 	uint8_t		ip_hdr_off;	/* IP Header Offset */
1154 	uint16_t	flags_opcode;	/* Bits 0-6: flags; 7-12: opcode */
1155 
1156 	/* flags field */
1157 #define Q8_TX_CMD_FLAGS_MULTICAST	0x01
1158 #define Q8_TX_CMD_FLAGS_LSO_TSO		0x02
1159 #define Q8_TX_CMD_FLAGS_VLAN_TAGGED	0x10
1160 #define Q8_TX_CMD_FLAGS_HW_VLAN_ID	0x40
1161 
1162 	/* opcode field */
1163 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6	(0xC << 7)
1164 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6	(0xB << 7)
1165 #define Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6		(0x6 << 7)
1166 #define Q8_TX_CMD_OP_XMT_TCP_LSO		(0x5 << 7)
1167 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM		(0x3 << 7)
1168 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM		(0x2 << 7)
1169 #define Q8_TX_CMD_OP_XMT_ETHER			(0x1 << 7)
1170 
1171 	uint8_t		n_bufs;		/* # of data segs in data buffer */
1172 	uint8_t		data_len_lo;	/* data length lower 8 bits */
1173 	uint16_t	data_len_hi;	/* data length upper 16 bits */
1174 
1175 	uint64_t	buf2_addr;	/* buffer 2 address */
1176 
1177 	uint16_t	rsrvd0;
1178 	uint16_t	mss;		/* MSS for this packet */
1179 	uint8_t		cntxtid;	/* Bits 7-4: ContextId; 3-0: reserved */
1180 
1181 #define Q8_TX_CMD_PORT_CNXTID(c_id) ((c_id & 0xF) << 4)
1182 
1183 	uint8_t		total_hdr_len;	/* MAC+IP+TCP Header Length for LSO */
1184 	uint16_t	rsrvd1;
1185 
1186 	uint64_t	buf3_addr;	/* buffer 3 address */
1187 	uint64_t	buf1_addr;	/* buffer 1 address */
1188 
1189 	uint16_t	buf1_len;	/* length of buffer 1 */
1190 	uint16_t	buf2_len;	/* length of buffer 2 */
1191 	uint16_t	buf3_len;	/* length of buffer 3 */
1192 	uint16_t	buf4_len;	/* length of buffer 4 */
1193 
1194 	uint64_t	buf4_addr;	/* buffer 4 address */
1195 
1196 	uint32_t	rsrvd2;
1197 	uint16_t	rsrvd3;
1198 	uint16_t	vlan_tci;	/* VLAN TCI when hw tagging is enabled*/
1199 
1200 } __packed q80_tx_cmd_t; /* 64 bytes */
1201 
1202 #define Q8_TX_CMD_MAX_SEGMENTS		4
1203 #define Q8_TX_CMD_TSO_ALIGN		2
1204 #define Q8_TX_MAX_NON_TSO_SEGS		62
1205 
1206 /*
1207  * Receive Related Definitions
1208  */
1209 #define MAX_RDS_RING_SETS	8 /* Max# of Receive Descriptor Rings */
1210 
1211 #ifdef QL_ENABLE_ISCSI_TLV
1212 #define MAX_SDS_RINGS           32 /* Max# of Status Descriptor Rings */
1213 #define NUM_TX_RINGS		(MAX_SDS_RINGS * 2)
1214 #else
1215 #define MAX_SDS_RINGS           32 /* Max# of Status Descriptor Rings */
1216 #define NUM_TX_RINGS		MAX_SDS_RINGS
1217 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */
1218 #define MAX_RDS_RINGS           MAX_SDS_RINGS /* Max# of Rcv Descriptor Rings */
1219 
1220 typedef struct _q80_rq_sds_ring {
1221 	uint64_t paddr; /* physical addr of status ring in system memory */
1222 	uint64_t hdr_split1;
1223 	uint64_t hdr_split2;
1224 	uint16_t size; /* number of entries in status ring */
1225 	uint16_t hdr_split1_size;
1226 	uint16_t hdr_split2_size;
1227 	uint16_t hdr_split_count;
1228 	uint16_t intr_id;
1229 	uint8_t  intr_src_bit;
1230 	uint8_t  rsrvd[5];
1231 } __packed q80_rq_sds_ring_t; /* 10 32bit words */
1232 
1233 typedef struct _q80_rq_rds_ring {
1234 	uint64_t paddr_std;	/* physical addr of rcv ring in system memory */
1235 	uint64_t paddr_jumbo;	/* physical addr of rcv ring in system memory */
1236 	uint16_t std_bsize;
1237 	uint16_t std_nentries;
1238 	uint16_t jumbo_bsize;
1239 	uint16_t jumbo_nentries;
1240 } __packed q80_rq_rds_ring_t; /* 6 32bit words */
1241 
1242 #define MAX_RCNTXT_SDS_RINGS	8
1243 
1244 typedef struct _q80_rq_rcv_cntxt {
1245 	uint16_t		opcode;
1246 	uint16_t 		count_version;
1247 	uint32_t		cap0;
1248 #define Q8_RCV_CNTXT_CAP0_BASEFW	(1 << 0)
1249 #define Q8_RCV_CNTXT_CAP0_MULTI_RDS	(1 << 1)
1250 #define Q8_RCV_CNTXT_CAP0_LRO		(1 << 5)
1251 #define Q8_RCV_CNTXT_CAP0_HW_LRO	(1 << 10)
1252 #define Q8_RCV_CNTXT_CAP0_VLAN_ALIGN	(1 << 14)
1253 #define Q8_RCV_CNTXT_CAP0_RSS		(1 << 15)
1254 #define Q8_RCV_CNTXT_CAP0_MSFT_RSS	(1 << 16)
1255 #define Q8_RCV_CNTXT_CAP0_SGL_JUMBO	(1 << 18)
1256 #define Q8_RCV_CNTXT_CAP0_SGL_LRO	(1 << 19)
1257 #define Q8_RCV_CNTXT_CAP0_SINGLE_JUMBO	(1 << 26)
1258 
1259 	uint32_t		cap1;
1260 	uint32_t		cap2;
1261 	uint32_t		cap3;
1262 	uint8_t 		nrds_sets_rings;
1263 	uint8_t 		nsds_rings;
1264 	uint16_t		rds_producer_mode;
1265 #define Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE	0
1266 #define Q8_RCV_CNTXT_RDS_PROD_MODE_SHARED	1
1267 
1268 	uint16_t		rcv_vpid;
1269 	uint16_t		rsrvd0;
1270 	uint32_t		rsrvd1;
1271 	q80_rq_sds_ring_t	sds[MAX_RCNTXT_SDS_RINGS];
1272 	q80_rq_rds_ring_t	rds[MAX_RDS_RING_SETS];
1273 } __packed q80_rq_rcv_cntxt_t;
1274 
1275 typedef struct _q80_rsp_rds_ring {
1276 	uint32_t prod_std;
1277 	uint32_t prod_jumbo;
1278 } __packed q80_rsp_rds_ring_t; /* 8 bytes */
1279 
1280 typedef struct _q80_rsp_rcv_cntxt {
1281 	uint16_t		opcode;
1282 	uint16_t		regcnt_status;
1283 	uint8_t 		nrds_sets_rings;
1284 	uint8_t 		nsds_rings;
1285 	uint16_t		cntxt_id;
1286 	uint8_t			state;
1287 	uint8_t			num_funcs;
1288 	uint8_t			phy_port;
1289 	uint8_t			virt_port;
1290 	uint32_t		sds_cons[MAX_RCNTXT_SDS_RINGS];
1291 	q80_rsp_rds_ring_t	rds[MAX_RDS_RING_SETS];
1292 } __packed q80_rsp_rcv_cntxt_t;
1293 
1294 typedef struct _q80_rcv_cntxt_destroy {
1295 	uint16_t	opcode;
1296 	uint16_t 	count_version;
1297 	uint32_t	cntxt_id;
1298 } __packed q80_rcv_cntxt_destroy_t;
1299 
1300 typedef struct _q80_rcv_cntxt_destroy_rsp {
1301 	uint16_t	opcode;
1302 	uint16_t	regcnt_status;
1303 } __packed q80_rcv_cntxt_destroy_rsp_t;
1304 
1305 /*
1306  * Add Receive Rings
1307  */
1308 typedef struct _q80_rq_add_rcv_rings {
1309 	uint16_t		opcode;
1310 	uint16_t		count_version;
1311 	uint8_t			nrds_sets_rings;
1312 	uint8_t			nsds_rings;
1313 	uint16_t		cntxt_id;
1314 	q80_rq_sds_ring_t	sds[MAX_RCNTXT_SDS_RINGS];
1315 	q80_rq_rds_ring_t	rds[MAX_RDS_RING_SETS];
1316 } __packed q80_rq_add_rcv_rings_t;
1317 
1318 typedef struct _q80_rsp_add_rcv_rings {
1319 	uint16_t		opcode;
1320 	uint16_t		regcnt_status;
1321 	uint8_t			nrds_sets_rings;
1322 	uint8_t			nsds_rings;
1323 	uint16_t		cntxt_id;
1324 	uint32_t		sds_cons[MAX_RCNTXT_SDS_RINGS];
1325 	q80_rsp_rds_ring_t	rds[MAX_RDS_RING_SETS];
1326 } __packed q80_rsp_add_rcv_rings_t;
1327 
1328 /*
1329  * Map Status Ring to Receive Descriptor Set
1330  */
1331 
1332 #define MAX_SDS_TO_RDS_MAP      16
1333 
1334 typedef struct _q80_sds_rds_map_e {
1335         uint8_t sds_ring;
1336         uint8_t rsrvd0;
1337         uint8_t rds_ring;
1338         uint8_t rsrvd1;
1339 } __packed q80_sds_rds_map_e_t;
1340 
1341 typedef struct _q80_rq_map_sds_to_rds {
1342         uint16_t                opcode;
1343         uint16_t                count_version;
1344         uint16_t                cntxt_id;
1345         uint16_t                num_rings;
1346         q80_sds_rds_map_e_t     sds_rds[MAX_SDS_TO_RDS_MAP];
1347 } __packed q80_rq_map_sds_to_rds_t;
1348 
1349 typedef struct _q80_rsp_map_sds_to_rds {
1350         uint16_t                opcode;
1351         uint16_t                regcnt_status;
1352         uint16_t                cntxt_id;
1353         uint16_t                num_rings;
1354         q80_sds_rds_map_e_t     sds_rds[MAX_SDS_TO_RDS_MAP];
1355 } __packed q80_rsp_map_sds_to_rds_t;
1356 
1357 /*
1358  * Receive Descriptor corresponding to each entry in the receive ring
1359  */
1360 typedef struct _q80_rcv_desc {
1361 	uint16_t handle;
1362 	uint16_t rsrvd;
1363 	uint32_t buf_size; /* buffer size in bytes */
1364 	uint64_t buf_addr; /* physical address of buffer */
1365 } __packed q80_recv_desc_t;
1366 
1367 /*
1368  * Status Descriptor corresponding to each entry in the Status ring
1369  */
1370 typedef struct _q80_stat_desc {
1371 	uint64_t data[2];
1372 } __packed q80_stat_desc_t;
1373 
1374 /*
1375  * definitions for data[0] field of Status Descriptor
1376  */
1377 #define Q8_STAT_DESC_RSS_HASH(data)		(data & 0xFFFFFFFF)
1378 #define Q8_STAT_DESC_TOTAL_LENGTH(data)		((data >> 32) & 0x3FFF)
1379 #define Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(data)	((data >> 32) & 0xFFFF)
1380 #define Q8_STAT_DESC_HANDLE(data)		((data >> 48) & 0xFFFF)
1381 /*
1382  * definitions for data[1] field of Status Descriptor
1383  */
1384 
1385 #define Q8_STAT_DESC_OPCODE(data)		((data >> 42) & 0xF)
1386 #define		Q8_STAT_DESC_OPCODE_RCV_PKT		0x01
1387 #define		Q8_STAT_DESC_OPCODE_LRO_PKT		0x02
1388 #define		Q8_STAT_DESC_OPCODE_SGL_LRO		0x04
1389 #define		Q8_STAT_DESC_OPCODE_SGL_RCV		0x05
1390 #define		Q8_STAT_DESC_OPCODE_CONT		0x06
1391 
1392 /*
1393  * definitions for data[1] field of Status Descriptor for standard frames
1394  * status descriptor opcode equals 0x04
1395  */
1396 #define Q8_STAT_DESC_STATUS(data)		((data >> 39) & 0x0007)
1397 #define		Q8_STAT_DESC_STATUS_CHKSUM_NOT_DONE	0x00
1398 #define		Q8_STAT_DESC_STATUS_NO_CHKSUM		0x01
1399 #define		Q8_STAT_DESC_STATUS_CHKSUM_OK		0x02
1400 #define		Q8_STAT_DESC_STATUS_CHKSUM_ERR		0x03
1401 
1402 #define Q8_STAT_DESC_VLAN(data)			((data >> 47) & 1)
1403 #define Q8_STAT_DESC_VLAN_ID(data)		((data >> 48) & 0xFFFF)
1404 
1405 #define Q8_STAT_DESC_PROTOCOL(data)		((data >> 44) & 0x000F)
1406 #define Q8_STAT_DESC_L2_OFFSET(data)		((data >> 48) & 0x001F)
1407 #define Q8_STAT_DESC_COUNT(data)		((data >> 37) & 0x0007)
1408 
1409 /*
1410  * definitions for data[0-1] fields of Status Descriptor for LRO
1411  * status descriptor opcode equals 0x04
1412  */
1413 
1414 /* definitions for data[1] field */
1415 #define Q8_LRO_STAT_DESC_SEQ_NUM(data)		(uint32_t)(data)
1416 
1417 /*
1418  * definitions specific to opcode 0x04 data[1]
1419  */
1420 #define	Q8_STAT_DESC_COUNT_SGL_LRO(data)	((data >> 13) & 0x0007)
1421 #define Q8_SGL_LRO_STAT_L2_OFFSET(data)         ((data >> 16) & 0xFF)
1422 #define Q8_SGL_LRO_STAT_L4_OFFSET(data)         ((data >> 24) & 0xFF)
1423 #define Q8_SGL_LRO_STAT_TS(data)                ((data >> 40) & 0x1)
1424 #define Q8_SGL_LRO_STAT_PUSH_BIT(data)          ((data >> 41) & 0x1)
1425 
1426 /*
1427  * definitions specific to opcode 0x05 data[1]
1428  */
1429 #define	Q8_STAT_DESC_COUNT_SGL_RCV(data)	((data >> 37) & 0x0003)
1430 
1431 /*
1432  * definitions for opcode 0x06
1433  */
1434 /* definitions for data[0] field */
1435 #define Q8_SGL_STAT_DESC_HANDLE1(data)          (data & 0xFFFF)
1436 #define Q8_SGL_STAT_DESC_HANDLE2(data)          ((data >> 16) & 0xFFFF)
1437 #define Q8_SGL_STAT_DESC_HANDLE3(data)          ((data >> 32) & 0xFFFF)
1438 #define Q8_SGL_STAT_DESC_HANDLE4(data)          ((data >> 48) & 0xFFFF)
1439 
1440 /* definitions for data[1] field */
1441 #define Q8_SGL_STAT_DESC_HANDLE5(data)          (data & 0xFFFF)
1442 #define Q8_SGL_STAT_DESC_HANDLE6(data)          ((data >> 16) & 0xFFFF)
1443 #define Q8_SGL_STAT_DESC_NUM_HANDLES(data)      ((data >> 32) & 0x7)
1444 #define Q8_SGL_STAT_DESC_HANDLE7(data)          ((data >> 48) & 0xFFFF)
1445 
1446 /** Driver Related Definitions Begin **/
1447 
1448 #define TX_SMALL_PKT_SIZE	128 /* size in bytes of small packets */
1449 
1450 /* The number of descriptors should be a power of 2 */
1451 #define NUM_TX_DESCRIPTORS		1024
1452 #define NUM_STATUS_DESCRIPTORS		1024
1453 
1454 #define NUM_RX_DESCRIPTORS	2048
1455 
1456 /*
1457  * structure describing various dma buffers
1458  */
1459 
1460 typedef struct qla_dmabuf {
1461         volatile struct {
1462                 uint32_t        tx_ring		:1,
1463                                 rds_ring	:1,
1464                                 sds_ring	:1,
1465 				minidump	:1;
1466         } flags;
1467 
1468         qla_dma_t               tx_ring;
1469         qla_dma_t               rds_ring[MAX_RDS_RINGS];
1470         qla_dma_t               sds_ring[MAX_SDS_RINGS];
1471 	qla_dma_t		minidump;
1472 } qla_dmabuf_t;
1473 
1474 typedef struct _qla_sds {
1475         q80_stat_desc_t *sds_ring_base; /* start of sds ring */
1476         uint32_t        sdsr_next; /* next entry in SDS ring to process */
1477         struct lro_ctrl lro;
1478         void            *rxb_free;
1479         uint32_t        rx_free;
1480         volatile uint32_t rcv_active;
1481 	uint32_t	sds_consumer;
1482 	uint64_t	intr_count;
1483 	uint64_t	spurious_intr_count;
1484 } qla_sds_t;
1485 
1486 #define Q8_MAX_LRO_CONT_DESC    7
1487 #define Q8_MAX_HANDLES_LRO      (1 + (Q8_MAX_LRO_CONT_DESC * 7))
1488 #define Q8_MAX_HANDLES_NON_LRO  8
1489 
1490 typedef struct _qla_sgl_rcv {
1491         uint16_t        pkt_length;
1492         uint16_t        num_handles;
1493         uint16_t        chksum_status;
1494         uint32_t        rss_hash;
1495         uint16_t        rss_hash_flags;
1496         uint16_t        vlan_tag;
1497         uint16_t        handle[Q8_MAX_HANDLES_NON_LRO];
1498 } qla_sgl_rcv_t;
1499 
1500 typedef struct _qla_sgl_lro {
1501         uint16_t        flags;
1502 #define Q8_LRO_COMP_TS          0x1
1503 #define Q8_LRO_COMP_PUSH_BIT    0x2
1504         uint16_t        l2_offset;
1505         uint16_t        l4_offset;
1506 
1507         uint16_t        payload_length;
1508         uint16_t        num_handles;
1509         uint32_t        rss_hash;
1510         uint16_t        rss_hash_flags;
1511         uint16_t        vlan_tag;
1512         uint16_t        handle[Q8_MAX_HANDLES_LRO];
1513 } qla_sgl_lro_t;
1514 
1515 typedef union {
1516         qla_sgl_rcv_t   rcv;
1517         qla_sgl_lro_t   lro;
1518 } qla_sgl_comp_t;
1519 
1520 #define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\
1521 		sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16)
1522 
1523 typedef struct _qla_hw_tx_cntxt {
1524 	q80_tx_cmd_t    *tx_ring_base;
1525 	bus_addr_t	tx_ring_paddr;
1526 
1527 	volatile uint32_t *tx_cons; /* tx consumer shadow reg */
1528 	bus_addr_t      tx_cons_paddr;
1529 
1530 	volatile uint32_t txr_free; /* # of free entries in tx ring */
1531 	volatile uint32_t txr_next; /* # next available tx ring entry */
1532 	volatile uint32_t txr_comp; /* index of last tx entry completed */
1533 
1534 	uint32_t        tx_prod_reg;
1535 	uint16_t	tx_cntxt_id;
1536 
1537 } qla_hw_tx_cntxt_t;
1538 
1539 typedef struct _qla_mcast {
1540 	uint16_t	rsrvd;
1541 	uint8_t		addr[ETHER_ADDR_LEN];
1542 } __packed qla_mcast_t;
1543 
1544 typedef struct _qla_rdesc {
1545         volatile uint32_t prod_std;
1546         volatile uint32_t prod_jumbo;
1547         volatile uint32_t rx_next; /* next standard rcv ring to arm fw */
1548         volatile int32_t  rx_in; /* next standard rcv ring to add mbufs */
1549 	uint64_t count;
1550 	uint64_t lro_pkt_count;
1551 	uint64_t lro_bytes;
1552 } qla_rdesc_t;
1553 
1554 typedef struct _qla_flash_desc_table {
1555 	uint32_t	flash_valid;
1556 	uint16_t	flash_ver;
1557 	uint16_t	flash_len;
1558 	uint16_t	flash_cksum;
1559 	uint16_t	flash_unused;
1560 	uint8_t		flash_model[16];
1561 	uint16_t	flash_manuf;
1562 	uint16_t	flash_id;
1563 	uint8_t		flash_flag;
1564 	uint8_t		erase_cmd;
1565 	uint8_t		alt_erase_cmd;
1566 	uint8_t		write_enable_cmd;
1567 	uint8_t		write_enable_bits;
1568 	uint8_t		write_statusreg_cmd;
1569 	uint8_t		unprotected_sec_cmd;
1570 	uint8_t		read_manuf_cmd;
1571 	uint32_t	block_size;
1572 	uint32_t	alt_block_size;
1573 	uint32_t	flash_size;
1574 	uint32_t	write_enable_data;
1575 	uint8_t		readid_addr_len;
1576 	uint8_t		write_disable_bits;
1577 	uint8_t		read_dev_id_len;
1578 	uint8_t		chip_erase_cmd;
1579 	uint16_t	read_timeo;
1580 	uint8_t		protected_sec_cmd;
1581 	uint8_t		resvd[65];
1582 } __packed qla_flash_desc_table_t;
1583 
1584 /*
1585  * struct for storing hardware specific information for a given interface
1586  */
1587 typedef struct _qla_hw {
1588 	struct {
1589 		uint32_t
1590 			unicast_mac	:1,
1591 			bcast_mac	:1,
1592 			init_tx_cnxt	:1,
1593 			init_rx_cnxt	:1,
1594 			init_intr_cnxt	:1,
1595 			fdt_valid	:1;
1596 	} flags;
1597 
1598 	volatile uint16_t	link_speed;
1599 	volatile uint16_t	cable_length;
1600 	volatile uint32_t	cable_oui;
1601 	volatile uint8_t	link_up;
1602 	volatile uint8_t	module_type;
1603 	volatile uint8_t	link_faults;
1604 	volatile uint8_t	loopback_mode;
1605 	volatile uint8_t	fduplex;
1606 	volatile uint8_t	autoneg;
1607 
1608 	volatile uint8_t	mac_rcv_mode;
1609 
1610 	volatile uint32_t	max_mtu;
1611 
1612 	uint8_t		mac_addr[ETHER_ADDR_LEN];
1613 
1614 	uint32_t	num_sds_rings;
1615 	uint32_t	num_rds_rings;
1616 	uint32_t	num_tx_rings;
1617 
1618         qla_dmabuf_t	dma_buf;
1619 
1620 	/* Transmit Side */
1621 
1622 	qla_hw_tx_cntxt_t tx_cntxt[NUM_TX_RINGS];
1623 
1624 	/* Receive Side */
1625 
1626 	uint16_t	rcv_cntxt_id;
1627 
1628 	uint32_t	mbx_intr_mask_offset;
1629 
1630 	uint16_t	intr_id[MAX_SDS_RINGS];
1631 	uint32_t	intr_src[MAX_SDS_RINGS];
1632 
1633 	qla_sds_t	sds[MAX_SDS_RINGS];
1634 	uint32_t	mbox[Q8_NUM_MBOX];
1635 	qla_rdesc_t	rds[MAX_RDS_RINGS];
1636 
1637 	uint32_t	rds_pidx_thres;
1638 	uint32_t	sds_cidx_thres;
1639 
1640 	uint32_t	rcv_intr_coalesce;
1641 	uint32_t	xmt_intr_coalesce;
1642 
1643 	/* Immediate Completion */
1644 	volatile uint32_t imd_compl;
1645 	volatile uint32_t aen_mb0;
1646 	volatile uint32_t aen_mb1;
1647 	volatile uint32_t aen_mb2;
1648 	volatile uint32_t aen_mb3;
1649 	volatile uint32_t aen_mb4;
1650 
1651 	/* multicast address list */
1652 	uint32_t	nmcast;
1653 	qla_mcast_t	mcast[Q8_MAX_NUM_MULTICAST_ADDRS];
1654 	uint8_t		mac_addr_arr[(Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)];
1655 
1656 	/* reset sequence */
1657 #define Q8_MAX_RESET_SEQ_IDX	16
1658 	uint32_t	rst_seq[Q8_MAX_RESET_SEQ_IDX];
1659 	uint32_t	rst_seq_idx;
1660 
1661 	/* heart beat register value */
1662 	uint32_t	hbeat_value;
1663 	uint32_t	health_count;
1664 	uint32_t	hbeat_failure;
1665 
1666 	uint32_t	max_tx_segs;
1667 	uint32_t	min_lro_pkt_size;
1668 
1669 	uint32_t        enable_hw_lro;
1670 	uint32_t        enable_soft_lro;
1671 	uint32_t        enable_9kb;
1672 
1673 	uint32_t	user_pri_nic;
1674 	uint32_t	user_pri_iscsi;
1675 
1676 	/* Flash Descriptor Table */
1677 	qla_flash_desc_table_t fdt;
1678 
1679 	/* stats */
1680 	q80_mac_stats_t mac;
1681 	q80_rcv_stats_t rcv;
1682 	q80_xmt_stats_t xmt[NUM_TX_RINGS];
1683 
1684 	/* Minidump Related */
1685 	uint32_t	mdump_init;
1686 	uint32_t	mdump_done;
1687 	uint32_t	mdump_active;
1688 	uint32_t	mdump_capture_mask;
1689 	uint32_t	mdump_start_seq_index;
1690 	void		*mdump_buffer;
1691 	uint32_t	mdump_buffer_size;
1692 	void		*mdump_template;
1693 	uint32_t	mdump_template_size;
1694 	uint64_t	mdump_usec_ts;
1695 
1696 #define Q8_MBX_COMP_MSECS	(19)
1697 	uint64_t	mbx_comp_msecs[Q8_MBX_COMP_MSECS];
1698 	/* driver state related */
1699 	void		*drvr_state;
1700 
1701 	/* slow path trace */
1702 	uint32_t	sp_log_stop_events;
1703 #define Q8_SP_LOG_STOP_HBEAT_FAILURE		0x001
1704 #define Q8_SP_LOG_STOP_TEMP_FAILURE		0x002
1705 #define Q8_SP_LOG_STOP_HW_INIT_FAILURE		0x004
1706 #define Q8_SP_LOG_STOP_IF_START_FAILURE		0x008
1707 #define Q8_SP_LOG_STOP_ERR_RECOVERY_FAILURE	0x010
1708 
1709 	uint32_t	sp_log_stop;
1710 	uint32_t	sp_log_index;
1711 	uint32_t	sp_log_num_entries;
1712 	void		*sp_log;
1713 } qla_hw_t;
1714 
1715 #define QL_UPDATE_RDS_PRODUCER_INDEX(ha, prod_reg, val) \
1716 		bus_write_4((ha->pci_reg), prod_reg, val);
1717 
1718 #define QL_UPDATE_TX_PRODUCER_INDEX(ha, val, i) \
1719 		WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val)
1720 
1721 #define QL_UPDATE_SDS_CONSUMER_INDEX(ha, i, val) \
1722 	bus_write_4((ha->pci_reg), (ha->hw.sds[i].sds_consumer), val);
1723 
1724 #define QL_ENABLE_INTERRUPTS(ha, i) \
1725 		bus_write_4((ha->pci_reg), (ha->hw.intr_src[i]), 0);
1726 
1727 #define QL_BUFFER_ALIGN                16
1728 
1729 /*
1730  * Flash Configuration
1731  */
1732 #define Q8_BOARD_CONFIG_OFFSET		0x370000
1733 #define Q8_BOARD_CONFIG_LENGTH		0x2000
1734 
1735 #define Q8_BOARD_CONFIG_MAC0_LO		0x400
1736 
1737 #define Q8_FDT_LOCK_MAGIC_ID		0x00FD00FD
1738 #define Q8_FDT_FLASH_ADDR_VAL		0xFD009F
1739 #define Q8_FDT_FLASH_CTRL_VAL		0x3F
1740 #define Q8_FDT_MASK_VAL			0xFF
1741 
1742 #define Q8_WR_ENABLE_FL_ADDR		0xFD0100
1743 #define Q8_WR_ENABLE_FL_CTRL		0x5
1744 
1745 #define Q8_ERASE_LOCK_MAGIC_ID		0x00EF00EF
1746 #define Q8_ERASE_FL_ADDR_MASK		0xFD0300
1747 #define Q8_ERASE_FL_CTRL_MASK		0x3D
1748 
1749 #define Q8_WR_FL_LOCK_MAGIC_ID		0xABCDABCD
1750 #define Q8_WR_FL_ADDR_MASK		0x800000
1751 #define Q8_WR_FL_CTRL_MASK		0x3D
1752 
1753 #define QL_FDT_OFFSET			0x3F0000
1754 #define Q8_FLASH_SECTOR_SIZE		0x10000
1755 
1756 /*
1757  * Off Chip Memory Access
1758  */
1759 
1760 typedef struct _q80_offchip_mem_val {
1761         uint32_t data_lo;
1762         uint32_t data_hi;
1763         uint32_t data_ulo;
1764         uint32_t data_uhi;
1765 } q80_offchip_mem_val_t;
1766 
1767 #endif /* #ifndef _QL_HW_H_ */
1768