1 /*-
2 * Copyright (c) 2017 Kevin Lo <kevlo@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 #include "opt_wlan.h"
29
30 #include <sys/param.h>
31 #include <sys/lock.h>
32 #include <sys/mutex.h>
33 #include <sys/mbuf.h>
34 #include <sys/kernel.h>
35 #include <sys/socket.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/queue.h>
39 #include <sys/taskqueue.h>
40 #include <sys/bus.h>
41 #include <sys/endian.h>
42 #include <sys/linker.h>
43
44 #include <net/if.h>
45 #include <net/ethernet.h>
46 #include <net/if_media.h>
47
48 #include <net80211/ieee80211_var.h>
49 #include <net80211/ieee80211_radiotap.h>
50
51 #include <dev/rtwn/if_rtwnreg.h>
52 #include <dev/rtwn/if_rtwnvar.h>
53
54 #include <dev/rtwn/if_rtwn_debug.h>
55 #include <dev/rtwn/if_rtwn_ridx.h>
56 #include <dev/rtwn/if_rtwn_rx.h>
57
58 #include <dev/rtwn/rtl8192c/r92c.h>
59
60 #include <dev/rtwn/rtl8192e/r92e.h>
61 #include <dev/rtwn/rtl8192e/r92e_reg.h>
62 #include <dev/rtwn/rtl8192e/r92e_var.h>
63
64 static int
r92e_get_power_group(struct rtwn_softc * sc,struct ieee80211_channel * c)65 r92e_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c)
66 {
67 uint8_t chan;
68 int group;
69
70 chan = rtwn_chan2centieee(c);
71 if (IEEE80211_IS_CHAN_2GHZ(c)) {
72 if (chan <= 2) group = 0;
73 else if (chan <= 5) group = 1;
74 else if (chan <= 8) group = 2;
75 else if (chan <= 11) group = 3;
76 else if (chan <= 14) group = 4;
77 else {
78 KASSERT(0, ("wrong 2GHz channel %d!\n", chan));
79 return (-1);
80 }
81 } else {
82 KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags));
83 return (-1);
84 }
85
86 return (group);
87 }
88
89 static void
r92e_get_txpower(struct rtwn_softc * sc,int chain,struct ieee80211_channel * c,uint8_t power[RTWN_RIDX_COUNT])90 r92e_get_txpower(struct rtwn_softc *sc, int chain, struct ieee80211_channel *c,
91 uint8_t power[RTWN_RIDX_COUNT])
92 {
93 struct r92e_softc *rs = sc->sc_priv;
94 int i, ridx, group, max_mcs;
95
96 /* Determine channel group. */
97 group = r92e_get_power_group(sc, c);
98 if (group == -1) { /* shouldn't happen */
99 device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__);
100 return;
101 }
102
103 max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1);
104
105 /* XXX regulatory */
106 /* XXX net80211 regulatory */
107
108 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++)
109 power[ridx] = rs->cck_tx_pwr[chain][group];
110 for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++)
111 power[ridx] = rs->ht40_tx_pwr_2g[chain][group];
112
113 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++)
114 power[ridx] += rs->ofdm_tx_pwr_diff_2g[chain][0];
115
116 for (i = 0; i < sc->ntxchains; i++) {
117 uint8_t min_mcs;
118 uint8_t pwr_diff;
119
120 if (IEEE80211_IS_CHAN_HT40(c))
121 pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i];
122 else
123 pwr_diff = rs->bw20_tx_pwr_diff_2g[chain][i];
124
125 min_mcs = RTWN_RIDX_HT_MCS(i * 8);
126 for (ridx = min_mcs; ridx <= max_mcs; ridx++)
127 power[ridx] += pwr_diff;
128 }
129
130 /* Apply max limit. */
131 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) {
132 if (power[ridx] > R92C_MAX_TX_PWR)
133 power[ridx] = R92C_MAX_TX_PWR;
134 }
135
136 #ifdef RTWN_DEBUG
137 if (sc->sc_debug & RTWN_DEBUG_TXPWR) {
138 /* Dump per-rate Tx power values. */
139 printf("Tx power for chain %d:\n", chain);
140 for (ridx = RTWN_RIDX_CCK1; ridx < RTWN_RIDX_COUNT; ridx++)
141 printf("Rate %d = %u\n", ridx, power[ridx]);
142 }
143 #endif
144 }
145
146 static void
r92e_set_txpower(struct rtwn_softc * sc,struct ieee80211_channel * c)147 r92e_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c)
148 {
149 uint8_t power[RTWN_RIDX_COUNT];
150 int i;
151
152 for (i = 0; i < sc->ntxchains; i++) {
153 memset(power, 0, sizeof(power));
154 /* Compute per-rate Tx power values. */
155 r92e_get_txpower(sc, i, c, power);
156 /* Write per-rate Tx power values to hardware. */
157 r92c_write_txpower(sc, i, power);
158 }
159 }
160
161 static void
r92e_set_bw40(struct rtwn_softc * sc,uint8_t chan,int prichlo)162 r92e_set_bw40(struct rtwn_softc *sc, uint8_t chan, int prichlo)
163 {
164 int i;
165
166 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80);
167 rtwn_write_1(sc, R12A_DATA_SEC,
168 prichlo ? R12A_DATA_SEC_PRIM_DOWN_20 : R12A_DATA_SEC_PRIM_UP_20);
169
170 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_40MHZ);
171 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, 0, R92C_RFMOD_40MHZ);
172
173 /* Select 40MHz bandwidth. */
174 for (i = 0; i < sc->nrxchains; i++)
175 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW,
176 R88E_RF_CHNLBW_BW20, 0x400);
177
178 /* Set CCK side band. */
179 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM,
180 R92C_CCK0_SYSTEM_CCK_SIDEBAND, (prichlo ? 0 : 1) << 4);
181
182 rtwn_bb_setbits(sc, R92C_OFDM1_LSTF, 0x0c00, (prichlo ? 1 : 2) << 10);
183
184 rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2,
185 R92C_FPGA0_ANAPARAM2_CBW20, 0);
186
187 rtwn_bb_setbits(sc, 0x818, 0x0c000000, (prichlo ? 2 : 1) << 26);
188 }
189
190 static void
r92e_set_bw20(struct rtwn_softc * sc,uint8_t chan)191 r92e_set_bw20(struct rtwn_softc *sc, uint8_t chan)
192 {
193 int i;
194
195 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0);
196 rtwn_write_1(sc, R12A_DATA_SEC, R12A_DATA_SEC_NO_EXT);
197
198 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, R92C_RFMOD_40MHZ, 0);
199 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, R92C_RFMOD_40MHZ, 0);
200
201 /* Select 20MHz bandwidth. */
202 for (i = 0; i < sc->nrxchains; i++)
203 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW,
204 R88E_RF_CHNLBW_BW20, 0xc00);
205
206 rtwn_bb_setbits(sc, R92C_OFDM0_TXPSEUDONOISEWGT, 0xc0000000, 0);
207 }
208
209 void
r92e_set_chan(struct rtwn_softc * sc,struct ieee80211_channel * c)210 r92e_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c)
211 {
212 struct r92e_softc *rs = sc->sc_priv;
213 u_int chan;
214 int i;
215
216 chan = rtwn_chan2centieee(c);
217
218 for (i = 0; i < sc->nrxchains; i++) {
219 rtwn_rf_write(sc, i, R92C_RF_CHNLBW,
220 RW(rs->rf_chnlbw[0], R92C_RF_CHNLBW_CHNL, chan));
221 }
222
223 if (IEEE80211_IS_CHAN_HT40(c))
224 r92e_set_bw40(sc, chan, IEEE80211_IS_CHAN_HT40U(c));
225 else
226 r92e_set_bw20(sc, chan);
227
228 /* Set Tx power for this new channel. */
229 r92e_set_txpower(sc, c);
230 }
231