1 /*-
2 * Copyright (c) 2017 Farhan Khan <khanzf@gmail.com>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <sys/cdefs.h>
18 #include "opt_wlan.h"
19
20 #include <sys/param.h>
21 #include <sys/lock.h>
22 #include <sys/mutex.h>
23 #include <sys/mbuf.h>
24 #include <sys/kernel.h>
25 #include <sys/socket.h>
26 #include <sys/systm.h>
27 #include <sys/malloc.h>
28 #include <sys/queue.h>
29 #include <sys/taskqueue.h>
30 #include <sys/bus.h>
31 #include <sys/endian.h>
32 #include <sys/linker.h>
33
34 #include <machine/bus.h>
35 #include <machine/resource.h>
36 #include <sys/rman.h>
37
38 #include <net/if.h>
39 #include <net/ethernet.h>
40 #include <net/if_media.h>
41
42 #include <net80211/ieee80211_var.h>
43 #include <net80211/ieee80211_radiotap.h>
44
45 #include <dev/rtwn/if_rtwnvar.h>
46
47 #include <dev/rtwn/pci/rtwn_pci_var.h>
48
49 #include <dev/rtwn/rtl8192c/r92c.h>
50
51 #include <dev/rtwn/rtl8188e/pci/r88ee.h>
52 #include <dev/rtwn/rtl8188e/pci/r88ee_reg.h>
53
54 void
r88ee_init_bb(struct rtwn_softc * sc)55 r88ee_init_bb(struct rtwn_softc *sc)
56 {
57
58 /* Enable BB and RF. */
59 rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
60 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
61 R92C_SYS_FUNC_EN_DIO_RF);
62
63 rtwn_write_1(sc, R92C_RF_CTRL,
64 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
65 rtwn_write_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_PPLL |
66 R92C_SYS_FUNC_EN_PCIEA | R92C_SYS_FUNC_EN_DIO_PCIE |
67 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
68
69 r88e_init_bb_common(sc);
70 }
71
72 void
r88ee_init_intr(struct rtwn_softc * sc)73 r88ee_init_intr(struct rtwn_softc *sc)
74 {
75 /* Disable interrupts. */
76 rtwn_write_4(sc, R88E_HIMR, 0x00000000);
77 rtwn_write_4(sc, R88E_HIMRE, 0x00000000);
78 }
79
80 int
r88ee_power_on(struct rtwn_softc * sc)81 r88ee_power_on(struct rtwn_softc *sc)
82 {
83 int ntries;
84
85 /* Disable XTAL output for power saving. */
86 rtwn_setbits_1(sc, R88E_XCK_OUT_CTRL, R88E_XCK_OUT_CTRL_EN, 0);
87
88 /* Unlock ISO/CLK/Power control register. */
89 rtwn_setbits_2(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_APDM_HPDN, 0);
90 rtwn_write_1(sc, R92C_RSV_CTRL, 0);
91
92 /* Wait for power ready bit */
93 for(ntries = 0; ntries < 5000; ntries++) {
94 if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
95 break;
96 rtwn_delay(sc, 10);
97 }
98 if (ntries == 5000) {
99 device_printf(sc->sc_dev,
100 "timeout waiting for chip power up\n");
101 return (ETIMEDOUT);
102 }
103
104 /* Reset BB. */
105 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
106 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
107
108 /* schmit trigger */
109 rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
110
111 /* Disable HWPDN. */
112 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
113 R92C_APS_FSMCO_APDM_HPDN, 0, 1);
114
115 /* Disable WL suspend. */
116 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
117 R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1);
118
119 /* Auto-enable WLAN */
120 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
121 0, R92C_APS_FSMCO_APFM_ONMAC, 1);
122 for (ntries = 0; ntries < 5000; ntries++) {
123 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
124 R92C_APS_FSMCO_APFM_ONMAC))
125 break;
126 rtwn_delay(sc, 10);
127 }
128 if (ntries == 5000)
129 return (ETIMEDOUT);
130
131 rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
132
133 /* Enable LDO normal mode. */
134 rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP, 0);
135
136 rtwn_setbits_1(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_PDN_EN);
137 rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
138 rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL_EXT + 1, 0, 0x02);
139 rtwn_setbits_1(sc, R92C_SYS_CLKR, 0, 0x08);
140 rtwn_setbits_2(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_ENSIC, 0);
141
142 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
143 rtwn_write_2(sc, R92C_CR, 0);
144 rtwn_setbits_2(sc, R92C_CR, 0,
145 R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
146 R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
147 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
148 ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
149 R92C_CR_CALTMR_EN);
150
151 rtwn_write_4(sc, R92C_INT_MIG, 0);
152 rtwn_write_4(sc, R92C_MCUTST_1, 0);
153
154 return (0);
155 }
156
157 void
r88ee_power_off(struct rtwn_softc * sc)158 r88ee_power_off(struct rtwn_softc *sc)
159 {
160 uint8_t reg;
161 int ntries;
162
163 /* Disable any kind of TX reports. */
164 rtwn_setbits_1(sc, R88E_TX_RPT_CTRL,
165 R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA, 0);
166
167 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 1, 0xFF);
168
169 /* Move card to Low Power State. */
170 /* Block all Tx queues. */
171 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
172
173 for (ntries = 0; ntries < 10; ntries++) {
174 /* Should be zero if no packet is transmitting. */
175 if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
176 break;
177
178 rtwn_delay(sc, 5000);
179 }
180 if (ntries == 10) {
181 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
182 __func__);
183 return;
184 }
185
186 /* CCK and OFDM are disabled, and clock are gated. */
187 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
188
189 rtwn_delay(sc, 1);
190
191 /* Reset MAC TRX */
192 rtwn_write_1(sc, R92C_CR,
193 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
194 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN |
195 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN);
196
197 /* Disable h/w encryption. */
198 rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
199
200 /* Respond TxOK to scheduler */
201 rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, 0x20);
202
203 /* If firmware in ram code, do reset. */
204 #ifndef RTWN_WITHOUT_UCODE
205 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY)
206 r88e_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
207 #endif
208
209 /* Reset MCU ready status. */
210 rtwn_write_1(sc, R92C_MCUFWDL, 0);
211
212 /* Disable 32k. */
213 rtwn_setbits_1(sc, R88E_32K_CTRL, 0x01, 0);
214
215 /* Move card to Disabled state. */
216 /* Turn off RF. */
217 rtwn_write_1(sc, R92C_RF_CTRL, 0);
218
219 /* LDO Sleep mode. */
220 rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
221
222 /* Turn off MAC by HW state machine */
223 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
224 R92C_APS_FSMCO_APFM_OFF, 1);
225
226 for (ntries = 0; ntries < 10; ntries++) {
227 /* Wait until it will be disabled. */
228 if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
229 R92C_APS_FSMCO_APFM_OFF) == 0)
230 break;
231
232 rtwn_delay(sc, 5000);
233 }
234 if (ntries == 10) {
235 device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
236 __func__);
237 return;
238 }
239
240 /* schmit trigger */
241 rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
242
243 /* Reset MCU IO Wrapper. */
244 reg = rtwn_read_1(sc, R92C_RSV_CTRL + 1);
245 rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08);
246 rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08);
247
248 /* marked as 'For Power Consumption' code. */
249 rtwn_write_1(sc, R92C_GPIO_OUT, rtwn_read_1(sc, R92C_GPIO_IN));
250 rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
251
252 rtwn_write_1(sc, R92C_GPIO_IO_SEL,
253 rtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4);
254 rtwn_setbits_1(sc, R92C_GPIO_MOD, 0, 0x0f);
255
256 /* Set LNA, TRSW, EX_PA Pin to output mode. */
257 rtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808);
258 }
259
260 void
r88ee_post_init(struct rtwn_softc * sc)261 r88ee_post_init(struct rtwn_softc *sc)
262 {
263
264 /* Enable per-packet TX report. */
265 rtwn_setbits_1(sc, R88E_TX_RPT_CTRL, 0, R88E_TX_RPT1_ENA);
266
267 /* Disable Tx if MACID is not associated. */
268 rtwn_write_4(sc, R88E_MACID_NO_LINK, 0xffffffff);
269 rtwn_write_4(sc, R88E_MACID_NO_LINK + 4, 0xffffffff);
270 r88e_macid_enable_link(sc, RTWN_MACID_BC, 1);
271
272 /* Perform LO and IQ calibrations. */
273 r88e_iq_calib(sc);
274 /* Perform LC calibration. */
275 r92c_lc_calib(sc);
276
277 /* Enable Rx DMA */
278 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 1, 0);
279
280 if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) {
281 /* No support (yet?) for f/w rate adaptation. */
282 sc->sc_ratectl = RTWN_RATECTL_NET80211;
283 } else
284 sc->sc_ratectl = sc->sc_ratectl_sysctl;
285 }
286