1 /*
2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <drm/amdgpu_drm.h>
26 #include <drm/clients/drm_client_setup.h>
27 #include <drm/drm_drv.h>
28 #include <drm/drm_fbdev_ttm.h>
29 #include <drm/drm_gem.h>
30 #include <drm/drm_managed.h>
31 #include <drm/drm_pciids.h>
32 #include <drm/drm_probe_helper.h>
33 #include <drm/drm_vblank.h>
34
35 #include <linux/cc_platform.h>
36 #include <linux/dynamic_debug.h>
37 #include <linux/module.h>
38 #include <linux/mmu_notifier.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/suspend.h>
41 #include <linux/vga_switcheroo.h>
42
43 #include "amdgpu.h"
44 #include "amdgpu_amdkfd.h"
45 #include "amdgpu_dma_buf.h"
46 #include "amdgpu_drv.h"
47 #include "amdgpu_fdinfo.h"
48 #include "amdgpu_irq.h"
49 #include "amdgpu_psp.h"
50 #include "amdgpu_ras.h"
51 #include "amdgpu_reset.h"
52 #include "amdgpu_sched.h"
53 #include "amdgpu_xgmi.h"
54 #include "amdgpu_userq.h"
55 #include "amdgpu_userq_fence.h"
56 #include "../amdxcp/amdgpu_xcp_drv.h"
57
58 /*
59 * KMS wrapper.
60 * - 3.0.0 - initial driver
61 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
62 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
63 * at the end of IBs.
64 * - 3.3.0 - Add VM support for UVD on supported hardware.
65 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
66 * - 3.5.0 - Add support for new UVD_NO_OP register.
67 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
68 * - 3.7.0 - Add support for VCE clock list packet
69 * - 3.8.0 - Add support raster config init in the kernel
70 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
71 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
72 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
73 * - 3.12.0 - Add query for double offchip LDS buffers
74 * - 3.13.0 - Add PRT support
75 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
76 * - 3.15.0 - Export more gpu info for gfx9
77 * - 3.16.0 - Add reserved vmid support
78 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
79 * - 3.18.0 - Export gpu always on cu bitmap
80 * - 3.19.0 - Add support for UVD MJPEG decode
81 * - 3.20.0 - Add support for local BOs
82 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
83 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
84 * - 3.23.0 - Add query for VRAM lost counter
85 * - 3.24.0 - Add high priority compute support for gfx9
86 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
87 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
88 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
89 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
90 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
91 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
92 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
93 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
94 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
95 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
96 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
97 * - 3.36.0 - Allow reading more status registers on si/cik
98 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
99 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
100 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
101 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
102 * - 3.41.0 - Add video codec query
103 * - 3.42.0 - Add 16bpc fixed point display support
104 * - 3.43.0 - Add device hot plug/unplug support
105 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
106 * - 3.45.0 - Add context ioctl stable pstate interface
107 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
108 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
109 * - 3.48.0 - Add IP discovery version info to HW INFO
110 * - 3.49.0 - Add gang submit into CS IOCTL
111 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
112 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock
113 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
114 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields:
115 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size,
116 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi
117 * 3.53.0 - Support for GFX11 CP GFX shadowing
118 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support
119 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query
120 * - 3.56.0 - Update IB start address and size alignment for decode and encode
121 * - 3.57.0 - Compute tunneling on GFX10+
122 * - 3.58.0 - Add GFX12 DCC support
123 * - 3.59.0 - Cleared VRAM
124 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)
125 * - 3.61.0 - Contains fix for RV/PCO compute queues
126 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT
127 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size
128 * - 3.64.0 - Userq IP support query
129 */
130 #define KMS_DRIVER_MAJOR 3
131 #define KMS_DRIVER_MINOR 64
132 #define KMS_DRIVER_PATCHLEVEL 0
133
134 /*
135 * amdgpu.debug module options. Are all disabled by default
136 */
137 enum AMDGPU_DEBUG_MASK {
138 AMDGPU_DEBUG_VM = BIT(0),
139 AMDGPU_DEBUG_LARGEBAR = BIT(1),
140 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2),
141 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3),
142 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4),
143 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5),
144 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6),
145 AMDGPU_DEBUG_SMU_POOL = BIT(7),
146 AMDGPU_DEBUG_VM_USERPTR = BIT(8),
147 AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9),
148 AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10)
149 };
150
151 unsigned int amdgpu_vram_limit = UINT_MAX;
152 int amdgpu_vis_vram_limit;
153 int amdgpu_gart_size = -1; /* auto */
154 int amdgpu_gtt_size = -1; /* auto */
155 int amdgpu_moverate = -1; /* auto */
156 int amdgpu_audio = -1;
157 int amdgpu_disp_priority;
158 int amdgpu_hw_i2c;
159 int amdgpu_pcie_gen2 = -1;
160 int amdgpu_msi = -1;
161 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
162 int amdgpu_dpm = -1;
163 int amdgpu_fw_load_type = -1;
164 int amdgpu_aspm = -1;
165 int amdgpu_runtime_pm = -1;
166 uint amdgpu_ip_block_mask = 0xffffffff;
167 int amdgpu_bapm = -1;
168 int amdgpu_deep_color;
169 int amdgpu_vm_size = -1;
170 int amdgpu_vm_fragment_size = -1;
171 int amdgpu_vm_block_size = -1;
172 int amdgpu_vm_fault_stop;
173 int amdgpu_vm_update_mode = -1;
174 int amdgpu_exp_hw_support;
175 int amdgpu_dc = -1;
176 int amdgpu_sched_jobs = 32;
177 int amdgpu_sched_hw_submission = 2;
178 uint amdgpu_pcie_gen_cap;
179 uint amdgpu_pcie_lane_cap;
180 u64 amdgpu_cg_mask = 0xffffffffffffffff;
181 uint amdgpu_pg_mask = 0xffffffff;
182 uint amdgpu_sdma_phase_quantum = 32;
183 char *amdgpu_disable_cu;
184 char *amdgpu_virtual_display;
185 int amdgpu_enforce_isolation = -1;
186 int amdgpu_modeset = -1;
187
188 /* Specifies the default granularity for SVM, used in buffer
189 * migration and restoration of backing memory when handling
190 * recoverable page faults.
191 *
192 * The value is given as log(numPages(buffer)); for a 2 MiB
193 * buffer it computes to be 9
194 */
195 uint amdgpu_svm_default_granularity = 9;
196
197 /*
198 * OverDrive(bit 14) disabled by default
199 * GFX DCS(bit 19) disabled by default
200 */
201 uint amdgpu_pp_feature_mask = 0xfff7bfff;
202 uint amdgpu_force_long_training;
203 int amdgpu_lbpw = -1;
204 int amdgpu_compute_multipipe = -1;
205 int amdgpu_gpu_recovery = -1; /* auto */
206 int amdgpu_emu_mode;
207 uint amdgpu_smu_memory_pool_size;
208 int amdgpu_smu_pptable_id = -1;
209 /*
210 * FBC (bit 0) disabled by default
211 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
212 * - With this, for multiple monitors in sync(e.g. with the same model),
213 * mclk switching will be allowed. And the mclk will be not foced to the
214 * highest. That helps saving some idle power.
215 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
216 * PSR (bit 3) disabled by default
217 * EDP NO POWER SEQUENCING (bit 4) disabled by default
218 */
219 uint amdgpu_dc_feature_mask = 2;
220 uint amdgpu_dc_debug_mask;
221 uint amdgpu_dc_visual_confirm;
222 int amdgpu_async_gfx_ring = 1;
223 int amdgpu_mcbp = -1;
224 int amdgpu_discovery = -1;
225 int amdgpu_mes;
226 int amdgpu_mes_log_enable = 0;
227 int amdgpu_mes_kiq;
228 int amdgpu_uni_mes = 1;
229 int amdgpu_noretry = -1;
230 int amdgpu_force_asic_type = -1;
231 int amdgpu_tmz = -1; /* auto */
232 uint amdgpu_freesync_vid_mode;
233 int amdgpu_reset_method = -1; /* auto */
234 int amdgpu_num_kcq = -1;
235 int amdgpu_smartshift_bias;
236 int amdgpu_use_xgmi_p2p = 1;
237 int amdgpu_vcnfw_log;
238 int amdgpu_sg_display = -1; /* auto */
239 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
240 int amdgpu_umsch_mm;
241 int amdgpu_seamless = -1; /* auto */
242 uint amdgpu_debug_mask;
243 int amdgpu_agp = -1; /* auto */
244 int amdgpu_wbrf = -1;
245 int amdgpu_damage_clips = -1; /* auto */
246 int amdgpu_umsch_mm_fwlog;
247 int amdgpu_rebar = -1; /* auto */
248 int amdgpu_user_queue = -1;
249
250 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
251 "DRM_UT_CORE",
252 "DRM_UT_DRIVER",
253 "DRM_UT_KMS",
254 "DRM_UT_PRIME",
255 "DRM_UT_ATOMIC",
256 "DRM_UT_VBL",
257 "DRM_UT_STATE",
258 "DRM_UT_LEASE",
259 "DRM_UT_DP",
260 "DRM_UT_DRMRES");
261
262 struct amdgpu_mgpu_info mgpu_info = {
263 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
264 };
265 int amdgpu_ras_enable = -1;
266 uint amdgpu_ras_mask = 0xffffffff;
267 int amdgpu_bad_page_threshold = -1;
268 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
269 .timeout_fatal_disable = false,
270 .period = 0x0, /* default to 0x0 (timeout disable) */
271 };
272
273 /**
274 * DOC: vramlimit (int)
275 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
276 */
277 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
278 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
279
280 /**
281 * DOC: vis_vramlimit (int)
282 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
283 */
284 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
285 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
286
287 /**
288 * DOC: gartsize (uint)
289 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing.
290 * The default is -1 (The size depends on asic).
291 */
292 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
293 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
294
295 /**
296 * DOC: gttsize (int)
297 * Restrict the size of GTT domain (for userspace use) in MiB for testing.
298 * The default is -1 (Use value specified by TTM).
299 * This parameter is deprecated and will be removed in the future.
300 */
301 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
302 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
303
304 /**
305 * DOC: moverate (int)
306 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
307 */
308 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
309 module_param_named(moverate, amdgpu_moverate, int, 0600);
310
311 /**
312 * DOC: audio (int)
313 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
314 */
315 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
316 module_param_named(audio, amdgpu_audio, int, 0444);
317
318 /**
319 * DOC: disp_priority (int)
320 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
321 */
322 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
323 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
324
325 /**
326 * DOC: hw_i2c (int)
327 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
328 */
329 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
330 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
331
332 /**
333 * DOC: pcie_gen2 (int)
334 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
335 */
336 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
337 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
338
339 /**
340 * DOC: msi (int)
341 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
342 */
343 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
344 module_param_named(msi, amdgpu_msi, int, 0444);
345
346 /**
347 * DOC: svm_default_granularity (uint)
348 * Used in buffer migration and handling of recoverable page faults
349 */
350 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB");
351 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644);
352
353 /**
354 * DOC: lockup_timeout (string)
355 * Set GPU scheduler timeout value in ms.
356 *
357 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
358 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
359 * to the default timeout.
360 *
361 * - With one value specified, the setting will apply to all non-compute jobs.
362 * - With multiple values specified, the first one will be for GFX.
363 * The second one is for Compute. The third and fourth ones are
364 * for SDMA and Video.
365 *
366 * By default(with no lockup_timeout settings), the timeout for all jobs is 10000.
367 */
368 MODULE_PARM_DESC(lockup_timeout,
369 "GPU lockup timeout in ms (default: 10000 for all jobs. "
370 "0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
371 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
372 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
373
374 /**
375 * DOC: dpm (int)
376 * Override for dynamic power management setting
377 * (0 = disable, 1 = enable)
378 * The default is -1 (auto).
379 */
380 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
381 module_param_named(dpm, amdgpu_dpm, int, 0444);
382
383 /**
384 * DOC: fw_load_type (int)
385 * Set different firmware loading type for debugging, if supported.
386 * Set to 0 to force direct loading if supported by the ASIC. Set
387 * to -1 to select the default loading mode for the ASIC, as defined
388 * by the driver. The default is -1 (auto).
389 */
390 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
391 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
392
393 /**
394 * DOC: aspm (int)
395 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
396 */
397 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
398 module_param_named(aspm, amdgpu_aspm, int, 0444);
399
400 /**
401 * DOC: runpm (int)
402 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
403 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
404 * Setting the value to 0 disables this functionality.
405 * Setting the value to -2 is auto enabled with power down when displays are attached.
406 */
407 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)");
408 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
409
410 /**
411 * DOC: ip_block_mask (uint)
412 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
413 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
414 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
415 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
416 */
417 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
418 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
419
420 /**
421 * DOC: bapm (int)
422 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
423 * The default -1 (auto, enabled)
424 */
425 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
426 module_param_named(bapm, amdgpu_bapm, int, 0444);
427
428 /**
429 * DOC: deep_color (int)
430 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
431 */
432 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
433 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
434
435 /**
436 * DOC: vm_size (int)
437 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
438 */
439 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
440 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
441
442 /**
443 * DOC: vm_fragment_size (int)
444 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
445 */
446 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
447 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
448
449 /**
450 * DOC: vm_block_size (int)
451 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
452 */
453 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
454 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
455
456 /**
457 * DOC: vm_fault_stop (int)
458 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
459 */
460 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
461 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
462
463 /**
464 * DOC: vm_update_mode (int)
465 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
466 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
467 */
468 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
469 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
470
471 /**
472 * DOC: exp_hw_support (int)
473 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
474 */
475 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
476 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
477
478 /**
479 * DOC: dc (int)
480 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
481 */
482 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
483 module_param_named(dc, amdgpu_dc, int, 0444);
484
485 /**
486 * DOC: sched_jobs (int)
487 * Override the max number of jobs supported in the sw queue. The default is 32.
488 */
489 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
490 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
491
492 /**
493 * DOC: sched_hw_submission (int)
494 * Override the max number of HW submissions. The default is 2.
495 */
496 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
497 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
498
499 /**
500 * DOC: ppfeaturemask (hexint)
501 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
502 * The default is the current set of stable power features.
503 */
504 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
505 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
506
507 /**
508 * DOC: forcelongtraining (uint)
509 * Force long memory training in resume.
510 * The default is zero, indicates short training in resume.
511 */
512 MODULE_PARM_DESC(forcelongtraining, "force memory long training");
513 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
514
515 /**
516 * DOC: pcie_gen_cap (uint)
517 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
518 * The default is 0 (automatic for each asic).
519 */
520 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
521 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
522
523 /**
524 * DOC: pcie_lane_cap (uint)
525 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
526 * The default is 0 (automatic for each asic).
527 */
528 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
529 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
530
531 /**
532 * DOC: cg_mask (ullong)
533 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
534 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
535 */
536 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
537 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
538
539 /**
540 * DOC: pg_mask (uint)
541 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
542 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
543 */
544 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
545 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
546
547 /**
548 * DOC: sdma_phase_quantum (uint)
549 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
550 */
551 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
552 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
553
554 /**
555 * DOC: disable_cu (charp)
556 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
557 */
558 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
559 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
560
561 /**
562 * DOC: virtual_display (charp)
563 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
564 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
565 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
566 * device at 26:00.0. The default is NULL.
567 */
568 MODULE_PARM_DESC(virtual_display,
569 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
570 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
571
572 /**
573 * DOC: lbpw (int)
574 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
575 */
576 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
577 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
578
579 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
580 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
581
582 /**
583 * DOC: gpu_recovery (int)
584 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
585 */
586 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
587 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
588
589 /**
590 * DOC: emu_mode (int)
591 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
592 */
593 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
594 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444);
595
596 /**
597 * DOC: ras_enable (int)
598 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
599 */
600 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
601 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
602
603 /**
604 * DOC: ras_mask (uint)
605 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
606 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
607 */
608 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
609 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
610
611 /**
612 * DOC: timeout_fatal_disable (bool)
613 * Disable Watchdog timeout fatal error event
614 */
615 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
616 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
617
618 /**
619 * DOC: timeout_period (uint)
620 * Modify the watchdog timeout max_cycles as (1 << period)
621 */
622 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
623 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
624
625 /**
626 * DOC: si_support (int)
627 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
628 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
629 * otherwise using amdgpu driver.
630 */
631 #ifdef CONFIG_DRM_AMDGPU_SI
632
633 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
634 int amdgpu_si_support;
635 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
636 #else
637 int amdgpu_si_support = 1;
638 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
639 #endif
640
641 module_param_named(si_support, amdgpu_si_support, int, 0444);
642 #endif
643
644 /**
645 * DOC: cik_support (int)
646 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
647 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
648 * otherwise using amdgpu driver.
649 */
650 #ifdef CONFIG_DRM_AMDGPU_CIK
651
652 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
653 int amdgpu_cik_support;
654 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
655 #else
656 int amdgpu_cik_support = 1;
657 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
658 #endif
659
660 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
661 #endif
662
663 /**
664 * DOC: smu_memory_pool_size (uint)
665 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
666 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
667 */
668 MODULE_PARM_DESC(smu_memory_pool_size,
669 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
670 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
671
672 /**
673 * DOC: async_gfx_ring (int)
674 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
675 */
676 MODULE_PARM_DESC(async_gfx_ring,
677 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
678 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
679
680 /**
681 * DOC: mcbp (int)
682 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default))
683 */
684 MODULE_PARM_DESC(mcbp,
685 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)");
686 module_param_named(mcbp, amdgpu_mcbp, int, 0444);
687
688 /**
689 * DOC: discovery (int)
690 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
691 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
692 */
693 MODULE_PARM_DESC(discovery,
694 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
695 module_param_named(discovery, amdgpu_discovery, int, 0444);
696
697 /**
698 * DOC: mes (int)
699 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
700 * (0 = disabled (default), 1 = enabled)
701 */
702 MODULE_PARM_DESC(mes,
703 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
704 module_param_named(mes, amdgpu_mes, int, 0444);
705
706 /**
707 * DOC: mes_log_enable (int)
708 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log.
709 * (0 = disabled (default), 1 = enabled)
710 */
711 MODULE_PARM_DESC(mes_log_enable,
712 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)");
713 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444);
714
715 /**
716 * DOC: mes_kiq (int)
717 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
718 * (0 = disabled (default), 1 = enabled)
719 */
720 MODULE_PARM_DESC(mes_kiq,
721 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
722 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
723
724 /**
725 * DOC: uni_mes (int)
726 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler.
727 * (0 = disabled (default), 1 = enabled)
728 */
729 MODULE_PARM_DESC(uni_mes,
730 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)");
731 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444);
732
733 /**
734 * DOC: noretry (int)
735 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
736 * do not support per-process XNACK this also disables retry page faults.
737 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
738 */
739 MODULE_PARM_DESC(noretry,
740 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
741 module_param_named(noretry, amdgpu_noretry, int, 0644);
742
743 /**
744 * DOC: force_asic_type (int)
745 * A non negative value used to specify the asic type for all supported GPUs.
746 */
747 MODULE_PARM_DESC(force_asic_type,
748 "A non negative value used to specify the asic type for all supported GPUs");
749 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444);
750
751 /**
752 * DOC: use_xgmi_p2p (int)
753 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
754 */
755 MODULE_PARM_DESC(use_xgmi_p2p,
756 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
757 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
758
759
760 #ifdef CONFIG_HSA_AMD
761 /**
762 * DOC: sched_policy (int)
763 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
764 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
765 * assigns queues to HQDs.
766 */
767 int sched_policy = KFD_SCHED_POLICY_HWS;
768 module_param_unsafe(sched_policy, int, 0444);
769 MODULE_PARM_DESC(sched_policy,
770 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
771
772 /**
773 * DOC: hws_max_conc_proc (int)
774 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
775 * number of VMIDs assigned to the HWS, which is also the default.
776 */
777 int hws_max_conc_proc = -1;
778 module_param(hws_max_conc_proc, int, 0444);
779 MODULE_PARM_DESC(hws_max_conc_proc,
780 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
781
782 /**
783 * DOC: cwsr_enable (int)
784 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
785 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
786 * disables it.
787 */
788 int cwsr_enable = 1;
789 module_param(cwsr_enable, int, 0444);
790 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
791
792 /**
793 * DOC: max_num_of_queues_per_device (int)
794 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
795 * is 4096.
796 */
797 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
798 module_param(max_num_of_queues_per_device, int, 0444);
799 MODULE_PARM_DESC(max_num_of_queues_per_device,
800 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
801
802 /**
803 * DOC: send_sigterm (int)
804 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
805 * but just print errors on dmesg. Setting 1 enables sending sigterm.
806 */
807 int send_sigterm;
808 module_param(send_sigterm, int, 0444);
809 MODULE_PARM_DESC(send_sigterm,
810 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
811
812 /**
813 * DOC: halt_if_hws_hang (int)
814 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
815 * Setting 1 enables halt on hang.
816 */
817 int halt_if_hws_hang;
818 module_param_unsafe(halt_if_hws_hang, int, 0644);
819 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
820
821 /**
822 * DOC: hws_gws_support(bool)
823 * Assume that HWS supports GWS barriers regardless of what firmware version
824 * check says. Default value: false (rely on MEC2 firmware version check).
825 */
826 bool hws_gws_support;
827 module_param_unsafe(hws_gws_support, bool, 0444);
828 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
829
830 /**
831 * DOC: queue_preemption_timeout_ms (int)
832 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
833 */
834 int queue_preemption_timeout_ms = 9000;
835 module_param(queue_preemption_timeout_ms, int, 0644);
836 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
837
838 /**
839 * DOC: debug_evictions(bool)
840 * Enable extra debug messages to help determine the cause of evictions
841 */
842 bool debug_evictions;
843 module_param(debug_evictions, bool, 0644);
844 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
845
846 /**
847 * DOC: no_system_mem_limit(bool)
848 * Disable system memory limit, to support multiple process shared memory
849 */
850 bool no_system_mem_limit;
851 module_param(no_system_mem_limit, bool, 0644);
852 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
853
854 /**
855 * DOC: no_queue_eviction_on_vm_fault (int)
856 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
857 */
858 int amdgpu_no_queue_eviction_on_vm_fault;
859 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
860 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
861 #endif
862
863 /**
864 * DOC: mtype_local (int)
865 */
866 int amdgpu_mtype_local;
867 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)");
868 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444);
869
870 /**
871 * DOC: pcie_p2p (bool)
872 * Enable PCIe P2P (requires large-BAR). Default value: true (on)
873 */
874 #ifdef CONFIG_HSA_AMD_P2P
875 bool pcie_p2p = true;
876 module_param(pcie_p2p, bool, 0444);
877 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
878 #endif
879
880 /**
881 * DOC: dcfeaturemask (uint)
882 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
883 * The default is the current set of stable display features.
884 */
885 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
886 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
887
888 /**
889 * DOC: dcdebugmask (uint)
890 * Display debug options. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
891 */
892 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
893 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
894
895 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
896 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
897
898 /**
899 * DOC: abmlevel (uint)
900 * Override the default ABM (Adaptive Backlight Management) level used for DC
901 * enabled hardware. Requires DMCU to be supported and loaded.
902 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
903 * default. Values 1-4 control the maximum allowable brightness reduction via
904 * the ABM algorithm, with 1 being the least reduction and 4 being the most
905 * reduction.
906 *
907 * Defaults to -1, or auto. Userspace can only override this level after
908 * boot if it's set to auto.
909 */
910 int amdgpu_dm_abm_level = -1;
911 MODULE_PARM_DESC(abmlevel,
912 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))");
913 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444);
914
915 int amdgpu_backlight = -1;
916 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
917 module_param_named(backlight, amdgpu_backlight, bint, 0444);
918
919 /**
920 * DOC: damageclips (int)
921 * Enable or disable damage clips support. If damage clips support is disabled,
922 * we will force full frame updates, irrespective of what user space sends to
923 * us.
924 *
925 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected).
926 */
927 MODULE_PARM_DESC(damageclips,
928 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))");
929 module_param_named(damageclips, amdgpu_damage_clips, int, 0444);
930
931 /**
932 * DOC: tmz (int)
933 * Trusted Memory Zone (TMZ) is a method to protect data being written
934 * to or read from memory.
935 *
936 * The default value: 0 (off). TODO: change to auto till it is completed.
937 */
938 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
939 module_param_named(tmz, amdgpu_tmz, int, 0444);
940
941 /**
942 * DOC: freesync_video (uint)
943 * Enable the optimization to adjust front porch timing to achieve seamless
944 * mode change experience when setting a freesync supported mode for which full
945 * modeset is not needed.
946 *
947 * The Display Core will add a set of modes derived from the base FreeSync
948 * video mode into the corresponding connector's mode list based on commonly
949 * used refresh rates and VRR range of the connected display, when users enable
950 * this feature. From the userspace perspective, they can see a seamless mode
951 * change experience when the change between different refresh rates under the
952 * same resolution. Additionally, userspace applications such as Video playback
953 * can read this modeset list and change the refresh rate based on the video
954 * frame rate. Finally, the userspace can also derive an appropriate mode for a
955 * particular refresh rate based on the FreeSync Mode and add it to the
956 * connector's mode list.
957 *
958 * Note: This is an experimental feature.
959 *
960 * The default value: 0 (off).
961 */
962 MODULE_PARM_DESC(
963 freesync_video,
964 "Adds additional modes via VRR for refresh changes without a full modeset (0 = off (default), 1 = on)");
965 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
966
967 /**
968 * DOC: reset_method (int)
969 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
970 */
971 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
972 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644);
973
974 /**
975 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
976 * threshold value of faulty pages detected by RAS ECC, which may
977 * result in the GPU entering bad status when the number of total
978 * faulty pages by ECC exceeds the threshold value.
979 */
980 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)");
981 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
982
983 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
984 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
985
986 /**
987 * DOC: vcnfw_log (int)
988 * Enable vcnfw log output for debugging, the default is disabled.
989 */
990 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
991 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
992
993 /**
994 * DOC: sg_display (int)
995 * Disable S/G (scatter/gather) display (i.e., display from system memory).
996 * This option is only relevant on APUs. Set this option to 0 to disable
997 * S/G display if you experience flickering or other issues under memory
998 * pressure and report the issue.
999 */
1000 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
1001 module_param_named(sg_display, amdgpu_sg_display, int, 0444);
1002
1003 /**
1004 * DOC: umsch_mm (int)
1005 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE.
1006 * (0 = disabled (default), 1 = enabled)
1007 */
1008 MODULE_PARM_DESC(umsch_mm,
1009 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)");
1010 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444);
1011
1012 /**
1013 * DOC: umsch_mm_fwlog (int)
1014 * Enable umschfw log output for debugging, the default is disabled.
1015 */
1016 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)");
1017 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444);
1018
1019 /**
1020 * DOC: smu_pptable_id (int)
1021 * Used to override pptable id. id = 0 use VBIOS pptable.
1022 * id > 0 use the soft pptable with specicfied id.
1023 */
1024 MODULE_PARM_DESC(smu_pptable_id,
1025 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
1026 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
1027
1028 /**
1029 * DOC: partition_mode (int)
1030 * Used to override the default SPX mode.
1031 */
1032 MODULE_PARM_DESC(
1033 user_partt_mode,
1034 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \
1035 0 = AMDGPU_SPX_PARTITION_MODE, \
1036 1 = AMDGPU_DPX_PARTITION_MODE, \
1037 2 = AMDGPU_TPX_PARTITION_MODE, \
1038 3 = AMDGPU_QPX_PARTITION_MODE, \
1039 4 = AMDGPU_CPX_PARTITION_MODE)");
1040 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);
1041
1042
1043 /**
1044 * DOC: enforce_isolation (int)
1045 * enforce process isolation between graphics and compute.
1046 * (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)
1047 */
1048 module_param_named(enforce_isolation, amdgpu_enforce_isolation, int, 0444);
1049 MODULE_PARM_DESC(enforce_isolation,
1050 "enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)");
1051
1052 /**
1053 * DOC: modeset (int)
1054 * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto).
1055 */
1056 MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)");
1057 module_param_named(modeset, amdgpu_modeset, int, 0444);
1058
1059 /**
1060 * DOC: seamless (int)
1061 * Seamless boot will keep the image on the screen during the boot process.
1062 */
1063 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)");
1064 module_param_named(seamless, amdgpu_seamless, int, 0444);
1065
1066 /**
1067 * DOC: debug_mask (uint)
1068 * Debug options for amdgpu, work as a binary mask with the following options:
1069 *
1070 * - 0x1: Debug VM handling
1071 * - 0x2: Enable simulating large-bar capability on non-large bar system. This
1072 * limits the VRAM size reported to ROCm applications to the visible
1073 * size, usually 256MB.
1074 * - 0x4: Disable GPU soft recovery, always do a full reset
1075 * - 0x8: Use VRAM for firmware loading
1076 * - 0x10: Enable ACA based RAS logging
1077 * - 0x20: Enable experimental resets
1078 * - 0x40: Disable ring resets
1079 * - 0x80: Use VRAM for SMU pool
1080 */
1081 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default");
1082 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444);
1083
1084 /**
1085 * DOC: agp (int)
1086 * Enable the AGP aperture. This provides an aperture in the GPU's internal
1087 * address space for direct access to system memory. Note that these accesses
1088 * are non-snooped, so they are only used for access to uncached memory.
1089 */
1090 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)");
1091 module_param_named(agp, amdgpu_agp, int, 0444);
1092
1093 /**
1094 * DOC: wbrf (int)
1095 * Enable Wifi RFI interference mitigation feature.
1096 * Due to electrical and mechanical constraints there may be likely interference of
1097 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio
1098 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference,
1099 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based
1100 * on active list of frequencies in-use (to be avoided) as part of initial setting or
1101 * P-state transition. However, there may be potential performance impact with this
1102 * feature enabled.
1103 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported))
1104 */
1105 MODULE_PARM_DESC(wbrf,
1106 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)");
1107 module_param_named(wbrf, amdgpu_wbrf, int, 0444);
1108
1109 /**
1110 * DOC: rebar (int)
1111 * Allow BAR resizing. Disable this to prevent the driver from attempting
1112 * to resize the BAR if the GPU supports it and there is available MMIO space.
1113 * Note that this just prevents the driver from resizing the BAR. The BIOS
1114 * may have already resized the BAR at boot time.
1115 */
1116 MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)");
1117 module_param_named(rebar, amdgpu_rebar, int, 0444);
1118
1119 /**
1120 * DOC: user_queue (int)
1121 * Enable user queues on systems that support user queues. Possible values:
1122 *
1123 * - -1 = auto (ASIC specific default)
1124 * - 0 = user queues disabled
1125 * - 1 = user queues enabled and kernel queues enabled (if supported)
1126 * - 2 = user queues enabled and kernel queues disabled
1127 */
1128 MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)");
1129 module_param_named(user_queue, amdgpu_user_queue, int, 0444);
1130
1131 /* These devices are not supported by amdgpu.
1132 * They are supported by the mach64, r128, radeon drivers
1133 */
1134 static const u16 amdgpu_unsupported_pciidlist[] = {
1135 /* mach64 */
1136 0x4354,
1137 0x4358,
1138 0x4554,
1139 0x4742,
1140 0x4744,
1141 0x4749,
1142 0x474C,
1143 0x474D,
1144 0x474E,
1145 0x474F,
1146 0x4750,
1147 0x4751,
1148 0x4752,
1149 0x4753,
1150 0x4754,
1151 0x4755,
1152 0x4756,
1153 0x4757,
1154 0x4758,
1155 0x4759,
1156 0x475A,
1157 0x4C42,
1158 0x4C44,
1159 0x4C47,
1160 0x4C49,
1161 0x4C4D,
1162 0x4C4E,
1163 0x4C50,
1164 0x4C51,
1165 0x4C52,
1166 0x4C53,
1167 0x5654,
1168 0x5655,
1169 0x5656,
1170 /* r128 */
1171 0x4c45,
1172 0x4c46,
1173 0x4d46,
1174 0x4d4c,
1175 0x5041,
1176 0x5042,
1177 0x5043,
1178 0x5044,
1179 0x5045,
1180 0x5046,
1181 0x5047,
1182 0x5048,
1183 0x5049,
1184 0x504A,
1185 0x504B,
1186 0x504C,
1187 0x504D,
1188 0x504E,
1189 0x504F,
1190 0x5050,
1191 0x5051,
1192 0x5052,
1193 0x5053,
1194 0x5054,
1195 0x5055,
1196 0x5056,
1197 0x5057,
1198 0x5058,
1199 0x5245,
1200 0x5246,
1201 0x5247,
1202 0x524b,
1203 0x524c,
1204 0x534d,
1205 0x5446,
1206 0x544C,
1207 0x5452,
1208 /* radeon */
1209 0x3150,
1210 0x3151,
1211 0x3152,
1212 0x3154,
1213 0x3155,
1214 0x3E50,
1215 0x3E54,
1216 0x4136,
1217 0x4137,
1218 0x4144,
1219 0x4145,
1220 0x4146,
1221 0x4147,
1222 0x4148,
1223 0x4149,
1224 0x414A,
1225 0x414B,
1226 0x4150,
1227 0x4151,
1228 0x4152,
1229 0x4153,
1230 0x4154,
1231 0x4155,
1232 0x4156,
1233 0x4237,
1234 0x4242,
1235 0x4336,
1236 0x4337,
1237 0x4437,
1238 0x4966,
1239 0x4967,
1240 0x4A48,
1241 0x4A49,
1242 0x4A4A,
1243 0x4A4B,
1244 0x4A4C,
1245 0x4A4D,
1246 0x4A4E,
1247 0x4A4F,
1248 0x4A50,
1249 0x4A54,
1250 0x4B48,
1251 0x4B49,
1252 0x4B4A,
1253 0x4B4B,
1254 0x4B4C,
1255 0x4C57,
1256 0x4C58,
1257 0x4C59,
1258 0x4C5A,
1259 0x4C64,
1260 0x4C66,
1261 0x4C67,
1262 0x4E44,
1263 0x4E45,
1264 0x4E46,
1265 0x4E47,
1266 0x4E48,
1267 0x4E49,
1268 0x4E4A,
1269 0x4E4B,
1270 0x4E50,
1271 0x4E51,
1272 0x4E52,
1273 0x4E53,
1274 0x4E54,
1275 0x4E56,
1276 0x5144,
1277 0x5145,
1278 0x5146,
1279 0x5147,
1280 0x5148,
1281 0x514C,
1282 0x514D,
1283 0x5157,
1284 0x5158,
1285 0x5159,
1286 0x515A,
1287 0x515E,
1288 0x5460,
1289 0x5462,
1290 0x5464,
1291 0x5548,
1292 0x5549,
1293 0x554A,
1294 0x554B,
1295 0x554C,
1296 0x554D,
1297 0x554E,
1298 0x554F,
1299 0x5550,
1300 0x5551,
1301 0x5552,
1302 0x5554,
1303 0x564A,
1304 0x564B,
1305 0x564F,
1306 0x5652,
1307 0x5653,
1308 0x5657,
1309 0x5834,
1310 0x5835,
1311 0x5954,
1312 0x5955,
1313 0x5974,
1314 0x5975,
1315 0x5960,
1316 0x5961,
1317 0x5962,
1318 0x5964,
1319 0x5965,
1320 0x5969,
1321 0x5a41,
1322 0x5a42,
1323 0x5a61,
1324 0x5a62,
1325 0x5b60,
1326 0x5b62,
1327 0x5b63,
1328 0x5b64,
1329 0x5b65,
1330 0x5c61,
1331 0x5c63,
1332 0x5d48,
1333 0x5d49,
1334 0x5d4a,
1335 0x5d4c,
1336 0x5d4d,
1337 0x5d4e,
1338 0x5d4f,
1339 0x5d50,
1340 0x5d52,
1341 0x5d57,
1342 0x5e48,
1343 0x5e4a,
1344 0x5e4b,
1345 0x5e4c,
1346 0x5e4d,
1347 0x5e4f,
1348 0x6700,
1349 0x6701,
1350 0x6702,
1351 0x6703,
1352 0x6704,
1353 0x6705,
1354 0x6706,
1355 0x6707,
1356 0x6708,
1357 0x6709,
1358 0x6718,
1359 0x6719,
1360 0x671c,
1361 0x671d,
1362 0x671f,
1363 0x6720,
1364 0x6721,
1365 0x6722,
1366 0x6723,
1367 0x6724,
1368 0x6725,
1369 0x6726,
1370 0x6727,
1371 0x6728,
1372 0x6729,
1373 0x6738,
1374 0x6739,
1375 0x673e,
1376 0x6740,
1377 0x6741,
1378 0x6742,
1379 0x6743,
1380 0x6744,
1381 0x6745,
1382 0x6746,
1383 0x6747,
1384 0x6748,
1385 0x6749,
1386 0x674A,
1387 0x6750,
1388 0x6751,
1389 0x6758,
1390 0x6759,
1391 0x675B,
1392 0x675D,
1393 0x675F,
1394 0x6760,
1395 0x6761,
1396 0x6762,
1397 0x6763,
1398 0x6764,
1399 0x6765,
1400 0x6766,
1401 0x6767,
1402 0x6768,
1403 0x6770,
1404 0x6771,
1405 0x6772,
1406 0x6778,
1407 0x6779,
1408 0x677B,
1409 0x6840,
1410 0x6841,
1411 0x6842,
1412 0x6843,
1413 0x6849,
1414 0x684C,
1415 0x6850,
1416 0x6858,
1417 0x6859,
1418 0x6880,
1419 0x6888,
1420 0x6889,
1421 0x688A,
1422 0x688C,
1423 0x688D,
1424 0x6898,
1425 0x6899,
1426 0x689b,
1427 0x689c,
1428 0x689d,
1429 0x689e,
1430 0x68a0,
1431 0x68a1,
1432 0x68a8,
1433 0x68a9,
1434 0x68b0,
1435 0x68b8,
1436 0x68b9,
1437 0x68ba,
1438 0x68be,
1439 0x68bf,
1440 0x68c0,
1441 0x68c1,
1442 0x68c7,
1443 0x68c8,
1444 0x68c9,
1445 0x68d8,
1446 0x68d9,
1447 0x68da,
1448 0x68de,
1449 0x68e0,
1450 0x68e1,
1451 0x68e4,
1452 0x68e5,
1453 0x68e8,
1454 0x68e9,
1455 0x68f1,
1456 0x68f2,
1457 0x68f8,
1458 0x68f9,
1459 0x68fa,
1460 0x68fe,
1461 0x7100,
1462 0x7101,
1463 0x7102,
1464 0x7103,
1465 0x7104,
1466 0x7105,
1467 0x7106,
1468 0x7108,
1469 0x7109,
1470 0x710A,
1471 0x710B,
1472 0x710C,
1473 0x710E,
1474 0x710F,
1475 0x7140,
1476 0x7141,
1477 0x7142,
1478 0x7143,
1479 0x7144,
1480 0x7145,
1481 0x7146,
1482 0x7147,
1483 0x7149,
1484 0x714A,
1485 0x714B,
1486 0x714C,
1487 0x714D,
1488 0x714E,
1489 0x714F,
1490 0x7151,
1491 0x7152,
1492 0x7153,
1493 0x715E,
1494 0x715F,
1495 0x7180,
1496 0x7181,
1497 0x7183,
1498 0x7186,
1499 0x7187,
1500 0x7188,
1501 0x718A,
1502 0x718B,
1503 0x718C,
1504 0x718D,
1505 0x718F,
1506 0x7193,
1507 0x7196,
1508 0x719B,
1509 0x719F,
1510 0x71C0,
1511 0x71C1,
1512 0x71C2,
1513 0x71C3,
1514 0x71C4,
1515 0x71C5,
1516 0x71C6,
1517 0x71C7,
1518 0x71CD,
1519 0x71CE,
1520 0x71D2,
1521 0x71D4,
1522 0x71D5,
1523 0x71D6,
1524 0x71DA,
1525 0x71DE,
1526 0x7200,
1527 0x7210,
1528 0x7211,
1529 0x7240,
1530 0x7243,
1531 0x7244,
1532 0x7245,
1533 0x7246,
1534 0x7247,
1535 0x7248,
1536 0x7249,
1537 0x724A,
1538 0x724B,
1539 0x724C,
1540 0x724D,
1541 0x724E,
1542 0x724F,
1543 0x7280,
1544 0x7281,
1545 0x7283,
1546 0x7284,
1547 0x7287,
1548 0x7288,
1549 0x7289,
1550 0x728B,
1551 0x728C,
1552 0x7290,
1553 0x7291,
1554 0x7293,
1555 0x7297,
1556 0x7834,
1557 0x7835,
1558 0x791e,
1559 0x791f,
1560 0x793f,
1561 0x7941,
1562 0x7942,
1563 0x796c,
1564 0x796d,
1565 0x796e,
1566 0x796f,
1567 0x9400,
1568 0x9401,
1569 0x9402,
1570 0x9403,
1571 0x9405,
1572 0x940A,
1573 0x940B,
1574 0x940F,
1575 0x94A0,
1576 0x94A1,
1577 0x94A3,
1578 0x94B1,
1579 0x94B3,
1580 0x94B4,
1581 0x94B5,
1582 0x94B9,
1583 0x9440,
1584 0x9441,
1585 0x9442,
1586 0x9443,
1587 0x9444,
1588 0x9446,
1589 0x944A,
1590 0x944B,
1591 0x944C,
1592 0x944E,
1593 0x9450,
1594 0x9452,
1595 0x9456,
1596 0x945A,
1597 0x945B,
1598 0x945E,
1599 0x9460,
1600 0x9462,
1601 0x946A,
1602 0x946B,
1603 0x947A,
1604 0x947B,
1605 0x9480,
1606 0x9487,
1607 0x9488,
1608 0x9489,
1609 0x948A,
1610 0x948F,
1611 0x9490,
1612 0x9491,
1613 0x9495,
1614 0x9498,
1615 0x949C,
1616 0x949E,
1617 0x949F,
1618 0x94C0,
1619 0x94C1,
1620 0x94C3,
1621 0x94C4,
1622 0x94C5,
1623 0x94C6,
1624 0x94C7,
1625 0x94C8,
1626 0x94C9,
1627 0x94CB,
1628 0x94CC,
1629 0x94CD,
1630 0x9500,
1631 0x9501,
1632 0x9504,
1633 0x9505,
1634 0x9506,
1635 0x9507,
1636 0x9508,
1637 0x9509,
1638 0x950F,
1639 0x9511,
1640 0x9515,
1641 0x9517,
1642 0x9519,
1643 0x9540,
1644 0x9541,
1645 0x9542,
1646 0x954E,
1647 0x954F,
1648 0x9552,
1649 0x9553,
1650 0x9555,
1651 0x9557,
1652 0x955f,
1653 0x9580,
1654 0x9581,
1655 0x9583,
1656 0x9586,
1657 0x9587,
1658 0x9588,
1659 0x9589,
1660 0x958A,
1661 0x958B,
1662 0x958C,
1663 0x958D,
1664 0x958E,
1665 0x958F,
1666 0x9590,
1667 0x9591,
1668 0x9593,
1669 0x9595,
1670 0x9596,
1671 0x9597,
1672 0x9598,
1673 0x9599,
1674 0x959B,
1675 0x95C0,
1676 0x95C2,
1677 0x95C4,
1678 0x95C5,
1679 0x95C6,
1680 0x95C7,
1681 0x95C9,
1682 0x95CC,
1683 0x95CD,
1684 0x95CE,
1685 0x95CF,
1686 0x9610,
1687 0x9611,
1688 0x9612,
1689 0x9613,
1690 0x9614,
1691 0x9615,
1692 0x9616,
1693 0x9640,
1694 0x9641,
1695 0x9642,
1696 0x9643,
1697 0x9644,
1698 0x9645,
1699 0x9647,
1700 0x9648,
1701 0x9649,
1702 0x964a,
1703 0x964b,
1704 0x964c,
1705 0x964e,
1706 0x964f,
1707 0x9710,
1708 0x9711,
1709 0x9712,
1710 0x9713,
1711 0x9714,
1712 0x9715,
1713 0x9802,
1714 0x9803,
1715 0x9804,
1716 0x9805,
1717 0x9806,
1718 0x9807,
1719 0x9808,
1720 0x9809,
1721 0x980A,
1722 0x9900,
1723 0x9901,
1724 0x9903,
1725 0x9904,
1726 0x9905,
1727 0x9906,
1728 0x9907,
1729 0x9908,
1730 0x9909,
1731 0x990A,
1732 0x990B,
1733 0x990C,
1734 0x990D,
1735 0x990E,
1736 0x990F,
1737 0x9910,
1738 0x9913,
1739 0x9917,
1740 0x9918,
1741 0x9919,
1742 0x9990,
1743 0x9991,
1744 0x9992,
1745 0x9993,
1746 0x9994,
1747 0x9995,
1748 0x9996,
1749 0x9997,
1750 0x9998,
1751 0x9999,
1752 0x999A,
1753 0x999B,
1754 0x999C,
1755 0x999D,
1756 0x99A0,
1757 0x99A2,
1758 0x99A4,
1759 /* radeon secondary ids */
1760 0x3171,
1761 0x3e70,
1762 0x4164,
1763 0x4165,
1764 0x4166,
1765 0x4168,
1766 0x4170,
1767 0x4171,
1768 0x4172,
1769 0x4173,
1770 0x496e,
1771 0x4a69,
1772 0x4a6a,
1773 0x4a6b,
1774 0x4a70,
1775 0x4a74,
1776 0x4b69,
1777 0x4b6b,
1778 0x4b6c,
1779 0x4c6e,
1780 0x4e64,
1781 0x4e65,
1782 0x4e66,
1783 0x4e67,
1784 0x4e68,
1785 0x4e69,
1786 0x4e6a,
1787 0x4e71,
1788 0x4f73,
1789 0x5569,
1790 0x556b,
1791 0x556d,
1792 0x556f,
1793 0x5571,
1794 0x5854,
1795 0x5874,
1796 0x5940,
1797 0x5941,
1798 0x5b70,
1799 0x5b72,
1800 0x5b73,
1801 0x5b74,
1802 0x5b75,
1803 0x5d44,
1804 0x5d45,
1805 0x5d6d,
1806 0x5d6f,
1807 0x5d72,
1808 0x5d77,
1809 0x5e6b,
1810 0x5e6d,
1811 0x7120,
1812 0x7124,
1813 0x7129,
1814 0x712e,
1815 0x712f,
1816 0x7162,
1817 0x7163,
1818 0x7166,
1819 0x7167,
1820 0x7172,
1821 0x7173,
1822 0x71a0,
1823 0x71a1,
1824 0x71a3,
1825 0x71a7,
1826 0x71bb,
1827 0x71e0,
1828 0x71e1,
1829 0x71e2,
1830 0x71e6,
1831 0x71e7,
1832 0x71f2,
1833 0x7269,
1834 0x726b,
1835 0x726e,
1836 0x72a0,
1837 0x72a8,
1838 0x72b1,
1839 0x72b3,
1840 0x793f,
1841 };
1842
1843 static const struct pci_device_id pciidlist[] = {
1844 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1845 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1846 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1847 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1848 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1849 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1850 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1851 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1852 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1853 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1854 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1855 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1856 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1857 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1858 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1859 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1860 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1861 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1862 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1863 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1864 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1865 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1866 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1867 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1868 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1869 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1870 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1871 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1872 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1873 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1874 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1875 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1876 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1877 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1878 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1879 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1880 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1881 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1882 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1883 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1884 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1885 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1886 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1887 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1888 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1889 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1890 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1891 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1892 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1893 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1894 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1895 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1896 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1897 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1898 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1899 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1900 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1901 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1902 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1903 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1904 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1905 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1906 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1907 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1908 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1909 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1910 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1911 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1912 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1913 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1914 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1915 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1916 /* Kaveri */
1917 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1918 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1919 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1920 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1921 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1922 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1923 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1924 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1925 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1926 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1927 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1928 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1929 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1930 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1931 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1932 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1933 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1934 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1935 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1936 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1937 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1938 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1939 /* Bonaire */
1940 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1941 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1942 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1943 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1944 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1945 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1946 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1947 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1948 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1949 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1950 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1951 /* Hawaii */
1952 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1953 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1954 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1955 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1956 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1957 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1958 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1959 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1960 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1961 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1962 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1963 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1964 /* Kabini */
1965 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1966 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1967 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1968 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1969 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1970 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1971 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1972 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1973 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1974 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1975 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1976 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1977 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1978 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1979 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1980 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1981 /* mullins */
1982 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1983 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1984 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1985 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1986 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1987 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1988 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1989 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1990 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1991 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1992 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1993 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1994 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1995 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1996 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1997 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1998 /* topaz */
1999 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
2000 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
2001 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
2002 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
2003 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
2004 /* tonga */
2005 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2006 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2007 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2008 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2009 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2010 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2011 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2012 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2013 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2014 /* fiji */
2015 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
2016 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
2017 /* carrizo */
2018 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
2019 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
2020 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
2021 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
2022 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
2023 /* stoney */
2024 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2025 /* Polaris11 */
2026 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2027 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2028 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2029 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2030 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2031 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2032 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2033 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2034 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2035 /* Polaris10 */
2036 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2037 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2038 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2039 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2040 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2041 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2042 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2043 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2044 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2045 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2046 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2047 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2048 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2049 /* Polaris12 */
2050 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2051 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2052 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2053 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2054 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2055 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2056 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2057 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2058 /* VEGAM */
2059 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
2060 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
2061 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
2062 /* Vega 10 */
2063 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2064 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2065 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2066 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2067 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2068 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2069 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2070 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2071 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2072 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2073 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2074 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2075 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2076 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2077 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2078 /* Vega 12 */
2079 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
2080 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
2081 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
2082 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
2083 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
2084 /* Vega 20 */
2085 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2086 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2087 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2088 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2089 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2090 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2091 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2092 /* Raven */
2093 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
2094 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
2095 /* Arcturus */
2096 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
2097 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
2098 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
2099 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
2100 /* Navi10 */
2101 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2102 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2103 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2104 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2105 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2106 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2107 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2108 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2109 /* Navi14 */
2110 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
2111 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
2112 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
2113 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
2114
2115 /* Renoir */
2116 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
2117 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
2118 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
2119 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
2120
2121 /* Navi12 */
2122 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
2123 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
2124
2125 /* Sienna_Cichlid */
2126 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2127 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2128 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2129 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2130 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2131 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2132 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2133 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2134 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2135 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2136 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2137 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2138 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2139
2140 /* Yellow Carp */
2141 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
2142 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
2143
2144 /* Navy_Flounder */
2145 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2146 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2147 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2148 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2149 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2150 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2151 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2152 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2153 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2154
2155 /* DIMGREY_CAVEFISH */
2156 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2157 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2158 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2159 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2160 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2161 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2162 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2163 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2164 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2165 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2166 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2167 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2168
2169 /* Aldebaran */
2170 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2171 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2172 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2173 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2174
2175 /* CYAN_SKILLFISH */
2176 {0x1002, 0x13DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2177 {0x1002, 0x13F9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2178 {0x1002, 0x13FA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2179 {0x1002, 0x13FB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2180 {0x1002, 0x13FC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2181 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2182 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2183
2184 /* BEIGE_GOBY */
2185 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2186 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2187 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2188 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2189 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2190 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2191
2192 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2193 .class = PCI_CLASS_DISPLAY_VGA << 8,
2194 .class_mask = 0xffffff,
2195 .driver_data = CHIP_IP_DISCOVERY },
2196
2197 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2198 .class = PCI_CLASS_DISPLAY_OTHER << 8,
2199 .class_mask = 0xffffff,
2200 .driver_data = CHIP_IP_DISCOVERY },
2201
2202 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2203 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8,
2204 .class_mask = 0xffffff,
2205 .driver_data = CHIP_IP_DISCOVERY },
2206
2207 {0, 0, 0}
2208 };
2209
2210 MODULE_DEVICE_TABLE(pci, pciidlist);
2211
2212 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = {
2213 /* differentiate between P10 and P11 asics with the same DID */
2214 {0x67FF, 0xE3, CHIP_POLARIS10},
2215 {0x67FF, 0xE7, CHIP_POLARIS10},
2216 {0x67FF, 0xF3, CHIP_POLARIS10},
2217 {0x67FF, 0xF7, CHIP_POLARIS10},
2218 };
2219
2220 static const struct drm_driver amdgpu_kms_driver;
2221
amdgpu_get_secondary_funcs(struct amdgpu_device * adev)2222 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
2223 {
2224 struct pci_dev *p = NULL;
2225 int i;
2226
2227 /* 0 - GPU
2228 * 1 - audio
2229 * 2 - USB
2230 * 3 - UCSI
2231 */
2232 for (i = 1; i < 4; i++) {
2233 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
2234 adev->pdev->bus->number, i);
2235 if (p) {
2236 pm_runtime_get_sync(&p->dev);
2237 pm_runtime_mark_last_busy(&p->dev);
2238 pm_runtime_put_autosuspend(&p->dev);
2239 pci_dev_put(p);
2240 }
2241 }
2242 }
2243
amdgpu_init_debug_options(struct amdgpu_device * adev)2244 static void amdgpu_init_debug_options(struct amdgpu_device *adev)
2245 {
2246 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) {
2247 pr_info("debug: VM handling debug enabled\n");
2248 adev->debug_vm = true;
2249 }
2250
2251 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) {
2252 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n");
2253 adev->debug_largebar = true;
2254 }
2255
2256 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) {
2257 pr_info("debug: soft reset for GPU recovery disabled\n");
2258 adev->debug_disable_soft_recovery = true;
2259 }
2260
2261 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) {
2262 pr_info("debug: place fw in vram for frontdoor loading\n");
2263 adev->debug_use_vram_fw_buf = true;
2264 }
2265
2266 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) {
2267 pr_info("debug: enable RAS ACA\n");
2268 adev->debug_enable_ras_aca = true;
2269 }
2270
2271 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) {
2272 pr_info("debug: enable experimental reset features\n");
2273 adev->debug_exp_resets = true;
2274 }
2275
2276 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) {
2277 pr_info("debug: ring reset disabled\n");
2278 adev->debug_disable_gpu_ring_reset = true;
2279 }
2280 if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) {
2281 pr_info("debug: use vram for smu pool\n");
2282 adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM;
2283 }
2284 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM_USERPTR) {
2285 pr_info("debug: VM mode debug for userptr is enabled\n");
2286 adev->debug_vm_userptr = true;
2287 }
2288
2289 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_RAS_CE_LOG) {
2290 pr_info("debug: disable kernel logs of correctable errors\n");
2291 adev->debug_disable_ce_logs = true;
2292 }
2293
2294 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_CE_CS) {
2295 pr_info("debug: allowing command submission to CE engine\n");
2296 adev->debug_enable_ce_cs = true;
2297 }
2298 }
2299
amdgpu_fix_asic_type(struct pci_dev * pdev,unsigned long flags)2300 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)
2301 {
2302 int i;
2303
2304 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) {
2305 if (pdev->device == asic_type_quirks[i].device &&
2306 pdev->revision == asic_type_quirks[i].revision) {
2307 flags &= ~AMD_ASIC_MASK;
2308 flags |= asic_type_quirks[i].type;
2309 break;
2310 }
2311 }
2312
2313 return flags;
2314 }
2315
amdgpu_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)2316 static int amdgpu_pci_probe(struct pci_dev *pdev,
2317 const struct pci_device_id *ent)
2318 {
2319 struct drm_device *ddev;
2320 struct amdgpu_device *adev;
2321 unsigned long flags = ent->driver_data;
2322 int ret, retry = 0, i;
2323 bool supports_atomic = false;
2324
2325 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA ||
2326 (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) {
2327 if (drm_firmware_drivers_only() && amdgpu_modeset == -1)
2328 return -EINVAL;
2329 }
2330
2331 /* skip devices which are owned by radeon */
2332 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2333 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2334 return -ENODEV;
2335 }
2336
2337 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2338 amdgpu_aspm = 0;
2339
2340 if (amdgpu_virtual_display ||
2341 amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK))
2342 supports_atomic = true;
2343
2344 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
2345 DRM_INFO("This hardware requires experimental hardware support.\n"
2346 "See modparam exp_hw_support\n");
2347 return -ENODEV;
2348 }
2349
2350 flags = amdgpu_fix_asic_type(pdev, flags);
2351
2352 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2353 * however, SME requires an indirect IOMMU mapping because the encryption
2354 * bit is beyond the DMA mask of the chip.
2355 */
2356 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2357 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
2358 dev_info(&pdev->dev,
2359 "SME is not compatible with RAVEN\n");
2360 return -ENOTSUPP;
2361 }
2362
2363 switch (flags & AMD_ASIC_MASK) {
2364 case CHIP_TAHITI:
2365 case CHIP_PITCAIRN:
2366 case CHIP_VERDE:
2367 case CHIP_OLAND:
2368 case CHIP_HAINAN:
2369 #ifdef CONFIG_DRM_AMDGPU_SI
2370 if (!amdgpu_si_support) {
2371 dev_info(&pdev->dev,
2372 "SI support provided by radeon.\n");
2373 dev_info(&pdev->dev,
2374 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2375 );
2376 return -ENODEV;
2377 }
2378 break;
2379 #else
2380 dev_info(&pdev->dev, "amdgpu is built without SI support.\n");
2381 return -ENODEV;
2382 #endif
2383 case CHIP_KAVERI:
2384 case CHIP_BONAIRE:
2385 case CHIP_HAWAII:
2386 case CHIP_KABINI:
2387 case CHIP_MULLINS:
2388 #ifdef CONFIG_DRM_AMDGPU_CIK
2389 if (!amdgpu_cik_support) {
2390 dev_info(&pdev->dev,
2391 "CIK support provided by radeon.\n");
2392 dev_info(&pdev->dev,
2393 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2394 );
2395 return -ENODEV;
2396 }
2397 break;
2398 #else
2399 dev_info(&pdev->dev, "amdgpu is built without CIK support.\n");
2400 return -ENODEV;
2401 #endif
2402 default:
2403 break;
2404 }
2405
2406 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2407 if (IS_ERR(adev))
2408 return PTR_ERR(adev);
2409
2410 adev->dev = &pdev->dev;
2411 adev->pdev = pdev;
2412 ddev = adev_to_drm(adev);
2413
2414 if (!supports_atomic)
2415 ddev->driver_features &= ~DRIVER_ATOMIC;
2416
2417 ret = pci_enable_device(pdev);
2418 if (ret)
2419 return ret;
2420
2421 pci_set_drvdata(pdev, ddev);
2422
2423 amdgpu_init_debug_options(adev);
2424
2425 ret = amdgpu_driver_load_kms(adev, flags);
2426 if (ret)
2427 goto err_pci;
2428
2429 retry_init:
2430 ret = drm_dev_register(ddev, flags);
2431 if (ret == -EAGAIN && ++retry <= 3) {
2432 DRM_INFO("retry init %d\n", retry);
2433 /* Don't request EX mode too frequently which is attacking */
2434 msleep(5000);
2435 goto retry_init;
2436 } else if (ret) {
2437 goto err_pci;
2438 }
2439
2440 ret = amdgpu_xcp_dev_register(adev, ent);
2441 if (ret)
2442 goto err_pci;
2443
2444 ret = amdgpu_amdkfd_drm_client_create(adev);
2445 if (ret)
2446 goto err_pci;
2447
2448 /*
2449 * 1. don't init fbdev on hw without DCE
2450 * 2. don't init fbdev if there are no connectors
2451 */
2452 if (adev->mode_info.mode_config_initialized &&
2453 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2454 const struct drm_format_info *format;
2455
2456 /* select 8 bpp console on low vram cards */
2457 if (adev->gmc.real_vram_size <= (32*1024*1024))
2458 format = drm_format_info(DRM_FORMAT_C8);
2459 else
2460 format = NULL;
2461
2462 drm_client_setup(adev_to_drm(adev), format);
2463 }
2464
2465 ret = amdgpu_debugfs_init(adev);
2466 if (ret)
2467 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2468
2469 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2470 /* only need to skip on ATPX */
2471 if (amdgpu_device_supports_px(adev))
2472 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2473 /* we want direct complete for BOCO */
2474 if (amdgpu_device_supports_boco(adev))
2475 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2476 DPM_FLAG_SMART_SUSPEND |
2477 DPM_FLAG_MAY_SKIP_RESUME);
2478 pm_runtime_use_autosuspend(ddev->dev);
2479 pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2480
2481 pm_runtime_allow(ddev->dev);
2482
2483 pm_runtime_mark_last_busy(ddev->dev);
2484 pm_runtime_put_autosuspend(ddev->dev);
2485
2486 pci_wake_from_d3(pdev, TRUE);
2487
2488 /*
2489 * For runpm implemented via BACO, PMFW will handle the
2490 * timing for BACO in and out:
2491 * - put ASIC into BACO state only when both video and
2492 * audio functions are in D3 state.
2493 * - pull ASIC out of BACO state when either video or
2494 * audio function is in D0 state.
2495 * Also, at startup, PMFW assumes both functions are in
2496 * D0 state.
2497 *
2498 * So if snd driver was loaded prior to amdgpu driver
2499 * and audio function was put into D3 state, there will
2500 * be no PMFW-aware D-state transition(D0->D3) on runpm
2501 * suspend. Thus the BACO will be not correctly kicked in.
2502 *
2503 * Via amdgpu_get_secondary_funcs(), the audio dev is put
2504 * into D0 state. Then there will be a PMFW-aware D-state
2505 * transition(D0->D3) on runpm suspend.
2506 */
2507 if (amdgpu_device_supports_baco(adev) &&
2508 !(adev->flags & AMD_IS_APU) &&
2509 adev->asic_type >= CHIP_NAVI10)
2510 amdgpu_get_secondary_funcs(adev);
2511 }
2512
2513 return 0;
2514
2515 err_pci:
2516 pci_disable_device(pdev);
2517 return ret;
2518 }
2519
2520 static void
amdgpu_pci_remove(struct pci_dev * pdev)2521 amdgpu_pci_remove(struct pci_dev *pdev)
2522 {
2523 struct drm_device *dev = pci_get_drvdata(pdev);
2524 struct amdgpu_device *adev = drm_to_adev(dev);
2525
2526 amdgpu_ras_eeprom_check_and_recover(adev);
2527 amdgpu_xcp_dev_unplug(adev);
2528 amdgpu_gmc_prepare_nps_mode_change(adev);
2529 drm_dev_unplug(dev);
2530
2531 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2532 pm_runtime_get_sync(dev->dev);
2533 pm_runtime_forbid(dev->dev);
2534 }
2535
2536 amdgpu_driver_unload_kms(dev);
2537
2538 /*
2539 * Flush any in flight DMA operations from device.
2540 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2541 * StatusTransactions Pending bit.
2542 */
2543 pci_disable_device(pdev);
2544 pci_wait_for_pending_transaction(pdev);
2545 }
2546
2547 static void
amdgpu_pci_shutdown(struct pci_dev * pdev)2548 amdgpu_pci_shutdown(struct pci_dev *pdev)
2549 {
2550 struct drm_device *dev = pci_get_drvdata(pdev);
2551 struct amdgpu_device *adev = drm_to_adev(dev);
2552
2553 if (amdgpu_ras_intr_triggered())
2554 return;
2555
2556 /* device maybe not resumed here, return immediately in this case */
2557 if (adev->in_s4 && adev->in_suspend)
2558 return;
2559
2560 /* if we are running in a VM, make sure the device
2561 * torn down properly on reboot/shutdown.
2562 * unfortunately we can't detect certain
2563 * hypervisors so just do this all the time.
2564 */
2565 if (!amdgpu_passthrough(adev))
2566 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2567 amdgpu_device_ip_suspend(adev);
2568 adev->mp1_state = PP_MP1_STATE_NONE;
2569 }
2570
amdgpu_pmops_prepare(struct device * dev)2571 static int amdgpu_pmops_prepare(struct device *dev)
2572 {
2573 struct drm_device *drm_dev = dev_get_drvdata(dev);
2574 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2575
2576 /* device maybe not resumed here, return immediately in this case */
2577 if (adev->in_s4 && adev->in_suspend)
2578 return 0;
2579
2580 /* Return a positive number here so
2581 * DPM_FLAG_SMART_SUSPEND works properly
2582 */
2583 if (amdgpu_device_supports_boco(adev) && pm_runtime_suspended(dev))
2584 return 1;
2585
2586 /* if we will not support s3 or s2i for the device
2587 * then skip suspend
2588 */
2589 if (!amdgpu_acpi_is_s0ix_active(adev) &&
2590 !amdgpu_acpi_is_s3_active(adev))
2591 return 1;
2592
2593 return amdgpu_device_prepare(drm_dev);
2594 }
2595
amdgpu_pmops_complete(struct device * dev)2596 static void amdgpu_pmops_complete(struct device *dev)
2597 {
2598 amdgpu_device_complete(dev_get_drvdata(dev));
2599 }
2600
amdgpu_pmops_suspend(struct device * dev)2601 static int amdgpu_pmops_suspend(struct device *dev)
2602 {
2603 struct drm_device *drm_dev = dev_get_drvdata(dev);
2604 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2605
2606 if (amdgpu_acpi_is_s0ix_active(adev))
2607 adev->in_s0ix = true;
2608 else if (amdgpu_acpi_is_s3_active(adev))
2609 adev->in_s3 = true;
2610 if (!adev->in_s0ix && !adev->in_s3) {
2611 #if IS_ENABLED(CONFIG_SUSPEND)
2612 /* don't allow going deep first time followed by s2idle the next time */
2613 if (adev->last_suspend_state != PM_SUSPEND_ON &&
2614 adev->last_suspend_state != pm_suspend_target_state) {
2615 drm_err_once(drm_dev, "Unsupported suspend state %d\n",
2616 pm_suspend_target_state);
2617 return -EINVAL;
2618 }
2619 #endif
2620 return 0;
2621 }
2622
2623 #if IS_ENABLED(CONFIG_SUSPEND)
2624 /* cache the state last used for suspend */
2625 adev->last_suspend_state = pm_suspend_target_state;
2626 #endif
2627
2628 return amdgpu_device_suspend(drm_dev, true);
2629 }
2630
amdgpu_pmops_suspend_noirq(struct device * dev)2631 static int amdgpu_pmops_suspend_noirq(struct device *dev)
2632 {
2633 struct drm_device *drm_dev = dev_get_drvdata(dev);
2634 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2635
2636 if (amdgpu_acpi_should_gpu_reset(adev))
2637 return amdgpu_asic_reset(adev);
2638
2639 return 0;
2640 }
2641
amdgpu_pmops_resume(struct device * dev)2642 static int amdgpu_pmops_resume(struct device *dev)
2643 {
2644 struct drm_device *drm_dev = dev_get_drvdata(dev);
2645 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2646 int r;
2647
2648 if (!adev->in_s0ix && !adev->in_s3)
2649 return 0;
2650
2651 /* Avoids registers access if device is physically gone */
2652 if (!pci_device_is_present(adev->pdev))
2653 adev->no_hw_access = true;
2654
2655 r = amdgpu_device_resume(drm_dev, true);
2656 if (amdgpu_acpi_is_s0ix_active(adev))
2657 adev->in_s0ix = false;
2658 else
2659 adev->in_s3 = false;
2660 return r;
2661 }
2662
amdgpu_pmops_freeze(struct device * dev)2663 static int amdgpu_pmops_freeze(struct device *dev)
2664 {
2665 struct drm_device *drm_dev = dev_get_drvdata(dev);
2666 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2667 int r;
2668
2669 r = amdgpu_device_suspend(drm_dev, true);
2670 if (r)
2671 return r;
2672
2673 if (amdgpu_acpi_should_gpu_reset(adev))
2674 return amdgpu_asic_reset(adev);
2675 return 0;
2676 }
2677
amdgpu_pmops_thaw(struct device * dev)2678 static int amdgpu_pmops_thaw(struct device *dev)
2679 {
2680 struct drm_device *drm_dev = dev_get_drvdata(dev);
2681
2682 /* do not resume device if it's normal hibernation */
2683 if (!pm_hibernate_is_recovering() && !pm_hibernation_mode_is_suspend())
2684 return 0;
2685
2686 return amdgpu_device_resume(drm_dev, true);
2687 }
2688
amdgpu_pmops_poweroff(struct device * dev)2689 static int amdgpu_pmops_poweroff(struct device *dev)
2690 {
2691 struct drm_device *drm_dev = dev_get_drvdata(dev);
2692 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2693
2694 /* device maybe not resumed here, return immediately in this case */
2695 if (adev->in_s4 && adev->in_suspend)
2696 return 0;
2697
2698 return amdgpu_device_suspend(drm_dev, true);
2699 }
2700
amdgpu_pmops_restore(struct device * dev)2701 static int amdgpu_pmops_restore(struct device *dev)
2702 {
2703 struct drm_device *drm_dev = dev_get_drvdata(dev);
2704
2705 return amdgpu_device_resume(drm_dev, true);
2706 }
2707
amdgpu_runtime_idle_check_display(struct device * dev)2708 static int amdgpu_runtime_idle_check_display(struct device *dev)
2709 {
2710 struct pci_dev *pdev = to_pci_dev(dev);
2711 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2712 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2713
2714 if (adev->mode_info.num_crtc) {
2715 struct drm_connector *list_connector;
2716 struct drm_connector_list_iter iter;
2717 int ret = 0;
2718
2719 if (amdgpu_runtime_pm != -2) {
2720 /* XXX: Return busy if any displays are connected to avoid
2721 * possible display wakeups after runtime resume due to
2722 * hotplug events in case any displays were connected while
2723 * the GPU was in suspend. Remove this once that is fixed.
2724 */
2725 mutex_lock(&drm_dev->mode_config.mutex);
2726 drm_connector_list_iter_begin(drm_dev, &iter);
2727 drm_for_each_connector_iter(list_connector, &iter) {
2728 if (list_connector->status == connector_status_connected) {
2729 ret = -EBUSY;
2730 break;
2731 }
2732 }
2733 drm_connector_list_iter_end(&iter);
2734 mutex_unlock(&drm_dev->mode_config.mutex);
2735
2736 if (ret)
2737 return ret;
2738 }
2739
2740 if (adev->dc_enabled) {
2741 struct drm_crtc *crtc;
2742
2743 drm_for_each_crtc(crtc, drm_dev) {
2744 drm_modeset_lock(&crtc->mutex, NULL);
2745 if (crtc->state->active)
2746 ret = -EBUSY;
2747 drm_modeset_unlock(&crtc->mutex);
2748 if (ret < 0)
2749 break;
2750 }
2751 } else {
2752 mutex_lock(&drm_dev->mode_config.mutex);
2753 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2754
2755 drm_connector_list_iter_begin(drm_dev, &iter);
2756 drm_for_each_connector_iter(list_connector, &iter) {
2757 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2758 ret = -EBUSY;
2759 break;
2760 }
2761 }
2762
2763 drm_connector_list_iter_end(&iter);
2764
2765 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2766 mutex_unlock(&drm_dev->mode_config.mutex);
2767 }
2768 if (ret)
2769 return ret;
2770 }
2771
2772 return 0;
2773 }
2774
amdgpu_runtime_idle_check_userq(struct device * dev)2775 static int amdgpu_runtime_idle_check_userq(struct device *dev)
2776 {
2777 struct pci_dev *pdev = to_pci_dev(dev);
2778 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2779 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2780 struct amdgpu_usermode_queue *queue;
2781 struct amdgpu_userq_mgr *uqm, *tmp;
2782 int queue_id;
2783 int ret = 0;
2784
2785 mutex_lock(&adev->userq_mutex);
2786 list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) {
2787 idr_for_each_entry(&uqm->userq_idr, queue, queue_id) {
2788 ret = -EBUSY;
2789 goto done;
2790 }
2791 }
2792 done:
2793 mutex_unlock(&adev->userq_mutex);
2794
2795 return ret;
2796 }
2797
amdgpu_pmops_runtime_suspend(struct device * dev)2798 static int amdgpu_pmops_runtime_suspend(struct device *dev)
2799 {
2800 struct pci_dev *pdev = to_pci_dev(dev);
2801 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2802 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2803 int ret, i;
2804
2805 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2806 pm_runtime_forbid(dev);
2807 return -EBUSY;
2808 }
2809
2810 ret = amdgpu_runtime_idle_check_display(dev);
2811 if (ret)
2812 return ret;
2813 ret = amdgpu_runtime_idle_check_userq(dev);
2814 if (ret)
2815 return ret;
2816
2817 /* wait for all rings to drain before suspending */
2818 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2819 struct amdgpu_ring *ring = adev->rings[i];
2820
2821 if (ring && ring->sched.ready) {
2822 ret = amdgpu_fence_wait_empty(ring);
2823 if (ret)
2824 return -EBUSY;
2825 }
2826 }
2827
2828 adev->in_runpm = true;
2829 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
2830 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2831
2832 /*
2833 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2834 * proper cleanups and put itself into a state ready for PNP. That
2835 * can address some random resuming failure observed on BOCO capable
2836 * platforms.
2837 * TODO: this may be also needed for PX capable platform.
2838 */
2839 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
2840 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2841
2842 ret = amdgpu_device_prepare(drm_dev);
2843 if (ret)
2844 return ret;
2845 ret = amdgpu_device_suspend(drm_dev, false);
2846 if (ret) {
2847 adev->in_runpm = false;
2848 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
2849 adev->mp1_state = PP_MP1_STATE_NONE;
2850 return ret;
2851 }
2852
2853 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
2854 adev->mp1_state = PP_MP1_STATE_NONE;
2855
2856 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {
2857 /* Only need to handle PCI state in the driver for ATPX
2858 * PCI core handles it for _PR3.
2859 */
2860 amdgpu_device_cache_pci_state(pdev);
2861 pci_disable_device(pdev);
2862 pci_ignore_hotplug(pdev);
2863 pci_set_power_state(pdev, PCI_D3cold);
2864 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
2865 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {
2866 /* nothing to do */
2867 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||
2868 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) {
2869 amdgpu_device_baco_enter(adev);
2870 }
2871
2872 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n");
2873
2874 return 0;
2875 }
2876
amdgpu_pmops_runtime_resume(struct device * dev)2877 static int amdgpu_pmops_runtime_resume(struct device *dev)
2878 {
2879 struct pci_dev *pdev = to_pci_dev(dev);
2880 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2881 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2882 int ret;
2883
2884 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
2885 return -EINVAL;
2886
2887 /* Avoids registers access if device is physically gone */
2888 if (!pci_device_is_present(adev->pdev))
2889 adev->no_hw_access = true;
2890
2891 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {
2892 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2893
2894 /* Only need to handle PCI state in the driver for ATPX
2895 * PCI core handles it for _PR3.
2896 */
2897 pci_set_power_state(pdev, PCI_D0);
2898 amdgpu_device_load_pci_state(pdev);
2899 ret = pci_enable_device(pdev);
2900 if (ret)
2901 return ret;
2902 pci_set_master(pdev);
2903 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {
2904 /* Only need to handle PCI state in the driver for ATPX
2905 * PCI core handles it for _PR3.
2906 */
2907 pci_set_master(pdev);
2908 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||
2909 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) {
2910 amdgpu_device_baco_exit(adev);
2911 }
2912 ret = amdgpu_device_resume(drm_dev, false);
2913 if (ret) {
2914 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
2915 pci_disable_device(pdev);
2916 return ret;
2917 }
2918
2919 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
2920 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
2921 adev->in_runpm = false;
2922 return 0;
2923 }
2924
amdgpu_pmops_runtime_idle(struct device * dev)2925 static int amdgpu_pmops_runtime_idle(struct device *dev)
2926 {
2927 struct drm_device *drm_dev = dev_get_drvdata(dev);
2928 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2929 int ret;
2930
2931 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2932 pm_runtime_forbid(dev);
2933 return -EBUSY;
2934 }
2935
2936 ret = amdgpu_runtime_idle_check_display(dev);
2937 if (ret)
2938 goto done;
2939
2940 ret = amdgpu_runtime_idle_check_userq(dev);
2941 done:
2942 pm_runtime_mark_last_busy(dev);
2943 pm_runtime_autosuspend(dev);
2944 return ret;
2945 }
2946
amdgpu_drm_release(struct inode * inode,struct file * filp)2947 static int amdgpu_drm_release(struct inode *inode, struct file *filp)
2948 {
2949 struct drm_file *file_priv = filp->private_data;
2950 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2951 struct drm_device *dev = file_priv->minor->dev;
2952 int idx;
2953
2954 if (fpriv && drm_dev_enter(dev, &idx)) {
2955 fpriv->evf_mgr.fd_closing = true;
2956 amdgpu_eviction_fence_destroy(&fpriv->evf_mgr);
2957 amdgpu_userq_mgr_fini(&fpriv->userq_mgr);
2958 drm_dev_exit(idx);
2959 }
2960
2961 return drm_release(inode, filp);
2962 }
2963
amdgpu_drm_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)2964 long amdgpu_drm_ioctl(struct file *filp,
2965 unsigned int cmd, unsigned long arg)
2966 {
2967 struct drm_file *file_priv = filp->private_data;
2968 struct drm_device *dev;
2969 long ret;
2970
2971 dev = file_priv->minor->dev;
2972 ret = pm_runtime_get_sync(dev->dev);
2973 if (ret < 0)
2974 goto out;
2975
2976 ret = drm_ioctl(filp, cmd, arg);
2977
2978 pm_runtime_mark_last_busy(dev->dev);
2979 out:
2980 pm_runtime_put_autosuspend(dev->dev);
2981 return ret;
2982 }
2983
2984 static const struct dev_pm_ops amdgpu_pm_ops = {
2985 .prepare = pm_sleep_ptr(amdgpu_pmops_prepare),
2986 .complete = pm_sleep_ptr(amdgpu_pmops_complete),
2987 .suspend = pm_sleep_ptr(amdgpu_pmops_suspend),
2988 .suspend_noirq = pm_sleep_ptr(amdgpu_pmops_suspend_noirq),
2989 .resume = pm_sleep_ptr(amdgpu_pmops_resume),
2990 .freeze = pm_sleep_ptr(amdgpu_pmops_freeze),
2991 .thaw = pm_sleep_ptr(amdgpu_pmops_thaw),
2992 .poweroff = pm_sleep_ptr(amdgpu_pmops_poweroff),
2993 .restore = pm_sleep_ptr(amdgpu_pmops_restore),
2994 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2995 .runtime_resume = amdgpu_pmops_runtime_resume,
2996 .runtime_idle = amdgpu_pmops_runtime_idle,
2997 };
2998
amdgpu_flush(struct file * f,fl_owner_t id)2999 static int amdgpu_flush(struct file *f, fl_owner_t id)
3000 {
3001 struct drm_file *file_priv = f->private_data;
3002 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
3003 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
3004
3005 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
3006 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
3007
3008 return timeout >= 0 ? 0 : timeout;
3009 }
3010
3011 static const struct file_operations amdgpu_driver_kms_fops = {
3012 .owner = THIS_MODULE,
3013 .open = drm_open,
3014 .flush = amdgpu_flush,
3015 .release = amdgpu_drm_release,
3016 .unlocked_ioctl = amdgpu_drm_ioctl,
3017 .mmap = drm_gem_mmap,
3018 .poll = drm_poll,
3019 .read = drm_read,
3020 #ifdef CONFIG_COMPAT
3021 .compat_ioctl = amdgpu_kms_compat_ioctl,
3022 #endif
3023 #ifdef CONFIG_PROC_FS
3024 .show_fdinfo = drm_show_fdinfo,
3025 #endif
3026 .fop_flags = FOP_UNSIGNED_OFFSET,
3027 };
3028
amdgpu_file_to_fpriv(struct file * filp,struct amdgpu_fpriv ** fpriv)3029 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
3030 {
3031 struct drm_file *file;
3032
3033 if (!filp)
3034 return -EINVAL;
3035
3036 if (filp->f_op != &amdgpu_driver_kms_fops)
3037 return -EINVAL;
3038
3039 file = filp->private_data;
3040 *fpriv = file->driver_priv;
3041 return 0;
3042 }
3043
3044 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
3045 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3046 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3047 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3048 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
3049 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3050 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3051 /* KMS */
3052 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3053 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3054 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3055 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3056 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3057 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3058 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3059 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3060 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3061 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3062 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3063 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3064 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3065 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3066 };
3067
3068 static const struct drm_driver amdgpu_kms_driver = {
3069 .driver_features =
3070 DRIVER_ATOMIC |
3071 DRIVER_GEM |
3072 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
3073 DRIVER_SYNCOBJ_TIMELINE,
3074 .open = amdgpu_driver_open_kms,
3075 .postclose = amdgpu_driver_postclose_kms,
3076 .ioctls = amdgpu_ioctls_kms,
3077 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
3078 .dumb_create = amdgpu_mode_dumb_create,
3079 .dumb_map_offset = amdgpu_mode_dumb_mmap,
3080 DRM_FBDEV_TTM_DRIVER_OPS,
3081 .fops = &amdgpu_driver_kms_fops,
3082 .release = &amdgpu_driver_release_kms,
3083 #ifdef CONFIG_PROC_FS
3084 .show_fdinfo = amdgpu_show_fdinfo,
3085 #endif
3086
3087 .gem_prime_import = amdgpu_gem_prime_import,
3088
3089 .name = DRIVER_NAME,
3090 .desc = DRIVER_DESC,
3091 .major = KMS_DRIVER_MAJOR,
3092 .minor = KMS_DRIVER_MINOR,
3093 .patchlevel = KMS_DRIVER_PATCHLEVEL,
3094 };
3095
3096 const struct drm_driver amdgpu_partition_driver = {
3097 .driver_features =
3098 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ |
3099 DRIVER_SYNCOBJ_TIMELINE,
3100 .open = amdgpu_driver_open_kms,
3101 .postclose = amdgpu_driver_postclose_kms,
3102 .ioctls = amdgpu_ioctls_kms,
3103 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
3104 .dumb_create = amdgpu_mode_dumb_create,
3105 .dumb_map_offset = amdgpu_mode_dumb_mmap,
3106 DRM_FBDEV_TTM_DRIVER_OPS,
3107 .fops = &amdgpu_driver_kms_fops,
3108 .release = &amdgpu_driver_release_kms,
3109
3110 .gem_prime_import = amdgpu_gem_prime_import,
3111
3112 .name = DRIVER_NAME,
3113 .desc = DRIVER_DESC,
3114 .major = KMS_DRIVER_MAJOR,
3115 .minor = KMS_DRIVER_MINOR,
3116 .patchlevel = KMS_DRIVER_PATCHLEVEL,
3117 };
3118
3119 static struct pci_error_handlers amdgpu_pci_err_handler = {
3120 .error_detected = amdgpu_pci_error_detected,
3121 .mmio_enabled = amdgpu_pci_mmio_enabled,
3122 .slot_reset = amdgpu_pci_slot_reset,
3123 .resume = amdgpu_pci_resume,
3124 };
3125
3126 static const struct attribute_group *amdgpu_sysfs_groups[] = {
3127 &amdgpu_vram_mgr_attr_group,
3128 &amdgpu_gtt_mgr_attr_group,
3129 &amdgpu_flash_attr_group,
3130 NULL,
3131 };
3132
3133 static struct pci_driver amdgpu_kms_pci_driver = {
3134 .name = DRIVER_NAME,
3135 .id_table = pciidlist,
3136 .probe = amdgpu_pci_probe,
3137 .remove = amdgpu_pci_remove,
3138 .shutdown = amdgpu_pci_shutdown,
3139 .driver.pm = pm_ptr(&amdgpu_pm_ops),
3140 .err_handler = &amdgpu_pci_err_handler,
3141 .dev_groups = amdgpu_sysfs_groups,
3142 };
3143
amdgpu_init(void)3144 static int __init amdgpu_init(void)
3145 {
3146 int r;
3147
3148 r = amdgpu_sync_init();
3149 if (r)
3150 goto error_sync;
3151
3152 r = amdgpu_userq_fence_slab_init();
3153 if (r)
3154 goto error_fence;
3155
3156 DRM_INFO("amdgpu kernel modesetting enabled.\n");
3157 amdgpu_register_atpx_handler();
3158 amdgpu_acpi_detect();
3159
3160 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
3161 amdgpu_amdkfd_init();
3162
3163 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) {
3164 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
3165 pr_crit("Overdrive is enabled, please disable it before "
3166 "reporting any bugs unrelated to overdrive.\n");
3167 }
3168
3169 /* let modprobe override vga console setting */
3170 return pci_register_driver(&amdgpu_kms_pci_driver);
3171
3172 error_fence:
3173 amdgpu_sync_fini();
3174
3175 error_sync:
3176 return r;
3177 }
3178
amdgpu_exit(void)3179 static void __exit amdgpu_exit(void)
3180 {
3181 amdgpu_amdkfd_fini();
3182 pci_unregister_driver(&amdgpu_kms_pci_driver);
3183 amdgpu_unregister_atpx_handler();
3184 amdgpu_acpi_release();
3185 amdgpu_sync_fini();
3186 amdgpu_userq_fence_slab_fini();
3187 mmu_notifier_synchronize();
3188 amdgpu_xcp_drv_release();
3189 }
3190
3191 module_init(amdgpu_init);
3192 module_exit(amdgpu_exit);
3193
3194 MODULE_AUTHOR(DRIVER_AUTHOR);
3195 MODULE_DESCRIPTION(DRIVER_DESC);
3196 MODULE_LICENSE("GPL and additional rights");
3197