1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * This is the MDIO controller for the IPQ4018/IPQ4019.
31 */
32
33 #include <sys/cdefs.h>
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/bus.h>
38
39 #include <sys/kernel.h>
40 #include <sys/module.h>
41 #include <sys/rman.h>
42 #include <sys/lock.h>
43 #include <sys/malloc.h>
44 #include <sys/mutex.h>
45 #include <sys/gpio.h>
46
47 #include <machine/bus.h>
48 #include <machine/resource.h>
49 #include <dev/gpio/gpiobusvar.h>
50
51 #include <dev/fdt/fdt_common.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
54
55 #include "mdio_if.h"
56
57 #include <dev/qcom_mdio/qcom_mdio_ipq4018_var.h>
58 #include <dev/qcom_mdio/qcom_mdio_ipq4018_reg.h>
59
60 #include <dev/qcom_mdio/qcom_mdio_debug.h>
61
62 static int
qcom_mdio_ipq4018_probe(device_t dev)63 qcom_mdio_ipq4018_probe(device_t dev)
64 {
65
66 if (! ofw_bus_status_okay(dev))
67 return (ENXIO);
68
69 if (ofw_bus_is_compatible(dev, "qcom,ipq4019-mdio") == 0)
70 return (ENXIO);
71
72 device_set_desc(dev,
73 "Qualcomm Atheros IPQ4018/IPQ4019 MDIO driver");
74 return (0);
75 }
76
77 static int
qcom_mdio_ipq4018_detach(device_t dev)78 qcom_mdio_ipq4018_detach(device_t dev)
79 {
80 struct qcom_mdio_ipq4018_softc *sc = device_get_softc(dev);
81
82 if (sc->sc_mem_res != NULL)
83 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
84 sc->sc_mem_res);
85 mtx_destroy(&sc->sc_mtx);
86
87 return (0);
88 }
89
90 static void
qcom_mdio_sysctl_attach(struct qcom_mdio_ipq4018_softc * sc)91 qcom_mdio_sysctl_attach(struct qcom_mdio_ipq4018_softc *sc)
92 {
93 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
94 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
95
96 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
97 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
98 "control debugging printfs");
99 }
100
101 static int
qcom_mdio_ipq4018_attach(device_t dev)102 qcom_mdio_ipq4018_attach(device_t dev)
103 {
104 phandle_t node;
105 struct qcom_mdio_ipq4018_softc *sc = device_get_softc(dev);
106 int error = 0;
107
108 node = ofw_bus_get_node(dev);
109
110 sc->sc_dev = dev;
111 sc->sc_debug = 0;
112 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
113
114 /*
115 * Map the MDIO memory region.
116 */
117 sc->sc_mem_rid = 0;
118 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
119 &sc->sc_mem_rid, RF_ACTIVE);
120 if (sc->sc_mem_res == NULL) {
121 error = ENXIO;
122 device_printf(dev, "%s: failed to map device memory\n",
123 __func__);
124 goto error;
125 }
126 sc->sc_mem_res_size = (size_t) bus_get_resource_count(dev,
127 SYS_RES_MEMORY, sc->sc_mem_rid);
128 if (sc->sc_mem_res_size == 0) {
129 error = ENXIO;
130 device_printf(dev, "%s: failed to get device memory size\n",
131 __func__);
132 goto error;
133
134 }
135
136 qcom_mdio_sysctl_attach(sc);
137
138 OF_device_register_xref(OF_xref_from_node(node), dev);
139
140 return (0);
141 error:
142 if (sc->sc_mem_res != NULL)
143 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
144 sc->sc_mem_res);
145
146 mtx_destroy(&sc->sc_mtx);
147 return (error);
148 }
149
150 /*
151 * Wait for the BUSY flag to become zero.
152 *
153 * This has to happen before every MDIO transfer.
154 *
155 * Returns 0 if OK, error if error/timed out.
156 */
157 static int
qcom_mdio_ipq4018_wait(struct qcom_mdio_ipq4018_softc * sc)158 qcom_mdio_ipq4018_wait(struct qcom_mdio_ipq4018_softc *sc)
159 {
160 int i;
161 uint32_t reg;
162
163 MDIO_LOCK_ASSERT(sc);
164
165 for (i = 0; i < QCOM_IPQ4018_MDIO_SLEEP_COUNT; i++) {
166 MDIO_BARRIER_READ(sc);
167
168 reg = MDIO_READ(sc, QCOM_IPQ4018_MDIO_REG_CMD);
169 if ((reg & QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_BUSY) == 0)
170 return (0);
171 DELAY(QCOM_IPQ4018_MDIO_SLEEP);
172 }
173 device_printf(sc->sc_dev, "%s: warning: timeout waiting for bus\n",
174 __func__);
175 return (ETIMEDOUT);
176 }
177
178 static void
qcom_mdio_ipq4018_set_phy_reg_addr(struct qcom_mdio_ipq4018_softc * sc,int phy,int reg)179 qcom_mdio_ipq4018_set_phy_reg_addr(struct qcom_mdio_ipq4018_softc *sc,
180 int phy, int reg)
181 {
182
183 MDIO_LOCK_ASSERT(sc);
184
185 MDIO_WRITE(sc, QCOM_IPQ4018_MDIO_REG_ADDR,
186 ((phy & 0xff) << 8) | (reg & 0xff));
187 MDIO_BARRIER_WRITE(sc);
188 }
189
190 static int
qcom_mdio_ipq4018_readreg(device_t dev,int phy,int reg)191 qcom_mdio_ipq4018_readreg(device_t dev, int phy, int reg)
192 {
193 struct qcom_mdio_ipq4018_softc *sc = device_get_softc(dev);
194 uint32_t ret;
195
196 QCOM_MDIO_DPRINTF(sc, QCOM_MDIO_DEBUG_REG_READ,
197 "%s: called; phy=0x%x reg=0x%x\n",
198 __func__, phy, reg);
199
200 MDIO_LOCK(sc);
201 if (qcom_mdio_ipq4018_wait(sc) != 0) {
202 MDIO_UNLOCK(sc);
203 return (-1);
204 }
205
206 /* Set phy/reg values */
207 qcom_mdio_ipq4018_set_phy_reg_addr(sc, phy, reg);
208
209 /* Issue read command */
210 MDIO_WRITE(sc, QCOM_IPQ4018_MDIO_REG_CMD,
211 QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_START |
212 QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_CODE_READ);
213 MDIO_BARRIER_WRITE(sc);
214
215 /* Wait for completion */
216 if (qcom_mdio_ipq4018_wait(sc) != 0) {
217 MDIO_UNLOCK(sc);
218 return (-1);
219 }
220
221 /* Fetch return register value */
222 MDIO_BARRIER_READ(sc);
223 ret = MDIO_READ(sc, QCOM_IPQ4018_MDIO_REG_READ);
224 MDIO_UNLOCK(sc);
225
226 QCOM_MDIO_DPRINTF(sc, QCOM_MDIO_DEBUG_REG_READ,
227 "%s: -> 0x%x\n", __func__, ret);
228
229 return (ret);
230 }
231
232 static int
qcom_mdio_ipq4018_writereg(device_t dev,int phy,int reg,int value)233 qcom_mdio_ipq4018_writereg(device_t dev, int phy, int reg, int value)
234 {
235 struct qcom_mdio_ipq4018_softc *sc = device_get_softc(dev);
236
237 QCOM_MDIO_DPRINTF(sc, QCOM_MDIO_DEBUG_REG_WRITE,
238 "%s: called; phy=0x%x reg=0x%x val=0x%x\n",
239 __func__, phy, reg, value);
240
241 MDIO_LOCK(sc);
242 if (qcom_mdio_ipq4018_wait(sc) != 0) {
243 MDIO_UNLOCK(sc);
244 return (-1);
245 }
246
247 /* Set phy/reg values */
248 qcom_mdio_ipq4018_set_phy_reg_addr(sc, phy, reg);
249
250 /* Write command */
251 MDIO_WRITE(sc, QCOM_IPQ4018_MDIO_REG_WRITE, value);
252 MDIO_BARRIER_WRITE(sc);
253
254 /* Issue write command */
255 MDIO_WRITE(sc, QCOM_IPQ4018_MDIO_REG_CMD,
256 QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_START |
257 QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_CODE_WRITE);
258 MDIO_BARRIER_WRITE(sc);
259
260 /* Wait for completion */
261 if (qcom_mdio_ipq4018_wait(sc) != 0) {
262 MDIO_UNLOCK(sc);
263 return (-1);
264 }
265 MDIO_UNLOCK(sc);
266
267 return (0);
268 }
269
270 static device_method_t qcom_mdio_ipq4018_methods[] = {
271 /* Driver */
272 DEVMETHOD(device_probe, qcom_mdio_ipq4018_probe),
273 DEVMETHOD(device_attach, qcom_mdio_ipq4018_attach),
274 DEVMETHOD(device_detach, qcom_mdio_ipq4018_detach),
275
276 /* Bus interface */
277 DEVMETHOD(bus_add_child, bus_generic_add_child),
278
279 /* MDIO interface */
280 DEVMETHOD(mdio_readreg, qcom_mdio_ipq4018_readreg),
281 DEVMETHOD(mdio_writereg, qcom_mdio_ipq4018_writereg),
282
283 {0, 0},
284 };
285
286 static driver_t qcom_mdio_ipq4018_driver = {
287 "mdio",
288 qcom_mdio_ipq4018_methods,
289 sizeof(struct qcom_mdio_ipq4018_softc),
290 };
291
292 EARLY_DRIVER_MODULE(qcom_mdio_ipq4018, simplebus, qcom_mdio_ipq4018_driver,
293 NULL, NULL, BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_LATE);
294
295 MODULE_DEPEND(qcom_mdio_ipq4018, ether, 1, 1, 1);
296 MODULE_DEPEND(qcom_mdio_ipq4018, mdio, 1, 1, 1);
297 MODULE_DEPEND(qcom_mdio_ipq4018, miibus, 1, 1, 1);
298
299 MODULE_VERSION(qcom_mdio_ipq4018, 1);
300