1 /*-
2 * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by BAE Systems, the University of Cambridge
6 * Computer Laboratory, and Memorial University under DARPA/AFRL contract
7 * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing
8 * (TC) research program.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/kthread.h>
36 #include <sys/rman.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <machine/bus.h>
40
41 #include <dev/ofw/ofw_bus.h>
42 #include <dev/ofw/ofw_bus_subr.h>
43
44 #define GCC_QDSS_BCR 0x29000
45 #define GCC_QDSS_BCR_BLK_ARES (1 << 0) /* Async software reset. */
46 #define GCC_QDSS_CFG_AHB_CBCR 0x29008
47 #define AHB_CBCR_CLK_ENABLE (1 << 0) /* AHB clk branch ctrl */
48 #define GCC_QDSS_ETR_USB_CBCR 0x29028
49 #define ETR_USB_CBCR_CLK_ENABLE (1 << 0) /* ETR USB clk branch ctrl */
50 #define GCC_QDSS_DAP_CBCR 0x29084
51 #define DAP_CBCR_CLK_ENABLE (1 << 0) /* DAP clk branch ctrl */
52
53 static struct ofw_compat_data compat_data[] = {
54 { "qcom,gcc-msm8916", 1 },
55 { NULL, 0 }
56 };
57
58 struct qcom_gcc_softc {
59 struct resource *res;
60 };
61
62 static struct resource_spec qcom_gcc_spec[] = {
63 { SYS_RES_MEMORY, 0, RF_ACTIVE },
64 { -1, 0 }
65 };
66
67 /*
68 * Qualcomm Debug Subsystem (QDSS)
69 * block enabling routine.
70 */
71 static void
qcom_qdss_enable(struct qcom_gcc_softc * sc)72 qcom_qdss_enable(struct qcom_gcc_softc *sc)
73 {
74
75 /* Put QDSS block to reset */
76 bus_write_4(sc->res, GCC_QDSS_BCR, GCC_QDSS_BCR_BLK_ARES);
77
78 /* Enable AHB clock branch */
79 bus_write_4(sc->res, GCC_QDSS_CFG_AHB_CBCR, AHB_CBCR_CLK_ENABLE);
80
81 /* Enable DAP clock branch */
82 bus_write_4(sc->res, GCC_QDSS_DAP_CBCR, DAP_CBCR_CLK_ENABLE);
83
84 /* Enable ETR USB clock branch */
85 bus_write_4(sc->res, GCC_QDSS_ETR_USB_CBCR, ETR_USB_CBCR_CLK_ENABLE);
86
87 /* Out of reset */
88 bus_write_4(sc->res, GCC_QDSS_BCR, 0);
89 }
90
91 static int
qcom_gcc_probe(device_t dev)92 qcom_gcc_probe(device_t dev)
93 {
94 if (!ofw_bus_status_okay(dev))
95 return (ENXIO);
96
97 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
98 return (ENXIO);
99
100 device_set_desc(dev, "Qualcomm Global Clock Controller");
101
102 return (BUS_PROBE_DEFAULT);
103 }
104
105 static int
qcom_gcc_attach(device_t dev)106 qcom_gcc_attach(device_t dev)
107 {
108 struct qcom_gcc_softc *sc;
109
110 sc = device_get_softc(dev);
111
112 if (bus_alloc_resources(dev, qcom_gcc_spec, &sc->res) != 0) {
113 device_printf(dev, "cannot allocate resources for device\n");
114 return (ENXIO);
115 }
116
117 /*
118 * Enable debug unit.
119 * This is required for Coresight operation.
120 * This also enables USB clock branch.
121 */
122 qcom_qdss_enable(sc);
123
124 return (0);
125 }
126
127 static device_method_t qcom_gcc_methods[] = {
128 /* Device interface */
129 DEVMETHOD(device_probe, qcom_gcc_probe),
130 DEVMETHOD(device_attach, qcom_gcc_attach),
131
132 DEVMETHOD_END
133 };
134
135 static driver_t qcom_gcc_driver = {
136 "qcom_gcc",
137 qcom_gcc_methods,
138 sizeof(struct qcom_gcc_softc),
139 };
140
141 EARLY_DRIVER_MODULE(qcom_gcc, simplebus, qcom_gcc_driver, 0, 0,
142 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
143 MODULE_VERSION(qcom_gcc, 1);
144