1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/sort.h> 6 #include <linux/udp.h> 7 8 #include "cam.h" 9 #include "chan.h" 10 #include "coex.h" 11 #include "core.h" 12 #include "efuse.h" 13 #include "fw.h" 14 #include "mac.h" 15 #include "phy.h" 16 #include "ps.h" 17 #include "reg.h" 18 #include "sar.h" 19 #include "ser.h" 20 #include "txrx.h" 21 #include "util.h" 22 #include "wow.h" 23 24 static bool rtw89_disable_ps_mode; 25 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 26 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 27 28 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 29 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 30 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 31 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 32 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 33 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 34 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 35 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 36 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 37 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 38 39 static struct ieee80211_channel rtw89_channels_2ghz[] = { 40 RTW89_DEF_CHAN_2G(2412, 1), 41 RTW89_DEF_CHAN_2G(2417, 2), 42 RTW89_DEF_CHAN_2G(2422, 3), 43 RTW89_DEF_CHAN_2G(2427, 4), 44 RTW89_DEF_CHAN_2G(2432, 5), 45 RTW89_DEF_CHAN_2G(2437, 6), 46 RTW89_DEF_CHAN_2G(2442, 7), 47 RTW89_DEF_CHAN_2G(2447, 8), 48 RTW89_DEF_CHAN_2G(2452, 9), 49 RTW89_DEF_CHAN_2G(2457, 10), 50 RTW89_DEF_CHAN_2G(2462, 11), 51 RTW89_DEF_CHAN_2G(2467, 12), 52 RTW89_DEF_CHAN_2G(2472, 13), 53 RTW89_DEF_CHAN_2G(2484, 14), 54 }; 55 56 static struct ieee80211_channel rtw89_channels_5ghz[] = { 57 RTW89_DEF_CHAN_5G(5180, 36), 58 RTW89_DEF_CHAN_5G(5200, 40), 59 RTW89_DEF_CHAN_5G(5220, 44), 60 RTW89_DEF_CHAN_5G(5240, 48), 61 RTW89_DEF_CHAN_5G(5260, 52), 62 RTW89_DEF_CHAN_5G(5280, 56), 63 RTW89_DEF_CHAN_5G(5300, 60), 64 RTW89_DEF_CHAN_5G(5320, 64), 65 RTW89_DEF_CHAN_5G(5500, 100), 66 RTW89_DEF_CHAN_5G(5520, 104), 67 RTW89_DEF_CHAN_5G(5540, 108), 68 RTW89_DEF_CHAN_5G(5560, 112), 69 RTW89_DEF_CHAN_5G(5580, 116), 70 RTW89_DEF_CHAN_5G(5600, 120), 71 RTW89_DEF_CHAN_5G(5620, 124), 72 RTW89_DEF_CHAN_5G(5640, 128), 73 RTW89_DEF_CHAN_5G(5660, 132), 74 RTW89_DEF_CHAN_5G(5680, 136), 75 RTW89_DEF_CHAN_5G(5700, 140), 76 RTW89_DEF_CHAN_5G(5720, 144), 77 RTW89_DEF_CHAN_5G(5745, 149), 78 RTW89_DEF_CHAN_5G(5765, 153), 79 RTW89_DEF_CHAN_5G(5785, 157), 80 RTW89_DEF_CHAN_5G(5805, 161), 81 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 82 RTW89_DEF_CHAN_5G(5845, 169), 83 RTW89_DEF_CHAN_5G(5865, 173), 84 RTW89_DEF_CHAN_5G(5885, 177), 85 }; 86 87 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM == 88 ARRAY_SIZE(rtw89_channels_5ghz)); 89 90 static struct ieee80211_channel rtw89_channels_6ghz[] = { 91 RTW89_DEF_CHAN_6G(5955, 1), 92 RTW89_DEF_CHAN_6G(5975, 5), 93 RTW89_DEF_CHAN_6G(5995, 9), 94 RTW89_DEF_CHAN_6G(6015, 13), 95 RTW89_DEF_CHAN_6G(6035, 17), 96 RTW89_DEF_CHAN_6G(6055, 21), 97 RTW89_DEF_CHAN_6G(6075, 25), 98 RTW89_DEF_CHAN_6G(6095, 29), 99 RTW89_DEF_CHAN_6G(6115, 33), 100 RTW89_DEF_CHAN_6G(6135, 37), 101 RTW89_DEF_CHAN_6G(6155, 41), 102 RTW89_DEF_CHAN_6G(6175, 45), 103 RTW89_DEF_CHAN_6G(6195, 49), 104 RTW89_DEF_CHAN_6G(6215, 53), 105 RTW89_DEF_CHAN_6G(6235, 57), 106 RTW89_DEF_CHAN_6G(6255, 61), 107 RTW89_DEF_CHAN_6G(6275, 65), 108 RTW89_DEF_CHAN_6G(6295, 69), 109 RTW89_DEF_CHAN_6G(6315, 73), 110 RTW89_DEF_CHAN_6G(6335, 77), 111 RTW89_DEF_CHAN_6G(6355, 81), 112 RTW89_DEF_CHAN_6G(6375, 85), 113 RTW89_DEF_CHAN_6G(6395, 89), 114 RTW89_DEF_CHAN_6G(6415, 93), 115 RTW89_DEF_CHAN_6G(6435, 97), 116 RTW89_DEF_CHAN_6G(6455, 101), 117 RTW89_DEF_CHAN_6G(6475, 105), 118 RTW89_DEF_CHAN_6G(6495, 109), 119 RTW89_DEF_CHAN_6G(6515, 113), 120 RTW89_DEF_CHAN_6G(6535, 117), 121 RTW89_DEF_CHAN_6G(6555, 121), 122 RTW89_DEF_CHAN_6G(6575, 125), 123 RTW89_DEF_CHAN_6G(6595, 129), 124 RTW89_DEF_CHAN_6G(6615, 133), 125 RTW89_DEF_CHAN_6G(6635, 137), 126 RTW89_DEF_CHAN_6G(6655, 141), 127 RTW89_DEF_CHAN_6G(6675, 145), 128 RTW89_DEF_CHAN_6G(6695, 149), 129 RTW89_DEF_CHAN_6G(6715, 153), 130 RTW89_DEF_CHAN_6G(6735, 157), 131 RTW89_DEF_CHAN_6G(6755, 161), 132 RTW89_DEF_CHAN_6G(6775, 165), 133 RTW89_DEF_CHAN_6G(6795, 169), 134 RTW89_DEF_CHAN_6G(6815, 173), 135 RTW89_DEF_CHAN_6G(6835, 177), 136 RTW89_DEF_CHAN_6G(6855, 181), 137 RTW89_DEF_CHAN_6G(6875, 185), 138 RTW89_DEF_CHAN_6G(6895, 189), 139 RTW89_DEF_CHAN_6G(6915, 193), 140 RTW89_DEF_CHAN_6G(6935, 197), 141 RTW89_DEF_CHAN_6G(6955, 201), 142 RTW89_DEF_CHAN_6G(6975, 205), 143 RTW89_DEF_CHAN_6G(6995, 209), 144 RTW89_DEF_CHAN_6G(7015, 213), 145 RTW89_DEF_CHAN_6G(7035, 217), 146 RTW89_DEF_CHAN_6G(7055, 221), 147 RTW89_DEF_CHAN_6G(7075, 225), 148 RTW89_DEF_CHAN_6G(7095, 229), 149 RTW89_DEF_CHAN_6G(7115, 233), 150 }; 151 152 static struct ieee80211_rate rtw89_bitrates[] = { 153 { .bitrate = 10, .hw_value = 0x00, }, 154 { .bitrate = 20, .hw_value = 0x01, }, 155 { .bitrate = 55, .hw_value = 0x02, }, 156 { .bitrate = 110, .hw_value = 0x03, }, 157 { .bitrate = 60, .hw_value = 0x04, }, 158 { .bitrate = 90, .hw_value = 0x05, }, 159 { .bitrate = 120, .hw_value = 0x06, }, 160 { .bitrate = 180, .hw_value = 0x07, }, 161 { .bitrate = 240, .hw_value = 0x08, }, 162 { .bitrate = 360, .hw_value = 0x09, }, 163 { .bitrate = 480, .hw_value = 0x0a, }, 164 { .bitrate = 540, .hw_value = 0x0b, }, 165 }; 166 167 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 168 { 169 .max = 1, 170 .types = BIT(NL80211_IFTYPE_STATION), 171 }, 172 { 173 .max = 1, 174 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 175 BIT(NL80211_IFTYPE_P2P_GO) | 176 BIT(NL80211_IFTYPE_AP), 177 }, 178 }; 179 180 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = { 181 { 182 .max = 1, 183 .types = BIT(NL80211_IFTYPE_STATION), 184 }, 185 { 186 .max = 1, 187 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 188 BIT(NL80211_IFTYPE_P2P_GO), 189 }, 190 }; 191 192 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 193 { 194 .limits = rtw89_iface_limits, 195 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 196 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 197 .num_different_channels = 1, 198 }, 199 { 200 .limits = rtw89_iface_limits_mcc, 201 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc), 202 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 203 .num_different_channels = 2, 204 }, 205 }; 206 207 static const u8 rtw89_ext_capa_sta[] = { 208 [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, 209 [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, 210 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, 211 }; 212 213 static const struct wiphy_iftype_ext_capab rtw89_iftypes_ext_capa[] = { 214 { 215 .iftype = NL80211_IFTYPE_STATION, 216 .extended_capabilities = rtw89_ext_capa_sta, 217 .extended_capabilities_mask = rtw89_ext_capa_sta, 218 .extended_capabilities_len = sizeof(rtw89_ext_capa_sta), 219 /* relevant only if EHT is supported */ 220 .eml_capabilities = 0, 221 .mld_capa_and_ops = 0, 222 }, 223 }; 224 225 #define RTW89_6GHZ_SPAN_HEAD 6145 226 #define RTW89_6GHZ_SPAN_IDX(center_freq) \ 227 ((((int)(center_freq) - RTW89_6GHZ_SPAN_HEAD) / 5) / 2) 228 229 #define RTW89_DECL_6GHZ_SPAN(center_freq, subband_l, subband_h) \ 230 [RTW89_6GHZ_SPAN_IDX(center_freq)] = { \ 231 .sar_subband_low = RTW89_SAR_6GHZ_ ## subband_l, \ 232 .sar_subband_high = RTW89_SAR_6GHZ_ ## subband_h, \ 233 .acpi_sar_subband_low = RTW89_ACPI_SAR_6GHZ_ ## subband_l, \ 234 .acpi_sar_subband_high = RTW89_ACPI_SAR_6GHZ_ ## subband_h, \ 235 .ant_gain_subband_low = RTW89_ANT_GAIN_6GHZ_ ## subband_l, \ 236 .ant_gain_subband_high = RTW89_ANT_GAIN_6GHZ_ ## subband_h, \ 237 } 238 239 /* Since 6GHz subbands are not edge aligned, some cases span two subbands. 240 * In the following, we describe each of them with rtw89_6ghz_span. 241 */ 242 static const struct rtw89_6ghz_span rtw89_overlapping_6ghz[] = { 243 RTW89_DECL_6GHZ_SPAN(6145, SUBBAND_5_L, SUBBAND_5_H), 244 RTW89_DECL_6GHZ_SPAN(6165, SUBBAND_5_L, SUBBAND_5_H), 245 RTW89_DECL_6GHZ_SPAN(6185, SUBBAND_5_L, SUBBAND_5_H), 246 RTW89_DECL_6GHZ_SPAN(6505, SUBBAND_6, SUBBAND_7_L), 247 RTW89_DECL_6GHZ_SPAN(6525, SUBBAND_6, SUBBAND_7_L), 248 RTW89_DECL_6GHZ_SPAN(6545, SUBBAND_6, SUBBAND_7_L), 249 RTW89_DECL_6GHZ_SPAN(6665, SUBBAND_7_L, SUBBAND_7_H), 250 RTW89_DECL_6GHZ_SPAN(6705, SUBBAND_7_L, SUBBAND_7_H), 251 RTW89_DECL_6GHZ_SPAN(6825, SUBBAND_7_H, SUBBAND_8), 252 RTW89_DECL_6GHZ_SPAN(6865, SUBBAND_7_H, SUBBAND_8), 253 RTW89_DECL_6GHZ_SPAN(6875, SUBBAND_7_H, SUBBAND_8), 254 RTW89_DECL_6GHZ_SPAN(6885, SUBBAND_7_H, SUBBAND_8), 255 }; 256 257 const struct rtw89_6ghz_span * 258 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq) 259 { 260 int idx; 261 262 if (center_freq >= RTW89_6GHZ_SPAN_HEAD) { 263 idx = RTW89_6GHZ_SPAN_IDX(center_freq); 264 /* To decrease size of rtw89_overlapping_6ghz[], 265 * RTW89_6GHZ_SPAN_IDX() truncates the leading NULLs 266 * to make first span as index 0 of the table. So, if center 267 * frequency is less than the first one, it will get netative. 268 */ 269 if (idx >= 0 && idx < ARRAY_SIZE(rtw89_overlapping_6ghz)) 270 return &rtw89_overlapping_6ghz[idx]; 271 } 272 273 return NULL; 274 } 275 276 bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate) 277 { 278 const struct ieee80211_rate *rate; 279 280 if (unlikely(legacy_rate >= ARRAY_SIZE(rtw89_bitrates))) { 281 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 282 "invalid legacy rate %d\n", legacy_rate); 283 return false; 284 } 285 286 rate = &rtw89_bitrates[legacy_rate]; 287 *bitrate = rate->bitrate; 288 289 return true; 290 } 291 292 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 293 .band = NL80211_BAND_2GHZ, 294 .channels = rtw89_channels_2ghz, 295 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 296 .bitrates = rtw89_bitrates, 297 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 298 .ht_cap = {0}, 299 .vht_cap = {0}, 300 }; 301 302 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 303 .band = NL80211_BAND_5GHZ, 304 .channels = rtw89_channels_5ghz, 305 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 306 307 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 308 .bitrates = rtw89_bitrates + 4, 309 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 310 .ht_cap = {0}, 311 .vht_cap = {0}, 312 }; 313 314 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 315 .band = NL80211_BAND_6GHZ, 316 .channels = rtw89_channels_6ghz, 317 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 318 319 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 320 .bitrates = rtw89_bitrates + 4, 321 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 322 }; 323 324 static const struct rtw89_hw_rate_def { 325 enum rtw89_hw_rate ht; 326 enum rtw89_hw_rate vht[RTW89_NSS_NUM]; 327 } rtw89_hw_rate[RTW89_CHIP_GEN_NUM] = { 328 [RTW89_CHIP_AX] = { 329 .ht = RTW89_HW_RATE_MCS0, 330 .vht = {RTW89_HW_RATE_VHT_NSS1_MCS0, 331 RTW89_HW_RATE_VHT_NSS2_MCS0, 332 RTW89_HW_RATE_VHT_NSS3_MCS0, 333 RTW89_HW_RATE_VHT_NSS4_MCS0}, 334 }, 335 [RTW89_CHIP_BE] = { 336 .ht = RTW89_HW_RATE_V1_MCS0, 337 .vht = {RTW89_HW_RATE_V1_VHT_NSS1_MCS0, 338 RTW89_HW_RATE_V1_VHT_NSS2_MCS0, 339 RTW89_HW_RATE_V1_VHT_NSS3_MCS0, 340 RTW89_HW_RATE_V1_VHT_NSS4_MCS0}, 341 }, 342 }; 343 344 static void __rtw89_traffic_stats_accu(struct rtw89_traffic_stats *stats, 345 struct sk_buff *skb, bool tx) 346 { 347 if (tx) { 348 stats->tx_cnt++; 349 stats->tx_unicast += skb->len; 350 } else { 351 stats->rx_cnt++; 352 stats->rx_unicast += skb->len; 353 } 354 } 355 356 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 357 struct rtw89_vif *rtwvif, 358 struct sk_buff *skb, 359 bool accu_dev, bool tx) 360 { 361 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 362 363 if (!ieee80211_is_data(hdr->frame_control)) 364 return; 365 366 if (is_broadcast_ether_addr(hdr->addr1) || 367 is_multicast_ether_addr(hdr->addr1)) 368 return; 369 370 if (accu_dev) 371 __rtw89_traffic_stats_accu(&rtwdev->stats, skb, tx); 372 373 if (rtwvif) { 374 __rtw89_traffic_stats_accu(&rtwvif->stats, skb, tx); 375 __rtw89_traffic_stats_accu(&rtwvif->stats_ps, skb, tx); 376 } 377 } 378 379 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 380 { 381 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 382 NL80211_CHAN_NO_HT); 383 } 384 385 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 386 struct rtw89_chan *chan) 387 { 388 struct ieee80211_channel *channel = chandef->chan; 389 enum nl80211_chan_width width = chandef->width; 390 u32 primary_freq, center_freq; 391 u8 center_chan; 392 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 393 u32 offset; 394 u8 band; 395 396 center_chan = channel->hw_value; 397 primary_freq = channel->center_freq; 398 center_freq = chandef->center_freq1; 399 400 switch (width) { 401 case NL80211_CHAN_WIDTH_20_NOHT: 402 case NL80211_CHAN_WIDTH_20: 403 bandwidth = RTW89_CHANNEL_WIDTH_20; 404 break; 405 case NL80211_CHAN_WIDTH_40: 406 bandwidth = RTW89_CHANNEL_WIDTH_40; 407 if (primary_freq > center_freq) { 408 center_chan -= 2; 409 } else { 410 center_chan += 2; 411 } 412 break; 413 case NL80211_CHAN_WIDTH_80: 414 case NL80211_CHAN_WIDTH_160: 415 bandwidth = nl_to_rtw89_bandwidth(width); 416 if (primary_freq > center_freq) { 417 offset = (primary_freq - center_freq - 10) / 20; 418 center_chan -= 2 + offset * 4; 419 } else { 420 offset = (center_freq - primary_freq - 10) / 20; 421 center_chan += 2 + offset * 4; 422 } 423 break; 424 default: 425 center_chan = 0; 426 break; 427 } 428 429 switch (channel->band) { 430 default: 431 case NL80211_BAND_2GHZ: 432 band = RTW89_BAND_2G; 433 break; 434 case NL80211_BAND_5GHZ: 435 band = RTW89_BAND_5G; 436 break; 437 case NL80211_BAND_6GHZ: 438 band = RTW89_BAND_6G; 439 break; 440 } 441 442 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 443 } 444 445 static void __rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev, 446 const struct rtw89_chan *chan, 447 enum rtw89_phy_idx phy_idx) 448 { 449 const struct rtw89_chip_info *chip = rtwdev->chip; 450 bool entity_active; 451 452 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 453 if (!entity_active) 454 return; 455 456 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 457 } 458 459 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 460 { 461 const struct rtw89_chan *chan; 462 463 chan = rtw89_mgnt_chan_get(rtwdev, 0); 464 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_0); 465 466 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX) 467 return; 468 469 chan = rtw89_mgnt_chan_get(rtwdev, 1); 470 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_1); 471 } 472 473 void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 474 struct rtw89_vif_link *rtwvif_link) 475 { 476 const struct rtw89_chip_info *chip = rtwdev->chip; 477 bool mon = !!rtwdev->pure_monitor_mode_vif; 478 bool prehdl_link = false; 479 480 if (chip->chip_gen != RTW89_CHIP_AX && 481 !RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw) && 482 !mon && !rtw89_entity_check_hw(rtwdev, rtwvif_link->phy_idx)) 483 prehdl_link = true; 484 485 if (prehdl_link) { 486 rtw89_entity_force_hw(rtwdev, rtwvif_link->phy_idx); 487 rtw89_set_channel(rtwdev); 488 } 489 490 if (chip->ops->rfk_channel) 491 chip->ops->rfk_channel(rtwdev, rtwvif_link); 492 493 if (prehdl_link) { 494 rtw89_entity_force_hw(rtwdev, RTW89_PHY_NUM); 495 rtw89_set_channel(rtwdev); 496 } 497 } 498 499 static void rtw89_chip_rfk_channel_for_pure_mon_vif(struct rtw89_dev *rtwdev, 500 enum rtw89_phy_idx phy_idx) 501 { 502 struct rtw89_vif *rtwvif = rtwdev->pure_monitor_mode_vif; 503 struct rtw89_vif_link *rtwvif_link; 504 505 if (!rtwvif) 506 return; 507 508 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, phy_idx); 509 if (!rtwvif_link) 510 return; 511 512 rtw89_chip_rfk_channel(rtwdev, rtwvif_link); 513 } 514 515 static void __rtw89_set_channel(struct rtw89_dev *rtwdev, 516 const struct rtw89_chan *chan, 517 enum rtw89_mac_idx mac_idx, 518 enum rtw89_phy_idx phy_idx) 519 { 520 const struct rtw89_chip_info *chip = rtwdev->chip; 521 const struct rtw89_chan_rcd *chan_rcd; 522 struct rtw89_channel_help_params bak; 523 bool entity_active; 524 525 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 526 527 chan_rcd = rtw89_chan_rcd_get_by_chan(chan); 528 529 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 530 531 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 532 533 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 534 535 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 536 537 if (!entity_active || chan_rcd->band_changed) { 538 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 539 rtw89_chip_rfk_band_changed(rtwdev, phy_idx, chan); 540 } 541 542 rtw89_set_entity_state(rtwdev, phy_idx, true); 543 544 rtw89_chip_rfk_channel_for_pure_mon_vif(rtwdev, phy_idx); 545 } 546 547 int rtw89_set_channel(struct rtw89_dev *rtwdev) 548 { 549 const struct rtw89_chan *chan; 550 enum rtw89_entity_mode mode; 551 552 mode = rtw89_entity_recalc(rtwdev); 553 if (mode < 0 || mode >= NUM_OF_RTW89_ENTITY_MODE) { 554 WARN(1, "Invalid ent mode: %d\n", mode); 555 return -EINVAL; 556 } 557 558 chan = rtw89_mgnt_chan_get(rtwdev, 0); 559 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_0, RTW89_PHY_0); 560 561 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX) 562 return 0; 563 564 chan = rtw89_mgnt_chan_get(rtwdev, 1); 565 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_1, RTW89_PHY_1); 566 567 return 0; 568 } 569 570 static enum rtw89_core_tx_type 571 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 572 struct sk_buff *skb) 573 { 574 struct ieee80211_hdr *hdr = (void *)skb->data; 575 __le16 fc = hdr->frame_control; 576 577 if (ieee80211_is_mgmt(fc) || ieee80211_is_any_nullfunc(fc)) 578 return RTW89_CORE_TX_TYPE_MGMT; 579 580 return RTW89_CORE_TX_TYPE_DATA; 581 } 582 583 static void 584 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 585 struct rtw89_core_tx_request *tx_req, 586 enum btc_pkt_type pkt_type) 587 { 588 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 589 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 590 struct ieee80211_link_sta *link_sta; 591 struct sk_buff *skb = tx_req->skb; 592 struct rtw89_sta *rtwsta; 593 u8 ampdu_num; 594 u8 tid; 595 596 if (pkt_type == PACKET_EAPOL) { 597 desc_info->bk = true; 598 return; 599 } 600 601 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 602 return; 603 604 if (!rtwsta_link) { 605 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 606 return; 607 } 608 609 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 610 rtwsta = rtwsta_link->rtwsta; 611 612 rcu_read_lock(); 613 614 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 615 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 616 rtwsta->ampdu_params[tid].agg_num : 617 4 << link_sta->ht_cap.ampdu_factor) - 1); 618 619 desc_info->agg_en = true; 620 desc_info->ampdu_density = link_sta->ht_cap.ampdu_density; 621 desc_info->ampdu_num = ampdu_num; 622 623 rcu_read_unlock(); 624 } 625 626 static void 627 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 628 struct rtw89_core_tx_request *tx_req) 629 { 630 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 631 const struct rtw89_chip_info *chip = rtwdev->chip; 632 const struct rtw89_sec_cam_entry *sec_cam; 633 struct ieee80211_tx_info *info; 634 struct ieee80211_key_conf *key; 635 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 636 struct sk_buff *skb = tx_req->skb; 637 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 638 u8 sec_cam_idx; 639 u64 pn64; 640 641 info = IEEE80211_SKB_CB(skb); 642 key = info->control.hw_key; 643 sec_cam_idx = key->hw_key_idx; 644 sec_cam = cam_info->sec_entries[sec_cam_idx]; 645 if (!sec_cam) { 646 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 647 return; 648 } 649 650 switch (key->cipher) { 651 case WLAN_CIPHER_SUITE_WEP40: 652 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 653 break; 654 case WLAN_CIPHER_SUITE_WEP104: 655 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 656 break; 657 case WLAN_CIPHER_SUITE_TKIP: 658 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 659 break; 660 case WLAN_CIPHER_SUITE_CCMP: 661 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 662 break; 663 case WLAN_CIPHER_SUITE_CCMP_256: 664 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 665 break; 666 case WLAN_CIPHER_SUITE_GCMP: 667 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 668 break; 669 case WLAN_CIPHER_SUITE_GCMP_256: 670 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 671 break; 672 default: 673 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 674 return; 675 } 676 677 desc_info->sec_en = true; 678 desc_info->sec_keyid = key->keyidx; 679 desc_info->sec_type = sec_type; 680 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 681 682 if (!chip->hw_sec_hdr) 683 return; 684 685 pn64 = atomic64_inc_return(&key->tx_pn); 686 desc_info->sec_seq[0] = pn64; 687 desc_info->sec_seq[1] = pn64 >> 8; 688 desc_info->sec_seq[2] = pn64 >> 16; 689 desc_info->sec_seq[3] = pn64 >> 24; 690 desc_info->sec_seq[4] = pn64 >> 32; 691 desc_info->sec_seq[5] = pn64 >> 40; 692 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 693 } 694 695 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 696 struct rtw89_core_tx_request *tx_req, 697 const struct rtw89_chan *chan) 698 { 699 struct sk_buff *skb = tx_req->skb; 700 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 701 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 702 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 703 struct ieee80211_vif *vif = tx_info->control.vif; 704 struct ieee80211_bss_conf *bss_conf; 705 u16 lowest_rate; 706 u16 rate; 707 708 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 709 (vif && vif->p2p)) 710 lowest_rate = RTW89_HW_RATE_OFDM6; 711 else if (chan->band_type == RTW89_BAND_2G) 712 lowest_rate = RTW89_HW_RATE_CCK1; 713 else 714 lowest_rate = RTW89_HW_RATE_OFDM6; 715 716 if (!rtwvif_link) 717 return lowest_rate; 718 719 rcu_read_lock(); 720 721 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 722 if (!bss_conf->basic_rates || !rtwsta_link) { 723 rate = lowest_rate; 724 goto out; 725 } 726 727 rate = __ffs(bss_conf->basic_rates) + lowest_rate; 728 729 out: 730 rcu_read_unlock(); 731 732 return rate; 733 } 734 735 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 736 struct rtw89_core_tx_request *tx_req) 737 { 738 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 739 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 740 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 741 742 if (desc_info->mlo && !desc_info->sw_mld) { 743 if (rtwsta_link) 744 return rtw89_sta_get_main_macid(rtwsta_link->rtwsta); 745 else 746 return rtw89_vif_get_main_macid(rtwvif_link->rtwvif); 747 } 748 749 if (!rtwsta_link) 750 return rtwvif_link->mac_id; 751 752 return rtwsta_link->mac_id; 753 } 754 755 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 756 struct rtw89_tx_desc_info *desc_info, 757 struct sk_buff *skb) 758 { 759 struct ieee80211_hdr *hdr = (void *)skb->data; 760 __le16 fc = hdr->frame_control; 761 762 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 763 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 764 } 765 766 u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 767 { 768 switch (qsel) { 769 default: 770 rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel); 771 fallthrough; 772 case RTW89_TX_QSEL_BE_0: 773 case RTW89_TX_QSEL_BE_1: 774 case RTW89_TX_QSEL_BE_2: 775 case RTW89_TX_QSEL_BE_3: 776 return RTW89_TXCH_ACH0; 777 case RTW89_TX_QSEL_BK_0: 778 case RTW89_TX_QSEL_BK_1: 779 case RTW89_TX_QSEL_BK_2: 780 case RTW89_TX_QSEL_BK_3: 781 return RTW89_TXCH_ACH1; 782 case RTW89_TX_QSEL_VI_0: 783 case RTW89_TX_QSEL_VI_1: 784 case RTW89_TX_QSEL_VI_2: 785 case RTW89_TX_QSEL_VI_3: 786 return RTW89_TXCH_ACH2; 787 case RTW89_TX_QSEL_VO_0: 788 case RTW89_TX_QSEL_VO_1: 789 case RTW89_TX_QSEL_VO_2: 790 case RTW89_TX_QSEL_VO_3: 791 return RTW89_TXCH_ACH3; 792 case RTW89_TX_QSEL_B0_MGMT: 793 return RTW89_TXCH_CH8; 794 case RTW89_TX_QSEL_B0_HI: 795 return RTW89_TXCH_CH9; 796 case RTW89_TX_QSEL_B1_MGMT: 797 return RTW89_TXCH_CH10; 798 case RTW89_TX_QSEL_B1_HI: 799 return RTW89_TXCH_CH11; 800 } 801 } 802 EXPORT_SYMBOL(rtw89_core_get_ch_dma); 803 804 u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel) 805 { 806 switch (qsel) { 807 default: 808 rtw89_warn(rtwdev, "Cannot map qsel to dma v1: %d\n", qsel); 809 fallthrough; 810 case RTW89_TX_QSEL_BE_0: 811 case RTW89_TX_QSEL_BK_0: 812 return RTW89_TXCH_ACH0; 813 case RTW89_TX_QSEL_VI_0: 814 case RTW89_TX_QSEL_VO_0: 815 return RTW89_TXCH_ACH2; 816 case RTW89_TX_QSEL_B0_MGMT: 817 case RTW89_TX_QSEL_B0_HI: 818 return RTW89_TXCH_CH8; 819 case RTW89_TX_QSEL_B1_MGMT: 820 case RTW89_TX_QSEL_B1_HI: 821 return RTW89_TXCH_CH10; 822 } 823 } 824 EXPORT_SYMBOL(rtw89_core_get_ch_dma_v1); 825 826 u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel) 827 { 828 switch (qsel) { 829 default: 830 rtw89_warn(rtwdev, "Cannot map qsel to dma v2: %d\n", qsel); 831 fallthrough; 832 case RTW89_TX_QSEL_BE_0: 833 case RTW89_TX_QSEL_VO_0: 834 return RTW89_TXCH_ACH0; 835 case RTW89_TX_QSEL_BK_0: 836 case RTW89_TX_QSEL_VI_0: 837 return RTW89_TXCH_ACH2; 838 case RTW89_TX_QSEL_B0_MGMT: 839 case RTW89_TX_QSEL_B0_HI: 840 return RTW89_TXCH_CH8; 841 } 842 } 843 EXPORT_SYMBOL(rtw89_core_get_ch_dma_v2); 844 845 static void 846 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 847 struct rtw89_core_tx_request *tx_req) 848 { 849 const struct rtw89_chip_info *chip = rtwdev->chip; 850 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 851 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 852 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 853 rtwvif_link->chanctx_idx); 854 struct sk_buff *skb = tx_req->skb; 855 u8 qsel, ch_dma; 856 857 qsel = rtw89_core_get_qsel_mgmt(rtwdev, tx_req); 858 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 859 860 desc_info->qsel = qsel; 861 desc_info->ch_dma = ch_dma; 862 desc_info->sw_mld = true; 863 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 864 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 865 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 866 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 867 868 /* fixed data rate for mgmt frames */ 869 desc_info->en_wd_info = true; 870 desc_info->use_rate = true; 871 desc_info->dis_data_fb = true; 872 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 873 874 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) { 875 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 876 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 877 } 878 879 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 880 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 881 desc_info->data_rate, chan->channel, chan->band_type, 882 chan->band_width); 883 } 884 885 static void 886 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 887 struct rtw89_core_tx_request *tx_req) 888 { 889 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 890 891 desc_info->is_bmc = false; 892 desc_info->wd_page = false; 893 desc_info->ch_dma = RTW89_DMA_H2C; 894 } 895 896 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 897 const struct rtw89_chan *chan) 898 { 899 static const u8 rtw89_bandwidth_to_om[] = { 900 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 901 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 902 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 903 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 904 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 905 }; 906 const struct rtw89_chip_info *chip = rtwdev->chip; 907 struct rtw89_hal *hal = &rtwdev->hal; 908 u8 om_bandwidth; 909 910 if (!chip->dis_2g_40m_ul_ofdma || 911 chan->band_type != RTW89_BAND_2G || 912 chan->band_width != RTW89_CHANNEL_WIDTH_40) 913 return; 914 915 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 916 rtw89_bandwidth_to_om[chan->band_width] : 0; 917 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 918 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 919 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 920 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 921 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 922 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 923 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 924 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 925 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 926 } 927 928 static bool 929 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 930 struct rtw89_core_tx_request *tx_req, 931 enum btc_pkt_type pkt_type) 932 { 933 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 934 struct sk_buff *skb = tx_req->skb; 935 struct ieee80211_hdr *hdr = (void *)skb->data; 936 struct ieee80211_link_sta *link_sta; 937 __le16 fc = hdr->frame_control; 938 939 /* AP IOT issue with EAPoL, ARP and DHCP */ 940 if (pkt_type < PACKET_MAX) 941 return false; 942 943 if (!rtwsta_link) 944 return false; 945 946 rcu_read_lock(); 947 948 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 949 if (!link_sta->he_cap.has_he) { 950 rcu_read_unlock(); 951 return false; 952 } 953 954 rcu_read_unlock(); 955 956 if (!ieee80211_is_data_qos(fc)) 957 return false; 958 959 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 960 return false; 961 962 if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy) 963 return false; 964 965 return true; 966 } 967 968 static void 969 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 970 struct rtw89_core_tx_request *tx_req) 971 { 972 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 973 struct sk_buff *skb = tx_req->skb; 974 struct ieee80211_hdr *hdr = (void *)skb->data; 975 __le16 fc = hdr->frame_control; 976 void *data; 977 __le32 *htc; 978 u8 *qc; 979 int hdr_len; 980 981 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 982 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 983 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 984 985 hdr = data; 986 htc = data + hdr_len; 987 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 988 *htc = rtwsta_link->htc_template ? rtwsta_link->htc_template : 989 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 990 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 991 992 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 993 qc[0] |= IEEE80211_QOS_CTL_EOSP; 994 } 995 996 static void 997 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 998 struct rtw89_core_tx_request *tx_req, 999 enum btc_pkt_type pkt_type) 1000 { 1001 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1002 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 1003 1004 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 1005 goto desc_bk; 1006 1007 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 1008 1009 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 1010 desc_info->a_ctrl_bsr = true; 1011 1012 desc_bk: 1013 if (!rtwvif_link || rtwvif_link->last_a_ctrl == desc_info->a_ctrl_bsr) 1014 return; 1015 1016 rtwvif_link->last_a_ctrl = desc_info->a_ctrl_bsr; 1017 desc_info->bk = true; 1018 } 1019 1020 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 1021 struct rtw89_core_tx_request *tx_req) 1022 { 1023 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 1024 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 1025 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 1026 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern; 1027 enum rtw89_chanctx_idx idx = rtwvif_link->chanctx_idx; 1028 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 1029 struct ieee80211_link_sta *link_sta; 1030 u16 lowest_rate; 1031 u16 rate; 1032 1033 if (rate_pattern->enable) 1034 return rate_pattern->rate; 1035 1036 if (vif->p2p) 1037 lowest_rate = RTW89_HW_RATE_OFDM6; 1038 else if (chan->band_type == RTW89_BAND_2G) 1039 lowest_rate = RTW89_HW_RATE_CCK1; 1040 else 1041 lowest_rate = RTW89_HW_RATE_OFDM6; 1042 1043 if (!rtwsta_link) 1044 return lowest_rate; 1045 1046 rcu_read_lock(); 1047 1048 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 1049 if (!link_sta->supp_rates[chan->band_type]) { 1050 rate = lowest_rate; 1051 goto out; 1052 } 1053 1054 rate = __ffs(link_sta->supp_rates[chan->band_type]) + lowest_rate; 1055 1056 out: 1057 rcu_read_unlock(); 1058 1059 return rate; 1060 } 1061 1062 static void 1063 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 1064 struct rtw89_core_tx_request *tx_req) 1065 { 1066 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 1067 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 1068 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1069 struct sk_buff *skb = tx_req->skb; 1070 u8 tid, tid_indicate; 1071 u8 qsel, ch_dma; 1072 1073 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 1074 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 1075 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 1076 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 1077 1078 desc_info->ch_dma = ch_dma; 1079 desc_info->tid_indicate = tid_indicate; 1080 desc_info->qsel = qsel; 1081 desc_info->sw_mld = false; 1082 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 1083 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 1084 desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false; 1085 desc_info->stbc = rtwsta_link ? rtwsta_link->ra.stbc_cap : false; 1086 desc_info->ldpc = rtwsta_link ? rtwsta_link->ra.ldpc_cap : false; 1087 1088 /* enable wd_info for AMPDU */ 1089 desc_info->en_wd_info = true; 1090 1091 if (IEEE80211_SKB_CB(skb)->control.hw_key) 1092 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 1093 1094 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 1095 } 1096 1097 static enum btc_pkt_type 1098 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 1099 struct rtw89_core_tx_request *tx_req) 1100 { 1101 struct wiphy *wiphy = rtwdev->hw->wiphy; 1102 struct sk_buff *skb = tx_req->skb; 1103 struct udphdr *udphdr; 1104 1105 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 1106 wiphy_work_queue(wiphy, &rtwdev->btc.eapol_notify_work); 1107 return PACKET_EAPOL; 1108 } 1109 1110 if (skb->protocol == htons(ETH_P_ARP)) { 1111 wiphy_work_queue(wiphy, &rtwdev->btc.arp_notify_work); 1112 return PACKET_ARP; 1113 } 1114 1115 if (skb->protocol == htons(ETH_P_IP) && 1116 ip_hdr(skb)->protocol == IPPROTO_UDP) { 1117 udphdr = udp_hdr(skb); 1118 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 1119 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 1120 skb->len > 282) { 1121 wiphy_work_queue(wiphy, &rtwdev->btc.dhcp_notify_work); 1122 return PACKET_DHCP; 1123 } 1124 } 1125 1126 if (skb->protocol == htons(ETH_P_IP) && 1127 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 1128 wiphy_work_queue(wiphy, &rtwdev->btc.icmp_notify_work); 1129 return PACKET_ICMP; 1130 } 1131 1132 return PACKET_MAX; 1133 } 1134 1135 static void 1136 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 1137 struct rtw89_core_tx_request *tx_req) 1138 { 1139 const struct rtw89_chip_info *chip = rtwdev->chip; 1140 1141 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 1142 return; 1143 1144 switch (chip->chip_id) { 1145 case RTL8852BT: 1146 if (test_bit(RTW89_FLAG_LEISURE_PS, rtwdev->flags)) 1147 goto notify; 1148 break; 1149 case RTL8852C: 1150 if (test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 1151 goto notify; 1152 break; 1153 default: 1154 if (test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags) && 1155 tx_req->tx_type == RTW89_CORE_TX_TYPE_MGMT) 1156 goto notify; 1157 break; 1158 } 1159 1160 return; 1161 1162 notify: 1163 rtw89_mac_notify_wake(rtwdev); 1164 } 1165 1166 static void rtw89_core_tx_update_injection(struct rtw89_dev *rtwdev, 1167 struct rtw89_core_tx_request *tx_req, 1168 struct ieee80211_tx_info *info) 1169 { 1170 const struct rtw89_hw_rate_def *hw_rate = &rtw89_hw_rate[rtwdev->chip->chip_gen]; 1171 enum mac80211_rate_control_flags flags = info->control.rates[0].flags; 1172 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1173 const struct rtw89_chan *chan; 1174 u8 idx = info->control.rates[0].idx; 1175 u8 nss, mcs; 1176 1177 desc_info->use_rate = true; 1178 desc_info->dis_data_fb = true; 1179 1180 if (flags & IEEE80211_TX_RC_160_MHZ_WIDTH) 1181 desc_info->data_bw = 3; 1182 else if (flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 1183 desc_info->data_bw = 2; 1184 else if (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1185 desc_info->data_bw = 1; 1186 1187 if (flags & IEEE80211_TX_RC_SHORT_GI) 1188 desc_info->gi_ltf = 1; 1189 1190 if (flags & IEEE80211_TX_RC_VHT_MCS) { 1191 nss = umin(idx >> 4, ARRAY_SIZE(hw_rate->vht) - 1); 1192 mcs = idx & 0xf; 1193 desc_info->data_rate = hw_rate->vht[nss] + mcs; 1194 } else if (flags & IEEE80211_TX_RC_MCS) { 1195 desc_info->data_rate = hw_rate->ht + idx; 1196 } else { 1197 chan = rtw89_chan_get(rtwdev, tx_req->rtwvif_link->chanctx_idx); 1198 1199 desc_info->data_rate = idx + (chan->band_type == RTW89_BAND_2G ? 1200 RTW89_HW_RATE_CCK1 : RTW89_HW_RATE_OFDM6); 1201 } 1202 } 1203 1204 static void 1205 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 1206 struct rtw89_core_tx_request *tx_req) 1207 { 1208 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1209 struct sk_buff *skb = tx_req->skb; 1210 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1211 struct ieee80211_hdr *hdr = (void *)skb->data; 1212 struct rtw89_addr_cam_entry *addr_cam; 1213 enum btc_pkt_type pkt_type; 1214 bool upd_wlan_hdr = false; 1215 bool is_bmc; 1216 u16 seq; 1217 1218 desc_info->pkt_size = skb->len; 1219 1220 if (unlikely(tx_req->tx_type == RTW89_CORE_TX_TYPE_FWCMD)) { 1221 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 1222 return; 1223 } 1224 1225 tx_req->tx_type = rtw89_core_get_tx_type(rtwdev, skb); 1226 1227 if (tx_req->sta) 1228 desc_info->mlo = tx_req->sta->mlo; 1229 else if (tx_req->vif) 1230 desc_info->mlo = ieee80211_vif_is_mld(tx_req->vif); 1231 1232 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 1233 addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link, 1234 tx_req->rtwsta_link); 1235 if (addr_cam->valid && desc_info->mlo) 1236 upd_wlan_hdr = true; 1237 1238 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS || tx_req->with_wait) 1239 rtw89_tx_rpt_init(rtwdev, tx_req); 1240 1241 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 1242 is_multicast_ether_addr(hdr->addr1)); 1243 1244 desc_info->seq = seq; 1245 desc_info->is_bmc = is_bmc; 1246 desc_info->wd_page = true; 1247 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 1248 desc_info->upd_wlan_hdr = upd_wlan_hdr; 1249 1250 switch (tx_req->tx_type) { 1251 case RTW89_CORE_TX_TYPE_MGMT: 1252 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 1253 break; 1254 case RTW89_CORE_TX_TYPE_DATA: 1255 rtw89_core_tx_update_data_info(rtwdev, tx_req); 1256 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 1257 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 1258 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 1259 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 1260 break; 1261 default: 1262 break; 1263 } 1264 1265 if (unlikely(info->flags & IEEE80211_TX_CTL_INJECTED)) 1266 rtw89_core_tx_update_injection(rtwdev, tx_req, info); 1267 } 1268 1269 static void rtw89_tx_wait_work(struct wiphy *wiphy, struct wiphy_work *work) 1270 { 1271 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 1272 tx_wait_work.work); 1273 1274 rtw89_tx_wait_list_clear(rtwdev); 1275 } 1276 1277 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 1278 { 1279 u8 ch_dma; 1280 1281 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 1282 1283 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 1284 } 1285 1286 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1287 struct rtw89_tx_wait_info *wait, int qsel, 1288 unsigned int timeout) 1289 { 1290 unsigned long time_left; 1291 int ret = 0; 1292 1293 lockdep_assert_wiphy(rtwdev->hw->wiphy); 1294 1295 rtw89_core_tx_kick_off(rtwdev, qsel); 1296 time_left = wait_for_completion_timeout(&wait->completion, 1297 msecs_to_jiffies(timeout)); 1298 1299 if (time_left == 0) { 1300 ret = -ETIMEDOUT; 1301 list_add_tail(&wait->list, &rtwdev->tx_waits); 1302 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->tx_wait_work, 1303 RTW89_TX_WAIT_WORK_TIMEOUT); 1304 } else { 1305 if (!wait->tx_done) 1306 ret = -EAGAIN; 1307 rtw89_tx_wait_release(wait); 1308 } 1309 1310 return ret; 1311 } 1312 1313 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 1314 struct sk_buff *skb, bool fwdl) 1315 { 1316 struct rtw89_core_tx_request tx_req = {0}; 1317 u32 cnt; 1318 int ret; 1319 1320 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 1321 rtw89_debug(rtwdev, RTW89_DBG_FW, 1322 "ignore h2c due to power is off with firmware state=%d\n", 1323 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 1324 dev_kfree_skb(skb); 1325 return 0; 1326 } 1327 1328 tx_req.skb = skb; 1329 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 1330 if (fwdl) 1331 tx_req.desc_info.fw_dl = true; 1332 1333 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1334 1335 if (!fwdl) 1336 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 1337 1338 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 1339 if (cnt == 0) { 1340 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 1341 return -ENOSPC; 1342 } 1343 1344 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1345 if (ret) { 1346 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1347 return ret; 1348 } 1349 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 1350 1351 return 0; 1352 } 1353 1354 static int rtw89_core_tx_write_link(struct rtw89_dev *rtwdev, 1355 struct rtw89_vif_link *rtwvif_link, 1356 struct rtw89_sta_link *rtwsta_link, 1357 struct sk_buff *skb, int *qsel, 1358 struct rtw89_tx_wait_info *wait) 1359 { 1360 struct ieee80211_sta *sta = rtwsta_link_to_sta_safe(rtwsta_link); 1361 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 1362 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 1363 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 1364 struct rtw89_core_tx_request tx_req = {}; 1365 int ret; 1366 1367 tx_req.skb = skb; 1368 tx_req.vif = vif; 1369 tx_req.sta = sta; 1370 tx_req.rtwvif_link = rtwvif_link; 1371 tx_req.rtwsta_link = rtwsta_link; 1372 tx_req.with_wait = !!wait; 1373 1374 rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, true, true); 1375 rtw89_wow_parse_akm(rtwdev, skb); 1376 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1377 rtw89_core_tx_wake(rtwdev, &tx_req); 1378 1379 rcu_assign_pointer(skb_data->wait, wait); 1380 1381 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1382 if (ret) { 1383 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1384 return ret; 1385 } 1386 1387 if (qsel) 1388 *qsel = tx_req.desc_info.qsel; 1389 1390 return 0; 1391 } 1392 1393 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1394 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1395 { 1396 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 1397 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 1398 struct rtw89_sta_link *rtwsta_link = NULL; 1399 struct rtw89_vif_link *rtwvif_link; 1400 1401 if (rtwsta) { 1402 rtwsta_link = rtw89_get_designated_link(rtwsta); 1403 if (unlikely(!rtwsta_link)) { 1404 rtw89_err(rtwdev, "tx: find no sta designated link\n"); 1405 return -ENOLINK; 1406 } 1407 1408 rtwvif_link = rtwsta_link->rtwvif_link; 1409 } else { 1410 rtwvif_link = rtw89_get_designated_link(rtwvif); 1411 if (unlikely(!rtwvif_link)) { 1412 rtw89_err(rtwdev, "tx: find no vif designated link\n"); 1413 return -ENOLINK; 1414 } 1415 } 1416 1417 return rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, qsel, NULL); 1418 } 1419 1420 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1421 { 1422 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1423 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1424 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1425 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1426 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1427 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1428 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1429 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1430 1431 return cpu_to_le32(dword); 1432 } 1433 1434 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1435 { 1436 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1437 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1438 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1439 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1440 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1441 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1442 1443 return cpu_to_le32(dword); 1444 } 1445 1446 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1447 { 1448 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1449 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1450 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1451 1452 return cpu_to_le32(dword); 1453 } 1454 1455 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1456 { 1457 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1458 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1459 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1460 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1461 1462 return cpu_to_le32(dword); 1463 } 1464 1465 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1466 { 1467 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1468 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1469 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1470 1471 return cpu_to_le32(dword); 1472 } 1473 1474 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1475 { 1476 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1477 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1478 1479 return cpu_to_le32(dword); 1480 } 1481 1482 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1483 { 1484 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1485 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1486 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1487 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1488 1489 return cpu_to_le32(dword); 1490 } 1491 1492 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1493 { 1494 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1495 FIELD_PREP(RTW89_TXWD_BODY7_DATA_BW, desc_info->data_bw) | 1496 FIELD_PREP(RTW89_TXWD_BODY7_GI_LTF, desc_info->gi_ltf) | 1497 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1498 1499 return cpu_to_le32(dword); 1500 } 1501 1502 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1503 { 1504 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1505 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW, desc_info->data_bw) | 1506 FIELD_PREP(RTW89_TXWD_INFO0_GI_LTF, desc_info->gi_ltf) | 1507 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1508 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1509 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1510 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1511 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1512 1513 return cpu_to_le32(dword); 1514 } 1515 1516 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1517 { 1518 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1519 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1520 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1521 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1522 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1523 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1524 1525 return cpu_to_le32(dword); 1526 } 1527 1528 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1529 { 1530 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1531 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1532 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1533 desc_info->data_retry_lowest_rate) | 1534 FIELD_PREP(RTW89_TXWD_INFO1_DATA_TXCNT_LMT_SEL, 1535 desc_info->tx_cnt_lmt_en) | 1536 FIELD_PREP(RTW89_TXWD_INFO1_DATA_TXCNT_LMT, desc_info->tx_cnt_lmt); 1537 1538 return cpu_to_le32(dword); 1539 } 1540 1541 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1542 { 1543 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1544 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1545 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1546 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1547 1548 return cpu_to_le32(dword); 1549 } 1550 1551 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1552 { 1553 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1554 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1555 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1556 1557 return cpu_to_le32(dword); 1558 } 1559 1560 static __le32 rtw89_build_txwd_info3(struct rtw89_tx_desc_info *desc_info) 1561 { 1562 u32 dword = FIELD_PREP(RTW89_TXWD_INFO3_SPE_RPT, desc_info->report); 1563 1564 return cpu_to_le32(dword); 1565 } 1566 1567 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1568 { 1569 bool rts_en = !desc_info->is_bmc; 1570 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) | 1571 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1) | 1572 FIELD_PREP(RTW89_TXWD_INFO4_SW_DEFINE, desc_info->sn); 1573 1574 return cpu_to_le32(dword); 1575 } 1576 1577 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1578 struct rtw89_tx_desc_info *desc_info, 1579 void *txdesc) 1580 { 1581 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1582 struct rtw89_txwd_info *txwd_info; 1583 1584 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1585 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1586 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1587 1588 if (!desc_info->en_wd_info) 1589 return; 1590 1591 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1592 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1593 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1594 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1595 txwd_info->dword3 = rtw89_build_txwd_info3(desc_info); 1596 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1597 1598 } 1599 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1600 1601 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1602 struct rtw89_tx_desc_info *desc_info, 1603 void *txdesc) 1604 { 1605 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1606 struct rtw89_txwd_info *txwd_info; 1607 1608 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1609 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1610 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1611 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1612 if (desc_info->sec_en) { 1613 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1614 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1615 } 1616 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1617 1618 if (!desc_info->en_wd_info) 1619 return; 1620 1621 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1622 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1623 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1624 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1625 txwd_info->dword3 = rtw89_build_txwd_info3(desc_info); 1626 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1627 } 1628 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1629 1630 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info) 1631 { 1632 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1633 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) | 1634 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) | 1635 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1636 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page); 1637 1638 return cpu_to_le32(dword); 1639 } 1640 1641 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info) 1642 { 1643 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1644 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1645 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type); 1646 1647 return cpu_to_le32(dword); 1648 } 1649 1650 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info) 1651 { 1652 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) | 1653 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) | 1654 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1655 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1656 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) | 1657 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id); 1658 1659 return cpu_to_le32(dword); 1660 } 1661 1662 static __le32 rtw89_build_txwd_body2_v3(struct rtw89_tx_desc_info *desc_info) 1663 { 1664 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND_V1, desc_info->tid_indicate) | 1665 FIELD_PREP(BE_TXD_BODY2_QSEL_V1, desc_info->qsel) | 1666 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1667 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1668 FIELD_PREP(BE_TXD_BODY2_MACID_V1, desc_info->mac_id); 1669 1670 return cpu_to_le32(dword); 1671 } 1672 1673 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info) 1674 { 1675 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) | 1676 FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) | 1677 FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld); 1678 1679 return cpu_to_le32(dword); 1680 } 1681 1682 static __le32 rtw89_build_txwd_body3_v3(struct rtw89_tx_desc_info *desc_info) 1683 { 1684 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) | 1685 FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) | 1686 FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld) | 1687 FIELD_PREP(BE_TXD_BODY3_BK_V1, desc_info->bk); 1688 1689 return cpu_to_le32(dword); 1690 } 1691 1692 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info) 1693 { 1694 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1695 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1696 1697 return cpu_to_le32(dword); 1698 } 1699 1700 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info) 1701 { 1702 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1703 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1704 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1705 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1706 1707 return cpu_to_le32(dword); 1708 } 1709 1710 static __le32 rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info *desc_info) 1711 { 1712 u32 dword = FIELD_PREP(BE_TXD_BODY6_UPD_WLAN_HDR, desc_info->upd_wlan_hdr); 1713 1714 return cpu_to_le32(dword); 1715 } 1716 1717 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info) 1718 { 1719 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) | 1720 FIELD_PREP(BE_TXD_BODY7_DATA_BW, desc_info->data_bw) | 1721 FIELD_PREP(BE_TXD_BODY7_GI_LTF, desc_info->gi_ltf) | 1722 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) | 1723 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) | 1724 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate); 1725 1726 return cpu_to_le32(dword); 1727 } 1728 1729 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info) 1730 { 1731 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) | 1732 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) | 1733 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1734 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port) | 1735 FIELD_PREP(BE_TXD_INFO0_DATA_TXCNT_LMT_SEL, 1736 desc_info->tx_cnt_lmt_en) | 1737 FIELD_PREP(BE_TXD_INFO0_DATA_TXCNT_LMT, desc_info->tx_cnt_lmt); 1738 1739 return cpu_to_le32(dword); 1740 } 1741 1742 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info) 1743 { 1744 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) | 1745 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1746 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE, 1747 desc_info->data_retry_lowest_rate) | 1748 FIELD_PREP(BE_TXD_INFO1_SW_DEFINE, desc_info->sn); 1749 1750 return cpu_to_le32(dword); 1751 } 1752 1753 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info) 1754 { 1755 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1756 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1757 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx) | 1758 FIELD_PREP(BE_TXD_INFO2_SPE_RPT_V1, desc_info->report); 1759 1760 return cpu_to_le32(dword); 1761 } 1762 1763 static __le32 rtw89_build_txwd_info2_v3(struct rtw89_tx_desc_info *desc_info) 1764 { 1765 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1766 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN_V1, desc_info->sec_en) | 1767 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX_V1, desc_info->sec_cam_idx); 1768 1769 return cpu_to_le32(dword); 1770 } 1771 1772 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info) 1773 { 1774 bool rts_en = !desc_info->is_bmc; 1775 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) | 1776 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1); 1777 1778 return cpu_to_le32(dword); 1779 } 1780 1781 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 1782 struct rtw89_tx_desc_info *desc_info, 1783 void *txdesc) 1784 { 1785 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1786 struct rtw89_txwd_info_v2 *txwd_info; 1787 1788 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1789 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1790 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info); 1791 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info); 1792 if (desc_info->sec_en) { 1793 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1794 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1795 } 1796 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info); 1797 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1798 1799 if (!desc_info->en_wd_info) 1800 return; 1801 1802 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1803 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1804 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1805 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info); 1806 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1807 } 1808 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2); 1809 1810 void rtw89_core_fill_txdesc_v3(struct rtw89_dev *rtwdev, 1811 struct rtw89_tx_desc_info *desc_info, 1812 void *txdesc) 1813 { 1814 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1815 struct rtw89_txwd_info_v2 *txwd_info; 1816 1817 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1818 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1819 txwd_body->dword2 = rtw89_build_txwd_body2_v3(desc_info); 1820 txwd_body->dword3 = rtw89_build_txwd_body3_v3(desc_info); 1821 if (desc_info->sec_en) { 1822 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1823 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1824 } 1825 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info); 1826 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1827 1828 if (!desc_info->en_wd_info) 1829 return; 1830 1831 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1832 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1833 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1834 txwd_info->dword2 = rtw89_build_txwd_info2_v3(desc_info); 1835 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1836 } 1837 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v3); 1838 1839 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1840 { 1841 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1842 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1843 RTW89_CORE_RX_TYPE_FWDL : 1844 RTW89_CORE_RX_TYPE_H2C); 1845 1846 return cpu_to_le32(dword); 1847 } 1848 1849 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1850 struct rtw89_tx_desc_info *desc_info, 1851 void *txdesc) 1852 { 1853 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1854 1855 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1856 } 1857 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1858 1859 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info) 1860 { 1861 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1862 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1863 RTW89_CORE_RX_TYPE_FWDL : 1864 RTW89_CORE_RX_TYPE_H2C); 1865 1866 return cpu_to_le32(dword); 1867 } 1868 1869 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 1870 struct rtw89_tx_desc_info *desc_info, 1871 void *txdesc) 1872 { 1873 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc; 1874 1875 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info); 1876 } 1877 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2); 1878 1879 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1880 struct sk_buff *skb, 1881 struct rtw89_rx_phy_ppdu *phy_ppdu) 1882 { 1883 const struct rtw89_chip_info *chip = rtwdev->chip; 1884 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data; 1885 const struct rtw89_rxinfo_user *user; 1886 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 1887 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE; 1888 bool rx_cnt_valid = false; 1889 bool invalid = false; 1890 u8 plcp_size = 0; 1891 u8 *phy_sts; 1892 u8 usr_num; 1893 int i; 1894 1895 if (chip_gen == RTW89_CHIP_BE) { 1896 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1); 1897 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1; 1898 } 1899 1900 if (invalid) 1901 return -EINVAL; 1902 1903 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1904 if (chip_gen == RTW89_CHIP_BE) { 1905 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3; 1906 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1); 1907 } else { 1908 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1909 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1910 } 1911 if (usr_num > chip->ppdu_max_usr) { 1912 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n", 1913 usr_num); 1914 return -EINVAL; 1915 } 1916 1917 for (i = 0; i < usr_num; i++) { 1918 user = &rxinfo->user[i]; 1919 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID)) 1920 continue; 1921 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set 1922 * by hardware, so update mac_id by rxinfo_user[].mac_id. 1923 */ 1924 if (chip->chip_id == RTL8922A) 1925 phy_ppdu->mac_id = 1926 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID); 1927 else if (chip->chip_id == RTL8922D) 1928 phy_ppdu->mac_id = 1929 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID_V1); 1930 1931 phy_ppdu->has_data = 1932 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA); 1933 phy_ppdu->has_bcn = 1934 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN); 1935 break; 1936 } 1937 1938 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1939 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1940 /* 8-byte alignment */ 1941 if (usr_num & BIT(0)) 1942 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1943 if (rx_cnt_valid) 1944 phy_sts += rx_cnt_size; 1945 phy_sts += plcp_size; 1946 1947 if (phy_sts > skb->data + skb->len) 1948 return -EINVAL; 1949 1950 phy_ppdu->buf = phy_sts; 1951 phy_ppdu->len = skb->data + skb->len - phy_sts; 1952 1953 return 0; 1954 } 1955 1956 static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate) 1957 { 1958 u8 data_rate_mode; 1959 1960 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1961 switch (data_rate_mode) { 1962 case DATA_RATE_MODE_NON_HT: 1963 return 1; 1964 case DATA_RATE_MODE_HT: 1965 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1; 1966 case DATA_RATE_MODE_VHT: 1967 case DATA_RATE_MODE_HE: 1968 case DATA_RATE_MODE_EHT: 1969 return rtw89_get_data_nss(rtwdev, data_rate) + 1; 1970 default: 1971 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1972 return 0; 1973 } 1974 } 1975 1976 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1977 struct ieee80211_sta *sta) 1978 { 1979 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1980 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 1981 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1982 struct rtw89_hal *hal = &rtwdev->hal; 1983 struct rtw89_sta_link *rtwsta_link; 1984 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 1985 u8 ant_pos = U8_MAX; 1986 u8 evm_pos = 0; 1987 int i; 1988 1989 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, phy_ppdu->phy_idx); 1990 if (unlikely(!rtwsta_link)) 1991 return; 1992 1993 if (rtwsta_link->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 1994 return; 1995 1996 if (hal->ant_diversity && hal->antenna_rx) { 1997 ant_pos = __ffs(hal->antenna_rx); 1998 evm_pos = ant_pos; 1999 } 2000 2001 ewma_rssi_add(&rtwsta_link->avg_rssi, phy_ppdu->rssi_avg); 2002 2003 if (ant_pos < ant_num) { 2004 ewma_rssi_add(&rtwsta_link->rssi[ant_pos], phy_ppdu->rssi[0]); 2005 } else { 2006 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 2007 ewma_rssi_add(&rtwsta_link->rssi[i], phy_ppdu->rssi[i]); 2008 } 2009 2010 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) { 2011 ewma_snr_add(&rtwsta_link->avg_snr, phy_ppdu->ofdm.avg_snr); 2012 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) { 2013 ewma_evm_add(&rtwsta_link->evm_1ss, phy_ppdu->ofdm.evm_min); 2014 } else { 2015 ewma_evm_add(&rtwsta_link->evm_min[evm_pos], 2016 phy_ppdu->ofdm.evm_min); 2017 ewma_evm_add(&rtwsta_link->evm_max[evm_pos], 2018 phy_ppdu->ofdm.evm_max); 2019 } 2020 } 2021 } 2022 2023 #define VAR_LEN 0xff 2024 #define VAR_LEN_UNIT 8 2025 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 2026 const struct rtw89_phy_sts_iehdr *iehdr) 2027 { 2028 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = { 2029 [RTW89_CHIP_AX] = { 2030 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 2031 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 2032 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 2033 }, 2034 [RTW89_CHIP_BE] = { 2035 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 2036 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 88, 56, VAR_LEN, 2037 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 2038 }, 2039 }; 2040 const u8 *physts_ie_len_tab; 2041 u16 ie_len; 2042 u8 ie; 2043 2044 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen]; 2045 2046 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 2047 if (physts_ie_len_tab[ie] != VAR_LEN) 2048 ie_len = physts_ie_len_tab[ie]; 2049 else 2050 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 2051 2052 return ie_len; 2053 } 2054 2055 static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev, 2056 const struct rtw89_phy_sts_iehdr *iehdr, 2057 struct rtw89_rx_phy_ppdu *phy_ppdu) 2058 { 2059 const struct rtw89_phy_sts_ie01_v2 *ie; 2060 u8 *rpl_fd = phy_ppdu->rpl_fd; 2061 2062 ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr; 2063 rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A); 2064 rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B); 2065 rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C); 2066 rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D); 2067 2068 phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX); 2069 } 2070 2071 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 2072 const struct rtw89_phy_sts_iehdr *iehdr, 2073 struct rtw89_rx_phy_ppdu *phy_ppdu) 2074 { 2075 const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr; 2076 s16 cfo; 2077 u32 t; 2078 2079 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 2080 2081 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 2082 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC); 2083 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC); 2084 } 2085 2086 if (!phy_ppdu->hdr_2_en) 2087 phy_ppdu->rx_path_en = 2088 le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN); 2089 2090 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 2091 return; 2092 2093 if (!phy_ppdu->to_self) 2094 return; 2095 2096 phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD); 2097 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 2098 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 2099 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 2100 phy_ppdu->ofdm.has = true; 2101 2102 /* sign conversion for S(12,2) */ 2103 if (rtwdev->chip->cfo_src_fd) { 2104 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 2105 cfo = sign_extend32(t, 11); 2106 } else { 2107 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 2108 cfo = sign_extend32(t, 11); 2109 } 2110 2111 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 2112 2113 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 2114 rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu); 2115 } 2116 2117 static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev, 2118 const struct rtw89_phy_sts_iehdr *iehdr, 2119 struct rtw89_rx_phy_ppdu *phy_ppdu) 2120 { 2121 const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr; 2122 u16 tmp_rpl; 2123 2124 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL); 2125 phy_ppdu->rpl_avg = tmp_rpl >> 1; 2126 2127 if (!phy_ppdu->hdr_2_en) 2128 phy_ppdu->rx_path_en = 2129 le32_get_bits(ie->w3, RTW89_PHY_STS_IE00_W3_RX_PATH_EN); 2130 } 2131 2132 static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev, 2133 const struct rtw89_phy_sts_iehdr *iehdr, 2134 struct rtw89_rx_phy_ppdu *phy_ppdu) 2135 { 2136 const struct rtw89_phy_sts_ie00_v2 *ie; 2137 u8 *rpl_path = phy_ppdu->rpl_path; 2138 u16 tmp_rpl[RF_PATH_MAX]; 2139 u8 i; 2140 2141 ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr; 2142 tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A); 2143 tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B); 2144 tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C); 2145 tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D); 2146 2147 for (i = 0; i < RF_PATH_MAX; i++) 2148 rpl_path[i] = tmp_rpl[i] >> 1; 2149 } 2150 2151 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 2152 const struct rtw89_phy_sts_iehdr *iehdr, 2153 struct rtw89_rx_phy_ppdu *phy_ppdu) 2154 { 2155 u8 ie; 2156 2157 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 2158 2159 switch (ie) { 2160 case RTW89_PHYSTS_IE00_CMN_CCK: 2161 rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu); 2162 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 2163 rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu); 2164 break; 2165 case RTW89_PHYSTS_IE01_CMN_OFDM: 2166 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 2167 break; 2168 default: 2169 break; 2170 } 2171 2172 return 0; 2173 } 2174 2175 static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu) 2176 { 2177 const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN; 2178 2179 phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN); 2180 } 2181 2182 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 2183 { 2184 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 2185 u8 *rssi = phy_ppdu->rssi; 2186 2187 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 2188 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 2189 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 2190 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 2191 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 2192 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 2193 2194 phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN); 2195 if (phy_ppdu->hdr_2_en) 2196 rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu); 2197 } 2198 2199 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 2200 struct rtw89_rx_phy_ppdu *phy_ppdu) 2201 { 2202 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 2203 u32 len_from_header; 2204 bool physts_valid; 2205 2206 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID); 2207 if (!physts_valid) 2208 return -EINVAL; 2209 2210 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 2211 2212 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 2213 len_from_header += PHY_STS_HDR_LEN; 2214 2215 if (len_from_header != phy_ppdu->len) { 2216 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 2217 return -EINVAL; 2218 } 2219 rtw89_core_update_phy_ppdu(phy_ppdu); 2220 2221 return 0; 2222 } 2223 2224 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 2225 struct rtw89_rx_phy_ppdu *phy_ppdu) 2226 { 2227 u16 ie_len; 2228 void *pos, *end; 2229 2230 /* mark invalid reports and bypass them */ 2231 if (phy_ppdu->ie < RTW89_CCK_PKT) 2232 return -EINVAL; 2233 2234 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 2235 if (phy_ppdu->hdr_2_en) 2236 pos += PHY_STS_HDR_LEN; 2237 end = phy_ppdu->buf + phy_ppdu->len; 2238 while (pos < end) { 2239 const struct rtw89_phy_sts_iehdr *iehdr = pos; 2240 2241 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 2242 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 2243 pos += ie_len; 2244 if (pos > end || ie_len == 0) { 2245 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2246 "phy status parse failed\n"); 2247 return -EINVAL; 2248 } 2249 } 2250 2251 rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu); 2252 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 2253 2254 return 0; 2255 } 2256 2257 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 2258 struct rtw89_rx_phy_ppdu *phy_ppdu) 2259 { 2260 int ret; 2261 2262 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 2263 if (ret) 2264 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 2265 else 2266 phy_ppdu->valid = true; 2267 2268 ieee80211_iterate_stations_atomic(rtwdev->hw, 2269 rtw89_core_rx_process_phy_ppdu_iter, 2270 phy_ppdu); 2271 } 2272 2273 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, 2274 u8 desc_info_gi, 2275 bool rx_status) 2276 { 2277 switch (desc_info_gi) { 2278 case RTW89_GILTF_SGI_4XHE08: 2279 case RTW89_GILTF_2XHE08: 2280 case RTW89_GILTF_1XHE08: 2281 return NL80211_RATE_INFO_HE_GI_0_8; 2282 case RTW89_GILTF_2XHE16: 2283 case RTW89_GILTF_1XHE16: 2284 return NL80211_RATE_INFO_HE_GI_1_6; 2285 case RTW89_GILTF_LGI_4XHE32: 2286 return NL80211_RATE_INFO_HE_GI_3_2; 2287 default: 2288 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 2289 if (rx_status) 2290 return NL80211_RATE_INFO_HE_GI_3_2; 2291 return U8_MAX; 2292 } 2293 } 2294 2295 static u8 rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev *rtwdev, 2296 u8 desc_info_gi, 2297 bool rx_status) 2298 { 2299 switch (desc_info_gi) { 2300 case RTW89_GILTF_SGI_4XHE08: 2301 case RTW89_GILTF_2XHE08: 2302 case RTW89_GILTF_1XHE08: 2303 return NL80211_RATE_INFO_EHT_GI_0_8; 2304 case RTW89_GILTF_2XHE16: 2305 case RTW89_GILTF_1XHE16: 2306 return NL80211_RATE_INFO_EHT_GI_1_6; 2307 case RTW89_GILTF_LGI_4XHE32: 2308 return NL80211_RATE_INFO_EHT_GI_3_2; 2309 default: 2310 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 2311 if (rx_status) 2312 return NL80211_RATE_INFO_EHT_GI_3_2; 2313 return U8_MAX; 2314 } 2315 } 2316 2317 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev, 2318 u8 desc_info_gi, 2319 bool rx_status, bool eht) 2320 { 2321 return eht ? rtw89_rxdesc_to_nl_eht_gi(rtwdev, desc_info_gi, rx_status) : 2322 rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info_gi, rx_status); 2323 } 2324 2325 static 2326 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf, 2327 bool eht) 2328 { 2329 if (eht) 2330 return status->eht.gi == gi_ltf; 2331 2332 return status->he_gi == gi_ltf; 2333 } 2334 2335 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 2336 struct rtw89_rx_desc_info *desc_info, 2337 struct ieee80211_rx_status *status) 2338 { 2339 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2340 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 2341 bool eht = false; 2342 u16 data_rate; 2343 bool ret; 2344 2345 data_rate = desc_info->data_rate; 2346 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2347 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2348 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2349 /* rate_idx is still hardware value here */ 2350 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2351 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2352 } else if (data_rate_mode == DATA_RATE_MODE_VHT || 2353 data_rate_mode == DATA_RATE_MODE_HE || 2354 data_rate_mode == DATA_RATE_MODE_EHT) { 2355 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2356 } else { 2357 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2358 } 2359 2360 eht = data_rate_mode == DATA_RATE_MODE_EHT; 2361 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2362 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht); 2363 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 2364 status->rate_idx == rate_idx && 2365 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) && 2366 status->bw == bw; 2367 2368 return ret; 2369 } 2370 2371 struct rtw89_vif_rx_stats_iter_data { 2372 struct rtw89_dev *rtwdev; 2373 struct rtw89_rx_phy_ppdu *phy_ppdu; 2374 struct rtw89_rx_desc_info *desc_info; 2375 struct sk_buff *skb; 2376 const u8 *bssid; 2377 }; 2378 2379 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 2380 struct rtw89_vif_link *rtwvif_link, 2381 struct ieee80211_bss_conf *bss_conf, 2382 struct sk_buff *skb) 2383 { 2384 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 2385 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 2386 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 2387 u8 *pos, *end, type, tf_bw; 2388 u16 aid, tf_rua; 2389 2390 if (!ether_addr_equal(bss_conf->bssid, tf->ta) || 2391 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION || 2392 rtwvif_link->net_type == RTW89_NET_TYPE_NO_LINK) 2393 return; 2394 2395 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 2396 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR) 2397 return; 2398 2399 end = (u8 *)tf + skb->len; 2400 pos = tf->variable; 2401 2402 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 2403 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 2404 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos); 2405 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK); 2406 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2407 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n", 2408 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 2409 tf_rua, tf_bw); 2410 2411 if (aid == RTW89_TF_PAD) 2412 break; 2413 2414 if (aid == vif->cfg.aid) { 2415 enum nl80211_he_ru_alloc rua; 2416 2417 rtwvif->stats.rx_tf_acc++; 2418 rtwdev->stats.rx_tf_acc++; 2419 2420 /* The following only required for HE trigger frame, but we 2421 * cannot use UL HE-SIG-A2 reserved subfield to identify it 2422 * since some 11ax APs will fill it with all 0s, which will 2423 * be misunderstood as EHT trigger frame. 2424 */ 2425 if (bss_conf->eht_support) 2426 break; 2427 2428 rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1); 2429 2430 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ && 2431 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106) 2432 rtwvif_link->pwr_diff_en = true; 2433 break; 2434 } 2435 2436 pos += RTW89_TF_BASIC_USER_INFO_SZ; 2437 } 2438 } 2439 2440 static void rtw89_cancel_6ghz_probe_work(struct wiphy *wiphy, struct wiphy_work *work) 2441 { 2442 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2443 cancel_6ghz_probe_work); 2444 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2445 struct rtw89_pktofld_info *info; 2446 2447 lockdep_assert_wiphy(wiphy); 2448 2449 if (!rtwdev->scanning) 2450 return; 2451 2452 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2453 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 2454 continue; 2455 2456 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 2457 2458 /* Don't delete/free info from pkt_list at this moment. Let it 2459 * be deleted/freed in rtw89_release_pkt_list() after scanning, 2460 * since if during scanning, pkt_list is accessed in bottom half. 2461 */ 2462 } 2463 } 2464 2465 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 2466 struct sk_buff *skb) 2467 { 2468 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2469 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 2470 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2471 struct rtw89_pktofld_info *info; 2472 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 2473 bool queue_work = false; 2474 2475 if (rx_status->band != NL80211_BAND_6GHZ) 2476 return; 2477 2478 if (unlikely(!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))) { 2479 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rx on unsupported 6 GHz\n"); 2480 return; 2481 } 2482 2483 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 2484 2485 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2486 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 2487 info->cancel = true; 2488 queue_work = true; 2489 continue; 2490 } 2491 2492 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 2493 continue; 2494 2495 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) { 2496 info->cancel = true; 2497 queue_work = true; 2498 } 2499 } 2500 2501 if (queue_work) 2502 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->cancel_6ghz_probe_work); 2503 } 2504 2505 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link *rtwvif_link, 2506 struct ieee80211_hdr *hdr, size_t len) 2507 { 2508 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr; 2509 2510 if (len < offsetof(typeof(*mgmt), u.beacon.variable)) 2511 return; 2512 2513 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp)); 2514 } 2515 2516 static u32 rtw89_bcn_calc_min_tbtt(struct rtw89_dev *rtwdev, u32 tbtt1, u32 tbtt2) 2517 { 2518 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2519 u32 close_bcn_intvl_th = bcn_track->close_bcn_intvl_th; 2520 u32 tbtt_diff_th = bcn_track->tbtt_diff_th; 2521 2522 if (tbtt2 > tbtt1) 2523 swap(tbtt1, tbtt2); 2524 2525 if (tbtt1 - tbtt2 > tbtt_diff_th) 2526 return tbtt1; 2527 else if (tbtt2 > close_bcn_intvl_th) 2528 return tbtt2; 2529 else if (tbtt1 > close_bcn_intvl_th) 2530 return tbtt1; 2531 else 2532 return tbtt2; 2533 } 2534 2535 static void rtw89_bcn_cfg_tbtt_offset(struct rtw89_dev *rtwdev, 2536 struct rtw89_vif_link *rtwvif_link) 2537 { 2538 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2539 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2540 u32 offset = bcn_track->tbtt_offset; 2541 2542 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2543 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2544 const struct rtw89_port_reg *p = mac->port_base; 2545 u32 bcnspc, val; 2546 2547 bcnspc = rtw89_read32_port_mask(rtwdev, rtwvif_link, 2548 p->bcn_space, B_AX_BCN_SPACE_MASK); 2549 val = bcnspc - (offset / 1024); 2550 val = u32_encode_bits(val, B_AX_TBTT_SHIFT_OFST_MAG) | 2551 B_AX_TBTT_SHIFT_OFST_SIGN; 2552 2553 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_shift, 2554 B_AX_TBTT_SHIFT_OFST_MASK, val); 2555 2556 return; 2557 } 2558 2559 rtw89_fw_h2c_tbtt_tuning(rtwdev, rtwvif_link, offset); 2560 } 2561 2562 static void rtw89_bcn_update_tbtt_offset(struct rtw89_dev *rtwdev, 2563 struct rtw89_vif_link *rtwvif_link) 2564 { 2565 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2566 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2567 u32 *tbtt_us = bcn_stat->tbtt_us; 2568 u32 offset = tbtt_us[0]; 2569 u8 i; 2570 2571 for (i = 1; i < RTW89_BCN_TRACK_STAT_NR; i++) 2572 offset = rtw89_bcn_calc_min_tbtt(rtwdev, tbtt_us[i], offset); 2573 2574 if (bcn_track->tbtt_offset == offset) 2575 return; 2576 2577 bcn_track->tbtt_offset = offset; 2578 rtw89_bcn_cfg_tbtt_offset(rtwdev, rtwvif_link); 2579 } 2580 2581 static int cmp_u16(const void *a, const void *b) 2582 { 2583 return *(const u16 *)a - *(const u16 *)b; 2584 } 2585 2586 static u16 _rtw89_bcn_calc_drift(u16 tbtt, u16 offset, u16 beacon_int) 2587 { 2588 if (tbtt < offset) 2589 return beacon_int - offset + tbtt; 2590 2591 return tbtt - offset; 2592 } 2593 2594 static void rtw89_bcn_calc_drift(struct rtw89_dev *rtwdev) 2595 { 2596 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2597 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2598 u16 offset_tu = bcn_track->tbtt_offset / 1024; 2599 u16 *tbtt_tu = bcn_stat->tbtt_tu; 2600 u16 *drift = bcn_stat->drift; 2601 u8 i; 2602 2603 bcn_stat->tbtt_tu_min = U16_MAX; 2604 bcn_stat->tbtt_tu_max = 0; 2605 for (i = 0; i < RTW89_BCN_TRACK_STAT_NR; i++) { 2606 drift[i] = _rtw89_bcn_calc_drift(tbtt_tu[i], offset_tu, 2607 bcn_track->beacon_int); 2608 2609 bcn_stat->tbtt_tu_min = min(bcn_stat->tbtt_tu_min, tbtt_tu[i]); 2610 bcn_stat->tbtt_tu_max = max(bcn_stat->tbtt_tu_max, tbtt_tu[i]); 2611 } 2612 2613 sort(drift, RTW89_BCN_TRACK_STAT_NR, sizeof(*drift), cmp_u16, NULL); 2614 } 2615 2616 static void rtw89_bcn_calc_distribution(struct rtw89_dev *rtwdev) 2617 { 2618 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2619 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 2620 u16 lower_bound, upper_bound, outlier_count = 0; 2621 u16 *drift = bcn_stat->drift; 2622 u16 *bins = bcn_dist->bins; 2623 u16 q1, q3, iqr, tmp; 2624 u8 i; 2625 2626 BUILD_BUG_ON(RTW89_BCN_TRACK_STAT_NR % 4 != 0); 2627 2628 memset(bcn_dist, 0, sizeof(*bcn_dist)); 2629 2630 bcn_dist->min = drift[0]; 2631 bcn_dist->max = drift[RTW89_BCN_TRACK_STAT_NR - 1]; 2632 2633 tmp = RTW89_BCN_TRACK_STAT_NR / 4; 2634 q1 = ((drift[tmp] + drift[tmp - 1]) * RTW89_BCN_TRACK_SCALE_FACTOR) / 2; 2635 2636 tmp = (RTW89_BCN_TRACK_STAT_NR * 3) / 4; 2637 q3 = ((drift[tmp] + drift[tmp - 1]) * RTW89_BCN_TRACK_SCALE_FACTOR) / 2; 2638 2639 iqr = q3 - q1; 2640 tmp = (3 * iqr) / 2; 2641 2642 if (bcn_dist->min <= 5) 2643 lower_bound = bcn_dist->min; 2644 else if (q1 > tmp) 2645 lower_bound = (q1 - tmp) / RTW89_BCN_TRACK_SCALE_FACTOR; 2646 else 2647 lower_bound = 0; 2648 2649 upper_bound = (q3 + tmp) / RTW89_BCN_TRACK_SCALE_FACTOR; 2650 2651 for (i = 0; i < RTW89_BCN_TRACK_STAT_NR; i++) { 2652 u16 tbtt = bcn_stat->tbtt_tu[i]; 2653 u16 min = bcn_stat->tbtt_tu_min; 2654 u8 bin_idx; 2655 2656 /* histogram */ 2657 bin_idx = min((tbtt - min) / RTW89_BCN_TRACK_BIN_WIDTH, 2658 RTW89_BCN_TRACK_MAX_BIN_NUM - 1); 2659 bins[bin_idx]++; 2660 2661 /* boxplot outlier */ 2662 if (drift[i] < lower_bound || drift[i] > upper_bound) 2663 outlier_count++; 2664 } 2665 2666 bcn_dist->outlier_count = outlier_count; 2667 bcn_dist->lower_bound = lower_bound; 2668 bcn_dist->upper_bound = upper_bound; 2669 } 2670 2671 static u8 rtw89_bcn_get_coverage(struct rtw89_dev *rtwdev, u16 threshold) 2672 { 2673 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2674 int l = 0, r = RTW89_BCN_TRACK_STAT_NR - 1, m; 2675 u16 *drift = bcn_stat->drift; 2676 int index = -1; 2677 u8 count = 0; 2678 2679 while (l <= r) { 2680 m = l + (r - l) / 2; 2681 2682 if (drift[m] <= threshold) { 2683 index = m; 2684 l = m + 1; 2685 } else { 2686 r = m - 1; 2687 } 2688 } 2689 2690 count = (index == -1) ? 0 : (index + 1); 2691 2692 return (count * PERCENT) / RTW89_BCN_TRACK_STAT_NR; 2693 } 2694 2695 static u16 rtw89_bcn_get_histogram_bound(struct rtw89_dev *rtwdev, u8 target) 2696 { 2697 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2698 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 2699 u16 tbtt_tu_max = bcn_stat->tbtt_tu_max; 2700 u16 upper, lower = bcn_stat->tbtt_tu_min; 2701 u8 i, count = 0; 2702 2703 for (i = 0; i < RTW89_BCN_TRACK_MAX_BIN_NUM; i++) { 2704 upper = lower + RTW89_BCN_TRACK_BIN_WIDTH - 1; 2705 if (i == RTW89_BCN_TRACK_MAX_BIN_NUM - 1) 2706 upper = max(upper, tbtt_tu_max); 2707 2708 count += bcn_dist->bins[i]; 2709 if (count > target) 2710 break; 2711 2712 lower = upper + 1; 2713 } 2714 2715 return upper; 2716 } 2717 2718 static u16 rtw89_bcn_get_rx_time(struct rtw89_dev *rtwdev, 2719 const struct rtw89_chan *chan) 2720 { 2721 #define RTW89_SYMBOL_TIME_2GHZ 192 2722 #define RTW89_SYMBOL_TIME_5GHZ 20 2723 #define RTW89_SYMBOL_TIME_6GHZ 20 2724 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 2725 u16 bitrate, val; 2726 2727 if (!rtw89_legacy_rate_to_bitrate(rtwdev, pkt_stat->beacon_rate, &bitrate)) 2728 return 0; 2729 2730 val = (pkt_stat->beacon_len * 8 * RTW89_BCN_TRACK_SCALE_FACTOR) / bitrate; 2731 2732 switch (chan->band_type) { 2733 default: 2734 case RTW89_BAND_2G: 2735 val += RTW89_SYMBOL_TIME_2GHZ; 2736 break; 2737 case RTW89_BAND_5G: 2738 val += RTW89_SYMBOL_TIME_5GHZ; 2739 break; 2740 case RTW89_BAND_6G: 2741 val += RTW89_SYMBOL_TIME_6GHZ; 2742 break; 2743 } 2744 2745 /* convert to millisecond */ 2746 return DIV_ROUND_UP(val, 1000); 2747 } 2748 2749 static void rtw89_bcn_calc_timeout(struct rtw89_dev *rtwdev, 2750 struct rtw89_vif_link *rtwvif_link) 2751 { 2752 #define RTW89_BCN_TRACK_EXTEND_TIMEOUT 5 2753 #define RTW89_BCN_TRACK_COVERAGE_TH 0 /* unit: TU */ 2754 #define RTW89_BCN_TRACK_STRONG_RSSI 80 2755 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 2756 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 2757 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2758 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2759 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 2760 u16 outlier_high_bcn_th = bcn_track->outlier_high_bcn_th; 2761 u16 outlier_low_bcn_th = bcn_track->outlier_low_bcn_th; 2762 u8 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 2763 u16 target_bcn_th = bcn_track->target_bcn_th; 2764 u16 low_bcn_th = bcn_track->low_bcn_th; 2765 u16 med_bcn_th = bcn_track->med_bcn_th; 2766 u16 beacon_int = bcn_track->beacon_int; 2767 u16 bcn_timeout; 2768 2769 if (pkt_stat->beacon_nr < low_bcn_th) { 2770 bcn_timeout = (RTW89_BCN_TRACK_TARGET_BCN * beacon_int) / PERCENT; 2771 goto out; 2772 } 2773 2774 if (bcn_dist->outlier_count >= outlier_high_bcn_th) { 2775 bcn_timeout = bcn_dist->max; 2776 goto out; 2777 } 2778 2779 if (pkt_stat->beacon_nr < med_bcn_th) { 2780 if (bcn_dist->outlier_count > outlier_low_bcn_th) 2781 bcn_timeout = (bcn_dist->max + bcn_dist->upper_bound) / 2; 2782 else 2783 bcn_timeout = bcn_dist->upper_bound + 2784 RTW89_BCN_TRACK_EXTEND_TIMEOUT; 2785 2786 goto out; 2787 } 2788 2789 if (rssi >= RTW89_BCN_TRACK_STRONG_RSSI) { 2790 if (rtw89_bcn_get_coverage(rtwdev, RTW89_BCN_TRACK_COVERAGE_TH) >= 90) { 2791 /* ideal case */ 2792 bcn_timeout = 0; 2793 } else { 2794 u16 offset_tu = bcn_track->tbtt_offset / 1024; 2795 u16 upper_bound; 2796 2797 upper_bound = 2798 rtw89_bcn_get_histogram_bound(rtwdev, target_bcn_th); 2799 bcn_timeout = 2800 _rtw89_bcn_calc_drift(upper_bound, offset_tu, beacon_int); 2801 } 2802 2803 goto out; 2804 } 2805 2806 bcn_timeout = bcn_stat->drift[target_bcn_th]; 2807 2808 out: 2809 bcn_track->bcn_timeout = bcn_timeout + rtw89_bcn_get_rx_time(rtwdev, chan); 2810 } 2811 2812 static void rtw89_bcn_update_timeout(struct rtw89_dev *rtwdev, 2813 struct rtw89_vif_link *rtwvif_link) 2814 { 2815 rtw89_bcn_calc_drift(rtwdev); 2816 rtw89_bcn_calc_distribution(rtwdev); 2817 rtw89_bcn_calc_timeout(rtwdev, rtwvif_link); 2818 } 2819 2820 static void rtw89_core_bcn_track(struct rtw89_dev *rtwdev) 2821 { 2822 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2823 struct rtw89_vif_link *rtwvif_link; 2824 struct rtw89_vif *rtwvif; 2825 unsigned int link_id; 2826 2827 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw)) 2828 return; 2829 2830 if (!rtwdev->lps_enabled) 2831 return; 2832 2833 if (!bcn_track->is_data_ready) 2834 return; 2835 2836 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 2837 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) { 2838 if (!(rtwvif_link->wifi_role == RTW89_WIFI_ROLE_STATION || 2839 rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT)) 2840 continue; 2841 2842 rtw89_bcn_update_tbtt_offset(rtwdev, rtwvif_link); 2843 rtw89_bcn_update_timeout(rtwdev, rtwvif_link); 2844 } 2845 } 2846 } 2847 2848 static bool rtw89_core_bcn_track_can_lps(struct rtw89_dev *rtwdev) 2849 { 2850 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2851 2852 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw)) 2853 return true; 2854 2855 return bcn_track->is_data_ready; 2856 } 2857 2858 static void rtw89_core_bcn_track_assoc(struct rtw89_dev *rtwdev, 2859 struct rtw89_vif_link *rtwvif_link) 2860 { 2861 #define RTW89_BCN_TRACK_MED_BCN 70 2862 #define RTW89_BCN_TRACK_LOW_BCN 30 2863 #define RTW89_BCN_TRACK_OUTLIER_HIGH_BCN 30 2864 #define RTW89_BCN_TRACK_OUTLIER_LOW_BCN 20 2865 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2866 u32 period = jiffies_to_msecs(RTW89_TRACK_WORK_PERIOD); 2867 struct ieee80211_bss_conf *bss_conf; 2868 u32 beacons_in_period; 2869 u32 bcn_intvl_us; 2870 u16 beacon_int; 2871 u8 dtim; 2872 2873 rcu_read_lock(); 2874 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 2875 beacon_int = bss_conf->beacon_int ?: 100; 2876 dtim = bss_conf->dtim_period; 2877 rcu_read_unlock(); 2878 2879 beacons_in_period = period / beacon_int / dtim; 2880 bcn_intvl_us = ieee80211_tu_to_usec(beacon_int); 2881 2882 bcn_track->low_bcn_th = 2883 (beacons_in_period * RTW89_BCN_TRACK_LOW_BCN) / PERCENT; 2884 bcn_track->med_bcn_th = 2885 (beacons_in_period * RTW89_BCN_TRACK_MED_BCN) / PERCENT; 2886 bcn_track->outlier_low_bcn_th = 2887 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_OUTLIER_LOW_BCN) / PERCENT; 2888 bcn_track->outlier_high_bcn_th = 2889 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_OUTLIER_HIGH_BCN) / PERCENT; 2890 bcn_track->target_bcn_th = 2891 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_TARGET_BCN) / PERCENT; 2892 2893 bcn_track->close_bcn_intvl_th = ieee80211_tu_to_usec(beacon_int - 3); 2894 bcn_track->tbtt_diff_th = (bcn_intvl_us * 85) / PERCENT; 2895 bcn_track->beacon_int = beacon_int; 2896 bcn_track->dtim = dtim; 2897 } 2898 2899 static void rtw89_core_bcn_track_reset(struct rtw89_dev *rtwdev) 2900 { 2901 memset(&rtwdev->phystat.bcn_stat, 0, sizeof(rtwdev->phystat.bcn_stat)); 2902 memset(&rtwdev->bcn_track, 0, sizeof(rtwdev->bcn_track)); 2903 } 2904 2905 static void rtw89_vif_rx_bcn_stat(struct rtw89_dev *rtwdev, struct sk_buff *skb) 2906 { 2907 #define RTW89_APPEND_TSF_2GHZ 384 2908 #define RTW89_APPEND_TSF_5GHZ 52 2909 #define RTW89_APPEND_TSF_6GHZ 52 2910 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 2911 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2912 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2913 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2914 u32 bcn_intvl_us = ieee80211_tu_to_usec(bcn_track->beacon_int); 2915 u64 tsf = le64_to_cpu(mgmt->u.beacon.timestamp); 2916 u8 wp, num = bcn_stat->num; 2917 u16 append; 2918 2919 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw)) 2920 return; 2921 2922 /* Skip if not yet associated */ 2923 if (!bcn_intvl_us) 2924 return; 2925 2926 switch (rx_status->band) { 2927 default: 2928 case NL80211_BAND_2GHZ: 2929 append = RTW89_APPEND_TSF_2GHZ; 2930 break; 2931 case NL80211_BAND_5GHZ: 2932 append = RTW89_APPEND_TSF_5GHZ; 2933 break; 2934 case NL80211_BAND_6GHZ: 2935 append = RTW89_APPEND_TSF_6GHZ; 2936 break; 2937 } 2938 2939 wp = bcn_stat->wp; 2940 div_u64_rem(tsf - append, bcn_intvl_us, &bcn_stat->tbtt_us[wp]); 2941 bcn_stat->tbtt_tu[wp] = bcn_stat->tbtt_us[wp] / 1024; 2942 bcn_stat->wp = (wp + 1) % RTW89_BCN_TRACK_STAT_NR; 2943 bcn_stat->num = umin(num + 1, RTW89_BCN_TRACK_STAT_NR); 2944 bcn_track->is_data_ready = bcn_stat->num == RTW89_BCN_TRACK_STAT_NR; 2945 } 2946 2947 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 2948 struct ieee80211_vif *vif) 2949 { 2950 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 2951 struct rtw89_dev *rtwdev = iter_data->rtwdev; 2952 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 2953 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 2954 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2955 struct sk_buff *skb = iter_data->skb; 2956 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2957 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2958 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 2959 bool is_mld = ieee80211_vif_is_mld(vif); 2960 struct ieee80211_bss_conf *bss_conf; 2961 struct rtw89_vif_link *rtwvif_link; 2962 const u8 *bssid = iter_data->bssid; 2963 const u8 *target_bssid; 2964 2965 if (rtwdev->scanning && 2966 (ieee80211_is_beacon(hdr->frame_control) || 2967 ieee80211_is_probe_resp(hdr->frame_control))) 2968 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 2969 2970 rcu_read_lock(); 2971 2972 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, desc_info->bb_sel); 2973 if (unlikely(!rtwvif_link)) 2974 goto out; 2975 2976 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 2977 if (!bss_conf->bssid) 2978 goto out; 2979 2980 if (ieee80211_is_trigger(hdr->frame_control)) { 2981 rtw89_stats_trigger_frame(rtwdev, rtwvif_link, bss_conf, skb); 2982 goto out; 2983 } 2984 2985 target_bssid = ieee80211_is_beacon(hdr->frame_control) && 2986 bss_conf->nontransmitted ? 2987 bss_conf->transmitter_bssid : bss_conf->bssid; 2988 if (!ether_addr_equal(target_bssid, bssid)) 2989 goto out; 2990 2991 if (is_mld) { 2992 rx_status->link_valid = true; 2993 rx_status->link_id = rtwvif_link->link_id; 2994 } 2995 2996 if (ieee80211_is_beacon(hdr->frame_control)) { 2997 if (vif->type == NL80211_IFTYPE_STATION && 2998 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) { 2999 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len); 3000 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 3001 } 3002 3003 if (phy_ppdu) { 3004 ewma_rssi_add(&rtwdev->phystat.bcn_rssi, phy_ppdu->rssi_avg); 3005 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 3006 rtwvif_link->bcn_bw_idx = phy_ppdu->bw_idx; 3007 } 3008 3009 pkt_stat->beacon_nr++; 3010 pkt_stat->beacon_rate = desc_info->data_rate; 3011 pkt_stat->beacon_len = skb->len; 3012 3013 rtw89_vif_rx_bcn_stat(rtwdev, skb); 3014 } 3015 3016 if (!ether_addr_equal(bss_conf->addr, hdr->addr1)) 3017 goto out; 3018 3019 if (desc_info->data_rate < RTW89_HW_RATE_NR) 3020 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 3021 3022 rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, false, false); 3023 3024 out: 3025 rcu_read_unlock(); 3026 } 3027 3028 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 3029 struct rtw89_rx_phy_ppdu *phy_ppdu, 3030 struct rtw89_rx_desc_info *desc_info, 3031 struct sk_buff *skb) 3032 { 3033 struct rtw89_vif_rx_stats_iter_data iter_data; 3034 3035 rtw89_traffic_stats_accu(rtwdev, NULL, skb, true, false); 3036 3037 iter_data.rtwdev = rtwdev; 3038 iter_data.phy_ppdu = phy_ppdu; 3039 iter_data.desc_info = desc_info; 3040 iter_data.skb = skb; 3041 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 3042 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 3043 } 3044 3045 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 3046 struct ieee80211_rx_status *status) 3047 { 3048 const struct rtw89_chan_rcd *rcd = 3049 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0); 3050 u16 chan = rcd->prev_primary_channel; 3051 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 3052 3053 if (status->band != NL80211_BAND_2GHZ && 3054 status->encoding == RX_ENC_LEGACY && 3055 status->rate_idx < RTW89_HW_RATE_OFDM6) { 3056 status->freq = ieee80211_channel_to_frequency(chan, band); 3057 status->band = band; 3058 } 3059 } 3060 3061 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 3062 { 3063 if (rx_status->band == NL80211_BAND_2GHZ || 3064 rx_status->encoding != RX_ENC_LEGACY) 3065 return; 3066 3067 /* Some control frames' freq(ACKs in this case) are reported wrong due 3068 * to FW notify timing, set to lowest rate to prevent overflow. 3069 */ 3070 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 3071 rx_status->rate_idx = 0; 3072 return; 3073 } 3074 3075 /* No 4 CCK rates for non-2G */ 3076 rx_status->rate_idx -= 4; 3077 } 3078 3079 static 3080 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev, 3081 struct ieee80211_rx_status *rx_status, 3082 struct rtw89_rx_phy_ppdu *phy_ppdu) 3083 { 3084 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 3085 return; 3086 3087 if (!phy_ppdu) 3088 return; 3089 3090 if (phy_ppdu->ldpc) 3091 rx_status->enc_flags |= RX_ENC_FLAG_LDPC; 3092 if (phy_ppdu->stbc) 3093 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK); 3094 } 3095 3096 static const u8 rx_status_bw_to_radiotap_eht_usig[] = { 3097 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ, 3098 [RATE_INFO_BW_5] = U8_MAX, 3099 [RATE_INFO_BW_10] = U8_MAX, 3100 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ, 3101 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ, 3102 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ, 3103 [RATE_INFO_BW_HE_RU] = U8_MAX, 3104 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1, 3105 [RATE_INFO_BW_EHT_RU] = U8_MAX, 3106 }; 3107 3108 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev, 3109 struct sk_buff *skb, 3110 struct ieee80211_rx_status *rx_status) 3111 { 3112 struct ieee80211_radiotap_eht_usig *usig; 3113 struct ieee80211_radiotap_eht *eht; 3114 struct ieee80211_radiotap_tlv *tlv; 3115 int eht_len = struct_size(eht, user_info, 1); 3116 int usig_len = sizeof(*usig); 3117 int len; 3118 u8 bw; 3119 3120 len = sizeof(*tlv) + ALIGN(eht_len, 4) + 3121 sizeof(*tlv) + ALIGN(usig_len, 4); 3122 3123 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; 3124 skb_reset_mac_header(skb); 3125 3126 /* EHT */ 3127 tlv = skb_push(skb, len); 3128 memset(tlv, 0, len); 3129 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); 3130 tlv->len = cpu_to_le16(eht_len); 3131 3132 eht = (struct ieee80211_radiotap_eht *)tlv->data; 3133 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI); 3134 eht->data[0] = 3135 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI); 3136 3137 eht->user_info[0] = 3138 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 3139 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O | 3140 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN); 3141 eht->user_info[0] |= 3142 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 3143 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); 3144 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC) 3145 eht->user_info[0] |= 3146 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING); 3147 3148 /* U-SIG */ 3149 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4); 3150 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); 3151 tlv->len = cpu_to_le16(usig_len); 3152 3153 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig)) 3154 return; 3155 3156 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw]; 3157 if (bw == U8_MAX) 3158 return; 3159 3160 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data; 3161 usig->common = 3162 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) | 3163 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW); 3164 } 3165 3166 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 3167 struct sk_buff *skb, 3168 struct ieee80211_rx_status *rx_status) 3169 { 3170 static const struct ieee80211_radiotap_he known_he = { 3171 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 3172 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN | 3173 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 3174 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 3175 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 3176 }; 3177 struct ieee80211_radiotap_he *he; 3178 3179 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 3180 return; 3181 3182 if (rx_status->encoding == RX_ENC_HE) { 3183 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 3184 he = skb_push(skb, sizeof(*he)); 3185 *he = known_he; 3186 } else if (rx_status->encoding == RX_ENC_EHT) { 3187 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status); 3188 } 3189 } 3190 3191 static void rtw89_core_validate_rx_signal(struct ieee80211_rx_status *rx_status) 3192 { 3193 if (!rx_status->signal) 3194 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 3195 } 3196 3197 static void rtw89_core_update_rx_freq_from_ie(struct rtw89_dev *rtwdev, 3198 struct sk_buff *skb, 3199 struct ieee80211_rx_status *rx_status) 3200 { 3201 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 3202 size_t hdr_len, ielen; 3203 u8 *variable; 3204 int chan; 3205 3206 if (!rtwdev->chip->rx_freq_from_ie) 3207 return; 3208 3209 if (!rtwdev->scanning) 3210 return; 3211 3212 if (ieee80211_is_beacon(mgmt->frame_control)) { 3213 variable = mgmt->u.beacon.variable; 3214 hdr_len = offsetof(struct ieee80211_mgmt, 3215 u.beacon.variable); 3216 } else if (ieee80211_is_probe_resp(mgmt->frame_control)) { 3217 variable = mgmt->u.probe_resp.variable; 3218 hdr_len = offsetof(struct ieee80211_mgmt, 3219 u.probe_resp.variable); 3220 } else { 3221 return; 3222 } 3223 3224 if (skb->len > hdr_len) 3225 ielen = skb->len - hdr_len; 3226 else 3227 return; 3228 3229 /* The parsing code for both 2GHz and 5GHz bands is the same in this 3230 * function. 3231 */ 3232 chan = cfg80211_get_ies_channel_number(variable, ielen, NL80211_BAND_2GHZ); 3233 if (chan == -1) 3234 return; 3235 3236 rx_status->band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 3237 rx_status->freq = ieee80211_channel_to_frequency(chan, rx_status->band); 3238 } 3239 3240 static void rtw89_core_correct_mcc_chan(struct rtw89_dev *rtwdev, 3241 struct rtw89_rx_desc_info *desc_info, 3242 struct ieee80211_rx_status *rx_status, 3243 struct rtw89_rx_phy_ppdu *phy_ppdu) 3244 { 3245 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 3246 struct rtw89_vif_link *rtwvif_link; 3247 struct rtw89_sta_link *rtwsta_link; 3248 const struct rtw89_chan *chan; 3249 u8 mac_id = desc_info->mac_id; 3250 enum rtw89_entity_mode mode; 3251 enum nl80211_band band; 3252 3253 mode = rtw89_get_entity_mode(rtwdev); 3254 if (likely(mode != RTW89_ENTITY_MODE_MCC)) 3255 return; 3256 3257 if (chip_gen == RTW89_CHIP_BE && phy_ppdu) 3258 mac_id = phy_ppdu->mac_id; 3259 3260 rcu_read_lock(); 3261 3262 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, mac_id); 3263 if (!rtwsta_link) 3264 goto out; 3265 3266 rtwvif_link = rtwsta_link->rtwvif_link; 3267 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 3268 band = rtw89_hw_to_nl80211_band(chan->band_type); 3269 rx_status->freq = ieee80211_channel_to_frequency(chan->primary_channel, band); 3270 3271 out: 3272 rcu_read_unlock(); 3273 } 3274 3275 static void __rtw89_core_tid_rx_stats_reset(struct rtw89_tid_stats *tid_stats) 3276 { 3277 tid_stats->last_pn = -1LL; 3278 tid_stats->last_sn = IEEE80211_SN_MASK; 3279 } 3280 3281 void rtw89_core_tid_rx_stats_ctrl(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3282 struct ieee80211_ampdu_params *params, bool enable) 3283 { 3284 struct rtw89_tid_stats *tid_stats; 3285 u16 tid = params->tid; 3286 3287 tid_stats = &rtwsta->tid_rx_stats[tid]; 3288 3289 if (enable) { 3290 __rtw89_core_tid_rx_stats_reset(tid_stats); 3291 tid_stats->started = true; 3292 } else { 3293 tid_stats->started = false; 3294 } 3295 } 3296 3297 void rtw89_core_tid_rx_stats_reset(struct rtw89_dev *rtwdev) 3298 { 3299 struct rtw89_tid_stats *tid_stats; 3300 struct ieee80211_sta *sta; 3301 struct rtw89_sta *rtwsta; 3302 u16 tid; 3303 3304 for_each_station(sta, rtwdev->hw) { 3305 rtwsta = sta_to_rtwsta(sta); 3306 3307 for (tid = 0; tid < IEEE80211_NUM_TIDS; tid++) { 3308 tid_stats = &rtwsta->tid_rx_stats[tid]; 3309 3310 if (!tid_stats->started) 3311 continue; 3312 3313 __rtw89_core_tid_rx_stats_reset(tid_stats); 3314 } 3315 } 3316 } 3317 3318 static bool rtw89_core_skb_pn_valid(struct rtw89_dev *rtwdev, 3319 struct rtw89_rx_desc_info *desc_info, 3320 struct sk_buff *skb) 3321 { 3322 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 3323 const struct rtw89_chip_info *chip = rtwdev->chip; 3324 struct rtw89_sta_link *rtwsta_link; 3325 struct rtw89_tid_stats *tid_stats; 3326 struct rtw89_sta *rtwsta; 3327 u8 tid, *ccmp_hdr_ptr; 3328 s64 pn, last_pn; 3329 u16 mpdu_sn; 3330 int hdrlen; 3331 3332 if (chip->chip_gen != RTW89_CHIP_AX) 3333 return true; 3334 3335 if (!ieee80211_is_data_qos(hdr->frame_control)) 3336 return true; 3337 3338 if (!desc_info->hw_dec || !desc_info->addr1_match) 3339 return true; 3340 3341 guard(rcu)(); 3342 3343 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, desc_info->mac_id); 3344 if (!rtwsta_link) 3345 return true; 3346 3347 rtwsta = rtwsta_link->rtwsta; 3348 tid = ieee80211_get_tid(hdr); 3349 tid_stats = &rtwsta->tid_rx_stats[tid]; 3350 3351 if (!tid_stats->started) 3352 return true; 3353 3354 switch (desc_info->sec_type) { 3355 case RTW89_SEC_KEY_TYPE_CCMP128: 3356 case RTW89_SEC_KEY_TYPE_CCMP256: 3357 case RTW89_SEC_KEY_TYPE_GCMP128: 3358 case RTW89_SEC_KEY_TYPE_GCMP256: 3359 mpdu_sn = ieee80211_get_sn(hdr); 3360 hdrlen = ieee80211_hdrlen(hdr->frame_control); 3361 ccmp_hdr_ptr = skb->data + hdrlen; 3362 ccmp_hdr2pn(&pn, ccmp_hdr_ptr); 3363 last_pn = tid_stats->last_pn; 3364 3365 if (pn > last_pn) { 3366 if (ieee80211_sn_less(mpdu_sn, tid_stats->last_sn)) { 3367 dev_kfree_skb_any(skb); 3368 3369 return false; 3370 } 3371 3372 tid_stats->last_sn = mpdu_sn; 3373 tid_stats->last_pn = pn; 3374 } 3375 break; 3376 default: 3377 break; 3378 } 3379 3380 return true; 3381 } 3382 3383 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 3384 struct rtw89_rx_phy_ppdu *phy_ppdu, 3385 struct rtw89_rx_desc_info *desc_info, 3386 struct sk_buff *skb_ppdu, 3387 struct ieee80211_rx_status *rx_status) 3388 { 3389 struct napi_struct *napi = &rtwdev->napi; 3390 3391 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 3392 if (unlikely(!napi_is_scheduled(napi))) 3393 napi = NULL; 3394 3395 rtw89_core_hw_to_sband_rate(rx_status); 3396 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 3397 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu); 3398 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 3399 rtw89_core_validate_rx_signal(rx_status); 3400 rtw89_core_update_rx_freq_from_ie(rtwdev, skb_ppdu, rx_status); 3401 rtw89_core_correct_mcc_chan(rtwdev, desc_info, rx_status, phy_ppdu); 3402 3403 /* In low power mode, it does RX in thread context. */ 3404 local_bh_disable(); 3405 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 3406 local_bh_enable(); 3407 rtwdev->napi_budget_countdown--; 3408 } 3409 3410 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 3411 struct rtw89_rx_phy_ppdu *phy_ppdu, 3412 struct rtw89_rx_desc_info *desc_info, 3413 struct sk_buff *skb) 3414 { 3415 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 3416 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 3417 struct sk_buff *skb_ppdu = NULL, *tmp; 3418 struct ieee80211_rx_status *rx_status; 3419 3420 if (curr > RTW89_MAX_PPDU_CNT) 3421 return; 3422 3423 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 3424 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 3425 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 3426 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 3427 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 3428 rtw89_correct_cck_chan(rtwdev, rx_status); 3429 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 3430 } 3431 } 3432 3433 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 3434 struct rtw89_rx_desc_info *desc_info, 3435 struct sk_buff *skb) 3436 { 3437 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 3438 .len = skb->len, 3439 .to_self = desc_info->addr1_match, 3440 .rate = desc_info->data_rate, 3441 .mac_id = desc_info->mac_id, 3442 .phy_idx = desc_info->bb_sel}; 3443 int ret; 3444 3445 if (desc_info->mac_info_valid) { 3446 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 3447 if (ret) 3448 goto out; 3449 } 3450 3451 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 3452 if (ret) 3453 goto out; 3454 3455 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 3456 3457 out: 3458 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 3459 dev_kfree_skb_any(skb); 3460 } 3461 3462 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 3463 struct rtw89_rx_desc_info *desc_info, 3464 struct sk_buff *skb) 3465 { 3466 switch (desc_info->pkt_type) { 3467 case RTW89_CORE_RX_TYPE_C2H: 3468 rtw89_fw_c2h_irqsafe(rtwdev, skb); 3469 break; 3470 case RTW89_CORE_RX_TYPE_PPDU_STAT: 3471 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 3472 break; 3473 default: 3474 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 3475 desc_info->pkt_type); 3476 dev_kfree_skb_any(skb); 3477 break; 3478 } 3479 } 3480 3481 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 3482 struct rtw89_rx_desc_info *desc_info, 3483 u8 *data, u32 data_offset) 3484 { 3485 const struct rtw89_chip_info *chip = rtwdev->chip; 3486 struct rtw89_rxdesc_short *rxd_s; 3487 struct rtw89_rxdesc_long *rxd_l; 3488 u8 shift_len, drv_info_len; 3489 3490 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 3491 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 3492 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 3493 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 3494 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 3495 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 3496 if (chip->chip_id == RTL8852C) 3497 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 3498 else 3499 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 3500 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 3501 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 3502 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 3503 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 3504 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 3505 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 3506 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 3507 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 3508 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 3509 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 3510 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 3511 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 3512 3513 shift_len = desc_info->shift << 1; /* 2-byte unit */ 3514 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 3515 desc_info->offset = data_offset + shift_len + drv_info_len; 3516 if (desc_info->long_rxdesc) 3517 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 3518 else 3519 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 3520 desc_info->ready = true; 3521 3522 if (!desc_info->long_rxdesc) 3523 return; 3524 3525 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 3526 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 3527 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 3528 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 3529 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 3530 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 3531 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 3532 desc_info->sec_type = le32_get_bits(rxd_l->dword7, AX_RXD_SEC_TYPE_MASK); 3533 } 3534 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 3535 3536 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 3537 struct rtw89_rx_desc_info *desc_info, 3538 u8 *data, u32 data_offset) 3539 { 3540 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt; 3541 struct rtw89_rxdesc_short_v2 *rxd_s; 3542 struct rtw89_rxdesc_long_v2 *rxd_l; 3543 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 3544 3545 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset); 3546 3547 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 3548 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 3549 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 3550 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 3551 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 3552 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 3553 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 3554 desc_info->bb_sel = le32_get_bits(rxd_s->dword0, BE_RXD_BB_SEL); 3555 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 3556 desc_info->mac_info_valid = true; 3557 3558 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 3559 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK); 3560 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 3561 3562 desc_info->sec_type = le32_get_bits(rxd_s->dword3, BE_RXD_SEC_TYPE_MASK); 3563 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 3564 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 3565 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 3566 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 3567 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 3568 3569 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 3570 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 3571 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 3572 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 3573 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 3574 3575 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 3576 3577 shift_len = desc_info->shift << 1; /* 2-byte unit */ 3578 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 3579 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 3580 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 3581 desc_info->offset = data_offset + shift_len + drv_info_len + 3582 phy_rtp_len + hdr_cnv_len; 3583 3584 if (desc_info->long_rxdesc) 3585 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2); 3586 else 3587 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2); 3588 desc_info->ready = true; 3589 3590 if (phy_rtp_len == sizeof(*rxd_rpt)) { 3591 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset + 3592 desc_info->rxd_len); 3593 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI); 3594 } 3595 3596 if (!desc_info->long_rxdesc) 3597 return; 3598 3599 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset); 3600 3601 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 3602 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 3603 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK); 3604 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK); 3605 3606 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 3607 } 3608 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2); 3609 3610 void rtw89_core_query_rxdesc_v3(struct rtw89_dev *rtwdev, 3611 struct rtw89_rx_desc_info *desc_info, 3612 u8 *data, u32 data_offset) 3613 { 3614 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt; 3615 struct rtw89_rxdesc_short_v3 *rxd_s; 3616 struct rtw89_rxdesc_long_v3 *rxd_l; 3617 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 3618 3619 rxd_s = (struct rtw89_rxdesc_short_v3 *)(data + data_offset); 3620 3621 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 3622 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 3623 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 3624 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 3625 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 3626 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 3627 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 3628 desc_info->bb_sel = le32_get_bits(rxd_s->dword0, BE_RXD_BB_SEL); 3629 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 3630 desc_info->mac_info_valid = true; 3631 3632 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 3633 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_V1); 3634 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 3635 3636 desc_info->sec_type = le32_get_bits(rxd_s->dword3, BE_RXD_SEC_TYPE_MASK); 3637 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 3638 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 3639 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 3640 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 3641 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 3642 3643 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 3644 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 3645 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 3646 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 3647 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 3648 3649 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 3650 3651 shift_len = desc_info->shift << 1; /* 2-byte unit */ 3652 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 3653 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 3654 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 3655 desc_info->offset = data_offset + shift_len + drv_info_len + 3656 phy_rtp_len + hdr_cnv_len; 3657 3658 if (desc_info->long_rxdesc) 3659 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v3); 3660 else 3661 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v3); 3662 desc_info->ready = true; 3663 3664 if (phy_rtp_len == sizeof(*rxd_rpt)) { 3665 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset + 3666 desc_info->rxd_len); 3667 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI); 3668 } 3669 3670 if (!desc_info->long_rxdesc) 3671 return; 3672 3673 rxd_l = (struct rtw89_rxdesc_long_v3 *)(data + data_offset); 3674 3675 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 3676 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 3677 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_V1); 3678 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_V1); 3679 3680 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 3681 } 3682 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v3); 3683 3684 struct rtw89_core_iter_rx_status { 3685 struct rtw89_dev *rtwdev; 3686 struct ieee80211_rx_status *rx_status; 3687 struct rtw89_rx_desc_info *desc_info; 3688 u8 mac_id; 3689 }; 3690 3691 static 3692 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 3693 { 3694 struct rtw89_core_iter_rx_status *iter_data = 3695 (struct rtw89_core_iter_rx_status *)data; 3696 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 3697 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 3698 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3699 struct rtw89_sta_link *rtwsta_link; 3700 u8 mac_id = iter_data->mac_id; 3701 3702 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, desc_info->bb_sel); 3703 if (unlikely(!rtwsta_link)) 3704 return; 3705 3706 if (mac_id != rtwsta_link->mac_id) 3707 return; 3708 3709 rtwsta_link->rx_status = *rx_status; 3710 rtwsta_link->rx_hw_rate = desc_info->data_rate; 3711 } 3712 3713 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 3714 struct rtw89_rx_desc_info *desc_info, 3715 struct ieee80211_rx_status *rx_status) 3716 { 3717 struct rtw89_core_iter_rx_status iter_data; 3718 3719 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 3720 return; 3721 3722 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 3723 return; 3724 3725 iter_data.rtwdev = rtwdev; 3726 iter_data.rx_status = rx_status; 3727 iter_data.desc_info = desc_info; 3728 iter_data.mac_id = desc_info->mac_id; 3729 ieee80211_iterate_stations_atomic(rtwdev->hw, 3730 rtw89_core_stats_sta_rx_status_iter, 3731 &iter_data); 3732 } 3733 3734 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 3735 struct sk_buff *skb, 3736 struct rtw89_rx_desc_info *desc_info, 3737 struct ieee80211_rx_status *rx_status) 3738 { 3739 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 3740 const struct cfg80211_chan_def *chandef = 3741 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0); 3742 u16 data_rate; 3743 u8 data_rate_mode; 3744 bool eht = false; 3745 u8 gi; 3746 3747 /* currently using single PHY */ 3748 rx_status->freq = chandef->chan->center_freq; 3749 rx_status->band = chandef->chan->band; 3750 3751 if (ieee80211_is_beacon(hdr->frame_control) || 3752 ieee80211_is_probe_resp(hdr->frame_control)) 3753 rx_status->boottime_ns = ktime_get_boottime_ns(); 3754 3755 if (rtwdev->scanning && 3756 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 3757 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 3758 u8 chan = cur->primary_channel; 3759 u8 band = cur->band_type; 3760 enum nl80211_band nl_band; 3761 3762 nl_band = rtw89_hw_to_nl80211_band(band); 3763 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 3764 rx_status->band = nl_band; 3765 } 3766 3767 if (desc_info->icv_err || desc_info->crc32_err) 3768 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 3769 3770 if (desc_info->hw_dec && 3771 !(desc_info->sw_dec || desc_info->icv_err)) 3772 rx_status->flag |= RX_FLAG_DECRYPTED; 3773 3774 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 3775 3776 data_rate = desc_info->data_rate; 3777 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 3778 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 3779 rx_status->encoding = RX_ENC_LEGACY; 3780 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 3781 /* convert rate_idx after we get the correct band */ 3782 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 3783 rx_status->encoding = RX_ENC_HT; 3784 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 3785 if (desc_info->gi_ltf) 3786 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 3787 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 3788 rx_status->encoding = RX_ENC_VHT; 3789 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 3790 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 3791 if (desc_info->gi_ltf) 3792 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 3793 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 3794 rx_status->encoding = RX_ENC_HE; 3795 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 3796 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 3797 } else if (data_rate_mode == DATA_RATE_MODE_EHT) { 3798 rx_status->encoding = RX_ENC_EHT; 3799 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 3800 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 3801 eht = true; 3802 } else { 3803 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 3804 } 3805 3806 /* he_gi is used to match ppdu, so we always fill it. */ 3807 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht); 3808 if (eht) 3809 rx_status->eht.gi = gi; 3810 else 3811 rx_status->he_gi = gi; 3812 rx_status->flag |= RX_FLAG_MACTIME_START; 3813 rx_status->mactime = desc_info->free_run_cnt; 3814 3815 rtw89_chip_phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 3816 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 3817 } 3818 3819 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 3820 { 3821 const struct rtw89_chip_info *chip = rtwdev->chip; 3822 3823 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE) 3824 return RTW89_PS_MODE_NONE; 3825 3826 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 3827 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 3828 return RTW89_PS_MODE_NONE; 3829 3830 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 3831 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 3832 return RTW89_PS_MODE_PWR_GATED; 3833 3834 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 3835 return RTW89_PS_MODE_CLK_GATED; 3836 3837 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 3838 return RTW89_PS_MODE_RFOFF; 3839 3840 return RTW89_PS_MODE_NONE; 3841 } 3842 3843 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 3844 struct rtw89_rx_desc_info *desc_info) 3845 { 3846 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 3847 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 3848 struct ieee80211_rx_status *rx_status; 3849 struct sk_buff *skb_ppdu, *tmp; 3850 3851 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 3852 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 3853 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 3854 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 3855 } 3856 } 3857 3858 static 3859 void rtw89_core_rx_pkt_hdl(struct rtw89_dev *rtwdev, const struct sk_buff *skb, 3860 const struct rtw89_rx_desc_info *desc) 3861 { 3862 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 3863 struct rtw89_sta_link *rtwsta_link; 3864 struct ieee80211_sta *sta; 3865 struct rtw89_sta *rtwsta; 3866 u8 macid = desc->mac_id; 3867 3868 if (!refcount_read(&rtwdev->refcount_ap_info)) 3869 return; 3870 3871 rcu_read_lock(); 3872 3873 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 3874 if (!rtwsta_link) 3875 goto out; 3876 3877 rtwsta = rtwsta_link->rtwsta; 3878 if (!test_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags)) 3879 goto out; 3880 3881 sta = rtwsta_to_sta(rtwsta); 3882 if (ieee80211_is_pspoll(hdr->frame_control)) 3883 ieee80211_sta_pspoll(sta); 3884 else if (ieee80211_has_pm(hdr->frame_control) && 3885 (ieee80211_is_data_qos(hdr->frame_control) || 3886 ieee80211_is_qos_nullfunc(hdr->frame_control))) 3887 ieee80211_sta_uapsd_trigger(sta, ieee80211_get_tid(hdr)); 3888 3889 out: 3890 rcu_read_unlock(); 3891 } 3892 3893 void rtw89_core_rx(struct rtw89_dev *rtwdev, 3894 struct rtw89_rx_desc_info *desc_info, 3895 struct sk_buff *skb) 3896 { 3897 struct ieee80211_rx_status *rx_status; 3898 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 3899 u8 ppdu_cnt = desc_info->ppdu_cnt; 3900 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 3901 3902 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 3903 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 3904 return; 3905 } 3906 3907 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 3908 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 3909 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 3910 } 3911 3912 rx_status = IEEE80211_SKB_RXCB(skb); 3913 memset(rx_status, 0, sizeof(*rx_status)); 3914 rtw89_core_update_rx_status(rtwdev, skb, desc_info, rx_status); 3915 rtw89_core_rx_pkt_hdl(rtwdev, skb, desc_info); 3916 3917 if (!rtw89_core_skb_pn_valid(rtwdev, desc_info, skb)) 3918 return; 3919 3920 if (desc_info->long_rxdesc && 3921 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 3922 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 3923 else 3924 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 3925 } 3926 EXPORT_SYMBOL(rtw89_core_rx); 3927 3928 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 3929 { 3930 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 3931 return; 3932 3933 napi_enable(&rtwdev->napi); 3934 } 3935 EXPORT_SYMBOL(rtw89_core_napi_start); 3936 3937 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 3938 { 3939 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 3940 return; 3941 3942 napi_synchronize(&rtwdev->napi); 3943 napi_disable(&rtwdev->napi); 3944 } 3945 EXPORT_SYMBOL(rtw89_core_napi_stop); 3946 3947 int rtw89_core_napi_init(struct rtw89_dev *rtwdev) 3948 { 3949 rtwdev->netdev = alloc_netdev_dummy(0); 3950 if (!rtwdev->netdev) 3951 return -ENOMEM; 3952 3953 netif_napi_add(rtwdev->netdev, &rtwdev->napi, 3954 rtwdev->hci.ops->napi_poll); 3955 return 0; 3956 } 3957 EXPORT_SYMBOL(rtw89_core_napi_init); 3958 3959 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 3960 { 3961 rtw89_core_napi_stop(rtwdev); 3962 netif_napi_del(&rtwdev->napi); 3963 free_netdev(rtwdev->netdev); 3964 } 3965 EXPORT_SYMBOL(rtw89_core_napi_deinit); 3966 3967 static void rtw89_core_ba_work(struct work_struct *work) 3968 { 3969 struct rtw89_dev *rtwdev = 3970 container_of(work, struct rtw89_dev, ba_work); 3971 struct rtw89_txq *rtwtxq, *tmp; 3972 int ret; 3973 3974 spin_lock_bh(&rtwdev->ba_lock); 3975 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 3976 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3977 struct ieee80211_sta *sta = txq->sta; 3978 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 3979 u8 tid = txq->tid; 3980 3981 if (!sta) { 3982 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 3983 goto skip_ba_work; 3984 } 3985 3986 if (rtwsta->disassoc) { 3987 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3988 "cannot start BA with disassoc sta\n"); 3989 goto skip_ba_work; 3990 } 3991 3992 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 3993 if (ret) { 3994 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3995 "failed to setup BA session for %pM:%2d: %d\n", 3996 sta->addr, tid, ret); 3997 if (ret == -EINVAL) 3998 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 3999 } 4000 skip_ba_work: 4001 list_del_init(&rtwtxq->list); 4002 } 4003 spin_unlock_bh(&rtwdev->ba_lock); 4004 } 4005 4006 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 4007 struct ieee80211_sta *sta) 4008 { 4009 struct rtw89_txq *rtwtxq, *tmp; 4010 4011 spin_lock_bh(&rtwdev->ba_lock); 4012 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 4013 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 4014 4015 if (sta == txq->sta) 4016 list_del_init(&rtwtxq->list); 4017 } 4018 spin_unlock_bh(&rtwdev->ba_lock); 4019 } 4020 4021 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 4022 struct ieee80211_sta *sta) 4023 { 4024 struct rtw89_txq *rtwtxq, *tmp; 4025 4026 spin_lock_bh(&rtwdev->ba_lock); 4027 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 4028 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 4029 4030 if (sta == txq->sta) { 4031 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 4032 list_del_init(&rtwtxq->list); 4033 } 4034 } 4035 spin_unlock_bh(&rtwdev->ba_lock); 4036 } 4037 4038 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 4039 struct ieee80211_sta *sta) 4040 { 4041 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 4042 struct sk_buff *skb; 4043 4044 while ((skb = skb_dequeue(&rtwsta->roc_queue))) 4045 dev_kfree_skb_any(skb); 4046 } 4047 4048 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 4049 struct rtw89_txq *rtwtxq) 4050 { 4051 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 4052 struct ieee80211_sta *sta = txq->sta; 4053 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 4054 4055 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 4056 return; 4057 4058 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 4059 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 4060 return; 4061 4062 spin_lock_bh(&rtwdev->ba_lock); 4063 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 4064 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 4065 spin_unlock_bh(&rtwdev->ba_lock); 4066 4067 ieee80211_stop_tx_ba_session(sta, txq->tid); 4068 cancel_delayed_work(&rtwdev->forbid_ba_work); 4069 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 4070 RTW89_FORBID_BA_TIMER); 4071 } 4072 4073 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 4074 struct rtw89_txq *rtwtxq, 4075 struct sk_buff *skb) 4076 { 4077 struct ieee80211_hw *hw = rtwdev->hw; 4078 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 4079 struct ieee80211_sta *sta = txq->sta; 4080 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 4081 4082 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 4083 return; 4084 4085 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 4086 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 4087 return; 4088 } 4089 4090 if (unlikely(!sta)) 4091 return; 4092 4093 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 4094 return; 4095 4096 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 4097 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 4098 return; 4099 } 4100 4101 spin_lock_bh(&rtwdev->ba_lock); 4102 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 4103 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 4104 ieee80211_queue_work(hw, &rtwdev->ba_work); 4105 } 4106 spin_unlock_bh(&rtwdev->ba_lock); 4107 } 4108 4109 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 4110 struct rtw89_txq *rtwtxq, 4111 unsigned long frame_cnt, 4112 unsigned long byte_cnt) 4113 { 4114 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 4115 struct ieee80211_vif *vif = txq->vif; 4116 struct ieee80211_sta *sta = txq->sta; 4117 struct sk_buff *skb; 4118 unsigned long i; 4119 int ret; 4120 4121 rcu_read_lock(); 4122 for (i = 0; i < frame_cnt; i++) { 4123 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 4124 if (!skb) { 4125 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 4126 goto out; 4127 } 4128 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 4129 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 4130 if (ret) { 4131 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 4132 ieee80211_free_txskb(rtwdev->hw, skb); 4133 break; 4134 } 4135 } 4136 out: 4137 rcu_read_unlock(); 4138 } 4139 4140 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 4141 { 4142 u8 qsel, ch_dma; 4143 4144 qsel = rtw89_core_get_qsel(rtwdev, tid); 4145 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 4146 4147 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 4148 } 4149 4150 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 4151 struct ieee80211_txq *txq, 4152 unsigned long *frame_cnt, 4153 bool *sched_txq, bool *reinvoke) 4154 { 4155 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 4156 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(txq->sta); 4157 struct rtw89_sta_link *rtwsta_link; 4158 4159 if (!rtwsta) 4160 return false; 4161 4162 rtwsta_link = rtw89_get_designated_link(rtwsta); 4163 if (unlikely(!rtwsta_link)) { 4164 rtw89_err(rtwdev, "agg wait: find no designated link\n"); 4165 return false; 4166 } 4167 4168 if (rtwsta_link->max_agg_wait <= 0) 4169 return false; 4170 4171 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 4172 return false; 4173 4174 if (*frame_cnt > 1) { 4175 *frame_cnt -= 1; 4176 *sched_txq = true; 4177 *reinvoke = true; 4178 rtwtxq->wait_cnt = 1; 4179 return false; 4180 } 4181 4182 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta_link->max_agg_wait) { 4183 *reinvoke = true; 4184 rtwtxq->wait_cnt++; 4185 return true; 4186 } 4187 4188 rtwtxq->wait_cnt = 0; 4189 return false; 4190 } 4191 4192 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 4193 { 4194 struct ieee80211_hw *hw = rtwdev->hw; 4195 struct ieee80211_txq *txq; 4196 struct rtw89_vif *rtwvif; 4197 struct rtw89_txq *rtwtxq; 4198 unsigned long frame_cnt; 4199 unsigned long byte_cnt; 4200 u32 tx_resource; 4201 bool sched_txq; 4202 4203 ieee80211_txq_schedule_start(hw, ac); 4204 while ((txq = ieee80211_next_txq(hw, ac))) { 4205 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 4206 rtwvif = vif_to_rtwvif(txq->vif); 4207 4208 if (rtwvif->offchan) { 4209 ieee80211_return_txq(hw, txq, true); 4210 continue; 4211 } 4212 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 4213 sched_txq = false; 4214 4215 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 4216 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 4217 ieee80211_return_txq(hw, txq, true); 4218 continue; 4219 } 4220 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 4221 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 4222 ieee80211_return_txq(hw, txq, sched_txq); 4223 if (frame_cnt != 0) 4224 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 4225 4226 /* bound of tx_resource could get stuck due to burst traffic */ 4227 if (frame_cnt == tx_resource) 4228 *reinvoke = true; 4229 } 4230 ieee80211_txq_schedule_end(hw, ac); 4231 } 4232 4233 static void rtw89_ips_work(struct wiphy *wiphy, struct wiphy_work *work) 4234 { 4235 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4236 ips_work); 4237 4238 lockdep_assert_wiphy(wiphy); 4239 4240 rtw89_enter_ips_by_hwflags(rtwdev); 4241 } 4242 4243 static void rtw89_core_txq_work(struct work_struct *w) 4244 { 4245 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 4246 bool reinvoke = false; 4247 u8 ac; 4248 4249 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 4250 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 4251 4252 if (reinvoke) { 4253 /* reinvoke to process the last frame */ 4254 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 4255 } 4256 } 4257 4258 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 4259 { 4260 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 4261 txq_reinvoke_work.work); 4262 4263 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 4264 } 4265 4266 static void rtw89_forbid_ba_work(struct work_struct *w) 4267 { 4268 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 4269 forbid_ba_work.work); 4270 struct rtw89_txq *rtwtxq, *tmp; 4271 4272 spin_lock_bh(&rtwdev->ba_lock); 4273 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 4274 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 4275 list_del_init(&rtwtxq->list); 4276 } 4277 spin_unlock_bh(&rtwdev->ba_lock); 4278 } 4279 4280 static void rtw89_core_sta_pending_tx_iter(void *data, 4281 struct ieee80211_sta *sta) 4282 { 4283 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 4284 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4285 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 4286 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4287 struct rtw89_vif_link *target = data; 4288 struct rtw89_vif_link *rtwvif_link; 4289 unsigned int link_id; 4290 struct sk_buff *skb; 4291 int qsel, ret; 4292 4293 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4294 if (rtwvif_link->chanctx_idx == target->chanctx_idx) 4295 goto bottom; 4296 4297 return; 4298 4299 bottom: 4300 if (skb_queue_len(&rtwsta->roc_queue) == 0) 4301 return; 4302 4303 while ((skb = skb_dequeue(&rtwsta->roc_queue))) { 4304 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 4305 if (ret) { 4306 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 4307 dev_kfree_skb_any(skb); 4308 } else { 4309 rtw89_core_tx_kick_off(rtwdev, qsel); 4310 } 4311 } 4312 } 4313 4314 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 4315 struct rtw89_vif_link *rtwvif_link) 4316 { 4317 ieee80211_iterate_stations_atomic(rtwdev->hw, 4318 rtw89_core_sta_pending_tx_iter, 4319 rtwvif_link); 4320 } 4321 4322 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4323 bool qos, bool ps, int timeout) 4324 { 4325 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4326 int link_id = ieee80211_vif_is_mld(vif) ? rtwvif_link->link_id : -1; 4327 struct rtw89_sta_link *rtwsta_link; 4328 struct rtw89_tx_wait_info *wait; 4329 struct ieee80211_sta *sta; 4330 struct ieee80211_hdr *hdr; 4331 struct rtw89_sta *rtwsta; 4332 struct sk_buff *skb; 4333 int ret, qsel; 4334 4335 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 4336 return 0; 4337 4338 wait = kzalloc_obj(*wait); 4339 if (!wait) 4340 return -ENOMEM; 4341 4342 init_completion(&wait->completion); 4343 4344 rcu_read_lock(); 4345 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr); 4346 if (!sta) { 4347 ret = -EINVAL; 4348 goto out; 4349 } 4350 rtwsta = sta_to_rtwsta(sta); 4351 4352 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, link_id, qos); 4353 if (!skb) { 4354 ret = -ENOMEM; 4355 goto out; 4356 } 4357 4358 wait->skb = skb; 4359 4360 hdr = (struct ieee80211_hdr *)skb->data; 4361 if (ps) 4362 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 4363 4364 rtwsta_link = rtwsta->links[rtwvif_link->link_id]; 4365 if (unlikely(!rtwsta_link)) { 4366 ret = -ENOLINK; 4367 dev_kfree_skb_any(skb); 4368 goto out; 4369 } 4370 4371 ret = rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, &qsel, wait); 4372 if (ret) { 4373 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 4374 dev_kfree_skb_any(skb); 4375 goto out; 4376 } 4377 4378 rcu_read_unlock(); 4379 4380 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, wait, qsel, 4381 timeout); 4382 out: 4383 rcu_read_unlock(); 4384 kfree(wait); 4385 4386 return ret; 4387 } 4388 4389 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4390 { 4391 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4392 struct rtw89_chanctx_pause_parm pause_parm = { 4393 .rsn = RTW89_CHANCTX_PAUSE_REASON_ROC, 4394 }; 4395 struct ieee80211_hw *hw = rtwdev->hw; 4396 struct rtw89_roc *roc = &rtwvif->roc; 4397 struct rtw89_vif_link *rtwvif_link; 4398 struct cfg80211_chan_def roc_chan; 4399 struct rtw89_vif *tmp_vif; 4400 u32 reg; 4401 int ret; 4402 4403 lockdep_assert_wiphy(hw->wiphy); 4404 4405 rtw89_leave_ips_by_hwflags(rtwdev); 4406 rtw89_leave_lps(rtwdev); 4407 4408 rtwvif_link = rtw89_get_designated_link(rtwvif); 4409 if (unlikely(!rtwvif_link)) { 4410 rtw89_err(rtwdev, "roc start: find no designated link\n"); 4411 return; 4412 } 4413 4414 roc->link_id = rtwvif_link->link_id; 4415 4416 pause_parm.trigger = rtwvif_link; 4417 rtw89_chanctx_pause(rtwdev, &pause_parm); 4418 4419 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, true, 4420 RTW89_ROC_TX_TIMEOUT); 4421 if (ret) 4422 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 4423 "roc send null-1 failed: %d\n", ret); 4424 4425 rtw89_for_each_rtwvif(rtwdev, tmp_vif) { 4426 struct rtw89_vif_link *tmp_link; 4427 unsigned int link_id; 4428 4429 rtw89_vif_for_each_link(tmp_vif, tmp_link, link_id) { 4430 if (tmp_link->chanctx_idx == rtwvif_link->chanctx_idx) { 4431 tmp_vif->offchan = true; 4432 break; 4433 } 4434 } 4435 } 4436 4437 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 4438 rtw89_config_roc_chandef(rtwdev, rtwvif_link, &roc_chan); 4439 rtw89_set_channel(rtwdev); 4440 4441 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx); 4442 rtw89_write32_clr(rtwdev, reg, B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 4443 4444 ieee80211_ready_on_channel(hw); 4445 wiphy_delayed_work_cancel(hw->wiphy, &rtwvif->roc.roc_work); 4446 wiphy_delayed_work_queue(hw->wiphy, &rtwvif->roc.roc_work, 4447 msecs_to_jiffies(rtwvif->roc.duration)); 4448 } 4449 4450 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4451 { 4452 struct ieee80211_hw *hw = rtwdev->hw; 4453 struct rtw89_roc *roc = &rtwvif->roc; 4454 struct rtw89_vif_link *rtwvif_link; 4455 struct rtw89_vif *tmp_vif; 4456 int ret; 4457 4458 lockdep_assert_wiphy(hw->wiphy); 4459 4460 ieee80211_remain_on_channel_expired(hw); 4461 4462 rtw89_leave_ips_by_hwflags(rtwdev); 4463 rtw89_leave_lps(rtwdev); 4464 4465 rtwvif_link = rtwvif->links[roc->link_id]; 4466 if (unlikely(!rtwvif_link)) { 4467 rtw89_err(rtwdev, "roc end: find no link (link id %u)\n", 4468 roc->link_id); 4469 return; 4470 } 4471 4472 rtw89_mac_set_rx_fltr(rtwdev, rtwvif_link->mac_idx, rtwdev->hal.rx_fltr); 4473 4474 roc->state = RTW89_ROC_IDLE; 4475 rtw89_config_roc_chandef(rtwdev, rtwvif_link, NULL); 4476 rtw89_chanctx_proceed(rtwdev, NULL); 4477 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, false, 4478 RTW89_ROC_TX_TIMEOUT); 4479 if (ret) 4480 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 4481 "roc send null-0 failed: %d\n", ret); 4482 4483 rtw89_for_each_rtwvif(rtwdev, tmp_vif) 4484 tmp_vif->offchan = false; 4485 4486 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif_link); 4487 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 4488 4489 if (hw->conf.flags & IEEE80211_CONF_IDLE) 4490 wiphy_delayed_work_queue(hw->wiphy, &roc->roc_work, 4491 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 4492 } 4493 4494 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work) 4495 { 4496 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 4497 roc.roc_work.work); 4498 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 4499 struct rtw89_roc *roc = &rtwvif->roc; 4500 4501 lockdep_assert_wiphy(wiphy); 4502 4503 switch (roc->state) { 4504 case RTW89_ROC_IDLE: 4505 rtw89_enter_ips_by_hwflags(rtwdev); 4506 break; 4507 case RTW89_ROC_MGMT: 4508 case RTW89_ROC_NORMAL: 4509 rtw89_roc_end(rtwdev, rtwvif); 4510 break; 4511 default: 4512 break; 4513 } 4514 } 4515 4516 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 4517 u32 throughput, u64 cnt, 4518 enum rtw89_tfc_interval interval) 4519 { 4520 u64 cnt_level; 4521 4522 switch (interval) { 4523 default: 4524 case RTW89_TFC_INTERVAL_100MS: 4525 cnt_level = 5; 4526 break; 4527 case RTW89_TFC_INTERVAL_2SEC: 4528 cnt_level = 100; 4529 break; 4530 } 4531 4532 if (cnt < cnt_level) 4533 return RTW89_TFC_IDLE; 4534 if (throughput > 50) 4535 return RTW89_TFC_HIGH; 4536 if (throughput > 10) 4537 return RTW89_TFC_MID; 4538 if (throughput > 2) 4539 return RTW89_TFC_LOW; 4540 return RTW89_TFC_ULTRA_LOW; 4541 } 4542 4543 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 4544 struct rtw89_traffic_stats *stats, 4545 enum rtw89_tfc_interval interval) 4546 { 4547 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 4548 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 4549 4550 stats->tx_throughput_raw = rtw89_bytes_to_mbps(stats->tx_unicast, interval); 4551 stats->rx_throughput_raw = rtw89_bytes_to_mbps(stats->rx_unicast, interval); 4552 4553 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 4554 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 4555 4556 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 4557 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 4558 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 4559 stats->tx_cnt, interval); 4560 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 4561 stats->rx_cnt, interval); 4562 stats->tx_avg_len = stats->tx_cnt ? 4563 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 4564 stats->rx_avg_len = stats->rx_cnt ? 4565 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 4566 4567 stats->tx_unicast = 0; 4568 stats->rx_unicast = 0; 4569 stats->tx_cnt = 0; 4570 stats->rx_cnt = 0; 4571 stats->rx_tf_periodic = stats->rx_tf_acc; 4572 stats->rx_tf_acc = 0; 4573 4574 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 4575 return true; 4576 4577 return false; 4578 } 4579 4580 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 4581 { 4582 struct rtw89_vif_link *rtwvif_link; 4583 struct rtw89_vif *rtwvif; 4584 unsigned int link_id; 4585 bool tfc_changed; 4586 4587 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats, 4588 RTW89_TFC_INTERVAL_2SEC); 4589 4590 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4591 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats, 4592 RTW89_TFC_INTERVAL_2SEC); 4593 4594 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4595 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif_link); 4596 } 4597 4598 return tfc_changed; 4599 } 4600 4601 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 4602 { 4603 struct ieee80211_vif *vif; 4604 struct rtw89_vif *rtwvif; 4605 4606 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4607 if (rtwvif->tdls_peer) 4608 continue; 4609 if (rtwvif->offchan) 4610 continue; 4611 4612 if (rtwvif->stats_ps.tx_tfc_lv >= RTW89_TFC_MID || 4613 rtwvif->stats_ps.rx_tfc_lv >= RTW89_TFC_MID) 4614 continue; 4615 4616 vif = rtwvif_to_vif(rtwvif); 4617 4618 if (!(vif->type == NL80211_IFTYPE_STATION || 4619 vif->type == NL80211_IFTYPE_P2P_CLIENT)) 4620 continue; 4621 4622 if (!rtw89_core_bcn_track_can_lps(rtwdev)) 4623 continue; 4624 4625 rtw89_enter_lps(rtwdev, rtwvif, true); 4626 } 4627 } 4628 4629 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev) 4630 { 4631 enum rtw89_entity_mode mode; 4632 4633 mode = rtw89_get_entity_mode(rtwdev); 4634 if (mode == RTW89_ENTITY_MODE_MCC) 4635 return; 4636 4637 rtw89_chip_rfk_track(rtwdev); 4638 } 4639 4640 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 4641 struct rtw89_vif_link *rtwvif_link, 4642 struct ieee80211_bss_conf *bss_conf) 4643 { 4644 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev); 4645 4646 if (mode == RTW89_ENTITY_MODE_MCC) 4647 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE); 4648 else 4649 rtw89_process_p2p_ps(rtwdev, rtwvif_link, bss_conf); 4650 } 4651 4652 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 4653 struct rtw89_traffic_stats *stats) 4654 { 4655 stats->tx_unicast = 0; 4656 stats->rx_unicast = 0; 4657 stats->tx_cnt = 0; 4658 stats->rx_cnt = 0; 4659 ewma_tp_init(&stats->tx_ewma_tp); 4660 ewma_tp_init(&stats->rx_ewma_tp); 4661 } 4662 4663 #define RTW89_MLSR_GOTO_2GHZ_THRESHOLD -53 4664 #define RTW89_MLSR_EXIT_2GHZ_THRESHOLD -38 4665 static void rtw89_core_mlsr_link_decision(struct rtw89_dev *rtwdev, 4666 struct rtw89_vif *rtwvif) 4667 { 4668 unsigned int sel_link_id = IEEE80211_MLD_MAX_NUM_LINKS; 4669 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4670 struct rtw89_vif_link *rtwvif_link; 4671 const struct rtw89_chan *chan; 4672 unsigned long usable_links; 4673 unsigned int link_id; 4674 u8 decided_bands; 4675 u8 rssi; 4676 4677 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 4678 if (unlikely(!rssi)) 4679 return; 4680 4681 if (RTW89_RSSI_RAW_TO_DBM(rssi) >= RTW89_MLSR_EXIT_2GHZ_THRESHOLD) 4682 decided_bands = BIT(RTW89_BAND_5G) | BIT(RTW89_BAND_6G); 4683 else if (RTW89_RSSI_RAW_TO_DBM(rssi) <= RTW89_MLSR_GOTO_2GHZ_THRESHOLD) 4684 decided_bands = BIT(RTW89_BAND_2G); 4685 else 4686 return; 4687 4688 usable_links = ieee80211_vif_usable_links(vif); 4689 4690 rtwvif_link = rtw89_get_designated_link(rtwvif); 4691 if (unlikely(!rtwvif_link)) 4692 goto select; 4693 4694 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 4695 if (decided_bands & BIT(chan->band_type)) 4696 return; 4697 4698 usable_links &= ~BIT(rtwvif_link->link_id); 4699 4700 select: 4701 rcu_read_lock(); 4702 4703 for_each_set_bit(link_id, &usable_links, IEEE80211_MLD_MAX_NUM_LINKS) { 4704 struct ieee80211_bss_conf *link_conf; 4705 struct ieee80211_channel *channel; 4706 enum rtw89_band band; 4707 4708 link_conf = rcu_dereference(vif->link_conf[link_id]); 4709 if (unlikely(!link_conf)) 4710 continue; 4711 4712 channel = link_conf->chanreq.oper.chan; 4713 if (unlikely(!channel)) 4714 continue; 4715 4716 band = rtw89_nl80211_to_hw_band(channel->band); 4717 if (decided_bands & BIT(band)) { 4718 sel_link_id = link_id; 4719 break; 4720 } 4721 } 4722 4723 rcu_read_unlock(); 4724 4725 if (sel_link_id == IEEE80211_MLD_MAX_NUM_LINKS) 4726 return; 4727 4728 rtw89_core_mlsr_switch(rtwdev, rtwvif, sel_link_id); 4729 } 4730 4731 static void rtw89_core_mlo_track(struct rtw89_dev *rtwdev) 4732 { 4733 struct rtw89_hal *hal = &rtwdev->hal; 4734 struct ieee80211_vif *vif; 4735 struct rtw89_vif *rtwvif; 4736 4737 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_MLO)) 4738 return; 4739 4740 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4741 vif = rtwvif_to_vif(rtwvif); 4742 if (!vif->cfg.assoc || !ieee80211_vif_is_mld(vif)) 4743 continue; 4744 4745 switch (rtwvif->mlo_mode) { 4746 case RTW89_MLO_MODE_MLSR: 4747 rtw89_core_mlsr_link_decision(rtwdev, rtwvif); 4748 break; 4749 default: 4750 break; 4751 } 4752 } 4753 } 4754 4755 static void rtw89_track_ps_work(struct wiphy *wiphy, struct wiphy_work *work) 4756 { 4757 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4758 track_ps_work.work); 4759 struct rtw89_vif *rtwvif; 4760 4761 lockdep_assert_wiphy(wiphy); 4762 4763 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WORK, rtwdev->flags)) 4764 return; 4765 4766 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 4767 return; 4768 4769 wiphy_delayed_work_queue(wiphy, &rtwdev->track_ps_work, 4770 RTW89_TRACK_PS_WORK_PERIOD); 4771 4772 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4773 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats_ps, 4774 RTW89_TFC_INTERVAL_100MS); 4775 4776 if (rtwdev->scanning) 4777 return; 4778 4779 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 4780 rtw89_enter_lps_track(rtwdev); 4781 } 4782 4783 static void rtw89_track_work(struct wiphy *wiphy, struct wiphy_work *work) 4784 { 4785 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4786 track_work.work); 4787 bool tfc_changed; 4788 4789 lockdep_assert_wiphy(wiphy); 4790 4791 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WORK, rtwdev->flags)) 4792 return; 4793 4794 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 4795 return; 4796 4797 wiphy_delayed_work_queue(wiphy, &rtwdev->track_work, 4798 RTW89_TRACK_WORK_PERIOD); 4799 4800 tfc_changed = rtw89_traffic_stats_track(rtwdev); 4801 if (rtwdev->scanning) 4802 return; 4803 4804 rtw89_leave_lps(rtwdev); 4805 4806 if (tfc_changed) { 4807 rtw89_hci_recalc_int_mit(rtwdev); 4808 rtw89_btc_ntfy_wl_sta(rtwdev); 4809 } 4810 rtw89_mac_bf_monitor_track(rtwdev); 4811 rtw89_core_bcn_track(rtwdev); 4812 rtw89_phy_stat_track(rtwdev); 4813 rtw89_phy_env_monitor_track(rtwdev); 4814 rtw89_phy_dig(rtwdev); 4815 rtw89_core_rfk_track(rtwdev); 4816 rtw89_phy_ra_update(rtwdev); 4817 rtw89_phy_cfo_track(rtwdev); 4818 rtw89_phy_tx_path_div_track(rtwdev); 4819 rtw89_phy_antdiv_track(rtwdev); 4820 rtw89_phy_ul_tb_ctrl_track(rtwdev); 4821 rtw89_phy_edcca_track(rtwdev); 4822 rtw89_sar_track(rtwdev); 4823 rtw89_chanctx_track(rtwdev); 4824 rtw89_core_rfkill_poll(rtwdev, false); 4825 rtw89_core_mlo_track(rtwdev); 4826 4827 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 4828 rtw89_enter_lps_track(rtwdev); 4829 } 4830 4831 void rtw89_core_dm_disable_cfg(struct rtw89_dev *rtwdev, u32 new) 4832 { 4833 struct rtw89_hal *hal = &rtwdev->hal; 4834 u32 old = hal->disabled_dm_bitmap; 4835 4836 if (new == old) 4837 return; 4838 4839 hal->disabled_dm_bitmap = new; 4840 4841 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Disable DM: 0x%x -> 0x%x\n", old, new); 4842 } 4843 4844 void rtw89_core_dm_disable_set(struct rtw89_dev *rtwdev, enum rtw89_dm_type type) 4845 { 4846 struct rtw89_hal *hal = &rtwdev->hal; 4847 u32 cur = hal->disabled_dm_bitmap; 4848 4849 rtw89_core_dm_disable_cfg(rtwdev, cur | BIT(type)); 4850 } 4851 4852 void rtw89_core_dm_disable_clr(struct rtw89_dev *rtwdev, enum rtw89_dm_type type) 4853 { 4854 struct rtw89_hal *hal = &rtwdev->hal; 4855 u32 cur = hal->disabled_dm_bitmap; 4856 4857 rtw89_core_dm_disable_cfg(rtwdev, cur & ~BIT(type)); 4858 } 4859 4860 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 4861 { 4862 unsigned long bit; 4863 4864 bit = find_first_zero_bit(addr, size); 4865 if (bit < size) 4866 set_bit(bit, addr); 4867 4868 return bit; 4869 } 4870 4871 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 4872 { 4873 clear_bit(bit, addr); 4874 } 4875 4876 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 4877 { 4878 bitmap_zero(addr, nbits); 4879 } 4880 4881 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 4882 struct rtw89_sta_link *rtwsta_link, u8 tid, 4883 u8 *cam_idx) 4884 { 4885 const struct rtw89_chip_info *chip = rtwdev->chip; 4886 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 4887 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 4888 u8 idx; 4889 int i; 4890 4891 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4892 4893 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 4894 if (idx == chip->bacam_num) { 4895 /* allocate a static BA CAM to tid=0/5, so replace the existing 4896 * one if BA CAM is full. Hardware will process the original tid 4897 * automatically. 4898 */ 4899 if (tid != 0 && tid != 5) 4900 return -ENOSPC; 4901 4902 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 4903 tmp = &cam_info->ba_cam_entry[i]; 4904 if (tmp->tid == 0 || tmp->tid == 5) 4905 continue; 4906 4907 idx = i; 4908 entry = tmp; 4909 list_del(&entry->list); 4910 break; 4911 } 4912 4913 if (!entry) 4914 return -ENOSPC; 4915 } else { 4916 entry = &cam_info->ba_cam_entry[idx]; 4917 } 4918 4919 entry->tid = tid; 4920 list_add_tail(&entry->list, &rtwsta_link->ba_cam_list); 4921 4922 *cam_idx = idx; 4923 4924 return 0; 4925 } 4926 4927 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 4928 struct rtw89_sta_link *rtwsta_link, u8 tid, 4929 u8 *cam_idx) 4930 { 4931 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 4932 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 4933 u8 idx; 4934 4935 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4936 4937 list_for_each_entry_safe(entry, tmp, &rtwsta_link->ba_cam_list, list) { 4938 if (entry->tid != tid) 4939 continue; 4940 4941 idx = entry - cam_info->ba_cam_entry; 4942 list_del(&entry->list); 4943 4944 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 4945 *cam_idx = idx; 4946 return 0; 4947 } 4948 4949 return -ENOENT; 4950 } 4951 4952 #define RTW89_TYPE_MAPPING(_type) \ 4953 case NL80211_IFTYPE_ ## _type: \ 4954 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 4955 break 4956 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc) 4957 { 4958 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4959 const struct ieee80211_bss_conf *bss_conf; 4960 4961 switch (vif->type) { 4962 case NL80211_IFTYPE_STATION: 4963 if (vif->p2p) 4964 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 4965 else 4966 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_STATION; 4967 break; 4968 case NL80211_IFTYPE_AP: 4969 if (vif->p2p) 4970 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 4971 else 4972 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_AP; 4973 break; 4974 RTW89_TYPE_MAPPING(ADHOC); 4975 RTW89_TYPE_MAPPING(MONITOR); 4976 RTW89_TYPE_MAPPING(MESH_POINT); 4977 default: 4978 WARN_ON(1); 4979 break; 4980 } 4981 4982 switch (vif->type) { 4983 case NL80211_IFTYPE_AP: 4984 case NL80211_IFTYPE_MESH_POINT: 4985 rtwvif_link->net_type = RTW89_NET_TYPE_AP_MODE; 4986 rtwvif_link->self_role = RTW89_SELF_ROLE_AP; 4987 break; 4988 case NL80211_IFTYPE_ADHOC: 4989 rtwvif_link->net_type = RTW89_NET_TYPE_AD_HOC; 4990 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 4991 break; 4992 case NL80211_IFTYPE_STATION: 4993 if (assoc) { 4994 rtwvif_link->net_type = RTW89_NET_TYPE_INFRA; 4995 4996 rcu_read_lock(); 4997 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 4998 rtwvif_link->trigger = bss_conf->he_support; 4999 rcu_read_unlock(); 5000 } else { 5001 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK; 5002 rtwvif_link->trigger = false; 5003 } 5004 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 5005 rtwvif_link->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 5006 break; 5007 case NL80211_IFTYPE_MONITOR: 5008 break; 5009 default: 5010 WARN_ON(1); 5011 break; 5012 } 5013 } 5014 5015 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 5016 struct rtw89_vif_link *rtwvif_link, 5017 struct rtw89_sta_link *rtwsta_link) 5018 { 5019 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5020 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 5021 struct rtw89_hal *hal = &rtwdev->hal; 5022 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 5023 int i; 5024 int ret; 5025 5026 rtwsta_link->prev_rssi = 0; 5027 INIT_LIST_HEAD(&rtwsta_link->ba_cam_list); 5028 ewma_rssi_init(&rtwsta_link->avg_rssi); 5029 ewma_snr_init(&rtwsta_link->avg_snr); 5030 ewma_evm_init(&rtwsta_link->evm_1ss); 5031 for (i = 0; i < ant_num; i++) { 5032 ewma_rssi_init(&rtwsta_link->rssi[i]); 5033 ewma_evm_init(&rtwsta_link->evm_min[i]); 5034 ewma_evm_init(&rtwsta_link->evm_max[i]); 5035 } 5036 5037 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 5038 /* must do rtw89_reg_6ghz_recalc() before rfk channel */ 5039 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, true); 5040 if (ret) 5041 return ret; 5042 5043 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 5044 BTC_ROLE_MSTS_STA_CONN_START); 5045 rtw89_chip_rfk_channel(rtwdev, rtwvif_link); 5046 5047 if (vif->p2p) { 5048 rtw89_mac_get_tx_retry_limit(rtwdev, rtwsta_link, 5049 &rtwsta_link->tx_retry); 5050 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 60); 5051 } 5052 rtw89_phy_dig_suspend(rtwdev); 5053 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 5054 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta_link->mac_id, false); 5055 if (ret) { 5056 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 5057 return ret; 5058 } 5059 5060 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 5061 RTW89_ROLE_CREATE); 5062 if (ret) { 5063 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 5064 return ret; 5065 } 5066 5067 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 5068 if (ret) 5069 return ret; 5070 5071 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 5072 if (ret) 5073 return ret; 5074 } 5075 5076 return 0; 5077 } 5078 5079 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 5080 struct rtw89_vif_link *rtwvif_link, 5081 struct rtw89_sta_link *rtwsta_link) 5082 { 5083 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5084 5085 rtw89_assoc_link_clr(rtwsta_link); 5086 5087 if (vif->type == NL80211_IFTYPE_STATION) { 5088 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false); 5089 rtw89_core_bcn_track_reset(rtwdev); 5090 } 5091 5092 if (rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT) 5093 rtw89_p2p_noa_once_deinit(rtwvif_link); 5094 5095 return 0; 5096 } 5097 5098 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 5099 struct rtw89_vif_link *rtwvif_link, 5100 struct rtw89_sta_link *rtwsta_link) 5101 { 5102 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5103 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 5104 int ret; 5105 5106 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, true); 5107 rtw89_mac_bf_disassoc(rtwdev, rtwvif_link, rtwsta_link); 5108 5109 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 5110 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam); 5111 if (sta->tdls) 5112 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam); 5113 5114 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 5115 rtw89_vif_type_mapping(rtwvif_link, false); 5116 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif_link, true); 5117 } 5118 5119 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 5120 if (ret) { 5121 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 5122 return ret; 5123 } 5124 5125 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, true); 5126 if (ret) { 5127 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 5128 return ret; 5129 } 5130 5131 /* update cam aid mac_id net_type */ 5132 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL, 5133 RTW89_ROLE_CON_DISCONN); 5134 if (ret) { 5135 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 5136 return ret; 5137 } 5138 5139 return ret; 5140 } 5141 5142 static bool rtw89_sta_link_can_er(struct rtw89_dev *rtwdev, 5143 struct ieee80211_bss_conf *bss_conf, 5144 struct ieee80211_link_sta *link_sta) 5145 { 5146 if (!bss_conf->he_support || 5147 bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE) 5148 return false; 5149 5150 if (rtwdev->chip->chip_id == RTL8852C && 5151 rtw89_sta_link_has_su_mu_4xhe08(link_sta) && 5152 !rtw89_sta_link_has_er_su_4xhe08(link_sta)) 5153 return false; 5154 5155 return true; 5156 } 5157 5158 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 5159 struct rtw89_vif_link *rtwvif_link, 5160 struct rtw89_sta_link *rtwsta_link) 5161 { 5162 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5163 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 5164 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link, 5165 rtwsta_link); 5166 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 5167 rtwvif_link->chanctx_idx); 5168 struct ieee80211_link_sta *link_sta; 5169 int ret; 5170 5171 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 5172 if (sta->tdls) { 5173 rcu_read_lock(); 5174 5175 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 5176 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif_link, bssid_cam, 5177 link_sta->addr); 5178 if (ret) { 5179 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 5180 rcu_read_unlock(); 5181 return ret; 5182 } 5183 5184 rcu_read_unlock(); 5185 } 5186 5187 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta_link->addr_cam, bssid_cam); 5188 if (ret) { 5189 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 5190 return ret; 5191 } 5192 } 5193 5194 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 5195 if (ret) { 5196 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 5197 return ret; 5198 } 5199 5200 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, false); 5201 if (ret) { 5202 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 5203 return ret; 5204 } 5205 5206 /* update cam aid mac_id net_type */ 5207 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL, 5208 RTW89_ROLE_CON_DISCONN); 5209 if (ret) { 5210 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 5211 return ret; 5212 } 5213 5214 rtw89_phy_ra_assoc(rtwdev, rtwsta_link); 5215 rtw89_mac_bf_assoc(rtwdev, rtwvif_link, rtwsta_link); 5216 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, false); 5217 5218 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 5219 struct ieee80211_bss_conf *bss_conf; 5220 5221 rcu_read_lock(); 5222 5223 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 5224 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 5225 rtwsta_link->er_cap = rtw89_sta_link_can_er(rtwdev, bss_conf, link_sta); 5226 5227 rcu_read_unlock(); 5228 5229 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 5230 BTC_ROLE_MSTS_STA_CONN_END); 5231 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan); 5232 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link); 5233 rtw89_core_bcn_track_assoc(rtwdev, rtwvif_link); 5234 5235 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id); 5236 if (ret) { 5237 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 5238 return ret; 5239 } 5240 5241 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 5242 5243 if (vif->p2p) 5244 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 5245 rtwsta_link->tx_retry); 5246 rtw89_phy_dig_resume(rtwdev, false); 5247 } 5248 5249 rtw89_assoc_link_set(rtwsta_link); 5250 return ret; 5251 } 5252 5253 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 5254 struct rtw89_vif_link *rtwvif_link, 5255 struct rtw89_sta_link *rtwsta_link) 5256 { 5257 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5258 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 5259 int ret; 5260 5261 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 5262 rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, false); 5263 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 5264 BTC_ROLE_MSTS_STA_DIS_CONN); 5265 5266 if (vif->p2p) 5267 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 5268 rtwsta_link->tx_retry); 5269 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 5270 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 5271 RTW89_ROLE_REMOVE); 5272 if (ret) { 5273 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 5274 return ret; 5275 } 5276 } 5277 5278 return 0; 5279 } 5280 5281 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 5282 struct ieee80211_sta *sta, 5283 struct cfg80211_tid_cfg *tid_conf) 5284 { 5285 struct ieee80211_txq *txq; 5286 struct rtw89_txq *rtwtxq; 5287 u32 mask = tid_conf->mask; 5288 u8 tids = tid_conf->tids; 5289 int tids_nbit = BITS_PER_BYTE; 5290 int i; 5291 5292 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 5293 if (!tids) 5294 break; 5295 5296 if (!(tids & BIT(0))) 5297 continue; 5298 5299 txq = sta->txq[i]; 5300 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 5301 5302 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 5303 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 5304 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 5305 } else { 5306 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 5307 ieee80211_stop_tx_ba_session(sta, txq->tid); 5308 spin_lock_bh(&rtwdev->ba_lock); 5309 list_del_init(&rtwtxq->list); 5310 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 5311 spin_unlock_bh(&rtwdev->ba_lock); 5312 } 5313 } 5314 5315 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 5316 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 5317 sta->max_amsdu_subframes = 0; 5318 else 5319 sta->max_amsdu_subframes = 1; 5320 } 5321 } 5322 } 5323 5324 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 5325 struct ieee80211_sta *sta, 5326 struct cfg80211_tid_config *tid_config) 5327 { 5328 int i; 5329 5330 for (i = 0; i < tid_config->n_tid_conf; i++) 5331 _rtw89_core_set_tid_config(rtwdev, sta, 5332 &tid_config->tid_conf[i]); 5333 } 5334 5335 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 5336 struct ieee80211_sta_ht_cap *ht_cap) 5337 { 5338 static const __le16 highest[RF_PATH_MAX] = { 5339 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 5340 }; 5341 struct rtw89_hal *hal = &rtwdev->hal; 5342 u8 nss = hal->rx_nss; 5343 int i; 5344 5345 ht_cap->ht_supported = true; 5346 ht_cap->cap = 0; 5347 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 5348 IEEE80211_HT_CAP_MAX_AMSDU | 5349 IEEE80211_HT_CAP_TX_STBC | 5350 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 5351 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 5352 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 5353 IEEE80211_HT_CAP_DSSSCCK40 | 5354 IEEE80211_HT_CAP_SGI_40; 5355 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 5356 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 5357 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 5358 for (i = 0; i < nss; i++) 5359 ht_cap->mcs.rx_mask[i] = 0xFF; 5360 ht_cap->mcs.rx_mask[4] = 0x01; 5361 ht_cap->mcs.rx_highest = highest[nss - 1]; 5362 } 5363 5364 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 5365 struct ieee80211_sta_vht_cap *vht_cap) 5366 { 5367 static const __le16 highest_bw80[RF_PATH_MAX] = { 5368 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 5369 }; 5370 static const __le16 highest_bw160[RF_PATH_MAX] = { 5371 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 5372 }; 5373 const struct rtw89_chip_info *chip = rtwdev->chip; 5374 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ? 5375 highest_bw160 : highest_bw80; 5376 struct rtw89_hal *hal = &rtwdev->hal; 5377 u16 tx_mcs_map = 0, rx_mcs_map = 0; 5378 u8 sts_cap = 3; 5379 int i; 5380 5381 for (i = 0; i < 8; i++) { 5382 if (i < hal->tx_nss) 5383 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 5384 else 5385 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 5386 if (i < hal->rx_nss) 5387 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 5388 else 5389 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 5390 } 5391 5392 vht_cap->vht_supported = true; 5393 vht_cap->cap = chip->max_vht_mpdu_cap | 5394 IEEE80211_VHT_CAP_SHORT_GI_80 | 5395 IEEE80211_VHT_CAP_RXSTBC_1 | 5396 IEEE80211_VHT_CAP_HTC_VHT | 5397 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 5398 0; 5399 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 5400 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 5401 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 5402 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 5403 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 5404 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 5405 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 5406 IEEE80211_VHT_CAP_SHORT_GI_160; 5407 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 5408 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 5409 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 5410 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 5411 5412 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW)) 5413 vht_cap->vht_mcs.tx_highest |= 5414 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 5415 } 5416 5417 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 5418 enum nl80211_band band, 5419 enum nl80211_iftype iftype, 5420 struct ieee80211_sband_iftype_data *iftype_data) 5421 { 5422 const struct rtw89_chip_info *chip = rtwdev->chip; 5423 struct rtw89_hal *hal = &rtwdev->hal; 5424 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 5425 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 5426 struct ieee80211_sta_he_cap *he_cap; 5427 int nss = hal->rx_nss; 5428 u8 *mac_cap_info; 5429 u8 *phy_cap_info; 5430 u16 mcs_map = 0; 5431 int i; 5432 5433 for (i = 0; i < 8; i++) { 5434 if (i < nss) 5435 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 5436 else 5437 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 5438 } 5439 5440 he_cap = &iftype_data->he_cap; 5441 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 5442 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 5443 5444 he_cap->has_he = true; 5445 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 5446 if (iftype == NL80211_IFTYPE_STATION) 5447 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 5448 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 5449 IEEE80211_HE_MAC_CAP2_BSR; 5450 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 5451 if (iftype == NL80211_IFTYPE_AP) 5452 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 5453 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 5454 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 5455 if (iftype == NL80211_IFTYPE_STATION) 5456 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 5457 if (band == NL80211_BAND_2GHZ) { 5458 phy_cap_info[0] = 5459 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 5460 } else { 5461 phy_cap_info[0] = 5462 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 5463 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 5464 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 5465 } 5466 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 5467 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 5468 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 5469 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 5470 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 5471 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 5472 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 5473 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 5474 if (iftype == NL80211_IFTYPE_STATION) 5475 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 5476 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 5477 if (iftype == NL80211_IFTYPE_AP) 5478 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 5479 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 5480 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 5481 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 5482 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 5483 phy_cap_info[5] = no_ng16 ? 0 : 5484 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 5485 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 5486 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 5487 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 5488 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 5489 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 5490 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 5491 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 5492 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 5493 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 5494 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 5495 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 5496 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 5497 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 5498 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 5499 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 5500 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 5501 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 5502 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 5503 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 5504 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 5505 if (iftype == NL80211_IFTYPE_STATION) 5506 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 5507 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 5508 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 5509 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) { 5510 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 5511 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 5512 } 5513 5514 if (band == NL80211_BAND_6GHZ) { 5515 __le16 capa; 5516 5517 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 5518 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 5519 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 5520 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 5521 le16_encode_bits(chip->max_vht_mpdu_cap, 5522 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 5523 iftype_data->he_6ghz_capa.capa = capa; 5524 } 5525 } 5526 5527 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, 5528 enum nl80211_band band, 5529 enum nl80211_iftype iftype, 5530 struct ieee80211_sband_iftype_data *iftype_data) 5531 { 5532 const struct rtw89_chip_info *chip = rtwdev->chip; 5533 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem; 5534 struct ieee80211_eht_mcs_nss_supp *eht_nss; 5535 struct ieee80211_sta_eht_cap *eht_cap; 5536 struct rtw89_hal *hal = &rtwdev->hal; 5537 bool support_mcs_12_13 = true; 5538 bool support_320mhz = false; 5539 u8 val, val_mcs13; 5540 int sts = 8; 5541 5542 if (chip->chip_gen == RTW89_CHIP_AX || hal->no_eht) 5543 return; 5544 5545 if (hal->no_mcs_12_13) 5546 support_mcs_12_13 = false; 5547 5548 if (band == NL80211_BAND_6GHZ && 5549 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320)) 5550 support_320mhz = true; 5551 5552 eht_cap = &iftype_data->eht_cap; 5553 eht_cap_elem = &eht_cap->eht_cap_elem; 5554 eht_nss = &eht_cap->eht_mcs_nss_supp; 5555 5556 eht_cap->has_eht = true; 5557 5558 eht_cap_elem->mac_cap_info[0] = 5559 u8_encode_bits(chip->max_eht_mpdu_cap, 5560 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 5561 eht_cap_elem->mac_cap_info[1] = 0; 5562 5563 eht_cap_elem->phy_cap_info[0] = 5564 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 5565 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 5566 if (support_320mhz) 5567 eht_cap_elem->phy_cap_info[0] |= 5568 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 5569 5570 eht_cap_elem->phy_cap_info[0] |= 5571 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)), 5572 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 5573 eht_cap_elem->phy_cap_info[1] = 5574 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)), 5575 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 5576 u8_encode_bits(sts - 1, 5577 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 5578 if (support_320mhz) 5579 eht_cap_elem->phy_cap_info[1] |= 5580 u8_encode_bits(sts - 1, 5581 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 5582 5583 eht_cap_elem->phy_cap_info[2] = 0; 5584 5585 eht_cap_elem->phy_cap_info[3] = 5586 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 5587 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 5588 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 5589 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 5590 5591 eht_cap_elem->phy_cap_info[4] = 5592 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 5593 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 5594 5595 eht_cap_elem->phy_cap_info[5] = 5596 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US, 5597 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK); 5598 5599 eht_cap_elem->phy_cap_info[6] = 0; 5600 eht_cap_elem->phy_cap_info[7] = 0; 5601 eht_cap_elem->phy_cap_info[8] = 0; 5602 5603 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) | 5604 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX); 5605 val_mcs13 = support_mcs_12_13 ? val : 0; 5606 5607 eht_nss->bw._80.rx_tx_mcs9_max_nss = val; 5608 eht_nss->bw._80.rx_tx_mcs11_max_nss = val; 5609 eht_nss->bw._80.rx_tx_mcs13_max_nss = val_mcs13; 5610 eht_nss->bw._160.rx_tx_mcs9_max_nss = val; 5611 eht_nss->bw._160.rx_tx_mcs11_max_nss = val; 5612 eht_nss->bw._160.rx_tx_mcs13_max_nss = val_mcs13; 5613 if (support_320mhz) { 5614 eht_nss->bw._320.rx_tx_mcs9_max_nss = val; 5615 eht_nss->bw._320.rx_tx_mcs11_max_nss = val; 5616 eht_nss->bw._320.rx_tx_mcs13_max_nss = val_mcs13; 5617 } 5618 } 5619 5620 #define RTW89_SBAND_IFTYPES_NR 2 5621 5622 static int rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev, 5623 enum nl80211_band band, 5624 struct ieee80211_supported_band *sband) 5625 { 5626 struct ieee80211_sband_iftype_data *iftype_data; 5627 enum nl80211_iftype iftype; 5628 int idx = 0; 5629 5630 iftype_data = devm_kcalloc(rtwdev->dev, RTW89_SBAND_IFTYPES_NR, 5631 sizeof(*iftype_data), GFP_KERNEL); 5632 if (!iftype_data) 5633 return -ENOMEM; 5634 5635 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) { 5636 switch (iftype) { 5637 case NL80211_IFTYPE_STATION: 5638 case NL80211_IFTYPE_AP: 5639 break; 5640 default: 5641 continue; 5642 } 5643 5644 if (idx >= RTW89_SBAND_IFTYPES_NR) { 5645 rtw89_warn(rtwdev, "run out of iftype_data\n"); 5646 break; 5647 } 5648 5649 iftype_data[idx].types_mask = BIT(iftype); 5650 5651 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]); 5652 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]); 5653 5654 idx++; 5655 } 5656 5657 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); 5658 return 0; 5659 } 5660 5661 static struct ieee80211_supported_band * 5662 rtw89_core_sband_dup(struct rtw89_dev *rtwdev, 5663 const struct ieee80211_supported_band *sband) 5664 { 5665 struct ieee80211_supported_band *dup; 5666 5667 dup = devm_kmemdup(rtwdev->dev, sband, sizeof(*sband), GFP_KERNEL); 5668 if (!dup) 5669 return NULL; 5670 5671 dup->channels = devm_kmemdup(rtwdev->dev, sband->channels, 5672 sizeof(*sband->channels) * sband->n_channels, 5673 GFP_KERNEL); 5674 if (!dup->channels) 5675 return NULL; 5676 5677 dup->bitrates = devm_kmemdup(rtwdev->dev, sband->bitrates, 5678 sizeof(*sband->bitrates) * sband->n_bitrates, 5679 GFP_KERNEL); 5680 if (!dup->bitrates) 5681 return NULL; 5682 5683 return dup; 5684 } 5685 5686 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 5687 { 5688 struct ieee80211_hw *hw = rtwdev->hw; 5689 struct ieee80211_supported_band *sband; 5690 u8 support_bands = rtwdev->chip->support_bands; 5691 int ret; 5692 5693 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 5694 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_2ghz); 5695 if (!sband) 5696 return -ENOMEM; 5697 rtw89_init_ht_cap(rtwdev, &sband->ht_cap); 5698 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband); 5699 if (ret) 5700 return ret; 5701 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 5702 } 5703 5704 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 5705 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_5ghz); 5706 if (!sband) 5707 return -ENOMEM; 5708 rtw89_init_ht_cap(rtwdev, &sband->ht_cap); 5709 rtw89_init_vht_cap(rtwdev, &sband->vht_cap); 5710 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband); 5711 if (ret) 5712 return ret; 5713 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 5714 } 5715 5716 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 5717 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_6ghz); 5718 if (!sband) 5719 return -ENOMEM; 5720 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband); 5721 if (ret) 5722 return ret; 5723 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband; 5724 } 5725 5726 return 0; 5727 } 5728 5729 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 5730 { 5731 int i; 5732 5733 for (i = 0; i < RTW89_PHY_NUM; i++) 5734 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 5735 for (i = 0; i < RTW89_PHY_NUM; i++) 5736 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 5737 } 5738 5739 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work) 5740 { 5741 struct rtw89_dev *rtwdev; 5742 struct rtw89_vif_link *rtwvif_link = container_of(work, struct rtw89_vif_link, 5743 update_beacon_work); 5744 5745 lockdep_assert_wiphy(wiphy); 5746 5747 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 5748 return; 5749 5750 rtwdev = rtwvif_link->rtwvif->rtwdev; 5751 5752 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link); 5753 } 5754 5755 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work) 5756 { 5757 struct rtw89_vif_link *rtwvif_link = 5758 container_of(work, struct rtw89_vif_link, csa_beacon_work.work); 5759 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5760 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 5761 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 5762 struct ieee80211_bss_conf *bss_conf; 5763 unsigned int delay; 5764 5765 lockdep_assert_wiphy(wiphy); 5766 5767 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 5768 return; 5769 5770 rcu_read_lock(); 5771 5772 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 5773 if (!bss_conf->csa_active) { 5774 rcu_read_unlock(); 5775 return; 5776 } 5777 5778 delay = ieee80211_tu_to_usec(bss_conf->beacon_int); 5779 5780 rcu_read_unlock(); 5781 5782 if (!ieee80211_beacon_cntdwn_is_complete(vif, rtwvif_link->link_id)) { 5783 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link); 5784 5785 wiphy_delayed_work_queue(wiphy, &rtwvif_link->csa_beacon_work, 5786 usecs_to_jiffies(delay)); 5787 } else { 5788 ieee80211_csa_finish(vif, rtwvif_link->link_id); 5789 } 5790 } 5791 5792 struct rtw89_wait_response * 5793 rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond) 5794 { 5795 struct rtw89_wait_response *prep; 5796 unsigned int cur; 5797 5798 /* use -EPERM _iff_ telling eval side not to make any changes */ 5799 5800 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 5801 if (cur != RTW89_WAIT_COND_IDLE) 5802 return ERR_PTR(-EPERM); 5803 5804 prep = kzalloc_obj(*prep); 5805 if (!prep) 5806 return ERR_PTR(-ENOMEM); 5807 5808 init_completion(&prep->completion); 5809 5810 rcu_assign_pointer(wait->resp, prep); 5811 5812 return prep; 5813 } 5814 5815 int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait, 5816 struct rtw89_wait_response *prep, int err) 5817 { 5818 unsigned long time_left; 5819 5820 if (IS_ERR(prep)) { 5821 err = err ?: PTR_ERR(prep); 5822 5823 /* special error case: no permission to reset anything */ 5824 if (PTR_ERR(prep) == -EPERM) 5825 return err; 5826 5827 goto reset; 5828 } 5829 5830 if (err) 5831 goto cleanup; 5832 5833 time_left = wait_for_completion_timeout(&prep->completion, 5834 RTW89_WAIT_FOR_COND_TIMEOUT); 5835 if (time_left == 0) { 5836 err = -ETIMEDOUT; 5837 goto cleanup; 5838 } 5839 5840 wait->data = prep->data; 5841 5842 cleanup: 5843 rcu_assign_pointer(wait->resp, NULL); 5844 kfree_rcu(prep, rcu_head); 5845 5846 reset: 5847 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 5848 5849 if (err) 5850 return err; 5851 5852 if (wait->data.err) 5853 return -EFAULT; 5854 5855 return 0; 5856 } 5857 5858 static void rtw89_complete_cond_resp(struct rtw89_wait_response *resp, 5859 const struct rtw89_completion_data *data) 5860 { 5861 resp->data = *data; 5862 complete(&resp->completion); 5863 } 5864 5865 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 5866 const struct rtw89_completion_data *data) 5867 { 5868 struct rtw89_wait_response *resp; 5869 unsigned int cur; 5870 5871 guard(rcu)(); 5872 5873 resp = rcu_dereference(wait->resp); 5874 if (!resp) 5875 return; 5876 5877 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 5878 if (cur != cond) 5879 return; 5880 5881 rtw89_complete_cond_resp(resp, data); 5882 } 5883 5884 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) 5885 { 5886 u16 bt_req_len; 5887 5888 switch (event) { 5889 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 5890 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); 5891 rtw89_debug(rtwdev, RTW89_DBG_BTC, 5892 "coex updates BT req len to %d TU\n", bt_req_len); 5893 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE); 5894 break; 5895 default: 5896 if (event < NUM_OF_RTW89_BTC_HMSG) 5897 rtw89_debug(rtwdev, RTW89_DBG_BTC, 5898 "unhandled BTC HMSG event: %d\n", event); 5899 else 5900 rtw89_warn(rtwdev, 5901 "unrecognized BTC HMSG event: %d\n", event); 5902 break; 5903 } 5904 } 5905 5906 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks) 5907 { 5908 const struct dmi_system_id *match; 5909 enum rtw89_quirks quirk; 5910 5911 if (!quirks) 5912 return; 5913 5914 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) { 5915 quirk = (uintptr_t)match->driver_data; 5916 if (quirk >= NUM_OF_RTW89_QUIRKS) 5917 continue; 5918 5919 set_bit(quirk, rtwdev->quirks); 5920 } 5921 } 5922 EXPORT_SYMBOL(rtw89_check_quirks); 5923 5924 int rtw89_core_start(struct rtw89_dev *rtwdev) 5925 { 5926 bool no_bbmcu = !rtwdev->chip->bbmcu_nr; 5927 int ret; 5928 5929 ret = rtw89_mac_preinit(rtwdev); 5930 if (ret) { 5931 rtw89_err(rtwdev, "mac preinit fail, ret: %d\n", ret); 5932 return ret; 5933 } 5934 5935 if (no_bbmcu) 5936 rtw89_chip_bb_preinit(rtwdev); 5937 5938 rtw89_phy_init_bb_afe(rtwdev); 5939 5940 /* above do preinit before downloading firmware */ 5941 5942 ret = rtw89_mac_init(rtwdev); 5943 if (ret) { 5944 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 5945 return ret; 5946 } 5947 5948 rtw89_btc_ntfy_poweron(rtwdev); 5949 5950 /* efuse process */ 5951 5952 /* pre-config BB/RF, BB reset/RFC reset */ 5953 ret = rtw89_chip_reset_bb_rf(rtwdev); 5954 if (ret) 5955 return ret; 5956 5957 rtw89_phy_init_bb_reg(rtwdev); 5958 rtw89_chip_bb_postinit(rtwdev); 5959 rtw89_phy_init_rf_reg(rtwdev, false); 5960 5961 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 5962 5963 rtw89_phy_dm_init(rtwdev); 5964 5965 rtw89_mac_set_edcca_mode_bands(rtwdev, true); 5966 rtw89_mac_cfg_ppdu_status_bands(rtwdev, true); 5967 rtw89_mac_cfg_phy_rpt_bands(rtwdev, true); 5968 rtw89_mac_update_rts_threshold(rtwdev); 5969 5970 ret = rtw89_hci_start(rtwdev); 5971 if (ret) { 5972 rtw89_err(rtwdev, "failed to start hci\n"); 5973 return ret; 5974 } 5975 5976 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_work, 5977 RTW89_TRACK_WORK_PERIOD); 5978 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_ps_work, 5979 RTW89_TRACK_PS_WORK_PERIOD); 5980 5981 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 5982 5983 rtw89_chip_rfk_init_late(rtwdev); 5984 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 5985 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 5986 rtw89_fw_h2c_init_ba_cam(rtwdev); 5987 rtw89_tas_fw_timer_enable(rtwdev, true); 5988 rtwdev->ps_hang_cnt = 0; 5989 5990 return 0; 5991 } 5992 5993 void rtw89_core_stop(struct rtw89_dev *rtwdev) 5994 { 5995 struct wiphy *wiphy = rtwdev->hw->wiphy; 5996 struct rtw89_btc *btc = &rtwdev->btc; 5997 5998 lockdep_assert_wiphy(wiphy); 5999 6000 /* Prvent to stop twice; enter_ips and ops_stop */ 6001 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 6002 return; 6003 6004 rtw89_tas_fw_timer_enable(rtwdev, false); 6005 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 6006 6007 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 6008 6009 wiphy_work_cancel(wiphy, &rtwdev->c2h_work); 6010 wiphy_work_cancel(wiphy, &rtwdev->cancel_6ghz_probe_work); 6011 wiphy_work_cancel(wiphy, &btc->eapol_notify_work); 6012 wiphy_work_cancel(wiphy, &btc->arp_notify_work); 6013 wiphy_work_cancel(wiphy, &btc->dhcp_notify_work); 6014 wiphy_work_cancel(wiphy, &btc->icmp_notify_work); 6015 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 6016 wiphy_delayed_work_cancel(wiphy, &rtwdev->tx_wait_work); 6017 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_work); 6018 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_ps_work); 6019 wiphy_delayed_work_cancel(wiphy, &rtwdev->chanctx_work); 6020 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_act1_work); 6021 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_bt_devinfo_work); 6022 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_rfk_chk_work); 6023 wiphy_delayed_work_cancel(wiphy, &rtwdev->cfo_track_work); 6024 wiphy_delayed_work_cancel(wiphy, &rtwdev->mcc_prepare_done_work); 6025 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 6026 wiphy_delayed_work_cancel(wiphy, &rtwdev->antdiv_work); 6027 6028 rtw89_btc_ntfy_poweroff(rtwdev); 6029 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 6030 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 6031 rtw89_hci_stop(rtwdev); 6032 rtw89_hci_deinit(rtwdev); 6033 rtw89_mac_pwr_off(rtwdev); 6034 rtw89_hci_reset(rtwdev); 6035 } 6036 6037 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev) 6038 { 6039 const struct rtw89_chip_info *chip = rtwdev->chip; 6040 u8 mac_id_num; 6041 u8 mac_id; 6042 6043 if (rtwdev->support_mlo) 6044 mac_id_num = chip->support_macid_num / chip->support_link_num; 6045 else 6046 mac_id_num = chip->support_macid_num; 6047 6048 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num); 6049 if (mac_id == mac_id_num) 6050 return RTW89_MAX_MAC_ID_NUM; 6051 6052 set_bit(mac_id, rtwdev->mac_id_map); 6053 return mac_id; 6054 } 6055 6056 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id) 6057 { 6058 clear_bit(mac_id, rtwdev->mac_id_map); 6059 } 6060 6061 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6062 u8 mac_id, u8 port) 6063 { 6064 const struct rtw89_chip_info *chip = rtwdev->chip; 6065 u8 support_link_num = chip->support_link_num; 6066 u8 support_mld_num = 0; 6067 unsigned int link_id; 6068 u8 index; 6069 6070 bitmap_zero(rtwvif->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 6071 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 6072 rtwvif->links[link_id] = NULL; 6073 6074 rtwvif->rtwdev = rtwdev; 6075 6076 if (rtwdev->support_mlo) { 6077 rtwvif->links_inst_valid_num = support_link_num; 6078 support_mld_num = chip->support_macid_num / support_link_num; 6079 } else { 6080 rtwvif->links_inst_valid_num = 1; 6081 } 6082 6083 for (index = 0; index < rtwvif->links_inst_valid_num; index++) { 6084 struct rtw89_vif_link *inst = &rtwvif->links_inst[index]; 6085 6086 inst->rtwvif = rtwvif; 6087 inst->mac_id = mac_id + index * support_mld_num; 6088 inst->mac_idx = RTW89_MAC_0 + index; 6089 inst->phy_idx = RTW89_PHY_0 + index; 6090 6091 /* multi-link use the same port id on different HW bands */ 6092 inst->port = port; 6093 } 6094 } 6095 6096 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6097 struct rtw89_sta *rtwsta, u8 mac_id) 6098 { 6099 const struct rtw89_chip_info *chip = rtwdev->chip; 6100 u8 support_link_num = chip->support_link_num; 6101 u8 support_mld_num = 0; 6102 unsigned int link_id; 6103 u8 index; 6104 6105 bitmap_zero(rtwsta->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 6106 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 6107 rtwsta->links[link_id] = NULL; 6108 6109 rtwsta->rtwdev = rtwdev; 6110 rtwsta->rtwvif = rtwvif; 6111 6112 if (rtwdev->support_mlo) { 6113 rtwsta->links_inst_valid_num = support_link_num; 6114 support_mld_num = chip->support_macid_num / support_link_num; 6115 } else { 6116 rtwsta->links_inst_valid_num = 1; 6117 } 6118 6119 for (index = 0; index < rtwsta->links_inst_valid_num; index++) { 6120 struct rtw89_sta_link *inst = &rtwsta->links_inst[index]; 6121 6122 inst->rtwvif_link = &rtwvif->links_inst[index]; 6123 6124 inst->rtwsta = rtwsta; 6125 inst->mac_id = mac_id + index * support_mld_num; 6126 } 6127 } 6128 6129 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 6130 unsigned int link_id) 6131 { 6132 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 6133 u8 index; 6134 int ret; 6135 6136 if (rtwvif_link) 6137 return rtwvif_link; 6138 6139 index = find_first_zero_bit(rtwvif->links_inst_map, 6140 rtwvif->links_inst_valid_num); 6141 if (index == rtwvif->links_inst_valid_num) { 6142 ret = -EBUSY; 6143 goto err; 6144 } 6145 6146 rtwvif_link = &rtwvif->links_inst[index]; 6147 rtwvif_link->link_id = link_id; 6148 6149 set_bit(index, rtwvif->links_inst_map); 6150 rtwvif->links[link_id] = rtwvif_link; 6151 list_add_tail(&rtwvif_link->dlink_schd, &rtwvif->dlink_pool); 6152 return rtwvif_link; 6153 6154 err: 6155 rtw89_err(rtwvif->rtwdev, "vif (link_id %u) failed to set link: %d\n", 6156 link_id, ret); 6157 return NULL; 6158 } 6159 6160 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id) 6161 { 6162 struct rtw89_vif_link **container = &rtwvif->links[link_id]; 6163 struct rtw89_vif_link *link = *container; 6164 u8 index; 6165 6166 if (!link) 6167 return; 6168 6169 index = rtw89_vif_link_inst_get_index(link); 6170 clear_bit(index, rtwvif->links_inst_map); 6171 *container = NULL; 6172 list_del(&link->dlink_schd); 6173 } 6174 6175 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 6176 unsigned int link_id) 6177 { 6178 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6179 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 6180 struct rtw89_sta_link *rtwsta_link = rtwsta->links[link_id]; 6181 u8 index; 6182 int ret; 6183 6184 if (rtwsta_link) 6185 return rtwsta_link; 6186 6187 if (!rtwvif_link) { 6188 ret = -ENOLINK; 6189 goto err; 6190 } 6191 6192 index = rtw89_vif_link_inst_get_index(rtwvif_link); 6193 if (test_bit(index, rtwsta->links_inst_map)) { 6194 ret = -EBUSY; 6195 goto err; 6196 } 6197 6198 rtwsta_link = &rtwsta->links_inst[index]; 6199 rtwsta_link->link_id = link_id; 6200 6201 set_bit(index, rtwsta->links_inst_map); 6202 rtwsta->links[link_id] = rtwsta_link; 6203 list_add_tail(&rtwsta_link->dlink_schd, &rtwsta->dlink_pool); 6204 return rtwsta_link; 6205 6206 err: 6207 rtw89_err(rtwsta->rtwdev, "sta (link_id %u) failed to set link: %d\n", 6208 link_id, ret); 6209 return NULL; 6210 } 6211 6212 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id) 6213 { 6214 struct rtw89_sta_link **container = &rtwsta->links[link_id]; 6215 struct rtw89_sta_link *link = *container; 6216 u8 index; 6217 6218 if (!link) 6219 return; 6220 6221 index = rtw89_sta_link_inst_get_index(link); 6222 clear_bit(index, rtwsta->links_inst_map); 6223 *container = NULL; 6224 list_del(&link->dlink_schd); 6225 } 6226 6227 int rtw89_core_init(struct rtw89_dev *rtwdev) 6228 { 6229 struct rtw89_btc *btc = &rtwdev->btc; 6230 u8 band; 6231 6232 bitmap_or(rtwdev->quirks, rtwdev->quirks, &rtwdev->chip->default_quirks, 6233 NUM_OF_RTW89_QUIRKS); 6234 6235 INIT_LIST_HEAD(&rtwdev->ba_list); 6236 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 6237 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 6238 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 6239 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 6240 if (!(rtwdev->chip->support_bands & BIT(band))) 6241 continue; 6242 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 6243 } 6244 INIT_LIST_HEAD(&rtwdev->scan_info.chan_list); 6245 INIT_LIST_HEAD(&rtwdev->tx_waits); 6246 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 6247 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 6248 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 6249 wiphy_delayed_work_init(&rtwdev->track_work, rtw89_track_work); 6250 wiphy_delayed_work_init(&rtwdev->track_ps_work, rtw89_track_ps_work); 6251 wiphy_delayed_work_init(&rtwdev->chanctx_work, rtw89_chanctx_work); 6252 wiphy_delayed_work_init(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 6253 wiphy_delayed_work_init(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 6254 wiphy_delayed_work_init(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 6255 wiphy_delayed_work_init(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 6256 wiphy_delayed_work_init(&rtwdev->mcc_prepare_done_work, rtw89_mcc_prepare_done_work); 6257 wiphy_delayed_work_init(&rtwdev->tx_wait_work, rtw89_tx_wait_work); 6258 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 6259 wiphy_delayed_work_init(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 6260 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 6261 if (!rtwdev->txq_wq) 6262 return -ENOMEM; 6263 spin_lock_init(&rtwdev->ba_lock); 6264 spin_lock_init(&rtwdev->rpwm_lock); 6265 rtwdev->total_sta_assoc = 0; 6266 6267 rtw89_init_wait(&rtwdev->mcc.wait); 6268 rtw89_init_wait(&rtwdev->mlo.wait); 6269 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 6270 rtw89_init_wait(&rtwdev->wow.wait); 6271 rtw89_init_wait(&rtwdev->mac.ps_wait); 6272 6273 wiphy_work_init(&rtwdev->c2h_work, rtw89_fw_c2h_work); 6274 wiphy_work_init(&rtwdev->ips_work, rtw89_ips_work); 6275 wiphy_work_init(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 6276 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 6277 6278 spin_lock_init(&rtwdev->tx_rpt.skb_lock); 6279 skb_queue_head_init(&rtwdev->c2h_queue); 6280 rtw89_core_ppdu_sts_init(rtwdev); 6281 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 6282 6283 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 6284 rtwdev->dbcc_en = false; 6285 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT; 6286 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 6287 6288 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 6289 rtwdev->dbcc_en = true; 6290 rtwdev->mac.qta_mode = RTW89_QTA_DBCC; 6291 rtwdev->mlo_dbcc_mode = MLO_1_PLUS_1_1RF; 6292 } 6293 6294 rtwdev->bbs[RTW89_PHY_0].phy_idx = RTW89_PHY_0; 6295 rtwdev->bbs[RTW89_PHY_1].phy_idx = RTW89_PHY_1; 6296 6297 wiphy_work_init(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 6298 wiphy_work_init(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 6299 wiphy_work_init(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 6300 wiphy_work_init(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 6301 6302 init_completion(&rtwdev->fw.req.completion); 6303 init_completion(&rtwdev->rfk_wait.completion); 6304 6305 schedule_work(&rtwdev->load_firmware_work); 6306 6307 rtw89_ser_init(rtwdev); 6308 rtw89_entity_init(rtwdev); 6309 rtw89_sar_init(rtwdev); 6310 rtw89_phy_ant_gain_init(rtwdev); 6311 6312 return 0; 6313 } 6314 EXPORT_SYMBOL(rtw89_core_init); 6315 6316 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 6317 { 6318 rtw89_ser_deinit(rtwdev); 6319 rtw89_unload_firmware(rtwdev); 6320 __rtw89_fw_free_all_early_h2c(rtwdev); 6321 6322 destroy_workqueue(rtwdev->txq_wq); 6323 } 6324 EXPORT_SYMBOL(rtw89_core_deinit); 6325 6326 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 6327 const u8 *mac_addr, bool hw_scan) 6328 { 6329 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 6330 rtwvif_link->chanctx_idx); 6331 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 6332 6333 rtwdev->scanning = true; 6334 6335 ether_addr_copy(rtwvif_link->mac_addr, mac_addr); 6336 rtw89_btc_ntfy_scan_start(rtwdev, rtwvif_link->phy_idx, chan->band_type); 6337 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, true); 6338 rtw89_hci_recalc_int_mit(rtwdev); 6339 rtw89_phy_config_edcca(rtwdev, bb, true); 6340 rtw89_tas_scan(rtwdev, true); 6341 6342 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr, 6343 RTW89_ROLE_INFO_CHANGE); 6344 } 6345 6346 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 6347 struct rtw89_vif_link *rtwvif_link, bool hw_scan) 6348 { 6349 struct ieee80211_bss_conf *bss_conf; 6350 struct rtw89_bb_ctx *bb; 6351 int ret; 6352 6353 if (!rtwvif_link) 6354 return; 6355 6356 rcu_read_lock(); 6357 6358 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 6359 ether_addr_copy(rtwvif_link->mac_addr, bss_conf->addr); 6360 6361 rcu_read_unlock(); 6362 6363 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL, 6364 RTW89_ROLE_INFO_CHANGE); 6365 6366 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false); 6367 rtw89_btc_ntfy_scan_finish(rtwdev, rtwvif_link->phy_idx); 6368 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 6369 rtw89_phy_config_edcca(rtwdev, bb, false); 6370 rtw89_tas_scan(rtwdev, false); 6371 6372 if (hw_scan) { 6373 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, false, false, 6374 RTW89_SCAN_NULL_TIMEOUT); 6375 if (ret) 6376 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 6377 "scan send null-0 failed: %d\n", ret); 6378 } 6379 6380 rtwdev->scanning = false; 6381 rtw89_for_each_active_bb(rtwdev, bb) 6382 bb->dig.bypass_dig = true; 6383 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 6384 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->ips_work); 6385 } 6386 6387 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 6388 { 6389 const struct rtw89_chip_info *chip = rtwdev->chip; 6390 struct rtw89_hal *hal = &rtwdev->hal; 6391 int ret; 6392 u8 val2; 6393 u8 val; 6394 u8 cv; 6395 6396 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 6397 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 6398 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 6399 cv = CHIP_CAV; 6400 else 6401 cv = CHIP_CBV; 6402 } 6403 6404 hal->cv = cv; 6405 6406 if (rtw89_is_rtl885xb(rtwdev) || chip->chip_gen >= RTW89_CHIP_BE) { 6407 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 6408 if (ret) 6409 return; 6410 6411 hal->acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 6412 } 6413 6414 if (chip->chip_gen >= RTW89_CHIP_BE) { 6415 hal->cid = 6416 rtw89_read32_mask(rtwdev, R_BE_SYS_CHIPINFO, B_BE_HW_ID_MASK); 6417 6418 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CHIP_ID_L, &val); 6419 if (ret) 6420 return; 6421 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CHIP_ID_H, &val2); 6422 if (ret) 6423 return; 6424 6425 hal->aid = val | val2 << 8; 6426 } 6427 } 6428 6429 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 6430 { 6431 const struct rtw89_chip_info *chip = rtwdev->chip; 6432 6433 rtwdev->hal.support_cckpd = 6434 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 6435 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 6436 rtwdev->hal.support_igi = 6437 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 6438 6439 if (test_bit(RTW89_QUIRK_THERMAL_PROT_120C, rtwdev->quirks)) 6440 rtwdev->hal.thermal_prot_th = chip->thermal_th[1]; 6441 else if (test_bit(RTW89_QUIRK_THERMAL_PROT_110C, rtwdev->quirks)) 6442 rtwdev->hal.thermal_prot_th = chip->thermal_th[0]; 6443 else 6444 rtwdev->hal.thermal_prot_th = 0; 6445 } 6446 6447 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 6448 { 6449 const struct rtw89_chip_info *chip = rtwdev->chip; 6450 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 6451 struct rtw89_efuse *efuse = &rtwdev->efuse; 6452 const struct rtw89_rfe_parms *sel; 6453 u8 rfe_type = efuse->rfe_type; 6454 6455 if (!conf) { 6456 sel = chip->dflt_parms; 6457 goto out; 6458 } 6459 6460 while (conf->rfe_parms) { 6461 if (rfe_type == conf->rfe_type) { 6462 sel = conf->rfe_parms; 6463 goto out; 6464 } 6465 conf++; 6466 } 6467 6468 sel = chip->dflt_parms; 6469 6470 out: 6471 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel); 6472 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl); 6473 } 6474 6475 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6476 unsigned int link_id) 6477 { 6478 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 6479 u16 usable_links = ieee80211_vif_usable_links(vif); 6480 u16 active_links = vif->active_links; 6481 struct rtw89_vif_link *target; 6482 int ret; 6483 6484 lockdep_assert_wiphy(rtwdev->hw->wiphy); 6485 6486 if (unlikely(!ieee80211_vif_is_mld(vif))) 6487 return -EOPNOTSUPP; 6488 6489 if (unlikely(link_id >= IEEE80211_MLD_MAX_NUM_LINKS || 6490 !(usable_links & BIT(link_id)))) { 6491 rtw89_warn(rtwdev, "%s: link id %u is not usable\n", __func__, 6492 link_id); 6493 return -ENOLINK; 6494 } 6495 6496 if (active_links == BIT(link_id)) 6497 return 0; 6498 6499 rtw89_debug(rtwdev, RTW89_DBG_STATE, "%s: switch to link id %u MLSR\n", 6500 __func__, link_id); 6501 6502 rtw89_leave_lps(rtwdev); 6503 6504 ieee80211_stop_queues(rtwdev->hw); 6505 flush_work(&rtwdev->txq_work); 6506 6507 ret = ieee80211_set_active_links(vif, BIT(link_id)); 6508 if (ret) { 6509 rtw89_err(rtwdev, "%s: failed to work on link id %u\n", 6510 __func__, link_id); 6511 goto wake_queue; 6512 } 6513 6514 target = rtwvif->links[link_id]; 6515 if (unlikely(!target)) { 6516 rtw89_err(rtwdev, "%s: failed to confirm link id %u\n", 6517 __func__, link_id); 6518 6519 ieee80211_set_active_links(vif, active_links); 6520 ret = -EFAULT; 6521 goto wake_queue; 6522 } 6523 6524 if (RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw)) 6525 rtw89_chip_rfk_channel(rtwdev, target); 6526 6527 rtwvif->mlo_mode = RTW89_MLO_MODE_MLSR; 6528 6529 wake_queue: 6530 ieee80211_wake_queues(rtwdev->hw); 6531 6532 return ret; 6533 } 6534 6535 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 6536 { 6537 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6538 int ret; 6539 6540 ret = rtw89_mac_partial_init(rtwdev, false); 6541 if (ret) 6542 return ret; 6543 6544 ret = mac->parse_efuse_map(rtwdev); 6545 if (ret) 6546 return ret; 6547 6548 ret = mac->parse_phycap_map(rtwdev); 6549 if (ret) 6550 return ret; 6551 6552 ret = rtw89_mac_setup_phycap(rtwdev); 6553 if (ret) 6554 return ret; 6555 6556 rtw89_core_setup_phycap(rtwdev); 6557 6558 rtw89_hci_mac_pre_deinit(rtwdev); 6559 6560 return 0; 6561 } 6562 6563 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 6564 { 6565 rtw89_chip_fem_setup(rtwdev); 6566 6567 return 0; 6568 } 6569 6570 static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev) 6571 { 6572 return !!rtwdev->chip->rfkill_init; 6573 } 6574 6575 static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev) 6576 { 6577 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init; 6578 6579 rtw89_write16_mask(rtwdev, regs->pinmux.addr, 6580 regs->pinmux.mask, regs->pinmux.data); 6581 rtw89_write16_mask(rtwdev, regs->mode.addr, 6582 regs->mode.mask, regs->mode.data); 6583 } 6584 6585 static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev) 6586 { 6587 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get; 6588 6589 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask); 6590 } 6591 6592 static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev) 6593 { 6594 if (!rtw89_chip_has_rfkill(rtwdev)) 6595 return; 6596 6597 rtw89_core_rfkill_init(rtwdev); 6598 rtw89_core_rfkill_poll(rtwdev, true); 6599 wiphy_rfkill_start_polling(rtwdev->hw->wiphy); 6600 } 6601 6602 static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev) 6603 { 6604 if (!rtw89_chip_has_rfkill(rtwdev)) 6605 return; 6606 6607 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy); 6608 } 6609 6610 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force) 6611 { 6612 bool prev, blocked; 6613 6614 if (!rtw89_chip_has_rfkill(rtwdev)) 6615 return; 6616 6617 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 6618 blocked = rtw89_core_rfkill_get(rtwdev); 6619 6620 if (!force && prev == blocked) 6621 return; 6622 6623 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n", 6624 blocked ? "disable" : "enable"); 6625 6626 if (blocked) 6627 set_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 6628 else 6629 clear_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 6630 6631 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked); 6632 } 6633 6634 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 6635 { 6636 struct rtw89_efuse *efuse = &rtwdev->efuse; 6637 struct rtw89_hal *hal = &rtwdev->hal; 6638 int ret; 6639 6640 rtw89_read_chip_ver(rtwdev); 6641 6642 ret = rtw89_mac_pwr_on(rtwdev); 6643 if (ret) { 6644 rtw89_err(rtwdev, "failed to power on\n"); 6645 return ret; 6646 } 6647 6648 ret = rtw89_wait_firmware_completion(rtwdev); 6649 if (ret) { 6650 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 6651 goto out; 6652 } 6653 6654 ret = rtw89_fw_recognize(rtwdev); 6655 if (ret) { 6656 rtw89_err(rtwdev, "failed to recognize firmware\n"); 6657 goto out; 6658 } 6659 6660 ret = rtw89_chip_efuse_info_setup(rtwdev); 6661 if (ret) 6662 goto out; 6663 6664 ret = rtw89_fw_recognize_elements(rtwdev); 6665 if (ret) { 6666 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 6667 goto out; 6668 } 6669 6670 ret = rtw89_chip_board_info_setup(rtwdev); 6671 if (ret) 6672 goto out; 6673 6674 rtw89_core_setup_rfe_parms(rtwdev); 6675 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 6676 6677 rtw89_info(rtwdev, "chip info CID: %x, CV: %x, AID: %x, ACV: %x, RFE: %d\n", 6678 hal->cid, hal->cv, hal->aid, hal->acv, efuse->rfe_type); 6679 6680 out: 6681 rtw89_mac_pwr_off(rtwdev); 6682 6683 return ret; 6684 } 6685 EXPORT_SYMBOL(rtw89_chip_info_setup); 6686 6687 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 6688 struct rtw89_vif_link *rtwvif_link) 6689 { 6690 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6691 const struct rtw89_chip_info *chip = rtwdev->chip; 6692 struct ieee80211_bss_conf *bss_conf; 6693 6694 rcu_read_lock(); 6695 6696 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 6697 if (!bss_conf->he_support || !vif->cfg.assoc) { 6698 rcu_read_unlock(); 6699 return; 6700 } 6701 6702 rcu_read_unlock(); 6703 6704 if (chip->ops->set_txpwr_ul_tb_offset) 6705 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif_link->mac_idx); 6706 } 6707 6708 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 6709 { 6710 const struct rtw89_chip_info *chip = rtwdev->chip; 6711 u8 n = rtwdev->support_mlo ? chip->support_link_num : 1; 6712 struct ieee80211_hw *hw = rtwdev->hw; 6713 struct rtw89_efuse *efuse = &rtwdev->efuse; 6714 struct rtw89_hal *hal = &rtwdev->hal; 6715 int ret; 6716 int tx_headroom = IEEE80211_HT_CTL_LEN; 6717 6718 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 6719 tx_headroom += chip->txwd_body_size + chip->txwd_info_size; 6720 6721 hw->vif_data_size = struct_size_t(struct rtw89_vif, links_inst, n); 6722 hw->sta_data_size = struct_size_t(struct rtw89_sta, links_inst, n); 6723 hw->txq_data_size = sizeof(struct rtw89_txq); 6724 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 6725 6726 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 6727 6728 hw->extra_tx_headroom = tx_headroom; 6729 hw->queues = IEEE80211_NUM_ACS; 6730 hw->max_rx_aggregation_subframes = chip->max_rx_agg_num; 6731 hw->max_tx_aggregation_subframes = chip->max_tx_agg_num; 6732 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 6733 6734 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC | 6735 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 6736 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC; 6737 6738 ieee80211_hw_set(hw, SIGNAL_DBM); 6739 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 6740 ieee80211_hw_set(hw, MFP_CAPABLE); 6741 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 6742 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 6743 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 6744 ieee80211_hw_set(hw, TX_AMSDU); 6745 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 6746 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 6747 ieee80211_hw_set(hw, SUPPORTS_PS); 6748 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 6749 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 6750 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 6751 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 6752 ieee80211_hw_set(hw, CHANCTX_STA_CSA); 6753 6754 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 6755 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 6756 6757 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 6758 ieee80211_hw_set(hw, CONNECTION_MONITOR); 6759 6760 if (RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &rtwdev->fw)) 6761 ieee80211_hw_set(hw, AP_LINK_PS); 6762 6763 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 6764 BIT(NL80211_IFTYPE_AP) | 6765 BIT(NL80211_IFTYPE_P2P_CLIENT) | 6766 BIT(NL80211_IFTYPE_P2P_GO); 6767 6768 if (hal->ant_diversity) { 6769 hw->wiphy->available_antennas_tx = 0x3; 6770 hw->wiphy->available_antennas_rx = 0x3; 6771 } else { 6772 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 6773 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 6774 } 6775 6776 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 6777 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 6778 WIPHY_FLAG_AP_UAPSD | 6779 WIPHY_FLAG_HAS_CHANNEL_SWITCH | 6780 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK; 6781 6782 if (!chip->support_rnr) 6783 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ; 6784 6785 if (chip->chip_gen == RTW89_CHIP_BE) 6786 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT; 6787 6788 if (rtwdev->support_mlo) { 6789 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO; 6790 hw->wiphy->iftype_ext_capab = rtw89_iftypes_ext_capa; 6791 hw->wiphy->num_iftype_ext_capab = ARRAY_SIZE(rtw89_iftypes_ext_capa); 6792 } 6793 6794 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 6795 6796 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 6797 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 6798 6799 #ifdef CONFIG_PM 6800 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 6801 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 6802 #endif 6803 6804 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 6805 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 6806 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 6807 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 6808 hw->wiphy->max_remain_on_channel_duration = 1000; 6809 6810 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 6811 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 6812 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 6813 6814 ret = rtw89_core_set_supported_band(rtwdev); 6815 if (ret) { 6816 rtw89_err(rtwdev, "failed to set supported band\n"); 6817 return ret; 6818 } 6819 6820 ret = rtw89_regd_setup(rtwdev); 6821 if (ret) { 6822 rtw89_err(rtwdev, "failed to set up regd\n"); 6823 return ret; 6824 } 6825 6826 hw->wiphy->sar_capa = &rtw89_sar_capa; 6827 6828 ret = ieee80211_register_hw(hw); 6829 if (ret) { 6830 rtw89_err(rtwdev, "failed to register hw\n"); 6831 return ret; 6832 } 6833 6834 ret = rtw89_regd_init_hint(rtwdev); 6835 if (ret) { 6836 rtw89_err(rtwdev, "failed to init regd\n"); 6837 goto err_unregister_hw; 6838 } 6839 6840 rtw89_rfkill_polling_init(rtwdev); 6841 6842 return 0; 6843 6844 err_unregister_hw: 6845 ieee80211_unregister_hw(hw); 6846 6847 return ret; 6848 } 6849 6850 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 6851 { 6852 struct ieee80211_hw *hw = rtwdev->hw; 6853 6854 rtw89_rfkill_polling_deinit(rtwdev); 6855 ieee80211_unregister_hw(hw); 6856 } 6857 6858 int rtw89_core_register(struct rtw89_dev *rtwdev) 6859 { 6860 int ret; 6861 6862 ret = rtw89_core_register_hw(rtwdev); 6863 if (ret) { 6864 rtw89_err(rtwdev, "failed to register core hw\n"); 6865 return ret; 6866 } 6867 6868 rtw89_phy_dm_init_data(rtwdev); 6869 rtw89_debugfs_init(rtwdev); 6870 6871 return 0; 6872 } 6873 EXPORT_SYMBOL(rtw89_core_register); 6874 6875 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 6876 { 6877 rtw89_core_unregister_hw(rtwdev); 6878 6879 rtw89_debugfs_deinit(rtwdev); 6880 } 6881 EXPORT_SYMBOL(rtw89_core_unregister); 6882 6883 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 6884 u32 bus_data_size, 6885 const struct rtw89_chip_info *chip, 6886 const struct rtw89_chip_variant *variant) 6887 { 6888 struct rtw89_fw_info early_fw = {}; 6889 const struct firmware *firmware; 6890 struct ieee80211_hw *hw; 6891 struct rtw89_dev *rtwdev; 6892 struct ieee80211_ops *ops; 6893 u32 driver_data_size; 6894 int fw_format = -1; 6895 bool support_mlo; 6896 bool no_chanctx; 6897 6898 firmware = rtw89_early_fw_feature_recognize(device, chip, variant, 6899 &early_fw, &fw_format); 6900 6901 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 6902 if (!ops) 6903 goto err; 6904 6905 no_chanctx = chip->support_chanctx_num == 0 || 6906 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 6907 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 6908 6909 if (no_chanctx) { 6910 ops->add_chanctx = ieee80211_emulate_add_chanctx; 6911 ops->remove_chanctx = ieee80211_emulate_remove_chanctx; 6912 ops->change_chanctx = ieee80211_emulate_change_chanctx; 6913 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx; 6914 ops->assign_vif_chanctx = NULL; 6915 ops->unassign_vif_chanctx = NULL; 6916 ops->remain_on_channel = NULL; 6917 ops->cancel_remain_on_channel = NULL; 6918 } 6919 6920 if (!chip->support_noise) 6921 ops->get_survey = NULL; 6922 6923 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 6924 hw = ieee80211_alloc_hw(driver_data_size, ops); 6925 if (!hw) 6926 goto err; 6927 6928 /* Currently, our AP_LINK_PS handling only works for non-MLD softap 6929 * or MLD-single-link softap. If RTW89_MLD_NON_STA_LINK_NUM enlarges, 6930 * please tweak entire AP_LINKS_PS handling before supporting MLO. 6931 */ 6932 support_mlo = !no_chanctx && chip->support_link_num && 6933 RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &early_fw) && 6934 RTW89_MLD_NON_STA_LINK_NUM == 1; 6935 6936 hw->wiphy->iface_combinations = rtw89_iface_combs; 6937 6938 if (no_chanctx || chip->support_chanctx_num == 1) 6939 hw->wiphy->n_iface_combinations = 1; 6940 else 6941 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 6942 6943 rtwdev = hw->priv; 6944 rtwdev->hw = hw; 6945 rtwdev->dev = device; 6946 rtwdev->ops = ops; 6947 rtwdev->chip = chip; 6948 rtwdev->variant = variant; 6949 rtwdev->fw.req.firmware = firmware; 6950 rtwdev->fw.fw_format = fw_format; 6951 rtwdev->support_mlo = support_mlo; 6952 6953 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s chanctx\n", 6954 no_chanctx ? "without" : "with"); 6955 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s MLO cap\n", 6956 support_mlo ? "with" : "without"); 6957 6958 return rtwdev; 6959 6960 err: 6961 kfree(ops); 6962 release_firmware(firmware); 6963 return NULL; 6964 } 6965 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 6966 6967 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 6968 { 6969 kfree(rtwdev->ops); 6970 kfree(rtwdev->rfe_data); 6971 release_firmware(rtwdev->fw.req.firmware); 6972 ieee80211_free_hw(rtwdev->hw); 6973 } 6974 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 6975 6976 MODULE_AUTHOR("Realtek Corporation"); 6977 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 6978 MODULE_LICENSE("Dual BSD/GPL"); 6979