1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020, Intel Corporation
3 */
4
5 #include <linux/clk-provider.h>
6 #include <linux/pci.h>
7 #include <linux/dmi.h>
8 #include <linux/platform_data/x86/intel_pmc_ipc.h>
9 #include <asm/cpuid/api.h>
10 #include "dwmac-intel.h"
11 #include "dwmac4.h"
12 #include "stmmac.h"
13 #include "stmmac_ptp.h"
14
15 struct pmc_serdes_regs {
16 u8 index;
17 u32 val;
18 };
19
20 struct pmc_serdes_reg_info {
21 const struct pmc_serdes_regs *regs;
22 u8 num_regs;
23 };
24
25 struct intel_priv_data {
26 int mdio_adhoc_addr; /* mdio address for serdes & etc */
27 unsigned long crossts_adj;
28 bool is_pse;
29 const int *tsn_lane_regs;
30 int max_tsn_lane_regs;
31 struct pmc_serdes_reg_info pid_1g;
32 struct pmc_serdes_reg_info pid_2p5g;
33 };
34
35 /* This struct is used to associate PCI Function of MAC controller on a board,
36 * discovered via DMI, with the address of PHY connected to the MAC. The
37 * negative value of the address means that MAC controller is not connected
38 * with PHY.
39 */
40 struct stmmac_pci_func_data {
41 unsigned int func;
42 int phy_addr;
43 };
44
45 struct stmmac_pci_dmi_data {
46 const struct stmmac_pci_func_data *func;
47 size_t nfuncs;
48 };
49
50 struct stmmac_pci_info {
51 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
52 };
53
54 static const struct pmc_serdes_regs pid_modphy3_1g_regs[] = {
55 { PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_1G },
56 { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_1G },
57 { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_1G },
58 { PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_1G },
59 { PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_1G },
60 {}
61 };
62
63 static const struct pmc_serdes_regs pid_modphy3_2p5g_regs[] = {
64 { PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_2P5G },
65 { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_2P5G },
66 { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_2P5G },
67 { PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_2P5G },
68 { PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G },
69 {}
70 };
71
72 static const struct pmc_serdes_regs pid_modphy1_1g_regs[] = {
73 { PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_1G },
74 { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_1G },
75 { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_1G },
76 { PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_1G },
77 { PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_1G },
78 {}
79 };
80
81 static const struct pmc_serdes_regs pid_modphy1_2p5g_regs[] = {
82 { PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_2P5G },
83 { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_2P5G },
84 { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_2P5G },
85 { PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_2P5G },
86 { PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G },
87 {}
88 };
89
90 static const int ehl_tsn_lane_regs[] = {7, 8, 9, 10, 11};
91 static const int adln_tsn_lane_regs[] = {6};
92
stmmac_pci_find_phy_addr(struct pci_dev * pdev,const struct dmi_system_id * dmi_list)93 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
94 const struct dmi_system_id *dmi_list)
95 {
96 const struct stmmac_pci_func_data *func_data;
97 const struct stmmac_pci_dmi_data *dmi_data;
98 const struct dmi_system_id *dmi_id;
99 int func = PCI_FUNC(pdev->devfn);
100 size_t n;
101
102 dmi_id = dmi_first_match(dmi_list);
103 if (!dmi_id)
104 return -ENODEV;
105
106 dmi_data = dmi_id->driver_data;
107 func_data = dmi_data->func;
108
109 for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
110 if (func_data->func == func)
111 return func_data->phy_addr;
112
113 return -ENODEV;
114 }
115
serdes_status_poll(struct stmmac_priv * priv,int phyaddr,int phyreg,u32 mask,u32 val)116 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr,
117 int phyreg, u32 mask, u32 val)
118 {
119 unsigned int retries = 10;
120 int val_rd;
121
122 do {
123 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg);
124 if ((val_rd & mask) == (val & mask))
125 return 0;
126 udelay(POLL_DELAY_US);
127 } while (--retries);
128
129 return -ETIMEDOUT;
130 }
131
intel_serdes_powerup(struct net_device * ndev,void * priv_data)132 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
133 {
134 struct intel_priv_data *intel_priv = priv_data;
135 struct stmmac_priv *priv = netdev_priv(ndev);
136 int serdes_phy_addr = 0;
137 u32 data = 0;
138
139 if (!intel_priv->mdio_adhoc_addr)
140 return 0;
141
142 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
143
144 /* Set the serdes rate and the PCLK rate */
145 data = mdiobus_read(priv->mii, serdes_phy_addr,
146 SERDES_GCR0);
147
148 data &= ~SERDES_RATE_MASK;
149 data &= ~SERDES_PCLK_MASK;
150
151 if (priv->plat->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
152 data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT |
153 SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT;
154 else
155 data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT |
156 SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT;
157
158 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
159
160 /* assert clk_req */
161 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
162 data |= SERDES_PLL_CLK;
163 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
164
165 /* check for clk_ack assertion */
166 data = serdes_status_poll(priv, serdes_phy_addr,
167 SERDES_GSR0,
168 SERDES_PLL_CLK,
169 SERDES_PLL_CLK);
170
171 if (data) {
172 dev_err(priv->device, "Serdes PLL clk request timeout\n");
173 return data;
174 }
175
176 /* assert lane reset */
177 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
178 data |= SERDES_RST;
179 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
180
181 /* check for assert lane reset reflection */
182 data = serdes_status_poll(priv, serdes_phy_addr,
183 SERDES_GSR0,
184 SERDES_RST,
185 SERDES_RST);
186
187 if (data) {
188 dev_err(priv->device, "Serdes assert lane reset timeout\n");
189 return data;
190 }
191
192 /* move power state to P0 */
193 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
194
195 data &= ~SERDES_PWR_ST_MASK;
196 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
197
198 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
199
200 /* Check for P0 state */
201 data = serdes_status_poll(priv, serdes_phy_addr,
202 SERDES_GSR0,
203 SERDES_PWR_ST_MASK,
204 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT);
205
206 if (data) {
207 dev_err(priv->device, "Serdes power state P0 timeout.\n");
208 return data;
209 }
210
211 /* PSE only - ungate SGMII PHY Rx Clock */
212 if (intel_priv->is_pse)
213 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
214 0, SERDES_PHY_RX_CLK);
215
216 return 0;
217 }
218
intel_serdes_powerdown(struct net_device * ndev,void * intel_data)219 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
220 {
221 struct intel_priv_data *intel_priv = intel_data;
222 struct stmmac_priv *priv = netdev_priv(ndev);
223 int serdes_phy_addr = 0;
224 u32 data = 0;
225
226 if (!intel_priv->mdio_adhoc_addr)
227 return;
228
229 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
230
231 /* PSE only - gate SGMII PHY Rx Clock */
232 if (intel_priv->is_pse)
233 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
234 SERDES_PHY_RX_CLK, 0);
235
236 /* move power state to P3 */
237 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
238
239 data &= ~SERDES_PWR_ST_MASK;
240 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT;
241
242 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
243
244 /* Check for P3 state */
245 data = serdes_status_poll(priv, serdes_phy_addr,
246 SERDES_GSR0,
247 SERDES_PWR_ST_MASK,
248 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT);
249
250 if (data) {
251 dev_err(priv->device, "Serdes power state P3 timeout\n");
252 return;
253 }
254
255 /* de-assert clk_req */
256 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
257 data &= ~SERDES_PLL_CLK;
258 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
259
260 /* check for clk_ack de-assert */
261 data = serdes_status_poll(priv, serdes_phy_addr,
262 SERDES_GSR0,
263 SERDES_PLL_CLK,
264 (u32)~SERDES_PLL_CLK);
265
266 if (data) {
267 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n");
268 return;
269 }
270
271 /* de-assert lane reset */
272 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
273 data &= ~SERDES_RST;
274 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
275
276 /* check for de-assert lane reset reflection */
277 data = serdes_status_poll(priv, serdes_phy_addr,
278 SERDES_GSR0,
279 SERDES_RST,
280 (u32)~SERDES_RST);
281
282 if (data) {
283 dev_err(priv->device, "Serdes de-assert lane reset timeout\n");
284 return;
285 }
286 }
287
tgl_get_interfaces(struct stmmac_priv * priv,void * bsp_priv,unsigned long * interfaces)288 static void tgl_get_interfaces(struct stmmac_priv *priv, void *bsp_priv,
289 unsigned long *interfaces)
290 {
291 struct intel_priv_data *intel_priv = bsp_priv;
292 phy_interface_t interface;
293 int data;
294
295 /* Determine the link speed mode: 2.5Gbps/1Gbps */
296 data = mdiobus_read(priv->mii, intel_priv->mdio_adhoc_addr, SERDES_GCR);
297 if (data < 0)
298 return;
299
300 if (FIELD_GET(SERDES_LINK_MODE_MASK, data) == SERDES_LINK_MODE_2G5) {
301 dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n");
302 priv->plat->default_an_inband = false;
303 interface = PHY_INTERFACE_MODE_2500BASEX;
304 } else {
305 interface = PHY_INTERFACE_MODE_SGMII;
306 }
307
308 __set_bit(interface, interfaces);
309 priv->plat->phy_interface = interface;
310 }
311
312 /* Program PTP Clock Frequency for different variant of
313 * Intel mGBE that has slightly different GPO mapping
314 */
intel_mgbe_ptp_clk_freq_config(struct stmmac_priv * priv)315 static void intel_mgbe_ptp_clk_freq_config(struct stmmac_priv *priv)
316 {
317 struct intel_priv_data *intel_priv;
318 u32 gpio_value;
319
320 intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv;
321
322 gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS);
323
324 if (intel_priv->is_pse) {
325 /* For PSE GbE, use 200MHz */
326 gpio_value &= ~PSE_PTP_CLK_FREQ_MASK;
327 gpio_value |= PSE_PTP_CLK_FREQ_200MHZ;
328 } else {
329 /* For PCH GbE, use 200MHz */
330 gpio_value &= ~PCH_PTP_CLK_FREQ_MASK;
331 gpio_value |= PCH_PTP_CLK_FREQ_200MHZ;
332 }
333
334 writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS);
335 }
336
get_arttime(struct mii_bus * mii,int intel_adhoc_addr,u64 * art_time)337 static void get_arttime(struct mii_bus *mii, int intel_adhoc_addr,
338 u64 *art_time)
339 {
340 u64 ns;
341
342 ns = mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE3);
343 ns <<= GMAC4_ART_TIME_SHIFT;
344 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE2);
345 ns <<= GMAC4_ART_TIME_SHIFT;
346 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE1);
347 ns <<= GMAC4_ART_TIME_SHIFT;
348 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE0);
349
350 *art_time = ns;
351 }
352
stmmac_cross_ts_isr(struct stmmac_priv * priv)353 static int stmmac_cross_ts_isr(struct stmmac_priv *priv)
354 {
355 return (readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE);
356 }
357
intel_crosststamp(ktime_t * device,struct system_counterval_t * system,void * ctx)358 static int intel_crosststamp(ktime_t *device,
359 struct system_counterval_t *system,
360 void *ctx)
361 {
362 struct intel_priv_data *intel_priv;
363
364 struct stmmac_priv *priv = (struct stmmac_priv *)ctx;
365 void __iomem *ptpaddr = priv->ptpaddr;
366 void __iomem *ioaddr = priv->hw->pcsr;
367 unsigned long flags;
368 u64 art_time = 0;
369 u64 ptp_time = 0;
370 u32 num_snapshot;
371 u32 gpio_value;
372 u32 acr_value;
373 int i;
374
375 intel_priv = priv->plat->bsp_priv;
376
377 /* Both internal crosstimestamping and external triggered event
378 * timestamping cannot be run concurrently.
379 */
380 if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN)
381 return -EBUSY;
382
383 priv->plat->flags |= STMMAC_FLAG_INT_SNAPSHOT_EN;
384
385 mutex_lock(&priv->aux_ts_lock);
386 /* Enable Internal snapshot trigger */
387 acr_value = readl(ptpaddr + PTP_ACR);
388 acr_value &= ~PTP_ACR_MASK;
389 switch (priv->plat->int_snapshot_num) {
390 case AUX_SNAPSHOT0:
391 acr_value |= PTP_ACR_ATSEN0;
392 break;
393 case AUX_SNAPSHOT1:
394 acr_value |= PTP_ACR_ATSEN1;
395 break;
396 case AUX_SNAPSHOT2:
397 acr_value |= PTP_ACR_ATSEN2;
398 break;
399 case AUX_SNAPSHOT3:
400 acr_value |= PTP_ACR_ATSEN3;
401 break;
402 default:
403 mutex_unlock(&priv->aux_ts_lock);
404 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN;
405 return -EINVAL;
406 }
407 writel(acr_value, ptpaddr + PTP_ACR);
408
409 /* Clear FIFO */
410 acr_value = readl(ptpaddr + PTP_ACR);
411 acr_value |= PTP_ACR_ATSFC;
412 writel(acr_value, ptpaddr + PTP_ACR);
413 /* Release the mutex */
414 mutex_unlock(&priv->aux_ts_lock);
415
416 /* Trigger Internal snapshot signal
417 * Create a rising edge by just toggle the GPO1 to low
418 * and back to high.
419 */
420 gpio_value = readl(ioaddr + GMAC_GPIO_STATUS);
421 gpio_value &= ~GMAC_GPO1;
422 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
423 gpio_value |= GMAC_GPO1;
424 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
425
426 /* Time sync done Indication - Interrupt method */
427 if (!wait_event_interruptible_timeout(priv->tstamp_busy_wait,
428 stmmac_cross_ts_isr(priv),
429 HZ / 100)) {
430 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN;
431 return -ETIMEDOUT;
432 }
433
434 *system = (struct system_counterval_t) {
435 .cycles = 0,
436 .cs_id = CSID_X86_ART,
437 .use_nsecs = false,
438 };
439
440 num_snapshot = (readl(ioaddr + GMAC_TIMESTAMP_STATUS) &
441 GMAC_TIMESTAMP_ATSNS_MASK) >>
442 GMAC_TIMESTAMP_ATSNS_SHIFT;
443
444 /* Repeat until the timestamps are from the FIFO last segment */
445 for (i = 0; i < num_snapshot; i++) {
446 read_lock_irqsave(&priv->ptp_lock, flags);
447 stmmac_get_ptptime(priv, ptpaddr, &ptp_time);
448 *device = ns_to_ktime(ptp_time);
449 read_unlock_irqrestore(&priv->ptp_lock, flags);
450 get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time);
451 system->cycles = art_time;
452 }
453
454 system->cycles *= intel_priv->crossts_adj;
455
456 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN;
457
458 return 0;
459 }
460
intel_mgbe_pse_crossts_adj(struct intel_priv_data * intel_priv,int base)461 static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv,
462 int base)
463 {
464 if (boot_cpu_has(X86_FEATURE_ART)) {
465 unsigned int art_freq;
466
467 /* On systems that support ART, ART frequency can be obtained
468 * from ECX register of CPUID leaf (0x15).
469 */
470 art_freq = cpuid_ecx(ART_CPUID_LEAF);
471 do_div(art_freq, base);
472 intel_priv->crossts_adj = art_freq;
473 }
474 }
475
intel_tsn_lane_is_available(struct net_device * ndev,struct intel_priv_data * intel_priv)476 static int intel_tsn_lane_is_available(struct net_device *ndev,
477 struct intel_priv_data *intel_priv)
478 {
479 struct stmmac_priv *priv = netdev_priv(ndev);
480 struct pmc_ipc_cmd tmp = {};
481 struct pmc_ipc_rbuf rbuf = {};
482 int ret = 0, i, j;
483 const int max_fia_regs = 5;
484
485 tmp.cmd = IPC_SOC_REGISTER_ACCESS;
486 tmp.sub_cmd = IPC_SOC_SUB_CMD_READ;
487
488 for (i = 0; i < max_fia_regs; i++) {
489 tmp.wbuf[0] = R_PCH_FIA_15_PCR_LOS1_REG_BASE + i;
490
491 ret = intel_pmc_ipc(&tmp, &rbuf);
492 if (ret < 0) {
493 netdev_info(priv->dev, "Failed to read from PMC.\n");
494 return ret;
495 }
496
497 for (j = 0; j <= intel_priv->max_tsn_lane_regs; j++)
498 if ((rbuf.buf[0] >>
499 (4 * (intel_priv->tsn_lane_regs[j] % 8)) &
500 B_PCH_FIA_PCR_L0O) == 0xB)
501 return 0;
502 }
503
504 return -EINVAL;
505 }
506
intel_set_reg_access(const struct pmc_serdes_regs * regs,int max_regs)507 static int intel_set_reg_access(const struct pmc_serdes_regs *regs, int max_regs)
508 {
509 int ret = 0, i;
510
511 for (i = 0; i < max_regs; i++) {
512 struct pmc_ipc_cmd tmp = {};
513 struct pmc_ipc_rbuf rbuf = {};
514
515 tmp.cmd = IPC_SOC_REGISTER_ACCESS;
516 tmp.sub_cmd = IPC_SOC_SUB_CMD_WRITE;
517 tmp.wbuf[0] = (u32)regs[i].index;
518 tmp.wbuf[1] = regs[i].val;
519
520 ret = intel_pmc_ipc(&tmp, &rbuf);
521 if (ret < 0)
522 return ret;
523 }
524
525 return ret;
526 }
527
528 /*
529 * Return true if the SerDes lane rate must change to serve @interface.
530 * If the current rate cannot be determined, reconfigure as before.
531 */
intel_serdes_needs_reconfig(struct stmmac_priv * priv,struct intel_priv_data * intel_priv,phy_interface_t interface)532 static bool intel_serdes_needs_reconfig(struct stmmac_priv *priv,
533 struct intel_priv_data *intel_priv,
534 phy_interface_t interface)
535 {
536 u32 cur_rate, want_rate;
537 int data;
538
539 if (!intel_priv->mdio_adhoc_addr)
540 return true;
541
542 data = mdiobus_read(priv->mii, intel_priv->mdio_adhoc_addr,
543 SERDES_GCR0);
544 if (data < 0)
545 return true;
546
547 cur_rate = (data & SERDES_RATE_MASK) >> SERDES_RATE_PCIE_SHIFT;
548 want_rate = interface == PHY_INTERFACE_MODE_2500BASEX ?
549 SERDES_RATE_PCIE_GEN2 : SERDES_RATE_PCIE_GEN1;
550
551 return cur_rate != want_rate;
552 }
553
intel_mac_finish(struct net_device * ndev,void * intel_data,unsigned int mode,phy_interface_t interface)554 static int intel_mac_finish(struct net_device *ndev,
555 void *intel_data,
556 unsigned int mode,
557 phy_interface_t interface)
558 {
559 struct intel_priv_data *intel_priv = intel_data;
560 struct stmmac_priv *priv = netdev_priv(ndev);
561 const struct pmc_serdes_regs *regs;
562 int max_regs = 0;
563 int ret = 0;
564
565 if (!intel_serdes_needs_reconfig(priv, intel_priv, interface)) {
566 priv->plat->phy_interface = interface;
567 return 0;
568 }
569
570 ret = intel_tsn_lane_is_available(ndev, intel_priv);
571 if (ret < 0) {
572 netdev_info(priv->dev, "No TSN lane available to set the registers.\n");
573 return ret;
574 }
575
576 if (interface == PHY_INTERFACE_MODE_2500BASEX) {
577 regs = intel_priv->pid_2p5g.regs;
578 max_regs = intel_priv->pid_2p5g.num_regs;
579 } else {
580 regs = intel_priv->pid_1g.regs;
581 max_regs = intel_priv->pid_1g.num_regs;
582 }
583
584 ret = intel_set_reg_access(regs, max_regs);
585 if (ret < 0)
586 return ret;
587
588 priv->plat->phy_interface = interface;
589
590 intel_serdes_powerdown(ndev, intel_priv);
591 intel_serdes_powerup(ndev, intel_priv);
592
593 return ret;
594 }
595
common_default_data(struct plat_stmmacenet_data * plat)596 static void common_default_data(struct plat_stmmacenet_data *plat)
597 {
598 /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
599 plat->clk_csr = STMMAC_CSR_20_35M;
600 plat->core_type = DWMAC_CORE_GMAC;
601 plat->force_sf_dma_mode = true;
602
603 plat->mdio_bus_data->needs_reset = true;
604 }
605
intel_mgbe_select_pcs(struct stmmac_priv * priv,phy_interface_t interface)606 static struct phylink_pcs *intel_mgbe_select_pcs(struct stmmac_priv *priv,
607 phy_interface_t interface)
608 {
609 /* plat->mdio_bus_data->has_xpcs has been set true, so there
610 * should always be an XPCS. The original code would always
611 * return this if present.
612 */
613 return xpcs_to_phylink_pcs(priv->hw->xpcs);
614 }
615
intel_mgbe_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)616 static int intel_mgbe_common_data(struct pci_dev *pdev,
617 struct plat_stmmacenet_data *plat)
618 {
619 struct fwnode_handle *fwnode;
620 char clk_name[20];
621 int ret;
622 int i;
623
624 plat->provide_bus_info = true;
625 plat->phy_addr = -1;
626 plat->clk_csr = STMMAC_CSR_250_300M;
627 plat->core_type = DWMAC_CORE_GMAC4;
628 plat->force_sf_dma_mode = 0;
629 plat->flags |= (STMMAC_FLAG_TSO_EN | STMMAC_FLAG_SPH_DISABLE);
630
631 /* Multiplying factor to the clk_eee_i clock time
632 * period to make it closer to 100 ns. This value
633 * should be programmed such that the clk_eee_time_period *
634 * (MULT_FACT_100NS + 1) should be within 80 ns to 120 ns
635 * clk_eee frequency is 19.2Mhz
636 * clk_eee_time_period is 52ns
637 * 52ns * (1 + 1) = 104ns
638 * MULT_FACT_100NS = 1
639 */
640 plat->mult_fact_100ns = 1;
641
642 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
643
644 for (i = 0; i < plat->rx_queues_to_use; i++)
645 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
646
647 for (i = 0; i < plat->tx_queues_to_use; i++) {
648 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
649
650 /* Default TX Q0 to use TSO and rest TXQ for TBS */
651 if (i > 0)
652 plat->tx_queues_cfg[i].tbs_en = 1;
653 }
654
655 /* FIFO size is 4096 bytes for 1 tx/rx queue */
656 plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
657 plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
658
659 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
660 plat->tx_queues_cfg[0].weight = 0x09;
661 plat->tx_queues_cfg[1].weight = 0x0A;
662 plat->tx_queues_cfg[2].weight = 0x0B;
663 plat->tx_queues_cfg[3].weight = 0x0C;
664 plat->tx_queues_cfg[4].weight = 0x0D;
665 plat->tx_queues_cfg[5].weight = 0x0E;
666 plat->tx_queues_cfg[6].weight = 0x0F;
667 plat->tx_queues_cfg[7].weight = 0x10;
668
669 plat->dma_cfg->pbl = 32;
670 plat->dma_cfg->pblx8 = true;
671 plat->dma_cfg->aal = 0;
672 plat->dma_cfg->dche = true;
673
674 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
675 GFP_KERNEL);
676 if (!plat->axi)
677 return -ENOMEM;
678
679 plat->axi->axi_lpi_en = 0;
680 plat->axi->axi_xit_frm = 0;
681 plat->axi->axi_wr_osr_lmt = 1;
682 plat->axi->axi_rd_osr_lmt = 1;
683 plat->axi->axi_blen_regval = DMA_AXI_BLEN4 | DMA_AXI_BLEN8 |
684 DMA_AXI_BLEN16;
685
686 plat->ptp_max_adj = plat->clk_ptp_rate;
687
688 /* Set system clock */
689 sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev));
690
691 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
692 clk_name, NULL, 0,
693 plat->clk_ptp_rate);
694
695 if (IS_ERR(plat->stmmac_clk)) {
696 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
697 plat->stmmac_clk = NULL;
698 }
699
700 ret = clk_prepare_enable(plat->stmmac_clk);
701 if (ret) {
702 clk_unregister_fixed_rate(plat->stmmac_clk);
703 return ret;
704 }
705
706 plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config;
707
708 plat->flags |= STMMAC_FLAG_VLAN_FAIL_Q_EN;
709
710 /* Use the last Rx queue */
711 plat->vlan_fail_q = plat->rx_queues_to_use - 1;
712
713 /* For fixed-link setup, we allow phy-mode setting */
714 fwnode = dev_fwnode(&pdev->dev);
715 if (fwnode) {
716 int phy_mode;
717
718 /* "phy-mode" setting is optional. If it is set,
719 * we allow either sgmii or 1000base-x for now.
720 */
721 phy_mode = fwnode_get_phy_mode(fwnode);
722 if (phy_mode >= 0) {
723 if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
724 phy_mode == PHY_INTERFACE_MODE_1000BASEX)
725 plat->phy_interface = phy_mode;
726 else
727 dev_warn(&pdev->dev, "Invalid phy-mode\n");
728 }
729 }
730
731 /* Intel mgbe SGMII interface uses pcs-xcps */
732 if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII ||
733 plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
734 plat->mdio_bus_data->pcs_mask = BIT_U32(INTEL_MGBE_XPCS_ADDR);
735 plat->default_an_inband = true;
736 plat->select_pcs = intel_mgbe_select_pcs;
737 }
738
739 /* Ensure mdio bus scan skips intel serdes and pcs-xpcs */
740 plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR;
741 plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR;
742
743 plat->int_snapshot_num = AUX_SNAPSHOT1;
744
745 if (boot_cpu_has(X86_FEATURE_ART))
746 plat->crosststamp = intel_crosststamp;
747
748 plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN;
749
750 /* Setup MSI vector offset specific to Intel mGbE controller */
751 plat->msi_mac_vec = 29;
752 plat->msi_sfty_ce_vec = 27;
753 plat->msi_sfty_ue_vec = 26;
754 plat->msi_rx_base_vec = 0;
755 plat->msi_tx_base_vec = 1;
756
757 return 0;
758 }
759
ehl_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)760 static int ehl_common_data(struct pci_dev *pdev,
761 struct plat_stmmacenet_data *plat)
762 {
763 struct intel_priv_data *intel_priv = plat->bsp_priv;
764
765 plat->rx_queues_to_use = 8;
766 plat->tx_queues_to_use = 8;
767 plat->flags |= STMMAC_FLAG_USE_PHY_WOL;
768 plat->flags |= STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY;
769
770 plat->safety_feat_cfg->tsoee = 1;
771 plat->safety_feat_cfg->mrxpee = 1;
772 plat->safety_feat_cfg->mestee = 1;
773 plat->safety_feat_cfg->mrxee = 1;
774 plat->safety_feat_cfg->mtxee = 1;
775 plat->safety_feat_cfg->epsi = 0;
776 plat->safety_feat_cfg->edpp = 0;
777 plat->safety_feat_cfg->prtyen = 0;
778 plat->safety_feat_cfg->tmouten = 0;
779
780 intel_priv->tsn_lane_regs = ehl_tsn_lane_regs;
781 intel_priv->max_tsn_lane_regs = ARRAY_SIZE(ehl_tsn_lane_regs);
782
783 return intel_mgbe_common_data(pdev, plat);
784 }
785
ehl_sgmii_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)786 static int ehl_sgmii_data(struct pci_dev *pdev,
787 struct plat_stmmacenet_data *plat)
788 {
789 struct intel_priv_data *intel_priv = plat->bsp_priv;
790
791 plat->bus_id = 1;
792 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
793 plat->serdes_powerup = intel_serdes_powerup;
794 plat->serdes_powerdown = intel_serdes_powerdown;
795 plat->mac_finish = intel_mac_finish;
796 plat->clk_ptp_rate = 204800000;
797
798 intel_priv->pid_1g.regs = pid_modphy3_1g_regs;
799 intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy3_1g_regs);
800 intel_priv->pid_2p5g.regs = pid_modphy3_2p5g_regs;
801 intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy3_2p5g_regs);
802
803 return ehl_common_data(pdev, plat);
804 }
805
806 static struct stmmac_pci_info ehl_sgmii1g_info = {
807 .setup = ehl_sgmii_data,
808 };
809
ehl_rgmii_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)810 static int ehl_rgmii_data(struct pci_dev *pdev,
811 struct plat_stmmacenet_data *plat)
812 {
813 plat->bus_id = 1;
814 plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
815
816 plat->clk_ptp_rate = 204800000;
817
818 return ehl_common_data(pdev, plat);
819 }
820
821 static struct stmmac_pci_info ehl_rgmii1g_info = {
822 .setup = ehl_rgmii_data,
823 };
824
ehl_pse0_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)825 static int ehl_pse0_common_data(struct pci_dev *pdev,
826 struct plat_stmmacenet_data *plat)
827 {
828 struct intel_priv_data *intel_priv = plat->bsp_priv;
829
830 intel_priv->is_pse = true;
831 plat->bus_id = 2;
832 plat->host_dma_width = 32;
833
834 plat->clk_ptp_rate = 200000000;
835
836 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
837
838 return ehl_common_data(pdev, plat);
839 }
840
ehl_pse0_rgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)841 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
842 struct plat_stmmacenet_data *plat)
843 {
844 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
845 return ehl_pse0_common_data(pdev, plat);
846 }
847
848 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {
849 .setup = ehl_pse0_rgmii1g_data,
850 };
851
ehl_pse0_sgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)852 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
853 struct plat_stmmacenet_data *plat)
854 {
855 struct intel_priv_data *intel_priv = plat->bsp_priv;
856
857 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
858 plat->serdes_powerup = intel_serdes_powerup;
859 plat->serdes_powerdown = intel_serdes_powerdown;
860 plat->mac_finish = intel_mac_finish;
861
862 intel_priv->pid_1g.regs = pid_modphy1_1g_regs;
863 intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy1_1g_regs);
864 intel_priv->pid_2p5g.regs = pid_modphy1_2p5g_regs;
865 intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy1_2p5g_regs);
866
867 return ehl_pse0_common_data(pdev, plat);
868 }
869
870 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = {
871 .setup = ehl_pse0_sgmii1g_data,
872 };
873
ehl_pse1_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)874 static int ehl_pse1_common_data(struct pci_dev *pdev,
875 struct plat_stmmacenet_data *plat)
876 {
877 struct intel_priv_data *intel_priv = plat->bsp_priv;
878
879 intel_priv->is_pse = true;
880 plat->bus_id = 3;
881 plat->host_dma_width = 32;
882
883 plat->clk_ptp_rate = 200000000;
884
885 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
886
887 return ehl_common_data(pdev, plat);
888 }
889
ehl_pse1_rgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)890 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
891 struct plat_stmmacenet_data *plat)
892 {
893 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
894 return ehl_pse1_common_data(pdev, plat);
895 }
896
897 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {
898 .setup = ehl_pse1_rgmii1g_data,
899 };
900
ehl_pse1_sgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)901 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
902 struct plat_stmmacenet_data *plat)
903 {
904 struct intel_priv_data *intel_priv = plat->bsp_priv;
905
906 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
907 plat->serdes_powerup = intel_serdes_powerup;
908 plat->serdes_powerdown = intel_serdes_powerdown;
909 plat->mac_finish = intel_mac_finish;
910
911 intel_priv->pid_1g.regs = pid_modphy1_1g_regs;
912 intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy1_1g_regs);
913 intel_priv->pid_2p5g.regs = pid_modphy1_2p5g_regs;
914 intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy1_2p5g_regs);
915
916 return ehl_pse1_common_data(pdev, plat);
917 }
918
919 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = {
920 .setup = ehl_pse1_sgmii1g_data,
921 };
922
tgl_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)923 static int tgl_common_data(struct pci_dev *pdev,
924 struct plat_stmmacenet_data *plat)
925 {
926 plat->rx_queues_to_use = 6;
927 plat->tx_queues_to_use = 4;
928 plat->clk_ptp_rate = 204800000;
929 plat->get_interfaces = tgl_get_interfaces;
930
931 plat->safety_feat_cfg->tsoee = 1;
932 plat->safety_feat_cfg->mrxpee = 0;
933 plat->safety_feat_cfg->mestee = 1;
934 plat->safety_feat_cfg->mrxee = 1;
935 plat->safety_feat_cfg->mtxee = 1;
936 plat->safety_feat_cfg->epsi = 0;
937 plat->safety_feat_cfg->edpp = 0;
938 plat->safety_feat_cfg->prtyen = 0;
939 plat->safety_feat_cfg->tmouten = 0;
940
941 return intel_mgbe_common_data(pdev, plat);
942 }
943
tgl_sgmii_phy0_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)944 static int tgl_sgmii_phy0_data(struct pci_dev *pdev,
945 struct plat_stmmacenet_data *plat)
946 {
947 plat->bus_id = 1;
948 plat->serdes_powerup = intel_serdes_powerup;
949 plat->serdes_powerdown = intel_serdes_powerdown;
950 return tgl_common_data(pdev, plat);
951 }
952
953 static struct stmmac_pci_info tgl_sgmii1g_phy0_info = {
954 .setup = tgl_sgmii_phy0_data,
955 };
956
tgl_sgmii_phy1_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)957 static int tgl_sgmii_phy1_data(struct pci_dev *pdev,
958 struct plat_stmmacenet_data *plat)
959 {
960 plat->bus_id = 2;
961 plat->serdes_powerup = intel_serdes_powerup;
962 plat->serdes_powerdown = intel_serdes_powerdown;
963 return tgl_common_data(pdev, plat);
964 }
965
966 static struct stmmac_pci_info tgl_sgmii1g_phy1_info = {
967 .setup = tgl_sgmii_phy1_data,
968 };
969
adls_sgmii_phy0_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)970 static int adls_sgmii_phy0_data(struct pci_dev *pdev,
971 struct plat_stmmacenet_data *plat)
972 {
973 plat->bus_id = 1;
974
975 /* SerDes power up and power down are done in BIOS for ADL */
976
977 return tgl_common_data(pdev, plat);
978 }
979
980 static struct stmmac_pci_info adls_sgmii1g_phy0_info = {
981 .setup = adls_sgmii_phy0_data,
982 };
983
adls_sgmii_phy1_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)984 static int adls_sgmii_phy1_data(struct pci_dev *pdev,
985 struct plat_stmmacenet_data *plat)
986 {
987 plat->bus_id = 2;
988
989 /* SerDes power up and power down are done in BIOS for ADL */
990
991 return tgl_common_data(pdev, plat);
992 }
993
994 static struct stmmac_pci_info adls_sgmii1g_phy1_info = {
995 .setup = adls_sgmii_phy1_data,
996 };
997
adln_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)998 static int adln_common_data(struct pci_dev *pdev,
999 struct plat_stmmacenet_data *plat)
1000 {
1001 struct intel_priv_data *intel_priv = plat->bsp_priv;
1002
1003 plat->rx_queues_to_use = 6;
1004 plat->tx_queues_to_use = 4;
1005 plat->clk_ptp_rate = 204800000;
1006
1007 plat->safety_feat_cfg->tsoee = 1;
1008 plat->safety_feat_cfg->mrxpee = 0;
1009 plat->safety_feat_cfg->mestee = 1;
1010 plat->safety_feat_cfg->mrxee = 1;
1011 plat->safety_feat_cfg->mtxee = 1;
1012 plat->safety_feat_cfg->epsi = 0;
1013 plat->safety_feat_cfg->edpp = 0;
1014 plat->safety_feat_cfg->prtyen = 0;
1015 plat->safety_feat_cfg->tmouten = 0;
1016
1017 intel_priv->tsn_lane_regs = adln_tsn_lane_regs;
1018 intel_priv->max_tsn_lane_regs = ARRAY_SIZE(adln_tsn_lane_regs);
1019
1020 return intel_mgbe_common_data(pdev, plat);
1021 }
1022
adln_sgmii_phy0_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)1023 static int adln_sgmii_phy0_data(struct pci_dev *pdev,
1024 struct plat_stmmacenet_data *plat)
1025 {
1026 struct intel_priv_data *intel_priv = plat->bsp_priv;
1027
1028 plat->bus_id = 1;
1029 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
1030 plat->serdes_powerup = intel_serdes_powerup;
1031 plat->serdes_powerdown = intel_serdes_powerdown;
1032 plat->mac_finish = intel_mac_finish;
1033
1034 intel_priv->pid_1g.regs = pid_modphy1_1g_regs;
1035 intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy1_1g_regs);
1036 intel_priv->pid_2p5g.regs = pid_modphy1_2p5g_regs;
1037 intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy1_2p5g_regs);
1038
1039 return adln_common_data(pdev, plat);
1040 }
1041
1042 static struct stmmac_pci_info adln_sgmii1g_phy0_info = {
1043 .setup = adln_sgmii_phy0_data,
1044 };
1045
1046 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
1047 {
1048 .func = 6,
1049 .phy_addr = 1,
1050 },
1051 };
1052
1053 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
1054 .func = galileo_stmmac_func_data,
1055 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
1056 };
1057
1058 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
1059 {
1060 .func = 6,
1061 .phy_addr = 1,
1062 },
1063 {
1064 .func = 7,
1065 .phy_addr = 1,
1066 },
1067 };
1068
1069 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
1070 .func = iot2040_stmmac_func_data,
1071 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
1072 };
1073
1074 static const struct dmi_system_id quark_pci_dmi[] = {
1075 {
1076 .matches = {
1077 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
1078 },
1079 .driver_data = (void *)&galileo_stmmac_dmi_data,
1080 },
1081 {
1082 .matches = {
1083 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
1084 },
1085 .driver_data = (void *)&galileo_stmmac_dmi_data,
1086 },
1087 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040.
1088 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
1089 * has only one pci network device while other asset tags are
1090 * for IOT2040 which has two.
1091 */
1092 {
1093 .matches = {
1094 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
1095 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
1096 "6ES7647-0AA00-0YA2"),
1097 },
1098 .driver_data = (void *)&galileo_stmmac_dmi_data,
1099 },
1100 {
1101 .matches = {
1102 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
1103 },
1104 .driver_data = (void *)&iot2040_stmmac_dmi_data,
1105 },
1106 {}
1107 };
1108
quark_default_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)1109 static int quark_default_data(struct pci_dev *pdev,
1110 struct plat_stmmacenet_data *plat)
1111 {
1112 int ret;
1113
1114 /* Set common default data first */
1115 common_default_data(plat);
1116
1117 /* Refuse to load the driver and register net device if MAC controller
1118 * does not connect to any PHY interface.
1119 */
1120 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
1121 if (ret < 0) {
1122 /* Return error to the caller on DMI enabled boards. */
1123 if (dmi_get_system_info(DMI_BOARD_NAME))
1124 return ret;
1125
1126 /* Galileo boards with old firmware don't support DMI. We always
1127 * use 1 here as PHY address, so at least the first found MAC
1128 * controller would be probed.
1129 */
1130 ret = 1;
1131 }
1132
1133 plat->bus_id = pci_dev_id(pdev);
1134 plat->phy_addr = ret;
1135 plat->phy_interface = PHY_INTERFACE_MODE_RMII;
1136
1137 plat->dma_cfg->pbl = 16;
1138 plat->dma_cfg->pblx8 = true;
1139 plat->dma_cfg->fixed_burst = true;
1140 /* AXI (TODO) */
1141
1142 return 0;
1143 }
1144
1145 static const struct stmmac_pci_info quark_info = {
1146 .setup = quark_default_data,
1147 };
1148
stmmac_config_single_msi(struct pci_dev * pdev,struct plat_stmmacenet_data * plat,struct stmmac_resources * res)1149 static int stmmac_config_single_msi(struct pci_dev *pdev,
1150 struct plat_stmmacenet_data *plat,
1151 struct stmmac_resources *res)
1152 {
1153 int ret;
1154
1155 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1156 if (ret < 0) {
1157 dev_info(&pdev->dev, "%s: Single IRQ enablement failed\n",
1158 __func__);
1159 return ret;
1160 }
1161
1162 res->irq = pci_irq_vector(pdev, 0);
1163 res->wol_irq = res->irq;
1164 plat->flags &= ~STMMAC_FLAG_MULTI_MSI_EN;
1165 dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n",
1166 __func__);
1167
1168 return 0;
1169 }
1170
stmmac_config_multi_msi(struct pci_dev * pdev,struct plat_stmmacenet_data * plat,struct stmmac_resources * res)1171 static int stmmac_config_multi_msi(struct pci_dev *pdev,
1172 struct plat_stmmacenet_data *plat,
1173 struct stmmac_resources *res)
1174 {
1175 int ret;
1176 int i;
1177
1178 if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX ||
1179 plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) {
1180 dev_info(&pdev->dev, "%s: Invalid RX & TX vector defined\n",
1181 __func__);
1182 return -1;
1183 }
1184
1185 ret = pci_alloc_irq_vectors(pdev, 2, STMMAC_MSI_VEC_MAX,
1186 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1187 if (ret < 0) {
1188 dev_info(&pdev->dev, "%s: multi MSI enablement failed\n",
1189 __func__);
1190 return ret;
1191 }
1192
1193 /* For RX MSI */
1194 for (i = 0; i < plat->rx_queues_to_use; i++) {
1195 res->rx_irq[i] = pci_irq_vector(pdev,
1196 plat->msi_rx_base_vec + i * 2);
1197 }
1198
1199 /* For TX MSI */
1200 for (i = 0; i < plat->tx_queues_to_use; i++) {
1201 res->tx_irq[i] = pci_irq_vector(pdev,
1202 plat->msi_tx_base_vec + i * 2);
1203 }
1204
1205 if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX)
1206 res->irq = pci_irq_vector(pdev, plat->msi_mac_vec);
1207 if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX)
1208 res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec);
1209 if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX)
1210 res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec);
1211 if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX)
1212 res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec);
1213
1214 plat->flags |= STMMAC_FLAG_MULTI_MSI_EN;
1215 dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__);
1216
1217 return 0;
1218 }
1219
intel_eth_pci_suspend(struct device * dev,void * bsp_priv)1220 static int intel_eth_pci_suspend(struct device *dev, void *bsp_priv)
1221 {
1222 struct pci_dev *pdev = to_pci_dev(dev);
1223 int ret;
1224
1225 ret = pci_save_state(pdev);
1226 if (ret)
1227 return ret;
1228
1229 pci_wake_from_d3(pdev, true);
1230 pci_set_power_state(pdev, PCI_D3hot);
1231 return 0;
1232 }
1233
intel_eth_pci_resume(struct device * dev,void * bsp_priv)1234 static int intel_eth_pci_resume(struct device *dev, void *bsp_priv)
1235 {
1236 struct pci_dev *pdev = to_pci_dev(dev);
1237 int ret;
1238
1239 pci_restore_state(pdev);
1240 pci_set_power_state(pdev, PCI_D0);
1241
1242 ret = pcim_enable_device(pdev);
1243 if (ret)
1244 return ret;
1245
1246 pci_set_master(pdev);
1247
1248 return 0;
1249 }
1250
1251 /**
1252 * intel_eth_pci_probe
1253 *
1254 * @pdev: pci device pointer
1255 * @id: pointer to table of device id/id's.
1256 *
1257 * Description: This probing function gets called for all PCI devices which
1258 * match the ID table and are not "owned" by other driver yet. This function
1259 * gets passed a "struct pci_dev *" for each device whose entry in the ID table
1260 * matches the device. The probe functions returns zero when the driver choose
1261 * to take "ownership" of the device or an error code(-ve no) otherwise.
1262 */
intel_eth_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)1263 static int intel_eth_pci_probe(struct pci_dev *pdev,
1264 const struct pci_device_id *id)
1265 {
1266 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
1267 struct intel_priv_data *intel_priv;
1268 struct plat_stmmacenet_data *plat;
1269 struct stmmac_resources res;
1270 int ret;
1271
1272 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL);
1273 if (!intel_priv)
1274 return -ENOMEM;
1275
1276 plat = stmmac_plat_dat_alloc(&pdev->dev);
1277 if (!plat)
1278 return -ENOMEM;
1279
1280 plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
1281 sizeof(*plat->mdio_bus_data),
1282 GFP_KERNEL);
1283 if (!plat->mdio_bus_data)
1284 return -ENOMEM;
1285
1286 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
1287 sizeof(*plat->safety_feat_cfg),
1288 GFP_KERNEL);
1289 if (!plat->safety_feat_cfg)
1290 return -ENOMEM;
1291
1292 /* Enable pci device */
1293 ret = pcim_enable_device(pdev);
1294 if (ret) {
1295 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
1296 __func__);
1297 return ret;
1298 }
1299
1300 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
1301 if (ret)
1302 return ret;
1303
1304 pci_set_master(pdev);
1305
1306 plat->bsp_priv = intel_priv;
1307 plat->suspend = intel_eth_pci_suspend;
1308 plat->resume = intel_eth_pci_resume;
1309
1310 intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR;
1311 intel_priv->crossts_adj = 1;
1312
1313 /* Initialize all MSI vectors to invalid so that it can be set
1314 * according to platform data settings below.
1315 * Note: MSI vector takes value from 0 upto 31 (STMMAC_MSI_VEC_MAX)
1316 */
1317 plat->msi_mac_vec = STMMAC_MSI_VEC_MAX;
1318 plat->msi_wol_vec = STMMAC_MSI_VEC_MAX;
1319 plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX;
1320 plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX;
1321 plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX;
1322 plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX;
1323
1324 ret = info->setup(pdev, plat);
1325 if (ret)
1326 return ret;
1327
1328 memset(&res, 0, sizeof(res));
1329 res.addr = pcim_iomap_table(pdev)[0];
1330
1331 ret = stmmac_config_multi_msi(pdev, plat, &res);
1332 if (ret) {
1333 ret = stmmac_config_single_msi(pdev, plat, &res);
1334 if (ret) {
1335 dev_err(&pdev->dev, "%s: ERROR: failed to enable IRQ\n",
1336 __func__);
1337 goto err_alloc_irq;
1338 }
1339 }
1340
1341 ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
1342 if (ret) {
1343 goto err_alloc_irq;
1344 }
1345
1346 return 0;
1347
1348 err_alloc_irq:
1349 clk_disable_unprepare(plat->stmmac_clk);
1350 clk_unregister_fixed_rate(plat->stmmac_clk);
1351 pci_free_irq_vectors(pdev);
1352 return ret;
1353 }
1354
1355 /**
1356 * intel_eth_pci_remove
1357 *
1358 * @pdev: pci device pointer
1359 * Description: this function calls the main to free the net resources
1360 * and releases the PCI resources.
1361 */
intel_eth_pci_remove(struct pci_dev * pdev)1362 static void intel_eth_pci_remove(struct pci_dev *pdev)
1363 {
1364 struct net_device *ndev = dev_get_drvdata(&pdev->dev);
1365 struct stmmac_priv *priv = netdev_priv(ndev);
1366
1367 stmmac_dvr_remove(&pdev->dev);
1368
1369 clk_disable_unprepare(priv->plat->stmmac_clk);
1370 clk_unregister_fixed_rate(priv->plat->stmmac_clk);
1371 pci_free_irq_vectors(pdev);
1372 }
1373
1374 #define PCI_DEVICE_ID_INTEL_QUARK 0x0937
1375 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30
1376 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G 0x4b31
1377 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32
1378 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
1379 * which are named PSE0 and PSE1
1380 */
1381 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0
1382 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1
1383 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2
1384 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0
1385 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1
1386 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2
1387 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0 0x43ac
1388 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1 0x43a2
1389 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G 0xa0ac
1390 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0 0x7aac
1391 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1 0x7aad
1392 #define PCI_DEVICE_ID_INTEL_ADLN_SGMII1G 0x54ac
1393 #define PCI_DEVICE_ID_INTEL_RPLP_SGMII1G 0x51ac
1394
1395 static const struct pci_device_id intel_eth_pci_id_table[] = {
1396 { PCI_DEVICE_DATA(INTEL, QUARK, &quark_info) },
1397 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, &ehl_rgmii1g_info) },
1398 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, &ehl_sgmii1g_info) },
1399 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, &ehl_sgmii1g_info) },
1400 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, &ehl_pse0_rgmii1g_info) },
1401 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, &ehl_pse0_sgmii1g_info) },
1402 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, &ehl_pse0_sgmii1g_info) },
1403 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, &ehl_pse1_rgmii1g_info) },
1404 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, &ehl_pse1_sgmii1g_info) },
1405 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, &ehl_pse1_sgmii1g_info) },
1406 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, &tgl_sgmii1g_phy0_info) },
1407 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, &tgl_sgmii1g_phy0_info) },
1408 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) },
1409 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) },
1410 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) },
1411 { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &adln_sgmii1g_phy0_info) },
1412 { PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &adln_sgmii1g_phy0_info) },
1413 {}
1414 };
1415 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
1416
1417 static struct pci_driver intel_eth_pci_driver = {
1418 .name = "intel-eth-pci",
1419 .id_table = intel_eth_pci_id_table,
1420 .probe = intel_eth_pci_probe,
1421 .remove = intel_eth_pci_remove,
1422 .driver = {
1423 .pm = &stmmac_simple_pm_ops,
1424 },
1425 };
1426
1427 module_pci_driver(intel_eth_pci_driver);
1428
1429 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver");
1430 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>");
1431 MODULE_LICENSE("GPL v2");
1432