1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
3 /*
4 Copyright (c) 2001, 2002 by D-Link Corporation
5 Written by Edward Peng.<edward_peng@dlink.com.tw>
6 Created 03-May-2001, base on Linux' sundance.c.
7
8 */
9
10 #include "dl2k.h"
11 #include <linux/dma-mapping.h>
12
13 #define dw32(reg, val) iowrite32(val, ioaddr + (reg))
14 #define dw16(reg, val) iowrite16(val, ioaddr + (reg))
15 #define dw8(reg, val) iowrite8(val, ioaddr + (reg))
16 #define dr32(reg) ioread32(ioaddr + (reg))
17 #define dr16(reg) ioread16(ioaddr + (reg))
18 #define dr8(reg) ioread8(ioaddr + (reg))
19
20 #define MAX_UNITS 8
21 static int mtu[MAX_UNITS];
22 static int vlan[MAX_UNITS];
23 static int jumbo[MAX_UNITS];
24 static char *media[MAX_UNITS];
25 static int tx_flow=-1;
26 static int rx_flow=-1;
27 static int copy_thresh;
28 static int rx_coalesce=10; /* Rx frame count each interrupt */
29 static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
30 static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
31
32
33 MODULE_AUTHOR ("Edward Peng");
34 MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
35 MODULE_LICENSE("GPL");
36 module_param_array(mtu, int, NULL, 0);
37 module_param_array(media, charp, NULL, 0);
38 module_param_array(vlan, int, NULL, 0);
39 module_param_array(jumbo, int, NULL, 0);
40 module_param(tx_flow, int, 0);
41 module_param(rx_flow, int, 0);
42 module_param(copy_thresh, int, 0);
43 module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
44 module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
45 module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
46
47
48 /* Enable the default interrupts */
49 #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
50 UpdateStats | LinkEvent)
51
dl2k_enable_int(struct netdev_private * np)52 static void dl2k_enable_int(struct netdev_private *np)
53 {
54 void __iomem *ioaddr = np->ioaddr;
55
56 dw16(IntEnable, DEFAULT_INTR);
57 }
58
59 static const int max_intrloop = 50;
60 static const int multicast_filter_limit = 0x40;
61
62 static int rio_open (struct net_device *dev);
63 static void rio_timer (struct timer_list *t);
64 static void rio_tx_timeout (struct net_device *dev, unsigned int txqueue);
65 static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
66 static irqreturn_t rio_interrupt (int irq, void *dev_instance);
67 static void rio_free_tx (struct net_device *dev, int irq);
68 static void tx_error (struct net_device *dev, int tx_status);
69 static int receive_packet (struct net_device *dev);
70 static void rio_error (struct net_device *dev, int int_status);
71 static void set_multicast (struct net_device *dev);
72 static struct net_device_stats *get_stats (struct net_device *dev);
73 static int clear_stats (struct net_device *dev);
74 static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
75 static int rio_close (struct net_device *dev);
76 static int find_miiphy (struct net_device *dev);
77 static int parse_eeprom (struct net_device *dev);
78 static int read_eeprom (struct netdev_private *, int eep_addr);
79 static int mii_wait_link (struct net_device *dev, int wait);
80 static int mii_set_media (struct net_device *dev);
81 static int mii_get_media (struct net_device *dev);
82 static int mii_set_media_pcs (struct net_device *dev);
83 static int mii_get_media_pcs (struct net_device *dev);
84 static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
85 static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
86 u16 data);
87
88 static const struct ethtool_ops ethtool_ops;
89
90 static const struct net_device_ops netdev_ops = {
91 .ndo_open = rio_open,
92 .ndo_start_xmit = start_xmit,
93 .ndo_stop = rio_close,
94 .ndo_get_stats = get_stats,
95 .ndo_validate_addr = eth_validate_addr,
96 .ndo_set_mac_address = eth_mac_addr,
97 .ndo_set_rx_mode = set_multicast,
98 .ndo_eth_ioctl = rio_ioctl,
99 .ndo_tx_timeout = rio_tx_timeout,
100 };
101
102 static int
rio_probe1(struct pci_dev * pdev,const struct pci_device_id * ent)103 rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
104 {
105 struct net_device *dev;
106 struct netdev_private *np;
107 static int card_idx;
108 int chip_idx = ent->driver_data;
109 int err, irq;
110 void __iomem *ioaddr;
111 void *ring_space;
112 dma_addr_t ring_dma;
113
114 err = pci_enable_device (pdev);
115 if (err)
116 return err;
117
118 irq = pdev->irq;
119 err = pci_request_regions (pdev, "dl2k");
120 if (err)
121 goto err_out_disable;
122
123 pci_set_master (pdev);
124
125 err = -ENOMEM;
126
127 dev = alloc_etherdev (sizeof (*np));
128 if (!dev)
129 goto err_out_res;
130 SET_NETDEV_DEV(dev, &pdev->dev);
131
132 np = netdev_priv(dev);
133
134 /* IO registers range. */
135 ioaddr = pci_iomap(pdev, 0, 0);
136 if (!ioaddr)
137 goto err_out_dev;
138 np->eeprom_addr = ioaddr;
139
140 #ifdef MEM_MAPPING
141 /* MM registers range. */
142 ioaddr = pci_iomap(pdev, 1, 0);
143 if (!ioaddr)
144 goto err_out_iounmap;
145 #endif
146 np->ioaddr = ioaddr;
147 np->chip_id = chip_idx;
148 np->pdev = pdev;
149 spin_lock_init (&np->tx_lock);
150 spin_lock_init (&np->rx_lock);
151
152 /* Parse manual configuration */
153 np->an_enable = 1;
154 np->tx_coalesce = 1;
155 if (card_idx < MAX_UNITS) {
156 if (media[card_idx] != NULL) {
157 np->an_enable = 0;
158 if (strcmp (media[card_idx], "auto") == 0 ||
159 strcmp (media[card_idx], "autosense") == 0 ||
160 strcmp (media[card_idx], "0") == 0 ) {
161 np->an_enable = 2;
162 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
163 strcmp (media[card_idx], "4") == 0) {
164 np->speed = 100;
165 np->full_duplex = 1;
166 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
167 strcmp (media[card_idx], "3") == 0) {
168 np->speed = 100;
169 np->full_duplex = 0;
170 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
171 strcmp (media[card_idx], "2") == 0) {
172 np->speed = 10;
173 np->full_duplex = 1;
174 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
175 strcmp (media[card_idx], "1") == 0) {
176 np->speed = 10;
177 np->full_duplex = 0;
178 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
179 strcmp (media[card_idx], "6") == 0) {
180 np->speed=1000;
181 np->full_duplex=1;
182 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
183 strcmp (media[card_idx], "5") == 0) {
184 np->speed = 1000;
185 np->full_duplex = 0;
186 } else {
187 np->an_enable = 1;
188 }
189 }
190 if (jumbo[card_idx] != 0) {
191 np->jumbo = 1;
192 dev->mtu = MAX_JUMBO;
193 } else {
194 np->jumbo = 0;
195 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
196 dev->mtu = mtu[card_idx];
197 }
198 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
199 vlan[card_idx] : 0;
200 if (rx_coalesce > 0 && rx_timeout > 0) {
201 np->rx_coalesce = rx_coalesce;
202 np->rx_timeout = rx_timeout;
203 np->coalesce = 1;
204 }
205 np->tx_flow = (tx_flow == 0) ? 0 : 1;
206 np->rx_flow = (rx_flow == 0) ? 0 : 1;
207
208 if (tx_coalesce < 1)
209 tx_coalesce = 1;
210 else if (tx_coalesce > TX_RING_SIZE-1)
211 tx_coalesce = TX_RING_SIZE - 1;
212 }
213 dev->netdev_ops = &netdev_ops;
214 dev->watchdog_timeo = TX_TIMEOUT;
215 dev->ethtool_ops = ðtool_ops;
216 #if 0
217 dev->features = NETIF_F_IP_CSUM;
218 #endif
219 /* MTU range: 68 - 1536 or 8000 */
220 dev->min_mtu = ETH_MIN_MTU;
221 dev->max_mtu = np->jumbo ? MAX_JUMBO : PACKET_SIZE;
222
223 pci_set_drvdata (pdev, dev);
224
225 ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, &ring_dma,
226 GFP_KERNEL);
227 if (!ring_space)
228 goto err_out_iounmap;
229 np->tx_ring = ring_space;
230 np->tx_ring_dma = ring_dma;
231
232 ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, &ring_dma,
233 GFP_KERNEL);
234 if (!ring_space)
235 goto err_out_unmap_tx;
236 np->rx_ring = ring_space;
237 np->rx_ring_dma = ring_dma;
238
239 /* Parse eeprom data */
240 parse_eeprom (dev);
241
242 /* Find PHY address */
243 err = find_miiphy (dev);
244 if (err)
245 goto err_out_unmap_rx;
246
247 /* Fiber device? */
248 np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
249 np->link_status = 0;
250 /* Set media and reset PHY */
251 if (np->phy_media) {
252 /* default Auto-Negotiation for fiber deivices */
253 if (np->an_enable == 2) {
254 np->an_enable = 1;
255 }
256 } else {
257 /* Auto-Negotiation is mandatory for 1000BASE-T,
258 IEEE 802.3ab Annex 28D page 14 */
259 if (np->speed == 1000)
260 np->an_enable = 1;
261 }
262
263 err = register_netdev (dev);
264 if (err)
265 goto err_out_unmap_rx;
266
267 card_idx++;
268
269 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
270 dev->name, np->name, dev->dev_addr, irq);
271 if (tx_coalesce > 1)
272 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
273 tx_coalesce);
274 if (np->coalesce)
275 printk(KERN_INFO
276 "rx_coalesce:\t%d packets\n"
277 "rx_timeout: \t%d ns\n",
278 np->rx_coalesce, np->rx_timeout*640);
279 if (np->vlan)
280 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
281 return 0;
282
283 err_out_unmap_rx:
284 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
285 np->rx_ring_dma);
286 err_out_unmap_tx:
287 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
288 np->tx_ring_dma);
289 err_out_iounmap:
290 #ifdef MEM_MAPPING
291 pci_iounmap(pdev, np->ioaddr);
292 #endif
293 pci_iounmap(pdev, np->eeprom_addr);
294 err_out_dev:
295 free_netdev (dev);
296 err_out_res:
297 pci_release_regions (pdev);
298 err_out_disable:
299 pci_disable_device (pdev);
300 return err;
301 }
302
303 static int
find_miiphy(struct net_device * dev)304 find_miiphy (struct net_device *dev)
305 {
306 struct netdev_private *np = netdev_priv(dev);
307 int i, phy_found = 0;
308
309 np->phy_addr = 1;
310
311 for (i = 31; i >= 0; i--) {
312 int mii_status = mii_read (dev, i, 1);
313 if (mii_status != 0xffff && mii_status != 0x0000) {
314 np->phy_addr = i;
315 phy_found++;
316 }
317 }
318 if (!phy_found) {
319 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
320 return -ENODEV;
321 }
322 return 0;
323 }
324
325 static int
parse_eeprom(struct net_device * dev)326 parse_eeprom (struct net_device *dev)
327 {
328 struct netdev_private *np = netdev_priv(dev);
329 void __iomem *ioaddr = np->ioaddr;
330 int i, j;
331 u8 sromdata[256];
332 u8 *psib;
333 u32 crc;
334 PSROM_t psrom = (PSROM_t) sromdata;
335
336 int cid, next;
337
338 for (i = 0; i < 128; i++)
339 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i));
340
341 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
342 /* Check CRC */
343 crc = ~ether_crc_le (256 - 4, sromdata);
344 if (psrom->crc != cpu_to_le32(crc)) {
345 printk (KERN_ERR "%s: EEPROM data CRC error.\n",
346 dev->name);
347 return -1;
348 }
349 }
350
351 /* Set MAC address */
352 eth_hw_addr_set(dev, psrom->mac_addr);
353
354 if (np->chip_id == CHIP_IP1000A) {
355 np->led_mode = psrom->led_mode;
356 return 0;
357 }
358
359 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
360 return 0;
361 }
362
363 /* Parse Software Information Block */
364 i = 0x30;
365 psib = (u8 *) sromdata;
366 do {
367 cid = psib[i++];
368 next = psib[i++];
369 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
370 printk (KERN_ERR "Cell data error\n");
371 return -1;
372 }
373 switch (cid) {
374 case 0: /* Format version */
375 break;
376 case 1: /* End of cell */
377 return 0;
378 case 2: /* Duplex Polarity */
379 np->duplex_polarity = psib[i];
380 dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]);
381 break;
382 case 3: /* Wake Polarity */
383 np->wake_polarity = psib[i];
384 break;
385 case 9: /* Adapter description */
386 j = (next - i > 255) ? 255 : next - i;
387 memcpy (np->name, &(psib[i]), j);
388 break;
389 case 4:
390 case 5:
391 case 6:
392 case 7:
393 case 8: /* Reversed */
394 break;
395 default: /* Unknown cell */
396 return -1;
397 }
398 i = next;
399 } while (1);
400
401 return 0;
402 }
403
rio_set_led_mode(struct net_device * dev)404 static void rio_set_led_mode(struct net_device *dev)
405 {
406 struct netdev_private *np = netdev_priv(dev);
407 void __iomem *ioaddr = np->ioaddr;
408 u32 mode;
409
410 if (np->chip_id != CHIP_IP1000A)
411 return;
412
413 mode = dr32(ASICCtrl);
414 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
415
416 if (np->led_mode & 0x01)
417 mode |= IPG_AC_LED_MODE;
418 if (np->led_mode & 0x02)
419 mode |= IPG_AC_LED_MODE_BIT_1;
420 if (np->led_mode & 0x08)
421 mode |= IPG_AC_LED_SPEED;
422
423 dw32(ASICCtrl, mode);
424 }
425
desc_to_dma(struct netdev_desc * desc)426 static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
427 {
428 return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
429 }
430
free_list(struct net_device * dev)431 static void free_list(struct net_device *dev)
432 {
433 struct netdev_private *np = netdev_priv(dev);
434 struct sk_buff *skb;
435 int i;
436
437 /* Free all the skbuffs in the queue. */
438 for (i = 0; i < RX_RING_SIZE; i++) {
439 skb = np->rx_skbuff[i];
440 if (skb) {
441 dma_unmap_single(&np->pdev->dev,
442 desc_to_dma(&np->rx_ring[i]),
443 skb->len, DMA_FROM_DEVICE);
444 dev_kfree_skb(skb);
445 np->rx_skbuff[i] = NULL;
446 }
447 np->rx_ring[i].status = 0;
448 np->rx_ring[i].fraginfo = 0;
449 }
450 for (i = 0; i < TX_RING_SIZE; i++) {
451 skb = np->tx_skbuff[i];
452 if (skb) {
453 dma_unmap_single(&np->pdev->dev,
454 desc_to_dma(&np->tx_ring[i]),
455 skb->len, DMA_TO_DEVICE);
456 dev_kfree_skb(skb);
457 np->tx_skbuff[i] = NULL;
458 }
459 }
460 }
461
rio_reset_ring(struct netdev_private * np)462 static void rio_reset_ring(struct netdev_private *np)
463 {
464 int i;
465
466 np->cur_rx = 0;
467 np->cur_tx = 0;
468 np->old_rx = 0;
469 np->old_tx = 0;
470
471 for (i = 0; i < TX_RING_SIZE; i++)
472 np->tx_ring[i].status = cpu_to_le64(TFDDone);
473
474 for (i = 0; i < RX_RING_SIZE; i++)
475 np->rx_ring[i].status = 0;
476 }
477
478 /* allocate and initialize Tx and Rx descriptors */
alloc_list(struct net_device * dev)479 static int alloc_list(struct net_device *dev)
480 {
481 struct netdev_private *np = netdev_priv(dev);
482 int i;
483
484 rio_reset_ring(np);
485 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
486
487 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
488 for (i = 0; i < TX_RING_SIZE; i++) {
489 np->tx_skbuff[i] = NULL;
490 np->tx_ring[i].next_desc = cpu_to_le64(np->tx_ring_dma +
491 ((i + 1) % TX_RING_SIZE) *
492 sizeof(struct netdev_desc));
493 }
494
495 /* Initialize Rx descriptors & allocate buffers */
496 for (i = 0; i < RX_RING_SIZE; i++) {
497 /* Allocated fixed size of skbuff */
498 struct sk_buff *skb;
499
500 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
501 np->rx_skbuff[i] = skb;
502 if (!skb) {
503 free_list(dev);
504 return -ENOMEM;
505 }
506
507 np->rx_ring[i].next_desc = cpu_to_le64(np->rx_ring_dma +
508 ((i + 1) % RX_RING_SIZE) *
509 sizeof(struct netdev_desc));
510 /* Rubicon now supports 40 bits of addressing space. */
511 np->rx_ring[i].fraginfo =
512 cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data,
513 np->rx_buf_sz, DMA_FROM_DEVICE));
514 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
515 }
516
517 return 0;
518 }
519
rio_hw_init(struct net_device * dev)520 static void rio_hw_init(struct net_device *dev)
521 {
522 struct netdev_private *np = netdev_priv(dev);
523 void __iomem *ioaddr = np->ioaddr;
524 int i;
525 u16 macctrl;
526
527 /* Reset all logic functions */
528 dw16(ASICCtrl + 2,
529 GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
530 mdelay(10);
531
532 rio_set_led_mode(dev);
533
534 /* DebugCtrl bit 4, 5, 9 must set */
535 dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
536
537 if (np->chip_id == CHIP_IP1000A &&
538 (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) {
539 /* PHY magic taken from ipg driver, undocumented registers */
540 mii_write(dev, np->phy_addr, 31, 0x0001);
541 mii_write(dev, np->phy_addr, 27, 0x01e0);
542 mii_write(dev, np->phy_addr, 31, 0x0002);
543 mii_write(dev, np->phy_addr, 27, 0xeb8e);
544 mii_write(dev, np->phy_addr, 31, 0x0000);
545 mii_write(dev, np->phy_addr, 30, 0x005e);
546 /* advertise 1000BASE-T half & full duplex, prefer MASTER */
547 mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700);
548 }
549
550 if (np->phy_media)
551 mii_set_media_pcs(dev);
552 else
553 mii_set_media(dev);
554
555 /* Jumbo frame */
556 if (np->jumbo != 0)
557 dw16(MaxFrameSize, MAX_JUMBO+14);
558
559 /* Set RFDListPtr */
560 dw32(RFDListPtr0, np->rx_ring_dma);
561 dw32(RFDListPtr1, 0);
562
563 /* Set station address */
564 /* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works
565 * too. However, it doesn't work on IP1000A so we use 16-bit access.
566 */
567 for (i = 0; i < 3; i++)
568 dw16(StationAddr0 + 2 * i, get_unaligned_le16(&dev->dev_addr[2 * i]));
569
570 set_multicast (dev);
571 if (np->coalesce) {
572 dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
573 }
574 /* Set RIO to poll every N*320nsec. */
575 dw8(RxDMAPollPeriod, 0x20);
576 dw8(TxDMAPollPeriod, 0xff);
577 dw8(RxDMABurstThresh, 0x30);
578 dw8(RxDMAUrgentThresh, 0x30);
579 dw32(RmonStatMask, 0x0007ffff);
580 /* clear statistics */
581 clear_stats (dev);
582
583 /* VLAN supported */
584 if (np->vlan) {
585 /* priority field in RxDMAIntCtrl */
586 dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
587 /* VLANId */
588 dw16(VLANId, np->vlan);
589 /* Length/Type should be 0x8100 */
590 dw32(VLANTag, 0x8100 << 16 | np->vlan);
591 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
592 VLAN information tagged by TFC' VID, CFI fields. */
593 dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
594 }
595
596 /* Start Tx/Rx */
597 dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
598
599 macctrl = 0;
600 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
601 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
602 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
603 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
604 dw16(MACCtrl, macctrl);
605 }
606
rio_hw_stop(struct net_device * dev)607 static void rio_hw_stop(struct net_device *dev)
608 {
609 struct netdev_private *np = netdev_priv(dev);
610 void __iomem *ioaddr = np->ioaddr;
611
612 /* Disable interrupts */
613 dw16(IntEnable, 0);
614
615 /* Stop Tx and Rx logics */
616 dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
617 }
618
rio_open(struct net_device * dev)619 static int rio_open(struct net_device *dev)
620 {
621 struct netdev_private *np = netdev_priv(dev);
622 const int irq = np->pdev->irq;
623 int i;
624
625 i = alloc_list(dev);
626 if (i)
627 return i;
628
629 rio_hw_init(dev);
630
631 i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
632 if (i) {
633 rio_hw_stop(dev);
634 free_list(dev);
635 return i;
636 }
637
638 timer_setup(&np->timer, rio_timer, 0);
639 np->timer.expires = jiffies + 1 * HZ;
640 add_timer(&np->timer);
641
642 netif_start_queue (dev);
643
644 dl2k_enable_int(np);
645 return 0;
646 }
647
648 static void
rio_timer(struct timer_list * t)649 rio_timer (struct timer_list *t)
650 {
651 struct netdev_private *np = from_timer(np, t, timer);
652 struct net_device *dev = pci_get_drvdata(np->pdev);
653 unsigned int entry;
654 int next_tick = 1*HZ;
655 unsigned long flags;
656
657 spin_lock_irqsave(&np->rx_lock, flags);
658 /* Recover rx ring exhausted error */
659 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
660 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
661 /* Re-allocate skbuffs to fill the descriptor ring */
662 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
663 struct sk_buff *skb;
664 entry = np->old_rx % RX_RING_SIZE;
665 /* Dropped packets don't need to re-allocate */
666 if (np->rx_skbuff[entry] == NULL) {
667 skb = netdev_alloc_skb_ip_align(dev,
668 np->rx_buf_sz);
669 if (skb == NULL) {
670 np->rx_ring[entry].fraginfo = 0;
671 printk (KERN_INFO
672 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
673 dev->name, entry);
674 break;
675 }
676 np->rx_skbuff[entry] = skb;
677 np->rx_ring[entry].fraginfo =
678 cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data,
679 np->rx_buf_sz, DMA_FROM_DEVICE));
680 }
681 np->rx_ring[entry].fraginfo |=
682 cpu_to_le64((u64)np->rx_buf_sz << 48);
683 np->rx_ring[entry].status = 0;
684 } /* end for */
685 } /* end if */
686 spin_unlock_irqrestore (&np->rx_lock, flags);
687 np->timer.expires = jiffies + next_tick;
688 add_timer(&np->timer);
689 }
690
691 static void
rio_tx_timeout(struct net_device * dev,unsigned int txqueue)692 rio_tx_timeout (struct net_device *dev, unsigned int txqueue)
693 {
694 struct netdev_private *np = netdev_priv(dev);
695 void __iomem *ioaddr = np->ioaddr;
696
697 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
698 dev->name, dr32(TxStatus));
699 rio_free_tx(dev, 0);
700 dev->if_port = 0;
701 netif_trans_update(dev); /* prevent tx timeout */
702 }
703
704 static netdev_tx_t
start_xmit(struct sk_buff * skb,struct net_device * dev)705 start_xmit (struct sk_buff *skb, struct net_device *dev)
706 {
707 struct netdev_private *np = netdev_priv(dev);
708 void __iomem *ioaddr = np->ioaddr;
709 struct netdev_desc *txdesc;
710 unsigned entry;
711 u64 tfc_vlan_tag = 0;
712
713 if (np->link_status == 0) { /* Link Down */
714 dev_kfree_skb(skb);
715 return NETDEV_TX_OK;
716 }
717 entry = np->cur_tx % TX_RING_SIZE;
718 np->tx_skbuff[entry] = skb;
719 txdesc = &np->tx_ring[entry];
720
721 #if 0
722 if (skb->ip_summed == CHECKSUM_PARTIAL) {
723 txdesc->status |=
724 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
725 IPChecksumEnable);
726 }
727 #endif
728 if (np->vlan) {
729 tfc_vlan_tag = VLANTagInsert |
730 ((u64)np->vlan << 32) |
731 ((u64)skb->priority << 45);
732 }
733 txdesc->fraginfo = cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data,
734 skb->len, DMA_TO_DEVICE));
735 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
736
737 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
738 * Work around: Always use 1 descriptor in 10Mbps mode */
739 if (entry % np->tx_coalesce == 0 || np->speed == 10)
740 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
741 WordAlignDisable |
742 TxDMAIndicate |
743 (1 << FragCountShift));
744 else
745 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
746 WordAlignDisable |
747 (1 << FragCountShift));
748
749 /* TxDMAPollNow */
750 dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
751 /* Schedule ISR */
752 dw32(CountDown, 10000);
753 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
754 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
755 < TX_QUEUE_LEN - 1 && np->speed != 10) {
756 /* do nothing */
757 } else if (!netif_queue_stopped(dev)) {
758 netif_stop_queue (dev);
759 }
760
761 /* The first TFDListPtr */
762 if (!dr32(TFDListPtr0)) {
763 dw32(TFDListPtr0, np->tx_ring_dma +
764 entry * sizeof (struct netdev_desc));
765 dw32(TFDListPtr1, 0);
766 }
767
768 return NETDEV_TX_OK;
769 }
770
771 static irqreturn_t
rio_interrupt(int irq,void * dev_instance)772 rio_interrupt (int irq, void *dev_instance)
773 {
774 struct net_device *dev = dev_instance;
775 struct netdev_private *np = netdev_priv(dev);
776 void __iomem *ioaddr = np->ioaddr;
777 unsigned int_status;
778 int cnt = max_intrloop;
779 int handled = 0;
780
781 while (1) {
782 int_status = dr16(IntStatus);
783 dw16(IntStatus, int_status);
784 int_status &= DEFAULT_INTR;
785 if (int_status == 0 || --cnt < 0)
786 break;
787 handled = 1;
788 /* Processing received packets */
789 if (int_status & RxDMAComplete)
790 receive_packet (dev);
791 /* TxDMAComplete interrupt */
792 if ((int_status & (TxDMAComplete|IntRequested))) {
793 int tx_status;
794 tx_status = dr32(TxStatus);
795 if (tx_status & 0x01)
796 tx_error (dev, tx_status);
797 /* Free used tx skbuffs */
798 rio_free_tx (dev, 1);
799 }
800
801 /* Handle uncommon events */
802 if (int_status &
803 (HostError | LinkEvent | UpdateStats))
804 rio_error (dev, int_status);
805 }
806 if (np->cur_tx != np->old_tx)
807 dw32(CountDown, 100);
808 return IRQ_RETVAL(handled);
809 }
810
811 static void
rio_free_tx(struct net_device * dev,int irq)812 rio_free_tx (struct net_device *dev, int irq)
813 {
814 struct netdev_private *np = netdev_priv(dev);
815 int entry = np->old_tx % TX_RING_SIZE;
816 unsigned long flag = 0;
817
818 if (irq)
819 spin_lock(&np->tx_lock);
820 else
821 spin_lock_irqsave(&np->tx_lock, flag);
822
823 /* Free used tx skbuffs */
824 while (entry != np->cur_tx) {
825 struct sk_buff *skb;
826
827 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
828 break;
829 skb = np->tx_skbuff[entry];
830 dma_unmap_single(&np->pdev->dev,
831 desc_to_dma(&np->tx_ring[entry]), skb->len,
832 DMA_TO_DEVICE);
833 if (irq)
834 dev_consume_skb_irq(skb);
835 else
836 dev_kfree_skb(skb);
837
838 np->tx_skbuff[entry] = NULL;
839 entry = (entry + 1) % TX_RING_SIZE;
840 }
841 if (irq)
842 spin_unlock(&np->tx_lock);
843 else
844 spin_unlock_irqrestore(&np->tx_lock, flag);
845 np->old_tx = entry;
846
847 /* If the ring is no longer full, clear tx_full and
848 call netif_wake_queue() */
849
850 if (netif_queue_stopped(dev) &&
851 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
852 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
853 netif_wake_queue (dev);
854 }
855 }
856
857 static void
tx_error(struct net_device * dev,int tx_status)858 tx_error (struct net_device *dev, int tx_status)
859 {
860 struct netdev_private *np = netdev_priv(dev);
861 void __iomem *ioaddr = np->ioaddr;
862 int frame_id;
863 int i;
864
865 frame_id = (tx_status & 0xffff0000);
866 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
867 dev->name, tx_status, frame_id);
868 dev->stats.tx_errors++;
869 /* Ttransmit Underrun */
870 if (tx_status & 0x10) {
871 dev->stats.tx_fifo_errors++;
872 dw16(TxStartThresh, dr16(TxStartThresh) + 0x10);
873 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
874 dw16(ASICCtrl + 2,
875 TxReset | DMAReset | FIFOReset | NetworkReset);
876 /* Wait for ResetBusy bit clear */
877 for (i = 50; i > 0; i--) {
878 if (!(dr16(ASICCtrl + 2) & ResetBusy))
879 break;
880 mdelay (1);
881 }
882 rio_set_led_mode(dev);
883 rio_free_tx (dev, 1);
884 /* Reset TFDListPtr */
885 dw32(TFDListPtr0, np->tx_ring_dma +
886 np->old_tx * sizeof (struct netdev_desc));
887 dw32(TFDListPtr1, 0);
888
889 /* Let TxStartThresh stay default value */
890 }
891 /* Late Collision */
892 if (tx_status & 0x04) {
893 dev->stats.tx_fifo_errors++;
894 /* TxReset and clear FIFO */
895 dw16(ASICCtrl + 2, TxReset | FIFOReset);
896 /* Wait reset done */
897 for (i = 50; i > 0; i--) {
898 if (!(dr16(ASICCtrl + 2) & ResetBusy))
899 break;
900 mdelay (1);
901 }
902 rio_set_led_mode(dev);
903 /* Let TxStartThresh stay default value */
904 }
905 /* Maximum Collisions */
906 if (tx_status & 0x08)
907 dev->stats.collisions++;
908 /* Restart the Tx */
909 dw32(MACCtrl, dr16(MACCtrl) | TxEnable);
910 }
911
912 static int
receive_packet(struct net_device * dev)913 receive_packet (struct net_device *dev)
914 {
915 struct netdev_private *np = netdev_priv(dev);
916 int entry = np->cur_rx % RX_RING_SIZE;
917 int cnt = 30;
918
919 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
920 while (1) {
921 struct netdev_desc *desc = &np->rx_ring[entry];
922 int pkt_len;
923 u64 frame_status;
924
925 if (!(desc->status & cpu_to_le64(RFDDone)) ||
926 !(desc->status & cpu_to_le64(FrameStart)) ||
927 !(desc->status & cpu_to_le64(FrameEnd)))
928 break;
929
930 /* Chip omits the CRC. */
931 frame_status = le64_to_cpu(desc->status);
932 pkt_len = frame_status & 0xffff;
933 if (--cnt < 0)
934 break;
935 /* Update rx error statistics, drop packet. */
936 if (frame_status & RFS_Errors) {
937 dev->stats.rx_errors++;
938 if (frame_status & (RxRuntFrame | RxLengthError))
939 dev->stats.rx_length_errors++;
940 if (frame_status & RxFCSError)
941 dev->stats.rx_crc_errors++;
942 if (frame_status & RxAlignmentError && np->speed != 1000)
943 dev->stats.rx_frame_errors++;
944 if (frame_status & RxFIFOOverrun)
945 dev->stats.rx_fifo_errors++;
946 } else {
947 struct sk_buff *skb;
948
949 /* Small skbuffs for short packets */
950 if (pkt_len > copy_thresh) {
951 dma_unmap_single(&np->pdev->dev,
952 desc_to_dma(desc),
953 np->rx_buf_sz,
954 DMA_FROM_DEVICE);
955 skb_put (skb = np->rx_skbuff[entry], pkt_len);
956 np->rx_skbuff[entry] = NULL;
957 } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) {
958 dma_sync_single_for_cpu(&np->pdev->dev,
959 desc_to_dma(desc),
960 np->rx_buf_sz,
961 DMA_FROM_DEVICE);
962 skb_copy_to_linear_data (skb,
963 np->rx_skbuff[entry]->data,
964 pkt_len);
965 skb_put (skb, pkt_len);
966 dma_sync_single_for_device(&np->pdev->dev,
967 desc_to_dma(desc),
968 np->rx_buf_sz,
969 DMA_FROM_DEVICE);
970 }
971 skb->protocol = eth_type_trans (skb, dev);
972 #if 0
973 /* Checksum done by hw, but csum value unavailable. */
974 if (np->pdev->pci_rev_id >= 0x0c &&
975 !(frame_status & (TCPError | UDPError | IPError))) {
976 skb->ip_summed = CHECKSUM_UNNECESSARY;
977 }
978 #endif
979 netif_rx (skb);
980 }
981 entry = (entry + 1) % RX_RING_SIZE;
982 }
983 spin_lock(&np->rx_lock);
984 np->cur_rx = entry;
985 /* Re-allocate skbuffs to fill the descriptor ring */
986 entry = np->old_rx;
987 while (entry != np->cur_rx) {
988 struct sk_buff *skb;
989 /* Dropped packets don't need to re-allocate */
990 if (np->rx_skbuff[entry] == NULL) {
991 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
992 if (skb == NULL) {
993 np->rx_ring[entry].fraginfo = 0;
994 printk (KERN_INFO
995 "%s: receive_packet: "
996 "Unable to re-allocate Rx skbuff.#%d\n",
997 dev->name, entry);
998 break;
999 }
1000 np->rx_skbuff[entry] = skb;
1001 np->rx_ring[entry].fraginfo =
1002 cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data,
1003 np->rx_buf_sz, DMA_FROM_DEVICE));
1004 }
1005 np->rx_ring[entry].fraginfo |=
1006 cpu_to_le64((u64)np->rx_buf_sz << 48);
1007 np->rx_ring[entry].status = 0;
1008 entry = (entry + 1) % RX_RING_SIZE;
1009 }
1010 np->old_rx = entry;
1011 spin_unlock(&np->rx_lock);
1012 return 0;
1013 }
1014
1015 static void
rio_error(struct net_device * dev,int int_status)1016 rio_error (struct net_device *dev, int int_status)
1017 {
1018 struct netdev_private *np = netdev_priv(dev);
1019 void __iomem *ioaddr = np->ioaddr;
1020 u16 macctrl;
1021
1022 /* Link change event */
1023 if (int_status & LinkEvent) {
1024 if (mii_wait_link (dev, 10) == 0) {
1025 printk (KERN_INFO "%s: Link up\n", dev->name);
1026 if (np->phy_media)
1027 mii_get_media_pcs (dev);
1028 else
1029 mii_get_media (dev);
1030 if (np->speed == 1000)
1031 np->tx_coalesce = tx_coalesce;
1032 else
1033 np->tx_coalesce = 1;
1034 macctrl = 0;
1035 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
1036 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
1037 macctrl |= (np->tx_flow) ?
1038 TxFlowControlEnable : 0;
1039 macctrl |= (np->rx_flow) ?
1040 RxFlowControlEnable : 0;
1041 dw16(MACCtrl, macctrl);
1042 np->link_status = 1;
1043 netif_carrier_on(dev);
1044 } else {
1045 printk (KERN_INFO "%s: Link off\n", dev->name);
1046 np->link_status = 0;
1047 netif_carrier_off(dev);
1048 }
1049 }
1050
1051 /* UpdateStats statistics registers */
1052 if (int_status & UpdateStats) {
1053 get_stats (dev);
1054 }
1055
1056 /* PCI Error, a catastronphic error related to the bus interface
1057 occurs, set GlobalReset and HostReset to reset. */
1058 if (int_status & HostError) {
1059 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
1060 dev->name, int_status);
1061 dw16(ASICCtrl + 2, GlobalReset | HostReset);
1062 mdelay (500);
1063 rio_set_led_mode(dev);
1064 }
1065 }
1066
1067 static struct net_device_stats *
get_stats(struct net_device * dev)1068 get_stats (struct net_device *dev)
1069 {
1070 struct netdev_private *np = netdev_priv(dev);
1071 void __iomem *ioaddr = np->ioaddr;
1072 #ifdef MEM_MAPPING
1073 int i;
1074 #endif
1075 unsigned int stat_reg;
1076
1077 /* All statistics registers need to be acknowledged,
1078 else statistic overflow could cause problems */
1079
1080 dev->stats.rx_packets += dr32(FramesRcvOk);
1081 dev->stats.tx_packets += dr32(FramesXmtOk);
1082 dev->stats.rx_bytes += dr32(OctetRcvOk);
1083 dev->stats.tx_bytes += dr32(OctetXmtOk);
1084
1085 dev->stats.multicast = dr32(McstFramesRcvdOk);
1086 dev->stats.collisions += dr32(SingleColFrames)
1087 + dr32(MultiColFrames);
1088
1089 /* detailed tx errors */
1090 stat_reg = dr16(FramesAbortXSColls);
1091 dev->stats.tx_aborted_errors += stat_reg;
1092 dev->stats.tx_errors += stat_reg;
1093
1094 stat_reg = dr16(CarrierSenseErrors);
1095 dev->stats.tx_carrier_errors += stat_reg;
1096 dev->stats.tx_errors += stat_reg;
1097
1098 /* Clear all other statistic register. */
1099 dr32(McstOctetXmtOk);
1100 dr16(BcstFramesXmtdOk);
1101 dr32(McstFramesXmtdOk);
1102 dr16(BcstFramesRcvdOk);
1103 dr16(MacControlFramesRcvd);
1104 dr16(FrameTooLongErrors);
1105 dr16(InRangeLengthErrors);
1106 dr16(FramesCheckSeqErrors);
1107 dr16(FramesLostRxErrors);
1108 dr32(McstOctetXmtOk);
1109 dr32(BcstOctetXmtOk);
1110 dr32(McstFramesXmtdOk);
1111 dr32(FramesWDeferredXmt);
1112 dr32(LateCollisions);
1113 dr16(BcstFramesXmtdOk);
1114 dr16(MacControlFramesXmtd);
1115 dr16(FramesWEXDeferal);
1116
1117 #ifdef MEM_MAPPING
1118 for (i = 0x100; i <= 0x150; i += 4)
1119 dr32(i);
1120 #endif
1121 dr16(TxJumboFrames);
1122 dr16(RxJumboFrames);
1123 dr16(TCPCheckSumErrors);
1124 dr16(UDPCheckSumErrors);
1125 dr16(IPCheckSumErrors);
1126 return &dev->stats;
1127 }
1128
1129 static int
clear_stats(struct net_device * dev)1130 clear_stats (struct net_device *dev)
1131 {
1132 struct netdev_private *np = netdev_priv(dev);
1133 void __iomem *ioaddr = np->ioaddr;
1134 #ifdef MEM_MAPPING
1135 int i;
1136 #endif
1137
1138 /* All statistics registers need to be acknowledged,
1139 else statistic overflow could cause problems */
1140 dr32(FramesRcvOk);
1141 dr32(FramesXmtOk);
1142 dr32(OctetRcvOk);
1143 dr32(OctetXmtOk);
1144
1145 dr32(McstFramesRcvdOk);
1146 dr32(SingleColFrames);
1147 dr32(MultiColFrames);
1148 dr32(LateCollisions);
1149 /* detailed rx errors */
1150 dr16(FrameTooLongErrors);
1151 dr16(InRangeLengthErrors);
1152 dr16(FramesCheckSeqErrors);
1153 dr16(FramesLostRxErrors);
1154
1155 /* detailed tx errors */
1156 dr16(FramesAbortXSColls);
1157 dr16(CarrierSenseErrors);
1158
1159 /* Clear all other statistic register. */
1160 dr32(McstOctetXmtOk);
1161 dr16(BcstFramesXmtdOk);
1162 dr32(McstFramesXmtdOk);
1163 dr16(BcstFramesRcvdOk);
1164 dr16(MacControlFramesRcvd);
1165 dr32(McstOctetXmtOk);
1166 dr32(BcstOctetXmtOk);
1167 dr32(McstFramesXmtdOk);
1168 dr32(FramesWDeferredXmt);
1169 dr16(BcstFramesXmtdOk);
1170 dr16(MacControlFramesXmtd);
1171 dr16(FramesWEXDeferal);
1172 #ifdef MEM_MAPPING
1173 for (i = 0x100; i <= 0x150; i += 4)
1174 dr32(i);
1175 #endif
1176 dr16(TxJumboFrames);
1177 dr16(RxJumboFrames);
1178 dr16(TCPCheckSumErrors);
1179 dr16(UDPCheckSumErrors);
1180 dr16(IPCheckSumErrors);
1181 return 0;
1182 }
1183
1184 static void
set_multicast(struct net_device * dev)1185 set_multicast (struct net_device *dev)
1186 {
1187 struct netdev_private *np = netdev_priv(dev);
1188 void __iomem *ioaddr = np->ioaddr;
1189 u32 hash_table[2];
1190 u16 rx_mode = 0;
1191
1192 hash_table[0] = hash_table[1] = 0;
1193 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
1194 hash_table[1] |= 0x02000000;
1195 if (dev->flags & IFF_PROMISC) {
1196 /* Receive all frames promiscuously. */
1197 rx_mode = ReceiveAllFrames;
1198 } else if ((dev->flags & IFF_ALLMULTI) ||
1199 (netdev_mc_count(dev) > multicast_filter_limit)) {
1200 /* Receive broadcast and multicast frames */
1201 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1202 } else if (!netdev_mc_empty(dev)) {
1203 struct netdev_hw_addr *ha;
1204 /* Receive broadcast frames and multicast frames filtering
1205 by Hashtable */
1206 rx_mode =
1207 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1208 netdev_for_each_mc_addr(ha, dev) {
1209 int bit, index = 0;
1210 int crc = ether_crc_le(ETH_ALEN, ha->addr);
1211 /* The inverted high significant 6 bits of CRC are
1212 used as an index to hashtable */
1213 for (bit = 0; bit < 6; bit++)
1214 if (crc & (1 << (31 - bit)))
1215 index |= (1 << bit);
1216 hash_table[index / 32] |= (1 << (index % 32));
1217 }
1218 } else {
1219 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1220 }
1221 if (np->vlan) {
1222 /* ReceiveVLANMatch field in ReceiveMode */
1223 rx_mode |= ReceiveVLANMatch;
1224 }
1225
1226 dw32(HashTable0, hash_table[0]);
1227 dw32(HashTable1, hash_table[1]);
1228 dw16(ReceiveMode, rx_mode);
1229 }
1230
rio_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1231 static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1232 {
1233 struct netdev_private *np = netdev_priv(dev);
1234
1235 strscpy(info->driver, "dl2k", sizeof(info->driver));
1236 strscpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
1237 }
1238
rio_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)1239 static int rio_get_link_ksettings(struct net_device *dev,
1240 struct ethtool_link_ksettings *cmd)
1241 {
1242 struct netdev_private *np = netdev_priv(dev);
1243 u32 supported, advertising;
1244
1245 if (np->phy_media) {
1246 /* fiber device */
1247 supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1248 advertising = ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1249 cmd->base.port = PORT_FIBRE;
1250 } else {
1251 /* copper device */
1252 supported = SUPPORTED_10baseT_Half |
1253 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1254 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1255 SUPPORTED_Autoneg | SUPPORTED_MII;
1256 advertising = ADVERTISED_10baseT_Half |
1257 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1258 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full |
1259 ADVERTISED_Autoneg | ADVERTISED_MII;
1260 cmd->base.port = PORT_MII;
1261 }
1262 if (np->link_status) {
1263 cmd->base.speed = np->speed;
1264 cmd->base.duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1265 } else {
1266 cmd->base.speed = SPEED_UNKNOWN;
1267 cmd->base.duplex = DUPLEX_UNKNOWN;
1268 }
1269 if (np->an_enable)
1270 cmd->base.autoneg = AUTONEG_ENABLE;
1271 else
1272 cmd->base.autoneg = AUTONEG_DISABLE;
1273
1274 cmd->base.phy_address = np->phy_addr;
1275
1276 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1277 supported);
1278 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1279 advertising);
1280
1281 return 0;
1282 }
1283
rio_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)1284 static int rio_set_link_ksettings(struct net_device *dev,
1285 const struct ethtool_link_ksettings *cmd)
1286 {
1287 struct netdev_private *np = netdev_priv(dev);
1288 u32 speed = cmd->base.speed;
1289 u8 duplex = cmd->base.duplex;
1290
1291 netif_carrier_off(dev);
1292 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1293 if (np->an_enable) {
1294 return 0;
1295 } else {
1296 np->an_enable = 1;
1297 mii_set_media(dev);
1298 return 0;
1299 }
1300 } else {
1301 np->an_enable = 0;
1302 if (np->speed == 1000) {
1303 speed = SPEED_100;
1304 duplex = DUPLEX_FULL;
1305 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1306 }
1307 switch (speed) {
1308 case SPEED_10:
1309 np->speed = 10;
1310 np->full_duplex = (duplex == DUPLEX_FULL);
1311 break;
1312 case SPEED_100:
1313 np->speed = 100;
1314 np->full_duplex = (duplex == DUPLEX_FULL);
1315 break;
1316 case SPEED_1000: /* not supported */
1317 default:
1318 return -EINVAL;
1319 }
1320 mii_set_media(dev);
1321 }
1322 return 0;
1323 }
1324
rio_get_link(struct net_device * dev)1325 static u32 rio_get_link(struct net_device *dev)
1326 {
1327 struct netdev_private *np = netdev_priv(dev);
1328 return np->link_status;
1329 }
1330
1331 static const struct ethtool_ops ethtool_ops = {
1332 .get_drvinfo = rio_get_drvinfo,
1333 .get_link = rio_get_link,
1334 .get_link_ksettings = rio_get_link_ksettings,
1335 .set_link_ksettings = rio_set_link_ksettings,
1336 };
1337
1338 static int
rio_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1339 rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1340 {
1341 int phy_addr;
1342 struct netdev_private *np = netdev_priv(dev);
1343 struct mii_ioctl_data *miidata = if_mii(rq);
1344
1345 phy_addr = np->phy_addr;
1346 switch (cmd) {
1347 case SIOCGMIIPHY:
1348 miidata->phy_id = phy_addr;
1349 break;
1350 case SIOCGMIIREG:
1351 miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
1352 break;
1353 case SIOCSMIIREG:
1354 if (!capable(CAP_NET_ADMIN))
1355 return -EPERM;
1356 mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
1357 break;
1358 default:
1359 return -EOPNOTSUPP;
1360 }
1361 return 0;
1362 }
1363
1364 #define EEP_READ 0x0200
1365 #define EEP_BUSY 0x8000
1366 /* Read the EEPROM word */
1367 /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
read_eeprom(struct netdev_private * np,int eep_addr)1368 static int read_eeprom(struct netdev_private *np, int eep_addr)
1369 {
1370 void __iomem *ioaddr = np->eeprom_addr;
1371 int i = 1000;
1372
1373 dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff));
1374 while (i-- > 0) {
1375 if (!(dr16(EepromCtrl) & EEP_BUSY))
1376 return dr16(EepromData);
1377 }
1378 return 0;
1379 }
1380
1381 enum phy_ctrl_bits {
1382 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1383 MII_DUPLEX = 0x08,
1384 };
1385
1386 #define mii_delay() dr8(PhyCtrl)
1387 static void
mii_sendbit(struct net_device * dev,u32 data)1388 mii_sendbit (struct net_device *dev, u32 data)
1389 {
1390 struct netdev_private *np = netdev_priv(dev);
1391 void __iomem *ioaddr = np->ioaddr;
1392
1393 data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE;
1394 dw8(PhyCtrl, data);
1395 mii_delay ();
1396 dw8(PhyCtrl, data | MII_CLK);
1397 mii_delay ();
1398 }
1399
1400 static int
mii_getbit(struct net_device * dev)1401 mii_getbit (struct net_device *dev)
1402 {
1403 struct netdev_private *np = netdev_priv(dev);
1404 void __iomem *ioaddr = np->ioaddr;
1405 u8 data;
1406
1407 data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
1408 dw8(PhyCtrl, data);
1409 mii_delay ();
1410 dw8(PhyCtrl, data | MII_CLK);
1411 mii_delay ();
1412 return (dr8(PhyCtrl) >> 1) & 1;
1413 }
1414
1415 static void
mii_send_bits(struct net_device * dev,u32 data,int len)1416 mii_send_bits (struct net_device *dev, u32 data, int len)
1417 {
1418 int i;
1419
1420 for (i = len - 1; i >= 0; i--) {
1421 mii_sendbit (dev, data & (1 << i));
1422 }
1423 }
1424
1425 static int
mii_read(struct net_device * dev,int phy_addr,int reg_num)1426 mii_read (struct net_device *dev, int phy_addr, int reg_num)
1427 {
1428 u32 cmd;
1429 int i;
1430 u32 retval = 0;
1431
1432 /* Preamble */
1433 mii_send_bits (dev, 0xffffffff, 32);
1434 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1435 /* ST,OP = 0110'b for read operation */
1436 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1437 mii_send_bits (dev, cmd, 14);
1438 /* Turnaround */
1439 if (mii_getbit (dev))
1440 goto err_out;
1441 /* Read data */
1442 for (i = 0; i < 16; i++) {
1443 retval |= mii_getbit (dev);
1444 retval <<= 1;
1445 }
1446 /* End cycle */
1447 mii_getbit (dev);
1448 return (retval >> 1) & 0xffff;
1449
1450 err_out:
1451 return 0;
1452 }
1453 static int
mii_write(struct net_device * dev,int phy_addr,int reg_num,u16 data)1454 mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1455 {
1456 u32 cmd;
1457
1458 /* Preamble */
1459 mii_send_bits (dev, 0xffffffff, 32);
1460 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1461 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1462 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1463 mii_send_bits (dev, cmd, 32);
1464 /* End cycle */
1465 mii_getbit (dev);
1466 return 0;
1467 }
1468 static int
mii_wait_link(struct net_device * dev,int wait)1469 mii_wait_link (struct net_device *dev, int wait)
1470 {
1471 __u16 bmsr;
1472 int phy_addr;
1473 struct netdev_private *np;
1474
1475 np = netdev_priv(dev);
1476 phy_addr = np->phy_addr;
1477
1478 do {
1479 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1480 if (bmsr & BMSR_LSTATUS)
1481 return 0;
1482 mdelay (1);
1483 } while (--wait > 0);
1484 return -1;
1485 }
1486 static int
mii_get_media(struct net_device * dev)1487 mii_get_media (struct net_device *dev)
1488 {
1489 __u16 negotiate;
1490 __u16 bmsr;
1491 __u16 mscr;
1492 __u16 mssr;
1493 int phy_addr;
1494 struct netdev_private *np;
1495
1496 np = netdev_priv(dev);
1497 phy_addr = np->phy_addr;
1498
1499 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1500 if (np->an_enable) {
1501 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1502 /* Auto-Negotiation not completed */
1503 return -1;
1504 }
1505 negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
1506 mii_read (dev, phy_addr, MII_LPA);
1507 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1508 mssr = mii_read (dev, phy_addr, MII_STAT1000);
1509 if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
1510 np->speed = 1000;
1511 np->full_duplex = 1;
1512 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1513 } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
1514 np->speed = 1000;
1515 np->full_duplex = 0;
1516 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1517 } else if (negotiate & ADVERTISE_100FULL) {
1518 np->speed = 100;
1519 np->full_duplex = 1;
1520 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1521 } else if (negotiate & ADVERTISE_100HALF) {
1522 np->speed = 100;
1523 np->full_duplex = 0;
1524 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1525 } else if (negotiate & ADVERTISE_10FULL) {
1526 np->speed = 10;
1527 np->full_duplex = 1;
1528 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1529 } else if (negotiate & ADVERTISE_10HALF) {
1530 np->speed = 10;
1531 np->full_duplex = 0;
1532 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1533 }
1534 if (negotiate & ADVERTISE_PAUSE_CAP) {
1535 np->tx_flow &= 1;
1536 np->rx_flow &= 1;
1537 } else if (negotiate & ADVERTISE_PAUSE_ASYM) {
1538 np->tx_flow = 0;
1539 np->rx_flow &= 1;
1540 }
1541 /* else tx_flow, rx_flow = user select */
1542 } else {
1543 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1544 switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
1545 case BMCR_SPEED1000:
1546 printk (KERN_INFO "Operating at 1000 Mbps, ");
1547 break;
1548 case BMCR_SPEED100:
1549 printk (KERN_INFO "Operating at 100 Mbps, ");
1550 break;
1551 case 0:
1552 printk (KERN_INFO "Operating at 10 Mbps, ");
1553 }
1554 if (bmcr & BMCR_FULLDPLX) {
1555 printk (KERN_CONT "Full duplex\n");
1556 } else {
1557 printk (KERN_CONT "Half duplex\n");
1558 }
1559 }
1560 if (np->tx_flow)
1561 printk(KERN_INFO "Enable Tx Flow Control\n");
1562 else
1563 printk(KERN_INFO "Disable Tx Flow Control\n");
1564 if (np->rx_flow)
1565 printk(KERN_INFO "Enable Rx Flow Control\n");
1566 else
1567 printk(KERN_INFO "Disable Rx Flow Control\n");
1568
1569 return 0;
1570 }
1571
1572 static int
mii_set_media(struct net_device * dev)1573 mii_set_media (struct net_device *dev)
1574 {
1575 __u16 pscr;
1576 __u16 bmcr;
1577 __u16 bmsr;
1578 __u16 anar;
1579 int phy_addr;
1580 struct netdev_private *np;
1581 np = netdev_priv(dev);
1582 phy_addr = np->phy_addr;
1583
1584 /* Does user set speed? */
1585 if (np->an_enable) {
1586 /* Advertise capabilities */
1587 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1588 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1589 ~(ADVERTISE_100FULL | ADVERTISE_10FULL |
1590 ADVERTISE_100HALF | ADVERTISE_10HALF |
1591 ADVERTISE_100BASE4);
1592 if (bmsr & BMSR_100FULL)
1593 anar |= ADVERTISE_100FULL;
1594 if (bmsr & BMSR_100HALF)
1595 anar |= ADVERTISE_100HALF;
1596 if (bmsr & BMSR_100BASE4)
1597 anar |= ADVERTISE_100BASE4;
1598 if (bmsr & BMSR_10FULL)
1599 anar |= ADVERTISE_10FULL;
1600 if (bmsr & BMSR_10HALF)
1601 anar |= ADVERTISE_10HALF;
1602 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1603 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1604
1605 /* Enable Auto crossover */
1606 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1607 pscr |= 3 << 5; /* 11'b */
1608 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1609
1610 /* Soft reset PHY */
1611 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1612 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1613 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1614 mdelay(1);
1615 } else {
1616 /* Force speed setting */
1617 /* 1) Disable Auto crossover */
1618 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1619 pscr &= ~(3 << 5);
1620 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1621
1622 /* 2) PHY Reset */
1623 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1624 bmcr |= BMCR_RESET;
1625 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1626
1627 /* 3) Power Down */
1628 bmcr = 0x1940; /* must be 0x1940 */
1629 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1630 mdelay (100); /* wait a certain time */
1631
1632 /* 4) Advertise nothing */
1633 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1634
1635 /* 5) Set media and Power Up */
1636 bmcr = BMCR_PDOWN;
1637 if (np->speed == 100) {
1638 bmcr |= BMCR_SPEED100;
1639 printk (KERN_INFO "Manual 100 Mbps, ");
1640 } else if (np->speed == 10) {
1641 printk (KERN_INFO "Manual 10 Mbps, ");
1642 }
1643 if (np->full_duplex) {
1644 bmcr |= BMCR_FULLDPLX;
1645 printk (KERN_CONT "Full duplex\n");
1646 } else {
1647 printk (KERN_CONT "Half duplex\n");
1648 }
1649 #if 0
1650 /* Set 1000BaseT Master/Slave setting */
1651 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1652 mscr |= MII_MSCR_CFG_ENABLE;
1653 mscr &= ~MII_MSCR_CFG_VALUE = 0;
1654 #endif
1655 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1656 mdelay(10);
1657 }
1658 return 0;
1659 }
1660
1661 static int
mii_get_media_pcs(struct net_device * dev)1662 mii_get_media_pcs (struct net_device *dev)
1663 {
1664 __u16 negotiate;
1665 __u16 bmsr;
1666 int phy_addr;
1667 struct netdev_private *np;
1668
1669 np = netdev_priv(dev);
1670 phy_addr = np->phy_addr;
1671
1672 bmsr = mii_read (dev, phy_addr, PCS_BMSR);
1673 if (np->an_enable) {
1674 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1675 /* Auto-Negotiation not completed */
1676 return -1;
1677 }
1678 negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
1679 mii_read (dev, phy_addr, PCS_ANLPAR);
1680 np->speed = 1000;
1681 if (negotiate & PCS_ANAR_FULL_DUPLEX) {
1682 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1683 np->full_duplex = 1;
1684 } else {
1685 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1686 np->full_duplex = 0;
1687 }
1688 if (negotiate & PCS_ANAR_PAUSE) {
1689 np->tx_flow &= 1;
1690 np->rx_flow &= 1;
1691 } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
1692 np->tx_flow = 0;
1693 np->rx_flow &= 1;
1694 }
1695 /* else tx_flow, rx_flow = user select */
1696 } else {
1697 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
1698 printk (KERN_INFO "Operating at 1000 Mbps, ");
1699 if (bmcr & BMCR_FULLDPLX) {
1700 printk (KERN_CONT "Full duplex\n");
1701 } else {
1702 printk (KERN_CONT "Half duplex\n");
1703 }
1704 }
1705 if (np->tx_flow)
1706 printk(KERN_INFO "Enable Tx Flow Control\n");
1707 else
1708 printk(KERN_INFO "Disable Tx Flow Control\n");
1709 if (np->rx_flow)
1710 printk(KERN_INFO "Enable Rx Flow Control\n");
1711 else
1712 printk(KERN_INFO "Disable Rx Flow Control\n");
1713
1714 return 0;
1715 }
1716
1717 static int
mii_set_media_pcs(struct net_device * dev)1718 mii_set_media_pcs (struct net_device *dev)
1719 {
1720 __u16 bmcr;
1721 __u16 esr;
1722 __u16 anar;
1723 int phy_addr;
1724 struct netdev_private *np;
1725 np = netdev_priv(dev);
1726 phy_addr = np->phy_addr;
1727
1728 /* Auto-Negotiation? */
1729 if (np->an_enable) {
1730 /* Advertise capabilities */
1731 esr = mii_read (dev, phy_addr, PCS_ESR);
1732 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1733 ~PCS_ANAR_HALF_DUPLEX &
1734 ~PCS_ANAR_FULL_DUPLEX;
1735 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
1736 anar |= PCS_ANAR_HALF_DUPLEX;
1737 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
1738 anar |= PCS_ANAR_FULL_DUPLEX;
1739 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
1740 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1741
1742 /* Soft reset PHY */
1743 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1744 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1745 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1746 mdelay(1);
1747 } else {
1748 /* Force speed setting */
1749 /* PHY Reset */
1750 bmcr = BMCR_RESET;
1751 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1752 mdelay(10);
1753 if (np->full_duplex) {
1754 bmcr = BMCR_FULLDPLX;
1755 printk (KERN_INFO "Manual full duplex\n");
1756 } else {
1757 bmcr = 0;
1758 printk (KERN_INFO "Manual half duplex\n");
1759 }
1760 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1761 mdelay(10);
1762
1763 /* Advertise nothing */
1764 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1765 }
1766 return 0;
1767 }
1768
1769
1770 static int
rio_close(struct net_device * dev)1771 rio_close (struct net_device *dev)
1772 {
1773 struct netdev_private *np = netdev_priv(dev);
1774 struct pci_dev *pdev = np->pdev;
1775
1776 netif_stop_queue (dev);
1777
1778 rio_hw_stop(dev);
1779
1780 free_irq(pdev->irq, dev);
1781 del_timer_sync (&np->timer);
1782
1783 free_list(dev);
1784
1785 return 0;
1786 }
1787
1788 static void
rio_remove1(struct pci_dev * pdev)1789 rio_remove1 (struct pci_dev *pdev)
1790 {
1791 struct net_device *dev = pci_get_drvdata (pdev);
1792
1793 if (dev) {
1794 struct netdev_private *np = netdev_priv(dev);
1795
1796 unregister_netdev (dev);
1797 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
1798 np->rx_ring_dma);
1799 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
1800 np->tx_ring_dma);
1801 #ifdef MEM_MAPPING
1802 pci_iounmap(pdev, np->ioaddr);
1803 #endif
1804 pci_iounmap(pdev, np->eeprom_addr);
1805 free_netdev (dev);
1806 pci_release_regions (pdev);
1807 pci_disable_device (pdev);
1808 }
1809 }
1810
1811 #ifdef CONFIG_PM_SLEEP
rio_suspend(struct device * device)1812 static int rio_suspend(struct device *device)
1813 {
1814 struct net_device *dev = dev_get_drvdata(device);
1815 struct netdev_private *np = netdev_priv(dev);
1816
1817 if (!netif_running(dev))
1818 return 0;
1819
1820 netif_device_detach(dev);
1821 del_timer_sync(&np->timer);
1822 rio_hw_stop(dev);
1823
1824 return 0;
1825 }
1826
rio_resume(struct device * device)1827 static int rio_resume(struct device *device)
1828 {
1829 struct net_device *dev = dev_get_drvdata(device);
1830 struct netdev_private *np = netdev_priv(dev);
1831
1832 if (!netif_running(dev))
1833 return 0;
1834
1835 rio_reset_ring(np);
1836 rio_hw_init(dev);
1837 np->timer.expires = jiffies + 1 * HZ;
1838 add_timer(&np->timer);
1839 netif_device_attach(dev);
1840 dl2k_enable_int(np);
1841
1842 return 0;
1843 }
1844
1845 static DEFINE_SIMPLE_DEV_PM_OPS(rio_pm_ops, rio_suspend, rio_resume);
1846 #define RIO_PM_OPS (&rio_pm_ops)
1847
1848 #else
1849
1850 #define RIO_PM_OPS NULL
1851
1852 #endif /* CONFIG_PM_SLEEP */
1853
1854 static struct pci_driver rio_driver = {
1855 .name = "dl2k",
1856 .id_table = rio_pci_tbl,
1857 .probe = rio_probe1,
1858 .remove = rio_remove1,
1859 .driver.pm = RIO_PM_OPS,
1860 };
1861
1862 module_pci_driver(rio_driver);
1863
1864 /* Read Documentation/networking/device_drivers/ethernet/dlink/dl2k.rst. */
1865