xref: /linux/drivers/net/wireless/intel/iwlwifi/fw/dbg.c (revision f315296c92fd4b7716bdea17f727ab431891dc3b)
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3  * Copyright (C) 2005-2014, 2018-2024 Intel Corporation
4  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5  * Copyright (C) 2015-2017 Intel Deutschland GmbH
6  */
7 #include <linux/devcoredump.h>
8 #include "iwl-drv.h"
9 #include "runtime.h"
10 #include "dbg.h"
11 #include "debugfs.h"
12 #include "iwl-io.h"
13 #include "iwl-prph.h"
14 #include "iwl-csr.h"
15 #include "iwl-fh.h"
16 /**
17  * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump
18  *
19  * @fwrt_ptr: pointer to the buffer coming from fwrt
20  * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the
21  *	transport's data.
22  * @fwrt_len: length of the valid data in fwrt_ptr
23  */
24 struct iwl_fw_dump_ptrs {
25 	struct iwl_trans_dump_data *trans_ptr;
26 	void *fwrt_ptr;
27 	u32 fwrt_len;
28 };
29 
30 #define RADIO_REG_MAX_READ 0x2ad
iwl_read_radio_regs(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data)31 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt,
32 				struct iwl_fw_error_dump_data **dump_data)
33 {
34 	u8 *pos = (void *)(*dump_data)->data;
35 	int i;
36 
37 	IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n");
38 
39 	if (!iwl_trans_grab_nic_access(fwrt->trans))
40 		return;
41 
42 	(*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG);
43 	(*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ);
44 
45 	for (i = 0; i < RADIO_REG_MAX_READ; i++) {
46 		u32 rd_cmd = RADIO_RSP_RD_CMD;
47 
48 		rd_cmd |= i << RADIO_RSP_ADDR_POS;
49 		iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd);
50 		*pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT);
51 
52 		pos++;
53 	}
54 
55 	*dump_data = iwl_fw_error_next_data(*dump_data);
56 
57 	iwl_trans_release_nic_access(fwrt->trans);
58 }
59 
iwl_fwrt_dump_rxf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data,int size,u32 offset,int fifo_num)60 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt,
61 			      struct iwl_fw_error_dump_data **dump_data,
62 			      int size, u32 offset, int fifo_num)
63 {
64 	struct iwl_fw_error_dump_fifo *fifo_hdr;
65 	u32 *fifo_data;
66 	u32 fifo_len;
67 	int i;
68 
69 	fifo_hdr = (void *)(*dump_data)->data;
70 	fifo_data = (void *)fifo_hdr->data;
71 	fifo_len = size;
72 
73 	/* No need to try to read the data if the length is 0 */
74 	if (fifo_len == 0)
75 		return;
76 
77 	/* Add a TLV for the RXF */
78 	(*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF);
79 	(*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
80 
81 	fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
82 	fifo_hdr->available_bytes =
83 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
84 						RXF_RD_D_SPACE + offset));
85 	fifo_hdr->wr_ptr =
86 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
87 						RXF_RD_WR_PTR + offset));
88 	fifo_hdr->rd_ptr =
89 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
90 						RXF_RD_RD_PTR + offset));
91 	fifo_hdr->fence_ptr =
92 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
93 						RXF_RD_FENCE_PTR + offset));
94 	fifo_hdr->fence_mode =
95 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
96 						RXF_SET_FENCE_MODE + offset));
97 
98 	/* Lock fence */
99 	iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1);
100 	/* Set fence pointer to the same place like WR pointer */
101 	iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1);
102 	/* Set fence offset */
103 	iwl_trans_write_prph(fwrt->trans,
104 			     RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);
105 
106 	/* Read FIFO */
107 	fifo_len /= sizeof(u32); /* Size in DWORDS */
108 	for (i = 0; i < fifo_len; i++)
109 		fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
110 						 RXF_FIFO_RD_FENCE_INC +
111 						 offset);
112 	*dump_data = iwl_fw_error_next_data(*dump_data);
113 }
114 
iwl_fwrt_dump_txf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data,int size,u32 offset,int fifo_num)115 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt,
116 			      struct iwl_fw_error_dump_data **dump_data,
117 			      int size, u32 offset, int fifo_num)
118 {
119 	struct iwl_fw_error_dump_fifo *fifo_hdr;
120 	u32 *fifo_data;
121 	u32 fifo_len;
122 	int i;
123 
124 	fifo_hdr = (void *)(*dump_data)->data;
125 	fifo_data = (void *)fifo_hdr->data;
126 	fifo_len = size;
127 
128 	/* No need to try to read the data if the length is 0 */
129 	if (fifo_len == 0)
130 		return;
131 
132 	/* Add a TLV for the FIFO */
133 	(*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF);
134 	(*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
135 
136 	fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
137 	fifo_hdr->available_bytes =
138 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
139 						TXF_FIFO_ITEM_CNT + offset));
140 	fifo_hdr->wr_ptr =
141 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
142 						TXF_WR_PTR + offset));
143 	fifo_hdr->rd_ptr =
144 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
145 						TXF_RD_PTR + offset));
146 	fifo_hdr->fence_ptr =
147 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
148 						TXF_FENCE_PTR + offset));
149 	fifo_hdr->fence_mode =
150 		cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
151 						TXF_LOCK_FENCE + offset));
152 
153 	/* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
154 	iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset,
155 			     TXF_WR_PTR + offset);
156 
157 	/* Dummy-read to advance the read pointer to the head */
158 	iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset);
159 
160 	/* Read FIFO */
161 	for (i = 0; i < fifo_len / sizeof(u32); i++)
162 		fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
163 						  TXF_READ_MODIFY_DATA +
164 						  offset);
165 
166 	if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf)
167 		fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx,
168 					     fifo_data, fifo_len);
169 
170 	*dump_data = iwl_fw_error_next_data(*dump_data);
171 }
172 
iwl_fw_dump_rxf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data)173 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt,
174 			    struct iwl_fw_error_dump_data **dump_data)
175 {
176 	struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
177 
178 	IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n");
179 
180 	if (!iwl_trans_grab_nic_access(fwrt->trans))
181 		return;
182 
183 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) {
184 		/* Pull RXF1 */
185 		iwl_fwrt_dump_rxf(fwrt, dump_data,
186 				  cfg->lmac[0].rxfifo1_size, 0, 0);
187 		/* Pull RXF2 */
188 		iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size,
189 				  RXF_DIFF_FROM_PREV +
190 				  fwrt->trans->trans_cfg->umac_prph_offset, 1);
191 		/* Pull LMAC2 RXF1 */
192 		if (fwrt->smem_cfg.num_lmacs > 1)
193 			iwl_fwrt_dump_rxf(fwrt, dump_data,
194 					  cfg->lmac[1].rxfifo1_size,
195 					  LMAC2_PRPH_OFFSET, 2);
196 	}
197 
198 	iwl_trans_release_nic_access(fwrt->trans);
199 }
200 
iwl_fw_dump_txf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data)201 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
202 			    struct iwl_fw_error_dump_data **dump_data)
203 {
204 	struct iwl_fw_error_dump_fifo *fifo_hdr;
205 	struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
206 	u32 *fifo_data;
207 	u32 fifo_len;
208 	int i, j;
209 
210 	IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n");
211 
212 	if (!iwl_trans_grab_nic_access(fwrt->trans))
213 		return;
214 
215 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) {
216 		/* Pull TXF data from LMAC1 */
217 		for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) {
218 			/* Mark the number of TXF we're pulling now */
219 			iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i);
220 			iwl_fwrt_dump_txf(fwrt, dump_data,
221 					  cfg->lmac[0].txfifo_size[i], 0, i);
222 		}
223 
224 		/* Pull TXF data from LMAC2 */
225 		if (fwrt->smem_cfg.num_lmacs > 1) {
226 			for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries;
227 			     i++) {
228 				/* Mark the number of TXF we're pulling now */
229 				iwl_trans_write_prph(fwrt->trans,
230 						     TXF_LARC_NUM +
231 						     LMAC2_PRPH_OFFSET, i);
232 				iwl_fwrt_dump_txf(fwrt, dump_data,
233 						  cfg->lmac[1].txfifo_size[i],
234 						  LMAC2_PRPH_OFFSET,
235 						  i + cfg->num_txfifo_entries);
236 			}
237 		}
238 	}
239 
240 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
241 	    fw_has_capa(&fwrt->fw->ucode_capa,
242 			IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
243 		/* Pull UMAC internal TXF data from all TXFs */
244 		for (i = 0;
245 		     i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size);
246 		     i++) {
247 			fifo_hdr = (void *)(*dump_data)->data;
248 			fifo_data = (void *)fifo_hdr->data;
249 			fifo_len = fwrt->smem_cfg.internal_txfifo_size[i];
250 
251 			/* No need to try to read the data if the length is 0 */
252 			if (fifo_len == 0)
253 				continue;
254 
255 			/* Add a TLV for the internal FIFOs */
256 			(*dump_data)->type =
257 				cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF);
258 			(*dump_data)->len =
259 				cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
260 
261 			fifo_hdr->fifo_num = cpu_to_le32(i);
262 
263 			/* Mark the number of TXF we're pulling now */
264 			iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i +
265 				fwrt->smem_cfg.num_txfifo_entries);
266 
267 			fifo_hdr->available_bytes =
268 				cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
269 								TXF_CPU2_FIFO_ITEM_CNT));
270 			fifo_hdr->wr_ptr =
271 				cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
272 								TXF_CPU2_WR_PTR));
273 			fifo_hdr->rd_ptr =
274 				cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
275 								TXF_CPU2_RD_PTR));
276 			fifo_hdr->fence_ptr =
277 				cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
278 								TXF_CPU2_FENCE_PTR));
279 			fifo_hdr->fence_mode =
280 				cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
281 								TXF_CPU2_LOCK_FENCE));
282 
283 			/* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */
284 			iwl_trans_write_prph(fwrt->trans,
285 					     TXF_CPU2_READ_MODIFY_ADDR,
286 					     TXF_CPU2_WR_PTR);
287 
288 			/* Dummy-read to advance the read pointer to head */
289 			iwl_trans_read_prph(fwrt->trans,
290 					    TXF_CPU2_READ_MODIFY_DATA);
291 
292 			/* Read FIFO */
293 			fifo_len /= sizeof(u32); /* Size in DWORDS */
294 			for (j = 0; j < fifo_len; j++)
295 				fifo_data[j] =
296 					iwl_trans_read_prph(fwrt->trans,
297 							    TXF_CPU2_READ_MODIFY_DATA);
298 			*dump_data = iwl_fw_error_next_data(*dump_data);
299 		}
300 	}
301 
302 	iwl_trans_release_nic_access(fwrt->trans);
303 }
304 
305 struct iwl_prph_range {
306 	u32 start, end;
307 };
308 
309 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = {
310 	{ .start = 0x00a00000, .end = 0x00a00000 },
311 	{ .start = 0x00a0000c, .end = 0x00a00024 },
312 	{ .start = 0x00a0002c, .end = 0x00a0003c },
313 	{ .start = 0x00a00410, .end = 0x00a00418 },
314 	{ .start = 0x00a00420, .end = 0x00a00420 },
315 	{ .start = 0x00a00428, .end = 0x00a00428 },
316 	{ .start = 0x00a00430, .end = 0x00a0043c },
317 	{ .start = 0x00a00444, .end = 0x00a00444 },
318 	{ .start = 0x00a004c0, .end = 0x00a004cc },
319 	{ .start = 0x00a004d8, .end = 0x00a004d8 },
320 	{ .start = 0x00a004e0, .end = 0x00a004f0 },
321 	{ .start = 0x00a00840, .end = 0x00a00840 },
322 	{ .start = 0x00a00850, .end = 0x00a00858 },
323 	{ .start = 0x00a01004, .end = 0x00a01008 },
324 	{ .start = 0x00a01010, .end = 0x00a01010 },
325 	{ .start = 0x00a01018, .end = 0x00a01018 },
326 	{ .start = 0x00a01024, .end = 0x00a01024 },
327 	{ .start = 0x00a0102c, .end = 0x00a01034 },
328 	{ .start = 0x00a0103c, .end = 0x00a01040 },
329 	{ .start = 0x00a01048, .end = 0x00a01094 },
330 	{ .start = 0x00a01c00, .end = 0x00a01c20 },
331 	{ .start = 0x00a01c58, .end = 0x00a01c58 },
332 	{ .start = 0x00a01c7c, .end = 0x00a01c7c },
333 	{ .start = 0x00a01c28, .end = 0x00a01c54 },
334 	{ .start = 0x00a01c5c, .end = 0x00a01c5c },
335 	{ .start = 0x00a01c60, .end = 0x00a01cdc },
336 	{ .start = 0x00a01ce0, .end = 0x00a01d0c },
337 	{ .start = 0x00a01d18, .end = 0x00a01d20 },
338 	{ .start = 0x00a01d2c, .end = 0x00a01d30 },
339 	{ .start = 0x00a01d40, .end = 0x00a01d5c },
340 	{ .start = 0x00a01d80, .end = 0x00a01d80 },
341 	{ .start = 0x00a01d98, .end = 0x00a01d9c },
342 	{ .start = 0x00a01da8, .end = 0x00a01da8 },
343 	{ .start = 0x00a01db8, .end = 0x00a01df4 },
344 	{ .start = 0x00a01dc0, .end = 0x00a01dfc },
345 	{ .start = 0x00a01e00, .end = 0x00a01e2c },
346 	{ .start = 0x00a01e40, .end = 0x00a01e60 },
347 	{ .start = 0x00a01e68, .end = 0x00a01e6c },
348 	{ .start = 0x00a01e74, .end = 0x00a01e74 },
349 	{ .start = 0x00a01e84, .end = 0x00a01e90 },
350 	{ .start = 0x00a01e9c, .end = 0x00a01ec4 },
351 	{ .start = 0x00a01ed0, .end = 0x00a01ee0 },
352 	{ .start = 0x00a01f00, .end = 0x00a01f1c },
353 	{ .start = 0x00a01f44, .end = 0x00a01ffc },
354 	{ .start = 0x00a02000, .end = 0x00a02048 },
355 	{ .start = 0x00a02068, .end = 0x00a020f0 },
356 	{ .start = 0x00a02100, .end = 0x00a02118 },
357 	{ .start = 0x00a02140, .end = 0x00a0214c },
358 	{ .start = 0x00a02168, .end = 0x00a0218c },
359 	{ .start = 0x00a021c0, .end = 0x00a021c0 },
360 	{ .start = 0x00a02400, .end = 0x00a02410 },
361 	{ .start = 0x00a02418, .end = 0x00a02420 },
362 	{ .start = 0x00a02428, .end = 0x00a0242c },
363 	{ .start = 0x00a02434, .end = 0x00a02434 },
364 	{ .start = 0x00a02440, .end = 0x00a02460 },
365 	{ .start = 0x00a02468, .end = 0x00a024b0 },
366 	{ .start = 0x00a024c8, .end = 0x00a024cc },
367 	{ .start = 0x00a02500, .end = 0x00a02504 },
368 	{ .start = 0x00a0250c, .end = 0x00a02510 },
369 	{ .start = 0x00a02540, .end = 0x00a02554 },
370 	{ .start = 0x00a02580, .end = 0x00a025f4 },
371 	{ .start = 0x00a02600, .end = 0x00a0260c },
372 	{ .start = 0x00a02648, .end = 0x00a02650 },
373 	{ .start = 0x00a02680, .end = 0x00a02680 },
374 	{ .start = 0x00a026c0, .end = 0x00a026d0 },
375 	{ .start = 0x00a02700, .end = 0x00a0270c },
376 	{ .start = 0x00a02804, .end = 0x00a02804 },
377 	{ .start = 0x00a02818, .end = 0x00a0281c },
378 	{ .start = 0x00a02c00, .end = 0x00a02db4 },
379 	{ .start = 0x00a02df4, .end = 0x00a02fb0 },
380 	{ .start = 0x00a03000, .end = 0x00a03014 },
381 	{ .start = 0x00a0301c, .end = 0x00a0302c },
382 	{ .start = 0x00a03034, .end = 0x00a03038 },
383 	{ .start = 0x00a03040, .end = 0x00a03048 },
384 	{ .start = 0x00a03060, .end = 0x00a03068 },
385 	{ .start = 0x00a03070, .end = 0x00a03074 },
386 	{ .start = 0x00a0307c, .end = 0x00a0307c },
387 	{ .start = 0x00a03080, .end = 0x00a03084 },
388 	{ .start = 0x00a0308c, .end = 0x00a03090 },
389 	{ .start = 0x00a03098, .end = 0x00a03098 },
390 	{ .start = 0x00a030a0, .end = 0x00a030a0 },
391 	{ .start = 0x00a030a8, .end = 0x00a030b4 },
392 	{ .start = 0x00a030bc, .end = 0x00a030bc },
393 	{ .start = 0x00a030c0, .end = 0x00a0312c },
394 	{ .start = 0x00a03c00, .end = 0x00a03c5c },
395 	{ .start = 0x00a04400, .end = 0x00a04454 },
396 	{ .start = 0x00a04460, .end = 0x00a04474 },
397 	{ .start = 0x00a044c0, .end = 0x00a044ec },
398 	{ .start = 0x00a04500, .end = 0x00a04504 },
399 	{ .start = 0x00a04510, .end = 0x00a04538 },
400 	{ .start = 0x00a04540, .end = 0x00a04548 },
401 	{ .start = 0x00a04560, .end = 0x00a0457c },
402 	{ .start = 0x00a04590, .end = 0x00a04598 },
403 	{ .start = 0x00a045c0, .end = 0x00a045f4 },
404 };
405 
406 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = {
407 	{ .start = 0x00a05c00, .end = 0x00a05c18 },
408 	{ .start = 0x00a05400, .end = 0x00a056e8 },
409 	{ .start = 0x00a08000, .end = 0x00a098bc },
410 	{ .start = 0x00a02400, .end = 0x00a02758 },
411 	{ .start = 0x00a04764, .end = 0x00a0476c },
412 	{ .start = 0x00a04770, .end = 0x00a04774 },
413 	{ .start = 0x00a04620, .end = 0x00a04624 },
414 };
415 
416 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = {
417 	{ .start = 0x00a00000, .end = 0x00a00000 },
418 	{ .start = 0x00a0000c, .end = 0x00a00024 },
419 	{ .start = 0x00a0002c, .end = 0x00a00034 },
420 	{ .start = 0x00a0003c, .end = 0x00a0003c },
421 	{ .start = 0x00a00410, .end = 0x00a00418 },
422 	{ .start = 0x00a00420, .end = 0x00a00420 },
423 	{ .start = 0x00a00428, .end = 0x00a00428 },
424 	{ .start = 0x00a00430, .end = 0x00a0043c },
425 	{ .start = 0x00a00444, .end = 0x00a00444 },
426 	{ .start = 0x00a00840, .end = 0x00a00840 },
427 	{ .start = 0x00a00850, .end = 0x00a00858 },
428 	{ .start = 0x00a01004, .end = 0x00a01008 },
429 	{ .start = 0x00a01010, .end = 0x00a01010 },
430 	{ .start = 0x00a01018, .end = 0x00a01018 },
431 	{ .start = 0x00a01024, .end = 0x00a01024 },
432 	{ .start = 0x00a0102c, .end = 0x00a01034 },
433 	{ .start = 0x00a0103c, .end = 0x00a01040 },
434 	{ .start = 0x00a01048, .end = 0x00a01050 },
435 	{ .start = 0x00a01058, .end = 0x00a01058 },
436 	{ .start = 0x00a01060, .end = 0x00a01070 },
437 	{ .start = 0x00a0108c, .end = 0x00a0108c },
438 	{ .start = 0x00a01c20, .end = 0x00a01c28 },
439 	{ .start = 0x00a01d10, .end = 0x00a01d10 },
440 	{ .start = 0x00a01e28, .end = 0x00a01e2c },
441 	{ .start = 0x00a01e60, .end = 0x00a01e60 },
442 	{ .start = 0x00a01e80, .end = 0x00a01e80 },
443 	{ .start = 0x00a01ea0, .end = 0x00a01ea0 },
444 	{ .start = 0x00a02000, .end = 0x00a0201c },
445 	{ .start = 0x00a02024, .end = 0x00a02024 },
446 	{ .start = 0x00a02040, .end = 0x00a02048 },
447 	{ .start = 0x00a020c0, .end = 0x00a020e0 },
448 	{ .start = 0x00a02400, .end = 0x00a02404 },
449 	{ .start = 0x00a0240c, .end = 0x00a02414 },
450 	{ .start = 0x00a0241c, .end = 0x00a0243c },
451 	{ .start = 0x00a02448, .end = 0x00a024bc },
452 	{ .start = 0x00a024c4, .end = 0x00a024cc },
453 	{ .start = 0x00a02508, .end = 0x00a02508 },
454 	{ .start = 0x00a02510, .end = 0x00a02514 },
455 	{ .start = 0x00a0251c, .end = 0x00a0251c },
456 	{ .start = 0x00a0252c, .end = 0x00a0255c },
457 	{ .start = 0x00a02564, .end = 0x00a025a0 },
458 	{ .start = 0x00a025a8, .end = 0x00a025b4 },
459 	{ .start = 0x00a025c0, .end = 0x00a025c0 },
460 	{ .start = 0x00a025e8, .end = 0x00a025f4 },
461 	{ .start = 0x00a02c08, .end = 0x00a02c18 },
462 	{ .start = 0x00a02c2c, .end = 0x00a02c38 },
463 	{ .start = 0x00a02c68, .end = 0x00a02c78 },
464 	{ .start = 0x00a03000, .end = 0x00a03000 },
465 	{ .start = 0x00a03010, .end = 0x00a03014 },
466 	{ .start = 0x00a0301c, .end = 0x00a0302c },
467 	{ .start = 0x00a03034, .end = 0x00a03038 },
468 	{ .start = 0x00a03040, .end = 0x00a03044 },
469 	{ .start = 0x00a03060, .end = 0x00a03068 },
470 	{ .start = 0x00a03070, .end = 0x00a03070 },
471 	{ .start = 0x00a0307c, .end = 0x00a03084 },
472 	{ .start = 0x00a0308c, .end = 0x00a03090 },
473 	{ .start = 0x00a03098, .end = 0x00a03098 },
474 	{ .start = 0x00a030a0, .end = 0x00a030a0 },
475 	{ .start = 0x00a030a8, .end = 0x00a030b4 },
476 	{ .start = 0x00a030bc, .end = 0x00a030c0 },
477 	{ .start = 0x00a030c8, .end = 0x00a030f4 },
478 	{ .start = 0x00a03100, .end = 0x00a0312c },
479 	{ .start = 0x00a03c00, .end = 0x00a03c5c },
480 	{ .start = 0x00a04400, .end = 0x00a04454 },
481 	{ .start = 0x00a04460, .end = 0x00a04474 },
482 	{ .start = 0x00a044c0, .end = 0x00a044ec },
483 	{ .start = 0x00a04500, .end = 0x00a04504 },
484 	{ .start = 0x00a04510, .end = 0x00a04538 },
485 	{ .start = 0x00a04540, .end = 0x00a04548 },
486 	{ .start = 0x00a04560, .end = 0x00a04560 },
487 	{ .start = 0x00a04570, .end = 0x00a0457c },
488 	{ .start = 0x00a04590, .end = 0x00a04590 },
489 	{ .start = 0x00a04598, .end = 0x00a04598 },
490 	{ .start = 0x00a045c0, .end = 0x00a045f4 },
491 	{ .start = 0x00a05c18, .end = 0x00a05c1c },
492 	{ .start = 0x00a0c000, .end = 0x00a0c018 },
493 	{ .start = 0x00a0c020, .end = 0x00a0c028 },
494 	{ .start = 0x00a0c038, .end = 0x00a0c094 },
495 	{ .start = 0x00a0c0c0, .end = 0x00a0c104 },
496 	{ .start = 0x00a0c10c, .end = 0x00a0c118 },
497 	{ .start = 0x00a0c150, .end = 0x00a0c174 },
498 	{ .start = 0x00a0c17c, .end = 0x00a0c188 },
499 	{ .start = 0x00a0c190, .end = 0x00a0c198 },
500 	{ .start = 0x00a0c1a0, .end = 0x00a0c1a8 },
501 	{ .start = 0x00a0c1b0, .end = 0x00a0c1b8 },
502 };
503 
504 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = {
505 	{ .start = 0x00d03c00, .end = 0x00d03c64 },
506 	{ .start = 0x00d05c18, .end = 0x00d05c1c },
507 	{ .start = 0x00d0c000, .end = 0x00d0c174 },
508 };
509 
iwl_read_prph_block(struct iwl_trans * trans,u32 start,u32 len_bytes,__le32 * data)510 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start,
511 				u32 len_bytes, __le32 *data)
512 {
513 	u32 i;
514 
515 	for (i = 0; i < len_bytes; i += 4)
516 		*data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i));
517 }
518 
iwl_dump_prph(struct iwl_fw_runtime * fwrt,const struct iwl_prph_range * iwl_prph_dump_addr,u32 range_len,void * ptr)519 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt,
520 			  const struct iwl_prph_range *iwl_prph_dump_addr,
521 			  u32 range_len, void *ptr)
522 {
523 	struct iwl_fw_error_dump_prph *prph;
524 	struct iwl_trans *trans = fwrt->trans;
525 	struct iwl_fw_error_dump_data **data =
526 		(struct iwl_fw_error_dump_data **)ptr;
527 	u32 i;
528 
529 	if (!data)
530 		return;
531 
532 	IWL_DEBUG_INFO(trans, "WRT PRPH dump\n");
533 
534 	if (!iwl_trans_grab_nic_access(trans))
535 		return;
536 
537 	for (i = 0; i < range_len; i++) {
538 		/* The range includes both boundaries */
539 		int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
540 			 iwl_prph_dump_addr[i].start + 4;
541 
542 		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
543 		(*data)->len = cpu_to_le32(sizeof(*prph) +
544 					num_bytes_in_chunk);
545 		prph = (void *)(*data)->data;
546 		prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
547 
548 		iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start,
549 				    /* our range is inclusive, hence + 4 */
550 				    iwl_prph_dump_addr[i].end -
551 				    iwl_prph_dump_addr[i].start + 4,
552 				    (void *)prph->data);
553 
554 		*data = iwl_fw_error_next_data(*data);
555 	}
556 
557 	iwl_trans_release_nic_access(trans);
558 }
559 
560 /*
561  * alloc_sgtable - allocates (chained) scatterlist in the given size,
562  *	fills it with pages and returns it
563  * @size: the size (in bytes) of the table
564  */
alloc_sgtable(ssize_t size)565 static struct scatterlist *alloc_sgtable(ssize_t size)
566 {
567 	struct scatterlist *result = NULL, *prev;
568 	int nents, i, n_prev;
569 
570 	nents = DIV_ROUND_UP(size, PAGE_SIZE);
571 
572 #define N_ENTRIES_PER_PAGE (PAGE_SIZE / sizeof(*result))
573 	/*
574 	 * We need an additional entry for table chaining,
575 	 * this ensures the loop can finish i.e. we can
576 	 * fit at least two entries per page (obviously,
577 	 * many more really fit.)
578 	 */
579 	BUILD_BUG_ON(N_ENTRIES_PER_PAGE < 2);
580 
581 	while (nents > 0) {
582 		struct scatterlist *new, *iter;
583 		int n_fill, n_alloc;
584 
585 		if (nents <= N_ENTRIES_PER_PAGE) {
586 			/* last needed table */
587 			n_fill = nents;
588 			n_alloc = nents;
589 			nents = 0;
590 		} else {
591 			/* fill a page with entries */
592 			n_alloc = N_ENTRIES_PER_PAGE;
593 			/* reserve one for chaining */
594 			n_fill = n_alloc - 1;
595 			nents -= n_fill;
596 		}
597 
598 		new = kcalloc(n_alloc, sizeof(*new), GFP_KERNEL);
599 		if (!new) {
600 			if (result)
601 				_devcd_free_sgtable(result);
602 			return NULL;
603 		}
604 		sg_init_table(new, n_alloc);
605 
606 		if (!result)
607 			result = new;
608 		else
609 			sg_chain(prev, n_prev, new);
610 		prev = new;
611 		n_prev = n_alloc;
612 
613 		for_each_sg(new, iter, n_fill, i) {
614 			struct page *new_page = alloc_page(GFP_KERNEL);
615 
616 			if (!new_page) {
617 				_devcd_free_sgtable(result);
618 				return NULL;
619 			}
620 
621 			sg_set_page(iter, new_page, PAGE_SIZE, 0);
622 		}
623 	}
624 
625 	return result;
626 }
627 
iwl_fw_get_prph_len(struct iwl_fw_runtime * fwrt,const struct iwl_prph_range * iwl_prph_dump_addr,u32 range_len,void * ptr)628 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt,
629 				const struct iwl_prph_range *iwl_prph_dump_addr,
630 				u32 range_len, void *ptr)
631 {
632 	u32 *prph_len = (u32 *)ptr;
633 	int i, num_bytes_in_chunk;
634 
635 	if (!prph_len)
636 		return;
637 
638 	for (i = 0; i < range_len; i++) {
639 		/* The range includes both boundaries */
640 		num_bytes_in_chunk =
641 			iwl_prph_dump_addr[i].end -
642 			iwl_prph_dump_addr[i].start + 4;
643 
644 		*prph_len += sizeof(struct iwl_fw_error_dump_data) +
645 			sizeof(struct iwl_fw_error_dump_prph) +
646 			num_bytes_in_chunk;
647 	}
648 }
649 
iwl_fw_prph_handler(struct iwl_fw_runtime * fwrt,void * ptr,void (* handler)(struct iwl_fw_runtime *,const struct iwl_prph_range *,u32,void *))650 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr,
651 				void (*handler)(struct iwl_fw_runtime *,
652 						const struct iwl_prph_range *,
653 						u32, void *))
654 {
655 	u32 range_len;
656 
657 	if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
658 		range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210);
659 		handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr);
660 	} else if (fwrt->trans->trans_cfg->device_family >=
661 		   IWL_DEVICE_FAMILY_22000) {
662 		range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000);
663 		handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr);
664 	} else {
665 		range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm);
666 		handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr);
667 
668 		if (fwrt->trans->trans_cfg->mq_rx_supported) {
669 			range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000);
670 			handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr);
671 		}
672 	}
673 }
674 
iwl_fw_dump_mem(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data,u32 len,u32 ofs,u32 type)675 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt,
676 			    struct iwl_fw_error_dump_data **dump_data,
677 			    u32 len, u32 ofs, u32 type)
678 {
679 	struct iwl_fw_error_dump_mem *dump_mem;
680 
681 	if (!len)
682 		return;
683 
684 	(*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
685 	(*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem));
686 	dump_mem = (void *)(*dump_data)->data;
687 	dump_mem->type = cpu_to_le32(type);
688 	dump_mem->offset = cpu_to_le32(ofs);
689 	iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len);
690 	*dump_data = iwl_fw_error_next_data(*dump_data);
691 
692 	if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
693 		fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs,
694 					     dump_mem->data, len);
695 
696 	IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type);
697 }
698 
699 #define ADD_LEN(len, item_len, const_len) \
700 	do {size_t item = item_len; len += (!!item) * const_len + item; } \
701 	while (0)
702 
iwl_fw_rxf_len(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_shared_mem_cfg * mem_cfg)703 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt,
704 			  struct iwl_fwrt_shared_mem_cfg *mem_cfg)
705 {
706 	size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) +
707 			 sizeof(struct iwl_fw_error_dump_fifo);
708 	u32 fifo_len = 0;
709 	int i;
710 
711 	if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF))
712 		return 0;
713 
714 	/* Count RXF2 size */
715 	ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len);
716 
717 	/* Count RXF1 sizes */
718 	if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC))
719 		mem_cfg->num_lmacs = MAX_NUM_LMAC;
720 
721 	for (i = 0; i < mem_cfg->num_lmacs; i++)
722 		ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len);
723 
724 	return fifo_len;
725 }
726 
iwl_fw_txf_len(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_shared_mem_cfg * mem_cfg)727 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt,
728 			  struct iwl_fwrt_shared_mem_cfg *mem_cfg)
729 {
730 	size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) +
731 			 sizeof(struct iwl_fw_error_dump_fifo);
732 	u32 fifo_len = 0;
733 	int i;
734 
735 	if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF))
736 		goto dump_internal_txf;
737 
738 	/* Count TXF sizes */
739 	if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC))
740 		mem_cfg->num_lmacs = MAX_NUM_LMAC;
741 
742 	for (i = 0; i < mem_cfg->num_lmacs; i++) {
743 		int j;
744 
745 		for (j = 0; j < mem_cfg->num_txfifo_entries; j++)
746 			ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j],
747 				hdr_len);
748 	}
749 
750 dump_internal_txf:
751 	if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
752 	      fw_has_capa(&fwrt->fw->ucode_capa,
753 			  IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)))
754 		goto out;
755 
756 	for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++)
757 		ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len);
758 
759 out:
760 	return fifo_len;
761 }
762 
iwl_dump_paging(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** data)763 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt,
764 			    struct iwl_fw_error_dump_data **data)
765 {
766 	int i;
767 
768 	IWL_DEBUG_INFO(fwrt, "WRT paging dump\n");
769 	for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) {
770 		struct iwl_fw_error_dump_paging *paging;
771 		struct page *pages =
772 			fwrt->fw_paging_db[i].fw_paging_block;
773 		dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys;
774 
775 		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
776 		(*data)->len = cpu_to_le32(sizeof(*paging) +
777 					     PAGING_BLOCK_SIZE);
778 		paging =  (void *)(*data)->data;
779 		paging->index = cpu_to_le32(i);
780 		dma_sync_single_for_cpu(fwrt->trans->dev, addr,
781 					PAGING_BLOCK_SIZE,
782 					DMA_BIDIRECTIONAL);
783 		memcpy(paging->data, page_address(pages),
784 		       PAGING_BLOCK_SIZE);
785 		dma_sync_single_for_device(fwrt->trans->dev, addr,
786 					   PAGING_BLOCK_SIZE,
787 					   DMA_BIDIRECTIONAL);
788 		(*data) = iwl_fw_error_next_data(*data);
789 
790 		if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
791 			fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx,
792 						     fwrt->fw_paging_db[i].fw_offs,
793 						     paging->data,
794 						     PAGING_BLOCK_SIZE);
795 	}
796 }
797 
798 static struct iwl_fw_error_dump_file *
iwl_fw_error_dump_file(struct iwl_fw_runtime * fwrt,struct iwl_fw_dump_ptrs * fw_error_dump,struct iwl_fwrt_dump_data * data)799 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt,
800 		       struct iwl_fw_dump_ptrs *fw_error_dump,
801 		       struct iwl_fwrt_dump_data *data)
802 {
803 	struct iwl_fw_error_dump_file *dump_file;
804 	struct iwl_fw_error_dump_data *dump_data;
805 	struct iwl_fw_error_dump_info *dump_info;
806 	struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg;
807 	struct iwl_fw_error_dump_trigger_desc *dump_trig;
808 	u32 sram_len, sram_ofs;
809 	const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv;
810 	struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg;
811 	u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0;
812 	u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len;
813 	u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ?
814 				0 : fwrt->trans->cfg->dccm2_len;
815 	int i;
816 
817 	/* SRAM - include stack CCM if driver knows the values for it */
818 	if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) {
819 		const struct fw_img *img;
820 
821 		if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX)
822 			return NULL;
823 		img = &fwrt->fw->img[fwrt->cur_fw_img];
824 		sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset;
825 		sram_len = img->sec[IWL_UCODE_SECTION_DATA].len;
826 	} else {
827 		sram_ofs = fwrt->trans->cfg->dccm_offset;
828 		sram_len = fwrt->trans->cfg->dccm_len;
829 	}
830 
831 	/* reading RXF/TXF sizes */
832 	if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) {
833 		fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg);
834 		fifo_len += iwl_fw_txf_len(fwrt, mem_cfg);
835 
836 		/* Make room for PRPH registers */
837 		if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH))
838 			iwl_fw_prph_handler(fwrt, &prph_len,
839 					    iwl_fw_get_prph_len);
840 
841 		if (fwrt->trans->trans_cfg->device_family ==
842 		    IWL_DEVICE_FAMILY_7000 &&
843 		    iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG))
844 			radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ;
845 	}
846 
847 	file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len;
848 
849 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO))
850 		file_len += sizeof(*dump_data) + sizeof(*dump_info);
851 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG))
852 		file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg);
853 
854 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) {
855 		size_t hdr_len = sizeof(*dump_data) +
856 				 sizeof(struct iwl_fw_error_dump_mem);
857 
858 		/* Dump SRAM only if no mem_tlvs */
859 		if (!fwrt->fw->dbg.n_mem_tlv)
860 			ADD_LEN(file_len, sram_len, hdr_len);
861 
862 		/* Make room for all mem types that exist */
863 		ADD_LEN(file_len, smem_len, hdr_len);
864 		ADD_LEN(file_len, sram2_len, hdr_len);
865 
866 		for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++)
867 			ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len);
868 	}
869 
870 	/* Make room for fw's virtual image pages, if it exists */
871 	if (iwl_fw_dbg_is_paging_enabled(fwrt))
872 		file_len += fwrt->num_of_paging_blk *
873 			(sizeof(*dump_data) +
874 			 sizeof(struct iwl_fw_error_dump_paging) +
875 			 PAGING_BLOCK_SIZE);
876 
877 	if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
878 		file_len += sizeof(*dump_data) +
879 			fwrt->trans->cfg->d3_debug_data_length * 2;
880 	}
881 
882 	/* If we only want a monitor dump, reset the file length */
883 	if (data->monitor_only) {
884 		file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 +
885 			   sizeof(*dump_info) + sizeof(*dump_smem_cfg);
886 	}
887 
888 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) &&
889 	    data->desc)
890 		file_len += sizeof(*dump_data) + sizeof(*dump_trig) +
891 			data->desc->len;
892 
893 	dump_file = vzalloc(file_len);
894 	if (!dump_file)
895 		return NULL;
896 
897 	fw_error_dump->fwrt_ptr = dump_file;
898 
899 	dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER);
900 	dump_data = (void *)dump_file->data;
901 
902 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) {
903 		dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO);
904 		dump_data->len = cpu_to_le32(sizeof(*dump_info));
905 		dump_info = (void *)dump_data->data;
906 		dump_info->hw_type =
907 			cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev));
908 		dump_info->hw_step =
909 			cpu_to_le32(fwrt->trans->hw_rev_step);
910 		memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable,
911 		       sizeof(dump_info->fw_human_readable));
912 		strscpy_pad(dump_info->dev_human_readable, fwrt->trans->name,
913 			sizeof(dump_info->dev_human_readable));
914 		strscpy_pad(dump_info->bus_human_readable, fwrt->dev->bus->name,
915 			sizeof(dump_info->bus_human_readable));
916 		dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs;
917 		dump_info->lmac_err_id[0] =
918 			cpu_to_le32(fwrt->dump.lmac_err_id[0]);
919 		if (fwrt->smem_cfg.num_lmacs > 1)
920 			dump_info->lmac_err_id[1] =
921 				cpu_to_le32(fwrt->dump.lmac_err_id[1]);
922 		dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id);
923 
924 		dump_data = iwl_fw_error_next_data(dump_data);
925 	}
926 
927 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) {
928 		/* Dump shared memory configuration */
929 		dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG);
930 		dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg));
931 		dump_smem_cfg = (void *)dump_data->data;
932 		dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs);
933 		dump_smem_cfg->num_txfifo_entries =
934 			cpu_to_le32(mem_cfg->num_txfifo_entries);
935 		for (i = 0; i < MAX_NUM_LMAC; i++) {
936 			int j;
937 			u32 *txf_size = mem_cfg->lmac[i].txfifo_size;
938 
939 			for (j = 0; j < TX_FIFO_MAX_NUM; j++)
940 				dump_smem_cfg->lmac[i].txfifo_size[j] =
941 					cpu_to_le32(txf_size[j]);
942 			dump_smem_cfg->lmac[i].rxfifo1_size =
943 				cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size);
944 		}
945 		dump_smem_cfg->rxfifo2_size =
946 			cpu_to_le32(mem_cfg->rxfifo2_size);
947 		dump_smem_cfg->internal_txfifo_addr =
948 			cpu_to_le32(mem_cfg->internal_txfifo_addr);
949 		for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) {
950 			dump_smem_cfg->internal_txfifo_size[i] =
951 				cpu_to_le32(mem_cfg->internal_txfifo_size[i]);
952 		}
953 
954 		dump_data = iwl_fw_error_next_data(dump_data);
955 	}
956 
957 	/* We only dump the FIFOs if the FW is in error state */
958 	if (fifo_len) {
959 		iwl_fw_dump_rxf(fwrt, &dump_data);
960 		iwl_fw_dump_txf(fwrt, &dump_data);
961 	}
962 
963 	if (radio_len)
964 		iwl_read_radio_regs(fwrt, &dump_data);
965 
966 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) &&
967 	    data->desc) {
968 		dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO);
969 		dump_data->len = cpu_to_le32(sizeof(*dump_trig) +
970 					     data->desc->len);
971 		dump_trig = (void *)dump_data->data;
972 		memcpy(dump_trig, &data->desc->trig_desc,
973 		       sizeof(*dump_trig) + data->desc->len);
974 
975 		dump_data = iwl_fw_error_next_data(dump_data);
976 	}
977 
978 	/* In case we only want monitor dump, skip to dump trasport data */
979 	if (data->monitor_only)
980 		goto out;
981 
982 	if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) {
983 		const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem =
984 			fwrt->fw->dbg.mem_tlv;
985 
986 		if (!fwrt->fw->dbg.n_mem_tlv)
987 			iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs,
988 					IWL_FW_ERROR_DUMP_MEM_SRAM);
989 
990 		for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) {
991 			u32 len = le32_to_cpu(fw_dbg_mem[i].len);
992 			u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs);
993 
994 			iwl_fw_dump_mem(fwrt, &dump_data, len, ofs,
995 					le32_to_cpu(fw_dbg_mem[i].data_type));
996 		}
997 
998 		iwl_fw_dump_mem(fwrt, &dump_data, smem_len,
999 				fwrt->trans->cfg->smem_offset,
1000 				IWL_FW_ERROR_DUMP_MEM_SMEM);
1001 
1002 		iwl_fw_dump_mem(fwrt, &dump_data, sram2_len,
1003 				fwrt->trans->cfg->dccm2_offset,
1004 				IWL_FW_ERROR_DUMP_MEM_SRAM);
1005 	}
1006 
1007 	if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
1008 		u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr;
1009 		size_t data_size = fwrt->trans->cfg->d3_debug_data_length;
1010 
1011 		dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA);
1012 		dump_data->len = cpu_to_le32(data_size * 2);
1013 
1014 		memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size);
1015 
1016 		kfree(fwrt->dump.d3_debug_data);
1017 		fwrt->dump.d3_debug_data = NULL;
1018 
1019 		iwl_trans_read_mem_bytes(fwrt->trans, addr,
1020 					 dump_data->data + data_size,
1021 					 data_size);
1022 
1023 		if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
1024 			fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr,
1025 						     dump_data->data + data_size,
1026 						     data_size);
1027 
1028 		dump_data = iwl_fw_error_next_data(dump_data);
1029 	}
1030 
1031 	/* Dump fw's virtual image */
1032 	if (iwl_fw_dbg_is_paging_enabled(fwrt))
1033 		iwl_dump_paging(fwrt, &dump_data);
1034 
1035 	if (prph_len)
1036 		iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph);
1037 
1038 out:
1039 	dump_file->file_len = cpu_to_le32(file_len);
1040 	return dump_file;
1041 }
1042 
1043 /**
1044  * struct iwl_dump_ini_region_data - region data
1045  * @reg_tlv: region TLV
1046  * @dump_data: dump data
1047  */
1048 struct iwl_dump_ini_region_data {
1049 	struct iwl_ucode_tlv *reg_tlv;
1050 	struct iwl_fwrt_dump_data *dump_data;
1051 };
1052 
iwl_dump_ini_prph_mac_iter_common(struct iwl_fw_runtime * fwrt,void * range_ptr,u32 addr,__le32 size)1053 static int iwl_dump_ini_prph_mac_iter_common(struct iwl_fw_runtime *fwrt,
1054 					     void *range_ptr, u32 addr,
1055 					     __le32 size)
1056 {
1057 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1058 	__le32 *val = range->data;
1059 	int i;
1060 
1061 	range->internal_base_addr = cpu_to_le32(addr);
1062 	range->range_data_size = size;
1063 	for (i = 0; i < le32_to_cpu(size); i += 4)
1064 		*val++ = cpu_to_le32(iwl_read_prph(fwrt->trans, addr + i));
1065 
1066 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1067 }
1068 
1069 static int
iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1070 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt,
1071 			   struct iwl_dump_ini_region_data *reg_data,
1072 			   void *range_ptr, u32 range_len, int idx)
1073 {
1074 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1075 	u32 addr = le32_to_cpu(reg->addrs[idx]) +
1076 		   le32_to_cpu(reg->dev_addr.offset);
1077 
1078 	return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr,
1079 						 reg->dev_addr.size);
1080 }
1081 
1082 static int
iwl_dump_ini_prph_mac_block_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1083 iwl_dump_ini_prph_mac_block_iter(struct iwl_fw_runtime *fwrt,
1084 				 struct iwl_dump_ini_region_data *reg_data,
1085 				 void *range_ptr, u32 range_len, int idx)
1086 {
1087 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1088 	struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs;
1089 	u32 addr = le32_to_cpu(reg->dev_addr_range.offset) +
1090 		   le32_to_cpu(pairs[idx].addr);
1091 
1092 	return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr,
1093 						 pairs[idx].size);
1094 }
1095 
iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime * fwrt,void * range_ptr,u32 addr,__le32 size,__le32 offset)1096 static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime *fwrt,
1097 					     void *range_ptr, u32 addr,
1098 					     __le32 size, __le32 offset)
1099 {
1100 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1101 	__le32 *val = range->data;
1102 	u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1;
1103 	u32 indirect_rd_addr = WMAL_MRSPF_1;
1104 	u32 prph_val;
1105 	u32 dphy_state;
1106 	u32 dphy_addr;
1107 	int i;
1108 
1109 	range->internal_base_addr = cpu_to_le32(addr);
1110 	range->range_data_size = size;
1111 
1112 	if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
1113 		indirect_wr_addr = WMAL_INDRCT_CMD1;
1114 
1115 	indirect_wr_addr += le32_to_cpu(offset);
1116 	indirect_rd_addr += le32_to_cpu(offset);
1117 
1118 	if (!iwl_trans_grab_nic_access(fwrt->trans))
1119 		return -EBUSY;
1120 
1121 	dphy_addr = (offset) ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW;
1122 	dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr);
1123 
1124 	for (i = 0; i < le32_to_cpu(size); i += 4) {
1125 		if (dphy_state == HBUS_TIMEOUT ||
1126 		    (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) !=
1127 		    WFPM_PHYRF_STATE_ON) {
1128 			*val++ = cpu_to_le32(WFPM_DPHY_OFF);
1129 			continue;
1130 		}
1131 
1132 		iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr,
1133 				       WMAL_INDRCT_CMD(addr + i));
1134 		prph_val = iwl_read_prph_no_grab(fwrt->trans,
1135 						 indirect_rd_addr);
1136 		*val++ = cpu_to_le32(prph_val);
1137 	}
1138 
1139 	iwl_trans_release_nic_access(fwrt->trans);
1140 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1141 }
1142 
1143 static int
iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1144 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt,
1145 			   struct iwl_dump_ini_region_data *reg_data,
1146 			   void *range_ptr, u32 range_len, int idx)
1147 {
1148 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1149 	u32 addr = le32_to_cpu(reg->addrs[idx]);
1150 
1151 	return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr,
1152 						 reg->dev_addr.size,
1153 						 reg->dev_addr.offset);
1154 }
1155 
1156 static int
iwl_dump_ini_prph_phy_block_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1157 iwl_dump_ini_prph_phy_block_iter(struct iwl_fw_runtime *fwrt,
1158 				 struct iwl_dump_ini_region_data *reg_data,
1159 				 void *range_ptr, u32 range_len, int idx)
1160 {
1161 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1162 	struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs;
1163 	u32 addr = le32_to_cpu(pairs[idx].addr);
1164 
1165 	return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr,
1166 						 pairs[idx].size,
1167 						 reg->dev_addr_range.offset);
1168 }
1169 
iwl_dump_ini_csr_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1170 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt,
1171 				 struct iwl_dump_ini_region_data *reg_data,
1172 				 void *range_ptr, u32 range_len, int idx)
1173 {
1174 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1175 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1176 	__le32 *val = range->data;
1177 	u32 addr = le32_to_cpu(reg->addrs[idx]) +
1178 		   le32_to_cpu(reg->dev_addr.offset);
1179 	int i;
1180 
1181 	range->internal_base_addr = cpu_to_le32(addr);
1182 	range->range_data_size = reg->dev_addr.size;
1183 	for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4)
1184 		*val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i));
1185 
1186 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1187 }
1188 
iwl_dump_ini_config_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1189 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt,
1190 				    struct iwl_dump_ini_region_data *reg_data,
1191 				    void *range_ptr, u32 range_len, int idx)
1192 {
1193 	struct iwl_trans *trans = fwrt->trans;
1194 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1195 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1196 	__le32 *val = range->data;
1197 	u32 addr = le32_to_cpu(reg->addrs[idx]) +
1198 		   le32_to_cpu(reg->dev_addr.offset);
1199 	int i;
1200 
1201 	range->internal_base_addr = cpu_to_le32(addr);
1202 	range->range_data_size = reg->dev_addr.size;
1203 	for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1204 		int ret;
1205 		u32 tmp;
1206 
1207 		ret = iwl_trans_read_config32(trans, addr + i, &tmp);
1208 		if (ret < 0)
1209 			return ret;
1210 
1211 		*val++ = cpu_to_le32(tmp);
1212 	}
1213 
1214 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1215 }
1216 
iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1217 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt,
1218 				     struct iwl_dump_ini_region_data *reg_data,
1219 				     void *range_ptr, u32 range_len, int idx)
1220 {
1221 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1222 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1223 	u32 addr = le32_to_cpu(reg->addrs[idx]) +
1224 		   le32_to_cpu(reg->dev_addr.offset);
1225 
1226 	range->internal_base_addr = cpu_to_le32(addr);
1227 	range->range_data_size = reg->dev_addr.size;
1228 	iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1229 				 le32_to_cpu(reg->dev_addr.size));
1230 
1231 	if (reg->sub_type == IWL_FW_INI_REGION_DEVICE_MEMORY_SUBTYPE_HW_SMEM &&
1232 	    fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf)
1233 		fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx,
1234 					     range->data,
1235 					     le32_to_cpu(reg->dev_addr.size));
1236 
1237 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1238 }
1239 
_iwl_dump_ini_paging_iter(struct iwl_fw_runtime * fwrt,void * range_ptr,u32 range_len,int idx)1240 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt,
1241 				     void *range_ptr, u32 range_len, int idx)
1242 {
1243 	struct page *page = fwrt->fw_paging_db[idx].fw_paging_block;
1244 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1245 	dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys;
1246 	u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size;
1247 
1248 	range->page_num = cpu_to_le32(idx);
1249 	range->range_data_size = cpu_to_le32(page_size);
1250 	dma_sync_single_for_cpu(fwrt->trans->dev, addr,	page_size,
1251 				DMA_BIDIRECTIONAL);
1252 	memcpy(range->data, page_address(page), page_size);
1253 	dma_sync_single_for_device(fwrt->trans->dev, addr, page_size,
1254 				   DMA_BIDIRECTIONAL);
1255 
1256 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1257 }
1258 
iwl_dump_ini_paging_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1259 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt,
1260 				    struct iwl_dump_ini_region_data *reg_data,
1261 				    void *range_ptr, u32 range_len, int idx)
1262 {
1263 	struct iwl_fw_ini_error_dump_range *range;
1264 	u32 page_size;
1265 
1266 	/* all paged index start from 1 to skip CSS section */
1267 	idx++;
1268 
1269 	if (!fwrt->trans->trans_cfg->gen2)
1270 		return _iwl_dump_ini_paging_iter(fwrt, range_ptr, range_len, idx);
1271 
1272 	range = range_ptr;
1273 	page_size = fwrt->trans->init_dram.paging[idx].size;
1274 
1275 	range->page_num = cpu_to_le32(idx);
1276 	range->range_data_size = cpu_to_le32(page_size);
1277 	memcpy(range->data, fwrt->trans->init_dram.paging[idx].block,
1278 	       page_size);
1279 
1280 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1281 }
1282 
1283 static int
iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1284 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt,
1285 			   struct iwl_dump_ini_region_data *reg_data,
1286 			   void *range_ptr, u32 range_len, int idx)
1287 {
1288 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1289 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1290 	struct iwl_dram_data *frag;
1291 	u32 alloc_id = le32_to_cpu(reg->dram_alloc_id);
1292 
1293 	frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx];
1294 
1295 	range->dram_base_addr = cpu_to_le64(frag->physical);
1296 	range->range_data_size = cpu_to_le32(frag->size);
1297 
1298 	memcpy(range->data, frag->block, frag->size);
1299 
1300 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1301 }
1302 
iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1303 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt,
1304 				      struct iwl_dump_ini_region_data *reg_data,
1305 				      void *range_ptr, u32 range_len, int idx)
1306 {
1307 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1308 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1309 	u32 addr = le32_to_cpu(reg->internal_buffer.base_addr);
1310 
1311 	range->internal_base_addr = cpu_to_le32(addr);
1312 	range->range_data_size = reg->internal_buffer.size;
1313 	iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1314 				 le32_to_cpu(reg->internal_buffer.size));
1315 
1316 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1317 }
1318 
iwl_ini_txf_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,int idx)1319 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt,
1320 			     struct iwl_dump_ini_region_data *reg_data, int idx)
1321 {
1322 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1323 	struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1324 	struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
1325 	int txf_num = cfg->num_txfifo_entries;
1326 	int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size);
1327 	u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]);
1328 
1329 	if (!idx) {
1330 		if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) {
1331 			IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n",
1332 				le32_to_cpu(reg->fifos.offset));
1333 			return false;
1334 		}
1335 
1336 		iter->internal_txf = 0;
1337 		iter->fifo_size = 0;
1338 		iter->fifo = -1;
1339 		if (le32_to_cpu(reg->fifos.offset))
1340 			iter->lmac = 1;
1341 		else
1342 			iter->lmac = 0;
1343 	}
1344 
1345 	if (!iter->internal_txf) {
1346 		for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) {
1347 			iter->fifo_size =
1348 				cfg->lmac[iter->lmac].txfifo_size[iter->fifo];
1349 			if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo)))
1350 				return true;
1351 		}
1352 		iter->fifo--;
1353 	}
1354 
1355 	iter->internal_txf = 1;
1356 
1357 	if (!fw_has_capa(&fwrt->fw->ucode_capa,
1358 			 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))
1359 		return false;
1360 
1361 	for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) {
1362 		iter->fifo_size =
1363 			cfg->internal_txfifo_size[iter->fifo - txf_num];
1364 		if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo)))
1365 			return true;
1366 	}
1367 
1368 	return false;
1369 }
1370 
iwl_dump_ini_txf_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1371 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,
1372 				 struct iwl_dump_ini_region_data *reg_data,
1373 				 void *range_ptr, u32 range_len, int idx)
1374 {
1375 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1376 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1377 	struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1378 	struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data;
1379 	u32 offs = le32_to_cpu(reg->fifos.offset), addr;
1380 	u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1381 	u32 registers_size = registers_num * sizeof(*reg_dump);
1382 	__le32 *data;
1383 	int i;
1384 
1385 	if (!iwl_ini_txf_iter(fwrt, reg_data, idx))
1386 		return -EIO;
1387 
1388 	if (!iwl_trans_grab_nic_access(fwrt->trans))
1389 		return -EBUSY;
1390 
1391 	range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo);
1392 	range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num);
1393 	range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size);
1394 
1395 	iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo);
1396 
1397 	/*
1398 	 * read txf registers. for each register, write to the dump the
1399 	 * register address and its value
1400 	 */
1401 	for (i = 0; i < registers_num; i++) {
1402 		addr = le32_to_cpu(reg->addrs[i]) + offs;
1403 
1404 		reg_dump->addr = cpu_to_le32(addr);
1405 		reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans,
1406 								   addr));
1407 
1408 		reg_dump++;
1409 	}
1410 
1411 	if (reg->fifos.hdr_only) {
1412 		range->range_data_size = cpu_to_le32(registers_size);
1413 		goto out;
1414 	}
1415 
1416 	/* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
1417 	iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs,
1418 			       TXF_WR_PTR + offs);
1419 
1420 	/* Dummy-read to advance the read pointer to the head */
1421 	iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs);
1422 
1423 	/* Read FIFO */
1424 	addr = TXF_READ_MODIFY_DATA + offs;
1425 	data = (void *)reg_dump;
1426 	for (i = 0; i < iter->fifo_size; i += sizeof(*data))
1427 		*data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
1428 
1429 	if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf)
1430 		fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx,
1431 					     reg_dump, iter->fifo_size);
1432 
1433 out:
1434 	iwl_trans_release_nic_access(fwrt->trans);
1435 
1436 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1437 }
1438 
1439 static int
iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1440 iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime *fwrt,
1441 				   struct iwl_dump_ini_region_data *reg_data,
1442 				   void *range_ptr, u32 range_len, int idx)
1443 {
1444 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1445 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1446 	__le32 *val = range->data;
1447 	__le32 offset = reg->dev_addr.offset;
1448 	u32 indirect_rd_wr_addr = DPHYIP_INDIRECT;
1449 	u32 addr = le32_to_cpu(reg->addrs[idx]);
1450 	u32 dphy_state, dphy_addr, prph_val;
1451 	int i;
1452 
1453 	range->internal_base_addr = cpu_to_le32(addr);
1454 	range->range_data_size = reg->dev_addr.size;
1455 
1456 	if (!iwl_trans_grab_nic_access(fwrt->trans))
1457 		return -EBUSY;
1458 
1459 	indirect_rd_wr_addr += le32_to_cpu(offset);
1460 
1461 	dphy_addr = offset ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW;
1462 	dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr);
1463 
1464 	for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1465 		if (dphy_state == HBUS_TIMEOUT ||
1466 		    (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) !=
1467 		    WFPM_PHYRF_STATE_ON) {
1468 			*val++ = cpu_to_le32(WFPM_DPHY_OFF);
1469 			continue;
1470 		}
1471 
1472 		iwl_write_prph_no_grab(fwrt->trans, indirect_rd_wr_addr,
1473 				       addr + i);
1474 		/* wait a bit for value to be ready in register */
1475 		udelay(1);
1476 		prph_val = iwl_read_prph_no_grab(fwrt->trans,
1477 						 indirect_rd_wr_addr);
1478 		*val++ = cpu_to_le32((prph_val & DPHYIP_INDIRECT_RD_MSK) >>
1479 				     DPHYIP_INDIRECT_RD_SHIFT);
1480 	}
1481 
1482 	iwl_trans_release_nic_access(fwrt->trans);
1483 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1484 }
1485 
1486 struct iwl_ini_rxf_data {
1487 	u32 fifo_num;
1488 	u32 size;
1489 	u32 offset;
1490 };
1491 
iwl_ini_get_rxf_data(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,struct iwl_ini_rxf_data * data)1492 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt,
1493 				 struct iwl_dump_ini_region_data *reg_data,
1494 				 struct iwl_ini_rxf_data *data)
1495 {
1496 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1497 	u32 fid1 = le32_to_cpu(reg->fifos.fid[0]);
1498 	u32 fid2 = le32_to_cpu(reg->fifos.fid[1]);
1499 	u8 fifo_idx;
1500 
1501 	if (!data)
1502 		return;
1503 
1504 	memset(data, 0, sizeof(*data));
1505 
1506 	/* make sure only one bit is set in only one fid */
1507 	if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1,
1508 		      "fid1=%x, fid2=%x\n", fid1, fid2))
1509 		return;
1510 
1511 	if (fid1) {
1512 		fifo_idx = ffs(fid1) - 1;
1513 		if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n",
1514 			      fifo_idx))
1515 			return;
1516 
1517 		data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size;
1518 		data->fifo_num = fifo_idx;
1519 	} else {
1520 		u8 max_idx;
1521 
1522 		fifo_idx = ffs(fid2) - 1;
1523 		if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP,
1524 					    SHARED_MEM_CFG_CMD, 0) <= 3)
1525 			max_idx = 0;
1526 		else
1527 			max_idx = 1;
1528 
1529 		if (WARN_ONCE(fifo_idx > max_idx,
1530 			      "invalid umac fifo idx %d", fifo_idx))
1531 			return;
1532 
1533 		/* use bit 31 to distinguish between umac and lmac rxf while
1534 		 * parsing the dump
1535 		 */
1536 		data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT;
1537 
1538 		switch (fifo_idx) {
1539 		case 0:
1540 			data->size = fwrt->smem_cfg.rxfifo2_size;
1541 			data->offset = iwl_umac_prph(fwrt->trans,
1542 						     RXF_DIFF_FROM_PREV);
1543 			break;
1544 		case 1:
1545 			data->size = fwrt->smem_cfg.rxfifo2_control_size;
1546 			data->offset = iwl_umac_prph(fwrt->trans,
1547 						     RXF2C_DIFF_FROM_PREV);
1548 			break;
1549 		}
1550 	}
1551 }
1552 
iwl_dump_ini_rxf_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1553 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt,
1554 				 struct iwl_dump_ini_region_data *reg_data,
1555 				 void *range_ptr, u32 range_len, int idx)
1556 {
1557 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1558 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1559 	struct iwl_ini_rxf_data rxf_data;
1560 	struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data;
1561 	u32 offs = le32_to_cpu(reg->fifos.offset), addr;
1562 	u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1563 	u32 registers_size = registers_num * sizeof(*reg_dump);
1564 	__le32 *data;
1565 	int i;
1566 
1567 	iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data);
1568 	if (!rxf_data.size)
1569 		return -EIO;
1570 
1571 	if (!iwl_trans_grab_nic_access(fwrt->trans))
1572 		return -EBUSY;
1573 
1574 	range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num);
1575 	range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num);
1576 	range->range_data_size = cpu_to_le32(rxf_data.size + registers_size);
1577 
1578 	/*
1579 	 * read rxf registers. for each register, write to the dump the
1580 	 * register address and its value
1581 	 */
1582 	for (i = 0; i < registers_num; i++) {
1583 		addr = le32_to_cpu(reg->addrs[i]) + offs;
1584 
1585 		reg_dump->addr = cpu_to_le32(addr);
1586 		reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans,
1587 								   addr));
1588 
1589 		reg_dump++;
1590 	}
1591 
1592 	if (reg->fifos.hdr_only) {
1593 		range->range_data_size = cpu_to_le32(registers_size);
1594 		goto out;
1595 	}
1596 
1597 	offs = rxf_data.offset;
1598 
1599 	/* Lock fence */
1600 	iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1);
1601 	/* Set fence pointer to the same place like WR pointer */
1602 	iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1);
1603 	/* Set fence offset */
1604 	iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs,
1605 			       0x0);
1606 
1607 	/* Read FIFO */
1608 	addr =  RXF_FIFO_RD_FENCE_INC + offs;
1609 	data = (void *)reg_dump;
1610 	for (i = 0; i < rxf_data.size; i += sizeof(*data))
1611 		*data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
1612 
1613 out:
1614 	iwl_trans_release_nic_access(fwrt->trans);
1615 
1616 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1617 }
1618 
1619 static int
iwl_dump_ini_err_table_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1620 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt,
1621 			    struct iwl_dump_ini_region_data *reg_data,
1622 			    void *range_ptr, u32 range_len, int idx)
1623 {
1624 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1625 	struct iwl_fw_ini_region_err_table *err_table = &reg->err_table;
1626 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1627 	u32 addr = le32_to_cpu(err_table->base_addr) +
1628 		   le32_to_cpu(err_table->offset);
1629 
1630 	range->internal_base_addr = cpu_to_le32(addr);
1631 	range->range_data_size = err_table->size;
1632 	iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1633 				 le32_to_cpu(err_table->size));
1634 
1635 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1636 }
1637 
1638 static int
iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1639 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt,
1640 			      struct iwl_dump_ini_region_data *reg_data,
1641 			      void *range_ptr, u32 range_len, int idx)
1642 {
1643 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1644 	struct iwl_fw_ini_region_special_device_memory *special_mem =
1645 		&reg->special_mem;
1646 
1647 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1648 	u32 addr = le32_to_cpu(special_mem->base_addr) +
1649 		   le32_to_cpu(special_mem->offset);
1650 
1651 	range->internal_base_addr = cpu_to_le32(addr);
1652 	range->range_data_size = special_mem->size;
1653 	iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1654 				 le32_to_cpu(special_mem->size));
1655 
1656 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1657 }
1658 
1659 static int
iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1660 iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt,
1661 			    struct iwl_dump_ini_region_data *reg_data,
1662 			    void *range_ptr, u32 range_len, int idx)
1663 {
1664 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1665 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1666 	__le32 *val = range->data;
1667 	u32 prph_data;
1668 	int i;
1669 
1670 	if (!iwl_trans_grab_nic_access(fwrt->trans))
1671 		return -EBUSY;
1672 
1673 	range->range_data_size = reg->dev_addr.size;
1674 	for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) {
1675 		prph_data = iwl_read_prph_no_grab(fwrt->trans, (i % 2) ?
1676 					  DBGI_SRAM_TARGET_ACCESS_RDATA_MSB :
1677 					  DBGI_SRAM_TARGET_ACCESS_RDATA_LSB);
1678 		if (iwl_trans_is_hw_error_value(prph_data)) {
1679 			iwl_trans_release_nic_access(fwrt->trans);
1680 			return -EBUSY;
1681 		}
1682 		*val++ = cpu_to_le32(prph_data);
1683 	}
1684 	iwl_trans_release_nic_access(fwrt->trans);
1685 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1686 }
1687 
iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1688 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt,
1689 				    struct iwl_dump_ini_region_data *reg_data,
1690 				    void *range_ptr, u32 range_len, int idx)
1691 {
1692 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1693 	struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt;
1694 	u32 pkt_len;
1695 
1696 	if (!pkt)
1697 		return -EIO;
1698 
1699 	pkt_len = iwl_rx_packet_payload_len(pkt);
1700 
1701 	memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr));
1702 	range->range_data_size = cpu_to_le32(pkt_len);
1703 
1704 	memcpy(range->data, pkt->data, pkt_len);
1705 
1706 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1707 }
1708 
iwl_dump_ini_imr_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1709 static int iwl_dump_ini_imr_iter(struct iwl_fw_runtime *fwrt,
1710 				 struct iwl_dump_ini_region_data *reg_data,
1711 				 void *range_ptr, u32 range_len, int idx)
1712 {
1713 	/* read the IMR memory and DMA it to SRAM */
1714 	struct iwl_fw_ini_error_dump_range *range = range_ptr;
1715 	u64 imr_curr_addr = fwrt->trans->dbg.imr_data.imr_curr_addr;
1716 	u32 imr_rem_bytes = fwrt->trans->dbg.imr_data.imr2sram_remainbyte;
1717 	u32 sram_addr = fwrt->trans->dbg.imr_data.sram_addr;
1718 	u32 sram_size = fwrt->trans->dbg.imr_data.sram_size;
1719 	u32 size_to_dump = (imr_rem_bytes > sram_size) ? sram_size : imr_rem_bytes;
1720 
1721 	range->range_data_size = cpu_to_le32(size_to_dump);
1722 	if (iwl_trans_write_imr_mem(fwrt->trans, sram_addr,
1723 				    imr_curr_addr, size_to_dump)) {
1724 		IWL_ERR(fwrt, "WRT_DEBUG: IMR Memory transfer failed\n");
1725 		return -1;
1726 	}
1727 
1728 	fwrt->trans->dbg.imr_data.imr_curr_addr = imr_curr_addr + size_to_dump;
1729 	fwrt->trans->dbg.imr_data.imr2sram_remainbyte -= size_to_dump;
1730 
1731 	iwl_trans_read_mem_bytes(fwrt->trans, sram_addr, range->data,
1732 				 size_to_dump);
1733 	return sizeof(*range) + le32_to_cpu(range->range_data_size);
1734 }
1735 
1736 static void *
iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1737 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt,
1738 			     struct iwl_dump_ini_region_data *reg_data,
1739 			     void *data, u32 data_len)
1740 {
1741 	struct iwl_fw_ini_error_dump *dump = data;
1742 
1743 	dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1744 
1745 	return dump->data;
1746 }
1747 
1748 /**
1749  * mask_apply_and_normalize - applies mask on val and normalize the result
1750  *
1751  * @val: value
1752  * @mask: mask to apply and to normalize with
1753  *
1754  * The normalization is based on the first set bit in the mask
1755  *
1756  * Returns: the extracted value
1757  */
mask_apply_and_normalize(u32 val,u32 mask)1758 static u32 mask_apply_and_normalize(u32 val, u32 mask)
1759 {
1760 	return (val & mask) >> (ffs(mask) - 1);
1761 }
1762 
iwl_get_mon_reg(struct iwl_fw_runtime * fwrt,u32 alloc_id,const struct iwl_fw_mon_reg * reg_info)1763 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id,
1764 			      const struct iwl_fw_mon_reg *reg_info)
1765 {
1766 	u32 val, offs;
1767 
1768 	/* The header addresses of DBGCi is calculate as follows:
1769 	 * DBGC1 address + (0x100 * i)
1770 	 */
1771 	offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100;
1772 
1773 	if (!reg_info || !reg_info->addr || !reg_info->mask)
1774 		return 0;
1775 
1776 	val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs);
1777 
1778 	return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask));
1779 }
1780 
1781 static void *
iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime * fwrt,u32 alloc_id,struct iwl_fw_ini_monitor_dump * data,const struct iwl_fw_mon_regs * addrs)1782 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, u32 alloc_id,
1783 			     struct iwl_fw_ini_monitor_dump *data,
1784 			     const struct iwl_fw_mon_regs *addrs)
1785 {
1786 	if (!iwl_trans_grab_nic_access(fwrt->trans)) {
1787 		IWL_ERR(fwrt, "Failed to get monitor header\n");
1788 		return NULL;
1789 	}
1790 
1791 	data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id,
1792 					  &addrs->write_ptr);
1793 	if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1794 		u32 wrt_ptr = le32_to_cpu(data->write_ptr);
1795 
1796 		data->write_ptr = cpu_to_le32(wrt_ptr >> 2);
1797 	}
1798 	data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id,
1799 					  &addrs->cycle_cnt);
1800 	data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id,
1801 					 &addrs->cur_frag);
1802 
1803 	iwl_trans_release_nic_access(fwrt->trans);
1804 
1805 	data->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1806 
1807 	return data->data;
1808 }
1809 
1810 static void *
iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1811 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt,
1812 				  struct iwl_dump_ini_region_data *reg_data,
1813 				  void *data, u32 data_len)
1814 {
1815 	struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1816 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1817 	u32 alloc_id = le32_to_cpu(reg->dram_alloc_id);
1818 
1819 	return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump,
1820 					    &fwrt->trans->cfg->mon_dram_regs);
1821 }
1822 
1823 static void *
iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1824 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt,
1825 				  struct iwl_dump_ini_region_data *reg_data,
1826 				  void *data, u32 data_len)
1827 {
1828 	struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1829 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1830 	u32 alloc_id = le32_to_cpu(reg->internal_buffer.alloc_id);
1831 
1832 	return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump,
1833 					    &fwrt->trans->cfg->mon_smem_regs);
1834 }
1835 
1836 static void *
iwl_dump_ini_mon_dbgi_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1837 iwl_dump_ini_mon_dbgi_fill_header(struct iwl_fw_runtime *fwrt,
1838 				  struct iwl_dump_ini_region_data *reg_data,
1839 				  void *data, u32 data_len)
1840 {
1841 	struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1842 
1843 	return iwl_dump_ini_mon_fill_header(fwrt,
1844 					    /* no offset calculation later */
1845 					    IWL_FW_INI_ALLOCATION_ID_DBGC1,
1846 					    mon_dump,
1847 					    &fwrt->trans->cfg->mon_dbgi_regs);
1848 }
1849 
1850 static void *
iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1851 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt,
1852 				   struct iwl_dump_ini_region_data *reg_data,
1853 				   void *data, u32 data_len)
1854 {
1855 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1856 	struct iwl_fw_ini_err_table_dump *dump = data;
1857 
1858 	dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1859 	dump->version = reg->err_table.version;
1860 
1861 	return dump->data;
1862 }
1863 
1864 static void *
iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1865 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt,
1866 				     struct iwl_dump_ini_region_data *reg_data,
1867 				     void *data, u32 data_len)
1868 {
1869 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1870 	struct iwl_fw_ini_special_device_memory *dump = data;
1871 
1872 	dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1873 	dump->type = reg->special_mem.type;
1874 	dump->version = reg->special_mem.version;
1875 
1876 	return dump->data;
1877 }
1878 
1879 static void *
iwl_dump_ini_imr_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1880 iwl_dump_ini_imr_fill_header(struct iwl_fw_runtime *fwrt,
1881 			     struct iwl_dump_ini_region_data *reg_data,
1882 			     void *data, u32 data_len)
1883 {
1884 	struct iwl_fw_ini_error_dump *dump = data;
1885 
1886 	dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1887 
1888 	return dump->data;
1889 }
1890 
iwl_dump_ini_mem_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1891 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt,
1892 				   struct iwl_dump_ini_region_data *reg_data)
1893 {
1894 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1895 
1896 	return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1897 }
1898 
1899 static u32
iwl_dump_ini_mem_block_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1900 iwl_dump_ini_mem_block_ranges(struct iwl_fw_runtime *fwrt,
1901 			      struct iwl_dump_ini_region_data *reg_data)
1902 {
1903 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1904 	size_t size = sizeof(struct iwl_fw_ini_addr_size);
1905 
1906 	return iwl_tlv_array_len_with_size(reg_data->reg_tlv, reg, size);
1907 }
1908 
iwl_dump_ini_paging_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1909 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt,
1910 				      struct iwl_dump_ini_region_data *reg_data)
1911 {
1912 	if (fwrt->trans->trans_cfg->gen2) {
1913 		if (fwrt->trans->init_dram.paging_cnt)
1914 			return fwrt->trans->init_dram.paging_cnt - 1;
1915 		else
1916 			return 0;
1917 	}
1918 
1919 	return fwrt->num_of_paging_blk;
1920 }
1921 
1922 static u32
iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1923 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt,
1924 			     struct iwl_dump_ini_region_data *reg_data)
1925 {
1926 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1927 	struct iwl_fw_mon *fw_mon;
1928 	u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);
1929 	int i;
1930 
1931 	fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
1932 
1933 	for (i = 0; i < fw_mon->num_frags; i++) {
1934 		if (!fw_mon->frags[i].size)
1935 			break;
1936 
1937 		ranges++;
1938 	}
1939 
1940 	return ranges;
1941 }
1942 
iwl_dump_ini_txf_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1943 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt,
1944 				   struct iwl_dump_ini_region_data *reg_data)
1945 {
1946 	u32 num_of_fifos = 0;
1947 
1948 	while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos))
1949 		num_of_fifos++;
1950 
1951 	return num_of_fifos;
1952 }
1953 
iwl_dump_ini_single_range(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1954 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt,
1955 				     struct iwl_dump_ini_region_data *reg_data)
1956 {
1957 	return 1;
1958 }
1959 
iwl_dump_ini_imr_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1960 static u32 iwl_dump_ini_imr_ranges(struct iwl_fw_runtime *fwrt,
1961 				   struct iwl_dump_ini_region_data *reg_data)
1962 {
1963 	/* range is total number of pages need to copied from
1964 	 *IMR memory to SRAM and later from SRAM to DRAM
1965 	 */
1966 	u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable;
1967 	u32 imr_size = fwrt->trans->dbg.imr_data.imr_size;
1968 	u32 sram_size = fwrt->trans->dbg.imr_data.sram_size;
1969 
1970 	if (imr_enable == 0 || imr_size == 0 || sram_size == 0) {
1971 		IWL_DEBUG_INFO(fwrt,
1972 			       "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n",
1973 			       imr_enable, imr_size, sram_size);
1974 		return 0;
1975 	}
1976 
1977 	return((imr_size % sram_size) ? (imr_size / sram_size + 1) : (imr_size / sram_size));
1978 }
1979 
iwl_dump_ini_mem_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1980 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt,
1981 				     struct iwl_dump_ini_region_data *reg_data)
1982 {
1983 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1984 	u32 size = le32_to_cpu(reg->dev_addr.size);
1985 	u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data);
1986 
1987 	if (!size || !ranges)
1988 		return 0;
1989 
1990 	return sizeof(struct iwl_fw_ini_error_dump) + ranges *
1991 		(size + sizeof(struct iwl_fw_ini_error_dump_range));
1992 }
1993 
1994 static u32
iwl_dump_ini_mem_block_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1995 iwl_dump_ini_mem_block_get_size(struct iwl_fw_runtime *fwrt,
1996 				struct iwl_dump_ini_region_data *reg_data)
1997 {
1998 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1999 	struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs;
2000 	u32 ranges = iwl_dump_ini_mem_block_ranges(fwrt, reg_data);
2001 	u32 size = sizeof(struct iwl_fw_ini_error_dump);
2002 	int range;
2003 
2004 	if (!ranges)
2005 		return 0;
2006 
2007 	for (range = 0; range < ranges; range++)
2008 		size += le32_to_cpu(pairs[range].size);
2009 
2010 	return size + ranges * sizeof(struct iwl_fw_ini_error_dump_range);
2011 }
2012 
2013 static u32
iwl_dump_ini_paging_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2014 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt,
2015 			     struct iwl_dump_ini_region_data *reg_data)
2016 {
2017 	int i;
2018 	u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range);
2019 	u32 size = sizeof(struct iwl_fw_ini_error_dump);
2020 
2021 	/* start from 1 to skip CSS section */
2022 	for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) {
2023 		size += range_header_len;
2024 		if (fwrt->trans->trans_cfg->gen2)
2025 			size += fwrt->trans->init_dram.paging[i].size;
2026 		else
2027 			size += fwrt->fw_paging_db[i].fw_paging_size;
2028 	}
2029 
2030 	return size;
2031 }
2032 
2033 static u32
iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2034 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt,
2035 			       struct iwl_dump_ini_region_data *reg_data)
2036 {
2037 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2038 	struct iwl_fw_mon *fw_mon;
2039 	u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);
2040 	int i;
2041 
2042 	fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
2043 
2044 	for (i = 0; i < fw_mon->num_frags; i++) {
2045 		struct iwl_dram_data *frag = &fw_mon->frags[i];
2046 
2047 		if (!frag->size)
2048 			break;
2049 
2050 		size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size;
2051 	}
2052 
2053 	if (size)
2054 		size += sizeof(struct iwl_fw_ini_monitor_dump);
2055 
2056 	return size;
2057 }
2058 
2059 static u32
iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2060 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt,
2061 			       struct iwl_dump_ini_region_data *reg_data)
2062 {
2063 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2064 	u32 size;
2065 
2066 	size = le32_to_cpu(reg->internal_buffer.size);
2067 	if (!size)
2068 		return 0;
2069 
2070 	size += sizeof(struct iwl_fw_ini_monitor_dump) +
2071 		sizeof(struct iwl_fw_ini_error_dump_range);
2072 
2073 	return size;
2074 }
2075 
iwl_dump_ini_mon_dbgi_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2076 static u32 iwl_dump_ini_mon_dbgi_get_size(struct iwl_fw_runtime *fwrt,
2077 					  struct iwl_dump_ini_region_data *reg_data)
2078 {
2079 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2080 	u32 size = le32_to_cpu(reg->dev_addr.size);
2081 	u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data);
2082 
2083 	if (!size || !ranges)
2084 		return 0;
2085 
2086 	return sizeof(struct iwl_fw_ini_monitor_dump) + ranges *
2087 		(size + sizeof(struct iwl_fw_ini_error_dump_range));
2088 }
2089 
iwl_dump_ini_txf_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2090 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt,
2091 				     struct iwl_dump_ini_region_data *reg_data)
2092 {
2093 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2094 	struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
2095 	u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
2096 	u32 size = 0;
2097 	u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) +
2098 		       registers_num *
2099 		       sizeof(struct iwl_fw_ini_error_dump_register);
2100 
2101 	while (iwl_ini_txf_iter(fwrt, reg_data, size)) {
2102 		size += fifo_hdr;
2103 		if (!reg->fifos.hdr_only)
2104 			size += iter->fifo_size;
2105 	}
2106 
2107 	if (!size)
2108 		return 0;
2109 
2110 	return size + sizeof(struct iwl_fw_ini_error_dump);
2111 }
2112 
iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2113 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt,
2114 				     struct iwl_dump_ini_region_data *reg_data)
2115 {
2116 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2117 	struct iwl_ini_rxf_data rx_data;
2118 	u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
2119 	u32 size = sizeof(struct iwl_fw_ini_error_dump) +
2120 		sizeof(struct iwl_fw_ini_error_dump_range) +
2121 		registers_num * sizeof(struct iwl_fw_ini_error_dump_register);
2122 
2123 	if (reg->fifos.hdr_only)
2124 		return size;
2125 
2126 	iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data);
2127 	size += rx_data.size;
2128 
2129 	return size;
2130 }
2131 
2132 static u32
iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2133 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt,
2134 				struct iwl_dump_ini_region_data *reg_data)
2135 {
2136 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2137 	u32 size = le32_to_cpu(reg->err_table.size);
2138 
2139 	if (size)
2140 		size += sizeof(struct iwl_fw_ini_err_table_dump) +
2141 			sizeof(struct iwl_fw_ini_error_dump_range);
2142 
2143 	return size;
2144 }
2145 
2146 static u32
iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2147 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt,
2148 				  struct iwl_dump_ini_region_data *reg_data)
2149 {
2150 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2151 	u32 size = le32_to_cpu(reg->special_mem.size);
2152 
2153 	if (size)
2154 		size += sizeof(struct iwl_fw_ini_special_device_memory) +
2155 			sizeof(struct iwl_fw_ini_error_dump_range);
2156 
2157 	return size;
2158 }
2159 
2160 static u32
iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2161 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt,
2162 			     struct iwl_dump_ini_region_data *reg_data)
2163 {
2164 	u32 size = 0;
2165 
2166 	if (!reg_data->dump_data->fw_pkt)
2167 		return 0;
2168 
2169 	size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt);
2170 	if (size)
2171 		size += sizeof(struct iwl_fw_ini_error_dump) +
2172 			sizeof(struct iwl_fw_ini_error_dump_range);
2173 
2174 	return size;
2175 }
2176 
2177 static u32
iwl_dump_ini_imr_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2178 iwl_dump_ini_imr_get_size(struct iwl_fw_runtime *fwrt,
2179 			  struct iwl_dump_ini_region_data *reg_data)
2180 {
2181 	u32 ranges = 0;
2182 	u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable;
2183 	u32 imr_size = fwrt->trans->dbg.imr_data.imr_size;
2184 	u32 sram_size = fwrt->trans->dbg.imr_data.sram_size;
2185 
2186 	if (imr_enable == 0 || imr_size == 0 || sram_size == 0) {
2187 		IWL_DEBUG_INFO(fwrt,
2188 			       "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n",
2189 			       imr_enable, imr_size, sram_size);
2190 		return 0;
2191 	}
2192 	ranges = iwl_dump_ini_imr_ranges(fwrt, reg_data);
2193 	if (!ranges) {
2194 		IWL_ERR(fwrt, "WRT: ranges :=%d\n", ranges);
2195 		return 0;
2196 	}
2197 	imr_size += sizeof(struct iwl_fw_ini_error_dump) +
2198 		ranges * sizeof(struct iwl_fw_ini_error_dump_range);
2199 	return imr_size;
2200 }
2201 
2202 /**
2203  * struct iwl_dump_ini_mem_ops - ini memory dump operations
2204  * @get_num_of_ranges: returns the number of memory ranges in the region.
2205  * @get_size: returns the total size of the region.
2206  * @fill_mem_hdr: fills region type specific headers and returns pointer to
2207  *	the first range or NULL if failed to fill headers.
2208  * @fill_range: copies a given memory range into the dump.
2209  *	Returns the size of the range or negative error value otherwise.
2210  */
2211 struct iwl_dump_ini_mem_ops {
2212 	u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt,
2213 				 struct iwl_dump_ini_region_data *reg_data);
2214 	u32 (*get_size)(struct iwl_fw_runtime *fwrt,
2215 			struct iwl_dump_ini_region_data *reg_data);
2216 	void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt,
2217 			      struct iwl_dump_ini_region_data *reg_data,
2218 			      void *data, u32 data_len);
2219 	int (*fill_range)(struct iwl_fw_runtime *fwrt,
2220 			  struct iwl_dump_ini_region_data *reg_data,
2221 			  void *range, u32 range_len, int idx);
2222 };
2223 
2224 /**
2225  * iwl_dump_ini_mem - dump memory region
2226  *
2227  * @fwrt: fw runtime struct
2228  * @list: list to add the dump tlv to
2229  * @reg_data: memory region
2230  * @ops: memory dump operations
2231  *
2232  * Creates a dump tlv and copy a memory region into it.
2233  *
2234  * Returns: the size of the current dump tlv or 0 if failed
2235  */
iwl_dump_ini_mem(struct iwl_fw_runtime * fwrt,struct list_head * list,struct iwl_dump_ini_region_data * reg_data,const struct iwl_dump_ini_mem_ops * ops)2236 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list,
2237 			    struct iwl_dump_ini_region_data *reg_data,
2238 			    const struct iwl_dump_ini_mem_ops *ops)
2239 {
2240 	struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2241 	struct iwl_fw_ini_dump_entry *entry;
2242 	struct iwl_fw_ini_error_dump_data *tlv;
2243 	struct iwl_fw_ini_error_dump_header *header;
2244 	u32 type = reg->type;
2245 	u32 id = le32_get_bits(reg->id, IWL_FW_INI_REGION_ID_MASK);
2246 	u32 num_of_ranges, i, size;
2247 	u8 *range;
2248 	u32 free_size;
2249 	u64 header_size;
2250 	u32 dump_policy = IWL_FW_INI_DUMP_VERBOSE;
2251 
2252 	IWL_DEBUG_FW(fwrt, "WRT: Collecting region: dump type=%d, id=%d, type=%d\n",
2253 		     dump_policy, id, type);
2254 
2255 	if (le32_to_cpu(reg->hdr.version) >= 2) {
2256 		u32 dp = le32_get_bits(reg->id,
2257 				       IWL_FW_INI_REGION_DUMP_POLICY_MASK);
2258 
2259 		if (dump_policy == IWL_FW_INI_DUMP_VERBOSE &&
2260 		    !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_NO_LIMIT)) {
2261 			IWL_DEBUG_FW(fwrt,
2262 				     "WRT: no dump - type %d and policy mismatch=%d\n",
2263 				     dump_policy, dp);
2264 			return 0;
2265 		} else if (dump_policy == IWL_FW_INI_DUMP_MEDIUM &&
2266 			   !(dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_MAX_LIMIT_5MB)) {
2267 			IWL_DEBUG_FW(fwrt,
2268 				     "WRT: no dump - type %d and policy mismatch=%d\n",
2269 				     dump_policy, dp);
2270 			return 0;
2271 		} else if (dump_policy == IWL_FW_INI_DUMP_BRIEF &&
2272 			   !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_MAX_LIMIT_600KB)) {
2273 			IWL_DEBUG_FW(fwrt,
2274 				     "WRT: no dump - type %d and policy mismatch=%d\n",
2275 				     dump_policy, dp);
2276 			return 0;
2277 		}
2278 	}
2279 
2280 	if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr ||
2281 	    !ops->fill_range) {
2282 		IWL_DEBUG_FW(fwrt, "WRT: no ops for collecting data\n");
2283 		return 0;
2284 	}
2285 
2286 	size = ops->get_size(fwrt, reg_data);
2287 
2288 	if (size < sizeof(*header)) {
2289 		IWL_DEBUG_FW(fwrt, "WRT: size didn't include space for header\n");
2290 		return 0;
2291 	}
2292 
2293 	entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size);
2294 	if (!entry)
2295 		return 0;
2296 
2297 	entry->size = sizeof(*tlv) + size;
2298 
2299 	tlv = (void *)entry->data;
2300 	tlv->type = reg->type;
2301 	tlv->sub_type = reg->sub_type;
2302 	tlv->sub_type_ver = reg->sub_type_ver;
2303 	tlv->reserved = reg->reserved;
2304 	tlv->len = cpu_to_le32(size);
2305 
2306 	num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data);
2307 
2308 	header = (void *)tlv->data;
2309 	header->region_id = cpu_to_le32(id);
2310 	header->num_of_ranges = cpu_to_le32(num_of_ranges);
2311 	header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME);
2312 	memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME);
2313 
2314 	free_size = size;
2315 	range = ops->fill_mem_hdr(fwrt, reg_data, header, free_size);
2316 	if (!range) {
2317 		IWL_ERR(fwrt,
2318 			"WRT: Failed to fill region header: id=%d, type=%d\n",
2319 			id, type);
2320 		goto out_err;
2321 	}
2322 
2323 	header_size = range - (u8 *)header;
2324 
2325 	if (WARN(header_size > free_size,
2326 		 "header size %llu > free_size %d",
2327 		 header_size, free_size)) {
2328 		IWL_ERR(fwrt,
2329 			"WRT: fill_mem_hdr used more than given free_size\n");
2330 		goto out_err;
2331 	}
2332 
2333 	free_size -= header_size;
2334 
2335 	for (i = 0; i < num_of_ranges; i++) {
2336 		int range_size = ops->fill_range(fwrt, reg_data, range,
2337 						 free_size, i);
2338 
2339 		if (range_size < 0) {
2340 			IWL_ERR(fwrt,
2341 				"WRT: Failed to dump region: id=%d, type=%d\n",
2342 				id, type);
2343 			goto out_err;
2344 		}
2345 
2346 		if (WARN(range_size > free_size, "range_size %d > free_size %d",
2347 			 range_size, free_size)) {
2348 			IWL_ERR(fwrt,
2349 				"WRT: fill_raged used more than given free_size\n");
2350 			goto out_err;
2351 		}
2352 
2353 		free_size -= range_size;
2354 		range = range + range_size;
2355 	}
2356 
2357 	list_add_tail(&entry->list, list);
2358 
2359 	return entry->size;
2360 
2361 out_err:
2362 	vfree(entry);
2363 
2364 	return 0;
2365 }
2366 
iwl_dump_ini_info(struct iwl_fw_runtime * fwrt,struct iwl_fw_ini_trigger_tlv * trigger,struct list_head * list)2367 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt,
2368 			     struct iwl_fw_ini_trigger_tlv *trigger,
2369 			     struct list_head *list)
2370 {
2371 	struct iwl_fw_ini_dump_entry *entry;
2372 	struct iwl_fw_error_dump_data *tlv;
2373 	struct iwl_fw_ini_dump_info *dump;
2374 	struct iwl_dbg_tlv_node *node;
2375 	struct iwl_fw_ini_dump_cfg_name *cfg_name;
2376 	u32 size = sizeof(*tlv) + sizeof(*dump);
2377 	u32 num_of_cfg_names = 0;
2378 	u32 hw_type;
2379 
2380 	list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) {
2381 		size += sizeof(*cfg_name);
2382 		num_of_cfg_names++;
2383 	}
2384 
2385 	entry = vzalloc(sizeof(*entry) + size);
2386 	if (!entry)
2387 		return 0;
2388 
2389 	entry->size = size;
2390 
2391 	tlv = (void *)entry->data;
2392 	tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE);
2393 	tlv->len = cpu_to_le32(size - sizeof(*tlv));
2394 
2395 	dump = (void *)tlv->data;
2396 
2397 	dump->version = cpu_to_le32(IWL_INI_DUMP_VER);
2398 	dump->time_point = trigger->time_point;
2399 	dump->trigger_reason = trigger->trigger_reason;
2400 	dump->external_cfg_state =
2401 		cpu_to_le32(fwrt->trans->dbg.external_ini_cfg);
2402 
2403 	dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type);
2404 	dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype);
2405 
2406 	dump->hw_step = cpu_to_le32(fwrt->trans->hw_rev_step);
2407 
2408 	/*
2409 	 * Several HWs all have type == 0x42, so we'll override this value
2410 	 * according to the detected HW
2411 	 */
2412 	hw_type = CSR_HW_REV_TYPE(fwrt->trans->hw_rev);
2413 	if (hw_type == IWL_AX210_HW_TYPE) {
2414 		u32 prph_val = iwl_read_umac_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR);
2415 		u32 is_jacket = !!(prph_val & WFPM_OTP_CFG1_IS_JACKET_BIT);
2416 		u32 is_cdb = !!(prph_val & WFPM_OTP_CFG1_IS_CDB_BIT);
2417 		u32 masked_bits = is_jacket | (is_cdb << 1);
2418 
2419 		/*
2420 		 * The HW type depends on certain bits in this case, so add
2421 		 * these bits to the HW type. We won't have collisions since we
2422 		 * add these bits after the highest possible bit in the mask.
2423 		 */
2424 		hw_type |= masked_bits << IWL_AX210_HW_TYPE_ADDITION_SHIFT;
2425 	}
2426 	dump->hw_type = cpu_to_le32(hw_type);
2427 
2428 	dump->rf_id_flavor =
2429 		cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id));
2430 	dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id));
2431 	dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id));
2432 	dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id));
2433 
2434 	dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major);
2435 	dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor);
2436 	dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major);
2437 	dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor);
2438 
2439 	dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest);
2440 	dump->regions_mask = trigger->regions_mask &
2441 			     ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk);
2442 
2443 	dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag));
2444 	memcpy(dump->build_tag, fwrt->fw->human_readable,
2445 	       sizeof(dump->build_tag));
2446 
2447 	cfg_name = dump->cfg_names;
2448 	dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names);
2449 	list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) {
2450 		struct iwl_fw_ini_debug_info_tlv *debug_info =
2451 			(void *)node->tlv.data;
2452 
2453 		BUILD_BUG_ON(sizeof(cfg_name->cfg_name) !=
2454 			     sizeof(debug_info->debug_cfg_name));
2455 
2456 		cfg_name->image_type = debug_info->image_type;
2457 		cfg_name->cfg_name_len =
2458 			cpu_to_le32(sizeof(cfg_name->cfg_name));
2459 		memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name,
2460 		       sizeof(cfg_name->cfg_name));
2461 		cfg_name++;
2462 	}
2463 
2464 	/* add dump info TLV to the beginning of the list since it needs to be
2465 	 * the first TLV in the dump
2466 	 */
2467 	list_add(&entry->list, list);
2468 
2469 	return entry->size;
2470 }
2471 
iwl_dump_ini_file_name_info(struct iwl_fw_runtime * fwrt,struct list_head * list)2472 static u32 iwl_dump_ini_file_name_info(struct iwl_fw_runtime *fwrt,
2473 				       struct list_head *list)
2474 {
2475 	struct iwl_fw_ini_dump_entry *entry;
2476 	struct iwl_dump_file_name_info *tlv;
2477 	u32 len = strnlen(fwrt->trans->dbg.dump_file_name_ext,
2478 			  IWL_FW_INI_MAX_NAME);
2479 
2480 	if (!fwrt->trans->dbg.dump_file_name_ext_valid)
2481 		return 0;
2482 
2483 	entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + len);
2484 	if (!entry)
2485 		return 0;
2486 
2487 	entry->size = sizeof(*tlv) + len;
2488 
2489 	tlv = (void *)entry->data;
2490 	tlv->type = cpu_to_le32(IWL_INI_DUMP_NAME_TYPE);
2491 	tlv->len = cpu_to_le32(len);
2492 	memcpy(tlv->data, fwrt->trans->dbg.dump_file_name_ext, len);
2493 
2494 	/* add the dump file name extension tlv to the list */
2495 	list_add_tail(&entry->list, list);
2496 
2497 	fwrt->trans->dbg.dump_file_name_ext_valid = false;
2498 
2499 	return entry->size;
2500 }
2501 
2502 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = {
2503 	[IWL_FW_INI_REGION_INVALID] = {},
2504 	[IWL_FW_INI_REGION_INTERNAL_BUFFER] = {
2505 		.get_num_of_ranges = iwl_dump_ini_single_range,
2506 		.get_size = iwl_dump_ini_mon_smem_get_size,
2507 		.fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header,
2508 		.fill_range = iwl_dump_ini_mon_smem_iter,
2509 	},
2510 	[IWL_FW_INI_REGION_DRAM_BUFFER] = {
2511 		.get_num_of_ranges = iwl_dump_ini_mon_dram_ranges,
2512 		.get_size = iwl_dump_ini_mon_dram_get_size,
2513 		.fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header,
2514 		.fill_range = iwl_dump_ini_mon_dram_iter,
2515 	},
2516 	[IWL_FW_INI_REGION_TXF] = {
2517 		.get_num_of_ranges = iwl_dump_ini_txf_ranges,
2518 		.get_size = iwl_dump_ini_txf_get_size,
2519 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2520 		.fill_range = iwl_dump_ini_txf_iter,
2521 	},
2522 	[IWL_FW_INI_REGION_RXF] = {
2523 		.get_num_of_ranges = iwl_dump_ini_single_range,
2524 		.get_size = iwl_dump_ini_rxf_get_size,
2525 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2526 		.fill_range = iwl_dump_ini_rxf_iter,
2527 	},
2528 	[IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = {
2529 		.get_num_of_ranges = iwl_dump_ini_single_range,
2530 		.get_size = iwl_dump_ini_err_table_get_size,
2531 		.fill_mem_hdr = iwl_dump_ini_err_table_fill_header,
2532 		.fill_range = iwl_dump_ini_err_table_iter,
2533 	},
2534 	[IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = {
2535 		.get_num_of_ranges = iwl_dump_ini_single_range,
2536 		.get_size = iwl_dump_ini_err_table_get_size,
2537 		.fill_mem_hdr = iwl_dump_ini_err_table_fill_header,
2538 		.fill_range = iwl_dump_ini_err_table_iter,
2539 	},
2540 	[IWL_FW_INI_REGION_RSP_OR_NOTIF] = {
2541 		.get_num_of_ranges = iwl_dump_ini_single_range,
2542 		.get_size = iwl_dump_ini_fw_pkt_get_size,
2543 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2544 		.fill_range = iwl_dump_ini_fw_pkt_iter,
2545 	},
2546 	[IWL_FW_INI_REGION_DEVICE_MEMORY] = {
2547 		.get_num_of_ranges = iwl_dump_ini_mem_ranges,
2548 		.get_size = iwl_dump_ini_mem_get_size,
2549 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2550 		.fill_range = iwl_dump_ini_dev_mem_iter,
2551 	},
2552 	[IWL_FW_INI_REGION_PERIPHERY_MAC] = {
2553 		.get_num_of_ranges = iwl_dump_ini_mem_ranges,
2554 		.get_size = iwl_dump_ini_mem_get_size,
2555 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2556 		.fill_range = iwl_dump_ini_prph_mac_iter,
2557 	},
2558 	[IWL_FW_INI_REGION_PERIPHERY_PHY] = {
2559 		.get_num_of_ranges = iwl_dump_ini_mem_ranges,
2560 		.get_size = iwl_dump_ini_mem_get_size,
2561 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2562 		.fill_range = iwl_dump_ini_prph_phy_iter,
2563 	},
2564 	[IWL_FW_INI_REGION_PERIPHERY_MAC_RANGE] = {
2565 		.get_num_of_ranges = iwl_dump_ini_mem_block_ranges,
2566 		.get_size = iwl_dump_ini_mem_block_get_size,
2567 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2568 		.fill_range = iwl_dump_ini_prph_mac_block_iter,
2569 	},
2570 	[IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE] = {
2571 		.get_num_of_ranges = iwl_dump_ini_mem_block_ranges,
2572 		.get_size = iwl_dump_ini_mem_block_get_size,
2573 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2574 		.fill_range = iwl_dump_ini_prph_phy_block_iter,
2575 	},
2576 	[IWL_FW_INI_REGION_PERIPHERY_AUX] = {},
2577 	[IWL_FW_INI_REGION_PAGING] = {
2578 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2579 		.get_num_of_ranges = iwl_dump_ini_paging_ranges,
2580 		.get_size = iwl_dump_ini_paging_get_size,
2581 		.fill_range = iwl_dump_ini_paging_iter,
2582 	},
2583 	[IWL_FW_INI_REGION_CSR] = {
2584 		.get_num_of_ranges = iwl_dump_ini_mem_ranges,
2585 		.get_size = iwl_dump_ini_mem_get_size,
2586 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2587 		.fill_range = iwl_dump_ini_csr_iter,
2588 	},
2589 	[IWL_FW_INI_REGION_DRAM_IMR] = {
2590 		.get_num_of_ranges = iwl_dump_ini_imr_ranges,
2591 		.get_size = iwl_dump_ini_imr_get_size,
2592 		.fill_mem_hdr = iwl_dump_ini_imr_fill_header,
2593 		.fill_range = iwl_dump_ini_imr_iter,
2594 	},
2595 	[IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = {
2596 		.get_num_of_ranges = iwl_dump_ini_mem_ranges,
2597 		.get_size = iwl_dump_ini_mem_get_size,
2598 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2599 		.fill_range = iwl_dump_ini_config_iter,
2600 	},
2601 	[IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = {
2602 		.get_num_of_ranges = iwl_dump_ini_single_range,
2603 		.get_size = iwl_dump_ini_special_mem_get_size,
2604 		.fill_mem_hdr = iwl_dump_ini_special_mem_fill_header,
2605 		.fill_range = iwl_dump_ini_special_mem_iter,
2606 	},
2607 	[IWL_FW_INI_REGION_DBGI_SRAM] = {
2608 		.get_num_of_ranges = iwl_dump_ini_mem_ranges,
2609 		.get_size = iwl_dump_ini_mon_dbgi_get_size,
2610 		.fill_mem_hdr = iwl_dump_ini_mon_dbgi_fill_header,
2611 		.fill_range = iwl_dump_ini_dbgi_sram_iter,
2612 	},
2613 	[IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP] = {
2614 		.get_num_of_ranges = iwl_dump_ini_mem_ranges,
2615 		.get_size = iwl_dump_ini_mem_get_size,
2616 		.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2617 		.fill_range = iwl_dump_ini_prph_snps_dphyip_iter,
2618 	},
2619 };
2620 
iwl_dump_ini_trigger(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,struct list_head * list)2621 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt,
2622 				struct iwl_fwrt_dump_data *dump_data,
2623 				struct list_head *list)
2624 {
2625 	struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig;
2626 	enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point);
2627 	struct iwl_dump_ini_region_data reg_data = {
2628 		.dump_data = dump_data,
2629 	};
2630 	struct iwl_dump_ini_region_data imr_reg_data = {
2631 		.dump_data = dump_data,
2632 	};
2633 	int i;
2634 	u32 size = 0;
2635 	u64 regions_mask = le64_to_cpu(trigger->regions_mask) &
2636 			   ~(fwrt->trans->dbg.unsupported_region_msk);
2637 
2638 	BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask));
2639 	BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) <
2640 		     ARRAY_SIZE(fwrt->trans->dbg.active_regions));
2641 
2642 	for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) {
2643 		u32 reg_type;
2644 		struct iwl_fw_ini_region_tlv *reg;
2645 
2646 		if (!(BIT_ULL(i) & regions_mask))
2647 			continue;
2648 
2649 		reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i];
2650 		if (!reg_data.reg_tlv) {
2651 			IWL_WARN(fwrt,
2652 				 "WRT: Unassigned region id %d, skipping\n", i);
2653 			continue;
2654 		}
2655 
2656 		reg = (void *)reg_data.reg_tlv->data;
2657 		reg_type = reg->type;
2658 		if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops))
2659 			continue;
2660 
2661 		if ((reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY ||
2662 		     reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE ||
2663 		     reg_type == IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP) &&
2664 		    tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) {
2665 			IWL_WARN(fwrt,
2666 				 "WRT: trying to collect phy prph at time point: %d, skipping\n",
2667 				 tp_id);
2668 			continue;
2669 		}
2670 		/*
2671 		 * DRAM_IMR can be collected only for FW/HW error timepoint
2672 		 * when fw is not alive. In addition, it must be collected
2673 		 * lastly as it overwrites SRAM that can possibly contain
2674 		 * debug data which also need to be collected.
2675 		 */
2676 		if (reg_type == IWL_FW_INI_REGION_DRAM_IMR) {
2677 			if (tp_id == IWL_FW_INI_TIME_POINT_FW_ASSERT ||
2678 			    tp_id == IWL_FW_INI_TIME_POINT_FW_HW_ERROR)
2679 				imr_reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i];
2680 			else
2681 				IWL_INFO(fwrt,
2682 					 "WRT: trying to collect DRAM_IMR at time point: %d, skipping\n",
2683 					 tp_id);
2684 		/* continue to next region */
2685 			continue;
2686 		}
2687 
2688 
2689 		size += iwl_dump_ini_mem(fwrt, list, &reg_data,
2690 					 &iwl_dump_ini_region_ops[reg_type]);
2691 	}
2692 	/* collect DRAM_IMR region in the last */
2693 	if (imr_reg_data.reg_tlv)
2694 		size += iwl_dump_ini_mem(fwrt, list, &reg_data,
2695 					 &iwl_dump_ini_region_ops[IWL_FW_INI_REGION_DRAM_IMR]);
2696 
2697 	if (size) {
2698 		size += iwl_dump_ini_file_name_info(fwrt, list);
2699 		size += iwl_dump_ini_info(fwrt, trigger, list);
2700 	}
2701 
2702 	return size;
2703 }
2704 
iwl_fw_ini_trigger_on(struct iwl_fw_runtime * fwrt,struct iwl_fw_ini_trigger_tlv * trig)2705 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt,
2706 				  struct iwl_fw_ini_trigger_tlv *trig)
2707 {
2708 	enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point);
2709 	u32 usec = le32_to_cpu(trig->ignore_consec);
2710 
2711 	if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
2712 	    tp_id == IWL_FW_INI_TIME_POINT_INVALID ||
2713 	    tp_id >= IWL_FW_INI_TIME_POINT_NUM ||
2714 	    iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec))
2715 		return false;
2716 
2717 	return true;
2718 }
2719 
iwl_dump_ini_file_gen(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,struct list_head * list)2720 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt,
2721 				 struct iwl_fwrt_dump_data *dump_data,
2722 				 struct list_head *list)
2723 {
2724 	struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig;
2725 	struct iwl_fw_ini_dump_entry *entry;
2726 	struct iwl_fw_ini_dump_file_hdr *hdr;
2727 	u32 size;
2728 
2729 	if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) ||
2730 	    !le64_to_cpu(trigger->regions_mask))
2731 		return 0;
2732 
2733 	entry = vzalloc(sizeof(*entry) + sizeof(*hdr));
2734 	if (!entry)
2735 		return 0;
2736 
2737 	entry->size = sizeof(*hdr);
2738 
2739 	size = iwl_dump_ini_trigger(fwrt, dump_data, list);
2740 	if (!size) {
2741 		vfree(entry);
2742 		return 0;
2743 	}
2744 
2745 	hdr = (void *)entry->data;
2746 	hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER);
2747 	hdr->file_len = cpu_to_le32(size + entry->size);
2748 
2749 	list_add(&entry->list, list);
2750 
2751 	return le32_to_cpu(hdr->file_len);
2752 }
2753 
iwl_fw_free_dump_desc(struct iwl_fw_runtime * fwrt,const struct iwl_fw_dump_desc * desc)2754 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt,
2755 					 const struct iwl_fw_dump_desc *desc)
2756 {
2757 	if (desc && desc != &iwl_dump_desc_assert)
2758 		kfree(desc);
2759 
2760 	fwrt->dump.lmac_err_id[0] = 0;
2761 	if (fwrt->smem_cfg.num_lmacs > 1)
2762 		fwrt->dump.lmac_err_id[1] = 0;
2763 	fwrt->dump.umac_err_id = 0;
2764 }
2765 
iwl_fw_error_dump(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data)2766 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt,
2767 			      struct iwl_fwrt_dump_data *dump_data)
2768 {
2769 	struct iwl_fw_dump_ptrs fw_error_dump = {};
2770 	struct iwl_fw_error_dump_file *dump_file;
2771 	struct scatterlist *sg_dump_data;
2772 	u32 file_len;
2773 	u32 dump_mask = fwrt->fw->dbg.dump_mask;
2774 
2775 	dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data);
2776 	if (!dump_file)
2777 		return;
2778 
2779 	if (dump_data->monitor_only)
2780 		dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR);
2781 
2782 	fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask,
2783 						      fwrt->sanitize_ops,
2784 						      fwrt->sanitize_ctx);
2785 	file_len = le32_to_cpu(dump_file->file_len);
2786 	fw_error_dump.fwrt_len = file_len;
2787 
2788 	if (fw_error_dump.trans_ptr) {
2789 		file_len += fw_error_dump.trans_ptr->len;
2790 		dump_file->file_len = cpu_to_le32(file_len);
2791 	}
2792 
2793 	sg_dump_data = alloc_sgtable(file_len);
2794 	if (sg_dump_data) {
2795 		sg_pcopy_from_buffer(sg_dump_data,
2796 				     sg_nents(sg_dump_data),
2797 				     fw_error_dump.fwrt_ptr,
2798 				     fw_error_dump.fwrt_len, 0);
2799 		if (fw_error_dump.trans_ptr)
2800 			sg_pcopy_from_buffer(sg_dump_data,
2801 					     sg_nents(sg_dump_data),
2802 					     fw_error_dump.trans_ptr->data,
2803 					     fw_error_dump.trans_ptr->len,
2804 					     fw_error_dump.fwrt_len);
2805 		dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len,
2806 			       GFP_KERNEL);
2807 	}
2808 	vfree(fw_error_dump.fwrt_ptr);
2809 	vfree(fw_error_dump.trans_ptr);
2810 }
2811 
iwl_dump_ini_list_free(struct list_head * list)2812 static void iwl_dump_ini_list_free(struct list_head *list)
2813 {
2814 	while (!list_empty(list)) {
2815 		struct iwl_fw_ini_dump_entry *entry =
2816 			list_entry(list->next, typeof(*entry), list);
2817 
2818 		list_del(&entry->list);
2819 		vfree(entry);
2820 	}
2821 }
2822 
iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data * dump_data)2823 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data)
2824 {
2825 	dump_data->trig = NULL;
2826 	kfree(dump_data->fw_pkt);
2827 	dump_data->fw_pkt = NULL;
2828 }
2829 
iwl_fw_error_ini_dump(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data)2830 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt,
2831 				  struct iwl_fwrt_dump_data *dump_data)
2832 {
2833 	LIST_HEAD(dump_list);
2834 	struct scatterlist *sg_dump_data;
2835 	u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list);
2836 
2837 	if (!file_len)
2838 		return;
2839 
2840 	sg_dump_data = alloc_sgtable(file_len);
2841 	if (sg_dump_data) {
2842 		struct iwl_fw_ini_dump_entry *entry;
2843 		int sg_entries = sg_nents(sg_dump_data);
2844 		u32 offs = 0;
2845 
2846 		list_for_each_entry(entry, &dump_list, list) {
2847 			sg_pcopy_from_buffer(sg_dump_data, sg_entries,
2848 					     entry->data, entry->size, offs);
2849 			offs += entry->size;
2850 		}
2851 		dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len,
2852 			       GFP_KERNEL);
2853 	}
2854 	iwl_dump_ini_list_free(&dump_list);
2855 }
2856 
2857 const struct iwl_fw_dump_desc iwl_dump_desc_assert = {
2858 	.trig_desc = {
2859 		.type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT),
2860 	},
2861 };
2862 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert);
2863 
iwl_fw_dbg_collect_desc(struct iwl_fw_runtime * fwrt,const struct iwl_fw_dump_desc * desc,bool monitor_only,unsigned int delay)2864 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt,
2865 			    const struct iwl_fw_dump_desc *desc,
2866 			    bool monitor_only,
2867 			    unsigned int delay)
2868 {
2869 	struct iwl_fwrt_wk_data *wk_data;
2870 	unsigned long idx;
2871 
2872 	if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2873 		iwl_fw_free_dump_desc(fwrt, desc);
2874 		return 0;
2875 	}
2876 
2877 	/*
2878 	 * Check there is an available worker.
2879 	 * ffz return value is undefined if no zero exists,
2880 	 * so check against ~0UL first.
2881 	 */
2882 	if (fwrt->dump.active_wks == ~0UL)
2883 		return -EBUSY;
2884 
2885 	idx = ffz(fwrt->dump.active_wks);
2886 
2887 	if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM ||
2888 	    test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks))
2889 		return -EBUSY;
2890 
2891 	wk_data = &fwrt->dump.wks[idx];
2892 
2893 	if (WARN_ON(wk_data->dump_data.desc))
2894 		iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc);
2895 
2896 	wk_data->dump_data.desc = desc;
2897 	wk_data->dump_data.monitor_only = monitor_only;
2898 
2899 	IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n",
2900 		 le32_to_cpu(desc->trig_desc.type));
2901 
2902 	queue_delayed_work(system_unbound_wq, &wk_data->wk,
2903 			   usecs_to_jiffies(delay));
2904 
2905 	return 0;
2906 }
2907 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc);
2908 
iwl_fw_dbg_error_collect(struct iwl_fw_runtime * fwrt,enum iwl_fw_dbg_trigger trig_type)2909 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt,
2910 			     enum iwl_fw_dbg_trigger trig_type)
2911 {
2912 	if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status))
2913 		return -EIO;
2914 
2915 	if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2916 		if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT &&
2917 		    trig_type != FW_DBG_TRIGGER_DRIVER)
2918 			return -EIO;
2919 
2920 		iwl_dbg_tlv_time_point(fwrt,
2921 				       IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT,
2922 				       NULL);
2923 	} else {
2924 		struct iwl_fw_dump_desc *iwl_dump_error_desc;
2925 		int ret;
2926 
2927 		iwl_dump_error_desc =
2928 			kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL);
2929 
2930 		if (!iwl_dump_error_desc)
2931 			return -ENOMEM;
2932 
2933 		iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type);
2934 		iwl_dump_error_desc->len = 0;
2935 
2936 		ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc,
2937 					      false, 0);
2938 		if (ret) {
2939 			kfree(iwl_dump_error_desc);
2940 			return ret;
2941 		}
2942 	}
2943 
2944 	iwl_trans_sync_nmi(fwrt->trans);
2945 
2946 	return 0;
2947 }
2948 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect);
2949 
iwl_fw_dbg_collect(struct iwl_fw_runtime * fwrt,enum iwl_fw_dbg_trigger trig,const char * str,size_t len,struct iwl_fw_dbg_trigger_tlv * trigger)2950 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt,
2951 		       enum iwl_fw_dbg_trigger trig,
2952 		       const char *str, size_t len,
2953 		       struct iwl_fw_dbg_trigger_tlv *trigger)
2954 {
2955 	struct iwl_fw_dump_desc *desc;
2956 	unsigned int delay = 0;
2957 	bool monitor_only = false;
2958 
2959 	if (trigger) {
2960 		u16 occurrences = le16_to_cpu(trigger->occurrences) - 1;
2961 
2962 		if (!le16_to_cpu(trigger->occurrences))
2963 			return 0;
2964 
2965 		if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) {
2966 			IWL_WARN(fwrt, "Force restart: trigger %d fired.\n",
2967 				 trig);
2968 			iwl_force_nmi(fwrt->trans);
2969 			return 0;
2970 		}
2971 
2972 		trigger->occurrences = cpu_to_le16(occurrences);
2973 		monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY;
2974 
2975 		/* convert msec to usec */
2976 		delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC;
2977 	}
2978 
2979 	desc = kzalloc(struct_size(desc, trig_desc.data, len), GFP_ATOMIC);
2980 	if (!desc)
2981 		return -ENOMEM;
2982 
2983 
2984 	desc->len = len;
2985 	desc->trig_desc.type = cpu_to_le32(trig);
2986 	memcpy(desc->trig_desc.data, str, len);
2987 
2988 	return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay);
2989 }
2990 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect);
2991 
iwl_fw_dbg_collect_trig(struct iwl_fw_runtime * fwrt,struct iwl_fw_dbg_trigger_tlv * trigger,const char * fmt,...)2992 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt,
2993 			    struct iwl_fw_dbg_trigger_tlv *trigger,
2994 			    const char *fmt, ...)
2995 {
2996 	int ret, len = 0;
2997 	char buf[64];
2998 
2999 	if (iwl_trans_dbg_ini_valid(fwrt->trans))
3000 		return 0;
3001 
3002 	if (fmt) {
3003 		va_list ap;
3004 
3005 		buf[sizeof(buf) - 1] = '\0';
3006 
3007 		va_start(ap, fmt);
3008 		vsnprintf(buf, sizeof(buf), fmt, ap);
3009 		va_end(ap);
3010 
3011 		/* check for truncation */
3012 		if (WARN_ON_ONCE(buf[sizeof(buf) - 1]))
3013 			buf[sizeof(buf) - 1] = '\0';
3014 
3015 		len = strlen(buf) + 1;
3016 	}
3017 
3018 	ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len,
3019 				 trigger);
3020 
3021 	if (ret)
3022 		return ret;
3023 
3024 	return 0;
3025 }
3026 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig);
3027 
iwl_fw_start_dbg_conf(struct iwl_fw_runtime * fwrt,u8 conf_id)3028 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id)
3029 {
3030 	u8 *ptr;
3031 	int ret;
3032 	int i;
3033 
3034 	if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv),
3035 		      "Invalid configuration %d\n", conf_id))
3036 		return -EINVAL;
3037 
3038 	/* EARLY START - firmware's configuration is hard coded */
3039 	if ((!fwrt->fw->dbg.conf_tlv[conf_id] ||
3040 	     !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) &&
3041 	    conf_id == FW_DBG_START_FROM_ALIVE)
3042 		return 0;
3043 
3044 	if (!fwrt->fw->dbg.conf_tlv[conf_id])
3045 		return -EINVAL;
3046 
3047 	if (fwrt->dump.conf != FW_DBG_INVALID)
3048 		IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n",
3049 			 fwrt->dump.conf);
3050 
3051 	/* Send all HCMDs for configuring the FW debug */
3052 	ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd;
3053 	for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) {
3054 		struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
3055 		struct iwl_host_cmd hcmd = {
3056 			.id = cmd->id,
3057 			.len = { le16_to_cpu(cmd->len), },
3058 			.data = { cmd->data, },
3059 		};
3060 
3061 		ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
3062 		if (ret)
3063 			return ret;
3064 
3065 		ptr += sizeof(*cmd);
3066 		ptr += le16_to_cpu(cmd->len);
3067 	}
3068 
3069 	fwrt->dump.conf = conf_id;
3070 
3071 	return 0;
3072 }
3073 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf);
3074 
iwl_send_dbg_dump_complete_cmd(struct iwl_fw_runtime * fwrt,u32 timepoint,u32 timepoint_data)3075 void iwl_send_dbg_dump_complete_cmd(struct iwl_fw_runtime *fwrt,
3076 				    u32 timepoint,
3077 				    u32 timepoint_data)
3078 {
3079 	struct iwl_dbg_dump_complete_cmd hcmd_data;
3080 	struct iwl_host_cmd hcmd = {
3081 		.id = WIDE_ID(DEBUG_GROUP, FW_DUMP_COMPLETE_CMD),
3082 		.data[0] = &hcmd_data,
3083 		.len[0] = sizeof(hcmd_data),
3084 	};
3085 
3086 	if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status))
3087 		return;
3088 
3089 	if (fw_has_capa(&fwrt->fw->ucode_capa,
3090 			IWL_UCODE_TLV_CAPA_DUMP_COMPLETE_SUPPORT)) {
3091 		hcmd_data.tp = cpu_to_le32(timepoint);
3092 		hcmd_data.tp_data = cpu_to_le32(timepoint_data);
3093 		iwl_trans_send_cmd(fwrt->trans, &hcmd);
3094 	}
3095 }
3096 
3097 /* this function assumes dump_start was called beforehand and dump_end will be
3098  * called afterwards
3099  */
iwl_fw_dbg_collect_sync(struct iwl_fw_runtime * fwrt,u8 wk_idx)3100 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx)
3101 {
3102 	struct iwl_fw_dbg_params params = {0};
3103 	struct iwl_fwrt_dump_data *dump_data =
3104 		&fwrt->dump.wks[wk_idx].dump_data;
3105 	if (!test_bit(wk_idx, &fwrt->dump.active_wks))
3106 		return;
3107 
3108 	/* also checks 'desc' for pre-ini mode, since that shadows in union */
3109 	if (!dump_data->trig) {
3110 		IWL_ERR(fwrt, "dump trigger data is not set\n");
3111 		goto out;
3112 	}
3113 
3114 	if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) {
3115 		IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n");
3116 		goto out;
3117 	}
3118 
3119 	/* there's no point in fw dump if the bus is dead */
3120 	if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) {
3121 		IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n");
3122 		goto out;
3123 	}
3124 
3125 	iwl_fw_dbg_stop_restart_recording(fwrt, &params, true);
3126 
3127 	IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n");
3128 	if (iwl_trans_dbg_ini_valid(fwrt->trans))
3129 		iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data);
3130 	else
3131 		iwl_fw_error_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data);
3132 	IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n");
3133 
3134 	iwl_fw_dbg_stop_restart_recording(fwrt, &params, false);
3135 
3136 	if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
3137 		u32 policy = le32_to_cpu(dump_data->trig->apply_policy);
3138 		u32 time_point = le32_to_cpu(dump_data->trig->time_point);
3139 
3140 		if (policy & IWL_FW_INI_APPLY_POLICY_DUMP_COMPLETE_CMD) {
3141 			IWL_DEBUG_FW_INFO(fwrt, "WRT: sending dump complete\n");
3142 			iwl_send_dbg_dump_complete_cmd(fwrt, time_point, 0);
3143 		}
3144 	}
3145 
3146 	if (fwrt->trans->dbg.last_tp_resetfw == IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY)
3147 		iwl_force_nmi(fwrt->trans);
3148 
3149 out:
3150 	if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
3151 		iwl_fw_error_dump_data_free(dump_data);
3152 	} else {
3153 		iwl_fw_free_dump_desc(fwrt, dump_data->desc);
3154 		dump_data->desc = NULL;
3155 	}
3156 
3157 	clear_bit(wk_idx, &fwrt->dump.active_wks);
3158 }
3159 
iwl_fw_dbg_ini_collect(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,bool sync)3160 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt,
3161 			   struct iwl_fwrt_dump_data *dump_data,
3162 			   bool sync)
3163 {
3164 	struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig;
3165 	enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point);
3166 	u32 occur, delay;
3167 	unsigned long idx;
3168 
3169 	if (!iwl_fw_ini_trigger_on(fwrt, trig)) {
3170 		IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n",
3171 			 tp_id);
3172 		return -EINVAL;
3173 	}
3174 
3175 	delay = le32_to_cpu(trig->dump_delay);
3176 	occur = le32_to_cpu(trig->occurrences);
3177 	if (!occur)
3178 		return 0;
3179 
3180 	trig->occurrences = cpu_to_le32(--occur);
3181 
3182 	/* Check there is an available worker.
3183 	 * ffz return value is undefined if no zero exists,
3184 	 * so check against ~0UL first.
3185 	 */
3186 	if (fwrt->dump.active_wks == ~0UL)
3187 		return -EBUSY;
3188 
3189 	idx = ffz(fwrt->dump.active_wks);
3190 
3191 	if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM ||
3192 	    test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks))
3193 		return -EBUSY;
3194 
3195 	fwrt->dump.wks[idx].dump_data = *dump_data;
3196 
3197 	if (sync)
3198 		delay = 0;
3199 
3200 	IWL_WARN(fwrt,
3201 		 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n",
3202 		 tp_id, (u32)(delay / USEC_PER_MSEC));
3203 
3204 	if (sync)
3205 		iwl_fw_dbg_collect_sync(fwrt, idx);
3206 	else
3207 		queue_delayed_work(system_unbound_wq,
3208 				   &fwrt->dump.wks[idx].wk,
3209 				   usecs_to_jiffies(delay));
3210 
3211 	return 0;
3212 }
3213 
iwl_fw_error_dump_wk(struct work_struct * work)3214 void iwl_fw_error_dump_wk(struct work_struct *work)
3215 {
3216 	struct iwl_fwrt_wk_data *wks =
3217 		container_of(work, typeof(*wks), wk.work);
3218 	struct iwl_fw_runtime *fwrt =
3219 		container_of(wks, typeof(*fwrt), dump.wks[wks->idx]);
3220 
3221 	/* assumes the op mode mutex is locked in dump_start since
3222 	 * iwl_fw_dbg_collect_sync can't run in parallel
3223 	 */
3224 	if (fwrt->ops && fwrt->ops->dump_start)
3225 		fwrt->ops->dump_start(fwrt->ops_ctx);
3226 
3227 	iwl_fw_dbg_collect_sync(fwrt, wks->idx);
3228 
3229 	if (fwrt->ops && fwrt->ops->dump_end)
3230 		fwrt->ops->dump_end(fwrt->ops_ctx);
3231 }
3232 
iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime * fwrt)3233 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt)
3234 {
3235 	const struct iwl_cfg *cfg = fwrt->trans->cfg;
3236 
3237 	if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt))
3238 		return;
3239 
3240 	if (!fwrt->dump.d3_debug_data) {
3241 		fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length,
3242 						   GFP_KERNEL);
3243 		if (!fwrt->dump.d3_debug_data) {
3244 			IWL_ERR(fwrt,
3245 				"failed to allocate memory for D3 debug data\n");
3246 			return;
3247 		}
3248 	}
3249 
3250 	/* if the buffer holds previous debug data it is overwritten */
3251 	iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr,
3252 				 fwrt->dump.d3_debug_data,
3253 				 cfg->d3_debug_data_length);
3254 
3255 	if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
3256 		fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx,
3257 					     cfg->d3_debug_data_base_addr,
3258 					     fwrt->dump.d3_debug_data,
3259 					     cfg->d3_debug_data_length);
3260 }
3261 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data);
3262 
iwl_fw_dbg_stop_sync(struct iwl_fw_runtime * fwrt)3263 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt)
3264 {
3265 	int i;
3266 
3267 	iwl_dbg_tlv_del_timers(fwrt->trans);
3268 	for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++)
3269 		iwl_fw_dbg_collect_sync(fwrt, i);
3270 
3271 	iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true);
3272 }
3273 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync);
3274 
iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans * trans,bool suspend)3275 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend)
3276 {
3277 	struct iwl_dbg_suspend_resume_cmd cmd = {
3278 		.operation = suspend ?
3279 			cpu_to_le32(DBGC_SUSPEND_CMD) :
3280 			cpu_to_le32(DBGC_RESUME_CMD),
3281 	};
3282 	struct iwl_host_cmd hcmd = {
3283 		.id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME),
3284 		.data[0] = &cmd,
3285 		.len[0] = sizeof(cmd),
3286 	};
3287 
3288 	return iwl_trans_send_cmd(trans, &hcmd);
3289 }
3290 
iwl_fw_dbg_stop_recording(struct iwl_trans * trans,struct iwl_fw_dbg_params * params)3291 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans,
3292 				      struct iwl_fw_dbg_params *params)
3293 {
3294 	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
3295 		iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
3296 		return;
3297 	}
3298 
3299 	if (params) {
3300 		params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE);
3301 		params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL);
3302 	}
3303 
3304 	iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);
3305 	/* wait for the DBGC to finish writing the internal buffer to DRAM to
3306 	 * avoid halting the HW while writing
3307 	 */
3308 	usleep_range(700, 1000);
3309 	iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0);
3310 }
3311 
iwl_fw_dbg_restart_recording(struct iwl_trans * trans,struct iwl_fw_dbg_params * params)3312 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans,
3313 					struct iwl_fw_dbg_params *params)
3314 {
3315 	if (!params)
3316 		return -EIO;
3317 
3318 	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
3319 		iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
3320 		iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
3321 		iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
3322 	} else {
3323 		iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample);
3324 		iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl);
3325 	}
3326 
3327 	return 0;
3328 }
3329 
iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime * fwrt)3330 int iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime *fwrt)
3331 {
3332 	struct iwl_mvm_marker marker = {
3333 		.dw_len = sizeof(struct iwl_mvm_marker) / 4,
3334 		.marker_id = MARKER_ID_SYNC_CLOCK,
3335 	};
3336 	struct iwl_host_cmd hcmd = {
3337 		.flags = CMD_ASYNC,
3338 		.id = WIDE_ID(LONG_GROUP, MARKER_CMD),
3339 		.dataflags = {},
3340 	};
3341 	struct iwl_mvm_marker_rsp *resp;
3342 	int cmd_ver = iwl_fw_lookup_cmd_ver(fwrt->fw,
3343 					    WIDE_ID(LONG_GROUP, MARKER_CMD),
3344 					    IWL_FW_CMD_VER_UNKNOWN);
3345 	int ret;
3346 
3347 	if (cmd_ver == 1) {
3348 		/* the real timestamp is taken from the ftrace clock
3349 		 * this is for finding the match between fw and kernel logs
3350 		 */
3351 		marker.timestamp = cpu_to_le64(fwrt->timestamp.seq++);
3352 	} else if (cmd_ver == 2) {
3353 		marker.timestamp = cpu_to_le64(ktime_get_boottime_ns());
3354 	} else {
3355 		IWL_DEBUG_INFO(fwrt,
3356 			       "Invalid version of Marker CMD. Ver = %d\n",
3357 			       cmd_ver);
3358 		return -EINVAL;
3359 	}
3360 
3361 	hcmd.data[0] = &marker;
3362 	hcmd.len[0] = sizeof(marker);
3363 
3364 	ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
3365 
3366 	if (cmd_ver > 1 && hcmd.resp_pkt) {
3367 		resp = (void *)hcmd.resp_pkt->data;
3368 		IWL_DEBUG_INFO(fwrt, "FW GP2 time: %u\n",
3369 			       le32_to_cpu(resp->gp2));
3370 	}
3371 
3372 	return ret;
3373 }
3374 
iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime * fwrt,struct iwl_fw_dbg_params * params,bool stop)3375 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt,
3376 				       struct iwl_fw_dbg_params *params,
3377 				       bool stop)
3378 {
3379 	int ret __maybe_unused = 0;
3380 
3381 	if (!iwl_trans_fw_running(fwrt->trans))
3382 		return;
3383 
3384 	if (fw_has_capa(&fwrt->fw->ucode_capa,
3385 			IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) {
3386 		if (stop)
3387 			iwl_fw_send_timestamp_marker_cmd(fwrt);
3388 		ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop);
3389 	} else if (stop) {
3390 		iwl_fw_dbg_stop_recording(fwrt->trans, params);
3391 	} else {
3392 		ret = iwl_fw_dbg_restart_recording(fwrt->trans, params);
3393 	}
3394 #ifdef CONFIG_IWLWIFI_DEBUGFS
3395 	if (!ret) {
3396 		if (stop)
3397 			fwrt->trans->dbg.rec_on = false;
3398 		else
3399 			iwl_fw_set_dbg_rec_on(fwrt);
3400 	}
3401 #endif
3402 }
3403 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording);
3404 
iwl_fw_disable_dbg_asserts(struct iwl_fw_runtime * fwrt)3405 void iwl_fw_disable_dbg_asserts(struct iwl_fw_runtime *fwrt)
3406 {
3407 	struct iwl_fw_dbg_config_cmd cmd = {
3408 		.type = cpu_to_le32(DEBUG_TOKEN_CONFIG_TYPE),
3409 		.conf = cpu_to_le32(IWL_FW_DBG_CONFIG_TOKEN),
3410 	};
3411 	struct iwl_host_cmd hcmd = {
3412 		.id = WIDE_ID(LONG_GROUP, LDBG_CONFIG_CMD),
3413 		.data[0] = &cmd,
3414 		.len[0] = sizeof(cmd),
3415 	};
3416 	u32 preset = u32_get_bits(fwrt->trans->dbg.domains_bitmap,
3417 				  GENMASK(31, IWL_FW_DBG_DOMAIN_POS + 1));
3418 
3419 	/* supported starting from 9000 devices */
3420 	if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_9000)
3421 		return;
3422 
3423 	if (fwrt->trans->dbg.yoyo_bin_loaded || (preset && preset != 1))
3424 		return;
3425 
3426 	iwl_trans_send_cmd(fwrt->trans, &hcmd);
3427 }
3428 IWL_EXPORT_SYMBOL(iwl_fw_disable_dbg_asserts);
3429 
iwl_fw_dbg_clear_monitor_buf(struct iwl_fw_runtime * fwrt)3430 void iwl_fw_dbg_clear_monitor_buf(struct iwl_fw_runtime *fwrt)
3431 {
3432 	struct iwl_fw_dbg_params params = {0};
3433 
3434 	iwl_fw_dbg_stop_sync(fwrt);
3435 
3436 	if (fw_has_api(&fwrt->fw->ucode_capa,
3437 		       IWL_UCODE_TLV_API_INT_DBG_BUF_CLEAR)) {
3438 		struct iwl_host_cmd hcmd = {
3439 			.id = WIDE_ID(DEBUG_GROUP, FW_CLEAR_BUFFER),
3440 		};
3441 		iwl_trans_send_cmd(fwrt->trans, &hcmd);
3442 	}
3443 
3444 	iwl_dbg_tlv_init_cfg(fwrt);
3445 	iwl_fw_dbg_stop_restart_recording(fwrt, &params, false);
3446 }
3447 IWL_EXPORT_SYMBOL(iwl_fw_dbg_clear_monitor_buf);
3448