1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2018 The FreeBSD Foundation
5 * Copyright (c) 1992 Terrence R. Lambert.
6 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
11 *
12 * Portions of this software were developed by A. Joseph Koshy under
13 * sponsorship from the FreeBSD Foundation and Google, Inc.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 * SUCH DAMAGE.
42 */
43
44 #include <sys/cdefs.h>
45 #include "opt_apic.h"
46 #include "opt_atpic.h"
47 #include "opt_cpu.h"
48 #include "opt_ddb.h"
49 #include "opt_inet.h"
50 #include "opt_isa.h"
51 #include "opt_kstack_pages.h"
52 #include "opt_maxmem.h"
53 #include "opt_platform.h"
54
55 #include <sys/param.h>
56 #include <sys/proc.h>
57 #include <sys/systm.h>
58 #include <sys/bio.h>
59 #include <sys/buf.h>
60 #include <sys/bus.h>
61 #include <sys/callout.h>
62 #include <sys/cons.h>
63 #include <sys/cpu.h>
64 #include <sys/eventhandler.h>
65 #include <sys/exec.h>
66 #include <sys/imgact.h>
67 #include <sys/kdb.h>
68 #include <sys/kernel.h>
69 #include <sys/ktr.h>
70 #include <sys/linker.h>
71 #include <sys/lock.h>
72 #include <sys/malloc.h>
73 #include <sys/memrange.h>
74 #include <sys/msgbuf.h>
75 #include <sys/mutex.h>
76 #include <sys/pcpu.h>
77 #include <sys/ptrace.h>
78 #include <sys/reboot.h>
79 #include <sys/reg.h>
80 #include <sys/rwlock.h>
81 #include <sys/sched.h>
82 #include <sys/signalvar.h>
83 #include <sys/smp.h>
84 #include <sys/syscallsubr.h>
85 #include <sys/sysctl.h>
86 #include <sys/sysent.h>
87 #include <sys/sysproto.h>
88 #include <sys/ucontext.h>
89 #include <sys/vmmeter.h>
90
91 #include <vm/vm.h>
92 #include <vm/vm_param.h>
93 #include <vm/vm_extern.h>
94 #include <vm/vm_kern.h>
95 #include <vm/vm_page.h>
96 #include <vm/vm_map.h>
97 #include <vm/vm_object.h>
98 #include <vm/vm_pager.h>
99 #include <vm/vm_phys.h>
100 #include <vm/vm_dumpset.h>
101
102 #ifdef DDB
103 #ifndef KDB
104 #error KDB must be enabled in order for DDB to work!
105 #endif
106 #include <ddb/ddb.h>
107 #include <ddb/db_sym.h>
108 #endif
109
110 #include <isa/rtc.h>
111
112 #include <net/netisr.h>
113
114 #include <dev/smbios/smbios.h>
115
116 #include <machine/bootinfo.h>
117 #include <machine/clock.h>
118 #include <machine/cpu.h>
119 #include <machine/cputypes.h>
120 #include <machine/intr_machdep.h>
121 #include <x86/mca.h>
122 #include <machine/md_var.h>
123 #include <machine/metadata.h>
124 #include <machine/pc/bios.h>
125 #include <machine/pcb.h>
126 #include <machine/pcb_ext.h>
127 #include <machine/proc.h>
128 #include <machine/sigframe.h>
129 #include <machine/specialreg.h>
130 #include <machine/sysarch.h>
131 #include <machine/trap.h>
132 #include <x86/ucode.h>
133 #include <machine/vm86.h>
134 #include <x86/init.h>
135 #ifdef SMP
136 #include <machine/smp.h>
137 #endif
138 #ifdef FDT
139 #include <x86/fdt.h>
140 #endif
141
142 #ifdef DEV_APIC
143 #include <x86/apicvar.h>
144 #endif
145
146 #ifdef DEV_ISA
147 #include <x86/isa/icu.h>
148 #endif
149
150 /* Sanity check for __curthread() */
151 CTASSERT(offsetof(struct pcpu, pc_curthread) == 0);
152
153 register_t init386(int first);
154 void dblfault_handler(void);
155 void identify_cpu(void);
156
157 static void cpu_startup(void *);
158 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
159
160 /* Intel ICH registers */
161 #define ICH_PMBASE 0x400
162 #define ICH_SMI_EN ICH_PMBASE + 0x30
163
164 int _udatasel, _ucodesel;
165 u_int basemem;
166 static int above4g_allow = 1;
167 static int above24g_allow = 0;
168
169 int cold = 1;
170
171 long Maxmem = 0;
172 long realmem = 0;
173 int late_console = 1;
174
175 #ifdef PAE
176 FEATURE(pae, "Physical Address Extensions");
177 #endif
178
179 struct kva_md_info kmi;
180
181 static struct trapframe proc0_tf;
182 struct pcpu __pcpu[MAXCPU];
183
184 static void i386_clock_source_init(void);
185
186 struct mtx icu_lock;
187
188 struct mem_range_softc mem_range_softc;
189
190 int fred;
191
192 extern char start_exceptions[], end_exceptions[];
193
194 extern struct sysentvec elf32_freebsd_sysvec;
195
196 /* Default init_ops implementation. */
197 struct init_ops init_ops = {
198 .early_clock_source_init = i386_clock_source_init,
199 .early_delay = i8254_delay,
200 };
201
202 static void
i386_clock_source_init(void)203 i386_clock_source_init(void)
204 {
205 i8254_init();
206 }
207
208 static void
cpu_startup(void * dummy)209 cpu_startup(void *dummy)
210 {
211 uintmax_t memsize;
212 char *sysenv;
213
214 /*
215 * On MacBooks, we need to disallow the legacy USB circuit to
216 * generate an SMI# because this can cause several problems,
217 * namely: incorrect CPU frequency detection and failure to
218 * start the APs.
219 * We do this by disabling a bit in the SMI_EN (SMI Control and
220 * Enable register) of the Intel ICH LPC Interface Bridge.
221 */
222 sysenv = kern_getenv("smbios.system.product");
223 if (sysenv != NULL) {
224 if (strncmp(sysenv, "MacBook1,1", 10) == 0 ||
225 strncmp(sysenv, "MacBook3,1", 10) == 0 ||
226 strncmp(sysenv, "MacBook4,1", 10) == 0 ||
227 strncmp(sysenv, "MacBookPro1,1", 13) == 0 ||
228 strncmp(sysenv, "MacBookPro1,2", 13) == 0 ||
229 strncmp(sysenv, "MacBookPro3,1", 13) == 0 ||
230 strncmp(sysenv, "MacBookPro4,1", 13) == 0 ||
231 strncmp(sysenv, "Macmini1,1", 10) == 0) {
232 if (bootverbose)
233 printf("Disabling LEGACY_USB_EN bit on "
234 "Intel ICH.\n");
235 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8);
236 }
237 freeenv(sysenv);
238 }
239
240 /*
241 * Good {morning,afternoon,evening,night}.
242 */
243 startrtclock();
244 printcpuinfo();
245 panicifcpuunsupported();
246
247 /*
248 * Display physical memory if SMBIOS reports reasonable amount.
249 */
250 memsize = 0;
251 sysenv = kern_getenv("smbios.memory.enabled");
252 if (sysenv != NULL) {
253 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10;
254 freeenv(sysenv);
255 }
256 if (memsize < ptoa((uintmax_t)vm_free_count()))
257 memsize = ptoa((uintmax_t)Maxmem);
258 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20);
259 realmem = atop(memsize);
260
261 /*
262 * Display any holes after the first chunk of extended memory.
263 */
264 if (bootverbose) {
265 int indx;
266
267 printf("Physical memory chunk(s):\n");
268 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
269 vm_paddr_t size;
270
271 size = phys_avail[indx + 1] - phys_avail[indx];
272 printf(
273 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n",
274 (uintmax_t)phys_avail[indx],
275 (uintmax_t)phys_avail[indx + 1] - 1,
276 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE);
277 }
278 }
279
280 vm_ksubmap_init(&kmi);
281
282 printf("avail memory = %ju (%ju MB)\n",
283 ptoa((uintmax_t)vm_free_count()),
284 ptoa((uintmax_t)vm_free_count()) / 1048576);
285
286 /*
287 * Set up buffers, so they can be used to read disk labels.
288 */
289 bufinit();
290 vm_pager_bufferinit();
291 cpu_setregs();
292 }
293
294 void
cpu_setregs(void)295 cpu_setregs(void)
296 {
297 unsigned int cr0;
298
299 cr0 = rcr0();
300
301 /*
302 * CR0_MP, CR0_NE and CR0_TS are set for NPX (FPU) support:
303 *
304 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
305 * instructions. We must set the CR0_MP bit and use the CR0_TS
306 * bit to control the trap, because setting the CR0_EM bit does
307 * not cause WAIT instructions to trap. It's important to trap
308 * WAIT instructions - otherwise the "wait" variants of no-wait
309 * control instructions would degenerate to the "no-wait" variants
310 * after FP context switches but work correctly otherwise. It's
311 * particularly important to trap WAITs when there is no NPX -
312 * otherwise the "wait" variants would always degenerate.
313 *
314 * Try setting CR0_NE to get correct error reporting on 486DX's.
315 * Setting it should fail or do nothing on lesser processors.
316 */
317 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM;
318 load_cr0(cr0);
319 load_gs(_udatasel);
320 }
321
322 u_long bootdev; /* not a struct cdev *- encoding is different */
323 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
324 CTLFLAG_RD, &bootdev, 0, "Maybe the Boot device (not in struct cdev *format)");
325
326 /*
327 * Initialize 386 and configure to run kernel
328 */
329
330 /*
331 * Initialize segments & interrupt table
332 */
333
334 int _default_ldt;
335
336 struct mtx dt_lock; /* lock for GDT and LDT */
337
338 union descriptor gdt0[NGDT]; /* initial global descriptor table */
339 union descriptor *gdt = gdt0; /* global descriptor table */
340
341 union descriptor *ldt; /* local descriptor table */
342
343 static struct gate_descriptor idt0[NIDT];
344 struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
345
346 static struct i386tss *dblfault_tss;
347 static char *dblfault_stack;
348
349 static struct i386tss common_tss0;
350
351 vm_offset_t proc0kstack;
352
353 /*
354 * software prototypes -- in more palatable form.
355 *
356 * GCODE_SEL through GUDATA_SEL must be in this order for syscall/sysret
357 * GUFS_SEL and GUGS_SEL must be in this order (swtch.s knows it)
358 */
359 struct soft_segment_descriptor gdt_segs[] = {
360 /* GNULL_SEL 0 Null Descriptor */
361 { .ssd_base = 0x0,
362 .ssd_limit = 0x0,
363 .ssd_type = 0,
364 .ssd_dpl = SEL_KPL,
365 .ssd_p = 0,
366 .ssd_xx = 0, .ssd_xx1 = 0,
367 .ssd_def32 = 0,
368 .ssd_gran = 0 },
369 /* GPRIV_SEL 1 SMP Per-Processor Private Data Descriptor */
370 { .ssd_base = 0x0,
371 .ssd_limit = 0xfffff,
372 .ssd_type = SDT_MEMRWA,
373 .ssd_dpl = SEL_KPL,
374 .ssd_p = 1,
375 .ssd_xx = 0, .ssd_xx1 = 0,
376 .ssd_def32 = 1,
377 .ssd_gran = 1 },
378 /* GUFS_SEL 2 %fs Descriptor for user */
379 { .ssd_base = 0x0,
380 .ssd_limit = 0xfffff,
381 .ssd_type = SDT_MEMRWA,
382 .ssd_dpl = SEL_UPL,
383 .ssd_p = 1,
384 .ssd_xx = 0, .ssd_xx1 = 0,
385 .ssd_def32 = 1,
386 .ssd_gran = 1 },
387 /* GUGS_SEL 3 %gs Descriptor for user */
388 { .ssd_base = 0x0,
389 .ssd_limit = 0xfffff,
390 .ssd_type = SDT_MEMRWA,
391 .ssd_dpl = SEL_UPL,
392 .ssd_p = 1,
393 .ssd_xx = 0, .ssd_xx1 = 0,
394 .ssd_def32 = 1,
395 .ssd_gran = 1 },
396 /* GCODE_SEL 4 Code Descriptor for kernel */
397 { .ssd_base = 0x0,
398 .ssd_limit = 0xfffff,
399 .ssd_type = SDT_MEMERA,
400 .ssd_dpl = SEL_KPL,
401 .ssd_p = 1,
402 .ssd_xx = 0, .ssd_xx1 = 0,
403 .ssd_def32 = 1,
404 .ssd_gran = 1 },
405 /* GDATA_SEL 5 Data Descriptor for kernel */
406 { .ssd_base = 0x0,
407 .ssd_limit = 0xfffff,
408 .ssd_type = SDT_MEMRWA,
409 .ssd_dpl = SEL_KPL,
410 .ssd_p = 1,
411 .ssd_xx = 0, .ssd_xx1 = 0,
412 .ssd_def32 = 1,
413 .ssd_gran = 1 },
414 /* GUCODE_SEL 6 Code Descriptor for user */
415 { .ssd_base = 0x0,
416 .ssd_limit = 0xfffff,
417 .ssd_type = SDT_MEMERA,
418 .ssd_dpl = SEL_UPL,
419 .ssd_p = 1,
420 .ssd_xx = 0, .ssd_xx1 = 0,
421 .ssd_def32 = 1,
422 .ssd_gran = 1 },
423 /* GUDATA_SEL 7 Data Descriptor for user */
424 { .ssd_base = 0x0,
425 .ssd_limit = 0xfffff,
426 .ssd_type = SDT_MEMRWA,
427 .ssd_dpl = SEL_UPL,
428 .ssd_p = 1,
429 .ssd_xx = 0, .ssd_xx1 = 0,
430 .ssd_def32 = 1,
431 .ssd_gran = 1 },
432 /* GBIOSLOWMEM_SEL 8 BIOS access to realmode segment 0x40, must be #8 in GDT */
433 { .ssd_base = 0x400,
434 .ssd_limit = 0xfffff,
435 .ssd_type = SDT_MEMRWA,
436 .ssd_dpl = SEL_KPL,
437 .ssd_p = 1,
438 .ssd_xx = 0, .ssd_xx1 = 0,
439 .ssd_def32 = 1,
440 .ssd_gran = 1 },
441 /* GPROC0_SEL 9 Proc 0 Tss Descriptor */
442 {
443 .ssd_base = 0x0,
444 .ssd_limit = sizeof(struct i386tss)-1,
445 .ssd_type = SDT_SYS386TSS,
446 .ssd_dpl = 0,
447 .ssd_p = 1,
448 .ssd_xx = 0, .ssd_xx1 = 0,
449 .ssd_def32 = 0,
450 .ssd_gran = 0 },
451 /* GLDT_SEL 10 LDT Descriptor */
452 { .ssd_base = 0,
453 .ssd_limit = sizeof(union descriptor) * NLDT - 1,
454 .ssd_type = SDT_SYSLDT,
455 .ssd_dpl = SEL_UPL,
456 .ssd_p = 1,
457 .ssd_xx = 0, .ssd_xx1 = 0,
458 .ssd_def32 = 0,
459 .ssd_gran = 0 },
460 /* GUSERLDT_SEL 11 User LDT Descriptor per process */
461 { .ssd_base = 0,
462 .ssd_limit = (512 * sizeof(union descriptor)-1),
463 .ssd_type = SDT_SYSLDT,
464 .ssd_dpl = 0,
465 .ssd_p = 1,
466 .ssd_xx = 0, .ssd_xx1 = 0,
467 .ssd_def32 = 0,
468 .ssd_gran = 0 },
469 /* GPANIC_SEL 12 Panic Tss Descriptor */
470 { .ssd_base = 0,
471 .ssd_limit = sizeof(struct i386tss)-1,
472 .ssd_type = SDT_SYS386TSS,
473 .ssd_dpl = 0,
474 .ssd_p = 1,
475 .ssd_xx = 0, .ssd_xx1 = 0,
476 .ssd_def32 = 0,
477 .ssd_gran = 0 },
478 /* GBIOSCODE32_SEL 13 BIOS 32-bit interface (32bit Code) */
479 { .ssd_base = 0,
480 .ssd_limit = 0xfffff,
481 .ssd_type = SDT_MEMERA,
482 .ssd_dpl = 0,
483 .ssd_p = 1,
484 .ssd_xx = 0, .ssd_xx1 = 0,
485 .ssd_def32 = 0,
486 .ssd_gran = 1 },
487 /* GBIOSCODE16_SEL 14 BIOS 32-bit interface (16bit Code) */
488 { .ssd_base = 0,
489 .ssd_limit = 0xfffff,
490 .ssd_type = SDT_MEMERA,
491 .ssd_dpl = 0,
492 .ssd_p = 1,
493 .ssd_xx = 0, .ssd_xx1 = 0,
494 .ssd_def32 = 0,
495 .ssd_gran = 1 },
496 /* GBIOSDATA_SEL 15 BIOS 32-bit interface (Data) */
497 { .ssd_base = 0,
498 .ssd_limit = 0xfffff,
499 .ssd_type = SDT_MEMRWA,
500 .ssd_dpl = 0,
501 .ssd_p = 1,
502 .ssd_xx = 0, .ssd_xx1 = 0,
503 .ssd_def32 = 1,
504 .ssd_gran = 1 },
505 /* GBIOSUTIL_SEL 16 BIOS 16-bit interface (Utility) */
506 { .ssd_base = 0,
507 .ssd_limit = 0xfffff,
508 .ssd_type = SDT_MEMRWA,
509 .ssd_dpl = 0,
510 .ssd_p = 1,
511 .ssd_xx = 0, .ssd_xx1 = 0,
512 .ssd_def32 = 0,
513 .ssd_gran = 1 },
514 /* GBIOSARGS_SEL 17 BIOS 16-bit interface (Arguments) */
515 { .ssd_base = 0,
516 .ssd_limit = 0xfffff,
517 .ssd_type = SDT_MEMRWA,
518 .ssd_dpl = 0,
519 .ssd_p = 1,
520 .ssd_xx = 0, .ssd_xx1 = 0,
521 .ssd_def32 = 0,
522 .ssd_gran = 1 },
523 /* GNDIS_SEL 18 NDIS Descriptor */
524 { .ssd_base = 0x0,
525 .ssd_limit = 0x0,
526 .ssd_type = 0,
527 .ssd_dpl = 0,
528 .ssd_p = 0,
529 .ssd_xx = 0, .ssd_xx1 = 0,
530 .ssd_def32 = 0,
531 .ssd_gran = 0 },
532 };
533
534 static struct soft_segment_descriptor ldt_segs[] = {
535 /* Null Descriptor - overwritten by call gate */
536 { .ssd_base = 0x0,
537 .ssd_limit = 0x0,
538 .ssd_type = 0,
539 .ssd_dpl = 0,
540 .ssd_p = 0,
541 .ssd_xx = 0, .ssd_xx1 = 0,
542 .ssd_def32 = 0,
543 .ssd_gran = 0 },
544 /* Null Descriptor - overwritten by call gate */
545 { .ssd_base = 0x0,
546 .ssd_limit = 0x0,
547 .ssd_type = 0,
548 .ssd_dpl = 0,
549 .ssd_p = 0,
550 .ssd_xx = 0, .ssd_xx1 = 0,
551 .ssd_def32 = 0,
552 .ssd_gran = 0 },
553 /* Null Descriptor - overwritten by call gate */
554 { .ssd_base = 0x0,
555 .ssd_limit = 0x0,
556 .ssd_type = 0,
557 .ssd_dpl = 0,
558 .ssd_p = 0,
559 .ssd_xx = 0, .ssd_xx1 = 0,
560 .ssd_def32 = 0,
561 .ssd_gran = 0 },
562 /* Code Descriptor for user */
563 { .ssd_base = 0x0,
564 .ssd_limit = 0xfffff,
565 .ssd_type = SDT_MEMERA,
566 .ssd_dpl = SEL_UPL,
567 .ssd_p = 1,
568 .ssd_xx = 0, .ssd_xx1 = 0,
569 .ssd_def32 = 1,
570 .ssd_gran = 1 },
571 /* Null Descriptor - overwritten by call gate */
572 { .ssd_base = 0x0,
573 .ssd_limit = 0x0,
574 .ssd_type = 0,
575 .ssd_dpl = 0,
576 .ssd_p = 0,
577 .ssd_xx = 0, .ssd_xx1 = 0,
578 .ssd_def32 = 0,
579 .ssd_gran = 0 },
580 /* Data Descriptor for user */
581 { .ssd_base = 0x0,
582 .ssd_limit = 0xfffff,
583 .ssd_type = SDT_MEMRWA,
584 .ssd_dpl = SEL_UPL,
585 .ssd_p = 1,
586 .ssd_xx = 0, .ssd_xx1 = 0,
587 .ssd_def32 = 1,
588 .ssd_gran = 1 },
589 };
590
591 size_t setidt_disp;
592
593 void
setidt(int idx,inthand_t * func,int typ,int dpl,int selec)594 setidt(int idx, inthand_t *func, int typ, int dpl, int selec)
595 {
596 uintptr_t off;
597
598 off = func != NULL ? (uintptr_t)func + setidt_disp : 0;
599 setidt_nodisp(idx, off, typ, dpl, selec);
600 }
601
602 void
setidt_nodisp(int idx,uintptr_t off,int typ,int dpl,int selec)603 setidt_nodisp(int idx, uintptr_t off, int typ, int dpl, int selec)
604 {
605 struct gate_descriptor *ip;
606
607 ip = idt + idx;
608 ip->gd_looffset = off;
609 ip->gd_selector = selec;
610 ip->gd_stkcpy = 0;
611 ip->gd_xx = 0;
612 ip->gd_type = typ;
613 ip->gd_dpl = dpl;
614 ip->gd_p = 1;
615 ip->gd_hioffset = ((u_int)off) >> 16 ;
616 }
617
618 extern inthand_t
619 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
620 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
621 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
622 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
623 IDTVEC(xmm),
624 #ifdef KDTRACE_HOOKS
625 IDTVEC(dtrace_ret),
626 #endif
627 #ifdef XENHVM
628 IDTVEC(xen_intr_upcall),
629 #endif
630 IDTVEC(int0x80_syscall);
631
632 #ifdef DDB
633 /*
634 * Display the index and function name of any IDT entries that don't use
635 * the default 'rsvd' entry point.
636 */
DB_SHOW_COMMAND_FLAGS(idt,db_show_idt,DB_CMD_MEMSAFE)637 DB_SHOW_COMMAND_FLAGS(idt, db_show_idt, DB_CMD_MEMSAFE)
638 {
639 struct gate_descriptor *ip;
640 int idx;
641 uintptr_t func, func_trm;
642 bool trm;
643
644 ip = idt;
645 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) {
646 if (ip->gd_type == SDT_SYSTASKGT) {
647 db_printf("%3d\t<TASK>\n", idx);
648 } else {
649 func = (ip->gd_hioffset << 16 | ip->gd_looffset);
650 if (func >= PMAP_TRM_MIN_ADDRESS) {
651 func_trm = func;
652 func -= setidt_disp;
653 trm = true;
654 } else
655 trm = false;
656 if (func != (uintptr_t)&IDTVEC(rsvd)) {
657 db_printf("%3d\t", idx);
658 db_printsym(func, DB_STGY_PROC);
659 if (trm)
660 db_printf(" (trampoline %#x)",
661 func_trm);
662 db_printf("\n");
663 }
664 }
665 ip++;
666 }
667 }
668
669 /* Show privileged registers. */
DB_SHOW_COMMAND_FLAGS(sysregs,db_show_sysregs,DB_CMD_MEMSAFE)670 DB_SHOW_COMMAND_FLAGS(sysregs, db_show_sysregs, DB_CMD_MEMSAFE)
671 {
672 uint64_t idtr, gdtr;
673
674 idtr = ridt();
675 db_printf("idtr\t0x%08x/%04x\n",
676 (u_int)(idtr >> 16), (u_int)idtr & 0xffff);
677 gdtr = rgdt();
678 db_printf("gdtr\t0x%08x/%04x\n",
679 (u_int)(gdtr >> 16), (u_int)gdtr & 0xffff);
680 db_printf("ldtr\t0x%04x\n", rldt());
681 db_printf("tr\t0x%04x\n", rtr());
682 db_printf("cr0\t0x%08x\n", rcr0());
683 db_printf("cr2\t0x%08x\n", rcr2());
684 db_printf("cr3\t0x%08x\n", rcr3());
685 db_printf("cr4\t0x%08x\n", rcr4());
686 if (rcr4() & CR4_XSAVE)
687 db_printf("xcr0\t0x%016llx\n", rxcr(0));
688 if (amd_feature & (AMDID_NX | AMDID_LM))
689 db_printf("EFER\t0x%016llx\n", rdmsr(MSR_EFER));
690 if (cpu_feature2 & (CPUID2_VMX | CPUID2_SMX))
691 db_printf("FEATURES_CTL\t0x%016llx\n",
692 rdmsr(MSR_IA32_FEATURE_CONTROL));
693 if (((cpu_vendor_id == CPU_VENDOR_INTEL ||
694 cpu_vendor_id == CPU_VENDOR_AMD) && CPUID_TO_FAMILY(cpu_id) >= 6) ||
695 cpu_vendor_id == CPU_VENDOR_HYGON)
696 db_printf("DEBUG_CTL\t0x%016llx\n", rdmsr(MSR_DEBUGCTLMSR));
697 if (cpu_feature & CPUID_PAT)
698 db_printf("PAT\t0x%016llx\n", rdmsr(MSR_PAT));
699 }
700
DB_SHOW_COMMAND_FLAGS(dbregs,db_show_dbregs,DB_CMD_MEMSAFE)701 DB_SHOW_COMMAND_FLAGS(dbregs, db_show_dbregs, DB_CMD_MEMSAFE)
702 {
703
704 db_printf("dr0\t0x%08x\n", rdr0());
705 db_printf("dr1\t0x%08x\n", rdr1());
706 db_printf("dr2\t0x%08x\n", rdr2());
707 db_printf("dr3\t0x%08x\n", rdr3());
708 db_printf("dr6\t0x%08x\n", rdr6());
709 db_printf("dr7\t0x%08x\n", rdr7());
710 }
711
DB_SHOW_COMMAND(frame,db_show_frame)712 DB_SHOW_COMMAND(frame, db_show_frame)
713 {
714 struct trapframe *frame;
715
716 frame = have_addr ? (struct trapframe *)addr : curthread->td_frame;
717 printf("ss %#x esp %#x efl %#x cs %#x eip %#x\n",
718 frame->tf_ss, frame->tf_esp, frame->tf_eflags, frame->tf_cs,
719 frame->tf_eip);
720 printf("err %#x trapno %d\n", frame->tf_err, frame->tf_trapno);
721 printf("ds %#x es %#x fs %#x\n",
722 frame->tf_ds, frame->tf_es, frame->tf_fs);
723 printf("eax %#x ecx %#x edx %#x ebx %#x\n",
724 frame->tf_eax, frame->tf_ecx, frame->tf_edx, frame->tf_ebx);
725 printf("ebp %#x esi %#x edi %#x\n",
726 frame->tf_ebp, frame->tf_esi, frame->tf_edi);
727
728 }
729 #endif
730
731 void
sdtossd(struct segment_descriptor * sd,struct soft_segment_descriptor * ssd)732 sdtossd(struct segment_descriptor *sd, struct soft_segment_descriptor *ssd)
733 {
734 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
735 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
736 ssd->ssd_type = sd->sd_type;
737 ssd->ssd_dpl = sd->sd_dpl;
738 ssd->ssd_p = sd->sd_p;
739 ssd->ssd_def32 = sd->sd_def32;
740 ssd->ssd_gran = sd->sd_gran;
741 }
742
743 static int
add_physmap_entry(uint64_t base,uint64_t length,vm_paddr_t * physmap,int * physmap_idxp)744 add_physmap_entry(uint64_t base, uint64_t length, vm_paddr_t *physmap,
745 int *physmap_idxp)
746 {
747 uint64_t lim, ign;
748 int i, insert_idx, physmap_idx;
749
750 physmap_idx = *physmap_idxp;
751
752 if (length == 0)
753 return (1);
754
755 lim = 0x100000000; /* 4G */
756 if (pae_mode && above4g_allow)
757 lim = above24g_allow ? -1ULL : 0x600000000; /* 24G */
758 if (base >= lim) {
759 printf("%uK of memory above %uGB ignored, pae %d "
760 "above4g_allow %d above24g_allow %d\n",
761 (u_int)(length / 1024), (u_int)(lim >> 30), pae_mode,
762 above4g_allow, above24g_allow);
763 return (1);
764 }
765 if (base + length >= lim) {
766 ign = base + length - lim;
767 length -= ign;
768 printf("%uK of memory above %uGB ignored, pae %d "
769 "above4g_allow %d above24g_allow %d\n",
770 (u_int)(ign / 1024), (u_int)(lim >> 30), pae_mode,
771 above4g_allow, above24g_allow);
772 }
773
774 /*
775 * Find insertion point while checking for overlap. Start off by
776 * assuming the new entry will be added to the end.
777 */
778 insert_idx = physmap_idx + 2;
779 for (i = 0; i <= physmap_idx; i += 2) {
780 if (base < physmap[i + 1]) {
781 if (base + length <= physmap[i]) {
782 insert_idx = i;
783 break;
784 }
785 if (boothowto & RB_VERBOSE)
786 printf(
787 "Overlapping memory regions, ignoring second region\n");
788 return (1);
789 }
790 }
791
792 /* See if we can prepend to the next entry. */
793 if (insert_idx <= physmap_idx && base + length == physmap[insert_idx]) {
794 physmap[insert_idx] = base;
795 return (1);
796 }
797
798 /* See if we can append to the previous entry. */
799 if (insert_idx > 0 && base == physmap[insert_idx - 1]) {
800 physmap[insert_idx - 1] += length;
801 return (1);
802 }
803
804 physmap_idx += 2;
805 *physmap_idxp = physmap_idx;
806 if (physmap_idx == PHYS_AVAIL_ENTRIES) {
807 printf(
808 "Too many segments in the physical address map, giving up\n");
809 return (0);
810 }
811
812 /*
813 * Move the last 'N' entries down to make room for the new
814 * entry if needed.
815 */
816 for (i = physmap_idx; i > insert_idx; i -= 2) {
817 physmap[i] = physmap[i - 2];
818 physmap[i + 1] = physmap[i - 1];
819 }
820
821 /* Insert the new entry. */
822 physmap[insert_idx] = base;
823 physmap[insert_idx + 1] = base + length;
824 return (1);
825 }
826
827 static int
add_smap_entry(struct bios_smap * smap,vm_paddr_t * physmap,int * physmap_idxp)828 add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp)
829 {
830 if (boothowto & RB_VERBOSE)
831 printf("SMAP type=%02x base=%016llx len=%016llx\n",
832 smap->type, smap->base, smap->length);
833
834 if (smap->type != SMAP_TYPE_MEMORY)
835 return (1);
836
837 return (add_physmap_entry(smap->base, smap->length, physmap,
838 physmap_idxp));
839 }
840
841 static void
add_smap_entries(struct bios_smap * smapbase,vm_paddr_t * physmap,int * physmap_idxp)842 add_smap_entries(struct bios_smap *smapbase, vm_paddr_t *physmap,
843 int *physmap_idxp)
844 {
845 struct bios_smap *smap, *smapend;
846 u_int32_t smapsize;
847 /*
848 * Memory map from INT 15:E820.
849 *
850 * subr_module.c says:
851 * "Consumer may safely assume that size value precedes data."
852 * ie: an int32_t immediately precedes SMAP.
853 */
854 smapsize = *((u_int32_t *)smapbase - 1);
855 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
856
857 for (smap = smapbase; smap < smapend; smap++)
858 if (!add_smap_entry(smap, physmap, physmap_idxp))
859 break;
860 }
861
862 static void
basemem_setup(void)863 basemem_setup(void)
864 {
865
866 if (basemem > 640) {
867 printf("Preposterous BIOS basemem of %uK, truncating to 640K\n",
868 basemem);
869 basemem = 640;
870 }
871
872 pmap_basemem_setup(basemem);
873 }
874
875 /*
876 * Populate the (physmap) array with base/bound pairs describing the
877 * available physical memory in the system, then test this memory and
878 * build the phys_avail array describing the actually-available memory.
879 *
880 * If we cannot accurately determine the physical memory map, then use
881 * value from the 0xE801 call, and failing that, the RTC.
882 *
883 * Total memory size may be set by the kernel environment variable
884 * hw.physmem or the compile-time define MAXMEM.
885 *
886 * XXX first should be vm_paddr_t.
887 */
888 static void
getmemsize(int first)889 getmemsize(int first)
890 {
891 int has_smap, off, physmap_idx, pa_indx, da_indx;
892 u_long memtest;
893 vm_paddr_t physmap[PHYS_AVAIL_ENTRIES];
894 quad_t dcons_addr, dcons_size, physmem_tunable;
895 int hasbrokenint12, i, res __diagused;
896 u_int extmem;
897 struct vm86frame vmf;
898 struct vm86context vmc;
899 vm_paddr_t pa;
900 struct bios_smap *smap, *smapbase;
901
902 has_smap = 0;
903 bzero(&vmf, sizeof(vmf));
904 bzero(physmap, sizeof(physmap));
905 basemem = 0;
906
907 /*
908 * Tell the physical memory allocator about pages used to store
909 * the kernel and preloaded data. See kmem_bootstrap_free().
910 */
911 vm_phys_early_add_seg((vm_paddr_t)KERNLOAD, trunc_page(first));
912
913 TUNABLE_INT_FETCH("hw.above4g_allow", &above4g_allow);
914 TUNABLE_INT_FETCH("hw.above24g_allow", &above24g_allow);
915
916 /*
917 * Check if the loader supplied an SMAP memory map. If so,
918 * use that and do not make any VM86 calls.
919 */
920 physmap_idx = 0;
921 smapbase = (struct bios_smap *)preload_search_info(preload_kmdp,
922 MODINFO_METADATA | MODINFOMD_SMAP);
923 if (smapbase != NULL) {
924 add_smap_entries(smapbase, physmap, &physmap_idx);
925 has_smap = 1;
926 goto have_smap;
927 }
928
929 /*
930 * Some newer BIOSes have a broken INT 12H implementation
931 * which causes a kernel panic immediately. In this case, we
932 * need use the SMAP to determine the base memory size.
933 */
934 hasbrokenint12 = 0;
935 TUNABLE_INT_FETCH("hw.hasbrokenint12", &hasbrokenint12);
936 if (hasbrokenint12 == 0) {
937 /* Use INT12 to determine base memory size. */
938 vm86_intcall(0x12, &vmf);
939 basemem = vmf.vmf_ax;
940 basemem_setup();
941 }
942
943 /*
944 * Fetch the memory map with INT 15:E820. Map page 1 R/W into
945 * the kernel page table so we can use it as a buffer. The
946 * kernel will unmap this page later.
947 */
948 vmc.npages = 0;
949 smap = (void *)vm86_addpage(&vmc, 1, PMAP_MAP_LOW + ptoa(1));
950 res = vm86_getptr(&vmc, (vm_offset_t)smap, &vmf.vmf_es, &vmf.vmf_di);
951 KASSERT(res != 0, ("vm86_getptr() failed: address not found"));
952
953 vmf.vmf_ebx = 0;
954 do {
955 vmf.vmf_eax = 0xE820;
956 vmf.vmf_edx = SMAP_SIG;
957 vmf.vmf_ecx = sizeof(struct bios_smap);
958 i = vm86_datacall(0x15, &vmf, &vmc);
959 if (i || vmf.vmf_eax != SMAP_SIG)
960 break;
961 has_smap = 1;
962 if (!add_smap_entry(smap, physmap, &physmap_idx))
963 break;
964 } while (vmf.vmf_ebx != 0);
965
966 have_smap:
967 /*
968 * If we didn't fetch the "base memory" size from INT12,
969 * figure it out from the SMAP (or just guess).
970 */
971 if (basemem == 0) {
972 for (i = 0; i <= physmap_idx; i += 2) {
973 if (physmap[i] == 0x00000000) {
974 basemem = physmap[i + 1] / 1024;
975 break;
976 }
977 }
978
979 /* XXX: If we couldn't find basemem from SMAP, just guess. */
980 if (basemem == 0)
981 basemem = 640;
982 basemem_setup();
983 }
984
985 if (physmap[1] != 0)
986 goto physmap_done;
987
988 /*
989 * If we failed to find an SMAP, figure out the extended
990 * memory size. We will then build a simple memory map with
991 * two segments, one for "base memory" and the second for
992 * "extended memory". Note that "extended memory" starts at a
993 * physical address of 1MB and that both basemem and extmem
994 * are in units of 1KB.
995 *
996 * First, try to fetch the extended memory size via INT 15:E801.
997 */
998 vmf.vmf_ax = 0xE801;
999 if (vm86_intcall(0x15, &vmf) == 0) {
1000 extmem = vmf.vmf_cx + vmf.vmf_dx * 64;
1001 } else {
1002 /*
1003 * If INT15:E801 fails, this is our last ditch effort
1004 * to determine the extended memory size. Currently
1005 * we prefer the RTC value over INT15:88.
1006 */
1007 #if 0
1008 vmf.vmf_ah = 0x88;
1009 vm86_intcall(0x15, &vmf);
1010 extmem = vmf.vmf_ax;
1011 #else
1012 extmem = rtcin(RTC_EXTLO) + (rtcin(RTC_EXTHI) << 8);
1013 #endif
1014 }
1015
1016 /*
1017 * Special hack for chipsets that still remap the 384k hole when
1018 * there's 16MB of memory - this really confuses people that
1019 * are trying to use bus mastering ISA controllers with the
1020 * "16MB limit"; they only have 16MB, but the remapping puts
1021 * them beyond the limit.
1022 *
1023 * If extended memory is between 15-16MB (16-17MB phys address range),
1024 * chop it to 15MB.
1025 */
1026 if ((extmem > 15 * 1024) && (extmem < 16 * 1024))
1027 extmem = 15 * 1024;
1028
1029 physmap[0] = 0;
1030 physmap[1] = basemem * 1024;
1031 physmap_idx = 2;
1032 physmap[physmap_idx] = 0x100000;
1033 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024;
1034
1035 physmap_done:
1036 /*
1037 * Now, physmap contains a map of physical memory.
1038 */
1039
1040 #ifdef SMP
1041 /* make hole for AP bootstrap code */
1042 alloc_ap_trampoline(physmap, &physmap_idx);
1043 #endif
1044
1045 /*
1046 * Maxmem isn't the "maximum memory", it's one larger than the
1047 * highest page of the physical address space. It should be
1048 * called something like "Maxphyspage". We may adjust this
1049 * based on ``hw.physmem'' and the results of the memory test.
1050 *
1051 * This is especially confusing when it is much larger than the
1052 * memory size and is displayed as "realmem".
1053 */
1054 Maxmem = atop(physmap[physmap_idx + 1]);
1055
1056 #ifdef MAXMEM
1057 Maxmem = MAXMEM / 4;
1058 #endif
1059
1060 if (TUNABLE_QUAD_FETCH("hw.physmem", &physmem_tunable))
1061 Maxmem = atop(physmem_tunable);
1062
1063 /*
1064 * If we have an SMAP, don't allow MAXMEM or hw.physmem to extend
1065 * the amount of memory in the system.
1066 */
1067 if (has_smap && Maxmem > atop(physmap[physmap_idx + 1]))
1068 Maxmem = atop(physmap[physmap_idx + 1]);
1069
1070 /*
1071 * The boot memory test is disabled by default, as it takes a
1072 * significant amount of time on large-memory systems, and is
1073 * unfriendly to virtual machines as it unnecessarily touches all
1074 * pages.
1075 *
1076 * A general name is used as the code may be extended to support
1077 * additional tests beyond the current "page present" test.
1078 */
1079 memtest = 0;
1080 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest);
1081
1082 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1083 (boothowto & RB_VERBOSE))
1084 printf("Physical memory use set to %ldK\n", Maxmem * 4);
1085
1086 /*
1087 * If Maxmem has been increased beyond what the system has detected,
1088 * extend the last memory segment to the new limit.
1089 */
1090 if (atop(physmap[physmap_idx + 1]) < Maxmem)
1091 physmap[physmap_idx + 1] = ptoa((vm_paddr_t)Maxmem);
1092
1093 /* call pmap initialization to make new kernel address space */
1094 pmap_bootstrap(first);
1095
1096 /*
1097 * Size up each available chunk of physical memory.
1098 */
1099 physmap[0] = PAGE_SIZE; /* mask off page 0 */
1100 pa_indx = 0;
1101 da_indx = 1;
1102 phys_avail[pa_indx++] = physmap[0];
1103 phys_avail[pa_indx] = physmap[0];
1104 dump_avail[da_indx] = physmap[0];
1105
1106 /*
1107 * Get dcons buffer address
1108 */
1109 if (getenv_quad("dcons.addr", &dcons_addr) == 0 ||
1110 getenv_quad("dcons.size", &dcons_size) == 0)
1111 dcons_addr = 0;
1112
1113 /*
1114 * physmap is in bytes, so when converting to page boundaries,
1115 * round up the start address and round down the end address.
1116 */
1117 for (i = 0; i <= physmap_idx; i += 2) {
1118 vm_paddr_t end;
1119
1120 end = ptoa((vm_paddr_t)Maxmem);
1121 if (physmap[i + 1] < end)
1122 end = trunc_page(physmap[i + 1]);
1123 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
1124 int *ptr;
1125 int tmp;
1126 bool full, page_bad;
1127
1128 full = false;
1129 /*
1130 * block out kernel memory as not available.
1131 */
1132 if (pa >= KERNLOAD && pa < first)
1133 goto do_dump_avail;
1134
1135 /*
1136 * block out dcons buffer
1137 */
1138 if (dcons_addr > 0
1139 && pa >= trunc_page(dcons_addr)
1140 && pa < dcons_addr + dcons_size)
1141 goto do_dump_avail;
1142
1143 page_bad = false;
1144 if (memtest == 0)
1145 goto skip_memtest;
1146
1147 /*
1148 * map page into kernel: valid, read/write,non-cacheable
1149 */
1150 ptr = (int *)pmap_cmap3(pa, PG_V | PG_RW | PG_N);
1151
1152 tmp = *(int *)ptr;
1153 /*
1154 * Test for alternating 1's and 0's
1155 */
1156 *(volatile int *)ptr = 0xaaaaaaaa;
1157 if (*(volatile int *)ptr != 0xaaaaaaaa)
1158 page_bad = true;
1159 /*
1160 * Test for alternating 0's and 1's
1161 */
1162 *(volatile int *)ptr = 0x55555555;
1163 if (*(volatile int *)ptr != 0x55555555)
1164 page_bad = true;
1165 /*
1166 * Test for all 1's
1167 */
1168 *(volatile int *)ptr = 0xffffffff;
1169 if (*(volatile int *)ptr != 0xffffffff)
1170 page_bad = true;
1171 /*
1172 * Test for all 0's
1173 */
1174 *(volatile int *)ptr = 0x0;
1175 if (*(volatile int *)ptr != 0x0)
1176 page_bad = true;
1177 /*
1178 * Restore original value.
1179 */
1180 *(int *)ptr = tmp;
1181
1182 skip_memtest:
1183 /*
1184 * Adjust array of valid/good pages.
1185 */
1186 if (page_bad == true)
1187 continue;
1188 /*
1189 * If this good page is a continuation of the
1190 * previous set of good pages, then just increase
1191 * the end pointer. Otherwise start a new chunk.
1192 * Note that "end" points one higher than end,
1193 * making the range >= start and < end.
1194 * If we're also doing a speculative memory
1195 * test and we at or past the end, bump up Maxmem
1196 * so that we keep going. The first bad page
1197 * will terminate the loop.
1198 */
1199 if (phys_avail[pa_indx] == pa) {
1200 phys_avail[pa_indx] += PAGE_SIZE;
1201 } else {
1202 pa_indx++;
1203 if (pa_indx == PHYS_AVAIL_ENTRIES) {
1204 printf(
1205 "Too many holes in the physical address space, giving up\n");
1206 pa_indx--;
1207 full = true;
1208 goto do_dump_avail;
1209 }
1210 phys_avail[pa_indx++] = pa; /* start */
1211 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
1212 }
1213 physmem++;
1214 do_dump_avail:
1215 if (dump_avail[da_indx] == pa) {
1216 dump_avail[da_indx] += PAGE_SIZE;
1217 } else {
1218 da_indx++;
1219 if (da_indx == PHYS_AVAIL_ENTRIES) {
1220 da_indx--;
1221 goto do_next;
1222 }
1223 dump_avail[da_indx++] = pa; /* start */
1224 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */
1225 }
1226 do_next:
1227 if (full)
1228 break;
1229 }
1230 }
1231 pmap_cmap3(0, 0);
1232
1233 /*
1234 * XXX
1235 * The last chunk must contain at least one page plus the message
1236 * buffer to avoid complicating other code (message buffer address
1237 * calculation, etc.).
1238 */
1239 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
1240 round_page(msgbufsize) >= phys_avail[pa_indx]) {
1241 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1242 phys_avail[pa_indx--] = 0;
1243 phys_avail[pa_indx--] = 0;
1244 }
1245
1246 Maxmem = atop(phys_avail[pa_indx]);
1247
1248 /* Trim off space for the message buffer. */
1249 phys_avail[pa_indx] -= round_page(msgbufsize);
1250
1251 /* Map the message buffer. */
1252 for (off = 0; off < round_page(msgbufsize); off += PAGE_SIZE)
1253 pmap_kenter((vm_offset_t)msgbufp + off, phys_avail[pa_indx] +
1254 off);
1255 }
1256
1257 static void
i386_kdb_init(void)1258 i386_kdb_init(void)
1259 {
1260 #ifdef DDB
1261 db_fetch_ksymtab(bootinfo.bi_symtab, bootinfo.bi_esymtab, 0);
1262 #endif
1263 kdb_init();
1264 #ifdef KDB
1265 if (boothowto & RB_KDB)
1266 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
1267 #endif
1268 }
1269
1270 static void
fixup_idt(void)1271 fixup_idt(void)
1272 {
1273 struct gate_descriptor *ip;
1274 uintptr_t off;
1275 int x;
1276
1277 for (x = 0; x < NIDT; x++) {
1278 ip = &idt[x];
1279 if (ip->gd_type != SDT_SYS386IGT &&
1280 ip->gd_type != SDT_SYS386TGT)
1281 continue;
1282 off = ip->gd_looffset + (((u_int)ip->gd_hioffset) << 16);
1283 KASSERT(off >= (uintptr_t)start_exceptions &&
1284 off < (uintptr_t)end_exceptions,
1285 ("IDT[%d] type %d off %#x", x, ip->gd_type, off));
1286 off += setidt_disp;
1287 MPASS(off >= PMAP_TRM_MIN_ADDRESS &&
1288 off < PMAP_TRM_MAX_ADDRESS);
1289 ip->gd_looffset = off;
1290 ip->gd_hioffset = off >> 16;
1291 }
1292 }
1293
1294 static void
i386_setidt1(void)1295 i386_setidt1(void)
1296 {
1297 int x;
1298
1299 /* exceptions */
1300 for (x = 0; x < NIDT; x++)
1301 setidt(x, &IDTVEC(rsvd), SDT_SYS386IGT, SEL_KPL,
1302 GSEL(GCODE_SEL, SEL_KPL));
1303 setidt(IDT_DE, &IDTVEC(div), SDT_SYS386IGT, SEL_KPL,
1304 GSEL(GCODE_SEL, SEL_KPL));
1305 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYS386IGT, SEL_KPL,
1306 GSEL(GCODE_SEL, SEL_KPL));
1307 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYS386IGT, SEL_KPL,
1308 GSEL(GCODE_SEL, SEL_KPL));
1309 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYS386IGT, SEL_UPL,
1310 GSEL(GCODE_SEL, SEL_KPL));
1311 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYS386IGT, SEL_UPL,
1312 GSEL(GCODE_SEL, SEL_KPL));
1313 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYS386IGT, SEL_KPL,
1314 GSEL(GCODE_SEL, SEL_KPL));
1315 setidt(IDT_UD, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL,
1316 GSEL(GCODE_SEL, SEL_KPL));
1317 setidt(IDT_NM, &IDTVEC(dna), SDT_SYS386IGT, SEL_KPL,
1318 GSEL(GCODE_SEL, SEL_KPL));
1319 setidt(IDT_DF, 0, SDT_SYSTASKGT, SEL_KPL, GSEL(GPANIC_SEL,
1320 SEL_KPL));
1321 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYS386IGT,
1322 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1323 setidt(IDT_TS, &IDTVEC(tss), SDT_SYS386IGT, SEL_KPL,
1324 GSEL(GCODE_SEL, SEL_KPL));
1325 setidt(IDT_NP, &IDTVEC(missing), SDT_SYS386IGT, SEL_KPL,
1326 GSEL(GCODE_SEL, SEL_KPL));
1327 setidt(IDT_SS, &IDTVEC(stk), SDT_SYS386IGT, SEL_KPL,
1328 GSEL(GCODE_SEL, SEL_KPL));
1329 setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL,
1330 GSEL(GCODE_SEL, SEL_KPL));
1331 setidt(IDT_PF, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL,
1332 GSEL(GCODE_SEL, SEL_KPL));
1333 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYS386IGT, SEL_KPL,
1334 GSEL(GCODE_SEL, SEL_KPL));
1335 setidt(IDT_AC, &IDTVEC(align), SDT_SYS386IGT, SEL_KPL,
1336 GSEL(GCODE_SEL, SEL_KPL));
1337 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYS386IGT, SEL_KPL,
1338 GSEL(GCODE_SEL, SEL_KPL));
1339 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYS386IGT, SEL_KPL,
1340 GSEL(GCODE_SEL, SEL_KPL));
1341 setidt(IDT_SYSCALL, &IDTVEC(int0x80_syscall),
1342 SDT_SYS386IGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
1343 #ifdef KDTRACE_HOOKS
1344 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret),
1345 SDT_SYS386IGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
1346 #endif
1347 #ifdef XENHVM
1348 setidt(IDT_EVTCHN, &IDTVEC(xen_intr_upcall),
1349 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1350 #endif
1351 }
1352
1353 static void
i386_setidt2(void)1354 i386_setidt2(void)
1355 {
1356
1357 setidt(IDT_UD, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL,
1358 GSEL(GCODE_SEL, SEL_KPL));
1359 setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL,
1360 GSEL(GCODE_SEL, SEL_KPL));
1361 }
1362
1363 #if defined(DEV_ISA) && !defined(DEV_ATPIC)
1364 static void
i386_setidt3(void)1365 i386_setidt3(void)
1366 {
1367
1368 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint),
1369 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1370 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint),
1371 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1372 }
1373 #endif
1374
1375 register_t
init386(int first)1376 init386(int first)
1377 {
1378 struct region_descriptor r_gdt, r_idt; /* table descriptors */
1379 int gsel_tss, metadata_missing, x, pa;
1380 struct pcpu *pc;
1381 struct xstate_hdr *xhdr;
1382 vm_offset_t addend;
1383 size_t ucode_len;
1384
1385 thread0.td_kstack = (char *)proc0kstack;
1386 thread0.td_kstack_pages = TD0_KSTACK_PAGES;
1387
1388 /*
1389 * This may be done better later if it gets more high level
1390 * components in it. If so just link td->td_proc here.
1391 */
1392 proc_linkup0(&proc0, &thread0);
1393
1394 if (bootinfo.bi_modulep) {
1395 metadata_missing = 0;
1396 addend = (vm_paddr_t)bootinfo.bi_modulep < KERNBASE ?
1397 PMAP_MAP_LOW : 0;
1398 preload_metadata = (caddr_t)bootinfo.bi_modulep + addend;
1399 preload_bootstrap_relocate(addend);
1400 } else {
1401 metadata_missing = 1;
1402 }
1403
1404 if (bootinfo.bi_envp != 0) {
1405 addend = (vm_paddr_t)bootinfo.bi_envp < KERNBASE ?
1406 PMAP_MAP_LOW : 0;
1407 init_static_kenv((char *)bootinfo.bi_envp + addend, 0);
1408 } else {
1409 init_static_kenv(NULL, 0);
1410 }
1411
1412 /*
1413 * Re-evaluate CPU features if we loaded a microcode update.
1414 */
1415 ucode_len = ucode_load_bsp(first);
1416 if (ucode_len != 0) {
1417 identify_cpu();
1418 first = roundup2(first + ucode_len, PAGE_SIZE);
1419 }
1420
1421 identify_hypervisor();
1422 identify_hypervisor_smbios();
1423
1424 /* Init basic tunables, hz etc */
1425 init_param1();
1426
1427 /* Set bootmethod to BIOS: it's the only supported on i386. */
1428 strlcpy(bootmethod, "BIOS", sizeof(bootmethod));
1429
1430 /*
1431 * Make gdt memory segments. All segments cover the full 4GB
1432 * of address space and permissions are enforced at page level.
1433 */
1434 gdt_segs[GCODE_SEL].ssd_limit = atop(0 - 1);
1435 gdt_segs[GDATA_SEL].ssd_limit = atop(0 - 1);
1436 gdt_segs[GUCODE_SEL].ssd_limit = atop(0 - 1);
1437 gdt_segs[GUDATA_SEL].ssd_limit = atop(0 - 1);
1438 gdt_segs[GUFS_SEL].ssd_limit = atop(0 - 1);
1439 gdt_segs[GUGS_SEL].ssd_limit = atop(0 - 1);
1440
1441 pc = &__pcpu[0];
1442 gdt_segs[GPRIV_SEL].ssd_limit = atop(0 - 1);
1443 gdt_segs[GPRIV_SEL].ssd_base = (int)pc;
1444 gdt_segs[GPROC0_SEL].ssd_base = (int)&common_tss0;
1445
1446 for (x = 0; x < NGDT; x++)
1447 ssdtosd(&gdt_segs[x], &gdt0[x].sd);
1448
1449 r_gdt.rd_limit = NGDT * sizeof(gdt0[0]) - 1;
1450 r_gdt.rd_base = (int)gdt0;
1451 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_SPIN);
1452 lgdt(&r_gdt);
1453
1454 pcpu_init(pc, 0, sizeof(struct pcpu));
1455 for (pa = first; pa < first + DPCPU_SIZE; pa += PAGE_SIZE)
1456 pmap_kenter(pa, pa);
1457 dpcpu_init((void *)first, 0);
1458 first += DPCPU_SIZE;
1459 PCPU_SET(prvspace, pc);
1460 PCPU_SET(curthread, &thread0);
1461 /* Non-late cninit() and printf() can be moved up to here. */
1462
1463 /*
1464 * Initialize mutexes.
1465 *
1466 * icu_lock: in order to allow an interrupt to occur in a critical
1467 * section, to set pcpu->ipending (etc...) properly, we
1468 * must be able to get the icu lock, so it can't be
1469 * under witness.
1470 */
1471 mutex_init();
1472 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS | MTX_NOPROFILE);
1473
1474 i386_setidt1();
1475
1476 r_idt.rd_limit = sizeof(idt0) - 1;
1477 r_idt.rd_base = (int) idt;
1478 lidt(&r_idt);
1479
1480 finishidentcpu(); /* Final stage of CPU initialization */
1481
1482 /*
1483 * Initialize the clock before the console so that console
1484 * initialization can use DELAY().
1485 */
1486 clock_init();
1487
1488 i386_setidt2();
1489 pmap_set_nx();
1490 initializecpu(); /* Initialize CPU registers */
1491 initializecpucache();
1492
1493 /* pointer to selector slot for %fs/%gs */
1494 PCPU_SET(fsgs_gdt, &gdt[GUFS_SEL].sd);
1495
1496 /* Initialize the tss (except for the final esp0) early for vm86. */
1497 common_tss0.tss_esp0 = (vm_offset_t)td_kstack_top(&thread0) -
1498 VM86_STACK_SPACE;
1499 common_tss0.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
1500 common_tss0.tss_ioopt = sizeof(struct i386tss) << 16;
1501 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
1502 PCPU_SET(tss_gdt, &gdt[GPROC0_SEL].sd);
1503 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
1504 ltr(gsel_tss);
1505
1506 /* Initialize the PIC early for vm86 calls. */
1507 #ifdef DEV_ISA
1508 #ifdef DEV_ATPIC
1509 elcr_probe();
1510 atpic_startup();
1511 #else
1512 /* Reset and mask the atpics and leave them shut down. */
1513 atpic_reset();
1514
1515 /*
1516 * Point the ICU spurious interrupt vectors at the APIC spurious
1517 * interrupt handler.
1518 */
1519 i386_setidt3();
1520 #endif
1521 #endif
1522
1523 /*
1524 * The console and kdb should be initialized even earlier than here,
1525 * but some console drivers don't work until after getmemsize().
1526 * Default to late console initialization to support these drivers.
1527 * This loses mainly printf()s in getmemsize() and early debugging.
1528 */
1529 TUNABLE_INT_FETCH("debug.late_console", &late_console);
1530 if (!late_console) {
1531 cninit();
1532 i386_kdb_init();
1533 }
1534
1535 if (cpu_fxsr && (cpu_feature2 & CPUID2_XSAVE) != 0) {
1536 use_xsave = 1;
1537 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
1538 }
1539
1540 /* Initialize preload_kmdp */
1541 preload_initkmdp(!metadata_missing);
1542 sched_instance_select();
1543 link_elf_ireloc();
1544
1545 vm86_initialize();
1546 getmemsize(first);
1547 init_param2(physmem);
1548
1549 /* now running on new page tables, configured,and u/iom is accessible */
1550
1551 if (late_console)
1552 cninit();
1553
1554 if (metadata_missing)
1555 printf("WARNING: loader(8) metadata is missing!\n");
1556
1557 if (late_console)
1558 i386_kdb_init();
1559
1560 msgbufinit(msgbufp, msgbufsize);
1561 npxinit(true);
1562
1563 /*
1564 * Set up thread0 pcb after npxinit calculated pcb + fpu save
1565 * area size. Zero out the extended state header in fpu save
1566 * area.
1567 */
1568 thread0.td_pcb = get_pcb_td(&thread0);
1569 thread0.td_pcb->pcb_save = get_pcb_user_save_td(&thread0);
1570 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size);
1571 if (use_xsave) {
1572 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) +
1573 1);
1574 xhdr->xstate_bv = xsave_mask;
1575 }
1576 PCPU_SET(curpcb, thread0.td_pcb);
1577 /* Move esp0 in the tss to its final place. */
1578 /* Note: -16 is so we can grow the trapframe if we came from vm86 */
1579 common_tss0.tss_esp0 = (vm_offset_t)thread0.td_pcb - VM86_STACK_SPACE;
1580 PCPU_SET(kesp0, common_tss0.tss_esp0);
1581 gdt[GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; /* clear busy bit */
1582 ltr(gsel_tss);
1583
1584 /* transfer to user mode */
1585
1586 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
1587 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
1588
1589 /* setup proc 0's pcb */
1590 thread0.td_pcb->pcb_flags = 0;
1591 thread0.td_pcb->pcb_cr3 = pmap_get_kcr3();
1592 thread0.td_pcb->pcb_ext = 0;
1593 thread0.td_frame = &proc0_tf;
1594
1595 #ifdef FDT
1596 x86_init_fdt();
1597 #endif
1598
1599 /* Location of kernel stack for locore */
1600 return ((register_t)thread0.td_pcb);
1601 }
1602
1603 static void
machdep_init_trampoline(void * dummy __unused)1604 machdep_init_trampoline(void *dummy __unused)
1605 {
1606 struct region_descriptor r_gdt, r_idt;
1607 struct i386tss *tss;
1608 char *copyout_buf, *trampoline, *tramp_stack_base;
1609 int x;
1610
1611 gdt = pmap_trm_alloc(sizeof(union descriptor) * NGDT * mp_ncpus,
1612 M_NOWAIT | M_ZERO);
1613 bcopy(gdt0, gdt, sizeof(union descriptor) * NGDT);
1614 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1615 r_gdt.rd_base = (int)gdt;
1616 lgdt(&r_gdt);
1617
1618 tss = pmap_trm_alloc(sizeof(struct i386tss) * mp_ncpus,
1619 M_NOWAIT | M_ZERO);
1620 bcopy(&common_tss0, tss, sizeof(struct i386tss));
1621 gdt[GPROC0_SEL].sd.sd_lobase = (int)tss;
1622 gdt[GPROC0_SEL].sd.sd_hibase = (u_int)tss >> 24;
1623 gdt[GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
1624
1625 PCPU_SET(fsgs_gdt, &gdt[GUFS_SEL].sd);
1626 PCPU_SET(tss_gdt, &gdt[GPROC0_SEL].sd);
1627 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
1628 PCPU_SET(common_tssp, tss);
1629 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1630
1631 trampoline = pmap_trm_alloc(end_exceptions - start_exceptions,
1632 M_NOWAIT);
1633 bcopy(start_exceptions, trampoline, end_exceptions - start_exceptions);
1634 tramp_stack_base = pmap_trm_alloc(TRAMP_STACK_SZ, M_NOWAIT);
1635 PCPU_SET(trampstk, (uintptr_t)tramp_stack_base + TRAMP_STACK_SZ -
1636 VM86_STACK_SPACE);
1637 tss[0].tss_esp0 = PCPU_GET(trampstk);
1638
1639 idt = pmap_trm_alloc(sizeof(idt0), M_NOWAIT | M_ZERO);
1640 bcopy(idt0, idt, sizeof(idt0));
1641
1642 /* Re-initialize new IDT since the handlers were relocated */
1643 setidt_disp = trampoline - start_exceptions;
1644 if (bootverbose)
1645 printf("Trampoline disposition %#zx\n", setidt_disp);
1646 fixup_idt();
1647
1648 r_idt.rd_limit = sizeof(struct gate_descriptor) * NIDT - 1;
1649 r_idt.rd_base = (int)idt;
1650 lidt(&r_idt);
1651
1652 /* dblfault TSS */
1653 dblfault_tss = pmap_trm_alloc(sizeof(struct i386tss), M_NOWAIT | M_ZERO);
1654 dblfault_stack = pmap_trm_alloc(PAGE_SIZE, M_NOWAIT);
1655 dblfault_tss->tss_esp = dblfault_tss->tss_esp0 =
1656 dblfault_tss->tss_esp1 = dblfault_tss->tss_esp2 =
1657 (int)dblfault_stack + PAGE_SIZE;
1658 dblfault_tss->tss_ss = dblfault_tss->tss_ss0 = dblfault_tss->tss_ss1 =
1659 dblfault_tss->tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
1660 dblfault_tss->tss_cr3 = pmap_get_kcr3();
1661 dblfault_tss->tss_eip = (int)dblfault_handler;
1662 dblfault_tss->tss_eflags = PSL_KERNEL;
1663 dblfault_tss->tss_ds = dblfault_tss->tss_es =
1664 dblfault_tss->tss_gs = GSEL(GDATA_SEL, SEL_KPL);
1665 dblfault_tss->tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
1666 dblfault_tss->tss_cs = GSEL(GCODE_SEL, SEL_KPL);
1667 dblfault_tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
1668 gdt[GPANIC_SEL].sd.sd_lobase = (int)dblfault_tss;
1669 gdt[GPANIC_SEL].sd.sd_hibase = (u_int)dblfault_tss >> 24;
1670
1671 /* make ldt memory segments */
1672 ldt = pmap_trm_alloc(sizeof(union descriptor) * NLDT,
1673 M_NOWAIT | M_ZERO);
1674 gdt[GLDT_SEL].sd.sd_lobase = (int)ldt;
1675 gdt[GLDT_SEL].sd.sd_hibase = (u_int)ldt >> 24;
1676 ldt_segs[LUCODE_SEL].ssd_limit = atop(0 - 1);
1677 ldt_segs[LUDATA_SEL].ssd_limit = atop(0 - 1);
1678 for (x = 0; x < nitems(ldt_segs); x++)
1679 ssdtosd(&ldt_segs[x], &ldt[x].sd);
1680
1681 _default_ldt = GSEL(GLDT_SEL, SEL_KPL);
1682 lldt(_default_ldt);
1683 PCPU_SET(currentldt, _default_ldt);
1684
1685 copyout_buf = pmap_trm_alloc(TRAMP_COPYOUT_SZ, M_NOWAIT);
1686 PCPU_SET(copyout_buf, copyout_buf);
1687 copyout_init_tramp();
1688 }
1689 SYSINIT(vm_mem, SI_SUB_VM, SI_ORDER_SECOND, machdep_init_trampoline, NULL);
1690
1691 #ifdef COMPAT_43
1692 static void
i386_setup_lcall_gate(void)1693 i386_setup_lcall_gate(void)
1694 {
1695 struct sysentvec *sv;
1696 struct user_segment_descriptor desc;
1697 u_int lcall_addr;
1698
1699 sv = &elf32_freebsd_sysvec;
1700 lcall_addr = (uintptr_t)sv->sv_psstrings - sz_lcall_tramp;
1701
1702 bzero(&desc, sizeof(desc));
1703 desc.sd_type = SDT_MEMERA;
1704 desc.sd_dpl = SEL_UPL;
1705 desc.sd_p = 1;
1706 desc.sd_def32 = 1;
1707 desc.sd_gran = 1;
1708 desc.sd_lolimit = 0xffff;
1709 desc.sd_hilimit = 0xf;
1710 desc.sd_lobase = lcall_addr;
1711 desc.sd_hibase = lcall_addr >> 24;
1712 bcopy(&desc, &ldt[LSYS5CALLS_SEL], sizeof(desc));
1713 }
1714 SYSINIT(elf32, SI_SUB_EXEC, SI_ORDER_ANY, i386_setup_lcall_gate, NULL);
1715 #endif
1716
1717 void
cpu_pcpu_init(struct pcpu * pcpu,int cpuid,size_t size)1718 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
1719 {
1720
1721 pcpu->pc_acpi_id = 0xffffffff;
1722 }
1723
1724 static int
smap_sysctl_handler(SYSCTL_HANDLER_ARGS)1725 smap_sysctl_handler(SYSCTL_HANDLER_ARGS)
1726 {
1727 struct bios_smap *smapbase;
1728 struct bios_smap_xattr smap;
1729 uint32_t *smapattr;
1730 int count, error, i;
1731
1732 /* Retrieve the system memory map from the loader. */
1733 smapbase = (struct bios_smap *)preload_search_info(preload_kmdp,
1734 MODINFO_METADATA | MODINFOMD_SMAP);
1735 if (smapbase == NULL)
1736 return (0);
1737 smapattr = (uint32_t *)preload_search_info(preload_kmdp,
1738 MODINFO_METADATA | MODINFOMD_SMAP_XATTR);
1739 count = *((u_int32_t *)smapbase - 1) / sizeof(*smapbase);
1740 error = 0;
1741 for (i = 0; i < count; i++) {
1742 smap.base = smapbase[i].base;
1743 smap.length = smapbase[i].length;
1744 smap.type = smapbase[i].type;
1745 if (smapattr != NULL)
1746 smap.xattr = smapattr[i];
1747 else
1748 smap.xattr = 0;
1749 error = SYSCTL_OUT(req, &smap, sizeof(smap));
1750 }
1751 return (error);
1752 }
1753 SYSCTL_PROC(_machdep, OID_AUTO, smap,
1754 CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
1755 smap_sysctl_handler, "S,bios_smap_xattr",
1756 "Raw BIOS SMAP data");
1757
1758 void
spinlock_enter(void)1759 spinlock_enter(void)
1760 {
1761 struct thread *td;
1762 register_t flags;
1763
1764 td = curthread;
1765 if (td->td_md.md_spinlock_count == 0) {
1766 flags = intr_disable();
1767 td->td_md.md_spinlock_count = 1;
1768 td->td_md.md_saved_flags = flags;
1769 critical_enter();
1770 } else
1771 td->td_md.md_spinlock_count++;
1772 }
1773
1774 void
spinlock_exit(void)1775 spinlock_exit(void)
1776 {
1777 struct thread *td;
1778 register_t flags;
1779
1780 td = curthread;
1781 flags = td->td_md.md_saved_flags;
1782 td->td_md.md_spinlock_count--;
1783 if (td->td_md.md_spinlock_count == 0) {
1784 critical_exit();
1785 intr_restore(flags);
1786 }
1787 }
1788
1789 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
1790 static void f00f_hack(void *unused);
1791 SYSINIT(f00f_hack, SI_SUB_INTRINSIC, SI_ORDER_FIRST, f00f_hack, NULL);
1792
1793 static void
f00f_hack(void * unused)1794 f00f_hack(void *unused)
1795 {
1796 struct region_descriptor r_idt;
1797 struct gate_descriptor *new_idt;
1798 vm_offset_t tmp;
1799
1800 if (!has_f00f_bug)
1801 return;
1802
1803 printf("Intel Pentium detected, installing workaround for F00F bug\n");
1804
1805 tmp = (vm_offset_t)pmap_trm_alloc(PAGE_SIZE * 3, M_NOWAIT | M_ZERO);
1806 if (tmp == 0)
1807 panic("kmem_malloc returned 0");
1808 tmp = round_page(tmp);
1809
1810 /* Put the problematic entry (#6) at the end of the lower page. */
1811 new_idt = (struct gate_descriptor *)
1812 (tmp + PAGE_SIZE - 7 * sizeof(struct gate_descriptor));
1813 bcopy(idt, new_idt, sizeof(idt0));
1814 r_idt.rd_base = (u_int)new_idt;
1815 r_idt.rd_limit = sizeof(idt0) - 1;
1816 lidt(&r_idt);
1817 /* SMP machines do not need the F00F hack. */
1818 idt = new_idt;
1819 pmap_protect(kernel_pmap, tmp, tmp + PAGE_SIZE, VM_PROT_READ);
1820 }
1821 #endif /* defined(I586_CPU) && !NO_F00F_HACK */
1822
1823 /*
1824 * Construct a PCB from a trapframe. This is called from kdb_trap() where
1825 * we want to start a backtrace from the function that caused us to enter
1826 * the debugger. We have the context in the trapframe, but base the trace
1827 * on the PCB. The PCB doesn't have to be perfect, as long as it contains
1828 * enough for a backtrace.
1829 */
1830 void
makectx(struct trapframe * tf,struct pcb * pcb)1831 makectx(struct trapframe *tf, struct pcb *pcb)
1832 {
1833
1834 pcb->pcb_edi = tf->tf_edi;
1835 pcb->pcb_esi = tf->tf_esi;
1836 pcb->pcb_ebp = tf->tf_ebp;
1837 pcb->pcb_ebx = tf->tf_ebx;
1838 pcb->pcb_eip = tf->tf_eip;
1839 pcb->pcb_esp = (ISPL(tf->tf_cs)) ? tf->tf_esp : (int)(tf + 1) - 8;
1840 pcb->pcb_gs = rgs();
1841 }
1842
1843 #ifdef KDB
1844
1845 /*
1846 * Provide inb() and outb() as functions. They are normally only available as
1847 * inline functions, thus cannot be called from the debugger.
1848 */
1849
1850 /* silence compiler warnings */
1851 u_char inb_(u_short);
1852 void outb_(u_short, u_char);
1853
1854 u_char
inb_(u_short port)1855 inb_(u_short port)
1856 {
1857 return inb(port);
1858 }
1859
1860 void
outb_(u_short port,u_char data)1861 outb_(u_short port, u_char data)
1862 {
1863 outb(port, data);
1864 }
1865
1866 #endif /* KDB */
1867