1 /* 2 * Copyright (c) 2026 Abdelkader Boudih <freebsd@seuros.com> 3 * 4 * SPDX-License-Identifier: BSD-2-Clause 5 */ 6 7 #ifndef _DEV_FIREWIRE_FWCAM_H_ 8 #define _DEV_FIREWIRE_FWCAM_H_ 9 10 /* 11 * IIDC 1394-based Digital Camera Specification v1.30 12 * Register offsets relative to command_regs_base 13 */ 14 15 /* Section 1.1 - Camera initialize register */ 16 #define IIDC_INITIALIZE 0x000 17 18 /* Section 1.2 - Inquiry registers for video format/mode/frame rate */ 19 #define IIDC_V_FORMAT_INQ 0x100 20 #define IIDC_V_MODE_INQ(f) (0x180 + (f) * 4) 21 #define IIDC_V_RATE_INQ(f, m) (0x200 + (f) * 0x20 + (m) * 4) 22 23 /* Section 1.3 - Inquiry register for basic function */ 24 #define IIDC_BASIC_FUNC_INQ 0x400 25 26 /* Section 1.4 - Inquiry registers for feature presence */ 27 #define IIDC_FEATURE_HI_INQ 0x404 28 #define IIDC_FEATURE_LO_INQ 0x408 29 30 /* Section 1.5 - Inquiry registers for feature elements (per feature) */ 31 #define IIDC_BRIGHTNESS_INQ 0x500 32 #define IIDC_AUTO_EXPOSURE_INQ 0x504 33 #define IIDC_SHARPNESS_INQ 0x508 34 #define IIDC_WHITE_BAL_INQ 0x50C 35 #define IIDC_HUE_INQ 0x510 36 #define IIDC_SATURATION_INQ 0x514 37 #define IIDC_GAMMA_INQ 0x518 38 #define IIDC_SHUTTER_INQ 0x51C 39 #define IIDC_GAIN_INQ 0x520 40 #define IIDC_IRIS_INQ 0x524 41 #define IIDC_FOCUS_INQ 0x528 42 #define IIDC_TEMPERATURE_INQ 0x52C 43 #define IIDC_TRIGGER_INQ 0x530 44 45 /* Section 1.6 - Status and control registers for camera */ 46 #define IIDC_CUR_V_FRM_RATE 0x600 47 #define IIDC_CUR_V_MODE 0x604 48 #define IIDC_CUR_V_FORMAT 0x608 49 #define IIDC_ISO_CHANNEL 0x60C 50 #define IIDC_CAMERA_POWER 0x610 51 #define IIDC_ISO_EN 0x614 52 #define IIDC_MEMORY_SAVE 0x618 53 #define IIDC_ONE_SHOT 0x61C 54 #define IIDC_MEM_SAVE_CH 0x620 55 #define IIDC_CUR_MEM_CH 0x624 56 57 /* Section 1.7 - Status and control register for features */ 58 #define IIDC_BRIGHTNESS 0x800 59 #define IIDC_AUTO_EXPOSURE 0x804 60 #define IIDC_SHARPNESS 0x808 61 #define IIDC_WHITE_BALANCE 0x80C 62 #define IIDC_HUE 0x810 63 #define IIDC_SATURATION 0x814 64 #define IIDC_GAMMA 0x818 65 #define IIDC_SHUTTER 0x81C 66 #define IIDC_GAIN 0x820 67 #define IIDC_IRIS 0x824 68 #define IIDC_FOCUS 0x828 69 #define IIDC_TEMPERATURE 0x82C 70 #define IIDC_TRIGGER_MODE 0x830 71 #define IIDC_ZOOM 0x880 72 #define IIDC_PAN 0x884 73 #define IIDC_TILT 0x888 74 75 /* Video format indices (CUR_V_FORMAT register) */ 76 #define IIDC_FMT_VGA 0 /* Format_0: VGA non-compressed */ 77 #define IIDC_FMT_SVGA1 1 /* Format_1: Super VGA (1) */ 78 #define IIDC_FMT_SVGA2 2 /* Format_2: Super VGA (2) */ 79 #define IIDC_FMT_STILL 6 /* Format_6: Still image */ 80 #define IIDC_FMT_PARTIAL 7 /* Format_7: Partial/scalable */ 81 82 /* V_FORMAT_INQ bits */ 83 #define IIDC_FORMAT_VGA (1 << 31) /* Format_0: VGA */ 84 #define IIDC_FORMAT_SVGA1 (1 << 30) /* Format_1: Super VGA (1) */ 85 #define IIDC_FORMAT_SVGA2 (1 << 29) /* Format_2: Super VGA (2) */ 86 #define IIDC_FORMAT_STILL (1 << 25) /* Format_6: Still image */ 87 #define IIDC_FORMAT_PARTIAL (1 << 24) /* Format_7: Partial image */ 88 89 /* ISO_CHANNEL register fields */ 90 #define IIDC_ISO_CH_MASK 0xf0000000 /* bits [0..3] */ 91 #define IIDC_ISO_CH_SHIFT 28 92 #define IIDC_ISO_SPEED_MASK 0x03000000 /* bits [6..7] */ 93 #define IIDC_ISO_SPEED_SHIFT 24 94 95 /* CAMERA_POWER register */ 96 #define IIDC_POWER_ON (1 << 31) /* bit [0] */ 97 98 /* ISO_EN register */ 99 #define IIDC_ISO_EN_ON (1 << 31) /* bit [0] */ 100 101 /* BASIC_FUNC_INQ bits */ 102 #define IIDC_ADV_FEATURE_INQ (1 << 31) /* bit [0] */ 103 #define IIDC_CAM_POWER_CTRL (1 << 15) /* bit [16] */ 104 #define IIDC_ONE_SHOT_INQ (1 << 12) /* bit [19] */ 105 #define IIDC_MULTI_SHOT_INQ (1 << 11) /* bit [20] */ 106 107 /* FEATURE_HI_INQ bits (feature presence, section 1.4) */ 108 #define IIDC_HAS_BRIGHTNESS (1 << 31) 109 #define IIDC_HAS_AUTO_EXPOSURE (1 << 30) 110 #define IIDC_HAS_SHARPNESS (1 << 29) 111 #define IIDC_HAS_WHITE_BALANCE (1 << 28) 112 #define IIDC_HAS_HUE (1 << 27) 113 #define IIDC_HAS_SATURATION (1 << 26) 114 #define IIDC_HAS_GAMMA (1 << 25) 115 #define IIDC_HAS_SHUTTER (1 << 24) 116 #define IIDC_HAS_GAIN (1 << 23) 117 #define IIDC_HAS_IRIS (1 << 22) 118 #define IIDC_HAS_FOCUS (1 << 21) 119 #define IIDC_HAS_TEMPERATURE (1 << 20) 120 #define IIDC_HAS_TRIGGER (1 << 19) 121 122 /* Config ROM: IIDC unit-dependent directory command_regs_base key */ 123 #define IIDC_CROM_CMD_BASE (CSRTYPE_C | 0x00) /* 0x40 */ 124 125 /* 126 * Frame size limits for Format_0 (VGA non-compressed): 127 * Mode_1: 320x240 YUV422 = 153,600 bytes 128 * Mode_2: 640x480 YUV411 = 460,800 bytes 129 * Mode_3: 640x480 YUV422 = 614,400 bytes 130 */ 131 /* 132 * ioctl interface 133 */ 134 struct fwcam_mode { 135 uint8_t format; /* IIDC video format (0-7) */ 136 uint8_t mode; /* IIDC video mode (0-7) */ 137 uint8_t framerate; /* IIDC frame rate (0-7) */ 138 uint8_t _pad; 139 uint32_t frame_size; /* computed frame size in bytes (read-only) */ 140 }; 141 142 struct fwcam_feature { 143 uint32_t id; /* FWCAM_FEAT_* */ 144 uint32_t flags; /* FWCAM_FEATF_* (from INQ, read-only) */ 145 uint32_t min; /* minimum value (from INQ, read-only) */ 146 uint32_t max; /* maximum value (from INQ, read-only) */ 147 uint32_t value; /* current value / value to set */ 148 uint32_t value2; /* second value (white balance V) */ 149 }; 150 151 /* Feature IDs (index into IIDC feature register space) */ 152 #define FWCAM_FEAT_BRIGHTNESS 0 153 #define FWCAM_FEAT_AUTO_EXPOSURE 1 154 #define FWCAM_FEAT_SHARPNESS 2 155 #define FWCAM_FEAT_WHITE_BALANCE 3 156 #define FWCAM_FEAT_HUE 4 157 #define FWCAM_FEAT_SATURATION 5 158 #define FWCAM_FEAT_GAMMA 6 159 #define FWCAM_FEAT_SHUTTER 7 160 #define FWCAM_FEAT_GAIN 8 161 #define FWCAM_FEAT_IRIS 9 162 #define FWCAM_FEAT_FOCUS 10 163 #define FWCAM_FEAT_TEMPERATURE 11 164 #define FWCAM_FEAT_TRIGGER 12 165 #define FWCAM_FEAT_ZOOM 13 166 #define FWCAM_FEAT_PAN 14 167 #define FWCAM_FEAT_TILT 15 168 #define FWCAM_FEAT_MAX 16 169 170 /* Feature flags (from INQ register bits) */ 171 #define FWCAM_FEATF_PRESENT (1 << 0) /* feature is present */ 172 #define FWCAM_FEATF_ONOFF (1 << 1) /* supports on/off */ 173 #define FWCAM_FEATF_AUTO (1 << 2) /* supports auto mode */ 174 #define FWCAM_FEATF_MANUAL (1 << 3) /* supports manual mode */ 175 176 struct fwcam_info { 177 uint32_t formats; /* V_FORMAT_INQ bitmask */ 178 uint32_t basic_func; /* BASIC_FUNC_INQ */ 179 uint32_t features_hi; /* FEATURE_HI_INQ */ 180 uint32_t features_lo; /* FEATURE_LO_INQ */ 181 uint8_t cur_format; 182 uint8_t cur_mode; 183 uint8_t cur_framerate; 184 uint8_t state; /* FWCAM_STATE_* */ 185 uint32_t frame_size; 186 uint32_t frame_dropped; 187 uint8_t iso_channel; /* active ISO receive channel */ 188 uint8_t _pad[3]; 189 }; 190 191 #define FWCAM_GMODE _IOR('C', 1, struct fwcam_mode) 192 #define FWCAM_SMODE _IOWR('C', 2, struct fwcam_mode) 193 #define FWCAM_GFEAT _IOWR('C', 3, struct fwcam_feature) 194 #define FWCAM_SFEAT _IOW('C', 4, struct fwcam_feature) 195 #define FWCAM_GINFO _IOR('C', 5, struct fwcam_info) 196 197 /* fwcam state values (visible to userland via fwcam_info.state) */ 198 #define FWCAM_STATE_IDLE 0 199 #define FWCAM_STATE_PROBED 1 200 #define FWCAM_STATE_STREAMING 2 201 #define FWCAM_STATE_DETACHING 3 202 203 /* 204 * Internal constants 205 */ 206 #define FWCAM_MAX_FRAME_SIZE (640 * 480 * 3) /* 921,600 (RGB24) */ 207 #define FWCAM_ISO_NCHUNK 256 /* receive DMA chunks */ 208 #define FWCAM_ISO_PKTSIZE 2048 /* max iso packet size (MCLBYTES) */ 209 210 #ifdef _KERNEL 211 struct fwcam_softc { 212 struct firewire_dev_comm fd; /* must be first */ 213 struct mtx mtx; 214 struct cdev *cdev; 215 216 /* Remote camera node */ 217 struct fw_device *fwdev; 218 219 /* IIDC command register addressing */ 220 uint16_t cmd_hi; /* always 0xffff */ 221 uint32_t cmd_lo; /* 0xf0000000 | (base << 2) */ 222 223 /* Capabilities from INQ registers */ 224 uint32_t formats; /* V_FORMAT_INQ */ 225 uint32_t basic_func; /* BASIC_FUNC_INQ */ 226 uint32_t features_hi; /* FEATURE_HI_INQ */ 227 uint32_t features_lo; /* FEATURE_LO_INQ */ 228 229 /* Current settings */ 230 uint8_t cur_format; 231 uint8_t cur_mode; 232 uint8_t cur_framerate; 233 uint8_t iso_channel; 234 uint8_t iso_speed; 235 236 /* Deferred probe task */ 237 struct task probe_task; 238 239 /* Isochronous receive */ 240 int dma_ch; /* IR DMA channel, -1 if none */ 241 int iso_active; /* iso_input running */ 242 243 /* Frame assembly (double buffer) */ 244 uint8_t *frame_buf; /* frame being assembled */ 245 uint8_t *read_buf; /* completed frame for read() */ 246 uint32_t frame_size; /* expected frame size (bytes) */ 247 uint32_t frame_offset; /* write position in frame_buf */ 248 int frame_ready; /* read_buf has valid frame */ 249 int read_in_progress; /* uiomove active on read_buf */ 250 int frame_dropped; /* dropped frame count */ 251 int open_count; /* cdev open count */ 252 struct selinfo rsel; /* poll/select/kqueue */ 253 254 /* State: one of FWCAM_STATE_* */ 255 int state; 256 }; 257 258 #define FWCAM_LOCK(sc) mtx_lock(&(sc)->mtx) 259 #define FWCAM_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 260 261 #endif /* _KERNEL */ 262 263 #endif /* _DEV_FIREWIRE_FWCAM_H_ */ 264