1 /*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <net/flow_dissector.h>
34 #include <net/flow_offload.h>
35 #include <net/sch_generic.h>
36 #include <net/pkt_cls.h>
37 #include <linux/mlx5/fs.h>
38 #include <linux/mlx5/device.h>
39 #include <linux/rhashtable.h>
40 #include <linux/refcount.h>
41 #include <linux/completion.h>
42 #include <net/arp.h>
43 #include <net/ipv6_stubs.h>
44 #include <net/bareudp.h>
45 #include <net/bonding.h>
46 #include <net/dst_metadata.h>
47 #include "devlink.h"
48 #include "en.h"
49 #include "en/tc/post_act.h"
50 #include "en/tc/act_stats.h"
51 #include "en_rep.h"
52 #include "en/rep/tc.h"
53 #include "en/rep/neigh.h"
54 #include "en_tc.h"
55 #include "eswitch.h"
56 #include "fs_core.h"
57 #include "en/port.h"
58 #include "en/tc_tun.h"
59 #include "en/mapping.h"
60 #include "en/tc_ct.h"
61 #include "en/mod_hdr.h"
62 #include "en/tc_tun_encap.h"
63 #include "en/tc/sample.h"
64 #include "en/tc/act/act.h"
65 #include "en/tc/post_meter.h"
66 #include "lib/devcom.h"
67 #include "lib/geneve.h"
68 #include "lib/fs_chains.h"
69 #include "diag/en_tc_tracepoint.h"
70 #include <asm/div64.h>
71 #include "lag/lag.h"
72 #include "lag/mp.h"
73
74 #define MLX5E_TC_TABLE_NUM_GROUPS 4
75 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
76
77 struct mlx5e_tc_table {
78 /* Protects the dynamic assignment of the t parameter
79 * which is the nic tc root table.
80 */
81 struct mutex t_lock;
82 struct mlx5e_priv *priv;
83 struct mlx5_flow_table *t;
84 struct mlx5_flow_table *miss_t;
85 struct mlx5_fs_chains *chains;
86 struct mlx5e_post_act *post_act;
87
88 struct rhashtable ht;
89
90 struct mod_hdr_tbl mod_hdr;
91 struct mutex hairpin_tbl_lock; /* protects hairpin_tbl */
92 DECLARE_HASHTABLE(hairpin_tbl, 8);
93
94 struct notifier_block netdevice_nb;
95 struct netdev_net_notifier netdevice_nn;
96
97 struct mlx5_tc_ct_priv *ct;
98 struct mapping_ctx *mapping;
99 struct dentry *dfs_root;
100
101 /* tc action stats */
102 struct mlx5e_tc_act_stats_handle *action_stats_handle;
103 };
104
105 struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
106 [MAPPED_OBJ_TO_REG] = {
107 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
108 .moffset = 0,
109 .mlen = 16,
110 },
111 [VPORT_TO_REG] = {
112 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
113 .moffset = 16,
114 .mlen = 16,
115 },
116 [TUNNEL_TO_REG] = {
117 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
118 .moffset = 8,
119 .mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
120 .soffset = MLX5_BYTE_OFF(fte_match_param,
121 misc_parameters_2.metadata_reg_c_1),
122 },
123 [ZONE_TO_REG] = zone_to_reg_ct,
124 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
125 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
126 [MARK_TO_REG] = mark_to_reg_ct,
127 [LABELS_TO_REG] = labels_to_reg_ct,
128 [FTEID_TO_REG] = fteid_to_reg_ct,
129 /* For NIC rules we store the restore metadata directly
130 * into reg_b that is passed to SW since we don't
131 * jump between steering domains.
132 */
133 [NIC_MAPPED_OBJ_TO_REG] = {
134 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
135 .moffset = 0,
136 .mlen = 16,
137 },
138 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
139 [PACKET_COLOR_TO_REG] = packet_color_to_reg,
140 };
141
142 struct mlx5e_tc_jump_state {
143 u32 jump_count;
144 bool jump_target;
145 struct mlx5_flow_attr *jumping_attr;
146
147 enum flow_action_id last_id;
148 u32 last_index;
149 };
150
mlx5e_tc_table_alloc(void)151 struct mlx5e_tc_table *mlx5e_tc_table_alloc(void)
152 {
153 struct mlx5e_tc_table *tc;
154
155 tc = kvzalloc(sizeof(*tc), GFP_KERNEL);
156 return tc ? tc : ERR_PTR(-ENOMEM);
157 }
158
mlx5e_tc_table_free(struct mlx5e_tc_table * tc)159 void mlx5e_tc_table_free(struct mlx5e_tc_table *tc)
160 {
161 kvfree(tc);
162 }
163
mlx5e_nic_chains(struct mlx5e_tc_table * tc)164 struct mlx5_fs_chains *mlx5e_nic_chains(struct mlx5e_tc_table *tc)
165 {
166 return tc->chains;
167 }
168
169 /* To avoid false lock dependency warning set the tc_ht lock
170 * class different than the lock class of the ht being used when deleting
171 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
172 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
173 * it's different than the ht->mutex here.
174 */
175 static struct lock_class_key tc_ht_lock_key;
176 static struct lock_class_key tc_ht_wq_key;
177
178 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
179 static void free_flow_post_acts(struct mlx5e_tc_flow *flow);
180 static void mlx5_free_flow_attr_actions(struct mlx5e_tc_flow *flow,
181 struct mlx5_flow_attr *attr);
182
183 void
mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec * spec,enum mlx5e_tc_attr_to_reg type,u32 val,u32 mask)184 mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
185 enum mlx5e_tc_attr_to_reg type,
186 u32 val,
187 u32 mask)
188 {
189 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
190 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
191 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
192 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
193 u32 max_mask = GENMASK(match_len - 1, 0);
194 __be32 curr_mask_be, curr_val_be;
195 u32 curr_mask, curr_val;
196
197 fmask = headers_c + soffset;
198 fval = headers_v + soffset;
199
200 memcpy(&curr_mask_be, fmask, 4);
201 memcpy(&curr_val_be, fval, 4);
202
203 curr_mask = be32_to_cpu(curr_mask_be);
204 curr_val = be32_to_cpu(curr_val_be);
205
206 //move to correct offset
207 WARN_ON(mask > max_mask);
208 mask <<= moffset;
209 val <<= moffset;
210 max_mask <<= moffset;
211
212 //zero val and mask
213 curr_mask &= ~max_mask;
214 curr_val &= ~max_mask;
215
216 //add current to mask
217 curr_mask |= mask;
218 curr_val |= val;
219
220 //back to be32 and write
221 curr_mask_be = cpu_to_be32(curr_mask);
222 curr_val_be = cpu_to_be32(curr_val);
223
224 memcpy(fmask, &curr_mask_be, 4);
225 memcpy(fval, &curr_val_be, 4);
226
227 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
228 }
229
230 void
mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec * spec,enum mlx5e_tc_attr_to_reg type,u32 * val,u32 * mask)231 mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
232 enum mlx5e_tc_attr_to_reg type,
233 u32 *val,
234 u32 *mask)
235 {
236 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
237 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
238 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
239 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
240 u32 max_mask = GENMASK(match_len - 1, 0);
241 __be32 curr_mask_be, curr_val_be;
242 u32 curr_mask, curr_val;
243
244 fmask = headers_c + soffset;
245 fval = headers_v + soffset;
246
247 memcpy(&curr_mask_be, fmask, 4);
248 memcpy(&curr_val_be, fval, 4);
249
250 curr_mask = be32_to_cpu(curr_mask_be);
251 curr_val = be32_to_cpu(curr_val_be);
252
253 *mask = (curr_mask >> moffset) & max_mask;
254 *val = (curr_val >> moffset) & max_mask;
255 }
256
257 int
mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev * mdev,struct mlx5e_tc_mod_hdr_acts * mod_hdr_acts,enum mlx5_flow_namespace_type ns,enum mlx5e_tc_attr_to_reg type,u32 data)258 mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
259 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
260 enum mlx5_flow_namespace_type ns,
261 enum mlx5e_tc_attr_to_reg type,
262 u32 data)
263 {
264 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
265 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
266 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
267 char *modact;
268 int err;
269
270 modact = mlx5e_mod_hdr_alloc(mdev, ns, mod_hdr_acts);
271 if (IS_ERR(modact))
272 return PTR_ERR(modact);
273
274 /* Firmware has 5bit length field and 0 means 32bits */
275 if (mlen == 32)
276 mlen = 0;
277
278 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
279 MLX5_SET(set_action_in, modact, field, mfield);
280 MLX5_SET(set_action_in, modact, offset, moffset);
281 MLX5_SET(set_action_in, modact, length, mlen);
282 MLX5_SET(set_action_in, modact, data, data);
283 err = mod_hdr_acts->num_actions;
284 mod_hdr_acts->num_actions++;
285
286 return err;
287 }
288
289 static struct mlx5e_tc_act_stats_handle *
get_act_stats_handle(struct mlx5e_priv * priv)290 get_act_stats_handle(struct mlx5e_priv *priv)
291 {
292 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
293 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
294 struct mlx5_rep_uplink_priv *uplink_priv;
295 struct mlx5e_rep_priv *uplink_rpriv;
296
297 if (is_mdev_switchdev_mode(priv->mdev)) {
298 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
299 uplink_priv = &uplink_rpriv->uplink_priv;
300
301 return uplink_priv->action_stats_handle;
302 }
303
304 return tc->action_stats_handle;
305 }
306
307 struct mlx5e_tc_int_port_priv *
mlx5e_get_int_port_priv(struct mlx5e_priv * priv)308 mlx5e_get_int_port_priv(struct mlx5e_priv *priv)
309 {
310 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
311 struct mlx5_rep_uplink_priv *uplink_priv;
312 struct mlx5e_rep_priv *uplink_rpriv;
313
314 if (is_mdev_switchdev_mode(priv->mdev)) {
315 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
316 uplink_priv = &uplink_rpriv->uplink_priv;
317
318 return uplink_priv->int_port_priv;
319 }
320
321 return NULL;
322 }
323
324 struct mlx5e_flow_meters *
mlx5e_get_flow_meters(struct mlx5_core_dev * dev)325 mlx5e_get_flow_meters(struct mlx5_core_dev *dev)
326 {
327 struct mlx5_eswitch *esw = dev->priv.eswitch;
328 struct mlx5_rep_uplink_priv *uplink_priv;
329 struct mlx5e_rep_priv *uplink_rpriv;
330 struct mlx5e_priv *priv;
331
332 if (is_mdev_switchdev_mode(dev)) {
333 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
334 uplink_priv = &uplink_rpriv->uplink_priv;
335 priv = netdev_priv(uplink_rpriv->netdev);
336 if (!uplink_priv->flow_meters)
337 uplink_priv->flow_meters =
338 mlx5e_flow_meters_init(priv,
339 MLX5_FLOW_NAMESPACE_FDB,
340 uplink_priv->post_act);
341 if (!IS_ERR(uplink_priv->flow_meters))
342 return uplink_priv->flow_meters;
343 }
344
345 return NULL;
346 }
347
348 static struct mlx5_tc_ct_priv *
get_ct_priv(struct mlx5e_priv * priv)349 get_ct_priv(struct mlx5e_priv *priv)
350 {
351 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
352 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
353 struct mlx5_rep_uplink_priv *uplink_priv;
354 struct mlx5e_rep_priv *uplink_rpriv;
355
356 if (is_mdev_switchdev_mode(priv->mdev)) {
357 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
358 uplink_priv = &uplink_rpriv->uplink_priv;
359
360 return uplink_priv->ct_priv;
361 }
362
363 return tc->ct;
364 }
365
366 static struct mlx5e_tc_psample *
get_sample_priv(struct mlx5e_priv * priv)367 get_sample_priv(struct mlx5e_priv *priv)
368 {
369 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
370 struct mlx5_rep_uplink_priv *uplink_priv;
371 struct mlx5e_rep_priv *uplink_rpriv;
372
373 if (is_mdev_switchdev_mode(priv->mdev)) {
374 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
375 uplink_priv = &uplink_rpriv->uplink_priv;
376
377 return uplink_priv->tc_psample;
378 }
379
380 return NULL;
381 }
382
383 static struct mlx5e_post_act *
get_post_action(struct mlx5e_priv * priv)384 get_post_action(struct mlx5e_priv *priv)
385 {
386 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
387 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
388 struct mlx5_rep_uplink_priv *uplink_priv;
389 struct mlx5e_rep_priv *uplink_rpriv;
390
391 if (is_mdev_switchdev_mode(priv->mdev)) {
392 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
393 uplink_priv = &uplink_rpriv->uplink_priv;
394
395 return uplink_priv->post_act;
396 }
397
398 return tc->post_act;
399 }
400
401 struct mlx5_flow_handle *
mlx5_tc_rule_insert(struct mlx5e_priv * priv,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr)402 mlx5_tc_rule_insert(struct mlx5e_priv *priv,
403 struct mlx5_flow_spec *spec,
404 struct mlx5_flow_attr *attr)
405 {
406 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
407
408 if (is_mdev_switchdev_mode(priv->mdev))
409 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
410
411 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
412 }
413
414 void
mlx5_tc_rule_delete(struct mlx5e_priv * priv,struct mlx5_flow_handle * rule,struct mlx5_flow_attr * attr)415 mlx5_tc_rule_delete(struct mlx5e_priv *priv,
416 struct mlx5_flow_handle *rule,
417 struct mlx5_flow_attr *attr)
418 {
419 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
420
421 if (is_mdev_switchdev_mode(priv->mdev)) {
422 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
423 return;
424 }
425
426 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
427 }
428
429 static bool
is_flow_meter_action(struct mlx5_flow_attr * attr)430 is_flow_meter_action(struct mlx5_flow_attr *attr)
431 {
432 return (((attr->action & MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO) &&
433 (attr->exe_aso_type == MLX5_EXE_ASO_FLOW_METER)) ||
434 attr->flags & MLX5_ATTR_FLAG_MTU);
435 }
436
437 static int
mlx5e_tc_add_flow_meter(struct mlx5e_priv * priv,struct mlx5_flow_attr * attr)438 mlx5e_tc_add_flow_meter(struct mlx5e_priv *priv,
439 struct mlx5_flow_attr *attr)
440 {
441 struct mlx5e_post_act *post_act = get_post_action(priv);
442 struct mlx5e_post_meter_priv *post_meter;
443 enum mlx5_flow_namespace_type ns_type;
444 struct mlx5e_flow_meter_handle *meter;
445 enum mlx5e_post_meter_type type;
446
447 if (IS_ERR(post_act))
448 return PTR_ERR(post_act);
449
450 meter = mlx5e_tc_meter_replace(priv->mdev, &attr->meter_attr.params);
451 if (IS_ERR(meter)) {
452 mlx5_core_err(priv->mdev, "Failed to get flow meter\n");
453 return PTR_ERR(meter);
454 }
455
456 ns_type = mlx5e_tc_meter_get_namespace(meter->flow_meters);
457 type = meter->params.mtu ? MLX5E_POST_METER_MTU : MLX5E_POST_METER_RATE;
458 post_meter = mlx5e_post_meter_init(priv, ns_type, post_act,
459 type,
460 meter->act_counter, meter->drop_counter,
461 attr->branch_true, attr->branch_false);
462 if (IS_ERR(post_meter)) {
463 mlx5_core_err(priv->mdev, "Failed to init post meter\n");
464 goto err_meter_init;
465 }
466
467 attr->meter_attr.meter = meter;
468 attr->meter_attr.post_meter = post_meter;
469 attr->dest_ft = mlx5e_post_meter_get_ft(post_meter);
470 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
471
472 return 0;
473
474 err_meter_init:
475 mlx5e_tc_meter_put(meter);
476 return PTR_ERR(post_meter);
477 }
478
479 static void
mlx5e_tc_del_flow_meter(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)480 mlx5e_tc_del_flow_meter(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
481 {
482 mlx5e_post_meter_cleanup(esw, attr->meter_attr.post_meter);
483 mlx5e_tc_meter_put(attr->meter_attr.meter);
484 }
485
486 struct mlx5_flow_handle *
mlx5e_tc_rule_offload(struct mlx5e_priv * priv,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr)487 mlx5e_tc_rule_offload(struct mlx5e_priv *priv,
488 struct mlx5_flow_spec *spec,
489 struct mlx5_flow_attr *attr)
490 {
491 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
492 int err;
493
494 if (!is_mdev_switchdev_mode(priv->mdev))
495 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
496
497 if (attr->flags & MLX5_ATTR_FLAG_SAMPLE)
498 return mlx5e_tc_sample_offload(get_sample_priv(priv), spec, attr);
499
500 if (is_flow_meter_action(attr)) {
501 err = mlx5e_tc_add_flow_meter(priv, attr);
502 if (err)
503 return ERR_PTR(err);
504 }
505
506 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
507 }
508
509 void
mlx5e_tc_rule_unoffload(struct mlx5e_priv * priv,struct mlx5_flow_handle * rule,struct mlx5_flow_attr * attr)510 mlx5e_tc_rule_unoffload(struct mlx5e_priv *priv,
511 struct mlx5_flow_handle *rule,
512 struct mlx5_flow_attr *attr)
513 {
514 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
515
516 if (!is_mdev_switchdev_mode(priv->mdev)) {
517 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
518 return;
519 }
520
521 if (attr->flags & MLX5_ATTR_FLAG_SAMPLE) {
522 mlx5e_tc_sample_unoffload(get_sample_priv(priv), rule, attr);
523 return;
524 }
525
526 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
527
528 if (attr->meter_attr.meter)
529 mlx5e_tc_del_flow_meter(esw, attr);
530 }
531
532 int
mlx5e_tc_match_to_reg_set(struct mlx5_core_dev * mdev,struct mlx5e_tc_mod_hdr_acts * mod_hdr_acts,enum mlx5_flow_namespace_type ns,enum mlx5e_tc_attr_to_reg type,u32 data)533 mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
534 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
535 enum mlx5_flow_namespace_type ns,
536 enum mlx5e_tc_attr_to_reg type,
537 u32 data)
538 {
539 int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
540
541 return ret < 0 ? ret : 0;
542 }
543
mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev * mdev,struct mlx5e_tc_mod_hdr_acts * mod_hdr_acts,enum mlx5e_tc_attr_to_reg type,int act_id,u32 data)544 void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
545 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
546 enum mlx5e_tc_attr_to_reg type,
547 int act_id, u32 data)
548 {
549 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
550 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
551 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
552 char *modact;
553
554 modact = mlx5e_mod_hdr_get_item(mod_hdr_acts, act_id);
555
556 /* Firmware has 5bit length field and 0 means 32bits */
557 if (mlen == 32)
558 mlen = 0;
559
560 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
561 MLX5_SET(set_action_in, modact, field, mfield);
562 MLX5_SET(set_action_in, modact, offset, moffset);
563 MLX5_SET(set_action_in, modact, length, mlen);
564 MLX5_SET(set_action_in, modact, data, data);
565 }
566
567 struct mlx5e_hairpin {
568 struct mlx5_hairpin *pair;
569
570 struct mlx5_core_dev *func_mdev;
571 struct mlx5e_priv *func_priv;
572 u32 tdn;
573 struct mlx5e_tir direct_tir;
574
575 int num_channels;
576 u8 log_num_packets;
577 struct mlx5e_rqt indir_rqt;
578 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
579 struct mlx5_ttc_table *ttc;
580 };
581
582 struct mlx5e_hairpin_entry {
583 /* a node of a hash table which keeps all the hairpin entries */
584 struct hlist_node hairpin_hlist;
585
586 /* protects flows list */
587 spinlock_t flows_lock;
588 /* flows sharing the same hairpin */
589 struct list_head flows;
590 /* hpe's that were not fully initialized when dead peer update event
591 * function traversed them.
592 */
593 struct list_head dead_peer_wait_list;
594
595 u16 peer_vhca_id;
596 u8 prio;
597 struct mlx5e_hairpin *hp;
598 refcount_t refcnt;
599 struct completion res_ready;
600 };
601
602 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
603 struct mlx5e_tc_flow *flow);
604
mlx5e_flow_get(struct mlx5e_tc_flow * flow)605 struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
606 {
607 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
608 return ERR_PTR(-EINVAL);
609 return flow;
610 }
611
mlx5e_flow_put(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow)612 void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
613 {
614 if (refcount_dec_and_test(&flow->refcnt)) {
615 mlx5e_tc_del_flow(priv, flow);
616 kfree_rcu(flow, rcu_head);
617 }
618 }
619
mlx5e_is_eswitch_flow(struct mlx5e_tc_flow * flow)620 bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
621 {
622 return flow_flag_test(flow, ESWITCH);
623 }
624
mlx5e_is_ft_flow(struct mlx5e_tc_flow * flow)625 bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
626 {
627 return flow_flag_test(flow, FT);
628 }
629
mlx5e_is_offloaded_flow(struct mlx5e_tc_flow * flow)630 bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
631 {
632 return flow_flag_test(flow, OFFLOADED);
633 }
634
mlx5e_get_flow_namespace(struct mlx5e_tc_flow * flow)635 int mlx5e_get_flow_namespace(struct mlx5e_tc_flow *flow)
636 {
637 return mlx5e_is_eswitch_flow(flow) ?
638 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
639 }
640
641 static struct mlx5_core_dev *
get_flow_counter_dev(struct mlx5e_tc_flow * flow)642 get_flow_counter_dev(struct mlx5e_tc_flow *flow)
643 {
644 return mlx5e_is_eswitch_flow(flow) ? flow->attr->esw_attr->counter_dev : flow->priv->mdev;
645 }
646
647 static struct mod_hdr_tbl *
get_mod_hdr_table(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow)648 get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
649 {
650 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
651 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
652
653 return mlx5e_get_flow_namespace(flow) == MLX5_FLOW_NAMESPACE_FDB ?
654 &esw->offloads.mod_hdr :
655 &tc->mod_hdr;
656 }
657
mlx5e_tc_attach_mod_hdr(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr)658 int mlx5e_tc_attach_mod_hdr(struct mlx5e_priv *priv,
659 struct mlx5e_tc_flow *flow,
660 struct mlx5_flow_attr *attr)
661 {
662 struct mlx5e_mod_hdr_handle *mh;
663
664 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
665 mlx5e_get_flow_namespace(flow),
666 &attr->parse_attr->mod_hdr_acts);
667 if (IS_ERR(mh))
668 return PTR_ERR(mh);
669
670 WARN_ON(attr->modify_hdr);
671 attr->modify_hdr = mlx5e_mod_hdr_get(mh);
672 attr->mh = mh;
673
674 return 0;
675 }
676
mlx5e_tc_detach_mod_hdr(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr)677 void mlx5e_tc_detach_mod_hdr(struct mlx5e_priv *priv,
678 struct mlx5e_tc_flow *flow,
679 struct mlx5_flow_attr *attr)
680 {
681 /* flow wasn't fully initialized */
682 if (!attr->mh)
683 return;
684
685 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
686 attr->mh);
687 attr->mh = NULL;
688 }
689
690 static
mlx5e_hairpin_get_mdev(struct net * net,int ifindex)691 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
692 {
693 struct mlx5_core_dev *mdev;
694 struct net_device *netdev;
695 struct mlx5e_priv *priv;
696
697 netdev = dev_get_by_index(net, ifindex);
698 if (!netdev)
699 return ERR_PTR(-ENODEV);
700
701 priv = netdev_priv(netdev);
702 mdev = priv->mdev;
703 dev_put(netdev);
704
705 /* Mirred tc action holds a refcount on the ifindex net_device (see
706 * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
707 * after dev_put(netdev), while we're in the context of adding a tc flow.
708 *
709 * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
710 * stored in a hairpin object, which exists until all flows, that refer to it, get
711 * removed.
712 *
713 * On the other hand, after a hairpin object has been created, the peer net_device may
714 * be removed/unbound while there are still some hairpin flows that are using it. This
715 * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
716 * NETDEV_UNREGISTER event of the peer net_device.
717 */
718 return mdev;
719 }
720
mlx5e_hairpin_create_transport(struct mlx5e_hairpin * hp)721 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
722 {
723 struct mlx5e_tir_builder *builder;
724 int err;
725
726 builder = mlx5e_tir_builder_alloc(false);
727 if (!builder)
728 return -ENOMEM;
729
730 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
731 if (err)
732 goto out;
733
734 mlx5e_tir_builder_build_inline(builder, hp->tdn, hp->pair->rqn[0]);
735 err = mlx5e_tir_init(&hp->direct_tir, builder, hp->func_mdev, false);
736 if (err)
737 goto create_tir_err;
738
739 out:
740 mlx5e_tir_builder_free(builder);
741 return err;
742
743 create_tir_err:
744 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
745
746 goto out;
747 }
748
mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin * hp)749 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
750 {
751 mlx5e_tir_destroy(&hp->direct_tir);
752 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
753 }
754
mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin * hp)755 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
756 {
757 struct mlx5e_priv *priv = hp->func_priv;
758 struct mlx5_core_dev *mdev = priv->mdev;
759 struct mlx5e_rss_params_indir indir;
760 int err;
761
762 err = mlx5e_rss_params_indir_init(&indir, mdev,
763 mlx5e_rqt_size(mdev, hp->num_channels),
764 mlx5e_rqt_size(mdev, hp->num_channels));
765 if (err)
766 return err;
767
768 mlx5e_rss_params_indir_init_uniform(&indir, hp->num_channels);
769 err = mlx5e_rqt_init_indir(&hp->indir_rqt, mdev, hp->pair->rqn, NULL, hp->num_channels,
770 mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc,
771 &indir);
772
773 mlx5e_rss_params_indir_cleanup(&indir);
774 return err;
775 }
776
mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin * hp)777 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
778 {
779 struct mlx5e_priv *priv = hp->func_priv;
780 struct mlx5e_rss_params_hash rss_hash;
781 enum mlx5_traffic_types tt, max_tt;
782 struct mlx5e_tir_builder *builder;
783 int err = 0;
784
785 builder = mlx5e_tir_builder_alloc(false);
786 if (!builder)
787 return -ENOMEM;
788
789 rss_hash = mlx5e_rx_res_get_current_hash(priv->rx_res);
790
791 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
792 struct mlx5e_rss_params_traffic_type rss_tt;
793
794 rss_tt = mlx5e_rss_get_default_tt_config(tt);
795
796 mlx5e_tir_builder_build_rqt(builder, hp->tdn,
797 mlx5e_rqt_get_rqtn(&hp->indir_rqt),
798 false);
799 mlx5e_tir_builder_build_rss(builder, &rss_hash, &rss_tt, false);
800
801 err = mlx5e_tir_init(&hp->indir_tir[tt], builder, hp->func_mdev, false);
802 if (err) {
803 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
804 goto err_destroy_tirs;
805 }
806
807 mlx5e_tir_builder_clear(builder);
808 }
809
810 out:
811 mlx5e_tir_builder_free(builder);
812 return err;
813
814 err_destroy_tirs:
815 max_tt = tt;
816 for (tt = 0; tt < max_tt; tt++)
817 mlx5e_tir_destroy(&hp->indir_tir[tt]);
818
819 goto out;
820 }
821
mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin * hp)822 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
823 {
824 int tt;
825
826 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
827 mlx5e_tir_destroy(&hp->indir_tir[tt]);
828 }
829
mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin * hp,struct ttc_params * ttc_params)830 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
831 struct ttc_params *ttc_params)
832 {
833 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
834 int tt;
835
836 memset(ttc_params, 0, sizeof(*ttc_params));
837
838 ttc_params->ns_type = MLX5_FLOW_NAMESPACE_KERNEL;
839 for (tt = 0; tt < MLX5_NUM_TT; tt++) {
840 ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
841 ttc_params->dests[tt].tir_num =
842 tt == MLX5_TT_ANY ?
843 mlx5e_tir_get_tirn(&hp->direct_tir) :
844 mlx5e_tir_get_tirn(&hp->indir_tir[tt]);
845 }
846
847 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
848 ft_attr->prio = MLX5E_TC_PRIO;
849 }
850
mlx5e_hairpin_rss_init(struct mlx5e_hairpin * hp)851 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
852 {
853 struct mlx5e_priv *priv = hp->func_priv;
854 struct ttc_params ttc_params;
855 struct mlx5_ttc_table *ttc;
856 int err;
857
858 err = mlx5e_hairpin_create_indirect_rqt(hp);
859 if (err)
860 return err;
861
862 err = mlx5e_hairpin_create_indirect_tirs(hp);
863 if (err)
864 goto err_create_indirect_tirs;
865
866 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
867 hp->ttc = mlx5_create_ttc_table(priv->mdev, &ttc_params);
868 if (IS_ERR(hp->ttc)) {
869 err = PTR_ERR(hp->ttc);
870 goto err_create_ttc_table;
871 }
872
873 ttc = mlx5e_fs_get_ttc(priv->fs, false);
874 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
875 hp->num_channels,
876 mlx5_get_ttc_flow_table(ttc)->id);
877
878 return 0;
879
880 err_create_ttc_table:
881 mlx5e_hairpin_destroy_indirect_tirs(hp);
882 err_create_indirect_tirs:
883 mlx5e_rqt_destroy(&hp->indir_rqt);
884
885 return err;
886 }
887
mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin * hp)888 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
889 {
890 mlx5_destroy_ttc_table(hp->ttc);
891 mlx5e_hairpin_destroy_indirect_tirs(hp);
892 mlx5e_rqt_destroy(&hp->indir_rqt);
893 }
894
895 static struct mlx5e_hairpin *
mlx5e_hairpin_create(struct mlx5e_priv * priv,struct mlx5_hairpin_params * params,int peer_ifindex)896 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
897 int peer_ifindex)
898 {
899 struct mlx5_core_dev *func_mdev, *peer_mdev;
900 struct mlx5e_hairpin *hp;
901 struct mlx5_hairpin *pair;
902 int err;
903
904 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
905 if (!hp)
906 return ERR_PTR(-ENOMEM);
907
908 func_mdev = priv->mdev;
909 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
910 if (IS_ERR(peer_mdev)) {
911 err = PTR_ERR(peer_mdev);
912 goto create_pair_err;
913 }
914
915 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
916 if (IS_ERR(pair)) {
917 err = PTR_ERR(pair);
918 goto create_pair_err;
919 }
920 hp->pair = pair;
921 hp->func_mdev = func_mdev;
922 hp->func_priv = priv;
923 hp->num_channels = params->num_channels;
924 hp->log_num_packets = params->log_num_packets;
925
926 err = mlx5e_hairpin_create_transport(hp);
927 if (err)
928 goto create_transport_err;
929
930 if (hp->num_channels > 1) {
931 err = mlx5e_hairpin_rss_init(hp);
932 if (err)
933 goto rss_init_err;
934 }
935
936 return hp;
937
938 rss_init_err:
939 mlx5e_hairpin_destroy_transport(hp);
940 create_transport_err:
941 mlx5_core_hairpin_destroy(hp->pair);
942 create_pair_err:
943 kfree(hp);
944 return ERR_PTR(err);
945 }
946
mlx5e_hairpin_destroy(struct mlx5e_hairpin * hp)947 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
948 {
949 if (hp->num_channels > 1)
950 mlx5e_hairpin_rss_cleanup(hp);
951 mlx5e_hairpin_destroy_transport(hp);
952 mlx5_core_hairpin_destroy(hp->pair);
953 kvfree(hp);
954 }
955
hash_hairpin_info(u16 peer_vhca_id,u8 prio)956 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
957 {
958 return (peer_vhca_id << 16 | prio);
959 }
960
mlx5e_hairpin_get(struct mlx5e_priv * priv,u16 peer_vhca_id,u8 prio)961 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
962 u16 peer_vhca_id, u8 prio)
963 {
964 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
965 struct mlx5e_hairpin_entry *hpe;
966 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
967
968 hash_for_each_possible(tc->hairpin_tbl, hpe,
969 hairpin_hlist, hash_key) {
970 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
971 refcount_inc(&hpe->refcnt);
972 return hpe;
973 }
974 }
975
976 return NULL;
977 }
978
mlx5e_hairpin_put(struct mlx5e_priv * priv,struct mlx5e_hairpin_entry * hpe)979 static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
980 struct mlx5e_hairpin_entry *hpe)
981 {
982 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
983 /* no more hairpin flows for us, release the hairpin pair */
984 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &tc->hairpin_tbl_lock))
985 return;
986 hash_del(&hpe->hairpin_hlist);
987 mutex_unlock(&tc->hairpin_tbl_lock);
988
989 if (!IS_ERR_OR_NULL(hpe->hp)) {
990 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
991 dev_name(hpe->hp->pair->peer_mdev->device));
992
993 mlx5e_hairpin_destroy(hpe->hp);
994 }
995
996 WARN_ON(!list_empty(&hpe->flows));
997 kfree(hpe);
998 }
999
1000 #define UNKNOWN_MATCH_PRIO 8
1001
mlx5e_hairpin_get_prio(struct mlx5e_priv * priv,struct mlx5_flow_spec * spec,u8 * match_prio,struct netlink_ext_ack * extack)1002 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
1003 struct mlx5_flow_spec *spec, u8 *match_prio,
1004 struct netlink_ext_ack *extack)
1005 {
1006 void *headers_c, *headers_v;
1007 u8 prio_val, prio_mask = 0;
1008 bool vlan_present;
1009
1010 #ifdef CONFIG_MLX5_CORE_EN_DCB
1011 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
1012 NL_SET_ERR_MSG_MOD(extack,
1013 "only PCP trust state supported for hairpin");
1014 return -EOPNOTSUPP;
1015 }
1016 #endif
1017 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
1018 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1019
1020 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
1021 if (vlan_present) {
1022 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
1023 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
1024 }
1025
1026 if (!vlan_present || !prio_mask) {
1027 prio_val = UNKNOWN_MATCH_PRIO;
1028 } else if (prio_mask != 0x7) {
1029 NL_SET_ERR_MSG_MOD(extack,
1030 "masked priority match not supported for hairpin");
1031 return -EOPNOTSUPP;
1032 }
1033
1034 *match_prio = prio_val;
1035 return 0;
1036 }
1037
debugfs_hairpin_num_active_get(void * data,u64 * val)1038 static int debugfs_hairpin_num_active_get(void *data, u64 *val)
1039 {
1040 struct mlx5e_tc_table *tc = data;
1041 struct mlx5e_hairpin_entry *hpe;
1042 u32 cnt = 0;
1043 u32 bkt;
1044
1045 mutex_lock(&tc->hairpin_tbl_lock);
1046 hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
1047 cnt++;
1048 mutex_unlock(&tc->hairpin_tbl_lock);
1049
1050 *val = cnt;
1051
1052 return 0;
1053 }
1054 DEFINE_DEBUGFS_ATTRIBUTE(fops_hairpin_num_active,
1055 debugfs_hairpin_num_active_get, NULL, "%llu\n");
1056
debugfs_hairpin_table_dump_show(struct seq_file * file,void * priv)1057 static int debugfs_hairpin_table_dump_show(struct seq_file *file, void *priv)
1058
1059 {
1060 struct mlx5e_tc_table *tc = file->private;
1061 struct mlx5e_hairpin_entry *hpe;
1062 u32 bkt;
1063
1064 mutex_lock(&tc->hairpin_tbl_lock);
1065 hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
1066 seq_printf(file,
1067 "Hairpin peer_vhca_id %u prio %u refcnt %u num_channels %u num_packets %lu\n",
1068 hpe->peer_vhca_id, hpe->prio,
1069 refcount_read(&hpe->refcnt), hpe->hp->num_channels,
1070 BIT(hpe->hp->log_num_packets));
1071 mutex_unlock(&tc->hairpin_tbl_lock);
1072
1073 return 0;
1074 }
1075 DEFINE_SHOW_ATTRIBUTE(debugfs_hairpin_table_dump);
1076
mlx5e_tc_debugfs_init(struct mlx5e_tc_table * tc,struct dentry * dfs_root)1077 static void mlx5e_tc_debugfs_init(struct mlx5e_tc_table *tc,
1078 struct dentry *dfs_root)
1079 {
1080 if (IS_ERR_OR_NULL(dfs_root))
1081 return;
1082
1083 tc->dfs_root = debugfs_create_dir("tc", dfs_root);
1084
1085 debugfs_create_file("hairpin_num_active", 0444, tc->dfs_root, tc,
1086 &fops_hairpin_num_active);
1087 debugfs_create_file("hairpin_table_dump", 0444, tc->dfs_root, tc,
1088 &debugfs_hairpin_table_dump_fops);
1089 }
1090
mlx5e_hairpin_flow_add(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct mlx5e_tc_flow_parse_attr * parse_attr,struct netlink_ext_ack * extack)1091 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
1092 struct mlx5e_tc_flow *flow,
1093 struct mlx5e_tc_flow_parse_attr *parse_attr,
1094 struct netlink_ext_ack *extack)
1095 {
1096 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1097 struct devlink *devlink = priv_to_devlink(priv->mdev);
1098 int peer_ifindex = parse_attr->mirred_ifindex[0];
1099 union devlink_param_value val = {};
1100 struct mlx5_hairpin_params params;
1101 struct mlx5_core_dev *peer_mdev;
1102 struct mlx5e_hairpin_entry *hpe;
1103 struct mlx5e_hairpin *hp;
1104 u8 match_prio;
1105 u16 peer_id;
1106 int err;
1107
1108 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
1109 if (IS_ERR(peer_mdev)) {
1110 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
1111 return PTR_ERR(peer_mdev);
1112 }
1113
1114 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
1115 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
1116 return -EOPNOTSUPP;
1117 }
1118
1119 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
1120 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
1121 extack);
1122 if (err)
1123 return err;
1124
1125 mutex_lock(&tc->hairpin_tbl_lock);
1126 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
1127 if (hpe) {
1128 mutex_unlock(&tc->hairpin_tbl_lock);
1129 wait_for_completion(&hpe->res_ready);
1130
1131 if (IS_ERR(hpe->hp)) {
1132 err = -EREMOTEIO;
1133 goto out_err;
1134 }
1135 goto attach_flow;
1136 }
1137
1138 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
1139 if (!hpe) {
1140 mutex_unlock(&tc->hairpin_tbl_lock);
1141 return -ENOMEM;
1142 }
1143
1144 spin_lock_init(&hpe->flows_lock);
1145 INIT_LIST_HEAD(&hpe->flows);
1146 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
1147 hpe->peer_vhca_id = peer_id;
1148 hpe->prio = match_prio;
1149 refcount_set(&hpe->refcnt, 1);
1150 init_completion(&hpe->res_ready);
1151
1152 hash_add(tc->hairpin_tbl, &hpe->hairpin_hlist,
1153 hash_hairpin_info(peer_id, match_prio));
1154 mutex_unlock(&tc->hairpin_tbl_lock);
1155
1156 err = devl_param_driverinit_value_get(
1157 devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_QUEUE_SIZE, &val);
1158 if (err) {
1159 err = -ENOMEM;
1160 goto out_err;
1161 }
1162
1163 params.log_num_packets = ilog2(val.vu32);
1164 params.log_data_size =
1165 clamp_t(u32,
1166 params.log_num_packets +
1167 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev),
1168 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz),
1169 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
1170
1171 params.q_counter = priv->q_counter[0];
1172 err = devl_param_driverinit_value_get(
1173 devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_NUM_QUEUES, &val);
1174 if (err) {
1175 err = -ENOMEM;
1176 goto out_err;
1177 }
1178
1179 params.num_channels = val.vu32;
1180
1181 hp = mlx5e_hairpin_create(priv, ¶ms, peer_ifindex);
1182 hpe->hp = hp;
1183 complete_all(&hpe->res_ready);
1184 if (IS_ERR(hp)) {
1185 err = PTR_ERR(hp);
1186 goto out_err;
1187 }
1188
1189 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
1190 mlx5e_tir_get_tirn(&hp->direct_tir), hp->pair->rqn[0],
1191 dev_name(hp->pair->peer_mdev->device),
1192 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
1193
1194 attach_flow:
1195 if (hpe->hp->num_channels > 1) {
1196 flow_flag_set(flow, HAIRPIN_RSS);
1197 flow->attr->nic_attr->hairpin_ft =
1198 mlx5_get_ttc_flow_table(hpe->hp->ttc);
1199 } else {
1200 flow->attr->nic_attr->hairpin_tirn = mlx5e_tir_get_tirn(&hpe->hp->direct_tir);
1201 }
1202
1203 flow->hpe = hpe;
1204 spin_lock(&hpe->flows_lock);
1205 list_add(&flow->hairpin, &hpe->flows);
1206 spin_unlock(&hpe->flows_lock);
1207
1208 return 0;
1209
1210 out_err:
1211 mlx5e_hairpin_put(priv, hpe);
1212 return err;
1213 }
1214
mlx5e_hairpin_flow_del(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow)1215 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
1216 struct mlx5e_tc_flow *flow)
1217 {
1218 /* flow wasn't fully initialized */
1219 if (!flow->hpe)
1220 return;
1221
1222 spin_lock(&flow->hpe->flows_lock);
1223 list_del(&flow->hairpin);
1224 spin_unlock(&flow->hpe->flows_lock);
1225
1226 mlx5e_hairpin_put(priv, flow->hpe);
1227 flow->hpe = NULL;
1228 }
1229
1230 struct mlx5_flow_handle *
mlx5e_add_offloaded_nic_rule(struct mlx5e_priv * priv,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr)1231 mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
1232 struct mlx5_flow_spec *spec,
1233 struct mlx5_flow_attr *attr)
1234 {
1235 struct mlx5_flow_context *flow_context = &spec->flow_context;
1236 struct mlx5e_vlan_table *vlan = mlx5e_fs_get_vlan(priv->fs);
1237 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1238 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
1239 struct mlx5_flow_destination dest[2] = {};
1240 struct mlx5_fs_chains *nic_chains;
1241 struct mlx5_flow_act flow_act = {
1242 .action = attr->action,
1243 .flags = FLOW_ACT_NO_APPEND,
1244 };
1245 struct mlx5_flow_handle *rule;
1246 struct mlx5_flow_table *ft;
1247 int dest_ix = 0;
1248
1249 nic_chains = mlx5e_nic_chains(tc);
1250 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1251 flow_context->flow_tag = nic_attr->flow_tag;
1252
1253 if (attr->dest_ft) {
1254 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1255 dest[dest_ix].ft = attr->dest_ft;
1256 dest_ix++;
1257 } else if (nic_attr->hairpin_ft) {
1258 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1259 dest[dest_ix].ft = nic_attr->hairpin_ft;
1260 dest_ix++;
1261 } else if (nic_attr->hairpin_tirn) {
1262 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1263 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
1264 dest_ix++;
1265 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1266 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1267 if (attr->dest_chain) {
1268 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
1269 attr->dest_chain, 1,
1270 MLX5E_TC_FT_LEVEL);
1271 if (IS_ERR(dest[dest_ix].ft))
1272 return ERR_CAST(dest[dest_ix].ft);
1273 } else {
1274 dest[dest_ix].ft = mlx5e_vlan_get_flowtable(vlan);
1275 }
1276 dest_ix++;
1277 }
1278
1279 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
1280 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
1281 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
1282
1283 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1284 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
1285 dest[dest_ix].counter = attr->counter;
1286 dest_ix++;
1287 }
1288
1289 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1290 flow_act.modify_hdr = attr->modify_hdr;
1291
1292 mutex_lock(&tc->t_lock);
1293 if (IS_ERR_OR_NULL(tc->t)) {
1294 /* Create the root table here if doesn't exist yet */
1295 tc->t =
1296 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
1297
1298 if (IS_ERR(tc->t)) {
1299 mutex_unlock(&tc->t_lock);
1300 netdev_err(priv->netdev,
1301 "Failed to create tc offload table\n");
1302 rule = ERR_CAST(tc->t);
1303 goto err_ft_get;
1304 }
1305 }
1306 mutex_unlock(&tc->t_lock);
1307
1308 if (attr->chain || attr->prio)
1309 ft = mlx5_chains_get_table(nic_chains,
1310 attr->chain, attr->prio,
1311 MLX5E_TC_FT_LEVEL);
1312 else
1313 ft = attr->ft;
1314
1315 if (IS_ERR(ft)) {
1316 rule = ERR_CAST(ft);
1317 goto err_ft_get;
1318 }
1319
1320 if (attr->outer_match_level != MLX5_MATCH_NONE)
1321 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
1322
1323 rule = mlx5_add_flow_rules(ft, spec,
1324 &flow_act, dest, dest_ix);
1325 if (IS_ERR(rule))
1326 goto err_rule;
1327
1328 return rule;
1329
1330 err_rule:
1331 if (attr->chain || attr->prio)
1332 mlx5_chains_put_table(nic_chains,
1333 attr->chain, attr->prio,
1334 MLX5E_TC_FT_LEVEL);
1335 err_ft_get:
1336 if (attr->dest_chain)
1337 mlx5_chains_put_table(nic_chains,
1338 attr->dest_chain, 1,
1339 MLX5E_TC_FT_LEVEL);
1340
1341 return ERR_CAST(rule);
1342 }
1343
1344 static int
alloc_flow_attr_counter(struct mlx5_core_dev * counter_dev,struct mlx5_flow_attr * attr)1345 alloc_flow_attr_counter(struct mlx5_core_dev *counter_dev,
1346 struct mlx5_flow_attr *attr)
1347
1348 {
1349 struct mlx5_fc *counter;
1350
1351 counter = mlx5_fc_create(counter_dev, true);
1352 if (IS_ERR(counter))
1353 return PTR_ERR(counter);
1354
1355 attr->counter = counter;
1356 return 0;
1357 }
1358
1359 static int
mlx5e_tc_add_nic_flow(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct netlink_ext_ack * extack)1360 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
1361 struct mlx5e_tc_flow *flow,
1362 struct netlink_ext_ack *extack)
1363 {
1364 struct mlx5e_tc_flow_parse_attr *parse_attr;
1365 struct mlx5_flow_attr *attr = flow->attr;
1366 struct mlx5_core_dev *dev = priv->mdev;
1367 int err;
1368
1369 parse_attr = attr->parse_attr;
1370
1371 if (flow_flag_test(flow, HAIRPIN)) {
1372 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1373 if (err)
1374 return err;
1375 }
1376
1377 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1378 err = alloc_flow_attr_counter(dev, attr);
1379 if (err)
1380 return err;
1381 }
1382
1383 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1384 err = mlx5e_tc_attach_mod_hdr(priv, flow, attr);
1385 if (err)
1386 return err;
1387 }
1388
1389 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec, attr);
1390 return PTR_ERR_OR_ZERO(flow->rule[0]);
1391 }
1392
mlx5e_del_offloaded_nic_rule(struct mlx5e_priv * priv,struct mlx5_flow_handle * rule,struct mlx5_flow_attr * attr)1393 void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
1394 struct mlx5_flow_handle *rule,
1395 struct mlx5_flow_attr *attr)
1396 {
1397 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1398 struct mlx5_fs_chains *nic_chains;
1399
1400 nic_chains = mlx5e_nic_chains(tc);
1401 mlx5_del_flow_rules(rule);
1402
1403 if (attr->chain || attr->prio)
1404 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1405 MLX5E_TC_FT_LEVEL);
1406
1407 if (attr->dest_chain)
1408 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1409 MLX5E_TC_FT_LEVEL);
1410 }
1411
mlx5e_tc_del_nic_flow(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow)1412 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1413 struct mlx5e_tc_flow *flow)
1414 {
1415 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1416 struct mlx5_flow_attr *attr = flow->attr;
1417
1418 flow_flag_clear(flow, OFFLOADED);
1419
1420 if (!IS_ERR_OR_NULL(flow->rule[0]))
1421 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1422
1423 /* Remove root table if no rules are left to avoid
1424 * extra steering hops.
1425 */
1426 mutex_lock(&tc->t_lock);
1427 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1428 !IS_ERR_OR_NULL(tc->t)) {
1429 mlx5_chains_put_table(mlx5e_nic_chains(tc), 0, 1, MLX5E_TC_FT_LEVEL);
1430 tc->t = NULL;
1431 }
1432 mutex_unlock(&tc->t_lock);
1433
1434 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1435 mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
1436 mlx5e_tc_detach_mod_hdr(priv, flow, attr);
1437 }
1438
1439 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1440 mlx5_fc_destroy(priv->mdev, attr->counter);
1441
1442 if (flow_flag_test(flow, HAIRPIN))
1443 mlx5e_hairpin_flow_del(priv, flow);
1444
1445 free_flow_post_acts(flow);
1446 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), attr);
1447
1448 kvfree(attr->parse_attr);
1449 kfree(flow->attr);
1450 }
1451
1452 struct mlx5_flow_handle *
mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch * esw,struct mlx5e_tc_flow * flow,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr)1453 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1454 struct mlx5e_tc_flow *flow,
1455 struct mlx5_flow_spec *spec,
1456 struct mlx5_flow_attr *attr)
1457 {
1458 struct mlx5_flow_handle *rule;
1459
1460 if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH)
1461 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1462
1463 rule = mlx5e_tc_rule_offload(flow->priv, spec, attr);
1464
1465 if (IS_ERR(rule))
1466 return rule;
1467
1468 if (attr->esw_attr->split_count) {
1469 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1470 if (IS_ERR(flow->rule[1]))
1471 goto err_rule1;
1472 }
1473
1474 return rule;
1475
1476 err_rule1:
1477 mlx5e_tc_rule_unoffload(flow->priv, rule, attr);
1478 return flow->rule[1];
1479 }
1480
mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch * esw,struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr)1481 void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1482 struct mlx5e_tc_flow *flow,
1483 struct mlx5_flow_attr *attr)
1484 {
1485 flow_flag_clear(flow, OFFLOADED);
1486
1487 if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH)
1488 return mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1489
1490 if (attr->esw_attr->split_count)
1491 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1492
1493 mlx5e_tc_rule_unoffload(flow->priv, flow->rule[0], attr);
1494 }
1495
1496 struct mlx5_flow_handle *
mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch * esw,struct mlx5e_tc_flow * flow,struct mlx5_flow_spec * spec)1497 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1498 struct mlx5e_tc_flow *flow,
1499 struct mlx5_flow_spec *spec)
1500 {
1501 struct mlx5e_tc_mod_hdr_acts mod_acts = {};
1502 struct mlx5e_mod_hdr_handle *mh = NULL;
1503 struct mlx5_flow_attr *slow_attr;
1504 struct mlx5_flow_handle *rule;
1505 bool fwd_and_modify_cap;
1506 u32 chain_mapping = 0;
1507 int err;
1508
1509 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1510 if (!slow_attr)
1511 return ERR_PTR(-ENOMEM);
1512
1513 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1514 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1515 slow_attr->esw_attr->split_count = 0;
1516 slow_attr->flags |= MLX5_ATTR_FLAG_SLOW_PATH;
1517
1518 fwd_and_modify_cap = MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table);
1519 if (!fwd_and_modify_cap)
1520 goto skip_restore;
1521
1522 err = mlx5_chains_get_chain_mapping(esw_chains(esw), flow->attr->chain, &chain_mapping);
1523 if (err)
1524 goto err_get_chain;
1525
1526 err = mlx5e_tc_match_to_reg_set(esw->dev, &mod_acts, MLX5_FLOW_NAMESPACE_FDB,
1527 MAPPED_OBJ_TO_REG, chain_mapping);
1528 if (err)
1529 goto err_reg_set;
1530
1531 mh = mlx5e_mod_hdr_attach(esw->dev, get_mod_hdr_table(flow->priv, flow),
1532 MLX5_FLOW_NAMESPACE_FDB, &mod_acts);
1533 if (IS_ERR(mh)) {
1534 err = PTR_ERR(mh);
1535 goto err_attach;
1536 }
1537
1538 slow_attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1539 slow_attr->modify_hdr = mlx5e_mod_hdr_get(mh);
1540
1541 skip_restore:
1542 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
1543 if (IS_ERR(rule)) {
1544 err = PTR_ERR(rule);
1545 goto err_offload;
1546 }
1547
1548 flow->attr->slow_mh = mh;
1549 flow->chain_mapping = chain_mapping;
1550 flow_flag_set(flow, SLOW);
1551
1552 mlx5e_mod_hdr_dealloc(&mod_acts);
1553 kfree(slow_attr);
1554
1555 return rule;
1556
1557 err_offload:
1558 if (fwd_and_modify_cap)
1559 mlx5e_mod_hdr_detach(esw->dev, get_mod_hdr_table(flow->priv, flow), mh);
1560 err_attach:
1561 err_reg_set:
1562 if (fwd_and_modify_cap)
1563 mlx5_chains_put_chain_mapping(esw_chains(esw), chain_mapping);
1564 err_get_chain:
1565 mlx5e_mod_hdr_dealloc(&mod_acts);
1566 kfree(slow_attr);
1567 return ERR_PTR(err);
1568 }
1569
mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch * esw,struct mlx5e_tc_flow * flow)1570 void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1571 struct mlx5e_tc_flow *flow)
1572 {
1573 struct mlx5e_mod_hdr_handle *slow_mh = flow->attr->slow_mh;
1574 struct mlx5_flow_attr *slow_attr;
1575
1576 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1577 if (!slow_attr) {
1578 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1579 return;
1580 }
1581
1582 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1583 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1584 slow_attr->esw_attr->split_count = 0;
1585 slow_attr->flags |= MLX5_ATTR_FLAG_SLOW_PATH;
1586 if (slow_mh) {
1587 slow_attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1588 slow_attr->modify_hdr = mlx5e_mod_hdr_get(slow_mh);
1589 }
1590 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
1591 if (slow_mh) {
1592 mlx5e_mod_hdr_detach(esw->dev, get_mod_hdr_table(flow->priv, flow), slow_mh);
1593 mlx5_chains_put_chain_mapping(esw_chains(esw), flow->chain_mapping);
1594 flow->chain_mapping = 0;
1595 flow->attr->slow_mh = NULL;
1596 }
1597 flow_flag_clear(flow, SLOW);
1598 kfree(slow_attr);
1599 }
1600
1601 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1602 * function.
1603 */
unready_flow_add(struct mlx5e_tc_flow * flow,struct list_head * unready_flows)1604 static void unready_flow_add(struct mlx5e_tc_flow *flow,
1605 struct list_head *unready_flows)
1606 {
1607 flow_flag_set(flow, NOT_READY);
1608 list_add_tail(&flow->unready, unready_flows);
1609 }
1610
1611 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1612 * function.
1613 */
unready_flow_del(struct mlx5e_tc_flow * flow)1614 static void unready_flow_del(struct mlx5e_tc_flow *flow)
1615 {
1616 list_del(&flow->unready);
1617 flow_flag_clear(flow, NOT_READY);
1618 }
1619
add_unready_flow(struct mlx5e_tc_flow * flow)1620 static void add_unready_flow(struct mlx5e_tc_flow *flow)
1621 {
1622 struct mlx5_rep_uplink_priv *uplink_priv;
1623 struct mlx5e_rep_priv *rpriv;
1624 struct mlx5_eswitch *esw;
1625
1626 esw = flow->priv->mdev->priv.eswitch;
1627 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1628 uplink_priv = &rpriv->uplink_priv;
1629
1630 mutex_lock(&uplink_priv->unready_flows_lock);
1631 unready_flow_add(flow, &uplink_priv->unready_flows);
1632 mutex_unlock(&uplink_priv->unready_flows_lock);
1633 }
1634
remove_unready_flow(struct mlx5e_tc_flow * flow)1635 static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1636 {
1637 struct mlx5_rep_uplink_priv *uplink_priv;
1638 struct mlx5e_rep_priv *rpriv;
1639 struct mlx5_eswitch *esw;
1640
1641 esw = flow->priv->mdev->priv.eswitch;
1642 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1643 uplink_priv = &rpriv->uplink_priv;
1644
1645 mutex_lock(&uplink_priv->unready_flows_lock);
1646 if (flow_flag_test(flow, NOT_READY))
1647 unready_flow_del(flow);
1648 mutex_unlock(&uplink_priv->unready_flows_lock);
1649 }
1650
mlx5e_tc_is_vf_tunnel(struct net_device * out_dev,struct net_device * route_dev)1651 bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
1652 {
1653 struct mlx5_core_dev *out_mdev, *route_mdev;
1654 struct mlx5e_priv *out_priv, *route_priv;
1655
1656 out_priv = netdev_priv(out_dev);
1657 out_mdev = out_priv->mdev;
1658 route_priv = netdev_priv(route_dev);
1659 route_mdev = route_priv->mdev;
1660
1661 if (out_mdev->coredev_type != MLX5_COREDEV_PF)
1662 return false;
1663
1664 if (route_mdev->coredev_type != MLX5_COREDEV_VF &&
1665 route_mdev->coredev_type != MLX5_COREDEV_SF)
1666 return false;
1667
1668 return mlx5e_same_hw_devs(out_priv, route_priv);
1669 }
1670
mlx5e_tc_query_route_vport(struct net_device * out_dev,struct net_device * route_dev,u16 * vport)1671 int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
1672 {
1673 struct mlx5e_priv *out_priv, *route_priv;
1674 struct mlx5_core_dev *route_mdev;
1675 struct mlx5_devcom_comp_dev *pos;
1676 struct mlx5_eswitch *esw;
1677 u16 vhca_id;
1678 int err;
1679
1680 out_priv = netdev_priv(out_dev);
1681 esw = out_priv->mdev->priv.eswitch;
1682 route_priv = netdev_priv(route_dev);
1683 route_mdev = route_priv->mdev;
1684
1685 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
1686 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1687 if (!err)
1688 return err;
1689
1690 if (!mlx5_lag_is_active(out_priv->mdev))
1691 return err;
1692
1693 rcu_read_lock();
1694 err = -ENODEV;
1695 mlx5_devcom_for_each_peer_entry_rcu(esw->devcom, esw, pos) {
1696 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1697 if (!err)
1698 break;
1699 }
1700 rcu_read_unlock();
1701
1702 return err;
1703 }
1704
1705 static int
verify_attr_actions(u32 actions,struct netlink_ext_ack * extack)1706 verify_attr_actions(u32 actions, struct netlink_ext_ack *extack)
1707 {
1708 if (!(actions &
1709 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
1710 NL_SET_ERR_MSG_MOD(extack, "Rule must have at least one forward/drop action");
1711 return -EOPNOTSUPP;
1712 }
1713
1714 if (!(~actions &
1715 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
1716 NL_SET_ERR_MSG_MOD(extack, "Rule cannot support forward+drop action");
1717 return -EOPNOTSUPP;
1718 }
1719
1720 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1721 actions & MLX5_FLOW_CONTEXT_ACTION_DROP) {
1722 NL_SET_ERR_MSG_MOD(extack, "Drop with modify header action is not supported");
1723 return -EOPNOTSUPP;
1724 }
1725
1726 return 0;
1727 }
1728
1729 static bool
has_encap_dests(struct mlx5_flow_attr * attr)1730 has_encap_dests(struct mlx5_flow_attr *attr)
1731 {
1732 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
1733 int out_index;
1734
1735 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
1736 if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1737 return true;
1738
1739 return false;
1740 }
1741
1742 static int
extra_split_attr_dests_needed(struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr)1743 extra_split_attr_dests_needed(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr)
1744 {
1745 bool int_dest = false, ext_dest = false;
1746 struct mlx5_esw_flow_attr *esw_attr;
1747 int i;
1748
1749 if (flow->attr != attr ||
1750 !list_is_first(&attr->list, &flow->attrs))
1751 return 0;
1752
1753 esw_attr = attr->esw_attr;
1754 if (!esw_attr->split_count ||
1755 esw_attr->split_count == esw_attr->out_count - 1)
1756 return 0;
1757
1758 if (esw_attr->dest_int_port &&
1759 (esw_attr->dests[esw_attr->split_count].flags &
1760 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE))
1761 return esw_attr->split_count + 1;
1762
1763 for (i = esw_attr->split_count; i < esw_attr->out_count; i++) {
1764 /* external dest with encap is considered as internal by firmware */
1765 if (esw_attr->dests[i].vport == MLX5_VPORT_UPLINK &&
1766 !(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1767 ext_dest = true;
1768 else
1769 int_dest = true;
1770
1771 if (ext_dest && int_dest)
1772 return esw_attr->split_count;
1773 }
1774
1775 return 0;
1776 }
1777
1778 static int
extra_split_attr_dests(struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr,int split_count)1779 extra_split_attr_dests(struct mlx5e_tc_flow *flow,
1780 struct mlx5_flow_attr *attr, int split_count)
1781 {
1782 struct mlx5e_post_act *post_act = get_post_action(flow->priv);
1783 struct mlx5e_tc_flow_parse_attr *parse_attr, *parse_attr2;
1784 struct mlx5_esw_flow_attr *esw_attr, *esw_attr2;
1785 struct mlx5e_post_act_handle *handle;
1786 struct mlx5_flow_attr *attr2;
1787 int i, j, err;
1788
1789 if (IS_ERR(post_act))
1790 return PTR_ERR(post_act);
1791
1792 attr2 = mlx5_alloc_flow_attr(mlx5e_get_flow_namespace(flow));
1793 parse_attr2 = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
1794 if (!attr2 || !parse_attr2) {
1795 err = -ENOMEM;
1796 goto err_free;
1797 }
1798 attr2->parse_attr = parse_attr2;
1799
1800 handle = mlx5e_tc_post_act_add(post_act, attr2);
1801 if (IS_ERR(handle)) {
1802 err = PTR_ERR(handle);
1803 goto err_free;
1804 }
1805
1806 esw_attr = attr->esw_attr;
1807 esw_attr2 = attr2->esw_attr;
1808 esw_attr2->in_rep = esw_attr->in_rep;
1809
1810 parse_attr = attr->parse_attr;
1811 parse_attr2->filter_dev = parse_attr->filter_dev;
1812
1813 for (i = split_count, j = 0; i < esw_attr->out_count; i++, j++)
1814 esw_attr2->dests[j] = esw_attr->dests[i];
1815
1816 esw_attr2->out_count = j;
1817 attr2->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1818
1819 err = mlx5e_tc_post_act_offload(post_act, handle);
1820 if (err)
1821 goto err_post_act_offload;
1822
1823 err = mlx5e_tc_post_act_set_handle(flow->priv->mdev, handle,
1824 &parse_attr->mod_hdr_acts);
1825 if (err)
1826 goto err_post_act_set_handle;
1827
1828 esw_attr->out_count = split_count;
1829 attr->extra_split_ft = mlx5e_tc_post_act_get_ft(post_act);
1830 flow->extra_split_attr = attr2;
1831
1832 attr2->post_act_handle = handle;
1833
1834 return 0;
1835
1836 err_post_act_set_handle:
1837 mlx5e_tc_post_act_unoffload(post_act, handle);
1838 err_post_act_offload:
1839 mlx5e_tc_post_act_del(post_act, handle);
1840 err_free:
1841 kvfree(parse_attr2);
1842 kfree(attr2);
1843 return err;
1844 }
1845
1846 static int
post_process_attr(struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr,struct netlink_ext_ack * extack)1847 post_process_attr(struct mlx5e_tc_flow *flow,
1848 struct mlx5_flow_attr *attr,
1849 struct netlink_ext_ack *extack)
1850 {
1851 int extra_split;
1852 bool vf_tun;
1853 int err = 0;
1854
1855 err = verify_attr_actions(attr->action, extack);
1856 if (err)
1857 goto err_out;
1858
1859 if (mlx5e_is_eswitch_flow(flow) && has_encap_dests(attr)) {
1860 err = mlx5e_tc_tun_encap_dests_set(flow->priv, flow, attr, extack, &vf_tun);
1861 if (err)
1862 goto err_out;
1863 }
1864
1865 extra_split = extra_split_attr_dests_needed(flow, attr);
1866 if (extra_split > 0) {
1867 err = extra_split_attr_dests(flow, attr, extra_split);
1868 if (err)
1869 goto err_out;
1870 }
1871
1872 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1873 err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr);
1874 if (err)
1875 goto err_out;
1876 }
1877
1878 if (attr->branch_true &&
1879 attr->branch_true->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1880 err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr->branch_true);
1881 if (err)
1882 goto err_out;
1883 }
1884
1885 if (attr->branch_false &&
1886 attr->branch_false->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1887 err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr->branch_false);
1888 if (err)
1889 goto err_out;
1890 }
1891
1892 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1893 err = alloc_flow_attr_counter(get_flow_counter_dev(flow), attr);
1894 if (err)
1895 goto err_out;
1896 }
1897
1898 err_out:
1899 return err;
1900 }
1901
1902 static int
mlx5e_tc_add_fdb_flow(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct netlink_ext_ack * extack)1903 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
1904 struct mlx5e_tc_flow *flow,
1905 struct netlink_ext_ack *extack)
1906 {
1907 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1908 struct mlx5e_tc_flow_parse_attr *parse_attr;
1909 struct mlx5_flow_attr *attr = flow->attr;
1910 struct mlx5_esw_flow_attr *esw_attr;
1911 u32 max_prio, max_chain;
1912 int err = 0;
1913
1914 parse_attr = attr->parse_attr;
1915 esw_attr = attr->esw_attr;
1916
1917 /* We check chain range only for tc flows.
1918 * For ft flows, we checked attr->chain was originally 0 and set it to
1919 * FDB_FT_CHAIN which is outside tc range.
1920 * See mlx5e_rep_setup_ft_cb().
1921 */
1922 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
1923 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
1924 NL_SET_ERR_MSG_MOD(extack,
1925 "Requested chain is out of supported range");
1926 err = -EOPNOTSUPP;
1927 goto err_out;
1928 }
1929
1930 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
1931 if (attr->prio > max_prio) {
1932 NL_SET_ERR_MSG_MOD(extack,
1933 "Requested priority is out of supported range");
1934 err = -EOPNOTSUPP;
1935 goto err_out;
1936 }
1937
1938 if (flow_flag_test(flow, TUN_RX)) {
1939 err = mlx5e_attach_decap_route(priv, flow);
1940 if (err)
1941 goto err_out;
1942
1943 if (!attr->chain && esw_attr->int_port &&
1944 attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1945 /* If decap route device is internal port, change the
1946 * source vport value in reg_c0 back to uplink just in
1947 * case the rule performs goto chain > 0. If we have a miss
1948 * on chain > 0 we want the metadata regs to hold the
1949 * chain id so SW will resume handling of this packet
1950 * from the proper chain.
1951 */
1952 u32 metadata = mlx5_eswitch_get_vport_metadata_for_set(esw,
1953 esw_attr->in_rep->vport);
1954
1955 err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
1956 MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
1957 metadata);
1958 if (err)
1959 goto err_out;
1960
1961 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1962 }
1963 }
1964
1965 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1966 err = mlx5e_attach_decap(priv, flow, extack);
1967 if (err)
1968 goto err_out;
1969 }
1970
1971 if (netif_is_ovs_master(parse_attr->filter_dev)) {
1972 struct mlx5e_tc_int_port *int_port;
1973
1974 if (attr->chain) {
1975 NL_SET_ERR_MSG_MOD(extack,
1976 "Internal port rule is only supported on chain 0");
1977 err = -EOPNOTSUPP;
1978 goto err_out;
1979 }
1980
1981 if (attr->dest_chain) {
1982 NL_SET_ERR_MSG_MOD(extack,
1983 "Internal port rule offload doesn't support goto action");
1984 err = -EOPNOTSUPP;
1985 goto err_out;
1986 }
1987
1988 int_port = mlx5e_tc_int_port_get(mlx5e_get_int_port_priv(priv),
1989 parse_attr->filter_dev->ifindex,
1990 flow_flag_test(flow, EGRESS) ?
1991 MLX5E_TC_INT_PORT_EGRESS :
1992 MLX5E_TC_INT_PORT_INGRESS);
1993 if (IS_ERR(int_port)) {
1994 err = PTR_ERR(int_port);
1995 goto err_out;
1996 }
1997
1998 esw_attr->int_port = int_port;
1999 }
2000
2001 err = post_process_attr(flow, attr, extack);
2002 if (err)
2003 goto err_out;
2004
2005 err = mlx5e_tc_act_stats_add_flow(get_act_stats_handle(priv), flow);
2006 if (err)
2007 goto err_out;
2008
2009 /* we get here if one of the following takes place:
2010 * (1) there's no error
2011 * (2) there's an encap action and we don't have valid neigh
2012 */
2013 if (flow_flag_test(flow, SLOW))
2014 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
2015 else
2016 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
2017
2018 if (IS_ERR(flow->rule[0])) {
2019 err = PTR_ERR(flow->rule[0]);
2020 goto err_out;
2021 }
2022 flow_flag_set(flow, OFFLOADED);
2023
2024 return 0;
2025
2026 err_out:
2027 flow_flag_set(flow, FAILED);
2028 return err;
2029 }
2030
mlx5_flow_has_geneve_opt(struct mlx5_flow_spec * spec)2031 static bool mlx5_flow_has_geneve_opt(struct mlx5_flow_spec *spec)
2032 {
2033 void *headers_v = MLX5_ADDR_OF(fte_match_param,
2034 spec->match_value,
2035 misc_parameters_3);
2036 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
2037 headers_v,
2038 geneve_tlv_option_0_data);
2039
2040 return !!geneve_tlv_opt_0_data;
2041 }
2042
free_branch_attr(struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr)2043 static void free_branch_attr(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr)
2044 {
2045 if (!attr)
2046 return;
2047
2048 mlx5_free_flow_attr_actions(flow, attr);
2049 kvfree(attr->parse_attr);
2050 kfree(attr);
2051 }
2052
mlx5e_tc_del_fdb_flow(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow)2053 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
2054 struct mlx5e_tc_flow *flow)
2055 {
2056 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2057 struct mlx5_flow_attr *attr = flow->attr;
2058
2059 mlx5e_put_flow_tunnel_id(flow);
2060
2061 remove_unready_flow(flow);
2062
2063 if (mlx5e_is_offloaded_flow(flow)) {
2064 if (flow_flag_test(flow, SLOW))
2065 mlx5e_tc_unoffload_from_slow_path(esw, flow);
2066 else
2067 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
2068 }
2069 complete_all(&flow->del_hw_done);
2070
2071 if (mlx5_flow_has_geneve_opt(&attr->parse_attr->spec))
2072 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
2073
2074 if (flow->decap_route)
2075 mlx5e_detach_decap_route(priv, flow);
2076
2077 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
2078
2079 if (flow_flag_test(flow, L3_TO_L2_DECAP))
2080 mlx5e_detach_decap(priv, flow);
2081
2082 mlx5e_tc_act_stats_del_flow(get_act_stats_handle(priv), flow);
2083
2084 free_flow_post_acts(flow);
2085 if (flow->extra_split_attr) {
2086 mlx5_free_flow_attr_actions(flow, flow->extra_split_attr);
2087 kvfree(flow->extra_split_attr->parse_attr);
2088 kfree(flow->extra_split_attr);
2089 }
2090 mlx5_free_flow_attr_actions(flow, attr);
2091
2092 kvfree(attr->esw_attr->rx_tun_attr);
2093 kvfree(attr->parse_attr);
2094 kfree(flow->attr);
2095 }
2096
mlx5e_tc_get_counter(struct mlx5e_tc_flow * flow)2097 struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
2098 {
2099 struct mlx5_flow_attr *attr;
2100
2101 attr = list_first_entry(&flow->attrs, struct mlx5_flow_attr, list);
2102 return attr->counter;
2103 }
2104
2105 /* Iterate over tmp_list of flows attached to flow_list head. */
mlx5e_put_flow_list(struct mlx5e_priv * priv,struct list_head * flow_list)2106 void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
2107 {
2108 struct mlx5e_tc_flow *flow, *tmp;
2109
2110 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
2111 mlx5e_flow_put(priv, flow);
2112 }
2113
mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow * flow,int peer_index)2114 static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow,
2115 int peer_index)
2116 {
2117 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
2118 struct mlx5e_tc_flow *peer_flow;
2119 struct mlx5e_tc_flow *tmp;
2120
2121 if (!flow_flag_test(flow, ESWITCH) ||
2122 !flow_flag_test(flow, DUP))
2123 return;
2124
2125 mutex_lock(&esw->offloads.peer_mutex);
2126 list_del(&flow->peer[peer_index]);
2127 mutex_unlock(&esw->offloads.peer_mutex);
2128
2129 list_for_each_entry_safe(peer_flow, tmp, &flow->peer_flows, peer_flows) {
2130 if (peer_index != mlx5_get_dev_index(peer_flow->priv->mdev))
2131 continue;
2132
2133 list_del(&peer_flow->peer_flows);
2134 if (refcount_dec_and_test(&peer_flow->refcnt)) {
2135 mlx5e_tc_del_fdb_flow(peer_flow->priv, peer_flow);
2136 kfree(peer_flow);
2137 }
2138 }
2139
2140 if (list_empty(&flow->peer_flows))
2141 flow_flag_clear(flow, DUP);
2142 }
2143
mlx5e_tc_del_fdb_peers_flow(struct mlx5e_tc_flow * flow)2144 static void mlx5e_tc_del_fdb_peers_flow(struct mlx5e_tc_flow *flow)
2145 {
2146 int i;
2147
2148 for (i = 0; i < MLX5_MAX_PORTS; i++) {
2149 if (i == mlx5_get_dev_index(flow->priv->mdev))
2150 continue;
2151 mlx5e_tc_del_fdb_peer_flow(flow, i);
2152 }
2153 }
2154
mlx5e_tc_del_flow(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow)2155 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
2156 struct mlx5e_tc_flow *flow)
2157 {
2158 if (mlx5e_is_eswitch_flow(flow)) {
2159 struct mlx5_devcom_comp_dev *devcom = flow->priv->mdev->priv.eswitch->devcom;
2160
2161 if (!mlx5_devcom_for_each_peer_begin(devcom)) {
2162 mlx5e_tc_del_fdb_flow(priv, flow);
2163 return;
2164 }
2165
2166 mlx5e_tc_del_fdb_peers_flow(flow);
2167 mlx5_devcom_for_each_peer_end(devcom);
2168 mlx5e_tc_del_fdb_flow(priv, flow);
2169 } else {
2170 mlx5e_tc_del_nic_flow(priv, flow);
2171 }
2172 }
2173
flow_requires_tunnel_mapping(u32 chain,struct flow_cls_offload * f)2174 static bool flow_requires_tunnel_mapping(u32 chain, struct flow_cls_offload *f)
2175 {
2176 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2177 struct flow_action *flow_action = &rule->action;
2178 const struct flow_action_entry *act;
2179 int i;
2180
2181 if (chain)
2182 return false;
2183
2184 flow_action_for_each(i, act, flow_action) {
2185 switch (act->id) {
2186 case FLOW_ACTION_GOTO:
2187 return true;
2188 case FLOW_ACTION_SAMPLE:
2189 return true;
2190 default:
2191 continue;
2192 }
2193 }
2194
2195 return false;
2196 }
2197
2198 static int
enc_opts_is_dont_care_or_full_match(struct mlx5e_priv * priv,struct flow_dissector_key_enc_opts * opts,struct netlink_ext_ack * extack,bool * dont_care)2199 enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
2200 struct flow_dissector_key_enc_opts *opts,
2201 struct netlink_ext_ack *extack,
2202 bool *dont_care)
2203 {
2204 struct geneve_opt *opt;
2205 int off = 0;
2206
2207 *dont_care = true;
2208
2209 while (opts->len > off) {
2210 opt = (struct geneve_opt *)&opts->data[off];
2211
2212 if (!(*dont_care) || opt->opt_class || opt->type ||
2213 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
2214 *dont_care = false;
2215
2216 if (opt->opt_class != htons(U16_MAX) ||
2217 opt->type != U8_MAX) {
2218 NL_SET_ERR_MSG_MOD(extack,
2219 "Partial match of tunnel options in chain > 0 isn't supported");
2220 netdev_warn(priv->netdev,
2221 "Partial match of tunnel options in chain > 0 isn't supported");
2222 return -EOPNOTSUPP;
2223 }
2224 }
2225
2226 off += sizeof(struct geneve_opt) + opt->length * 4;
2227 }
2228
2229 return 0;
2230 }
2231
2232 #define COPY_DISSECTOR(rule, diss_key, dst)\
2233 ({ \
2234 struct flow_rule *__rule = (rule);\
2235 typeof(dst) __dst = dst;\
2236 \
2237 memcpy(__dst,\
2238 skb_flow_dissector_target(__rule->match.dissector,\
2239 diss_key,\
2240 __rule->match.key),\
2241 sizeof(*__dst));\
2242 })
2243
mlx5e_get_flow_tunnel_id(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct flow_cls_offload * f,struct net_device * filter_dev)2244 static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
2245 struct mlx5e_tc_flow *flow,
2246 struct flow_cls_offload *f,
2247 struct net_device *filter_dev)
2248 {
2249 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2250 struct netlink_ext_ack *extack = f->common.extack;
2251 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
2252 struct flow_match_enc_opts enc_opts_match;
2253 struct tunnel_match_enc_opts tun_enc_opts;
2254 struct mlx5_rep_uplink_priv *uplink_priv;
2255 struct mlx5_flow_attr *attr = flow->attr;
2256 struct mlx5e_rep_priv *uplink_rpriv;
2257 struct tunnel_match_key tunnel_key;
2258 bool enc_opts_is_dont_care = true;
2259 u32 tun_id, enc_opts_id = 0;
2260 struct mlx5_eswitch *esw;
2261 u32 value, mask;
2262 int err;
2263
2264 esw = priv->mdev->priv.eswitch;
2265 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2266 uplink_priv = &uplink_rpriv->uplink_priv;
2267
2268 memset(&tunnel_key, 0, sizeof(tunnel_key));
2269 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
2270 &tunnel_key.enc_control);
2271 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
2272 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
2273 &tunnel_key.enc_ipv4);
2274 else
2275 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
2276 &tunnel_key.enc_ipv6);
2277 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
2278 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
2279 &tunnel_key.enc_tp);
2280 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
2281 &tunnel_key.enc_key_id);
2282 tunnel_key.filter_ifindex = filter_dev->ifindex;
2283
2284 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
2285 if (err)
2286 return err;
2287
2288 flow_rule_match_enc_opts(rule, &enc_opts_match);
2289 err = enc_opts_is_dont_care_or_full_match(priv,
2290 enc_opts_match.mask,
2291 extack,
2292 &enc_opts_is_dont_care);
2293 if (err)
2294 goto err_enc_opts;
2295
2296 if (!enc_opts_is_dont_care) {
2297 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
2298 memcpy(&tun_enc_opts.key, enc_opts_match.key,
2299 sizeof(*enc_opts_match.key));
2300 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
2301 sizeof(*enc_opts_match.mask));
2302
2303 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
2304 &tun_enc_opts, &enc_opts_id);
2305 if (err)
2306 goto err_enc_opts;
2307 }
2308
2309 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
2310 mask = enc_opts_id ? TUNNEL_ID_MASK :
2311 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
2312
2313 if (attr->chain) {
2314 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
2315 TUNNEL_TO_REG, value, mask);
2316 } else {
2317 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
2318 err = mlx5e_tc_match_to_reg_set(priv->mdev,
2319 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
2320 TUNNEL_TO_REG, value);
2321 if (err)
2322 goto err_set;
2323
2324 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2325 }
2326
2327 flow->attr->tunnel_id = value;
2328 return 0;
2329
2330 err_set:
2331 if (enc_opts_id)
2332 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2333 enc_opts_id);
2334 err_enc_opts:
2335 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2336 return err;
2337 }
2338
mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow * flow)2339 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
2340 {
2341 u32 enc_opts_id = flow->attr->tunnel_id & ENC_OPTS_BITS_MASK;
2342 u32 tun_id = flow->attr->tunnel_id >> ENC_OPTS_BITS;
2343 struct mlx5_rep_uplink_priv *uplink_priv;
2344 struct mlx5e_rep_priv *uplink_rpriv;
2345 struct mlx5_eswitch *esw;
2346
2347 esw = flow->priv->mdev->priv.eswitch;
2348 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2349 uplink_priv = &uplink_rpriv->uplink_priv;
2350
2351 if (tun_id)
2352 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2353 if (enc_opts_id)
2354 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2355 enc_opts_id);
2356 }
2357
mlx5e_tc_set_ethertype(struct mlx5_core_dev * mdev,struct flow_match_basic * match,bool outer,void * headers_c,void * headers_v)2358 void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
2359 struct flow_match_basic *match, bool outer,
2360 void *headers_c, void *headers_v)
2361 {
2362 bool ip_version_cap;
2363
2364 ip_version_cap = outer ?
2365 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2366 ft_field_support.outer_ip_version) :
2367 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2368 ft_field_support.inner_ip_version);
2369
2370 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
2371 (match->key->n_proto == htons(ETH_P_IP) ||
2372 match->key->n_proto == htons(ETH_P_IPV6))) {
2373 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
2374 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
2375 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
2376 } else {
2377 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
2378 ntohs(match->mask->n_proto));
2379 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
2380 ntohs(match->key->n_proto));
2381 }
2382 }
2383
mlx5e_tc_get_ip_version(struct mlx5_flow_spec * spec,bool outer)2384 u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
2385 {
2386 void *headers_v;
2387 u16 ethertype;
2388 u8 ip_version;
2389
2390 if (outer)
2391 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2392 else
2393 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
2394
2395 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
2396 /* Return ip_version converted from ethertype anyway */
2397 if (!ip_version) {
2398 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2399 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
2400 ip_version = 4;
2401 else if (ethertype == ETH_P_IPV6)
2402 ip_version = 6;
2403 }
2404 return ip_version;
2405 }
2406
2407 /* Tunnel device follows RFC 6040, see include/net/inet_ecn.h.
2408 * And changes inner ip_ecn depending on inner and outer ip_ecn as follows:
2409 * +---------+----------------------------------------+
2410 * |Arriving | Arriving Outer Header |
2411 * | Inner +---------+---------+---------+----------+
2412 * | Header | Not-ECT | ECT(0) | ECT(1) | CE |
2413 * +---------+---------+---------+---------+----------+
2414 * | Not-ECT | Not-ECT | Not-ECT | Not-ECT | <drop> |
2415 * | ECT(0) | ECT(0) | ECT(0) | ECT(1) | CE* |
2416 * | ECT(1) | ECT(1) | ECT(1) | ECT(1)* | CE* |
2417 * | CE | CE | CE | CE | CE |
2418 * +---------+---------+---------+---------+----------+
2419 *
2420 * Tc matches on inner after decapsulation on tunnel device, but hw offload matches
2421 * the inner ip_ecn value before hardware decap action.
2422 *
2423 * Cells marked are changed from original inner packet ip_ecn value during decap, and
2424 * so matching those values on inner ip_ecn before decap will fail.
2425 *
2426 * The following helper allows offload when inner ip_ecn won't be changed by outer ip_ecn,
2427 * except for the outer ip_ecn = CE, where in all cases inner ip_ecn will be changed to CE,
2428 * and such we can drop the inner ip_ecn=CE match.
2429 */
2430
mlx5e_tc_verify_tunnel_ecn(struct mlx5e_priv * priv,struct flow_cls_offload * f,bool * match_inner_ecn)2431 static int mlx5e_tc_verify_tunnel_ecn(struct mlx5e_priv *priv,
2432 struct flow_cls_offload *f,
2433 bool *match_inner_ecn)
2434 {
2435 u8 outer_ecn_mask = 0, outer_ecn_key = 0, inner_ecn_mask = 0, inner_ecn_key = 0;
2436 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2437 struct netlink_ext_ack *extack = f->common.extack;
2438 struct flow_match_ip match;
2439
2440 *match_inner_ecn = true;
2441
2442 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
2443 flow_rule_match_enc_ip(rule, &match);
2444 outer_ecn_key = match.key->tos & INET_ECN_MASK;
2445 outer_ecn_mask = match.mask->tos & INET_ECN_MASK;
2446 }
2447
2448 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2449 flow_rule_match_ip(rule, &match);
2450 inner_ecn_key = match.key->tos & INET_ECN_MASK;
2451 inner_ecn_mask = match.mask->tos & INET_ECN_MASK;
2452 }
2453
2454 if (outer_ecn_mask != 0 && outer_ecn_mask != INET_ECN_MASK) {
2455 NL_SET_ERR_MSG_MOD(extack, "Partial match on enc_tos ecn bits isn't supported");
2456 netdev_warn(priv->netdev, "Partial match on enc_tos ecn bits isn't supported");
2457 return -EOPNOTSUPP;
2458 }
2459
2460 if (!outer_ecn_mask) {
2461 if (!inner_ecn_mask)
2462 return 0;
2463
2464 NL_SET_ERR_MSG_MOD(extack,
2465 "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2466 netdev_warn(priv->netdev,
2467 "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2468 return -EOPNOTSUPP;
2469 }
2470
2471 if (inner_ecn_mask && inner_ecn_mask != INET_ECN_MASK) {
2472 NL_SET_ERR_MSG_MOD(extack,
2473 "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2474 netdev_warn(priv->netdev,
2475 "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2476 return -EOPNOTSUPP;
2477 }
2478
2479 if (!inner_ecn_mask)
2480 return 0;
2481
2482 /* Both inner and outer have full mask on ecn */
2483
2484 if (outer_ecn_key == INET_ECN_ECT_1) {
2485 /* inner ecn might change by DECAP action */
2486
2487 NL_SET_ERR_MSG_MOD(extack, "Match on enc_tos ecn = ECT(1) isn't supported");
2488 netdev_warn(priv->netdev, "Match on enc_tos ecn = ECT(1) isn't supported");
2489 return -EOPNOTSUPP;
2490 }
2491
2492 if (outer_ecn_key != INET_ECN_CE)
2493 return 0;
2494
2495 if (inner_ecn_key != INET_ECN_CE) {
2496 /* Can't happen in software, as packet ecn will be changed to CE after decap */
2497 NL_SET_ERR_MSG_MOD(extack,
2498 "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2499 netdev_warn(priv->netdev,
2500 "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2501 return -EOPNOTSUPP;
2502 }
2503
2504 /* outer ecn = CE, inner ecn = CE, as decap will change inner ecn to CE in anycase,
2505 * drop match on inner ecn
2506 */
2507 *match_inner_ecn = false;
2508
2509 return 0;
2510 }
2511
parse_tunnel_attr(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct mlx5_flow_spec * spec,struct flow_cls_offload * f,struct net_device * filter_dev,u8 * match_level,bool * match_inner)2512 static int parse_tunnel_attr(struct mlx5e_priv *priv,
2513 struct mlx5e_tc_flow *flow,
2514 struct mlx5_flow_spec *spec,
2515 struct flow_cls_offload *f,
2516 struct net_device *filter_dev,
2517 u8 *match_level,
2518 bool *match_inner)
2519 {
2520 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
2521 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2522 struct netlink_ext_ack *extack = f->common.extack;
2523 bool needs_mapping, sets_mapping;
2524 int err;
2525
2526 if (!mlx5e_is_eswitch_flow(flow)) {
2527 NL_SET_ERR_MSG_MOD(extack, "Match on tunnel is not supported");
2528 return -EOPNOTSUPP;
2529 }
2530
2531 needs_mapping = !!flow->attr->chain;
2532 sets_mapping = flow_requires_tunnel_mapping(flow->attr->chain, f);
2533 *match_inner = !needs_mapping;
2534
2535 if ((needs_mapping || sets_mapping) &&
2536 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
2537 NL_SET_ERR_MSG_MOD(extack,
2538 "Chains on tunnel devices isn't supported without register loopback support");
2539 netdev_warn(priv->netdev,
2540 "Chains on tunnel devices isn't supported without register loopback support");
2541 return -EOPNOTSUPP;
2542 }
2543
2544 if (!flow->attr->chain) {
2545 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
2546 match_level);
2547 if (err) {
2548 NL_SET_ERR_MSG_MOD(extack,
2549 "Failed to parse tunnel attributes");
2550 netdev_warn(priv->netdev,
2551 "Failed to parse tunnel attributes");
2552 return err;
2553 }
2554
2555 /* With mpls over udp we decapsulate using packet reformat
2556 * object
2557 */
2558 if (!netif_is_bareudp(filter_dev))
2559 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2560 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
2561 if (err)
2562 return err;
2563 } else if (tunnel) {
2564 struct mlx5_flow_spec *tmp_spec;
2565
2566 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
2567 if (!tmp_spec) {
2568 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for tunnel tmp spec");
2569 netdev_warn(priv->netdev, "Failed to allocate memory for tunnel tmp spec");
2570 return -ENOMEM;
2571 }
2572 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
2573
2574 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
2575 if (err) {
2576 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
2577 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
2578 } else {
2579 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
2580 }
2581 if (mlx5_flow_has_geneve_opt(tmp_spec))
2582 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
2583 kvfree(tmp_spec);
2584 if (err)
2585 return err;
2586 }
2587
2588 if (!needs_mapping && !sets_mapping)
2589 return 0;
2590
2591 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
2592 }
2593
get_match_inner_headers_criteria(struct mlx5_flow_spec * spec)2594 static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
2595 {
2596 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2597 inner_headers);
2598 }
2599
get_match_inner_headers_value(struct mlx5_flow_spec * spec)2600 static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
2601 {
2602 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2603 inner_headers);
2604 }
2605
get_match_outer_headers_criteria(struct mlx5_flow_spec * spec)2606 static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2607 {
2608 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2609 outer_headers);
2610 }
2611
get_match_outer_headers_value(struct mlx5_flow_spec * spec)2612 static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2613 {
2614 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2615 outer_headers);
2616 }
2617
mlx5e_get_match_headers_value(u32 flags,struct mlx5_flow_spec * spec)2618 void *mlx5e_get_match_headers_value(u32 flags, struct mlx5_flow_spec *spec)
2619 {
2620 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2621 get_match_inner_headers_value(spec) :
2622 get_match_outer_headers_value(spec);
2623 }
2624
mlx5e_get_match_headers_criteria(u32 flags,struct mlx5_flow_spec * spec)2625 void *mlx5e_get_match_headers_criteria(u32 flags, struct mlx5_flow_spec *spec)
2626 {
2627 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2628 get_match_inner_headers_criteria(spec) :
2629 get_match_outer_headers_criteria(spec);
2630 }
2631
mlx5e_flower_parse_meta(struct net_device * filter_dev,struct flow_cls_offload * f)2632 static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2633 struct flow_cls_offload *f)
2634 {
2635 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2636 struct netlink_ext_ack *extack = f->common.extack;
2637 struct net_device *ingress_dev;
2638 struct flow_match_meta match;
2639
2640 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2641 return 0;
2642
2643 flow_rule_match_meta(rule, &match);
2644
2645 if (match.mask->l2_miss) {
2646 NL_SET_ERR_MSG_MOD(f->common.extack, "Can't match on \"l2_miss\"");
2647 return -EOPNOTSUPP;
2648 }
2649
2650 if (!match.mask->ingress_ifindex)
2651 return 0;
2652
2653 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2654 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
2655 return -EOPNOTSUPP;
2656 }
2657
2658 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2659 match.key->ingress_ifindex);
2660 if (!ingress_dev) {
2661 NL_SET_ERR_MSG_MOD(extack,
2662 "Can't find the ingress port to match on");
2663 return -ENOENT;
2664 }
2665
2666 if (ingress_dev != filter_dev) {
2667 NL_SET_ERR_MSG_MOD(extack,
2668 "Can't match on the ingress filter port");
2669 return -EOPNOTSUPP;
2670 }
2671
2672 return 0;
2673 }
2674
skip_key_basic(struct net_device * filter_dev,struct flow_cls_offload * f)2675 static bool skip_key_basic(struct net_device *filter_dev,
2676 struct flow_cls_offload *f)
2677 {
2678 /* When doing mpls over udp decap, the user needs to provide
2679 * MPLS_UC as the protocol in order to be able to match on mpls
2680 * label fields. However, the actual ethertype is IP so we want to
2681 * avoid matching on this, otherwise we'll fail the match.
2682 */
2683 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2684 return true;
2685
2686 return false;
2687 }
2688
__parse_cls_flower(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct mlx5_flow_spec * spec,struct flow_cls_offload * f,struct net_device * filter_dev,u8 * inner_match_level,u8 * outer_match_level)2689 static int __parse_cls_flower(struct mlx5e_priv *priv,
2690 struct mlx5e_tc_flow *flow,
2691 struct mlx5_flow_spec *spec,
2692 struct flow_cls_offload *f,
2693 struct net_device *filter_dev,
2694 u8 *inner_match_level, u8 *outer_match_level)
2695 {
2696 struct netlink_ext_ack *extack = f->common.extack;
2697 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2698 outer_headers);
2699 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2700 outer_headers);
2701 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2702 misc_parameters);
2703 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2704 misc_parameters);
2705 void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2706 misc_parameters_3);
2707 void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2708 misc_parameters_3);
2709 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2710 struct flow_dissector *dissector = rule->match.dissector;
2711 enum fs_flow_table_type fs_type;
2712 bool match_inner_ecn = true;
2713 u16 addr_type = 0;
2714 u8 ip_proto = 0;
2715 u8 *match_level;
2716 int err;
2717
2718 fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
2719 match_level = outer_match_level;
2720
2721 if (dissector->used_keys &
2722 ~(BIT_ULL(FLOW_DISSECTOR_KEY_META) |
2723 BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
2724 BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
2725 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2726 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
2727 BIT_ULL(FLOW_DISSECTOR_KEY_CVLAN) |
2728 BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2729 BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
2730 BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
2731 BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2732 BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2733 BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2734 BIT_ULL(FLOW_DISSECTOR_KEY_ENC_PORTS) |
2735 BIT_ULL(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
2736 BIT_ULL(FLOW_DISSECTOR_KEY_TCP) |
2737 BIT_ULL(FLOW_DISSECTOR_KEY_IP) |
2738 BIT_ULL(FLOW_DISSECTOR_KEY_CT) |
2739 BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IP) |
2740 BIT_ULL(FLOW_DISSECTOR_KEY_ENC_OPTS) |
2741 BIT_ULL(FLOW_DISSECTOR_KEY_ICMP) |
2742 BIT_ULL(FLOW_DISSECTOR_KEY_MPLS))) {
2743 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
2744 netdev_dbg(priv->netdev, "Unsupported key used: 0x%llx\n",
2745 dissector->used_keys);
2746 return -EOPNOTSUPP;
2747 }
2748
2749 if (mlx5e_get_tc_tun(filter_dev)) {
2750 bool match_inner = false;
2751
2752 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2753 outer_match_level, &match_inner);
2754 if (err)
2755 return err;
2756
2757 if (match_inner) {
2758 /* header pointers should point to the inner headers
2759 * if the packet was decapsulated already.
2760 * outer headers are set by parse_tunnel_attr.
2761 */
2762 match_level = inner_match_level;
2763 headers_c = get_match_inner_headers_criteria(spec);
2764 headers_v = get_match_inner_headers_value(spec);
2765 }
2766
2767 err = mlx5e_tc_verify_tunnel_ecn(priv, f, &match_inner_ecn);
2768 if (err)
2769 return err;
2770 }
2771
2772 err = mlx5e_flower_parse_meta(filter_dev, f);
2773 if (err)
2774 return err;
2775
2776 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2777 !skip_key_basic(filter_dev, f)) {
2778 struct flow_match_basic match;
2779
2780 flow_rule_match_basic(rule, &match);
2781 mlx5e_tc_set_ethertype(priv->mdev, &match,
2782 match_level == outer_match_level,
2783 headers_c, headers_v);
2784
2785 if (match.mask->n_proto)
2786 *match_level = MLX5_MATCH_L2;
2787 }
2788 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2789 is_vlan_dev(filter_dev)) {
2790 struct flow_dissector_key_vlan filter_dev_mask;
2791 struct flow_dissector_key_vlan filter_dev_key;
2792 struct flow_match_vlan match;
2793
2794 if (is_vlan_dev(filter_dev)) {
2795 match.key = &filter_dev_key;
2796 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2797 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2798 match.key->vlan_priority = 0;
2799 match.mask = &filter_dev_mask;
2800 memset(match.mask, 0xff, sizeof(*match.mask));
2801 match.mask->vlan_priority = 0;
2802 } else {
2803 flow_rule_match_vlan(rule, &match);
2804 }
2805 if (match.mask->vlan_id ||
2806 match.mask->vlan_priority ||
2807 match.mask->vlan_tpid) {
2808 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2809 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2810 svlan_tag, 1);
2811 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2812 svlan_tag, 1);
2813 } else {
2814 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2815 cvlan_tag, 1);
2816 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2817 cvlan_tag, 1);
2818 }
2819
2820 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2821 match.mask->vlan_id);
2822 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2823 match.key->vlan_id);
2824
2825 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2826 match.mask->vlan_priority);
2827 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2828 match.key->vlan_priority);
2829
2830 *match_level = MLX5_MATCH_L2;
2831
2832 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN) &&
2833 match.mask->vlan_eth_type &&
2834 MLX5_CAP_FLOWTABLE_TYPE(priv->mdev,
2835 ft_field_support.outer_second_vid,
2836 fs_type)) {
2837 MLX5_SET(fte_match_set_misc, misc_c,
2838 outer_second_cvlan_tag, 1);
2839 spec->match_criteria_enable |=
2840 MLX5_MATCH_MISC_PARAMETERS;
2841 }
2842 }
2843 } else if (*match_level != MLX5_MATCH_NONE) {
2844 /* cvlan_tag enabled in match criteria and
2845 * disabled in match value means both S & C tags
2846 * don't exist (untagged of both)
2847 */
2848 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
2849 *match_level = MLX5_MATCH_L2;
2850 }
2851
2852 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2853 struct flow_match_vlan match;
2854
2855 flow_rule_match_cvlan(rule, &match);
2856 if (match.mask->vlan_id ||
2857 match.mask->vlan_priority ||
2858 match.mask->vlan_tpid) {
2859 if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2860 fs_type)) {
2861 NL_SET_ERR_MSG_MOD(extack,
2862 "Matching on CVLAN is not supported");
2863 return -EOPNOTSUPP;
2864 }
2865
2866 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2867 MLX5_SET(fte_match_set_misc, misc_c,
2868 outer_second_svlan_tag, 1);
2869 MLX5_SET(fte_match_set_misc, misc_v,
2870 outer_second_svlan_tag, 1);
2871 } else {
2872 MLX5_SET(fte_match_set_misc, misc_c,
2873 outer_second_cvlan_tag, 1);
2874 MLX5_SET(fte_match_set_misc, misc_v,
2875 outer_second_cvlan_tag, 1);
2876 }
2877
2878 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
2879 match.mask->vlan_id);
2880 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
2881 match.key->vlan_id);
2882 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
2883 match.mask->vlan_priority);
2884 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
2885 match.key->vlan_priority);
2886
2887 *match_level = MLX5_MATCH_L2;
2888 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
2889 }
2890 }
2891
2892 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2893 struct flow_match_eth_addrs match;
2894
2895 flow_rule_match_eth_addrs(rule, &match);
2896 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2897 dmac_47_16),
2898 match.mask->dst);
2899 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2900 dmac_47_16),
2901 match.key->dst);
2902
2903 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2904 smac_47_16),
2905 match.mask->src);
2906 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2907 smac_47_16),
2908 match.key->src);
2909
2910 if (!is_zero_ether_addr(match.mask->src) ||
2911 !is_zero_ether_addr(match.mask->dst))
2912 *match_level = MLX5_MATCH_L2;
2913 }
2914
2915 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2916 struct flow_match_control match;
2917
2918 flow_rule_match_control(rule, &match);
2919 addr_type = match.key->addr_type;
2920
2921 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
2922 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2923 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
2924 match.key->flags & FLOW_DIS_IS_FRAGMENT);
2925
2926 /* the HW doesn't need L3 inline to match on frag=no */
2927 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
2928 *match_level = MLX5_MATCH_L2;
2929 /* *** L2 attributes parsing up to here *** */
2930 else
2931 *match_level = MLX5_MATCH_L3;
2932 }
2933
2934 if (!flow_rule_is_supp_control_flags(FLOW_DIS_IS_FRAGMENT,
2935 match.mask->flags, extack))
2936 return -EOPNOTSUPP;
2937 }
2938
2939 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2940 struct flow_match_basic match;
2941
2942 flow_rule_match_basic(rule, &match);
2943 ip_proto = match.key->ip_proto;
2944
2945 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2946 match.mask->ip_proto);
2947 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2948 match.key->ip_proto);
2949
2950 if (match.mask->ip_proto)
2951 *match_level = MLX5_MATCH_L3;
2952 }
2953
2954 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
2955 struct flow_match_ipv4_addrs match;
2956
2957 flow_rule_match_ipv4_addrs(rule, &match);
2958 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2959 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2960 &match.mask->src, sizeof(match.mask->src));
2961 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2962 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2963 &match.key->src, sizeof(match.key->src));
2964 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2965 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2966 &match.mask->dst, sizeof(match.mask->dst));
2967 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2968 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2969 &match.key->dst, sizeof(match.key->dst));
2970
2971 if (match.mask->src || match.mask->dst)
2972 *match_level = MLX5_MATCH_L3;
2973 }
2974
2975 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
2976 struct flow_match_ipv6_addrs match;
2977
2978 flow_rule_match_ipv6_addrs(rule, &match);
2979 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2980 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2981 &match.mask->src, sizeof(match.mask->src));
2982 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2983 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2984 &match.key->src, sizeof(match.key->src));
2985
2986 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2987 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2988 &match.mask->dst, sizeof(match.mask->dst));
2989 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2990 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2991 &match.key->dst, sizeof(match.key->dst));
2992
2993 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2994 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
2995 *match_level = MLX5_MATCH_L3;
2996 }
2997
2998 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2999 struct flow_match_ip match;
3000
3001 flow_rule_match_ip(rule, &match);
3002 if (match_inner_ecn) {
3003 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
3004 match.mask->tos & 0x3);
3005 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
3006 match.key->tos & 0x3);
3007 }
3008
3009 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
3010 match.mask->tos >> 2);
3011 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
3012 match.key->tos >> 2);
3013
3014 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
3015 match.mask->ttl);
3016 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
3017 match.key->ttl);
3018
3019 if (match.mask->ttl &&
3020 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3021 ft_field_support.outer_ipv4_ttl)) {
3022 NL_SET_ERR_MSG_MOD(extack,
3023 "Matching on TTL is not supported");
3024 return -EOPNOTSUPP;
3025 }
3026
3027 if (match.mask->tos || match.mask->ttl)
3028 *match_level = MLX5_MATCH_L3;
3029 }
3030
3031 /* *** L3 attributes parsing up to here *** */
3032
3033 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
3034 struct flow_match_ports match;
3035
3036 flow_rule_match_ports(rule, &match);
3037 switch (ip_proto) {
3038 case IPPROTO_TCP:
3039 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
3040 tcp_sport, ntohs(match.mask->src));
3041 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3042 tcp_sport, ntohs(match.key->src));
3043
3044 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
3045 tcp_dport, ntohs(match.mask->dst));
3046 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3047 tcp_dport, ntohs(match.key->dst));
3048 break;
3049
3050 case IPPROTO_UDP:
3051 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
3052 udp_sport, ntohs(match.mask->src));
3053 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3054 udp_sport, ntohs(match.key->src));
3055
3056 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
3057 udp_dport, ntohs(match.mask->dst));
3058 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3059 udp_dport, ntohs(match.key->dst));
3060 break;
3061 default:
3062 NL_SET_ERR_MSG_MOD(extack,
3063 "Only UDP and TCP transports are supported for L4 matching");
3064 netdev_err(priv->netdev,
3065 "Only UDP and TCP transport are supported\n");
3066 return -EINVAL;
3067 }
3068
3069 if (match.mask->src || match.mask->dst)
3070 *match_level = MLX5_MATCH_L4;
3071 }
3072
3073 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
3074 struct flow_match_tcp match;
3075
3076 flow_rule_match_tcp(rule, &match);
3077 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
3078 ntohs(match.mask->flags));
3079 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
3080 ntohs(match.key->flags));
3081
3082 if (match.mask->flags)
3083 *match_level = MLX5_MATCH_L4;
3084 }
3085 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
3086 struct flow_match_icmp match;
3087
3088 flow_rule_match_icmp(rule, &match);
3089 switch (ip_proto) {
3090 case IPPROTO_ICMP:
3091 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
3092 MLX5_FLEX_PROTO_ICMP)) {
3093 NL_SET_ERR_MSG_MOD(extack,
3094 "Match on Flex protocols for ICMP is not supported");
3095 return -EOPNOTSUPP;
3096 }
3097 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
3098 match.mask->type);
3099 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
3100 match.key->type);
3101 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
3102 match.mask->code);
3103 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
3104 match.key->code);
3105 break;
3106 case IPPROTO_ICMPV6:
3107 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
3108 MLX5_FLEX_PROTO_ICMPV6)) {
3109 NL_SET_ERR_MSG_MOD(extack,
3110 "Match on Flex protocols for ICMPV6 is not supported");
3111 return -EOPNOTSUPP;
3112 }
3113 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
3114 match.mask->type);
3115 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
3116 match.key->type);
3117 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
3118 match.mask->code);
3119 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
3120 match.key->code);
3121 break;
3122 default:
3123 NL_SET_ERR_MSG_MOD(extack,
3124 "Code and type matching only with ICMP and ICMPv6");
3125 netdev_err(priv->netdev,
3126 "Code and type matching only with ICMP and ICMPv6\n");
3127 return -EINVAL;
3128 }
3129 if (match.mask->code || match.mask->type) {
3130 *match_level = MLX5_MATCH_L4;
3131 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
3132 }
3133 }
3134 /* Currently supported only for MPLS over UDP */
3135 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
3136 !netif_is_bareudp(filter_dev)) {
3137 NL_SET_ERR_MSG_MOD(extack,
3138 "Matching on MPLS is supported only for MPLS over UDP");
3139 netdev_err(priv->netdev,
3140 "Matching on MPLS is supported only for MPLS over UDP\n");
3141 return -EOPNOTSUPP;
3142 }
3143
3144 return 0;
3145 }
3146
parse_cls_flower(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct mlx5_flow_spec * spec,struct flow_cls_offload * f,struct net_device * filter_dev)3147 static int parse_cls_flower(struct mlx5e_priv *priv,
3148 struct mlx5e_tc_flow *flow,
3149 struct mlx5_flow_spec *spec,
3150 struct flow_cls_offload *f,
3151 struct net_device *filter_dev)
3152 {
3153 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
3154 struct netlink_ext_ack *extack = f->common.extack;
3155 struct mlx5_core_dev *dev = priv->mdev;
3156 struct mlx5_eswitch *esw = dev->priv.eswitch;
3157 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3158 struct mlx5_eswitch_rep *rep;
3159 bool is_eswitch_flow;
3160 int err;
3161
3162 inner_match_level = MLX5_MATCH_NONE;
3163 outer_match_level = MLX5_MATCH_NONE;
3164
3165 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
3166 &inner_match_level, &outer_match_level);
3167 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
3168 outer_match_level : inner_match_level;
3169
3170 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
3171 if (!err && is_eswitch_flow) {
3172 rep = rpriv->rep;
3173 if (rep->vport != MLX5_VPORT_UPLINK &&
3174 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
3175 esw->offloads.inline_mode < non_tunnel_match_level)) {
3176 NL_SET_ERR_MSG_MOD(extack,
3177 "Flow is not offloaded due to min inline setting");
3178 netdev_warn(priv->netdev,
3179 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
3180 non_tunnel_match_level, esw->offloads.inline_mode);
3181 return -EOPNOTSUPP;
3182 }
3183 }
3184
3185 flow->attr->inner_match_level = inner_match_level;
3186 flow->attr->outer_match_level = outer_match_level;
3187
3188
3189 return err;
3190 }
3191
3192 struct mlx5_fields {
3193 u8 field;
3194 u8 field_bsize;
3195 u32 field_mask;
3196 u32 offset;
3197 u32 match_offset;
3198 };
3199
3200 #define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
3201 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
3202 offsetof(struct pedit_headers, field) + (off), \
3203 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
3204
3205 /* masked values are the same and there are no rewrites that do not have a
3206 * match.
3207 */
3208 #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
3209 type matchmaskx = *(type *)(matchmaskp); \
3210 type matchvalx = *(type *)(matchvalp); \
3211 type maskx = *(type *)(maskp); \
3212 type valx = *(type *)(valp); \
3213 \
3214 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
3215 matchmaskx)); \
3216 })
3217
cmp_val_mask(void * valp,void * maskp,void * matchvalp,void * matchmaskp,u8 bsize)3218 static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
3219 void *matchmaskp, u8 bsize)
3220 {
3221 bool same = false;
3222
3223 switch (bsize) {
3224 case 8:
3225 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
3226 break;
3227 case 16:
3228 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
3229 break;
3230 case 32:
3231 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
3232 break;
3233 }
3234
3235 return same;
3236 }
3237
3238 static struct mlx5_fields fields[] = {
3239 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
3240 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
3241 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
3242 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
3243 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
3244 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
3245
3246 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
3247 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
3248 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
3249 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
3250
3251 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
3252 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
3253 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
3254 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
3255 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
3256 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
3257 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
3258 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
3259 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
3260 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
3261 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
3262 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
3263 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
3264 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
3265 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
3266 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
3267 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
3268 OFFLOAD(IP_DSCP, 16, 0x0fc0, ip6, 0, ip_dscp),
3269
3270 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
3271 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
3272 /* in linux iphdr tcp_flags is 8 bits long */
3273 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
3274
3275 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
3276 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
3277 };
3278
mask_field_get(void * mask,struct mlx5_fields * f)3279 static u32 mask_field_get(void *mask, struct mlx5_fields *f)
3280 {
3281 switch (f->field_bsize) {
3282 case 32:
3283 return be32_to_cpu(*(__be32 *)mask) & f->field_mask;
3284 case 16:
3285 return be16_to_cpu(*(__be16 *)mask) & (u16)f->field_mask;
3286 default:
3287 return *(u8 *)mask & (u8)f->field_mask;
3288 }
3289 }
3290
mask_field_clear(void * mask,struct mlx5_fields * f)3291 static void mask_field_clear(void *mask, struct mlx5_fields *f)
3292 {
3293 switch (f->field_bsize) {
3294 case 32:
3295 *(__be32 *)mask &= ~cpu_to_be32(f->field_mask);
3296 break;
3297 case 16:
3298 *(__be16 *)mask &= ~cpu_to_be16((u16)f->field_mask);
3299 break;
3300 default:
3301 *(u8 *)mask &= ~(u8)f->field_mask;
3302 break;
3303 }
3304 }
3305
offload_pedit_fields(struct mlx5e_priv * priv,int namespace,struct mlx5e_tc_flow_parse_attr * parse_attr,u32 * action_flags,struct netlink_ext_ack * extack)3306 static int offload_pedit_fields(struct mlx5e_priv *priv,
3307 int namespace,
3308 struct mlx5e_tc_flow_parse_attr *parse_attr,
3309 u32 *action_flags,
3310 struct netlink_ext_ack *extack)
3311 {
3312 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
3313 struct pedit_headers_action *hdrs = parse_attr->hdrs;
3314 void *headers_c, *headers_v, *action, *vals_p;
3315 struct mlx5e_tc_mod_hdr_acts *mod_acts;
3316 void *s_masks_p, *a_masks_p;
3317 int i, first, last, next_z;
3318 struct mlx5_fields *f;
3319 unsigned long mask;
3320 u32 s_mask, a_mask;
3321 u8 cmd;
3322
3323 mod_acts = &parse_attr->mod_hdr_acts;
3324 headers_c = mlx5e_get_match_headers_criteria(*action_flags, &parse_attr->spec);
3325 headers_v = mlx5e_get_match_headers_value(*action_flags, &parse_attr->spec);
3326
3327 set_masks = &hdrs[TCA_PEDIT_KEY_EX_CMD_SET].masks;
3328 add_masks = &hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].masks;
3329 set_vals = &hdrs[TCA_PEDIT_KEY_EX_CMD_SET].vals;
3330 add_vals = &hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].vals;
3331
3332 for (i = 0; i < ARRAY_SIZE(fields); i++) {
3333 bool skip;
3334
3335 f = &fields[i];
3336 s_masks_p = (void *)set_masks + f->offset;
3337 a_masks_p = (void *)add_masks + f->offset;
3338
3339 s_mask = mask_field_get(s_masks_p, f);
3340 a_mask = mask_field_get(a_masks_p, f);
3341
3342 if (!s_mask && !a_mask) /* nothing to offload here */
3343 continue;
3344
3345 if (s_mask && a_mask) {
3346 NL_SET_ERR_MSG_MOD(extack,
3347 "can't set and add to the same HW field");
3348 netdev_warn(priv->netdev,
3349 "mlx5: can't set and add to the same HW field (%x)\n",
3350 f->field);
3351 return -EOPNOTSUPP;
3352 }
3353
3354 skip = false;
3355 if (s_mask) {
3356 void *match_mask = headers_c + f->match_offset;
3357 void *match_val = headers_v + f->match_offset;
3358
3359 cmd = MLX5_ACTION_TYPE_SET;
3360 mask = s_mask;
3361 vals_p = (void *)set_vals + f->offset;
3362 /* don't rewrite if we have a match on the same value */
3363 if (cmp_val_mask(vals_p, s_masks_p, match_val,
3364 match_mask, f->field_bsize))
3365 skip = true;
3366 /* clear to denote we consumed this field */
3367 mask_field_clear(s_masks_p, f);
3368 } else {
3369 cmd = MLX5_ACTION_TYPE_ADD;
3370 mask = a_mask;
3371 vals_p = (void *)add_vals + f->offset;
3372 /* add 0 is no change */
3373 if (!mask_field_get(vals_p, f))
3374 skip = true;
3375 /* clear to denote we consumed this field */
3376 mask_field_clear(a_masks_p, f);
3377 }
3378 if (skip)
3379 continue;
3380
3381 first = find_first_bit(&mask, f->field_bsize);
3382 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
3383 last = find_last_bit(&mask, f->field_bsize);
3384 if (first < next_z && next_z < last) {
3385 NL_SET_ERR_MSG_MOD(extack,
3386 "rewrite of few sub-fields isn't supported");
3387 netdev_warn(priv->netdev,
3388 "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
3389 mask);
3390 return -EOPNOTSUPP;
3391 }
3392
3393 action = mlx5e_mod_hdr_alloc(priv->mdev, namespace, mod_acts);
3394 if (IS_ERR(action)) {
3395 NL_SET_ERR_MSG_MOD(extack,
3396 "too many pedit actions, can't offload");
3397 mlx5_core_warn(priv->mdev,
3398 "mlx5: parsed %d pedit actions, can't do more\n",
3399 mod_acts->num_actions);
3400 return PTR_ERR(action);
3401 }
3402
3403 MLX5_SET(set_action_in, action, action_type, cmd);
3404 MLX5_SET(set_action_in, action, field, f->field);
3405
3406 if (cmd == MLX5_ACTION_TYPE_SET) {
3407 unsigned long field_mask = f->field_mask;
3408 int start;
3409
3410 /* if field is bit sized it can start not from first bit */
3411 start = find_first_bit(&field_mask, f->field_bsize);
3412
3413 MLX5_SET(set_action_in, action, offset, first - start);
3414 /* length is num of bits to be written, zero means length of 32 */
3415 MLX5_SET(set_action_in, action, length, (last - first + 1));
3416 }
3417
3418 if (f->field_bsize == 32)
3419 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
3420 else if (f->field_bsize == 16)
3421 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
3422 else if (f->field_bsize == 8)
3423 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
3424
3425 ++mod_acts->num_actions;
3426 }
3427
3428 return 0;
3429 }
3430
3431 static const struct pedit_headers zero_masks = {};
3432
verify_offload_pedit_fields(struct mlx5e_priv * priv,struct mlx5e_tc_flow_parse_attr * parse_attr,struct netlink_ext_ack * extack)3433 static int verify_offload_pedit_fields(struct mlx5e_priv *priv,
3434 struct mlx5e_tc_flow_parse_attr *parse_attr,
3435 struct netlink_ext_ack *extack)
3436 {
3437 struct pedit_headers *cmd_masks;
3438 u8 cmd;
3439
3440 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
3441 cmd_masks = &parse_attr->hdrs[cmd].masks;
3442 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
3443 NL_SET_ERR_MSG_MOD(extack, "attempt to offload an unsupported field");
3444 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
3445 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
3446 16, 1, cmd_masks, sizeof(zero_masks), true);
3447 return -EOPNOTSUPP;
3448 }
3449 }
3450
3451 return 0;
3452 }
3453
alloc_tc_pedit_action(struct mlx5e_priv * priv,int namespace,struct mlx5e_tc_flow_parse_attr * parse_attr,u32 * action_flags,struct netlink_ext_ack * extack)3454 static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
3455 struct mlx5e_tc_flow_parse_attr *parse_attr,
3456 u32 *action_flags,
3457 struct netlink_ext_ack *extack)
3458 {
3459 int err;
3460
3461 err = offload_pedit_fields(priv, namespace, parse_attr, action_flags, extack);
3462 if (err)
3463 goto out_dealloc_parsed_actions;
3464
3465 err = verify_offload_pedit_fields(priv, parse_attr, extack);
3466 if (err)
3467 goto out_dealloc_parsed_actions;
3468
3469 return 0;
3470
3471 out_dealloc_parsed_actions:
3472 mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
3473 return err;
3474 }
3475
3476 struct ip_ttl_word {
3477 __u8 ttl;
3478 __u8 protocol;
3479 __sum16 check;
3480 };
3481
3482 struct ipv6_hoplimit_word {
3483 __be16 payload_len;
3484 __u8 nexthdr;
3485 __u8 hop_limit;
3486 };
3487
3488 static bool
is_flow_action_modify_ip_header(struct flow_action * flow_action)3489 is_flow_action_modify_ip_header(struct flow_action *flow_action)
3490 {
3491 const struct flow_action_entry *act;
3492 u32 mask, offset;
3493 u8 htype;
3494 int i;
3495
3496 /* For IPv4 & IPv6 header check 4 byte word,
3497 * to determine that modified fields
3498 * are NOT ttl & hop_limit only.
3499 */
3500 flow_action_for_each(i, act, flow_action) {
3501 if (act->id != FLOW_ACTION_MANGLE &&
3502 act->id != FLOW_ACTION_ADD)
3503 continue;
3504
3505 htype = act->mangle.htype;
3506 offset = act->mangle.offset;
3507 mask = ~act->mangle.mask;
3508
3509 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3510 struct ip_ttl_word *ttl_word =
3511 (struct ip_ttl_word *)&mask;
3512
3513 if (offset != offsetof(struct iphdr, ttl) ||
3514 ttl_word->protocol ||
3515 ttl_word->check)
3516 return true;
3517 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3518 struct ipv6_hoplimit_word *hoplimit_word =
3519 (struct ipv6_hoplimit_word *)&mask;
3520
3521 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3522 hoplimit_word->payload_len ||
3523 hoplimit_word->nexthdr)
3524 return true;
3525 }
3526 }
3527
3528 return false;
3529 }
3530
modify_header_match_supported(struct mlx5e_priv * priv,struct mlx5_flow_spec * spec,struct flow_action * flow_action,u32 actions,struct netlink_ext_ack * extack)3531 static bool modify_header_match_supported(struct mlx5e_priv *priv,
3532 struct mlx5_flow_spec *spec,
3533 struct flow_action *flow_action,
3534 u32 actions,
3535 struct netlink_ext_ack *extack)
3536 {
3537 bool modify_ip_header;
3538 void *headers_c;
3539 void *headers_v;
3540 u16 ethertype;
3541 u8 ip_proto;
3542
3543 headers_c = mlx5e_get_match_headers_criteria(actions, spec);
3544 headers_v = mlx5e_get_match_headers_value(actions, spec);
3545 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3546
3547 /* for non-IP we only re-write MACs, so we're okay */
3548 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3549 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
3550 goto out_ok;
3551
3552 modify_ip_header = is_flow_action_modify_ip_header(flow_action);
3553 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
3554 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3555 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
3556 NL_SET_ERR_MSG_MOD(extack,
3557 "can't offload re-write of non TCP/UDP");
3558 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3559 ip_proto);
3560 return false;
3561 }
3562
3563 out_ok:
3564 return true;
3565 }
3566
3567 static bool
actions_match_supported_fdb(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct netlink_ext_ack * extack)3568 actions_match_supported_fdb(struct mlx5e_priv *priv,
3569 struct mlx5e_tc_flow *flow,
3570 struct netlink_ext_ack *extack)
3571 {
3572 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
3573
3574 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3575 NL_SET_ERR_MSG_MOD(extack,
3576 "current firmware doesn't support split rule for port mirroring");
3577 netdev_warn_once(priv->netdev,
3578 "current firmware doesn't support split rule for port mirroring\n");
3579 return false;
3580 }
3581
3582 return true;
3583 }
3584
3585 static bool
actions_match_supported(struct mlx5e_priv * priv,struct flow_action * flow_action,u32 actions,struct mlx5e_tc_flow_parse_attr * parse_attr,struct mlx5e_tc_flow * flow,struct netlink_ext_ack * extack)3586 actions_match_supported(struct mlx5e_priv *priv,
3587 struct flow_action *flow_action,
3588 u32 actions,
3589 struct mlx5e_tc_flow_parse_attr *parse_attr,
3590 struct mlx5e_tc_flow *flow,
3591 struct netlink_ext_ack *extack)
3592 {
3593 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
3594 !modify_header_match_supported(priv, &parse_attr->spec, flow_action, actions,
3595 extack))
3596 return false;
3597
3598 if (mlx5e_is_eswitch_flow(flow) &&
3599 !actions_match_supported_fdb(priv, flow, extack))
3600 return false;
3601
3602 return true;
3603 }
3604
same_port_devs(struct mlx5e_priv * priv,struct mlx5e_priv * peer_priv)3605 static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3606 {
3607 return priv->mdev == peer_priv->mdev;
3608 }
3609
mlx5e_same_hw_devs(struct mlx5e_priv * priv,struct mlx5e_priv * peer_priv)3610 bool mlx5e_same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3611 {
3612 struct mlx5_core_dev *fmdev, *pmdev;
3613 u64 fsystem_guid, psystem_guid;
3614
3615 fmdev = priv->mdev;
3616 pmdev = peer_priv->mdev;
3617
3618 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3619 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
3620
3621 return (fsystem_guid == psystem_guid);
3622 }
3623
3624 static int
actions_prepare_mod_hdr_actions(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr,struct netlink_ext_ack * extack)3625 actions_prepare_mod_hdr_actions(struct mlx5e_priv *priv,
3626 struct mlx5e_tc_flow *flow,
3627 struct mlx5_flow_attr *attr,
3628 struct netlink_ext_ack *extack)
3629 {
3630 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3631 struct pedit_headers_action *hdrs = parse_attr->hdrs;
3632 enum mlx5_flow_namespace_type ns_type;
3633 int err;
3634
3635 if (!hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits &&
3636 !hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits)
3637 return 0;
3638
3639 ns_type = mlx5e_get_flow_namespace(flow);
3640
3641 err = alloc_tc_pedit_action(priv, ns_type, parse_attr, &attr->action, extack);
3642 if (err)
3643 return err;
3644
3645 if (parse_attr->mod_hdr_acts.num_actions > 0)
3646 return 0;
3647
3648 /* In case all pedit actions are skipped, remove the MOD_HDR flag. */
3649 attr->action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3650 mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
3651
3652 if (ns_type != MLX5_FLOW_NAMESPACE_FDB)
3653 return 0;
3654
3655 if (!((attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3656 (attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3657 attr->esw_attr->split_count = 0;
3658
3659 return 0;
3660 }
3661
3662 static struct mlx5_flow_attr*
mlx5e_clone_flow_attr_for_post_act(struct mlx5_flow_attr * attr,enum mlx5_flow_namespace_type ns_type)3663 mlx5e_clone_flow_attr_for_post_act(struct mlx5_flow_attr *attr,
3664 enum mlx5_flow_namespace_type ns_type)
3665 {
3666 struct mlx5e_tc_flow_parse_attr *parse_attr;
3667 u32 attr_sz = ns_to_attr_sz(ns_type);
3668 struct mlx5_flow_attr *attr2;
3669
3670 attr2 = mlx5_alloc_flow_attr(ns_type);
3671 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
3672 if (!attr2 || !parse_attr) {
3673 kvfree(parse_attr);
3674 kfree(attr2);
3675 return NULL;
3676 }
3677
3678 memcpy(attr2, attr, attr_sz);
3679 INIT_LIST_HEAD(&attr2->list);
3680 parse_attr->filter_dev = attr->parse_attr->filter_dev;
3681 attr2->action = 0;
3682 attr2->counter = NULL;
3683 attr2->tc_act_cookies_count = 0;
3684 attr2->flags = 0;
3685 attr2->parse_attr = parse_attr;
3686 attr2->dest_chain = 0;
3687 attr2->dest_ft = NULL;
3688 attr2->act_id_restore_rule = NULL;
3689 memset(&attr2->ct_attr, 0, sizeof(attr2->ct_attr));
3690
3691 if (ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3692 attr2->esw_attr->out_count = 0;
3693 attr2->esw_attr->split_count = 0;
3694 }
3695
3696 attr2->branch_true = NULL;
3697 attr2->branch_false = NULL;
3698 attr2->jumping_attr = NULL;
3699 return attr2;
3700 }
3701
3702 struct mlx5_flow_attr *
mlx5e_tc_get_encap_attr(struct mlx5e_tc_flow * flow)3703 mlx5e_tc_get_encap_attr(struct mlx5e_tc_flow *flow)
3704 {
3705 struct mlx5_esw_flow_attr *esw_attr;
3706 struct mlx5_flow_attr *attr;
3707 int i;
3708
3709 list_for_each_entry(attr, &flow->attrs, list) {
3710 esw_attr = attr->esw_attr;
3711 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
3712 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP)
3713 return attr;
3714 }
3715 }
3716
3717 return NULL;
3718 }
3719
3720 void
mlx5e_tc_unoffload_flow_post_acts(struct mlx5e_tc_flow * flow)3721 mlx5e_tc_unoffload_flow_post_acts(struct mlx5e_tc_flow *flow)
3722 {
3723 struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3724 struct mlx5_flow_attr *attr;
3725
3726 list_for_each_entry(attr, &flow->attrs, list) {
3727 if (list_is_last(&attr->list, &flow->attrs))
3728 break;
3729
3730 mlx5e_tc_post_act_unoffload(post_act, attr->post_act_handle);
3731 }
3732 }
3733
3734 static void
free_flow_post_acts(struct mlx5e_tc_flow * flow)3735 free_flow_post_acts(struct mlx5e_tc_flow *flow)
3736 {
3737 struct mlx5_flow_attr *attr, *tmp;
3738
3739 list_for_each_entry_safe(attr, tmp, &flow->attrs, list) {
3740 if (list_is_last(&attr->list, &flow->attrs))
3741 break;
3742
3743 mlx5_free_flow_attr_actions(flow, attr);
3744
3745 list_del(&attr->list);
3746 kvfree(attr->parse_attr);
3747 kfree(attr);
3748 }
3749 }
3750
3751 int
mlx5e_tc_offload_flow_post_acts(struct mlx5e_tc_flow * flow)3752 mlx5e_tc_offload_flow_post_acts(struct mlx5e_tc_flow *flow)
3753 {
3754 struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3755 struct mlx5_flow_attr *attr;
3756 int err = 0;
3757
3758 list_for_each_entry(attr, &flow->attrs, list) {
3759 if (list_is_last(&attr->list, &flow->attrs))
3760 break;
3761
3762 err = mlx5e_tc_post_act_offload(post_act, attr->post_act_handle);
3763 if (err)
3764 break;
3765 }
3766
3767 return err;
3768 }
3769
3770 /* TC filter rule HW translation:
3771 *
3772 * +---------------------+
3773 * + ft prio (tc chain) +
3774 * + original match +
3775 * +---------------------+
3776 * |
3777 * | if multi table action
3778 * |
3779 * v
3780 * +---------------------+
3781 * + post act ft |<----.
3782 * + match fte id | | split on multi table action
3783 * + do actions |-----'
3784 * +---------------------+
3785 * |
3786 * |
3787 * v
3788 * Do rest of the actions after last multi table action.
3789 */
3790 static int
alloc_flow_post_acts(struct mlx5e_tc_flow * flow,struct netlink_ext_ack * extack)3791 alloc_flow_post_acts(struct mlx5e_tc_flow *flow, struct netlink_ext_ack *extack)
3792 {
3793 struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3794 struct mlx5_flow_attr *attr, *next_attr = NULL;
3795 struct mlx5e_post_act_handle *handle;
3796 int err;
3797
3798 /* This is going in reverse order as needed.
3799 * The first entry is the last attribute.
3800 */
3801 list_for_each_entry(attr, &flow->attrs, list) {
3802 if (!next_attr) {
3803 /* Set counter action on last post act rule. */
3804 attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3805 }
3806
3807 if (next_attr && !(attr->flags & MLX5_ATTR_FLAG_TERMINATING)) {
3808 err = mlx5e_tc_act_set_next_post_act(flow, attr, next_attr);
3809 if (err)
3810 goto out_free;
3811 }
3812
3813 /* Don't add post_act rule for first attr (last in the list).
3814 * It's being handled by the caller.
3815 */
3816 if (list_is_last(&attr->list, &flow->attrs))
3817 break;
3818
3819 err = actions_prepare_mod_hdr_actions(flow->priv, flow, attr, extack);
3820 if (err)
3821 goto out_free;
3822
3823 err = post_process_attr(flow, attr, extack);
3824 if (err)
3825 goto out_free;
3826
3827 handle = mlx5e_tc_post_act_add(post_act, attr);
3828 if (IS_ERR(handle)) {
3829 err = PTR_ERR(handle);
3830 goto out_free;
3831 }
3832
3833 attr->post_act_handle = handle;
3834
3835 if (attr->jumping_attr) {
3836 err = mlx5e_tc_act_set_next_post_act(flow, attr->jumping_attr, attr);
3837 if (err)
3838 goto out_free;
3839 }
3840
3841 next_attr = attr;
3842 }
3843
3844 if (flow_flag_test(flow, SLOW))
3845 goto out;
3846
3847 err = mlx5e_tc_offload_flow_post_acts(flow);
3848 if (err)
3849 goto out_free;
3850
3851 out:
3852 return 0;
3853
3854 out_free:
3855 free_flow_post_acts(flow);
3856 return err;
3857 }
3858
3859 static int
set_branch_dest_ft(struct mlx5e_priv * priv,struct mlx5_flow_attr * attr)3860 set_branch_dest_ft(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr)
3861 {
3862 struct mlx5e_post_act *post_act = get_post_action(priv);
3863
3864 if (IS_ERR(post_act))
3865 return PTR_ERR(post_act);
3866
3867 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3868 attr->dest_ft = mlx5e_tc_post_act_get_ft(post_act);
3869
3870 return 0;
3871 }
3872
3873 static int
alloc_branch_attr(struct mlx5e_tc_flow * flow,struct mlx5e_tc_act_branch_ctrl * cond,struct mlx5_flow_attr ** cond_attr,u32 * jump_count,struct netlink_ext_ack * extack)3874 alloc_branch_attr(struct mlx5e_tc_flow *flow,
3875 struct mlx5e_tc_act_branch_ctrl *cond,
3876 struct mlx5_flow_attr **cond_attr,
3877 u32 *jump_count,
3878 struct netlink_ext_ack *extack)
3879 {
3880 struct mlx5_flow_attr *attr;
3881 int err = 0;
3882
3883 *cond_attr = mlx5e_clone_flow_attr_for_post_act(flow->attr,
3884 mlx5e_get_flow_namespace(flow));
3885 if (!(*cond_attr))
3886 return -ENOMEM;
3887
3888 attr = *cond_attr;
3889
3890 switch (cond->act_id) {
3891 case FLOW_ACTION_DROP:
3892 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
3893 break;
3894 case FLOW_ACTION_ACCEPT:
3895 case FLOW_ACTION_PIPE:
3896 err = set_branch_dest_ft(flow->priv, attr);
3897 if (err)
3898 goto out_err;
3899 break;
3900 case FLOW_ACTION_JUMP:
3901 if (*jump_count) {
3902 NL_SET_ERR_MSG_MOD(extack, "Cannot offload flows with nested jumps");
3903 err = -EOPNOTSUPP;
3904 goto out_err;
3905 }
3906 *jump_count = cond->extval;
3907 err = set_branch_dest_ft(flow->priv, attr);
3908 if (err)
3909 goto out_err;
3910 break;
3911 default:
3912 err = -EOPNOTSUPP;
3913 goto out_err;
3914 }
3915
3916 return err;
3917 out_err:
3918 kfree(*cond_attr);
3919 *cond_attr = NULL;
3920 return err;
3921 }
3922
3923 static void
dec_jump_count(struct flow_action_entry * act,struct mlx5e_tc_act * tc_act,struct mlx5_flow_attr * attr,struct mlx5e_priv * priv,struct mlx5e_tc_jump_state * jump_state)3924 dec_jump_count(struct flow_action_entry *act, struct mlx5e_tc_act *tc_act,
3925 struct mlx5_flow_attr *attr, struct mlx5e_priv *priv,
3926 struct mlx5e_tc_jump_state *jump_state)
3927 {
3928 if (!jump_state->jump_count)
3929 return;
3930
3931 /* Single tc action can instantiate multiple offload actions (e.g. pedit)
3932 * Jump only over a tc action
3933 */
3934 if (act->id == jump_state->last_id && act->hw_index == jump_state->last_index)
3935 return;
3936
3937 jump_state->last_id = act->id;
3938 jump_state->last_index = act->hw_index;
3939
3940 /* nothing to do for intermediate actions */
3941 if (--jump_state->jump_count > 1)
3942 return;
3943
3944 if (jump_state->jump_count == 1) { /* last action in the jump action list */
3945
3946 /* create a new attribute after this action */
3947 jump_state->jump_target = true;
3948
3949 if (tc_act->is_terminating_action) { /* the branch ends here */
3950 attr->flags |= MLX5_ATTR_FLAG_TERMINATING;
3951 attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3952 } else { /* the branch continues executing the rest of the actions */
3953 struct mlx5e_post_act *post_act;
3954
3955 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3956 post_act = get_post_action(priv);
3957 attr->dest_ft = mlx5e_tc_post_act_get_ft(post_act);
3958 }
3959 } else if (jump_state->jump_count == 0) { /* first attr after the jump action list */
3960 /* This is the post action for the jumping attribute (either red or green)
3961 * Use the stored jumping_attr to set the post act id on the jumping attribute
3962 */
3963 attr->jumping_attr = jump_state->jumping_attr;
3964 }
3965 }
3966
3967 static int
parse_branch_ctrl(struct flow_action_entry * act,struct mlx5e_tc_act * tc_act,struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr,struct mlx5e_tc_jump_state * jump_state,struct netlink_ext_ack * extack)3968 parse_branch_ctrl(struct flow_action_entry *act, struct mlx5e_tc_act *tc_act,
3969 struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr,
3970 struct mlx5e_tc_jump_state *jump_state,
3971 struct netlink_ext_ack *extack)
3972 {
3973 struct mlx5e_tc_act_branch_ctrl cond_true, cond_false;
3974 u32 jump_count = jump_state->jump_count;
3975 int err;
3976
3977 if (!tc_act->get_branch_ctrl)
3978 return 0;
3979
3980 tc_act->get_branch_ctrl(act, &cond_true, &cond_false);
3981
3982 err = alloc_branch_attr(flow, &cond_true,
3983 &attr->branch_true, &jump_count, extack);
3984 if (err)
3985 goto out_err;
3986
3987 if (jump_count)
3988 jump_state->jumping_attr = attr->branch_true;
3989
3990 err = alloc_branch_attr(flow, &cond_false,
3991 &attr->branch_false, &jump_count, extack);
3992 if (err)
3993 goto err_branch_false;
3994
3995 if (jump_count && !jump_state->jumping_attr)
3996 jump_state->jumping_attr = attr->branch_false;
3997
3998 jump_state->jump_count = jump_count;
3999
4000 /* branching action requires its own counter */
4001 attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
4002 flow_flag_set(flow, USE_ACT_STATS);
4003
4004 return 0;
4005
4006 err_branch_false:
4007 free_branch_attr(flow, attr->branch_true);
4008 out_err:
4009 return err;
4010 }
4011
4012 static int
parse_tc_actions(struct mlx5e_tc_act_parse_state * parse_state,struct flow_action * flow_action)4013 parse_tc_actions(struct mlx5e_tc_act_parse_state *parse_state,
4014 struct flow_action *flow_action)
4015 {
4016 struct netlink_ext_ack *extack = parse_state->extack;
4017 struct mlx5e_tc_flow *flow = parse_state->flow;
4018 struct mlx5e_tc_jump_state jump_state = {};
4019 struct mlx5_flow_attr *attr = flow->attr;
4020 enum mlx5_flow_namespace_type ns_type;
4021 struct mlx5e_priv *priv = flow->priv;
4022 struct mlx5_flow_attr *prev_attr;
4023 struct flow_action_entry *act;
4024 struct mlx5e_tc_act *tc_act;
4025 int err, i, i_split = 0;
4026 bool is_missable;
4027
4028 ns_type = mlx5e_get_flow_namespace(flow);
4029 list_add(&attr->list, &flow->attrs);
4030
4031 flow_action_for_each(i, act, flow_action) {
4032 jump_state.jump_target = false;
4033 is_missable = false;
4034 prev_attr = attr;
4035
4036 tc_act = mlx5e_tc_act_get(act->id, ns_type);
4037 if (!tc_act) {
4038 NL_SET_ERR_MSG_MOD(extack, "Not implemented offload action");
4039 err = -EOPNOTSUPP;
4040 goto out_free_post_acts;
4041 }
4042
4043 if (tc_act->can_offload && !tc_act->can_offload(parse_state, act, i, attr)) {
4044 err = -EOPNOTSUPP;
4045 goto out_free_post_acts;
4046 }
4047
4048 err = tc_act->parse_action(parse_state, act, priv, attr);
4049 if (err)
4050 goto out_free_post_acts;
4051
4052 dec_jump_count(act, tc_act, attr, priv, &jump_state);
4053
4054 err = parse_branch_ctrl(act, tc_act, flow, attr, &jump_state, extack);
4055 if (err)
4056 goto out_free_post_acts;
4057
4058 parse_state->actions |= attr->action;
4059
4060 /* Split attr for multi table act if not the last act. */
4061 if (jump_state.jump_target ||
4062 (tc_act->is_multi_table_act &&
4063 tc_act->is_multi_table_act(priv, act, attr) &&
4064 i < flow_action->num_entries - 1)) {
4065 is_missable = tc_act->is_missable ? tc_act->is_missable(act) : false;
4066
4067 err = mlx5e_tc_act_post_parse(parse_state, flow_action, i_split, i, attr,
4068 ns_type);
4069 if (err)
4070 goto out_free_post_acts;
4071
4072 attr = mlx5e_clone_flow_attr_for_post_act(flow->attr, ns_type);
4073 if (!attr) {
4074 err = -ENOMEM;
4075 goto out_free_post_acts;
4076 }
4077
4078 i_split = i + 1;
4079 parse_state->if_count = 0;
4080 list_add(&attr->list, &flow->attrs);
4081 }
4082
4083 if (is_missable) {
4084 /* Add counter to prev, and assign act to new (next) attr */
4085 prev_attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
4086 flow_flag_set(flow, USE_ACT_STATS);
4087
4088 attr->tc_act_cookies[attr->tc_act_cookies_count++] = act->cookie;
4089 } else if (!tc_act->stats_action) {
4090 prev_attr->tc_act_cookies[prev_attr->tc_act_cookies_count++] = act->cookie;
4091 }
4092 }
4093
4094 err = mlx5e_tc_act_post_parse(parse_state, flow_action, i_split, i, attr, ns_type);
4095 if (err)
4096 goto out_free_post_acts;
4097
4098 err = alloc_flow_post_acts(flow, extack);
4099 if (err)
4100 goto out_free_post_acts;
4101
4102 return 0;
4103
4104 out_free_post_acts:
4105 free_flow_post_acts(flow);
4106
4107 return err;
4108 }
4109
4110 static int
flow_action_supported(struct flow_action * flow_action,struct netlink_ext_ack * extack)4111 flow_action_supported(struct flow_action *flow_action,
4112 struct netlink_ext_ack *extack)
4113 {
4114 if (!flow_action_has_entries(flow_action)) {
4115 NL_SET_ERR_MSG_MOD(extack, "Flow action doesn't have any entries");
4116 return -EINVAL;
4117 }
4118
4119 if (!flow_action_hw_stats_check(flow_action, extack,
4120 FLOW_ACTION_HW_STATS_DELAYED_BIT)) {
4121 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
4122 return -EOPNOTSUPP;
4123 }
4124
4125 return 0;
4126 }
4127
4128 static int
parse_tc_nic_actions(struct mlx5e_priv * priv,struct flow_action * flow_action,struct mlx5e_tc_flow * flow,struct netlink_ext_ack * extack)4129 parse_tc_nic_actions(struct mlx5e_priv *priv,
4130 struct flow_action *flow_action,
4131 struct mlx5e_tc_flow *flow,
4132 struct netlink_ext_ack *extack)
4133 {
4134 struct mlx5e_tc_act_parse_state *parse_state;
4135 struct mlx5e_tc_flow_parse_attr *parse_attr;
4136 struct mlx5_flow_attr *attr = flow->attr;
4137 int err;
4138
4139 err = flow_action_supported(flow_action, extack);
4140 if (err)
4141 return err;
4142
4143 attr->nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
4144 parse_attr = attr->parse_attr;
4145 parse_state = &parse_attr->parse_state;
4146 mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
4147 parse_state->ct_priv = get_ct_priv(priv);
4148
4149 err = parse_tc_actions(parse_state, flow_action);
4150 if (err)
4151 return err;
4152
4153 err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
4154 if (err)
4155 return err;
4156
4157 err = verify_attr_actions(attr->action, extack);
4158 if (err)
4159 return err;
4160
4161 if (!actions_match_supported(priv, flow_action, parse_state->actions,
4162 parse_attr, flow, extack))
4163 return -EOPNOTSUPP;
4164
4165 return 0;
4166 }
4167
is_merged_eswitch_vfs(struct mlx5e_priv * priv,struct net_device * peer_netdev)4168 static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
4169 struct net_device *peer_netdev)
4170 {
4171 struct mlx5e_priv *peer_priv;
4172
4173 peer_priv = netdev_priv(peer_netdev);
4174
4175 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
4176 mlx5e_eswitch_vf_rep(priv->netdev) &&
4177 mlx5e_eswitch_vf_rep(peer_netdev) &&
4178 mlx5e_same_hw_devs(priv, peer_priv));
4179 }
4180
same_hw_reps(struct mlx5e_priv * priv,struct net_device * peer_netdev)4181 static bool same_hw_reps(struct mlx5e_priv *priv,
4182 struct net_device *peer_netdev)
4183 {
4184 struct mlx5e_priv *peer_priv;
4185
4186 peer_priv = netdev_priv(peer_netdev);
4187
4188 return mlx5e_eswitch_rep(priv->netdev) &&
4189 mlx5e_eswitch_rep(peer_netdev) &&
4190 mlx5e_same_hw_devs(priv, peer_priv);
4191 }
4192
is_lag_dev(struct mlx5e_priv * priv,struct net_device * peer_netdev)4193 static bool is_lag_dev(struct mlx5e_priv *priv,
4194 struct net_device *peer_netdev)
4195 {
4196 return ((mlx5_lag_is_sriov(priv->mdev) ||
4197 mlx5_lag_is_multipath(priv->mdev)) &&
4198 same_hw_reps(priv, peer_netdev));
4199 }
4200
is_multiport_eligible(struct mlx5e_priv * priv,struct net_device * out_dev)4201 static bool is_multiport_eligible(struct mlx5e_priv *priv, struct net_device *out_dev)
4202 {
4203 return same_hw_reps(priv, out_dev) && mlx5_lag_is_mpesw(priv->mdev);
4204 }
4205
mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv * priv,struct net_device * out_dev)4206 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
4207 struct net_device *out_dev)
4208 {
4209 if (is_merged_eswitch_vfs(priv, out_dev))
4210 return true;
4211
4212 if (is_multiport_eligible(priv, out_dev))
4213 return true;
4214
4215 if (is_lag_dev(priv, out_dev))
4216 return true;
4217
4218 return mlx5e_eswitch_rep(out_dev) &&
4219 same_port_devs(priv, netdev_priv(out_dev));
4220 }
4221
mlx5e_set_fwd_to_int_port_actions(struct mlx5e_priv * priv,struct mlx5_flow_attr * attr,int ifindex,enum mlx5e_tc_int_port_type type,u32 * action,int out_index)4222 int mlx5e_set_fwd_to_int_port_actions(struct mlx5e_priv *priv,
4223 struct mlx5_flow_attr *attr,
4224 int ifindex,
4225 enum mlx5e_tc_int_port_type type,
4226 u32 *action,
4227 int out_index)
4228 {
4229 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
4230 struct mlx5e_tc_int_port_priv *int_port_priv;
4231 struct mlx5e_tc_flow_parse_attr *parse_attr;
4232 struct mlx5e_tc_int_port *dest_int_port;
4233 int err;
4234
4235 parse_attr = attr->parse_attr;
4236 int_port_priv = mlx5e_get_int_port_priv(priv);
4237
4238 dest_int_port = mlx5e_tc_int_port_get(int_port_priv, ifindex, type);
4239 if (IS_ERR(dest_int_port))
4240 return PTR_ERR(dest_int_port);
4241
4242 err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
4243 MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
4244 mlx5e_tc_int_port_get_metadata(dest_int_port));
4245 if (err) {
4246 mlx5e_tc_int_port_put(int_port_priv, dest_int_port);
4247 return err;
4248 }
4249
4250 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
4251
4252 esw_attr->dest_int_port = dest_int_port;
4253 esw_attr->dests[out_index].flags |= MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE;
4254 esw_attr->split_count = out_index;
4255
4256 /* Forward to root fdb for matching against the new source vport */
4257 attr->dest_chain = 0;
4258
4259 return 0;
4260 }
4261
4262 static int
parse_tc_fdb_actions(struct mlx5e_priv * priv,struct flow_action * flow_action,struct mlx5e_tc_flow * flow,struct netlink_ext_ack * extack)4263 parse_tc_fdb_actions(struct mlx5e_priv *priv,
4264 struct flow_action *flow_action,
4265 struct mlx5e_tc_flow *flow,
4266 struct netlink_ext_ack *extack)
4267 {
4268 struct mlx5e_tc_act_parse_state *parse_state;
4269 struct mlx5e_tc_flow_parse_attr *parse_attr;
4270 struct mlx5_flow_attr *attr = flow->attr;
4271 struct mlx5_esw_flow_attr *esw_attr;
4272 struct net_device *filter_dev;
4273 int err;
4274
4275 err = flow_action_supported(flow_action, extack);
4276 if (err)
4277 return err;
4278
4279 esw_attr = attr->esw_attr;
4280 parse_attr = attr->parse_attr;
4281 filter_dev = parse_attr->filter_dev;
4282 parse_state = &parse_attr->parse_state;
4283 mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
4284 parse_state->ct_priv = get_ct_priv(priv);
4285
4286 err = parse_tc_actions(parse_state, flow_action);
4287 if (err)
4288 return err;
4289
4290 /* Forward to/from internal port can only have 1 dest */
4291 if ((netif_is_ovs_master(filter_dev) || esw_attr->dest_int_port) &&
4292 esw_attr->out_count > 1) {
4293 NL_SET_ERR_MSG_MOD(extack,
4294 "Rules with internal port can have only one destination");
4295 return -EOPNOTSUPP;
4296 }
4297
4298 /* Forward from tunnel/internal port to internal port is not supported */
4299 if ((mlx5e_get_tc_tun(filter_dev) || netif_is_ovs_master(filter_dev)) &&
4300 esw_attr->dest_int_port) {
4301 NL_SET_ERR_MSG_MOD(extack,
4302 "Forwarding from tunnel/internal port to internal port is not supported");
4303 return -EOPNOTSUPP;
4304 }
4305
4306 err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
4307 if (err)
4308 return err;
4309
4310 if (!actions_match_supported(priv, flow_action, parse_state->actions,
4311 parse_attr, flow, extack))
4312 return -EOPNOTSUPP;
4313
4314 return 0;
4315 }
4316
get_flags(int flags,unsigned long * flow_flags)4317 static void get_flags(int flags, unsigned long *flow_flags)
4318 {
4319 unsigned long __flow_flags = 0;
4320
4321 if (flags & MLX5_TC_FLAG(INGRESS))
4322 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4323 if (flags & MLX5_TC_FLAG(EGRESS))
4324 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
4325
4326 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4327 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4328 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4329 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4330 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4331 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
4332
4333 *flow_flags = __flow_flags;
4334 }
4335
4336 static const struct rhashtable_params tc_ht_params = {
4337 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4338 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4339 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4340 .automatic_shrinking = true,
4341 };
4342
get_tc_ht(struct mlx5e_priv * priv,unsigned long flags)4343 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4344 unsigned long flags)
4345 {
4346 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
4347 struct mlx5e_rep_priv *rpriv;
4348
4349 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
4350 rpriv = priv->ppriv;
4351 return &rpriv->tc_ht;
4352 } else /* NIC offload */
4353 return &tc->ht;
4354 }
4355
is_peer_flow_needed(struct mlx5e_tc_flow * flow)4356 static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4357 {
4358 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4359 struct mlx5_flow_attr *attr = flow->attr;
4360 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
4361 flow_flag_test(flow, INGRESS);
4362 bool act_is_encap = !!(attr->action &
4363 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
4364 bool esw_paired = mlx5_devcom_comp_is_ready(esw_attr->in_mdev->priv.eswitch->devcom);
4365
4366 if (!esw_paired)
4367 return false;
4368
4369 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4370 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
4371 (is_rep_ingress || act_is_encap))
4372 return true;
4373
4374 if (mlx5_lag_is_mpesw(esw_attr->in_mdev))
4375 return true;
4376
4377 return false;
4378 }
4379
4380 struct mlx5_flow_attr *
mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)4381 mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4382 {
4383 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
4384 sizeof(struct mlx5_esw_flow_attr) :
4385 sizeof(struct mlx5_nic_flow_attr);
4386 struct mlx5_flow_attr *attr;
4387
4388 attr = kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4389 if (!attr)
4390 return attr;
4391
4392 INIT_LIST_HEAD(&attr->list);
4393 return attr;
4394 }
4395
4396 static void
mlx5_free_flow_attr_actions(struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr)4397 mlx5_free_flow_attr_actions(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr)
4398 {
4399 struct mlx5_core_dev *counter_dev = get_flow_counter_dev(flow);
4400 struct mlx5_esw_flow_attr *esw_attr;
4401
4402 if (!attr)
4403 return;
4404
4405 if (attr->post_act_handle)
4406 mlx5e_tc_post_act_del(get_post_action(flow->priv), attr->post_act_handle);
4407
4408 mlx5e_tc_tun_encap_dests_unset(flow->priv, flow, attr);
4409
4410 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
4411 mlx5_fc_destroy(counter_dev, attr->counter);
4412
4413 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
4414 mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
4415 mlx5e_tc_detach_mod_hdr(flow->priv, flow, attr);
4416 }
4417
4418 if (mlx5e_is_eswitch_flow(flow)) {
4419 esw_attr = attr->esw_attr;
4420
4421 if (esw_attr->int_port)
4422 mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(flow->priv),
4423 esw_attr->int_port);
4424
4425 if (esw_attr->dest_int_port)
4426 mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(flow->priv),
4427 esw_attr->dest_int_port);
4428 }
4429
4430 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), attr);
4431
4432 free_branch_attr(flow, attr->branch_true);
4433 free_branch_attr(flow, attr->branch_false);
4434 }
4435
4436 static int
mlx5e_alloc_flow(struct mlx5e_priv * priv,int attr_size,struct flow_cls_offload * f,unsigned long flow_flags,struct mlx5e_tc_flow_parse_attr ** __parse_attr,struct mlx5e_tc_flow ** __flow)4437 mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
4438 struct flow_cls_offload *f, unsigned long flow_flags,
4439 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4440 struct mlx5e_tc_flow **__flow)
4441 {
4442 struct mlx5e_tc_flow_parse_attr *parse_attr;
4443 struct mlx5_flow_attr *attr;
4444 struct mlx5e_tc_flow *flow;
4445 int err = -ENOMEM;
4446 int out_index;
4447
4448 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
4449 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
4450 if (!parse_attr || !flow)
4451 goto err_free;
4452
4453 flow->flags = flow_flags;
4454 flow->cookie = f->cookie;
4455 flow->priv = priv;
4456
4457 attr = mlx5_alloc_flow_attr(mlx5e_get_flow_namespace(flow));
4458 if (!attr)
4459 goto err_free;
4460
4461 flow->attr = attr;
4462
4463 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4464 INIT_LIST_HEAD(&flow->encaps[out_index].list);
4465 INIT_LIST_HEAD(&flow->hairpin);
4466 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
4467 INIT_LIST_HEAD(&flow->attrs);
4468 INIT_LIST_HEAD(&flow->peer_flows);
4469 refcount_set(&flow->refcnt, 1);
4470 init_completion(&flow->init_done);
4471 init_completion(&flow->del_hw_done);
4472
4473 *__flow = flow;
4474 *__parse_attr = parse_attr;
4475
4476 return 0;
4477
4478 err_free:
4479 kfree(flow);
4480 kvfree(parse_attr);
4481 return err;
4482 }
4483
4484 static void
mlx5e_flow_attr_init(struct mlx5_flow_attr * attr,struct mlx5e_tc_flow_parse_attr * parse_attr,struct flow_cls_offload * f)4485 mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4486 struct mlx5e_tc_flow_parse_attr *parse_attr,
4487 struct flow_cls_offload *f)
4488 {
4489 attr->parse_attr = parse_attr;
4490 attr->chain = f->common.chain_index;
4491 attr->prio = f->common.prio;
4492 }
4493
4494 static void
mlx5e_flow_esw_attr_init(struct mlx5_flow_attr * attr,struct mlx5e_priv * priv,struct mlx5e_tc_flow_parse_attr * parse_attr,struct flow_cls_offload * f,struct mlx5_eswitch_rep * in_rep,struct mlx5_core_dev * in_mdev)4495 mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
4496 struct mlx5e_priv *priv,
4497 struct mlx5e_tc_flow_parse_attr *parse_attr,
4498 struct flow_cls_offload *f,
4499 struct mlx5_eswitch_rep *in_rep,
4500 struct mlx5_core_dev *in_mdev)
4501 {
4502 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4503 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
4504
4505 mlx5e_flow_attr_init(attr, parse_attr, f);
4506
4507 esw_attr->in_rep = in_rep;
4508 esw_attr->in_mdev = in_mdev;
4509
4510 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4511 MLX5_COUNTER_SOURCE_ESWITCH)
4512 esw_attr->counter_dev = in_mdev;
4513 else
4514 esw_attr->counter_dev = priv->mdev;
4515 }
4516
4517 static struct mlx5e_tc_flow *
__mlx5e_add_fdb_flow(struct mlx5e_priv * priv,struct flow_cls_offload * f,unsigned long flow_flags,struct net_device * filter_dev,struct mlx5_eswitch_rep * in_rep,struct mlx5_core_dev * in_mdev)4518 __mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4519 struct flow_cls_offload *f,
4520 unsigned long flow_flags,
4521 struct net_device *filter_dev,
4522 struct mlx5_eswitch_rep *in_rep,
4523 struct mlx5_core_dev *in_mdev)
4524 {
4525 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4526 struct netlink_ext_ack *extack = f->common.extack;
4527 struct mlx5e_tc_flow_parse_attr *parse_attr;
4528 struct mlx5e_tc_flow *flow;
4529 int attr_size, err;
4530
4531 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4532 attr_size = sizeof(struct mlx5_esw_flow_attr);
4533 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4534 &parse_attr, &flow);
4535 if (err)
4536 goto out;
4537
4538 parse_attr->filter_dev = filter_dev;
4539 mlx5e_flow_esw_attr_init(flow->attr,
4540 priv, parse_attr,
4541 f, in_rep, in_mdev);
4542
4543 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4544 f, filter_dev);
4545 if (err)
4546 goto err_free;
4547
4548 /* actions validation depends on parsing the ct matches first */
4549 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4550 &flow->attr->ct_attr, extack);
4551 if (err)
4552 goto err_free;
4553
4554 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4555 if (err)
4556 goto err_free;
4557
4558 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
4559 complete_all(&flow->init_done);
4560 if (err) {
4561 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4562 goto err_free;
4563
4564 add_unready_flow(flow);
4565 }
4566
4567 return flow;
4568
4569 err_free:
4570 mlx5e_flow_put(priv, flow);
4571 out:
4572 return ERR_PTR(err);
4573 }
4574
mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload * f,struct mlx5e_tc_flow * flow,unsigned long flow_flags,struct mlx5_eswitch * peer_esw)4575 static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
4576 struct mlx5e_tc_flow *flow,
4577 unsigned long flow_flags,
4578 struct mlx5_eswitch *peer_esw)
4579 {
4580 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4581 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4582 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
4583 struct mlx5e_tc_flow_parse_attr *parse_attr;
4584 int i = mlx5_get_dev_index(peer_esw->dev);
4585 struct mlx5e_rep_priv *peer_urpriv;
4586 struct mlx5e_tc_flow *peer_flow;
4587 struct mlx5_core_dev *in_mdev;
4588 int err = 0;
4589
4590 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4591 peer_priv = netdev_priv(peer_urpriv->netdev);
4592
4593 /* in_mdev is assigned of which the packet originated from.
4594 * So packets redirected to uplink use the same mdev of the
4595 * original flow and packets redirected from uplink use the
4596 * peer mdev.
4597 * In multiport eswitch it's a special case that we need to
4598 * keep the original mdev.
4599 */
4600 if (attr->in_rep->vport == MLX5_VPORT_UPLINK && !mlx5_lag_is_mpesw(priv->mdev))
4601 in_mdev = peer_priv->mdev;
4602 else
4603 in_mdev = priv->mdev;
4604
4605 parse_attr = flow->attr->parse_attr;
4606 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
4607 parse_attr->filter_dev,
4608 attr->in_rep, in_mdev);
4609 if (IS_ERR(peer_flow)) {
4610 err = PTR_ERR(peer_flow);
4611 goto out;
4612 }
4613
4614 list_add_tail(&peer_flow->peer_flows, &flow->peer_flows);
4615 flow_flag_set(flow, DUP);
4616 mutex_lock(&esw->offloads.peer_mutex);
4617 list_add_tail(&flow->peer[i], &esw->offloads.peer_flows[i]);
4618 mutex_unlock(&esw->offloads.peer_mutex);
4619
4620 out:
4621 return err;
4622 }
4623
4624 static int
mlx5e_add_fdb_flow(struct mlx5e_priv * priv,struct flow_cls_offload * f,unsigned long flow_flags,struct net_device * filter_dev,struct mlx5e_tc_flow ** __flow)4625 mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4626 struct flow_cls_offload *f,
4627 unsigned long flow_flags,
4628 struct net_device *filter_dev,
4629 struct mlx5e_tc_flow **__flow)
4630 {
4631 struct mlx5_devcom_comp_dev *devcom = priv->mdev->priv.eswitch->devcom, *pos;
4632 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4633 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4634 struct mlx5_core_dev *in_mdev = priv->mdev;
4635 struct mlx5_eswitch *peer_esw;
4636 struct mlx5e_tc_flow *flow;
4637 int err;
4638
4639 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4640 in_mdev);
4641 if (IS_ERR(flow))
4642 return PTR_ERR(flow);
4643
4644 if (!is_peer_flow_needed(flow)) {
4645 *__flow = flow;
4646 return 0;
4647 }
4648
4649 if (!mlx5_devcom_for_each_peer_begin(devcom)) {
4650 err = -ENODEV;
4651 goto clean_flow;
4652 }
4653
4654 mlx5_devcom_for_each_peer_entry(devcom, peer_esw, pos) {
4655 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags, peer_esw);
4656 if (err)
4657 goto peer_clean;
4658 }
4659
4660 mlx5_devcom_for_each_peer_end(devcom);
4661
4662 *__flow = flow;
4663 return 0;
4664
4665 peer_clean:
4666 mlx5e_tc_del_fdb_peers_flow(flow);
4667 mlx5_devcom_for_each_peer_end(devcom);
4668 clean_flow:
4669 mlx5e_tc_del_fdb_flow(priv, flow);
4670 return err;
4671 }
4672
4673 static int
mlx5e_add_nic_flow(struct mlx5e_priv * priv,struct flow_cls_offload * f,unsigned long flow_flags,struct net_device * filter_dev,struct mlx5e_tc_flow ** __flow)4674 mlx5e_add_nic_flow(struct mlx5e_priv *priv,
4675 struct flow_cls_offload *f,
4676 unsigned long flow_flags,
4677 struct net_device *filter_dev,
4678 struct mlx5e_tc_flow **__flow)
4679 {
4680 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4681 struct netlink_ext_ack *extack = f->common.extack;
4682 struct mlx5e_tc_flow_parse_attr *parse_attr;
4683 struct mlx5e_tc_flow *flow;
4684 int attr_size, err;
4685
4686 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4687 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4688 return -EOPNOTSUPP;
4689 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
4690 return -EOPNOTSUPP;
4691 }
4692
4693 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4694 attr_size = sizeof(struct mlx5_nic_flow_attr);
4695 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4696 &parse_attr, &flow);
4697 if (err)
4698 goto out;
4699
4700 parse_attr->filter_dev = filter_dev;
4701 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4702
4703 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4704 f, filter_dev);
4705 if (err)
4706 goto err_free;
4707
4708 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4709 &flow->attr->ct_attr, extack);
4710 if (err)
4711 goto err_free;
4712
4713 err = parse_tc_nic_actions(priv, &rule->action, flow, extack);
4714 if (err)
4715 goto err_free;
4716
4717 err = mlx5e_tc_add_nic_flow(priv, flow, extack);
4718 if (err)
4719 goto err_free;
4720
4721 flow_flag_set(flow, OFFLOADED);
4722 *__flow = flow;
4723
4724 return 0;
4725
4726 err_free:
4727 flow_flag_set(flow, FAILED);
4728 mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
4729 mlx5e_flow_put(priv, flow);
4730 out:
4731 return err;
4732 }
4733
4734 static int
mlx5e_tc_add_flow(struct mlx5e_priv * priv,struct flow_cls_offload * f,unsigned long flags,struct net_device * filter_dev,struct mlx5e_tc_flow ** flow)4735 mlx5e_tc_add_flow(struct mlx5e_priv *priv,
4736 struct flow_cls_offload *f,
4737 unsigned long flags,
4738 struct net_device *filter_dev,
4739 struct mlx5e_tc_flow **flow)
4740 {
4741 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4742 unsigned long flow_flags;
4743 int err;
4744
4745 get_flags(flags, &flow_flags);
4746
4747 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4748 return -EOPNOTSUPP;
4749
4750 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
4751 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4752 filter_dev, flow);
4753 else
4754 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4755 filter_dev, flow);
4756
4757 return err;
4758 }
4759
is_flow_rule_duplicate_allowed(struct net_device * dev,struct mlx5e_rep_priv * rpriv)4760 static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4761 struct mlx5e_rep_priv *rpriv)
4762 {
4763 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
4764 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4765 * function is called from NIC mode.
4766 */
4767 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
4768 }
4769
4770 /* As IPsec and TC order is not aligned between software and hardware-offload,
4771 * either IPsec offload or TC offload, not both, is allowed for a specific interface.
4772 */
is_tc_ipsec_order_check_needed(struct net_device * filter,struct mlx5e_priv * priv)4773 static bool is_tc_ipsec_order_check_needed(struct net_device *filter, struct mlx5e_priv *priv)
4774 {
4775 if (!IS_ENABLED(CONFIG_MLX5_EN_IPSEC))
4776 return false;
4777
4778 if (filter != priv->netdev)
4779 return false;
4780
4781 if (mlx5e_eswitch_vf_rep(priv->netdev))
4782 return false;
4783
4784 return true;
4785 }
4786
mlx5e_tc_block_ipsec_offload(struct net_device * filter,struct mlx5e_priv * priv)4787 static int mlx5e_tc_block_ipsec_offload(struct net_device *filter, struct mlx5e_priv *priv)
4788 {
4789 struct mlx5_core_dev *mdev = priv->mdev;
4790
4791 if (!is_tc_ipsec_order_check_needed(filter, priv))
4792 return 0;
4793
4794 if (mdev->num_block_tc)
4795 return -EBUSY;
4796
4797 mdev->num_block_ipsec++;
4798
4799 return 0;
4800 }
4801
mlx5e_tc_unblock_ipsec_offload(struct net_device * filter,struct mlx5e_priv * priv)4802 static void mlx5e_tc_unblock_ipsec_offload(struct net_device *filter, struct mlx5e_priv *priv)
4803 {
4804 if (!is_tc_ipsec_order_check_needed(filter, priv))
4805 return;
4806
4807 priv->mdev->num_block_ipsec--;
4808 }
4809
mlx5e_configure_flower(struct net_device * dev,struct mlx5e_priv * priv,struct flow_cls_offload * f,unsigned long flags)4810 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
4811 struct flow_cls_offload *f, unsigned long flags)
4812 {
4813 struct netlink_ext_ack *extack = f->common.extack;
4814 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4815 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4816 struct mlx5e_tc_flow *flow;
4817 int err = 0;
4818
4819 if (!mlx5_esw_hold(priv->mdev))
4820 return -EBUSY;
4821
4822 err = mlx5e_tc_block_ipsec_offload(dev, priv);
4823 if (err)
4824 goto esw_release;
4825
4826 mlx5_esw_get(priv->mdev);
4827
4828 rcu_read_lock();
4829 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4830 if (flow) {
4831 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4832 * just return 0.
4833 */
4834 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
4835 goto rcu_unlock;
4836
4837 NL_SET_ERR_MSG_MOD(extack,
4838 "flow cookie already exists, ignoring");
4839 netdev_warn_once(priv->netdev,
4840 "flow cookie %lx already exists, ignoring\n",
4841 f->cookie);
4842 err = -EEXIST;
4843 goto rcu_unlock;
4844 }
4845 rcu_unlock:
4846 rcu_read_unlock();
4847 if (flow)
4848 goto out;
4849
4850 trace_mlx5e_configure_flower(f);
4851 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
4852 if (err)
4853 goto out;
4854
4855 /* Flow rule offloaded to non-uplink representor sharing tc block,
4856 * set the flow's owner dev.
4857 */
4858 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4859 flow->orig_dev = dev;
4860
4861 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
4862 if (err)
4863 goto err_free;
4864
4865 mlx5_esw_release(priv->mdev);
4866 return 0;
4867
4868 err_free:
4869 mlx5e_flow_put(priv, flow);
4870 out:
4871 mlx5e_tc_unblock_ipsec_offload(dev, priv);
4872 mlx5_esw_put(priv->mdev);
4873 esw_release:
4874 mlx5_esw_release(priv->mdev);
4875 return err;
4876 }
4877
same_flow_direction(struct mlx5e_tc_flow * flow,int flags)4878 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4879 {
4880 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4881 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
4882
4883 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4884 flow_flag_test(flow, EGRESS) == dir_egress;
4885 }
4886
mlx5e_delete_flower(struct net_device * dev,struct mlx5e_priv * priv,struct flow_cls_offload * f,unsigned long flags)4887 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
4888 struct flow_cls_offload *f, unsigned long flags)
4889 {
4890 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4891 struct mlx5e_tc_flow *flow;
4892 int err;
4893
4894 rcu_read_lock();
4895 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4896 if (!flow || !same_flow_direction(flow, flags)) {
4897 err = -EINVAL;
4898 goto errout;
4899 }
4900
4901 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4902 * set.
4903 */
4904 if (flow_flag_test_and_set(flow, DELETED)) {
4905 err = -EINVAL;
4906 goto errout;
4907 }
4908 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
4909 rcu_read_unlock();
4910
4911 trace_mlx5e_delete_flower(f);
4912 mlx5e_flow_put(priv, flow);
4913
4914 mlx5e_tc_unblock_ipsec_offload(dev, priv);
4915 mlx5_esw_put(priv->mdev);
4916 return 0;
4917
4918 errout:
4919 rcu_read_unlock();
4920 return err;
4921 }
4922
mlx5e_tc_fill_action_stats(struct mlx5e_priv * priv,struct flow_offload_action * fl_act)4923 int mlx5e_tc_fill_action_stats(struct mlx5e_priv *priv,
4924 struct flow_offload_action *fl_act)
4925 {
4926 return mlx5e_tc_act_stats_fill_stats(get_act_stats_handle(priv), fl_act);
4927 }
4928
mlx5e_stats_flower(struct net_device * dev,struct mlx5e_priv * priv,struct flow_cls_offload * f,unsigned long flags)4929 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
4930 struct flow_cls_offload *f, unsigned long flags)
4931 {
4932 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4933 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4934 struct mlx5e_tc_flow *flow;
4935 struct mlx5_fc *counter;
4936 u64 lastuse = 0;
4937 u64 packets = 0;
4938 u64 bytes = 0;
4939 int err = 0;
4940
4941 rcu_read_lock();
4942 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4943 tc_ht_params));
4944 rcu_read_unlock();
4945 if (IS_ERR(flow))
4946 return PTR_ERR(flow);
4947
4948 if (!same_flow_direction(flow, flags)) {
4949 err = -EINVAL;
4950 goto errout;
4951 }
4952
4953 if (mlx5e_is_offloaded_flow(flow)) {
4954 if (flow_flag_test(flow, USE_ACT_STATS)) {
4955 f->use_act_stats = true;
4956 } else {
4957 counter = mlx5e_tc_get_counter(flow);
4958 if (!counter)
4959 goto errout;
4960
4961 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4962 }
4963 }
4964
4965 /* Under multipath it's possible for one rule to be currently
4966 * un-offloaded while the other rule is offloaded.
4967 */
4968 if (esw && !mlx5_devcom_for_each_peer_begin(esw->devcom))
4969 goto out;
4970
4971 if (flow_flag_test(flow, DUP)) {
4972 struct mlx5e_tc_flow *peer_flow;
4973
4974 list_for_each_entry(peer_flow, &flow->peer_flows, peer_flows) {
4975 u64 packets2;
4976 u64 lastuse2;
4977 u64 bytes2;
4978
4979 if (!flow_flag_test(peer_flow, OFFLOADED))
4980 continue;
4981 if (flow_flag_test(flow, USE_ACT_STATS)) {
4982 f->use_act_stats = true;
4983 break;
4984 }
4985
4986 counter = mlx5e_tc_get_counter(peer_flow);
4987 if (!counter)
4988 goto no_peer_counter;
4989 mlx5_fc_query_cached(counter, &bytes2, &packets2,
4990 &lastuse2);
4991
4992 bytes += bytes2;
4993 packets += packets2;
4994 lastuse = max_t(u64, lastuse, lastuse2);
4995 }
4996 }
4997
4998 no_peer_counter:
4999 if (esw)
5000 mlx5_devcom_for_each_peer_end(esw->devcom);
5001 out:
5002 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
5003 FLOW_ACTION_HW_STATS_DELAYED);
5004 trace_mlx5e_stats_flower(f);
5005 errout:
5006 mlx5e_flow_put(priv, flow);
5007 return err;
5008 }
5009
apply_police_params(struct mlx5e_priv * priv,u64 rate,struct netlink_ext_ack * extack)5010 static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
5011 struct netlink_ext_ack *extack)
5012 {
5013 struct mlx5e_rep_priv *rpriv = priv->ppriv;
5014 struct mlx5_eswitch *esw;
5015 u32 rate_mbps = 0;
5016 u16 vport_num;
5017 int err;
5018
5019 vport_num = rpriv->rep->vport;
5020 if (vport_num >= MLX5_VPORT_ECPF) {
5021 NL_SET_ERR_MSG_MOD(extack,
5022 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
5023 return -EOPNOTSUPP;
5024 }
5025
5026 esw = priv->mdev->priv.eswitch;
5027 /* rate is given in bytes/sec.
5028 * First convert to bits/sec and then round to the nearest mbit/secs.
5029 * mbit means million bits.
5030 * Moreover, if rate is non zero we choose to configure to a minimum of
5031 * 1 mbit/sec.
5032 */
5033 if (rate) {
5034 rate = (rate * BITS_PER_BYTE) + 500000;
5035 do_div(rate, 1000000);
5036 rate_mbps = max_t(u32, rate, 1);
5037 }
5038
5039 err = mlx5_esw_qos_modify_vport_rate(esw, vport_num, rate_mbps);
5040 if (err)
5041 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
5042
5043 return err;
5044 }
5045
5046 static int
tc_matchall_police_validate(const struct flow_action * action,const struct flow_action_entry * act,struct netlink_ext_ack * extack)5047 tc_matchall_police_validate(const struct flow_action *action,
5048 const struct flow_action_entry *act,
5049 struct netlink_ext_ack *extack)
5050 {
5051 if (act->police.notexceed.act_id != FLOW_ACTION_CONTINUE) {
5052 NL_SET_ERR_MSG_MOD(extack,
5053 "Offload not supported when conform action is not continue");
5054 return -EOPNOTSUPP;
5055 }
5056
5057 if (act->police.exceed.act_id != FLOW_ACTION_DROP) {
5058 NL_SET_ERR_MSG_MOD(extack,
5059 "Offload not supported when exceed action is not drop");
5060 return -EOPNOTSUPP;
5061 }
5062
5063 if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT &&
5064 !flow_action_is_last_entry(action, act)) {
5065 NL_SET_ERR_MSG_MOD(extack,
5066 "Offload not supported when conform action is ok, but action is not last");
5067 return -EOPNOTSUPP;
5068 }
5069
5070 if (act->police.peakrate_bytes_ps ||
5071 act->police.avrate || act->police.overhead) {
5072 NL_SET_ERR_MSG_MOD(extack,
5073 "Offload not supported when peakrate/avrate/overhead is configured");
5074 return -EOPNOTSUPP;
5075 }
5076
5077 return 0;
5078 }
5079
scan_tc_matchall_fdb_actions(struct mlx5e_priv * priv,struct flow_action * flow_action,struct netlink_ext_ack * extack)5080 static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
5081 struct flow_action *flow_action,
5082 struct netlink_ext_ack *extack)
5083 {
5084 struct mlx5e_rep_priv *rpriv = priv->ppriv;
5085 const struct flow_action_entry *act;
5086 int err;
5087 int i;
5088
5089 if (!flow_action_has_entries(flow_action)) {
5090 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
5091 return -EINVAL;
5092 }
5093
5094 if (!flow_offload_has_one_action(flow_action)) {
5095 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
5096 return -EOPNOTSUPP;
5097 }
5098
5099 if (!flow_action_basic_hw_stats_check(flow_action, extack)) {
5100 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
5101 return -EOPNOTSUPP;
5102 }
5103
5104 flow_action_for_each(i, act, flow_action) {
5105 switch (act->id) {
5106 case FLOW_ACTION_POLICE:
5107 err = tc_matchall_police_validate(flow_action, act, extack);
5108 if (err)
5109 return err;
5110
5111 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
5112 if (err)
5113 return err;
5114
5115 mlx5e_stats_copy_rep_stats(&rpriv->prev_vf_vport_stats,
5116 &priv->stats.rep_stats);
5117 break;
5118 default:
5119 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
5120 return -EOPNOTSUPP;
5121 }
5122 }
5123
5124 return 0;
5125 }
5126
mlx5e_tc_configure_matchall(struct mlx5e_priv * priv,struct tc_cls_matchall_offload * ma)5127 int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
5128 struct tc_cls_matchall_offload *ma)
5129 {
5130 struct netlink_ext_ack *extack = ma->common.extack;
5131
5132 if (ma->common.prio != 1) {
5133 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
5134 return -EINVAL;
5135 }
5136
5137 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
5138 }
5139
mlx5e_tc_delete_matchall(struct mlx5e_priv * priv,struct tc_cls_matchall_offload * ma)5140 int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
5141 struct tc_cls_matchall_offload *ma)
5142 {
5143 struct netlink_ext_ack *extack = ma->common.extack;
5144
5145 return apply_police_params(priv, 0, extack);
5146 }
5147
mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv * priv,struct mlx5e_priv * peer_priv)5148 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
5149 struct mlx5e_priv *peer_priv)
5150 {
5151 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5152 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
5153 struct mlx5e_hairpin_entry *hpe, *tmp;
5154 LIST_HEAD(init_wait_list);
5155 u16 peer_vhca_id;
5156 int bkt;
5157
5158 if (!mlx5e_same_hw_devs(priv, peer_priv))
5159 return;
5160
5161 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
5162
5163 mutex_lock(&tc->hairpin_tbl_lock);
5164 hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
5165 if (refcount_inc_not_zero(&hpe->refcnt))
5166 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
5167 mutex_unlock(&tc->hairpin_tbl_lock);
5168
5169 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
5170 wait_for_completion(&hpe->res_ready);
5171 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
5172 mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
5173
5174 mlx5e_hairpin_put(priv, hpe);
5175 }
5176 }
5177
mlx5e_tc_netdev_event(struct notifier_block * this,unsigned long event,void * ptr)5178 static int mlx5e_tc_netdev_event(struct notifier_block *this,
5179 unsigned long event, void *ptr)
5180 {
5181 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
5182 struct mlx5e_priv *peer_priv;
5183 struct mlx5e_tc_table *tc;
5184 struct mlx5e_priv *priv;
5185
5186 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
5187 event != NETDEV_UNREGISTER ||
5188 ndev->reg_state == NETREG_REGISTERED)
5189 return NOTIFY_DONE;
5190
5191 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
5192 priv = tc->priv;
5193 peer_priv = netdev_priv(ndev);
5194 if (priv == peer_priv ||
5195 !(priv->netdev->features & NETIF_F_HW_TC))
5196 return NOTIFY_DONE;
5197
5198 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
5199
5200 return NOTIFY_DONE;
5201 }
5202
mlx5e_tc_nic_create_miss_table(struct mlx5e_priv * priv)5203 static int mlx5e_tc_nic_create_miss_table(struct mlx5e_priv *priv)
5204 {
5205 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5206 struct mlx5_flow_table **ft = &tc->miss_t;
5207 struct mlx5_flow_table_attr ft_attr = {};
5208 struct mlx5_flow_namespace *ns;
5209 int err = 0;
5210
5211 ft_attr.max_fte = 1;
5212 ft_attr.autogroup.max_num_groups = 1;
5213 ft_attr.level = MLX5E_TC_MISS_LEVEL;
5214 ft_attr.prio = 0;
5215 ns = mlx5_get_flow_namespace(priv->mdev, MLX5_FLOW_NAMESPACE_KERNEL);
5216
5217 *ft = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
5218 if (IS_ERR(*ft)) {
5219 err = PTR_ERR(*ft);
5220 netdev_err(priv->netdev, "failed to create tc nic miss table err=%d\n", err);
5221 }
5222
5223 return err;
5224 }
5225
mlx5e_tc_nic_destroy_miss_table(struct mlx5e_priv * priv)5226 static void mlx5e_tc_nic_destroy_miss_table(struct mlx5e_priv *priv)
5227 {
5228 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5229
5230 mlx5_destroy_flow_table(tc->miss_t);
5231 }
5232
mlx5e_tc_nic_init(struct mlx5e_priv * priv)5233 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
5234 {
5235 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5236 struct mlx5_core_dev *dev = priv->mdev;
5237 struct mapping_ctx *chains_mapping;
5238 struct mlx5_chains_attr attr = {};
5239 u64 mapping_id;
5240 int err;
5241
5242 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
5243 mutex_init(&tc->t_lock);
5244 mutex_init(&tc->hairpin_tbl_lock);
5245 hash_init(tc->hairpin_tbl);
5246 tc->priv = priv;
5247
5248 err = rhashtable_init(&tc->ht, &tc_ht_params);
5249 if (err)
5250 return err;
5251
5252 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
5253 lockdep_init_map(&tc->ht.run_work.lockdep_map, "tc_ht_wq_key", &tc_ht_wq_key, 0);
5254
5255 mapping_id = mlx5_query_nic_system_image_guid(dev);
5256
5257 chains_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
5258 sizeof(struct mlx5_mapped_obj),
5259 MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
5260
5261 if (IS_ERR(chains_mapping)) {
5262 err = PTR_ERR(chains_mapping);
5263 goto err_mapping;
5264 }
5265 tc->mapping = chains_mapping;
5266
5267 err = mlx5e_tc_nic_create_miss_table(priv);
5268 if (err)
5269 goto err_chains;
5270
5271 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
5272 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
5273 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
5274 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
5275 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
5276 attr.default_ft = tc->miss_t;
5277 attr.mapping = chains_mapping;
5278 attr.fs_base_prio = MLX5E_TC_PRIO;
5279
5280 tc->chains = mlx5_chains_create(dev, &attr);
5281 if (IS_ERR(tc->chains)) {
5282 err = PTR_ERR(tc->chains);
5283 goto err_miss;
5284 }
5285
5286 mlx5_chains_print_info(tc->chains);
5287
5288 tc->post_act = mlx5e_tc_post_act_init(priv, tc->chains, MLX5_FLOW_NAMESPACE_KERNEL);
5289 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &tc->mod_hdr,
5290 MLX5_FLOW_NAMESPACE_KERNEL, tc->post_act);
5291
5292 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
5293 err = register_netdevice_notifier_dev_net(priv->netdev,
5294 &tc->netdevice_nb,
5295 &tc->netdevice_nn);
5296 if (err) {
5297 tc->netdevice_nb.notifier_call = NULL;
5298 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
5299 goto err_reg;
5300 }
5301
5302 mlx5e_tc_debugfs_init(tc, mlx5e_fs_get_debugfs_root(priv->fs));
5303
5304 tc->action_stats_handle = mlx5e_tc_act_stats_create();
5305 if (IS_ERR(tc->action_stats_handle)) {
5306 err = PTR_ERR(tc->action_stats_handle);
5307 goto err_act_stats;
5308 }
5309
5310 return 0;
5311
5312 err_act_stats:
5313 unregister_netdevice_notifier_dev_net(priv->netdev,
5314 &tc->netdevice_nb,
5315 &tc->netdevice_nn);
5316 err_reg:
5317 mlx5_tc_ct_clean(tc->ct);
5318 mlx5e_tc_post_act_destroy(tc->post_act);
5319 mlx5_chains_destroy(tc->chains);
5320 err_miss:
5321 mlx5e_tc_nic_destroy_miss_table(priv);
5322 err_chains:
5323 mapping_destroy(chains_mapping);
5324 err_mapping:
5325 rhashtable_destroy(&tc->ht);
5326 return err;
5327 }
5328
_mlx5e_tc_del_flow(void * ptr,void * arg)5329 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
5330 {
5331 struct mlx5e_tc_flow *flow = ptr;
5332 struct mlx5e_priv *priv = flow->priv;
5333
5334 mlx5e_tc_del_flow(priv, flow);
5335 kfree(flow);
5336 }
5337
mlx5e_tc_nic_cleanup(struct mlx5e_priv * priv)5338 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
5339 {
5340 struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5341
5342 debugfs_remove_recursive(tc->dfs_root);
5343
5344 if (tc->netdevice_nb.notifier_call)
5345 unregister_netdevice_notifier_dev_net(priv->netdev,
5346 &tc->netdevice_nb,
5347 &tc->netdevice_nn);
5348
5349 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
5350 mutex_destroy(&tc->hairpin_tbl_lock);
5351
5352 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
5353
5354 if (!IS_ERR_OR_NULL(tc->t)) {
5355 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
5356 tc->t = NULL;
5357 }
5358 mutex_destroy(&tc->t_lock);
5359
5360 mlx5_tc_ct_clean(tc->ct);
5361 mlx5e_tc_post_act_destroy(tc->post_act);
5362 mapping_destroy(tc->mapping);
5363 mlx5_chains_destroy(tc->chains);
5364 mlx5e_tc_nic_destroy_miss_table(priv);
5365 mlx5e_tc_act_stats_free(tc->action_stats_handle);
5366 }
5367
mlx5e_tc_ht_init(struct rhashtable * tc_ht)5368 int mlx5e_tc_ht_init(struct rhashtable *tc_ht)
5369 {
5370 int err;
5371
5372 err = rhashtable_init(tc_ht, &tc_ht_params);
5373 if (err)
5374 return err;
5375
5376 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
5377 lockdep_init_map(&tc_ht->run_work.lockdep_map, "tc_ht_wq_key", &tc_ht_wq_key, 0);
5378
5379 return 0;
5380 }
5381
mlx5e_tc_ht_cleanup(struct rhashtable * tc_ht)5382 void mlx5e_tc_ht_cleanup(struct rhashtable *tc_ht)
5383 {
5384 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
5385 }
5386
mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv * uplink_priv)5387 int mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv *uplink_priv)
5388 {
5389 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
5390 struct netdev_phys_item_id ppid;
5391 struct mlx5e_rep_priv *rpriv;
5392 struct mapping_ctx *mapping;
5393 struct mlx5_eswitch *esw;
5394 struct mlx5e_priv *priv;
5395 u64 mapping_id, key;
5396 int err = 0;
5397
5398 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5399 priv = netdev_priv(rpriv->netdev);
5400 esw = priv->mdev->priv.eswitch;
5401
5402 uplink_priv->post_act = mlx5e_tc_post_act_init(priv, esw_chains(esw),
5403 MLX5_FLOW_NAMESPACE_FDB);
5404 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
5405 esw_chains(esw),
5406 &esw->offloads.mod_hdr,
5407 MLX5_FLOW_NAMESPACE_FDB,
5408 uplink_priv->post_act);
5409
5410 uplink_priv->int_port_priv = mlx5e_tc_int_port_init(netdev_priv(priv->netdev));
5411
5412 uplink_priv->tc_psample = mlx5e_tc_sample_init(esw, uplink_priv->post_act);
5413
5414 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
5415
5416 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL,
5417 sizeof(struct tunnel_match_key),
5418 TUNNEL_INFO_BITS_MASK, true);
5419
5420 if (IS_ERR(mapping)) {
5421 err = PTR_ERR(mapping);
5422 goto err_tun_mapping;
5423 }
5424 uplink_priv->tunnel_mapping = mapping;
5425
5426 /* Two last values are reserved for stack devices slow path table mark
5427 * and bridge ingress push mark.
5428 */
5429 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL_ENC_OPTS,
5430 sz_enc_opts, ENC_OPTS_BITS_MASK - 2, true);
5431 if (IS_ERR(mapping)) {
5432 err = PTR_ERR(mapping);
5433 goto err_enc_opts_mapping;
5434 }
5435 uplink_priv->tunnel_enc_opts_mapping = mapping;
5436
5437 uplink_priv->encap = mlx5e_tc_tun_init(priv);
5438 if (IS_ERR(uplink_priv->encap)) {
5439 err = PTR_ERR(uplink_priv->encap);
5440 goto err_register_fib_notifier;
5441 }
5442
5443 uplink_priv->action_stats_handle = mlx5e_tc_act_stats_create();
5444 if (IS_ERR(uplink_priv->action_stats_handle)) {
5445 err = PTR_ERR(uplink_priv->action_stats_handle);
5446 goto err_action_counter;
5447 }
5448
5449 err = dev_get_port_parent_id(priv->netdev, &ppid, false);
5450 if (!err) {
5451 memcpy(&key, &ppid.id, sizeof(key));
5452 mlx5_esw_offloads_devcom_init(esw, key);
5453 }
5454
5455 return 0;
5456
5457 err_action_counter:
5458 mlx5e_tc_tun_cleanup(uplink_priv->encap);
5459 err_register_fib_notifier:
5460 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5461 err_enc_opts_mapping:
5462 mapping_destroy(uplink_priv->tunnel_mapping);
5463 err_tun_mapping:
5464 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
5465 mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
5466 mlx5_tc_ct_clean(uplink_priv->ct_priv);
5467 netdev_warn(priv->netdev,
5468 "Failed to initialize tc (eswitch), err: %d", err);
5469 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
5470 return err;
5471 }
5472
mlx5e_tc_esw_cleanup(struct mlx5_rep_uplink_priv * uplink_priv)5473 void mlx5e_tc_esw_cleanup(struct mlx5_rep_uplink_priv *uplink_priv)
5474 {
5475 struct mlx5e_rep_priv *rpriv;
5476 struct mlx5_eswitch *esw;
5477 struct mlx5e_priv *priv;
5478
5479 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5480 priv = netdev_priv(rpriv->netdev);
5481 esw = priv->mdev->priv.eswitch;
5482
5483 mlx5_esw_offloads_devcom_cleanup(esw);
5484
5485 mlx5e_tc_tun_cleanup(uplink_priv->encap);
5486
5487 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5488 mapping_destroy(uplink_priv->tunnel_mapping);
5489
5490 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
5491 mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
5492 mlx5_tc_ct_clean(uplink_priv->ct_priv);
5493 mlx5e_flow_meters_cleanup(uplink_priv->flow_meters);
5494 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
5495 mlx5e_tc_act_stats_free(uplink_priv->action_stats_handle);
5496 }
5497
mlx5e_tc_num_filters(struct mlx5e_priv * priv,unsigned long flags)5498 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
5499 {
5500 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
5501
5502 return atomic_read(&tc_ht->nelems);
5503 }
5504
mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch * esw)5505 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5506 {
5507 struct mlx5e_tc_flow *flow, *tmp;
5508 int i;
5509
5510 for (i = 0; i < MLX5_MAX_PORTS; i++) {
5511 if (i == mlx5_get_dev_index(esw->dev))
5512 continue;
5513 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows[i], peer[i])
5514 mlx5e_tc_del_fdb_peers_flow(flow);
5515 }
5516 }
5517
mlx5e_tc_reoffload_flows_work(struct work_struct * work)5518 void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5519 {
5520 struct mlx5_rep_uplink_priv *rpriv =
5521 container_of(work, struct mlx5_rep_uplink_priv,
5522 reoffload_flows_work);
5523 struct mlx5e_tc_flow *flow, *tmp;
5524
5525 mutex_lock(&rpriv->unready_flows_lock);
5526 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5527 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
5528 unready_flow_del(flow);
5529 }
5530 mutex_unlock(&rpriv->unready_flows_lock);
5531 }
5532
mlx5e_setup_tc_cls_flower(struct mlx5e_priv * priv,struct flow_cls_offload * cls_flower,unsigned long flags)5533 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5534 struct flow_cls_offload *cls_flower,
5535 unsigned long flags)
5536 {
5537 switch (cls_flower->command) {
5538 case FLOW_CLS_REPLACE:
5539 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5540 flags);
5541 case FLOW_CLS_DESTROY:
5542 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5543 flags);
5544 case FLOW_CLS_STATS:
5545 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5546 flags);
5547 default:
5548 return -EOPNOTSUPP;
5549 }
5550 }
5551
mlx5e_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)5552 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5553 void *cb_priv)
5554 {
5555 unsigned long flags = MLX5_TC_FLAG(INGRESS);
5556 struct mlx5e_priv *priv = cb_priv;
5557
5558 if (!priv->netdev || !netif_device_present(priv->netdev))
5559 return -EOPNOTSUPP;
5560
5561 if (mlx5e_is_uplink_rep(priv))
5562 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
5563 else
5564 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
5565
5566 switch (type) {
5567 case TC_SETUP_CLSFLOWER:
5568 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5569 default:
5570 return -EOPNOTSUPP;
5571 }
5572 }
5573
mlx5e_tc_restore_tunnel(struct mlx5e_priv * priv,struct sk_buff * skb,struct mlx5e_tc_update_priv * tc_priv,u32 tunnel_id)5574 static bool mlx5e_tc_restore_tunnel(struct mlx5e_priv *priv, struct sk_buff *skb,
5575 struct mlx5e_tc_update_priv *tc_priv,
5576 u32 tunnel_id)
5577 {
5578 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5579 struct tunnel_match_enc_opts enc_opts = {};
5580 struct mlx5_rep_uplink_priv *uplink_priv;
5581 IP_TUNNEL_DECLARE_FLAGS(flags) = { };
5582 struct mlx5e_rep_priv *uplink_rpriv;
5583 struct metadata_dst *tun_dst;
5584 struct tunnel_match_key key;
5585 u32 tun_id, enc_opts_id;
5586 struct net_device *dev;
5587 int err;
5588
5589 __set_bit(IP_TUNNEL_KEY_BIT, flags);
5590
5591 enc_opts_id = tunnel_id & ENC_OPTS_BITS_MASK;
5592 tun_id = tunnel_id >> ENC_OPTS_BITS;
5593
5594 if (!tun_id)
5595 return true;
5596
5597 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5598 uplink_priv = &uplink_rpriv->uplink_priv;
5599
5600 err = mapping_find(uplink_priv->tunnel_mapping, tun_id, &key);
5601 if (err) {
5602 netdev_dbg(priv->netdev,
5603 "Couldn't find tunnel for tun_id: %d, err: %d\n",
5604 tun_id, err);
5605 return false;
5606 }
5607
5608 if (enc_opts_id) {
5609 err = mapping_find(uplink_priv->tunnel_enc_opts_mapping,
5610 enc_opts_id, &enc_opts);
5611 if (err) {
5612 netdev_dbg(priv->netdev,
5613 "Couldn't find tunnel (opts) for tun_id: %d, err: %d\n",
5614 enc_opts_id, err);
5615 return false;
5616 }
5617 }
5618
5619 switch (key.enc_control.addr_type) {
5620 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
5621 tun_dst = __ip_tun_set_dst(key.enc_ipv4.src, key.enc_ipv4.dst,
5622 key.enc_ip.tos, key.enc_ip.ttl,
5623 key.enc_tp.dst, flags,
5624 key32_to_tunnel_id(key.enc_key_id.keyid),
5625 enc_opts.key.len);
5626 break;
5627 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
5628 tun_dst = __ipv6_tun_set_dst(&key.enc_ipv6.src, &key.enc_ipv6.dst,
5629 key.enc_ip.tos, key.enc_ip.ttl,
5630 key.enc_tp.dst, 0, flags,
5631 key32_to_tunnel_id(key.enc_key_id.keyid),
5632 enc_opts.key.len);
5633 break;
5634 default:
5635 netdev_dbg(priv->netdev,
5636 "Couldn't restore tunnel, unsupported addr_type: %d\n",
5637 key.enc_control.addr_type);
5638 return false;
5639 }
5640
5641 if (!tun_dst) {
5642 netdev_dbg(priv->netdev, "Couldn't restore tunnel, no tun_dst\n");
5643 return false;
5644 }
5645
5646 tun_dst->u.tun_info.key.tp_src = key.enc_tp.src;
5647
5648 if (enc_opts.key.len) {
5649 ip_tunnel_flags_zero(flags);
5650 if (enc_opts.key.dst_opt_type)
5651 __set_bit(enc_opts.key.dst_opt_type, flags);
5652
5653 ip_tunnel_info_opts_set(&tun_dst->u.tun_info,
5654 enc_opts.key.data,
5655 enc_opts.key.len,
5656 flags);
5657 }
5658
5659 skb_dst_set(skb, (struct dst_entry *)tun_dst);
5660 dev = dev_get_by_index(&init_net, key.filter_ifindex);
5661 if (!dev) {
5662 netdev_dbg(priv->netdev,
5663 "Couldn't find tunnel device with ifindex: %d\n",
5664 key.filter_ifindex);
5665 return false;
5666 }
5667
5668 /* Set fwd_dev so we do dev_put() after datapath */
5669 tc_priv->fwd_dev = dev;
5670
5671 skb->dev = dev;
5672
5673 return true;
5674 }
5675
mlx5e_tc_restore_skb_tc_meta(struct sk_buff * skb,struct mlx5_tc_ct_priv * ct_priv,struct mlx5_mapped_obj * mapped_obj,u32 zone_restore_id,u32 tunnel_id,struct mlx5e_tc_update_priv * tc_priv)5676 static bool mlx5e_tc_restore_skb_tc_meta(struct sk_buff *skb, struct mlx5_tc_ct_priv *ct_priv,
5677 struct mlx5_mapped_obj *mapped_obj, u32 zone_restore_id,
5678 u32 tunnel_id, struct mlx5e_tc_update_priv *tc_priv)
5679 {
5680 struct mlx5e_priv *priv = netdev_priv(skb->dev);
5681 struct tc_skb_ext *tc_skb_ext;
5682 u64 act_miss_cookie;
5683 u32 chain;
5684
5685 chain = mapped_obj->type == MLX5_MAPPED_OBJ_CHAIN ? mapped_obj->chain : 0;
5686 act_miss_cookie = mapped_obj->type == MLX5_MAPPED_OBJ_ACT_MISS ?
5687 mapped_obj->act_miss_cookie : 0;
5688 if (chain || act_miss_cookie) {
5689 if (!mlx5e_tc_ct_restore_flow(ct_priv, skb, zone_restore_id))
5690 return false;
5691
5692 tc_skb_ext = tc_skb_ext_alloc(skb);
5693 if (!tc_skb_ext) {
5694 WARN_ON(1);
5695 return false;
5696 }
5697
5698 if (act_miss_cookie) {
5699 tc_skb_ext->act_miss_cookie = act_miss_cookie;
5700 tc_skb_ext->act_miss = 1;
5701 } else {
5702 tc_skb_ext->chain = chain;
5703 }
5704 }
5705
5706 if (tc_priv)
5707 return mlx5e_tc_restore_tunnel(priv, skb, tc_priv, tunnel_id);
5708
5709 return true;
5710 }
5711
mlx5e_tc_restore_skb_sample(struct mlx5e_priv * priv,struct sk_buff * skb,struct mlx5_mapped_obj * mapped_obj,struct mlx5e_tc_update_priv * tc_priv)5712 static void mlx5e_tc_restore_skb_sample(struct mlx5e_priv *priv, struct sk_buff *skb,
5713 struct mlx5_mapped_obj *mapped_obj,
5714 struct mlx5e_tc_update_priv *tc_priv)
5715 {
5716 if (!mlx5e_tc_restore_tunnel(priv, skb, tc_priv, mapped_obj->sample.tunnel_id)) {
5717 netdev_dbg(priv->netdev,
5718 "Failed to restore tunnel info for sampled packet\n");
5719 return;
5720 }
5721 mlx5e_tc_sample_skb(skb, mapped_obj);
5722 }
5723
mlx5e_tc_restore_skb_int_port(struct mlx5e_priv * priv,struct sk_buff * skb,struct mlx5_mapped_obj * mapped_obj,struct mlx5e_tc_update_priv * tc_priv,u32 tunnel_id)5724 static bool mlx5e_tc_restore_skb_int_port(struct mlx5e_priv *priv, struct sk_buff *skb,
5725 struct mlx5_mapped_obj *mapped_obj,
5726 struct mlx5e_tc_update_priv *tc_priv,
5727 u32 tunnel_id)
5728 {
5729 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5730 struct mlx5_rep_uplink_priv *uplink_priv;
5731 struct mlx5e_rep_priv *uplink_rpriv;
5732 bool forward_tx = false;
5733
5734 /* Tunnel restore takes precedence over int port restore */
5735 if (tunnel_id)
5736 return mlx5e_tc_restore_tunnel(priv, skb, tc_priv, tunnel_id);
5737
5738 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5739 uplink_priv = &uplink_rpriv->uplink_priv;
5740
5741 if (mlx5e_tc_int_port_dev_fwd(uplink_priv->int_port_priv, skb,
5742 mapped_obj->int_port_metadata, &forward_tx)) {
5743 /* Set fwd_dev for future dev_put */
5744 tc_priv->fwd_dev = skb->dev;
5745 tc_priv->forward_tx = forward_tx;
5746
5747 return true;
5748 }
5749
5750 return false;
5751 }
5752
mlx5e_tc_update_skb(struct mlx5_cqe64 * cqe,struct sk_buff * skb,struct mapping_ctx * mapping_ctx,u32 mapped_obj_id,struct mlx5_tc_ct_priv * ct_priv,u32 zone_restore_id,u32 tunnel_id,struct mlx5e_tc_update_priv * tc_priv)5753 bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe, struct sk_buff *skb,
5754 struct mapping_ctx *mapping_ctx, u32 mapped_obj_id,
5755 struct mlx5_tc_ct_priv *ct_priv,
5756 u32 zone_restore_id, u32 tunnel_id,
5757 struct mlx5e_tc_update_priv *tc_priv)
5758 {
5759 struct mlx5e_priv *priv = netdev_priv(skb->dev);
5760 struct mlx5_mapped_obj mapped_obj;
5761 int err;
5762
5763 err = mapping_find(mapping_ctx, mapped_obj_id, &mapped_obj);
5764 if (err) {
5765 netdev_dbg(skb->dev,
5766 "Couldn't find mapped object for mapped_obj_id: %d, err: %d\n",
5767 mapped_obj_id, err);
5768 return false;
5769 }
5770
5771 switch (mapped_obj.type) {
5772 case MLX5_MAPPED_OBJ_CHAIN:
5773 case MLX5_MAPPED_OBJ_ACT_MISS:
5774 return mlx5e_tc_restore_skb_tc_meta(skb, ct_priv, &mapped_obj, zone_restore_id,
5775 tunnel_id, tc_priv);
5776 case MLX5_MAPPED_OBJ_SAMPLE:
5777 mlx5e_tc_restore_skb_sample(priv, skb, &mapped_obj, tc_priv);
5778 tc_priv->skb_done = true;
5779 return true;
5780 case MLX5_MAPPED_OBJ_INT_PORT_METADATA:
5781 return mlx5e_tc_restore_skb_int_port(priv, skb, &mapped_obj, tc_priv, tunnel_id);
5782 default:
5783 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
5784 return false;
5785 }
5786
5787 return false;
5788 }
5789
mlx5e_tc_update_skb_nic(struct mlx5_cqe64 * cqe,struct sk_buff * skb)5790 bool mlx5e_tc_update_skb_nic(struct mlx5_cqe64 *cqe, struct sk_buff *skb)
5791 {
5792 struct mlx5e_priv *priv = netdev_priv(skb->dev);
5793 u32 mapped_obj_id, reg_b, zone_restore_id;
5794 struct mlx5_tc_ct_priv *ct_priv;
5795 struct mapping_ctx *mapping_ctx;
5796 struct mlx5e_tc_table *tc;
5797
5798 reg_b = be32_to_cpu(cqe->ft_metadata);
5799 tc = mlx5e_fs_get_tc(priv->fs);
5800 mapped_obj_id = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5801 zone_restore_id = (reg_b >> MLX5_REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
5802 ESW_ZONE_ID_MASK;
5803 ct_priv = tc->ct;
5804 mapping_ctx = tc->mapping;
5805
5806 return mlx5e_tc_update_skb(cqe, skb, mapping_ctx, mapped_obj_id, ct_priv, zone_restore_id,
5807 0, NULL);
5808 }
5809
5810 static struct mapping_ctx *
mlx5e_get_priv_obj_mapping(struct mlx5e_priv * priv)5811 mlx5e_get_priv_obj_mapping(struct mlx5e_priv *priv)
5812 {
5813 struct mlx5e_tc_table *tc;
5814 struct mlx5_eswitch *esw;
5815 struct mapping_ctx *ctx;
5816
5817 if (is_mdev_switchdev_mode(priv->mdev)) {
5818 esw = priv->mdev->priv.eswitch;
5819 ctx = esw->offloads.reg_c0_obj_pool;
5820 } else {
5821 tc = mlx5e_fs_get_tc(priv->fs);
5822 ctx = tc->mapping;
5823 }
5824
5825 return ctx;
5826 }
5827
mlx5e_tc_action_miss_mapping_get(struct mlx5e_priv * priv,struct mlx5_flow_attr * attr,u64 act_miss_cookie,u32 * act_miss_mapping)5828 int mlx5e_tc_action_miss_mapping_get(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr,
5829 u64 act_miss_cookie, u32 *act_miss_mapping)
5830 {
5831 struct mlx5_mapped_obj mapped_obj = {};
5832 struct mlx5_eswitch *esw;
5833 struct mapping_ctx *ctx;
5834 int err;
5835
5836 ctx = mlx5e_get_priv_obj_mapping(priv);
5837 mapped_obj.type = MLX5_MAPPED_OBJ_ACT_MISS;
5838 mapped_obj.act_miss_cookie = act_miss_cookie;
5839 err = mapping_add(ctx, &mapped_obj, act_miss_mapping);
5840 if (err)
5841 return err;
5842
5843 if (!is_mdev_switchdev_mode(priv->mdev))
5844 return 0;
5845
5846 esw = priv->mdev->priv.eswitch;
5847 attr->act_id_restore_rule = esw_add_restore_rule(esw, *act_miss_mapping);
5848 if (IS_ERR(attr->act_id_restore_rule)) {
5849 err = PTR_ERR(attr->act_id_restore_rule);
5850 goto err_rule;
5851 }
5852
5853 return 0;
5854
5855 err_rule:
5856 mapping_remove(ctx, *act_miss_mapping);
5857 return err;
5858 }
5859
mlx5e_tc_action_miss_mapping_put(struct mlx5e_priv * priv,struct mlx5_flow_attr * attr,u32 act_miss_mapping)5860 void mlx5e_tc_action_miss_mapping_put(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr,
5861 u32 act_miss_mapping)
5862 {
5863 struct mapping_ctx *ctx = mlx5e_get_priv_obj_mapping(priv);
5864
5865 if (is_mdev_switchdev_mode(priv->mdev))
5866 mlx5_del_flow_rules(attr->act_id_restore_rule);
5867 mapping_remove(ctx, act_miss_mapping);
5868 }
5869