1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 #ifndef __PREROCE__ 37 #define __PREROCE__ 38 /********************************/ 39 /* Add include to common target */ 40 /********************************/ 41 #include "common_hsi.h" 42 43 /************************/ 44 /* PREROCE FW CONSTANTS */ 45 /************************/ 46 47 #define PREROCE_MAX_SGE_PER_SQ_WQE 4 //max number of SGEs in a single request 48 #define PREROCE_MAX_MR_SIZE 9000 //max size for MR (temporary firmware limitation) 49 50 #define PREROCE_PAGE_SIZE (0x1000) //4KB pages 51 52 /* 53 * The roce storm context of Mstorm 54 */ 55 struct mstorm_pre_roce_conn_st_ctx 56 { 57 struct regpair temp[2]; 58 }; 59 60 61 /* 62 * The roce task context of Mstorm 63 */ 64 struct mstorm_pre_roce_task_st_ctx 65 { 66 struct regpair temp[6]; 67 }; 68 69 70 /* 71 * The roce storm context of Ystorm 72 */ 73 struct ystorm_pre_roce_conn_st_ctx 74 { 75 struct regpair temp[4]; 76 }; 77 78 /* 79 * The roce storm context of Mstorm 80 */ 81 struct pstorm_pre_roce_conn_st_ctx 82 { 83 struct regpair temp[20]; 84 }; 85 86 /* 87 * The roce storm context of Xstorm 88 */ 89 struct xstorm_pre_roce_conn_st_ctx 90 { 91 struct regpair temp[20]; 92 }; 93 94 struct e4_xstorm_pre_roce_conn_ag_ctx 95 { 96 UCHAR reserved0 /* cdu_validation */; 97 UCHAR state /* state */; 98 UCHAR flags0; 99 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 100 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 101 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 102 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED1_SHIFT 1 103 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 104 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED2_SHIFT 2 105 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 106 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 107 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 108 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED3_SHIFT 4 109 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 110 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED4_SHIFT 5 111 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 112 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED5_SHIFT 6 113 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 114 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED6_SHIFT 7 115 UCHAR flags1; 116 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 117 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED7_SHIFT 0 118 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 119 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED8_SHIFT 1 120 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DA_ENABLE_MASK 0x1 /* bit10 */ 121 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DA_ENABLE_SHIFT 2 122 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 123 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT11_SHIFT 3 124 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 125 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT12_SHIFT 4 126 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 127 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT13_SHIFT 5 128 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 129 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT14_SHIFT 6 130 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT15_MASK 0x1 /* bit15 */ 131 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT15_SHIFT 7 132 UCHAR flags2; 133 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 134 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF0_SHIFT 0 135 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 136 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF1_SHIFT 2 137 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 138 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF2_SHIFT 4 139 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 140 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 141 UCHAR flags3; 142 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SET_DA_TIMER_CF_MASK 0x3 /* cf4 */ 143 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SET_DA_TIMER_CF_SHIFT 0 144 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 /* cf5 */ 145 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 2 146 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_IRQ_RXMIT_CF_MASK 0x3 /* cf6 */ 147 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_IRQ_RXMIT_CF_SHIFT 4 148 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_TMR_RWND_CF_MASK 0x3 /* cf7 */ 149 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_TMR_RWND_CF_SHIFT 6 150 UCHAR flags4; 151 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 /* cf8 */ 152 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 0 153 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RNR_CF_MASK 0x3 /* cf9 */ 154 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RNR_CF_SHIFT 2 155 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 156 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF10_SHIFT 4 157 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 158 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF11_SHIFT 6 159 UCHAR flags5; 160 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 161 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF12_SHIFT 0 162 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 163 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF13_SHIFT 2 164 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 165 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF14_SHIFT 4 166 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 167 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF15_SHIFT 6 168 UCHAR flags6; 169 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_CF_MASK 0x3 /* cf16 */ 170 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_CF_SHIFT 0 171 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 172 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF17_SHIFT 2 173 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 174 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF18_SHIFT 4 175 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 /* cf19 */ 176 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 177 UCHAR flags7; 178 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 179 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 180 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 181 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED10_SHIFT 2 182 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 183 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 184 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 185 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF0EN_SHIFT 6 186 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 187 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_SHIFT 7 188 UCHAR flags8; 189 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 190 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_SHIFT 0 191 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 192 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 193 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DA_EXPIRED_MASK 0x1 /* cf4en */ 194 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DA_EXPIRED_SHIFT 2 195 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 /* cf5en */ 196 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 3 197 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_IRQ_RXMIT_CF_EN_MASK 0x1 /* cf6en */ 198 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_IRQ_RXMIT_CF_EN_SHIFT 4 199 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_TMR_RWND_CF_EN_MASK 0x1 /* cf7en */ 200 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_TMR_RWND_CF_EN_SHIFT 5 201 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 /* cf8en */ 202 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 6 203 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RNR_CF_EN_MASK 0x1 /* cf9en */ 204 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RNR_CF_EN_SHIFT 7 205 UCHAR flags9; 206 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 207 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF10EN_SHIFT 0 208 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 209 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF11EN_SHIFT 1 210 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 211 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF12EN_SHIFT 2 212 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 213 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF13EN_SHIFT 3 214 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 215 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF14EN_SHIFT 4 216 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 217 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF15EN_SHIFT 5 218 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_CF_EN_MASK 0x1 /* cf16en */ 219 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_CF_EN_SHIFT 6 220 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 221 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF17EN_SHIFT 7 222 UCHAR flags10; 223 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 224 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_CF18EN_SHIFT 0 225 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 /* cf19en */ 226 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 227 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 228 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 229 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 230 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED11_SHIFT 3 231 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 232 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 233 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DPM_DONE_CF_EN_MASK 0x1 /* cf23en */ 234 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DPM_DONE_CF_EN_SHIFT 5 235 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 236 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED12_SHIFT 6 237 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 238 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED13_SHIFT 7 239 UCHAR flags11; 240 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 241 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED14_SHIFT 0 242 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 243 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED15_SHIFT 1 244 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED16_MASK 0x1 /* rule4en */ 245 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED16_SHIFT 2 246 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DA_CNT_EN_MASK 0x1 /* rule5en */ 247 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DA_CNT_EN_SHIFT 3 248 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 249 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 4 250 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_UNA_EN_MASK 0x1 /* rule7en */ 251 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_UNA_EN_SHIFT 5 252 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 253 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 254 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 255 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE9EN_SHIFT 7 256 UCHAR flags12; 257 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 /* rule10en */ 258 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 259 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 260 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE11EN_SHIFT 1 261 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 262 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 263 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 264 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 265 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SQ_CMP_CONS_EN_MASK 0x1 /* rule14en */ 266 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SQ_CMP_CONS_EN_SHIFT 4 267 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SNDLSN_NE_SNDSSN_EN_MASK 0x1 /* rule15en */ 268 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_SNDLSN_NE_SNDSSN_EN_SHIFT 5 269 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 270 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE16EN_SHIFT 6 271 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 272 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE17EN_SHIFT 7 273 UCHAR flags13; 274 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RCQ_PROD_EN_MASK 0x1 /* rule18en */ 275 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RCQ_PROD_EN_SHIFT 0 276 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_HQ_EN_MASK 0x1 /* rule19en */ 277 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_HQ_EN_SHIFT 1 278 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 279 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 280 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 281 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 282 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 283 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 284 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 285 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 286 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 287 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 288 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 289 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 290 UCHAR flags14; 291 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_MIGRATION_MASK 0x1 /* bit16 */ 292 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_MIGRATION_SHIFT 0 293 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 294 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT17_SHIFT 1 295 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 296 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 297 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 298 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 299 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 300 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 301 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DPM_DONE_CF_MASK 0x3 /* cf23 */ 302 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_DPM_DONE_CF_SHIFT 6 303 UCHAR da_mode /* byte2 */; 304 USHORT physical_q0 /* physical_q0 */; 305 USHORT word1 /* physical_q1 */; 306 USHORT sq_cmp_cons /* physical_q2 */; 307 USHORT sq_cons /* word3 */; 308 USHORT sq_prod /* word4 */; 309 USHORT word5 /* word5 */; 310 USHORT conn_dpi /* conn_dpi */; 311 UCHAR da_cnt /* byte3 */; 312 UCHAR snd_syn /* byte4 */; 313 UCHAR da_threshold /* byte5 */; 314 UCHAR da_timeout_value /* byte6 */; 315 ULONG snd_una_psn /* reg0 */; 316 ULONG snd_una_psn_th /* reg1 */; 317 ULONG snd_lsn /* reg2 */; 318 ULONG snd_nxt_psn /* reg3 */; 319 ULONG reg4 /* reg4 */; 320 ULONG snd_ssn /* cf_array0 */; 321 ULONG irq_rxmit_psn /* cf_array1 */; 322 USHORT rcq_prod /* word7 */; 323 USHORT rcq_prod_th /* word8 */; 324 USHORT hq_cons_th /* word9 */; 325 USHORT hq_cons /* word10 */; 326 ULONG ack_msn_syn_to_fe /* reg7 */; 327 ULONG ack_psn_to_fe /* reg8 */; 328 ULONG inv_stag /* reg9 */; 329 UCHAR rxmit_cmd_seq /* byte7 */; 330 UCHAR rxmit_seq /* byte8 */; 331 UCHAR byte9 /* byte9 */; 332 UCHAR byte10 /* byte10 */; 333 UCHAR byte11 /* byte11 */; 334 UCHAR byte12 /* byte12 */; 335 UCHAR byte13 /* byte13 */; 336 UCHAR byte14 /* byte14 */; 337 UCHAR byte15 /* byte15 */; 338 UCHAR e5_reserved /* e5_reserved */; 339 USHORT word11 /* word11 */; 340 }; 341 342 struct e4_tstorm_pre_roce_conn_ag_ctx 343 { 344 UCHAR reserved0 /* cdu_validation */; 345 UCHAR state /* state */; 346 UCHAR flags0; 347 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 348 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 349 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 350 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 351 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 352 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT2_SHIFT 2 353 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 354 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT3_SHIFT 3 355 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 356 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT4_SHIFT 4 357 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 358 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT5_SHIFT 5 359 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMEOUT_MASK 0x3 /* timer0cf */ 360 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMEOUT_SHIFT 6 361 UCHAR flags1; 362 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* timer1cf */ 363 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 364 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_SND_DONE_MASK 0x3 /* timer2cf */ 365 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_SND_DONE_SHIFT 2 366 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 367 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 368 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED_CF_MASK 0x3 /* cf4 */ 369 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED_CF_SHIFT 6 370 UCHAR flags2; 371 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 /* cf5 */ 372 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_SHIFT 0 373 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 374 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF6_SHIFT 2 375 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 376 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF7_SHIFT 4 377 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 378 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF8_SHIFT 6 379 UCHAR flags3; 380 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 381 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF9_SHIFT 0 382 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 383 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF10_SHIFT 2 384 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMEOUT_EN_MASK 0x1 /* cf0en */ 385 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMEOUT_EN_SHIFT 4 386 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf1en */ 387 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 388 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_SND_DONE_EN_MASK 0x1 /* cf2en */ 389 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_SND_DONE_EN_SHIFT 6 390 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 391 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 392 UCHAR flags4; 393 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED_CF_EN_MASK 0x1 /* cf4en */ 394 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED_CF_EN_SHIFT 0 395 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 /* cf5en */ 396 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 397 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 398 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF6EN_SHIFT 2 399 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 400 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF7EN_SHIFT 3 401 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 402 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF8EN_SHIFT 4 403 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 404 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF9EN_SHIFT 5 405 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 406 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_CF10EN_SHIFT 6 407 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RXMIT_SEQ_EN_MASK 0x1 /* rule0en */ 408 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RXMIT_SEQ_EN_SHIFT 7 409 UCHAR flags5; 410 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RXMIT_SEQ_LAG_EN_MASK 0x1 /* rule1en */ 411 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RXMIT_SEQ_LAG_EN_SHIFT 0 412 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 413 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 1 414 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 415 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 2 416 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 417 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 3 418 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 419 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 4 420 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 421 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 5 422 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 423 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 6 424 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 425 #define E4_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE8EN_SHIFT 7 426 ULONG reg0 /* reg0 */; 427 ULONG reg1 /* reg1 */; 428 ULONG snd_max_psn /* reg2 */; 429 ULONG orq_prod /* reg3 */; 430 ULONG irq_cons /* reg4 */; 431 ULONG snd_nxt_psn /* reg5 */; 432 ULONG reg6 /* reg6 */; 433 ULONG irq_rxmit_psn_echo /* reg7 */; 434 ULONG trcq_cons /* reg8 */; 435 UCHAR rxmit_seq /* byte2 */; 436 UCHAR rxmit_seq_echo /* byte3 */; 437 USHORT rq_prod /* word0 */; 438 UCHAR byte4 /* byte4 */; 439 UCHAR byte5 /* byte5 */; 440 USHORT word1 /* word1 */; 441 USHORT conn_dpi /* conn_dpi */; 442 USHORT word3 /* word3 */; 443 ULONG reg9 /* reg9 */; 444 ULONG reg10 /* reg10 */; 445 }; 446 447 struct e4_ustorm_pre_roce_conn_ag_ctx 448 { 449 UCHAR reserved /* cdu_validation */; 450 UCHAR byte1 /* state */; 451 UCHAR flags0; 452 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 453 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 454 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 455 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 456 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 457 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF0_SHIFT 2 458 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 459 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF1_SHIFT 4 460 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 461 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF2_SHIFT 6 462 UCHAR flags1; 463 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 464 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF3_SHIFT 0 465 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 466 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 467 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 468 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 469 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 470 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF6_SHIFT 6 471 UCHAR flags2; 472 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 473 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0 474 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 475 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 476 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 477 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 478 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 479 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF3EN_SHIFT 3 480 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 481 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 482 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 483 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 484 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 485 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CF6EN_SHIFT 6 486 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 487 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 488 UCHAR flags3; 489 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 490 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_EN_SHIFT 0 491 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 492 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 1 493 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 494 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 2 495 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 496 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 3 497 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 498 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 4 499 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 500 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 5 501 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 502 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 6 503 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 504 #define E4_USTORM_PRE_ROCE_CONN_AG_CTX_RULE8EN_SHIFT 7 505 UCHAR byte2 /* byte2 */; 506 UCHAR byte3 /* byte3 */; 507 USHORT conn_dpi /* conn_dpi */; 508 USHORT word1 /* word1 */; 509 ULONG cq_cons /* reg0 */; 510 ULONG cq_se_prod /* reg1 */; 511 ULONG cq_prod /* reg2 */; 512 ULONG reg3 /* reg3 */; 513 USHORT word2 /* word2 */; 514 USHORT word3 /* word3 */; 515 }; 516 517 /* 518 * The roce storm context of Tstorm 519 */ 520 struct tstorm_pre_roce_conn_st_ctx 521 { 522 struct regpair temp[14]; 523 }; 524 525 /* 526 * The roce storm context of Ystorm 527 */ 528 struct ustorm_pre_roce_conn_st_ctx 529 { 530 struct regpair temp[2]; 531 }; 532 533 /* 534 * pre_roce connection context 535 */ 536 struct pre_roce_conn_context 537 { 538 struct ystorm_pre_roce_conn_st_ctx ystorm_st_context /* ystorm storm context */; 539 struct pstorm_pre_roce_conn_st_ctx pstorm_st_context /* pstorm storm context */; 540 struct xstorm_pre_roce_conn_st_ctx xstorm_st_context /* xstorm storm context */; 541 struct e4_xstorm_pre_roce_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 542 struct regpair xstorm_ag_padding[4] /* padding */; 543 struct e4_tstorm_pre_roce_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 544 struct timers_context timer_context /* timer context */; 545 struct e4_ustorm_pre_roce_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 546 struct tstorm_pre_roce_conn_st_ctx tstorm_st_context /* tstorm storm context */; 547 struct regpair tstorm_st_padding[2] /* padding */; 548 struct mstorm_pre_roce_conn_st_ctx mstorm_st_context /* mstorm storm context */; 549 struct regpair mstorm_st_padding[2] /* padding */; 550 struct ustorm_pre_roce_conn_st_ctx ustorm_st_context /* ustorm storm context */; 551 struct regpair ustorm_st_padding[2] /* padding */; 552 }; 553 554 555 /* 556 * roce protocol connection states 557 */ 558 enum pre_roce_conn_state 559 { 560 PREROCE_STATE_REQ_CONNECTION=0, 561 PREROCE_STATE_RESP_CONNECTION=4, 562 MAX_PRE_ROCE_CONN_STATE 563 }; 564 565 566 /* 567 * roce connection type: requestor/responder 568 */ 569 enum pre_roce_conn_type 570 { 571 PREROCE_CONN_TYPE_REQ=0, 572 PREROCE_CONN_TYPE_RESP=1, 573 MAX_PRE_ROCE_CONN_TYPE 574 }; 575 576 577 /* 578 * CQE of a regular requester completion 579 */ 580 struct pre_roce_cqe_requester 581 { 582 UCHAR type /* CQE type (0 in roce_cqe_requester) */; 583 UCHAR reserved0; 584 USHORT sq_cons /* Send-queue consumer */; 585 ULONG reserved1; 586 struct regpair qp_handle /* pointer to QP handle in driver memory */; 587 ULONG reserved2[4]; 588 }; 589 590 /* 591 * CQE of a regular responder completion 592 */ 593 struct pre_roce_cqe_responder 594 { 595 UCHAR type /* CQE type (1 in roce_cqe_responder) */; 596 UCHAR flags; 597 #define PRE_ROCE_CQE_RESPONDER_INVALIDATE_MASK 0x1 /* Set in case of SEND_WITH_INVALIDATE completion */ 598 #define PRE_ROCE_CQE_RESPONDER_INVALIDATE_SHIFT 0 599 #define PRE_ROCE_CQE_RESPONDER_SRQ_MASK 0x1 /* Set in case SRQ was used */ 600 #define PRE_ROCE_CQE_RESPONDER_SRQ_SHIFT 1 601 #define PRE_ROCE_CQE_RESPONDER_IMMEDIATE_MASK 0x1 /* Set in case immediate data */ 602 #define PRE_ROCE_CQE_RESPONDER_IMMEDIATE_SHIFT 2 603 #define PRE_ROCE_CQE_RESPONDER_RESERVED0_MASK 0x1F 604 #define PRE_ROCE_CQE_RESPONDER_RESERVED0_SHIFT 3 605 USHORT reserved1; 606 ULONG length /* Length of the data placed */; 607 struct regpair qp_handle /* pointer to QP handle in driver memory */; 608 struct regpair srq_handle /* pointer to SQR handle in driver memory (in case SRQ was used) */; 609 ULONG r_key /* The invalidated r_key in case of SEND_WITH_INVALIDATE */; 610 ULONG immData /* The immediate data in case on SEND_WITH_IMMEDIATE or RDMA_WRITE_WITH_IMMEDIATE */; 611 }; 612 613 /* 614 * CQE of an error notification 615 */ 616 struct pre_roce_cqe_error 617 { 618 UCHAR type /* CQE type (2/3 in roce_cqe_error) */; 619 UCHAR err_code; 620 USHORT reserved0; 621 ULONG err_data; 622 struct regpair qp_handle /* pointer to QP handle in driver memory */; 623 ULONG reserved1[4]; 624 }; 625 626 union pre_roce_cqe 627 { 628 struct pre_roce_cqe_requester req /* CQE of a regular requester completion */; 629 struct pre_roce_cqe_responder resp /* CQE of a regular responder completion */; 630 struct pre_roce_cqe_error err /* CQE of an error notification */; 631 }; 632 633 634 635 636 637 /* 638 * CQE type enumeration 639 */ 640 enum pre_roce_cqe_type 641 { 642 PREROCE_REQUESTER_COMP, 643 PREROCE_RESPONDER_COMP, 644 PREROCE_REQUSTER_ERR, 645 PREROCE_RESPONDER_ERR, 646 MAX_PRE_ROCE_CQE_TYPE 647 }; 648 649 650 struct pre_roce_eqe_data 651 { 652 ULONG cq_id; 653 USHORT cq_prod /* CQ producer index of the FW */; 654 USHORT reserved; 655 }; 656 657 658 /* 659 * opcodes for the event ring 660 */ 661 enum pre_roce_event_opcode 662 { 663 PREROCE_EVENT_UNUSED, 664 PREROCE_EVENT_COMP, 665 MAX_PRE_ROCE_EVENT_OPCODE 666 }; 667 668 669 /* 670 * MR state enum 671 */ 672 enum pre_roce_mr_state 673 { 674 PREROCE_FREE, 675 PREROCE_INVALID, 676 PREROCE_VALID, 677 MAX_PRE_ROCE_MR_STATE 678 }; 679 680 681 /* 682 * Scather/Gather element used for packets data placement/transmission 683 */ 684 struct pre_roce_sge 685 { 686 struct regpair va /* virtual address of SGE beginning */; 687 ULONG l_key /* local key of MR */; 688 ULONG length /* length of the sge */; 689 }; 690 691 692 /* 693 * Second WQEs for RMDA write 694 */ 695 struct pre_roce_sq_rdma_write_second_wqe 696 { 697 ULONG remote_key /* Remote key */; 698 struct regpair va /* Remote virtual address */; 699 ULONG reserved; 700 }; 701 702 703 /* 704 * SQ WQE req type enumeration 705 */ 706 enum pre_roce_sq_req_type 707 { 708 PREROCE_REQ_TYPE_SEND, 709 PREROCE_REQ_TYPE_SEND_WITH_INVALIDATE, 710 PREROCE_REQ_TYPE_SEND_WITH_IMMEDIATE, 711 PREROCE_REQ_TYPE_LOCAL_INVALIDATE, 712 PREROCE_REQ_TYPE_RDMA_WRITE, 713 PREROCE_REQ_TYPE_RDMA_WRITE_WITH_IMMEDIATE, 714 PREROCE_REQ_TYPE_INVALID, 715 MAX_PRE_ROCE_SQ_REQ_TYPE 716 }; 717 718 719 struct pre_roce_sq_wqe_struct 720 { 721 UCHAR req_type /* Type of WQE */; 722 UCHAR flags; 723 #define PRE_ROCE_SQ_WQE_STRUCT_COMP_FLAG_MASK 0x1 /* If set, completion will be generated when the WQE is completed */ 724 #define PRE_ROCE_SQ_WQE_STRUCT_COMP_FLAG_SHIFT 0 725 #define PRE_ROCE_SQ_WQE_STRUCT_RD_FENCE_FLAG_MASK 0x1 /* If set, all pending READ operations will be completed before start processing this WQE */ 726 #define PRE_ROCE_SQ_WQE_STRUCT_RD_FENCE_FLAG_SHIFT 1 727 #define PRE_ROCE_SQ_WQE_STRUCT_INV_FENCE_FLAG_MASK 0x1 /* If set, all pending LOCAL_INVALIDATE operations will be completed before start processing this WQE */ 728 #define PRE_ROCE_SQ_WQE_STRUCT_INV_FENCE_FLAG_SHIFT 2 729 #define PRE_ROCE_SQ_WQE_STRUCT_SE_FLAG_MASK 0x1 /* If set, signal the responder to generate a solicited event on this WQE */ 730 #define PRE_ROCE_SQ_WQE_STRUCT_SE_FLAG_SHIFT 3 731 #define PRE_ROCE_SQ_WQE_STRUCT_NUM_SGES_MASK 0x7 /* Number of SGEs following this WQE (up to 4) */ 732 #define PRE_ROCE_SQ_WQE_STRUCT_NUM_SGES_SHIFT 4 733 #define PRE_ROCE_SQ_WQE_STRUCT_RESERVED0_MASK 0x1 734 #define PRE_ROCE_SQ_WQE_STRUCT_RESERVED0_SHIFT 7 735 USHORT reserved1; 736 ULONG data_2_trans /* Total data to transfer in bytes */; 737 ULONG invalidate_key /* In case of SEND_WITH_INVALIDATE, this is the r_key to invalidate. In case of LOCAL_INVALIDATE, this is the l_key to invalidate */; 738 ULONG imm_data /* In case of send with immediate or RDMA write with immediate, this is the immediate data */; 739 }; 740 741 742 /* 743 * The roce task context of Mstorm 744 */ 745 struct ystorm_pre_roce_task_st_ctx 746 { 747 struct regpair temp[6]; 748 }; 749 750 struct e4_ystorm_pre_roce_task_ag_ctx 751 { 752 UCHAR reserved /* cdu_validation */; 753 UCHAR byte1 /* state */; 754 USHORT icid /* icid */; 755 UCHAR flags0; 756 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 757 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 758 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 759 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 760 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 761 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_BIT1_SHIFT 5 762 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */ 763 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_VALID_SHIFT 6 764 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 765 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_BIT3_SHIFT 7 766 UCHAR flags1; 767 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 768 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_CF0_SHIFT 0 769 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 770 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_CF1_SHIFT 2 771 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 772 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 773 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 774 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_SHIFT 6 775 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 776 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_SHIFT 7 777 UCHAR flags2; 778 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 779 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_BIT4_SHIFT 0 780 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_EQ_EN_MASK 0x1 /* rule0en */ 781 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_EQ_EN_SHIFT 1 782 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_NE_EN_MASK 0x1 /* rule1en */ 783 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_NE_EN_SHIFT 2 784 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_EQ_EN_MASK 0x1 /* rule2en */ 785 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_EQ_EN_SHIFT 3 786 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_NE_EN_MASK 0x1 /* rule3en */ 787 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_NE_EN_SHIFT 4 788 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 789 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_SHIFT 5 790 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 791 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_SHIFT 6 792 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 793 #define E4_YSTORM_PRE_ROCE_TASK_AG_CTX_RULE6EN_SHIFT 7 794 UCHAR rx_ref_count /* byte2 */; 795 ULONG mw_cnt /* reg0 */; 796 UCHAR rx_ref_count_th /* byte3 */; 797 UCHAR byte4 /* byte4 */; 798 USHORT word1 /* word1 */; 799 USHORT tx_ref_count /* word2 */; 800 USHORT tx_ref_count_th /* word3 */; 801 USHORT word4 /* word4 */; 802 USHORT word5 /* word5 */; 803 ULONG reg1 /* reg1 */; 804 ULONG reg2 /* reg2 */; 805 }; 806 807 struct e4_mstorm_pre_roce_task_ag_ctx 808 { 809 UCHAR reserved /* cdu_validation */; 810 UCHAR byte1 /* state */; 811 USHORT icid /* icid */; 812 UCHAR flags0; 813 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 814 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 815 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 816 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 817 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 818 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_BIT1_SHIFT 5 819 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */ 820 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_VALID_SHIFT 6 821 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 822 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_BIT3_SHIFT 7 823 UCHAR flags1; 824 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 825 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_CF0_SHIFT 0 826 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 827 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_CF1_SHIFT 2 828 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 829 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_CF2_SHIFT 4 830 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 831 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_SHIFT 6 832 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 833 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_SHIFT 7 834 UCHAR flags2; 835 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 836 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_CF2EN_SHIFT 0 837 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_EQ_EN_MASK 0x1 /* rule0en */ 838 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_EQ_EN_SHIFT 1 839 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_NE_EN_MASK 0x1 /* rule1en */ 840 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_NE_EN_SHIFT 2 841 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_EQ_EN_MASK 0x1 /* rule2en */ 842 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_EQ_EN_SHIFT 3 843 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_NE_EN_MASK 0x1 /* rule3en */ 844 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_NE_EN_SHIFT 4 845 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 846 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_SHIFT 5 847 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 848 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_SHIFT 6 849 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 850 #define E4_MSTORM_PRE_ROCE_TASK_AG_CTX_RULE6EN_SHIFT 7 851 UCHAR rx_ref_count /* byte2 */; 852 ULONG mw_cnt /* reg0 */; 853 UCHAR rx_ref_count_th /* byte3 */; 854 UCHAR byte4 /* byte4 */; 855 USHORT word1 /* word1 */; 856 USHORT tx_ref_count /* word2 */; 857 USHORT tx_ref_count_th /* word3 */; 858 USHORT word4 /* word4 */; 859 USHORT word5 /* word5 */; 860 ULONG reg1 /* reg1 */; 861 ULONG reg2 /* reg2 */; 862 }; 863 864 /* 865 * pre_roce task context 866 */ 867 struct pre_roce_task_context 868 { 869 struct ystorm_pre_roce_task_st_ctx ystorm_st_context /* ystorm storm context */; 870 struct regpair ystorm_st_padding[2] /* padding */; 871 struct e4_ystorm_pre_roce_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 872 struct e4_mstorm_pre_roce_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 873 struct mstorm_pre_roce_task_st_ctx mstorm_st_context /* mstorm storm context */; 874 struct regpair mstorm_st_padding[2] /* padding */; 875 }; 876 877 878 879 880 881 882 883 884 struct e4_mstorm_pre_roce_conn_ag_ctx 885 { 886 UCHAR reserved /* cdu_validation */; 887 UCHAR byte1 /* state */; 888 UCHAR flags0; 889 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 890 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 891 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 892 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 893 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 /* cf0 */ 894 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2 895 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 896 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_CF1_SHIFT 4 897 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 898 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_CF2_SHIFT 6 899 UCHAR flags1; 900 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 /* cf0en */ 901 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0 902 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 903 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 904 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 905 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 906 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 907 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3 908 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 909 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4 910 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 911 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5 912 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 /* rule3en */ 913 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6 914 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 915 #define E4_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7 916 USHORT rcq_cons /* word0 */; 917 USHORT rcq_cons_th /* word1 */; 918 ULONG reg0 /* reg0 */; 919 ULONG reg1 /* reg1 */; 920 }; 921 922 923 924 925 struct e4_tstorm_pre_roce_task_ag_ctx 926 { 927 UCHAR byte0 /* cdu_validation */; 928 UCHAR byte1 /* state */; 929 USHORT word0 /* icid */; 930 UCHAR flags0; 931 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 932 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_NIBBLE0_SHIFT 0 933 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 934 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT0_SHIFT 4 935 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 936 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT1_SHIFT 5 937 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 938 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT2_SHIFT 6 939 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 940 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT3_SHIFT 7 941 UCHAR flags1; 942 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 943 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT4_SHIFT 0 944 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 945 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT5_SHIFT 1 946 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 947 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF0_SHIFT 2 948 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 949 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF1_SHIFT 4 950 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 951 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF2_SHIFT 6 952 UCHAR flags2; 953 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 954 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF3_SHIFT 0 955 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF4_MASK 0x3 /* cf4 */ 956 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF4_SHIFT 2 957 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF5_MASK 0x3 /* cf5 */ 958 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF5_SHIFT 4 959 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF6_MASK 0x3 /* cf6 */ 960 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF6_SHIFT 6 961 UCHAR flags3; 962 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF7_MASK 0x3 /* cf7 */ 963 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF7_SHIFT 0 964 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 965 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_SHIFT 2 966 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 967 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_SHIFT 3 968 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 969 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF2EN_SHIFT 4 970 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 971 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF3EN_SHIFT 5 972 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 973 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF4EN_SHIFT 6 974 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 975 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF5EN_SHIFT 7 976 UCHAR flags4; 977 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 978 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF6EN_SHIFT 0 979 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 980 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_CF7EN_SHIFT 1 981 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 982 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE0EN_SHIFT 2 983 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 984 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE1EN_SHIFT 3 985 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 986 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE2EN_SHIFT 4 987 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 988 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE3EN_SHIFT 5 989 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 990 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_SHIFT 6 991 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 992 #define E4_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_SHIFT 7 993 UCHAR byte2 /* byte2 */; 994 USHORT word1 /* word1 */; 995 ULONG reg0 /* reg0 */; 996 UCHAR byte3 /* byte3 */; 997 UCHAR byte4 /* byte4 */; 998 USHORT word2 /* word2 */; 999 USHORT word3 /* word3 */; 1000 USHORT word4 /* word4 */; 1001 ULONG reg1 /* reg1 */; 1002 ULONG reg2 /* reg2 */; 1003 }; 1004 1005 1006 1007 struct e4_ustorm_pre_roce_task_ag_ctx 1008 { 1009 UCHAR byte0 /* cdu_validation */; 1010 UCHAR byte1 /* state */; 1011 USHORT word0 /* icid */; 1012 UCHAR flags0; 1013 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 1014 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_NIBBLE0_SHIFT 0 1015 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1016 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_BIT0_SHIFT 4 1017 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1018 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_BIT1_SHIFT 5 1019 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1020 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF0_SHIFT 6 1021 UCHAR flags1; 1022 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1023 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF1_SHIFT 0 1024 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1025 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF2_SHIFT 2 1026 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1027 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF3_SHIFT 4 1028 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1029 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF4_SHIFT 6 1030 UCHAR flags2; 1031 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1032 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_SHIFT 0 1033 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1034 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_SHIFT 1 1035 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1036 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF2EN_SHIFT 2 1037 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1038 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF3EN_SHIFT 3 1039 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1040 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_CF4EN_SHIFT 4 1041 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1042 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_RULE0EN_SHIFT 5 1043 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1044 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_RULE1EN_SHIFT 6 1045 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1046 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_RULE2EN_SHIFT 7 1047 UCHAR flags3; 1048 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1049 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_RULE3EN_SHIFT 0 1050 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1051 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_SHIFT 1 1052 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1053 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_SHIFT 2 1054 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1055 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_RULE6EN_SHIFT 3 1056 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_NIBBLE1_MASK 0xF /* nibble1 */ 1057 #define E4_USTORM_PRE_ROCE_TASK_AG_CTX_NIBBLE1_SHIFT 4 1058 ULONG reg0 /* reg0 */; 1059 ULONG reg1 /* reg1 */; 1060 ULONG reg2 /* reg2 */; 1061 ULONG reg3 /* reg3 */; 1062 ULONG reg4 /* reg4 */; 1063 ULONG reg5 /* reg5 */; 1064 UCHAR byte2 /* byte2 */; 1065 UCHAR byte3 /* byte3 */; 1066 USHORT word1 /* word1 */; 1067 USHORT word2 /* word2 */; 1068 USHORT word3 /* word3 */; 1069 ULONG reg6 /* reg6 */; 1070 ULONG reg7 /* reg7 */; 1071 }; 1072 1073 1074 1075 struct e4_ystorm_pre_roce_conn_ag_ctx 1076 { 1077 UCHAR byte0 /* cdu_validation */; 1078 UCHAR byte1 /* state */; 1079 UCHAR flags0; 1080 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1081 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_BIT0_SHIFT 0 1082 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1083 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 1084 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1085 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_CF0_SHIFT 2 1086 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1087 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_CF1_SHIFT 4 1088 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1089 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_CF2_SHIFT 6 1090 UCHAR flags1; 1091 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1092 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0 1093 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1094 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 1095 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1096 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 1097 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1098 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3 1099 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1100 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4 1101 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1102 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5 1103 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1104 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6 1105 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1106 #define E4_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7 1107 UCHAR byte2 /* byte2 */; 1108 UCHAR byte3 /* byte3 */; 1109 USHORT word0 /* word0 */; 1110 ULONG reg0 /* reg0 */; 1111 ULONG reg1 /* reg1 */; 1112 USHORT word1 /* word1 */; 1113 USHORT word2 /* word2 */; 1114 USHORT word3 /* word3 */; 1115 USHORT word4 /* word4 */; 1116 ULONG reg2 /* reg2 */; 1117 ULONG reg3 /* reg3 */; 1118 }; 1119 1120 1121 1122 struct e5_mstorm_pre_roce_conn_ag_ctx 1123 { 1124 UCHAR reserved /* cdu_validation */; 1125 UCHAR byte1 /* state_and_core_id */; 1126 UCHAR flags0; 1127 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1128 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1129 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1130 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 1131 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 /* cf0 */ 1132 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2 1133 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1134 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_CF1_SHIFT 4 1135 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1136 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_CF2_SHIFT 6 1137 UCHAR flags1; 1138 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 /* cf0en */ 1139 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0 1140 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1141 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 1142 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1143 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 1144 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1145 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3 1146 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1147 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4 1148 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1149 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5 1150 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 /* rule3en */ 1151 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6 1152 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1153 #define E5_MSTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7 1154 USHORT rcq_cons /* word0 */; 1155 USHORT rcq_cons_th /* word1 */; 1156 ULONG reg0 /* reg0 */; 1157 ULONG reg1 /* reg1 */; 1158 }; 1159 1160 1161 struct e5_mstorm_pre_roce_task_ag_ctx 1162 { 1163 UCHAR reserved /* cdu_validation */; 1164 UCHAR byte1 /* state_and_core_id */; 1165 USHORT icid /* icid */; 1166 UCHAR flags0; 1167 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 1168 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 1169 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1170 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 1171 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1172 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_BIT1_SHIFT 5 1173 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */ 1174 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_VALID_SHIFT 6 1175 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1176 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_BIT3_SHIFT 7 1177 UCHAR flags1; 1178 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1179 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_CF0_SHIFT 0 1180 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1181 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_CF1_SHIFT 2 1182 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1183 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_CF2_SHIFT 4 1184 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1185 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_SHIFT 6 1186 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1187 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_SHIFT 7 1188 UCHAR flags2; 1189 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1190 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_CF2EN_SHIFT 0 1191 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_EQ_EN_MASK 0x1 /* rule0en */ 1192 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_EQ_EN_SHIFT 1 1193 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_NE_EN_MASK 0x1 /* rule1en */ 1194 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_NE_EN_SHIFT 2 1195 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_EQ_EN_MASK 0x1 /* rule2en */ 1196 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_EQ_EN_SHIFT 3 1197 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_NE_EN_MASK 0x1 /* rule3en */ 1198 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_NE_EN_SHIFT 4 1199 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1200 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_SHIFT 5 1201 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1202 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_SHIFT 6 1203 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1204 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_RULE6EN_SHIFT 7 1205 UCHAR flags3; 1206 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit4 */ 1207 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 1208 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 1209 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 1210 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 1211 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 1212 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 1213 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 1214 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 1215 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 1216 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 1217 #define E5_MSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 1218 ULONG mw_cnt /* reg0 */; 1219 UCHAR rx_ref_count /* byte2 */; 1220 UCHAR rx_ref_count_th /* byte3 */; 1221 UCHAR byte4 /* byte4 */; 1222 UCHAR e4_reserved7 /* byte5 */; 1223 USHORT word1 /* regpair0 */; 1224 USHORT tx_ref_count /* word2 */; 1225 USHORT tx_ref_count_th /* word3 */; 1226 USHORT word4 /* word4 */; 1227 USHORT word5 /* regpair1 */; 1228 USHORT e4_reserved8 /* word6 */; 1229 ULONG reg1 /* reg1 */; 1230 }; 1231 1232 1233 struct e5_tstorm_pre_roce_conn_ag_ctx 1234 { 1235 UCHAR reserved0 /* cdu_validation */; 1236 UCHAR state_and_core_id /* state_and_core_id */; 1237 UCHAR flags0; 1238 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1239 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1240 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1241 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 1242 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1243 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT2_SHIFT 2 1244 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1245 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT3_SHIFT 3 1246 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1247 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT4_SHIFT 4 1248 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1249 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_BIT5_SHIFT 5 1250 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMEOUT_MASK 0x3 /* timer0cf */ 1251 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMEOUT_SHIFT 6 1252 UCHAR flags1; 1253 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* timer1cf */ 1254 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 1255 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_SND_DONE_MASK 0x3 /* timer2cf */ 1256 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_SND_DONE_SHIFT 2 1257 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 1258 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 1259 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED_CF_MASK 0x3 /* cf4 */ 1260 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED_CF_SHIFT 6 1261 UCHAR flags2; 1262 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 /* cf5 */ 1263 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_SHIFT 0 1264 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1265 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF6_SHIFT 2 1266 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1267 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF7_SHIFT 4 1268 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1269 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF8_SHIFT 6 1270 UCHAR flags3; 1271 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1272 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF9_SHIFT 0 1273 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1274 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF10_SHIFT 2 1275 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMEOUT_EN_MASK 0x1 /* cf0en */ 1276 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMEOUT_EN_SHIFT 4 1277 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf1en */ 1278 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 1279 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_SND_DONE_EN_MASK 0x1 /* cf2en */ 1280 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_SND_DONE_EN_SHIFT 6 1281 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 1282 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 1283 UCHAR flags4; 1284 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED_CF_EN_MASK 0x1 /* cf4en */ 1285 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED_CF_EN_SHIFT 0 1286 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 /* cf5en */ 1287 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 1288 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1289 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF6EN_SHIFT 2 1290 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1291 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF7EN_SHIFT 3 1292 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1293 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF8EN_SHIFT 4 1294 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1295 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF9EN_SHIFT 5 1296 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1297 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_CF10EN_SHIFT 6 1298 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RXMIT_SEQ_EN_MASK 0x1 /* rule0en */ 1299 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RXMIT_SEQ_EN_SHIFT 7 1300 UCHAR flags5; 1301 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RXMIT_SEQ_LAG_EN_MASK 0x1 /* rule1en */ 1302 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RXMIT_SEQ_LAG_EN_SHIFT 0 1303 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1304 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 1 1305 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1306 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 2 1307 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1308 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 3 1309 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1310 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 4 1311 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1312 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 5 1313 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1314 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 6 1315 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1316 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_RULE8EN_SHIFT 7 1317 UCHAR flags6; 1318 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1319 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1320 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1321 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1322 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1323 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1324 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1325 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1326 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1327 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1328 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1329 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1330 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1331 #define E5_TSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1332 UCHAR rxmit_seq /* byte2 */; 1333 USHORT rq_prod /* word0 */; 1334 ULONG reg0 /* reg0 */; 1335 ULONG reg1 /* reg1 */; 1336 ULONG snd_max_psn /* reg2 */; 1337 ULONG orq_prod /* reg3 */; 1338 ULONG irq_cons /* reg4 */; 1339 ULONG snd_nxt_psn /* reg5 */; 1340 ULONG reg6 /* reg6 */; 1341 ULONG irq_rxmit_psn_echo /* reg7 */; 1342 ULONG trcq_cons /* reg8 */; 1343 UCHAR rxmit_seq_echo /* byte3 */; 1344 UCHAR byte4 /* byte4 */; 1345 UCHAR byte5 /* byte5 */; 1346 UCHAR e4_reserved8 /* byte6 */; 1347 USHORT word1 /* word1 */; 1348 USHORT conn_dpi /* conn_dpi */; 1349 ULONG reg9 /* reg9 */; 1350 USHORT word3 /* word3 */; 1351 USHORT e4_reserved9 /* word4 */; 1352 }; 1353 1354 1355 struct e5_tstorm_pre_roce_task_ag_ctx 1356 { 1357 UCHAR byte0 /* cdu_validation */; 1358 UCHAR byte1 /* state_and_core_id */; 1359 USHORT word0 /* icid */; 1360 UCHAR flags0; 1361 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 1362 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_NIBBLE0_SHIFT 0 1363 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1364 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT0_SHIFT 4 1365 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1366 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT1_SHIFT 5 1367 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1368 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT2_SHIFT 6 1369 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1370 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT3_SHIFT 7 1371 UCHAR flags1; 1372 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1373 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT4_SHIFT 0 1374 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1375 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_BIT5_SHIFT 1 1376 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1377 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF0_SHIFT 2 1378 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1379 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF1_SHIFT 4 1380 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1381 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF2_SHIFT 6 1382 UCHAR flags2; 1383 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1384 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF3_SHIFT 0 1385 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1386 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF4_SHIFT 2 1387 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1388 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF5_SHIFT 4 1389 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1390 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF6_SHIFT 6 1391 UCHAR flags3; 1392 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1393 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF7_SHIFT 0 1394 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1395 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_SHIFT 2 1396 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1397 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_SHIFT 3 1398 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1399 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF2EN_SHIFT 4 1400 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1401 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF3EN_SHIFT 5 1402 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1403 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF4EN_SHIFT 6 1404 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1405 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF5EN_SHIFT 7 1406 UCHAR flags4; 1407 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1408 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF6EN_SHIFT 0 1409 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1410 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_CF7EN_SHIFT 1 1411 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1412 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE0EN_SHIFT 2 1413 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1414 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE1EN_SHIFT 3 1415 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1416 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE2EN_SHIFT 4 1417 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1418 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE3EN_SHIFT 5 1419 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1420 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_SHIFT 6 1421 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1422 #define E5_TSTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_SHIFT 7 1423 UCHAR byte2 /* byte2 */; 1424 USHORT word1 /* word1 */; 1425 ULONG reg0 /* reg0 */; 1426 UCHAR byte3 /* regpair0 */; 1427 UCHAR byte4 /* byte4 */; 1428 USHORT word2 /* word2 */; 1429 USHORT word3 /* word3 */; 1430 USHORT word4 /* word4 */; 1431 ULONG reg1 /* regpair1 */; 1432 ULONG reg2 /* reg2 */; 1433 }; 1434 1435 1436 struct e5_ustorm_pre_roce_conn_ag_ctx 1437 { 1438 UCHAR reserved /* cdu_validation */; 1439 UCHAR byte1 /* state_and_core_id */; 1440 UCHAR flags0; 1441 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1442 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1443 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1444 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 1445 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1446 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF0_SHIFT 2 1447 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1448 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF1_SHIFT 4 1449 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1450 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF2_SHIFT 6 1451 UCHAR flags1; 1452 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1453 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF3_SHIFT 0 1454 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 1455 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 1456 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 1457 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 1458 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1459 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF6_SHIFT 6 1460 UCHAR flags2; 1461 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1462 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0 1463 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1464 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 1465 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1466 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 1467 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1468 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF3EN_SHIFT 3 1469 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 1470 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 1471 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 1472 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 1473 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1474 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CF6EN_SHIFT 6 1475 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 1476 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 1477 UCHAR flags3; 1478 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 1479 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_CQ_EN_SHIFT 0 1480 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1481 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 1 1482 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1483 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 2 1484 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1485 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 3 1486 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1487 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 4 1488 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1489 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 5 1490 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1491 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 6 1492 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1493 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_RULE8EN_SHIFT 7 1494 UCHAR flags4; 1495 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1496 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1497 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1498 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1499 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1500 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1501 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1502 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1503 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1504 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1505 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1506 #define E5_USTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1507 UCHAR byte2 /* byte2 */; 1508 USHORT conn_dpi /* conn_dpi */; 1509 USHORT word1 /* word1 */; 1510 ULONG cq_cons /* reg0 */; 1511 ULONG cq_se_prod /* reg1 */; 1512 ULONG cq_prod /* reg2 */; 1513 ULONG reg3 /* reg3 */; 1514 USHORT word2 /* word2 */; 1515 USHORT word3 /* word3 */; 1516 }; 1517 1518 1519 struct e5_ustorm_pre_roce_task_ag_ctx 1520 { 1521 UCHAR byte0 /* cdu_validation */; 1522 UCHAR byte1 /* state_and_core_id */; 1523 USHORT word0 /* icid */; 1524 UCHAR flags0; 1525 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 1526 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_NIBBLE0_SHIFT 0 1527 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1528 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_BIT0_SHIFT 4 1529 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1530 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_BIT1_SHIFT 5 1531 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1532 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF0_SHIFT 6 1533 UCHAR flags1; 1534 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1535 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF1_SHIFT 0 1536 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1537 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF2_SHIFT 2 1538 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1539 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF3_SHIFT 4 1540 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF4_MASK 0x3 /* dif_error_cf */ 1541 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF4_SHIFT 6 1542 UCHAR flags2; 1543 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1544 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_SHIFT 0 1545 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1546 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_SHIFT 1 1547 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1548 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF2EN_SHIFT 2 1549 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1550 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF3EN_SHIFT 3 1551 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1552 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_CF4EN_SHIFT 4 1553 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1554 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_RULE0EN_SHIFT 5 1555 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1556 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_RULE1EN_SHIFT 6 1557 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1558 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_RULE2EN_SHIFT 7 1559 UCHAR flags3; 1560 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1561 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_RULE3EN_SHIFT 0 1562 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1563 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_SHIFT 1 1564 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1565 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_SHIFT 2 1566 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1567 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_RULE6EN_SHIFT 3 1568 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1569 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED1_SHIFT 4 1570 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1571 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED2_SHIFT 5 1572 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit4 */ 1573 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED3_SHIFT 6 1574 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* rule7en */ 1575 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED4_SHIFT 7 1576 UCHAR flags4; 1577 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED5_MASK 0x3 /* cf5 */ 1578 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED5_SHIFT 0 1579 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf5en */ 1580 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED6_SHIFT 2 1581 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule8en */ 1582 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED7_SHIFT 3 1583 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_NIBBLE1_MASK 0xF /* dif_error_type */ 1584 #define E5_USTORM_PRE_ROCE_TASK_AG_CTX_NIBBLE1_SHIFT 4 1585 UCHAR byte2 /* byte2 */; 1586 UCHAR byte3 /* byte3 */; 1587 UCHAR e4_reserved8 /* byte4 */; 1588 ULONG reg0 /* dif_err_intervals */; 1589 ULONG reg1 /* dif_error_1st_interval */; 1590 ULONG reg2 /* reg2 */; 1591 ULONG reg3 /* reg3 */; 1592 ULONG reg4 /* reg4 */; 1593 ULONG reg5 /* reg5 */; 1594 USHORT word1 /* word1 */; 1595 USHORT word2 /* word2 */; 1596 ULONG reg6 /* reg6 */; 1597 ULONG reg7 /* reg7 */; 1598 }; 1599 1600 1601 struct e5_xstorm_pre_roce_conn_ag_ctx 1602 { 1603 UCHAR reserved0 /* cdu_validation */; 1604 UCHAR state_and_core_id /* state_and_core_id */; 1605 UCHAR flags0; 1606 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1607 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1608 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 1609 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED1_SHIFT 1 1610 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 1611 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED2_SHIFT 2 1612 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1613 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1614 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 1615 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED3_SHIFT 4 1616 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 1617 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED4_SHIFT 5 1618 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 1619 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED5_SHIFT 6 1620 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 1621 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED6_SHIFT 7 1622 UCHAR flags1; 1623 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 1624 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED7_SHIFT 0 1625 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 1626 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED8_SHIFT 1 1627 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DA_ENABLE_MASK 0x1 /* bit10 */ 1628 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DA_ENABLE_SHIFT 2 1629 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1630 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT11_SHIFT 3 1631 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1632 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT12_SHIFT 4 1633 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 1634 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT13_SHIFT 5 1635 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 1636 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT14_SHIFT 6 1637 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT15_MASK 0x1 /* bit15 */ 1638 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT15_SHIFT 7 1639 UCHAR flags2; 1640 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1641 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF0_SHIFT 0 1642 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1643 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF1_SHIFT 2 1644 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1645 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF2_SHIFT 4 1646 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 1647 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 1648 UCHAR flags3; 1649 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SET_DA_TIMER_CF_MASK 0x3 /* cf4 */ 1650 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SET_DA_TIMER_CF_SHIFT 0 1651 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 /* cf5 */ 1652 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 2 1653 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_IRQ_RXMIT_CF_MASK 0x3 /* cf6 */ 1654 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_IRQ_RXMIT_CF_SHIFT 4 1655 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_TMR_RWND_CF_MASK 0x3 /* cf7 */ 1656 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_TMR_RWND_CF_SHIFT 6 1657 UCHAR flags4; 1658 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 /* cf8 */ 1659 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 0 1660 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RNR_CF_MASK 0x3 /* cf9 */ 1661 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RNR_CF_SHIFT 2 1662 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1663 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF10_SHIFT 4 1664 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1665 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF11_SHIFT 6 1666 UCHAR flags5; 1667 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1668 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF12_SHIFT 0 1669 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1670 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF13_SHIFT 2 1671 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1672 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF14_SHIFT 4 1673 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1674 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF15_SHIFT 6 1675 UCHAR flags6; 1676 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_CF_MASK 0x3 /* cf16 */ 1677 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_CF_SHIFT 0 1678 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1679 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF17_SHIFT 2 1680 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1681 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF18_SHIFT 4 1682 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 /* cf19 */ 1683 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 1684 UCHAR flags7; 1685 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 1686 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 1687 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 1688 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED10_SHIFT 2 1689 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1690 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1691 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1692 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF0EN_SHIFT 6 1693 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1694 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_SHIFT 7 1695 UCHAR flags8; 1696 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1697 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_SHIFT 0 1698 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 1699 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 1700 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DA_EXPIRED_MASK 0x1 /* cf4en */ 1701 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DA_EXPIRED_SHIFT 2 1702 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 /* cf5en */ 1703 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 3 1704 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_IRQ_RXMIT_CF_EN_MASK 0x1 /* cf6en */ 1705 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_IRQ_RXMIT_CF_EN_SHIFT 4 1706 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_TMR_RWND_CF_EN_MASK 0x1 /* cf7en */ 1707 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_TMR_RWND_CF_EN_SHIFT 5 1708 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 /* cf8en */ 1709 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 6 1710 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RNR_CF_EN_MASK 0x1 /* cf9en */ 1711 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_RNR_CF_EN_SHIFT 7 1712 UCHAR flags9; 1713 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1714 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF10EN_SHIFT 0 1715 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1716 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF11EN_SHIFT 1 1717 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1718 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF12EN_SHIFT 2 1719 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1720 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF13EN_SHIFT 3 1721 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 1722 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF14EN_SHIFT 4 1723 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1724 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF15EN_SHIFT 5 1725 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_CF_EN_MASK 0x1 /* cf16en */ 1726 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_INV_STAG_CF_EN_SHIFT 6 1727 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1728 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF17EN_SHIFT 7 1729 UCHAR flags10; 1730 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1731 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_CF18EN_SHIFT 0 1732 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 /* cf19en */ 1733 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 1734 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 1735 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 1736 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 1737 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED11_SHIFT 3 1738 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1739 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1740 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DPM_DONE_CF_EN_MASK 0x1 /* cf23en */ 1741 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DPM_DONE_CF_EN_SHIFT 5 1742 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 1743 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED12_SHIFT 6 1744 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 1745 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED13_SHIFT 7 1746 UCHAR flags11; 1747 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 1748 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED14_SHIFT 0 1749 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 1750 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED15_SHIFT 1 1751 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED16_MASK 0x1 /* rule4en */ 1752 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED16_SHIFT 2 1753 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DA_CNT_EN_MASK 0x1 /* rule5en */ 1754 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DA_CNT_EN_SHIFT 3 1755 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1756 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 4 1757 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_UNA_EN_MASK 0x1 /* rule7en */ 1758 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SND_UNA_EN_SHIFT 5 1759 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1760 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1761 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1762 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE9EN_SHIFT 7 1763 UCHAR flags12; 1764 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 /* rule10en */ 1765 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 1766 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1767 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE11EN_SHIFT 1 1768 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1769 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1770 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1771 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1772 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SQ_CMP_CONS_EN_MASK 0x1 /* rule14en */ 1773 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SQ_CMP_CONS_EN_SHIFT 4 1774 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SNDLSN_NE_SNDSSN_EN_MASK 0x1 /* rule15en */ 1775 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_SNDLSN_NE_SNDSSN_EN_SHIFT 5 1776 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 1777 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE16EN_SHIFT 6 1778 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 1779 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RULE17EN_SHIFT 7 1780 UCHAR flags13; 1781 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RCQ_PROD_EN_MASK 0x1 /* rule18en */ 1782 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_RCQ_PROD_EN_SHIFT 0 1783 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_HQ_EN_MASK 0x1 /* rule19en */ 1784 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_HQ_EN_SHIFT 1 1785 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1786 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1787 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1788 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1789 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1790 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1791 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1792 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1793 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1794 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1795 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1796 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1797 UCHAR flags14; 1798 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_MIGRATION_MASK 0x1 /* bit16 */ 1799 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_MIGRATION_SHIFT 0 1800 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1801 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_BIT17_SHIFT 1 1802 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 1803 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 1804 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 1805 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 1806 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1807 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 1808 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DPM_DONE_CF_MASK 0x3 /* cf23 */ 1809 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_DPM_DONE_CF_SHIFT 6 1810 UCHAR da_mode /* byte2 */; 1811 USHORT physical_q0 /* physical_q0 */; 1812 USHORT word1 /* physical_q1 */; 1813 USHORT sq_cmp_cons /* physical_q2 */; 1814 USHORT sq_cons /* word3 */; 1815 USHORT sq_prod /* word4 */; 1816 USHORT word5 /* word5 */; 1817 USHORT conn_dpi /* conn_dpi */; 1818 UCHAR da_cnt /* byte3 */; 1819 UCHAR snd_syn /* byte4 */; 1820 UCHAR da_threshold /* byte5 */; 1821 UCHAR da_timeout_value /* byte6 */; 1822 ULONG snd_una_psn /* reg0 */; 1823 ULONG snd_una_psn_th /* reg1 */; 1824 ULONG snd_lsn /* reg2 */; 1825 ULONG snd_nxt_psn /* reg3 */; 1826 ULONG reg4 /* reg4 */; 1827 ULONG snd_ssn /* cf_array0 */; 1828 ULONG irq_rxmit_psn /* cf_array1 */; 1829 UCHAR flags15; 1830 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit22 */ 1831 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1832 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit23 */ 1833 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1834 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */ 1835 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1836 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */ 1837 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1838 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */ 1839 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1840 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */ 1841 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1842 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */ 1843 #define E5_XSTORM_PRE_ROCE_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1844 UCHAR rxmit_cmd_seq /* byte7 */; 1845 USHORT rcq_prod /* word7 */; 1846 USHORT rcq_prod_th /* word8 */; 1847 USHORT hq_cons_th /* word9 */; 1848 USHORT hq_cons /* word10 */; 1849 USHORT word11 /* word11 */; 1850 ULONG ack_msn_syn_to_fe /* reg7 */; 1851 ULONG ack_psn_to_fe /* reg8 */; 1852 ULONG inv_stag /* reg9 */; 1853 UCHAR rxmit_seq /* byte8 */; 1854 UCHAR byte9 /* byte9 */; 1855 UCHAR byte10 /* byte10 */; 1856 UCHAR byte11 /* byte11 */; 1857 UCHAR byte12 /* byte12 */; 1858 UCHAR byte13 /* byte13 */; 1859 UCHAR byte14 /* byte14 */; 1860 UCHAR byte15 /* byte15 */; 1861 }; 1862 1863 1864 struct e5_ystorm_pre_roce_conn_ag_ctx 1865 { 1866 UCHAR byte0 /* cdu_validation */; 1867 UCHAR byte1 /* state_and_core_id */; 1868 UCHAR flags0; 1869 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1870 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_BIT0_SHIFT 0 1871 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1872 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 1873 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1874 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_CF0_SHIFT 2 1875 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1876 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_CF1_SHIFT 4 1877 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1878 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_CF2_SHIFT 6 1879 UCHAR flags1; 1880 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1881 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0 1882 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1883 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 1884 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1885 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 1886 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1887 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3 1888 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1889 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4 1890 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1891 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5 1892 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1893 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6 1894 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1895 #define E5_YSTORM_PRE_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7 1896 UCHAR byte2 /* byte2 */; 1897 UCHAR byte3 /* byte3 */; 1898 USHORT word0 /* word0 */; 1899 ULONG reg0 /* reg0 */; 1900 ULONG reg1 /* reg1 */; 1901 USHORT word1 /* word1 */; 1902 USHORT word2 /* word2 */; 1903 USHORT word3 /* word3 */; 1904 USHORT word4 /* word4 */; 1905 ULONG reg2 /* reg2 */; 1906 ULONG reg3 /* reg3 */; 1907 }; 1908 1909 1910 struct e5_ystorm_pre_roce_task_ag_ctx 1911 { 1912 UCHAR reserved /* cdu_validation */; 1913 UCHAR byte1 /* state_and_core_id */; 1914 USHORT icid /* icid */; 1915 UCHAR flags0; 1916 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 1917 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 1918 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1919 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 1920 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1921 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_BIT1_SHIFT 5 1922 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */ 1923 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_VALID_SHIFT 6 1924 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1925 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_BIT3_SHIFT 7 1926 UCHAR flags1; 1927 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1928 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_CF0_SHIFT 0 1929 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1930 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_CF1_SHIFT 2 1931 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 1932 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 1933 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1934 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_CF0EN_SHIFT 6 1935 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1936 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_CF1EN_SHIFT 7 1937 UCHAR flags2; 1938 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1939 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_BIT4_SHIFT 0 1940 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_EQ_EN_MASK 0x1 /* rule0en */ 1941 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_EQ_EN_SHIFT 1 1942 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_NE_EN_MASK 0x1 /* rule1en */ 1943 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_RX_REF_CNT_NE_EN_SHIFT 2 1944 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_EQ_EN_MASK 0x1 /* rule2en */ 1945 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_EQ_EN_SHIFT 3 1946 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_NE_EN_MASK 0x1 /* rule3en */ 1947 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_TX_REF_CNT_NE_EN_SHIFT 4 1948 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1949 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_RULE4EN_SHIFT 5 1950 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1951 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_RULE5EN_SHIFT 6 1952 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1953 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_RULE6EN_SHIFT 7 1954 UCHAR flags3; 1955 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit5 */ 1956 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 1957 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 1958 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 1959 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 1960 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 1961 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 1962 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 1963 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 1964 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 1965 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 1966 #define E5_YSTORM_PRE_ROCE_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 1967 ULONG mw_cnt /* reg0 */; 1968 UCHAR rx_ref_count /* byte2 */; 1969 UCHAR rx_ref_count_th /* byte3 */; 1970 UCHAR byte4 /* byte4 */; 1971 UCHAR e4_reserved7 /* byte5 */; 1972 USHORT word1 /* word1 */; 1973 USHORT tx_ref_count /* word2 */; 1974 USHORT tx_ref_count_th /* word3 */; 1975 USHORT word4 /* word4 */; 1976 USHORT word5 /* word5 */; 1977 USHORT e4_reserved8 /* word6 */; 1978 ULONG reg1 /* reg1 */; 1979 }; 1980 1981 1982 /* 1983 * Pre-Roce doorbell data 1984 */ 1985 struct pre_roce_db_data 1986 { 1987 UCHAR params; 1988 #define PRE_ROCE_DB_DATA_DEST_MASK 0x3 /* destination of doorbell (use enum db_dest) */ 1989 #define PRE_ROCE_DB_DATA_DEST_SHIFT 0 1990 #define PRE_ROCE_DB_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 1991 #define PRE_ROCE_DB_DATA_AGG_CMD_SHIFT 2 1992 #define PRE_ROCE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */ 1993 #define PRE_ROCE_DB_DATA_BYPASS_EN_SHIFT 4 1994 #define PRE_ROCE_DB_DATA_RESERVED_MASK 0x1 1995 #define PRE_ROCE_DB_DATA_RESERVED_SHIFT 5 1996 #define PRE_ROCE_DB_DATA_AGG_VAL_SEL_MASK 0x3 /* aggregative value selection */ 1997 #define PRE_ROCE_DB_DATA_AGG_VAL_SEL_SHIFT 6 1998 UCHAR agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */; 1999 USHORT prod_val; 2000 }; 2001 2002 2003 /* 2004 * Pre-RoCE doorbell data for SQ and RQ 2005 */ 2006 struct pre_roce_pwm_val16_data 2007 { 2008 USHORT icid /* internal CID */; 2009 USHORT prod_val /* aggregated value to update */; 2010 }; 2011 2012 2013 /* 2014 * Pre-RoCE doorbell data for CQ 2015 */ 2016 struct pre_roce_pwm_val32_data 2017 { 2018 USHORT icid /* internal CID */; 2019 UCHAR agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */; 2020 UCHAR params; 2021 #define PRE_ROCE_PWM_VAL32_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 2022 #define PRE_ROCE_PWM_VAL32_DATA_AGG_CMD_SHIFT 0 2023 #define PRE_ROCE_PWM_VAL32_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */ 2024 #define PRE_ROCE_PWM_VAL32_DATA_BYPASS_EN_SHIFT 2 2025 #define PRE_ROCE_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_MASK 0x1 /* Connection type is iWARP */ 2026 #define PRE_ROCE_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_SHIFT 3 2027 #define PRE_ROCE_PWM_VAL32_DATA_RESERVED_MASK 0xF 2028 #define PRE_ROCE_PWM_VAL32_DATA_RESERVED_SHIFT 4 2029 ULONG cq_cons_val /* aggregated value to update */; 2030 }; 2031 2032 #endif /* __PREROCE__ */ 2033