1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 */
5
6 #include <linux/debugfs.h>
7
8 #include "g4x_dp.h"
9 #include "i915_drv.h"
10 #include "i915_reg.h"
11 #include "intel_de.h"
12 #include "intel_display_power_well.h"
13 #include "intel_display_types.h"
14 #include "intel_dp.h"
15 #include "intel_dpio_phy.h"
16 #include "intel_dpll.h"
17 #include "intel_lvds.h"
18 #include "intel_lvds_regs.h"
19 #include "intel_pps.h"
20 #include "intel_pps_regs.h"
21 #include "intel_quirks.h"
22
23 static void vlv_steal_power_sequencer(struct intel_display *display,
24 enum pipe pipe);
25
26 static void pps_init_delays(struct intel_dp *intel_dp);
27 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
28
pps_name(struct intel_dp * intel_dp)29 static const char *pps_name(struct intel_dp *intel_dp)
30 {
31 struct intel_display *display = to_intel_display(intel_dp);
32 struct intel_pps *pps = &intel_dp->pps;
33
34 if (display->platform.valleyview || display->platform.cherryview) {
35 switch (pps->vlv_pps_pipe) {
36 case INVALID_PIPE:
37 /*
38 * FIXME would be nice if we can guarantee
39 * to always have a valid PPS when calling this.
40 */
41 return "PPS <none>";
42 case PIPE_A:
43 return "PPS A";
44 case PIPE_B:
45 return "PPS B";
46 default:
47 MISSING_CASE(pps->vlv_pps_pipe);
48 break;
49 }
50 } else {
51 switch (pps->pps_idx) {
52 case 0:
53 return "PPS 0";
54 case 1:
55 return "PPS 1";
56 default:
57 MISSING_CASE(pps->pps_idx);
58 break;
59 }
60 }
61
62 return "PPS <invalid>";
63 }
64
intel_pps_lock(struct intel_dp * intel_dp)65 intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
66 {
67 struct intel_display *display = to_intel_display(intel_dp);
68 struct drm_i915_private *dev_priv = to_i915(display->drm);
69 intel_wakeref_t wakeref;
70
71 /*
72 * See vlv_pps_reset_all() why we need a power domain reference here.
73 */
74 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
75 mutex_lock(&display->pps.mutex);
76
77 return wakeref;
78 }
79
intel_pps_unlock(struct intel_dp * intel_dp,intel_wakeref_t wakeref)80 intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
81 intel_wakeref_t wakeref)
82 {
83 struct intel_display *display = to_intel_display(intel_dp);
84 struct drm_i915_private *dev_priv = to_i915(display->drm);
85
86 mutex_unlock(&display->pps.mutex);
87 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
88
89 return NULL;
90 }
91
92 static void
vlv_power_sequencer_kick(struct intel_dp * intel_dp)93 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
94 {
95 struct intel_display *display = to_intel_display(intel_dp);
96 struct drm_i915_private *dev_priv = to_i915(display->drm);
97 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
98 enum pipe pipe = intel_dp->pps.vlv_pps_pipe;
99 bool pll_enabled, release_cl_override = false;
100 enum dpio_phy phy = vlv_pipe_to_phy(pipe);
101 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
102 u32 DP;
103
104 if (drm_WARN(display->drm,
105 intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN,
106 "skipping %s kick due to [ENCODER:%d:%s] being active\n",
107 pps_name(intel_dp),
108 dig_port->base.base.base.id, dig_port->base.base.name))
109 return;
110
111 drm_dbg_kms(display->drm,
112 "kicking %s for [ENCODER:%d:%s]\n",
113 pps_name(intel_dp),
114 dig_port->base.base.base.id, dig_port->base.base.name);
115
116 /* Preserve the BIOS-computed detected bit. This is
117 * supposed to be read-only.
118 */
119 DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;
120 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
121 DP |= DP_PORT_WIDTH(1);
122 DP |= DP_LINK_TRAIN_PAT_1;
123
124 if (display->platform.cherryview)
125 DP |= DP_PIPE_SEL_CHV(pipe);
126 else
127 DP |= DP_PIPE_SEL(pipe);
128
129 pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;
130
131 /*
132 * The DPLL for the pipe must be enabled for this to work.
133 * So enable temporarily it if it's not already enabled.
134 */
135 if (!pll_enabled) {
136 release_cl_override = display->platform.cherryview &&
137 !chv_phy_powergate_ch(display, phy, ch, true);
138
139 if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
140 drm_err(display->drm,
141 "Failed to force on PLL for pipe %c!\n",
142 pipe_name(pipe));
143 return;
144 }
145 }
146
147 /*
148 * Similar magic as in intel_dp_enable_port().
149 * We _must_ do this port enable + disable trick
150 * to make this power sequencer lock onto the port.
151 * Otherwise even VDD force bit won't work.
152 */
153 intel_de_write(display, intel_dp->output_reg, DP);
154 intel_de_posting_read(display, intel_dp->output_reg);
155
156 intel_de_write(display, intel_dp->output_reg, DP | DP_PORT_EN);
157 intel_de_posting_read(display, intel_dp->output_reg);
158
159 intel_de_write(display, intel_dp->output_reg, DP & ~DP_PORT_EN);
160 intel_de_posting_read(display, intel_dp->output_reg);
161
162 if (!pll_enabled) {
163 vlv_force_pll_off(dev_priv, pipe);
164
165 if (release_cl_override)
166 chv_phy_powergate_ch(display, phy, ch, false);
167 }
168 }
169
vlv_find_free_pps(struct intel_display * display)170 static enum pipe vlv_find_free_pps(struct intel_display *display)
171 {
172 struct intel_encoder *encoder;
173 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
174
175 /*
176 * We don't have power sequencer currently.
177 * Pick one that's not used by other ports.
178 */
179 for_each_intel_dp(display->drm, encoder) {
180 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
181
182 if (encoder->type == INTEL_OUTPUT_EDP) {
183 drm_WARN_ON(display->drm,
184 intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&
185 intel_dp->pps.vlv_active_pipe !=
186 intel_dp->pps.vlv_pps_pipe);
187
188 if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)
189 pipes &= ~(1 << intel_dp->pps.vlv_pps_pipe);
190 } else {
191 drm_WARN_ON(display->drm,
192 intel_dp->pps.vlv_pps_pipe != INVALID_PIPE);
193
194 if (intel_dp->pps.vlv_active_pipe != INVALID_PIPE)
195 pipes &= ~(1 << intel_dp->pps.vlv_active_pipe);
196 }
197 }
198
199 if (pipes == 0)
200 return INVALID_PIPE;
201
202 return ffs(pipes) - 1;
203 }
204
205 static enum pipe
vlv_power_sequencer_pipe(struct intel_dp * intel_dp)206 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
207 {
208 struct intel_display *display = to_intel_display(intel_dp);
209 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
210 enum pipe pipe;
211
212 lockdep_assert_held(&display->pps.mutex);
213
214 /* We should never land here with regular DP ports */
215 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));
216
217 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&
218 intel_dp->pps.vlv_active_pipe != intel_dp->pps.vlv_pps_pipe);
219
220 if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)
221 return intel_dp->pps.vlv_pps_pipe;
222
223 pipe = vlv_find_free_pps(display);
224
225 /*
226 * Didn't find one. This should not happen since there
227 * are two power sequencers and up to two eDP ports.
228 */
229 if (drm_WARN_ON(display->drm, pipe == INVALID_PIPE))
230 pipe = PIPE_A;
231
232 vlv_steal_power_sequencer(display, pipe);
233 intel_dp->pps.vlv_pps_pipe = pipe;
234
235 drm_dbg_kms(display->drm,
236 "picked %s for [ENCODER:%d:%s]\n",
237 pps_name(intel_dp),
238 dig_port->base.base.base.id, dig_port->base.base.name);
239
240 /* init power sequencer on this pipe and port */
241 pps_init_delays(intel_dp);
242 pps_init_registers(intel_dp, true);
243
244 /*
245 * Even vdd force doesn't work until we've made
246 * the power sequencer lock in on the port.
247 */
248 vlv_power_sequencer_kick(intel_dp);
249
250 return intel_dp->pps.vlv_pps_pipe;
251 }
252
253 static int
bxt_power_sequencer_idx(struct intel_dp * intel_dp)254 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
255 {
256 struct intel_display *display = to_intel_display(intel_dp);
257 int pps_idx = intel_dp->pps.pps_idx;
258
259 lockdep_assert_held(&display->pps.mutex);
260
261 /* We should never land here with regular DP ports */
262 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));
263
264 if (!intel_dp->pps.bxt_pps_reset)
265 return pps_idx;
266
267 intel_dp->pps.bxt_pps_reset = false;
268
269 /*
270 * Only the HW needs to be reprogrammed, the SW state is fixed and
271 * has been setup during connector init.
272 */
273 pps_init_registers(intel_dp, false);
274
275 return pps_idx;
276 }
277
278 typedef bool (*pps_check)(struct intel_display *display, int pps_idx);
279
pps_has_pp_on(struct intel_display * display,int pps_idx)280 static bool pps_has_pp_on(struct intel_display *display, int pps_idx)
281 {
282 return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON;
283 }
284
pps_has_vdd_on(struct intel_display * display,int pps_idx)285 static bool pps_has_vdd_on(struct intel_display *display, int pps_idx)
286 {
287 return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD;
288 }
289
pps_any(struct intel_display * display,int pps_idx)290 static bool pps_any(struct intel_display *display, int pps_idx)
291 {
292 return true;
293 }
294
295 static enum pipe
vlv_initial_pps_pipe(struct intel_display * display,enum port port,pps_check check)296 vlv_initial_pps_pipe(struct intel_display *display,
297 enum port port, pps_check check)
298 {
299 enum pipe pipe;
300
301 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
302 u32 port_sel = intel_de_read(display,
303 PP_ON_DELAYS(display, pipe)) &
304 PANEL_PORT_SELECT_MASK;
305
306 if (port_sel != PANEL_PORT_SELECT_VLV(port))
307 continue;
308
309 if (!check(display, pipe))
310 continue;
311
312 return pipe;
313 }
314
315 return INVALID_PIPE;
316 }
317
318 static void
vlv_initial_power_sequencer_setup(struct intel_dp * intel_dp)319 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
320 {
321 struct intel_display *display = to_intel_display(intel_dp);
322 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
323 enum port port = dig_port->base.port;
324
325 lockdep_assert_held(&display->pps.mutex);
326
327 /* try to find a pipe with this port selected */
328 /* first pick one where the panel is on */
329 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,
330 pps_has_pp_on);
331 /* didn't find one? pick one where vdd is on */
332 if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
333 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,
334 pps_has_vdd_on);
335 /* didn't find one? pick one with just the correct port */
336 if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
337 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,
338 pps_any);
339
340 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
341 if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) {
342 drm_dbg_kms(display->drm,
343 "[ENCODER:%d:%s] no initial power sequencer\n",
344 dig_port->base.base.base.id, dig_port->base.base.name);
345 return;
346 }
347
348 drm_dbg_kms(display->drm,
349 "[ENCODER:%d:%s] initial power sequencer: %s\n",
350 dig_port->base.base.base.id, dig_port->base.base.name,
351 pps_name(intel_dp));
352 }
353
intel_num_pps(struct intel_display * display)354 static int intel_num_pps(struct intel_display *display)
355 {
356 struct drm_i915_private *i915 = to_i915(display->drm);
357
358 if (display->platform.valleyview || display->platform.cherryview)
359 return 2;
360
361 if (display->platform.geminilake || display->platform.broxton)
362 return 2;
363
364 if (INTEL_PCH_TYPE(i915) >= PCH_MTL)
365 return 2;
366
367 if (INTEL_PCH_TYPE(i915) >= PCH_DG1)
368 return 1;
369
370 if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
371 return 2;
372
373 return 1;
374 }
375
intel_pps_is_valid(struct intel_dp * intel_dp)376 static bool intel_pps_is_valid(struct intel_dp *intel_dp)
377 {
378 struct intel_display *display = to_intel_display(intel_dp);
379 struct drm_i915_private *i915 = to_i915(display->drm);
380
381 if (intel_dp->pps.pps_idx == 1 &&
382 INTEL_PCH_TYPE(i915) >= PCH_ICP &&
383 INTEL_PCH_TYPE(i915) <= PCH_ADP)
384 return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;
385
386 return true;
387 }
388
389 static int
bxt_initial_pps_idx(struct intel_display * display,pps_check check)390 bxt_initial_pps_idx(struct intel_display *display, pps_check check)
391 {
392 int pps_idx, pps_num = intel_num_pps(display);
393
394 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
395 if (check(display, pps_idx))
396 return pps_idx;
397 }
398
399 return -1;
400 }
401
402 static bool
pps_initial_setup(struct intel_dp * intel_dp)403 pps_initial_setup(struct intel_dp *intel_dp)
404 {
405 struct intel_display *display = to_intel_display(intel_dp);
406 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
407 struct intel_connector *connector = intel_dp->attached_connector;
408
409 lockdep_assert_held(&display->pps.mutex);
410
411 if (display->platform.valleyview || display->platform.cherryview) {
412 vlv_initial_power_sequencer_setup(intel_dp);
413 return true;
414 }
415
416 /* first ask the VBT */
417 if (intel_num_pps(display) > 1)
418 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;
419 else
420 intel_dp->pps.pps_idx = 0;
421
422 if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display)))
423 intel_dp->pps.pps_idx = -1;
424
425 /* VBT wasn't parsed yet? pick one where the panel is on */
426 if (intel_dp->pps.pps_idx < 0)
427 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on);
428 /* didn't find one? pick one where vdd is on */
429 if (intel_dp->pps.pps_idx < 0)
430 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on);
431 /* didn't find one? pick any */
432 if (intel_dp->pps.pps_idx < 0) {
433 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any);
434
435 drm_dbg_kms(display->drm,
436 "[ENCODER:%d:%s] no initial power sequencer, assuming %s\n",
437 encoder->base.base.id, encoder->base.name,
438 pps_name(intel_dp));
439 } else {
440 drm_dbg_kms(display->drm,
441 "[ENCODER:%d:%s] initial power sequencer: %s\n",
442 encoder->base.base.id, encoder->base.name,
443 pps_name(intel_dp));
444 }
445
446 return intel_pps_is_valid(intel_dp);
447 }
448
vlv_pps_reset_all(struct intel_display * display)449 void vlv_pps_reset_all(struct intel_display *display)
450 {
451 struct intel_encoder *encoder;
452
453 if (!HAS_DISPLAY(display))
454 return;
455
456 /*
457 * We can't grab pps_mutex here due to deadlock with power_domain
458 * mutex when power_domain functions are called while holding pps_mutex.
459 * That also means that in order to use vlv_pps_pipe the code needs to
460 * hold both a power domain reference and pps_mutex, and the power domain
461 * reference get/put must be done while _not_ holding pps_mutex.
462 * pps_{lock,unlock}() do these steps in the correct order, so one
463 * should use them always.
464 */
465
466 for_each_intel_dp(display->drm, encoder) {
467 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
468
469 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
470
471 if (encoder->type == INTEL_OUTPUT_EDP)
472 intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
473 }
474 }
475
bxt_pps_reset_all(struct intel_display * display)476 void bxt_pps_reset_all(struct intel_display *display)
477 {
478 struct intel_encoder *encoder;
479
480 if (!HAS_DISPLAY(display))
481 return;
482
483 /* See vlv_pps_reset_all() for why we can't grab pps_mutex here. */
484
485 for_each_intel_dp(display->drm, encoder) {
486 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
487
488 if (encoder->type == INTEL_OUTPUT_EDP)
489 intel_dp->pps.bxt_pps_reset = true;
490 }
491 }
492
493 struct pps_registers {
494 i915_reg_t pp_ctrl;
495 i915_reg_t pp_stat;
496 i915_reg_t pp_on;
497 i915_reg_t pp_off;
498 i915_reg_t pp_div;
499 };
500
intel_pps_get_registers(struct intel_dp * intel_dp,struct pps_registers * regs)501 static void intel_pps_get_registers(struct intel_dp *intel_dp,
502 struct pps_registers *regs)
503 {
504 struct intel_display *display = to_intel_display(intel_dp);
505 struct drm_i915_private *dev_priv = to_i915(display->drm);
506 int pps_idx;
507
508 memset(regs, 0, sizeof(*regs));
509
510 if (display->platform.valleyview || display->platform.cherryview)
511 pps_idx = vlv_power_sequencer_pipe(intel_dp);
512 else if (display->platform.geminilake || display->platform.broxton)
513 pps_idx = bxt_power_sequencer_idx(intel_dp);
514 else
515 pps_idx = intel_dp->pps.pps_idx;
516
517 regs->pp_ctrl = PP_CONTROL(display, pps_idx);
518 regs->pp_stat = PP_STATUS(display, pps_idx);
519 regs->pp_on = PP_ON_DELAYS(display, pps_idx);
520 regs->pp_off = PP_OFF_DELAYS(display, pps_idx);
521
522 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
523 if (display->platform.geminilake || display->platform.broxton ||
524 INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
525 regs->pp_div = INVALID_MMIO_REG;
526 else
527 regs->pp_div = PP_DIVISOR(display, pps_idx);
528 }
529
530 static i915_reg_t
_pp_ctrl_reg(struct intel_dp * intel_dp)531 _pp_ctrl_reg(struct intel_dp *intel_dp)
532 {
533 struct pps_registers regs;
534
535 intel_pps_get_registers(intel_dp, ®s);
536
537 return regs.pp_ctrl;
538 }
539
540 static i915_reg_t
_pp_stat_reg(struct intel_dp * intel_dp)541 _pp_stat_reg(struct intel_dp *intel_dp)
542 {
543 struct pps_registers regs;
544
545 intel_pps_get_registers(intel_dp, ®s);
546
547 return regs.pp_stat;
548 }
549
edp_have_panel_power(struct intel_dp * intel_dp)550 static bool edp_have_panel_power(struct intel_dp *intel_dp)
551 {
552 struct intel_display *display = to_intel_display(intel_dp);
553
554 lockdep_assert_held(&display->pps.mutex);
555
556 if ((display->platform.valleyview || display->platform.cherryview) &&
557 intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
558 return false;
559
560 return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
561 }
562
edp_have_panel_vdd(struct intel_dp * intel_dp)563 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
564 {
565 struct intel_display *display = to_intel_display(intel_dp);
566
567 lockdep_assert_held(&display->pps.mutex);
568
569 if ((display->platform.valleyview || display->platform.cherryview) &&
570 intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
571 return false;
572
573 return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
574 }
575
intel_pps_check_power_unlocked(struct intel_dp * intel_dp)576 void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
577 {
578 struct intel_display *display = to_intel_display(intel_dp);
579 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
580
581 if (!intel_dp_is_edp(intel_dp))
582 return;
583
584 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
585 drm_WARN(display->drm, 1,
586 "[ENCODER:%d:%s] %s powered off while attempting AUX CH communication.\n",
587 dig_port->base.base.base.id, dig_port->base.base.name,
588 pps_name(intel_dp));
589 drm_dbg_kms(display->drm,
590 "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
591 dig_port->base.base.base.id, dig_port->base.base.name,
592 pps_name(intel_dp),
593 intel_de_read(display, _pp_stat_reg(intel_dp)),
594 intel_de_read(display, _pp_ctrl_reg(intel_dp)));
595 }
596 }
597
598 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
599 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
600
601 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
602 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
603
604 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
605 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
606
607 static void intel_pps_verify_state(struct intel_dp *intel_dp);
608
wait_panel_status(struct intel_dp * intel_dp,u32 mask,u32 value)609 static void wait_panel_status(struct intel_dp *intel_dp,
610 u32 mask, u32 value)
611 {
612 struct intel_display *display = to_intel_display(intel_dp);
613 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
614 i915_reg_t pp_stat_reg, pp_ctrl_reg;
615
616 lockdep_assert_held(&display->pps.mutex);
617
618 intel_pps_verify_state(intel_dp);
619
620 pp_stat_reg = _pp_stat_reg(intel_dp);
621 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
622
623 drm_dbg_kms(display->drm,
624 "[ENCODER:%d:%s] %s mask: 0x%08x value: 0x%08x PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
625 dig_port->base.base.base.id, dig_port->base.base.name,
626 pps_name(intel_dp),
627 mask, value,
628 intel_de_read(display, pp_stat_reg),
629 intel_de_read(display, pp_ctrl_reg));
630
631 if (intel_de_wait(display, pp_stat_reg, mask, value, 5000))
632 drm_err(display->drm,
633 "[ENCODER:%d:%s] %s panel status timeout: PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
634 dig_port->base.base.base.id, dig_port->base.base.name,
635 pps_name(intel_dp),
636 intel_de_read(display, pp_stat_reg),
637 intel_de_read(display, pp_ctrl_reg));
638
639 drm_dbg_kms(display->drm, "Wait complete\n");
640 }
641
wait_panel_on(struct intel_dp * intel_dp)642 static void wait_panel_on(struct intel_dp *intel_dp)
643 {
644 struct intel_display *display = to_intel_display(intel_dp);
645 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
646
647 drm_dbg_kms(display->drm,
648 "[ENCODER:%d:%s] %s wait for panel power on\n",
649 dig_port->base.base.base.id, dig_port->base.base.name,
650 pps_name(intel_dp));
651 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
652 }
653
wait_panel_off(struct intel_dp * intel_dp)654 static void wait_panel_off(struct intel_dp *intel_dp)
655 {
656 struct intel_display *display = to_intel_display(intel_dp);
657 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
658
659 drm_dbg_kms(display->drm,
660 "[ENCODER:%d:%s] %s wait for panel power off time\n",
661 dig_port->base.base.base.id, dig_port->base.base.name,
662 pps_name(intel_dp));
663 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
664 }
665
wait_panel_power_cycle(struct intel_dp * intel_dp)666 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
667 {
668 struct intel_display *display = to_intel_display(intel_dp);
669 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
670 ktime_t panel_power_on_time;
671 s64 panel_power_off_duration, remaining;
672
673 /* take the difference of current time and panel power off time
674 * and then make panel wait for power_cycle if needed. */
675 panel_power_on_time = ktime_get_boottime();
676 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);
677
678 remaining = max(0, intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);
679
680 drm_dbg_kms(display->drm,
681 "[ENCODER:%d:%s] %s wait for panel power cycle (%lld ms remaining)\n",
682 dig_port->base.base.base.id, dig_port->base.base.name,
683 pps_name(intel_dp), remaining);
684
685 /* When we disable the VDD override bit last we have to do the manual
686 * wait. */
687 if (remaining)
688 wait_remaining_ms_from_jiffies(jiffies, remaining);
689
690 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
691 }
692
intel_pps_wait_power_cycle(struct intel_dp * intel_dp)693 void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
694 {
695 intel_wakeref_t wakeref;
696
697 if (!intel_dp_is_edp(intel_dp))
698 return;
699
700 with_intel_pps_lock(intel_dp, wakeref)
701 wait_panel_power_cycle(intel_dp);
702 }
703
wait_backlight_on(struct intel_dp * intel_dp)704 static void wait_backlight_on(struct intel_dp *intel_dp)
705 {
706 wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,
707 intel_dp->pps.backlight_on_delay);
708 }
709
edp_wait_backlight_off(struct intel_dp * intel_dp)710 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
711 {
712 wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,
713 intel_dp->pps.backlight_off_delay);
714 }
715
716 /* Read the current pp_control value, unlocking the register if it
717 * is locked
718 */
719
ilk_get_pp_control(struct intel_dp * intel_dp)720 static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
721 {
722 struct intel_display *display = to_intel_display(intel_dp);
723 u32 control;
724
725 lockdep_assert_held(&display->pps.mutex);
726
727 control = intel_de_read(display, _pp_ctrl_reg(intel_dp));
728 if (drm_WARN_ON(display->drm, !HAS_DDI(display) &&
729 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
730 control &= ~PANEL_UNLOCK_MASK;
731 control |= PANEL_UNLOCK_REGS;
732 }
733 return control;
734 }
735
736 /*
737 * Must be paired with intel_pps_vdd_off_unlocked().
738 * Must hold pps_mutex around the whole on/off sequence.
739 * Can be nested with intel_pps_vdd_{on,off}() calls.
740 */
intel_pps_vdd_on_unlocked(struct intel_dp * intel_dp)741 bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
742 {
743 struct intel_display *display = to_intel_display(intel_dp);
744 struct drm_i915_private *dev_priv = to_i915(display->drm);
745 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
746 u32 pp;
747 i915_reg_t pp_stat_reg, pp_ctrl_reg;
748 bool need_to_disable = !intel_dp->pps.want_panel_vdd;
749
750 lockdep_assert_held(&display->pps.mutex);
751
752 if (!intel_dp_is_edp(intel_dp))
753 return false;
754
755 cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
756 intel_dp->pps.want_panel_vdd = true;
757
758 if (edp_have_panel_vdd(intel_dp))
759 return need_to_disable;
760
761 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
762 intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
763 intel_aux_power_domain(dig_port));
764
765 pp_stat_reg = _pp_stat_reg(intel_dp);
766 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
767
768 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD on\n",
769 dig_port->base.base.base.id, dig_port->base.base.name,
770 pps_name(intel_dp));
771
772 if (!edp_have_panel_power(intel_dp))
773 wait_panel_power_cycle(intel_dp);
774
775 pp = ilk_get_pp_control(intel_dp);
776 pp |= EDP_FORCE_VDD;
777
778 intel_de_write(display, pp_ctrl_reg, pp);
779 intel_de_posting_read(display, pp_ctrl_reg);
780 drm_dbg_kms(display->drm,
781 "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
782 dig_port->base.base.base.id, dig_port->base.base.name,
783 pps_name(intel_dp),
784 intel_de_read(display, pp_stat_reg),
785 intel_de_read(display, pp_ctrl_reg));
786 /*
787 * If the panel wasn't on, delay before accessing aux channel
788 */
789 if (!edp_have_panel_power(intel_dp)) {
790 drm_dbg_kms(display->drm,
791 "[ENCODER:%d:%s] %s panel power wasn't enabled\n",
792 dig_port->base.base.base.id, dig_port->base.base.name,
793 pps_name(intel_dp));
794 msleep(intel_dp->pps.panel_power_up_delay);
795 }
796
797 return need_to_disable;
798 }
799
800 /*
801 * Must be paired with intel_pps_vdd_off() or - to disable
802 * both VDD and panel power - intel_pps_off().
803 * Nested calls to these functions are not allowed since
804 * we drop the lock. Caller must use some higher level
805 * locking to prevent nested calls from other threads.
806 */
intel_pps_vdd_on(struct intel_dp * intel_dp)807 void intel_pps_vdd_on(struct intel_dp *intel_dp)
808 {
809 struct intel_display *display = to_intel_display(intel_dp);
810 intel_wakeref_t wakeref;
811 bool vdd;
812
813 if (!intel_dp_is_edp(intel_dp))
814 return;
815
816 vdd = false;
817 with_intel_pps_lock(intel_dp, wakeref)
818 vdd = intel_pps_vdd_on_unlocked(intel_dp);
819 INTEL_DISPLAY_STATE_WARN(display, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n",
820 dp_to_dig_port(intel_dp)->base.base.base.id,
821 dp_to_dig_port(intel_dp)->base.base.name,
822 pps_name(intel_dp));
823 }
824
intel_pps_vdd_off_sync_unlocked(struct intel_dp * intel_dp)825 static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
826 {
827 struct intel_display *display = to_intel_display(intel_dp);
828 struct drm_i915_private *dev_priv = to_i915(display->drm);
829 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
830 u32 pp;
831 i915_reg_t pp_stat_reg, pp_ctrl_reg;
832
833 lockdep_assert_held(&display->pps.mutex);
834
835 drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd);
836
837 if (!edp_have_panel_vdd(intel_dp))
838 return;
839
840 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD off\n",
841 dig_port->base.base.base.id, dig_port->base.base.name,
842 pps_name(intel_dp));
843
844 pp = ilk_get_pp_control(intel_dp);
845 pp &= ~EDP_FORCE_VDD;
846
847 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
848 pp_stat_reg = _pp_stat_reg(intel_dp);
849
850 intel_de_write(display, pp_ctrl_reg, pp);
851 intel_de_posting_read(display, pp_ctrl_reg);
852
853 /* Make sure sequencer is idle before allowing subsequent activity */
854 drm_dbg_kms(display->drm,
855 "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
856 dig_port->base.base.base.id, dig_port->base.base.name,
857 pps_name(intel_dp),
858 intel_de_read(display, pp_stat_reg),
859 intel_de_read(display, pp_ctrl_reg));
860
861 if ((pp & PANEL_POWER_ON) == 0) {
862 intel_dp->pps.panel_power_off_time = ktime_get_boottime();
863 intel_dp_invalidate_source_oui(intel_dp);
864 }
865
866 intel_display_power_put(dev_priv,
867 intel_aux_power_domain(dig_port),
868 fetch_and_zero(&intel_dp->pps.vdd_wakeref));
869 }
870
intel_pps_vdd_off_sync(struct intel_dp * intel_dp)871 void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
872 {
873 intel_wakeref_t wakeref;
874
875 if (!intel_dp_is_edp(intel_dp))
876 return;
877
878 cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);
879 /*
880 * vdd might still be enabled due to the delayed vdd off.
881 * Make sure vdd is actually turned off here.
882 */
883 with_intel_pps_lock(intel_dp, wakeref)
884 intel_pps_vdd_off_sync_unlocked(intel_dp);
885 }
886
edp_panel_vdd_work(struct work_struct * __work)887 static void edp_panel_vdd_work(struct work_struct *__work)
888 {
889 struct intel_pps *pps = container_of(to_delayed_work(__work),
890 struct intel_pps, panel_vdd_work);
891 struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);
892 intel_wakeref_t wakeref;
893
894 with_intel_pps_lock(intel_dp, wakeref) {
895 if (!intel_dp->pps.want_panel_vdd)
896 intel_pps_vdd_off_sync_unlocked(intel_dp);
897 }
898 }
899
edp_panel_vdd_schedule_off(struct intel_dp * intel_dp)900 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
901 {
902 struct intel_display *display = to_intel_display(intel_dp);
903 struct drm_i915_private *i915 = to_i915(display->drm);
904 unsigned long delay;
905
906 /*
907 * We may not yet know the real power sequencing delays,
908 * so keep VDD enabled until we're done with init.
909 */
910 if (intel_dp->pps.initializing)
911 return;
912
913 /*
914 * Queue the timer to fire a long time from now (relative to the power
915 * down delay) to keep the panel power up across a sequence of
916 * operations.
917 */
918 delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);
919 queue_delayed_work(i915->unordered_wq,
920 &intel_dp->pps.panel_vdd_work, delay);
921 }
922
923 /*
924 * Must be paired with edp_panel_vdd_on().
925 * Must hold pps_mutex around the whole on/off sequence.
926 * Can be nested with intel_pps_vdd_{on,off}() calls.
927 */
intel_pps_vdd_off_unlocked(struct intel_dp * intel_dp,bool sync)928 void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
929 {
930 struct intel_display *display = to_intel_display(intel_dp);
931
932 lockdep_assert_held(&display->pps.mutex);
933
934 if (!intel_dp_is_edp(intel_dp))
935 return;
936
937 INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,
938 "[ENCODER:%d:%s] %s VDD not forced on",
939 dp_to_dig_port(intel_dp)->base.base.base.id,
940 dp_to_dig_port(intel_dp)->base.base.name,
941 pps_name(intel_dp));
942
943 intel_dp->pps.want_panel_vdd = false;
944
945 if (sync)
946 intel_pps_vdd_off_sync_unlocked(intel_dp);
947 else
948 edp_panel_vdd_schedule_off(intel_dp);
949 }
950
intel_pps_vdd_off(struct intel_dp * intel_dp)951 void intel_pps_vdd_off(struct intel_dp *intel_dp)
952 {
953 intel_wakeref_t wakeref;
954
955 if (!intel_dp_is_edp(intel_dp))
956 return;
957
958 with_intel_pps_lock(intel_dp, wakeref)
959 intel_pps_vdd_off_unlocked(intel_dp, false);
960 }
961
intel_pps_on_unlocked(struct intel_dp * intel_dp)962 void intel_pps_on_unlocked(struct intel_dp *intel_dp)
963 {
964 struct intel_display *display = to_intel_display(intel_dp);
965 u32 pp;
966 i915_reg_t pp_ctrl_reg;
967
968 lockdep_assert_held(&display->pps.mutex);
969
970 if (!intel_dp_is_edp(intel_dp))
971 return;
972
973 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power on\n",
974 dp_to_dig_port(intel_dp)->base.base.base.id,
975 dp_to_dig_port(intel_dp)->base.base.name,
976 pps_name(intel_dp));
977
978 if (drm_WARN(display->drm, edp_have_panel_power(intel_dp),
979 "[ENCODER:%d:%s] %s panel power already on\n",
980 dp_to_dig_port(intel_dp)->base.base.base.id,
981 dp_to_dig_port(intel_dp)->base.base.name,
982 pps_name(intel_dp)))
983 return;
984
985 wait_panel_power_cycle(intel_dp);
986
987 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
988 pp = ilk_get_pp_control(intel_dp);
989 if (display->platform.ironlake) {
990 /* ILK workaround: disable reset around power sequence */
991 pp &= ~PANEL_POWER_RESET;
992 intel_de_write(display, pp_ctrl_reg, pp);
993 intel_de_posting_read(display, pp_ctrl_reg);
994 }
995
996 /*
997 * WA: 22019252566
998 * Disable DPLS gating around power sequence.
999 */
1000 if (IS_DISPLAY_VER(display, 13, 14))
1001 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
1002 0, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
1003
1004 pp |= PANEL_POWER_ON;
1005 if (!display->platform.ironlake)
1006 pp |= PANEL_POWER_RESET;
1007
1008 intel_de_write(display, pp_ctrl_reg, pp);
1009 intel_de_posting_read(display, pp_ctrl_reg);
1010
1011 wait_panel_on(intel_dp);
1012 intel_dp->pps.last_power_on = jiffies;
1013
1014 if (IS_DISPLAY_VER(display, 13, 14))
1015 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
1016 PCH_DPLSUNIT_CLOCK_GATE_DISABLE, 0);
1017
1018 if (display->platform.ironlake) {
1019 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1020 intel_de_write(display, pp_ctrl_reg, pp);
1021 intel_de_posting_read(display, pp_ctrl_reg);
1022 }
1023 }
1024
intel_pps_on(struct intel_dp * intel_dp)1025 void intel_pps_on(struct intel_dp *intel_dp)
1026 {
1027 intel_wakeref_t wakeref;
1028
1029 if (!intel_dp_is_edp(intel_dp))
1030 return;
1031
1032 with_intel_pps_lock(intel_dp, wakeref)
1033 intel_pps_on_unlocked(intel_dp);
1034 }
1035
intel_pps_off_unlocked(struct intel_dp * intel_dp)1036 void intel_pps_off_unlocked(struct intel_dp *intel_dp)
1037 {
1038 struct intel_display *display = to_intel_display(intel_dp);
1039 struct drm_i915_private *dev_priv = to_i915(display->drm);
1040 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1041 u32 pp;
1042 i915_reg_t pp_ctrl_reg;
1043
1044 lockdep_assert_held(&display->pps.mutex);
1045
1046 if (!intel_dp_is_edp(intel_dp))
1047 return;
1048
1049 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power off\n",
1050 dig_port->base.base.base.id, dig_port->base.base.name,
1051 pps_name(intel_dp));
1052
1053 drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd,
1054 "[ENCODER:%d:%s] %s need VDD to turn off panel\n",
1055 dig_port->base.base.base.id, dig_port->base.base.name,
1056 pps_name(intel_dp));
1057
1058 pp = ilk_get_pp_control(intel_dp);
1059 /* We need to switch off panel power _and_ force vdd, for otherwise some
1060 * panels get very unhappy and cease to work. */
1061 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1062 EDP_BLC_ENABLE);
1063
1064 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1065
1066 intel_dp->pps.want_panel_vdd = false;
1067
1068 intel_de_write(display, pp_ctrl_reg, pp);
1069 intel_de_posting_read(display, pp_ctrl_reg);
1070
1071 wait_panel_off(intel_dp);
1072 intel_dp->pps.panel_power_off_time = ktime_get_boottime();
1073
1074 intel_dp_invalidate_source_oui(intel_dp);
1075
1076 /* We got a reference when we enabled the VDD. */
1077 intel_display_power_put(dev_priv,
1078 intel_aux_power_domain(dig_port),
1079 fetch_and_zero(&intel_dp->pps.vdd_wakeref));
1080 }
1081
intel_pps_off(struct intel_dp * intel_dp)1082 void intel_pps_off(struct intel_dp *intel_dp)
1083 {
1084 intel_wakeref_t wakeref;
1085
1086 if (!intel_dp_is_edp(intel_dp))
1087 return;
1088
1089 with_intel_pps_lock(intel_dp, wakeref)
1090 intel_pps_off_unlocked(intel_dp);
1091 }
1092
1093 /* Enable backlight in the panel power control. */
intel_pps_backlight_on(struct intel_dp * intel_dp)1094 void intel_pps_backlight_on(struct intel_dp *intel_dp)
1095 {
1096 struct intel_display *display = to_intel_display(intel_dp);
1097 intel_wakeref_t wakeref;
1098
1099 /*
1100 * If we enable the backlight right away following a panel power
1101 * on, we may see slight flicker as the panel syncs with the eDP
1102 * link. So delay a bit to make sure the image is solid before
1103 * allowing it to appear.
1104 */
1105 wait_backlight_on(intel_dp);
1106
1107 with_intel_pps_lock(intel_dp, wakeref) {
1108 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1109 u32 pp;
1110
1111 pp = ilk_get_pp_control(intel_dp);
1112 pp |= EDP_BLC_ENABLE;
1113
1114 intel_de_write(display, pp_ctrl_reg, pp);
1115 intel_de_posting_read(display, pp_ctrl_reg);
1116 }
1117 }
1118
1119 /* Disable backlight in the panel power control. */
intel_pps_backlight_off(struct intel_dp * intel_dp)1120 void intel_pps_backlight_off(struct intel_dp *intel_dp)
1121 {
1122 struct intel_display *display = to_intel_display(intel_dp);
1123 intel_wakeref_t wakeref;
1124
1125 if (!intel_dp_is_edp(intel_dp))
1126 return;
1127
1128 with_intel_pps_lock(intel_dp, wakeref) {
1129 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1130 u32 pp;
1131
1132 pp = ilk_get_pp_control(intel_dp);
1133 pp &= ~EDP_BLC_ENABLE;
1134
1135 intel_de_write(display, pp_ctrl_reg, pp);
1136 intel_de_posting_read(display, pp_ctrl_reg);
1137 }
1138
1139 intel_dp->pps.last_backlight_off = jiffies;
1140 edp_wait_backlight_off(intel_dp);
1141 }
1142
1143 /*
1144 * Hook for controlling the panel power control backlight through the bl_power
1145 * sysfs attribute. Take care to handle multiple calls.
1146 */
intel_pps_backlight_power(struct intel_connector * connector,bool enable)1147 void intel_pps_backlight_power(struct intel_connector *connector, bool enable)
1148 {
1149 struct intel_display *display = to_intel_display(connector);
1150 struct intel_dp *intel_dp = intel_attached_dp(connector);
1151 intel_wakeref_t wakeref;
1152 bool is_enabled;
1153
1154 is_enabled = false;
1155 with_intel_pps_lock(intel_dp, wakeref)
1156 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1157 if (is_enabled == enable)
1158 return;
1159
1160 drm_dbg_kms(display->drm, "panel power control backlight %s\n",
1161 str_enable_disable(enable));
1162
1163 if (enable)
1164 intel_pps_backlight_on(intel_dp);
1165 else
1166 intel_pps_backlight_off(intel_dp);
1167 }
1168
vlv_detach_power_sequencer(struct intel_dp * intel_dp)1169 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
1170 {
1171 struct intel_display *display = to_intel_display(intel_dp);
1172 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1173 enum pipe pipe = intel_dp->pps.vlv_pps_pipe;
1174 i915_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe);
1175
1176 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
1177
1178 if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))
1179 return;
1180
1181 intel_pps_vdd_off_sync_unlocked(intel_dp);
1182
1183 /*
1184 * VLV seems to get confused when multiple power sequencers
1185 * have the same port selected (even if only one has power/vdd
1186 * enabled). The failure manifests as vlv_wait_port_ready() failing
1187 * CHV on the other hand doesn't seem to mind having the same port
1188 * selected in multiple power sequencers, but let's clear the
1189 * port select always when logically disconnecting a power sequencer
1190 * from a port.
1191 */
1192 drm_dbg_kms(display->drm,
1193 "detaching %s from [ENCODER:%d:%s]\n",
1194 pps_name(intel_dp),
1195 dig_port->base.base.base.id, dig_port->base.base.name);
1196 intel_de_write(display, pp_on_reg, 0);
1197 intel_de_posting_read(display, pp_on_reg);
1198
1199 intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
1200 }
1201
vlv_steal_power_sequencer(struct intel_display * display,enum pipe pipe)1202 static void vlv_steal_power_sequencer(struct intel_display *display,
1203 enum pipe pipe)
1204 {
1205 struct intel_encoder *encoder;
1206
1207 lockdep_assert_held(&display->pps.mutex);
1208
1209 for_each_intel_dp(display->drm, encoder) {
1210 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1211
1212 drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe,
1213 "stealing PPS %c from active [ENCODER:%d:%s]\n",
1214 pipe_name(pipe), encoder->base.base.id,
1215 encoder->base.name);
1216
1217 if (intel_dp->pps.vlv_pps_pipe != pipe)
1218 continue;
1219
1220 drm_dbg_kms(display->drm,
1221 "stealing PPS %c from [ENCODER:%d:%s]\n",
1222 pipe_name(pipe), encoder->base.base.id,
1223 encoder->base.name);
1224
1225 /* make sure vdd is off before we steal it */
1226 vlv_detach_power_sequencer(intel_dp);
1227 }
1228 }
1229
vlv_active_pipe(struct intel_dp * intel_dp)1230 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
1231 {
1232 struct intel_display *display = to_intel_display(intel_dp);
1233 struct drm_i915_private *dev_priv = to_i915(display->drm);
1234 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1235 enum pipe pipe;
1236
1237 if (g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
1238 encoder->port, &pipe))
1239 return pipe;
1240
1241 return INVALID_PIPE;
1242 }
1243
1244 /* Call on all DP, not just eDP */
vlv_pps_pipe_init(struct intel_dp * intel_dp)1245 void vlv_pps_pipe_init(struct intel_dp *intel_dp)
1246 {
1247 intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
1248 intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);
1249 }
1250
1251 /* Call on all DP, not just eDP */
vlv_pps_pipe_reset(struct intel_dp * intel_dp)1252 void vlv_pps_pipe_reset(struct intel_dp *intel_dp)
1253 {
1254 intel_wakeref_t wakeref;
1255
1256 with_intel_pps_lock(intel_dp, wakeref)
1257 intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);
1258 }
1259
vlv_pps_backlight_initial_pipe(struct intel_dp * intel_dp)1260 enum pipe vlv_pps_backlight_initial_pipe(struct intel_dp *intel_dp)
1261 {
1262 enum pipe pipe;
1263
1264 /*
1265 * Figure out the current pipe for the initial backlight setup. If the
1266 * current pipe isn't valid, try the PPS pipe, and if that fails just
1267 * assume pipe A.
1268 */
1269 pipe = vlv_active_pipe(intel_dp);
1270
1271 if (pipe != PIPE_A && pipe != PIPE_B)
1272 pipe = intel_dp->pps.vlv_pps_pipe;
1273
1274 if (pipe != PIPE_A && pipe != PIPE_B)
1275 pipe = PIPE_A;
1276
1277 return pipe;
1278 }
1279
1280 /* Call on all DP, not just eDP */
vlv_pps_port_enable_unlocked(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1281 void vlv_pps_port_enable_unlocked(struct intel_encoder *encoder,
1282 const struct intel_crtc_state *crtc_state)
1283 {
1284 struct intel_display *display = to_intel_display(encoder);
1285 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1286 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1287
1288 lockdep_assert_held(&display->pps.mutex);
1289
1290 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
1291
1292 if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE &&
1293 intel_dp->pps.vlv_pps_pipe != crtc->pipe) {
1294 /*
1295 * If another power sequencer was being used on this
1296 * port previously make sure to turn off vdd there while
1297 * we still have control of it.
1298 */
1299 vlv_detach_power_sequencer(intel_dp);
1300 }
1301
1302 /*
1303 * We may be stealing the power
1304 * sequencer from another port.
1305 */
1306 vlv_steal_power_sequencer(display, crtc->pipe);
1307
1308 intel_dp->pps.vlv_active_pipe = crtc->pipe;
1309
1310 if (!intel_dp_is_edp(intel_dp))
1311 return;
1312
1313 /* now it's all ours */
1314 intel_dp->pps.vlv_pps_pipe = crtc->pipe;
1315
1316 drm_dbg_kms(display->drm,
1317 "initializing %s for [ENCODER:%d:%s]\n",
1318 pps_name(intel_dp),
1319 encoder->base.base.id, encoder->base.name);
1320
1321 /* init power sequencer on this pipe and port */
1322 pps_init_delays(intel_dp);
1323 pps_init_registers(intel_dp, true);
1324 }
1325
1326 /* Call on all DP, not just eDP */
vlv_pps_port_disable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1327 void vlv_pps_port_disable(struct intel_encoder *encoder,
1328 const struct intel_crtc_state *crtc_state)
1329 {
1330 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1331
1332 intel_wakeref_t wakeref;
1333
1334 with_intel_pps_lock(intel_dp, wakeref)
1335 intel_dp->pps.vlv_active_pipe = INVALID_PIPE;
1336 }
1337
pps_vdd_init(struct intel_dp * intel_dp)1338 static void pps_vdd_init(struct intel_dp *intel_dp)
1339 {
1340 struct intel_display *display = to_intel_display(intel_dp);
1341 struct drm_i915_private *dev_priv = to_i915(display->drm);
1342 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1343
1344 lockdep_assert_held(&display->pps.mutex);
1345
1346 if (!edp_have_panel_vdd(intel_dp))
1347 return;
1348
1349 /*
1350 * The VDD bit needs a power domain reference, so if the bit is
1351 * already enabled when we boot or resume, grab this reference and
1352 * schedule a vdd off, so we don't hold on to the reference
1353 * indefinitely.
1354 */
1355 drm_dbg_kms(display->drm,
1356 "[ENCODER:%d:%s] %s VDD left on by BIOS, adjusting state tracking\n",
1357 dig_port->base.base.base.id, dig_port->base.base.name,
1358 pps_name(intel_dp));
1359 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
1360 intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
1361 intel_aux_power_domain(dig_port));
1362 }
1363
intel_pps_have_panel_power_or_vdd(struct intel_dp * intel_dp)1364 bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp)
1365 {
1366 intel_wakeref_t wakeref;
1367 bool have_power = false;
1368
1369 with_intel_pps_lock(intel_dp, wakeref) {
1370 have_power = edp_have_panel_power(intel_dp) ||
1371 edp_have_panel_vdd(intel_dp);
1372 }
1373
1374 return have_power;
1375 }
1376
pps_init_timestamps(struct intel_dp * intel_dp)1377 static void pps_init_timestamps(struct intel_dp *intel_dp)
1378 {
1379 /*
1380 * Initialize panel power off time to 0, assuming panel power could have
1381 * been toggled between kernel boot and now only by a previously loaded
1382 * and removed i915, which has already ensured sufficient power off
1383 * delay at module remove.
1384 */
1385 intel_dp->pps.panel_power_off_time = 0;
1386 intel_dp->pps.last_power_on = jiffies;
1387 intel_dp->pps.last_backlight_off = jiffies;
1388 }
1389
1390 static void
intel_pps_readout_hw_state(struct intel_dp * intel_dp,struct intel_pps_delays * seq)1391 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct intel_pps_delays *seq)
1392 {
1393 struct intel_display *display = to_intel_display(intel_dp);
1394 u32 pp_on, pp_off, pp_ctl, power_cycle_delay;
1395 struct pps_registers regs;
1396
1397 intel_pps_get_registers(intel_dp, ®s);
1398
1399 pp_ctl = ilk_get_pp_control(intel_dp);
1400
1401 /* Ensure PPS is unlocked */
1402 if (!HAS_DDI(display))
1403 intel_de_write(display, regs.pp_ctrl, pp_ctl);
1404
1405 pp_on = intel_de_read(display, regs.pp_on);
1406 pp_off = intel_de_read(display, regs.pp_off);
1407
1408 /* Pull timing values out of registers */
1409 seq->power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
1410 seq->backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
1411 seq->backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
1412 seq->power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
1413
1414 if (i915_mmio_reg_valid(regs.pp_div)) {
1415 u32 pp_div;
1416
1417 pp_div = intel_de_read(display, regs.pp_div);
1418
1419 power_cycle_delay = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div);
1420 } else {
1421 power_cycle_delay = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl);
1422 }
1423
1424 /* hardware wants <delay>+1 in 100ms units */
1425 seq->power_cycle = power_cycle_delay ? (power_cycle_delay - 1) * 1000 : 0;
1426 }
1427
1428 static void
intel_pps_dump_state(struct intel_dp * intel_dp,const char * state_name,const struct intel_pps_delays * seq)1429 intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name,
1430 const struct intel_pps_delays *seq)
1431 {
1432 struct intel_display *display = to_intel_display(intel_dp);
1433
1434 drm_dbg_kms(display->drm,
1435 "%s power_up %d backlight_on %d backlight_off %d power_down %d power_cycle %d\n",
1436 state_name, seq->power_up, seq->backlight_on,
1437 seq->backlight_off, seq->power_down, seq->power_cycle);
1438 }
1439
1440 static void
intel_pps_verify_state(struct intel_dp * intel_dp)1441 intel_pps_verify_state(struct intel_dp *intel_dp)
1442 {
1443 struct intel_display *display = to_intel_display(intel_dp);
1444 struct intel_pps_delays hw;
1445 struct intel_pps_delays *sw = &intel_dp->pps.pps_delays;
1446
1447 intel_pps_readout_hw_state(intel_dp, &hw);
1448
1449 if (hw.power_up != sw->power_up ||
1450 hw.backlight_on != sw->backlight_on ||
1451 hw.backlight_off != sw->backlight_off ||
1452 hw.power_down != sw->power_down ||
1453 hw.power_cycle != sw->power_cycle) {
1454 drm_err(display->drm, "PPS state mismatch\n");
1455 intel_pps_dump_state(intel_dp, "sw", sw);
1456 intel_pps_dump_state(intel_dp, "hw", &hw);
1457 }
1458 }
1459
pps_delays_valid(struct intel_pps_delays * delays)1460 static bool pps_delays_valid(struct intel_pps_delays *delays)
1461 {
1462 return delays->power_up || delays->backlight_on || delays->backlight_off ||
1463 delays->power_down || delays->power_cycle;
1464 }
1465
msecs_to_pps_units(int msecs)1466 static int msecs_to_pps_units(int msecs)
1467 {
1468 /* PPS uses 100us units */
1469 return msecs * 10;
1470 }
1471
pps_units_to_msecs(int val)1472 static int pps_units_to_msecs(int val)
1473 {
1474 /* PPS uses 100us units */
1475 return DIV_ROUND_UP(val, 10);
1476 }
1477
pps_init_delays_bios(struct intel_dp * intel_dp,struct intel_pps_delays * bios)1478 static void pps_init_delays_bios(struct intel_dp *intel_dp,
1479 struct intel_pps_delays *bios)
1480 {
1481 struct intel_display *display = to_intel_display(intel_dp);
1482
1483 lockdep_assert_held(&display->pps.mutex);
1484
1485 if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))
1486 intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);
1487
1488 *bios = intel_dp->pps.bios_pps_delays;
1489
1490 intel_pps_dump_state(intel_dp, "bios", bios);
1491 }
1492
pps_init_delays_vbt(struct intel_dp * intel_dp,struct intel_pps_delays * vbt)1493 static void pps_init_delays_vbt(struct intel_dp *intel_dp,
1494 struct intel_pps_delays *vbt)
1495 {
1496 struct intel_display *display = to_intel_display(intel_dp);
1497 struct intel_connector *connector = intel_dp->attached_connector;
1498
1499 *vbt = connector->panel.vbt.edp.pps;
1500
1501 if (!pps_delays_valid(vbt))
1502 return;
1503
1504 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
1505 * of 500ms appears to be too short. Ocassionally the panel
1506 * just fails to power back on. Increasing the delay to 800ms
1507 * seems sufficient to avoid this problem.
1508 */
1509 if (intel_has_quirk(display, QUIRK_INCREASE_T12_DELAY)) {
1510 vbt->power_cycle = max_t(u16, vbt->power_cycle, msecs_to_pps_units(1300));
1511 drm_dbg_kms(display->drm,
1512 "Increasing T12 panel delay as per the quirk to %d\n",
1513 vbt->power_cycle);
1514 }
1515
1516 intel_pps_dump_state(intel_dp, "vbt", vbt);
1517 }
1518
pps_init_delays_spec(struct intel_dp * intel_dp,struct intel_pps_delays * spec)1519 static void pps_init_delays_spec(struct intel_dp *intel_dp,
1520 struct intel_pps_delays *spec)
1521 {
1522 struct intel_display *display = to_intel_display(intel_dp);
1523
1524 lockdep_assert_held(&display->pps.mutex);
1525
1526 /* Upper limits from eDP 1.3 spec */
1527 spec->power_up = msecs_to_pps_units(10 + 200); /* T1+T3 */
1528 spec->backlight_on = msecs_to_pps_units(50); /* no limit for T8, use T7 instead */
1529 spec->backlight_off = msecs_to_pps_units(50); /* no limit for T9, make it symmetric with T8 */
1530 spec->power_down = msecs_to_pps_units(500); /* T10 */
1531 spec->power_cycle = msecs_to_pps_units(10 + 500); /* T11+T12 */
1532
1533 intel_pps_dump_state(intel_dp, "spec", spec);
1534 }
1535
pps_init_delays(struct intel_dp * intel_dp)1536 static void pps_init_delays(struct intel_dp *intel_dp)
1537 {
1538 struct intel_display *display = to_intel_display(intel_dp);
1539 struct intel_pps_delays cur, vbt, spec,
1540 *final = &intel_dp->pps.pps_delays;
1541
1542 lockdep_assert_held(&display->pps.mutex);
1543
1544 /* already initialized? */
1545 if (pps_delays_valid(final))
1546 return;
1547
1548 pps_init_delays_bios(intel_dp, &cur);
1549 pps_init_delays_vbt(intel_dp, &vbt);
1550 pps_init_delays_spec(intel_dp, &spec);
1551
1552 /* Use the max of the register settings and vbt. If both are
1553 * unset, fall back to the spec limits. */
1554 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
1555 spec.field : \
1556 max(cur.field, vbt.field))
1557 assign_final(power_up);
1558 assign_final(backlight_on);
1559 assign_final(backlight_off);
1560 assign_final(power_down);
1561 assign_final(power_cycle);
1562 #undef assign_final
1563
1564 intel_dp->pps.panel_power_up_delay = pps_units_to_msecs(final->power_up);
1565 intel_dp->pps.backlight_on_delay = pps_units_to_msecs(final->backlight_on);
1566 intel_dp->pps.backlight_off_delay = pps_units_to_msecs(final->backlight_off);
1567 intel_dp->pps.panel_power_down_delay = pps_units_to_msecs(final->power_down);
1568 intel_dp->pps.panel_power_cycle_delay = pps_units_to_msecs(final->power_cycle);
1569
1570 drm_dbg_kms(display->drm,
1571 "panel power up delay %d, power down delay %d, power cycle delay %d\n",
1572 intel_dp->pps.panel_power_up_delay,
1573 intel_dp->pps.panel_power_down_delay,
1574 intel_dp->pps.panel_power_cycle_delay);
1575
1576 drm_dbg_kms(display->drm, "backlight on delay %d, off delay %d\n",
1577 intel_dp->pps.backlight_on_delay,
1578 intel_dp->pps.backlight_off_delay);
1579
1580 /*
1581 * We override the HW backlight delays to 1 because we do manual waits
1582 * on them. For backlight_on, even BSpec recommends doing it. For
1583 * backlight_off, if we don't do this, we'll end up waiting for the
1584 * backlight off delay twice: once when we do the manual sleep, and
1585 * once when we disable the panel and wait for the PP_STATUS bit to
1586 * become zero.
1587 */
1588 final->backlight_on = 1;
1589 final->backlight_off = 1;
1590
1591 /*
1592 * HW has only a 100msec granularity for power_cycle so round it up
1593 * accordingly.
1594 */
1595 final->power_cycle = roundup(final->power_cycle, msecs_to_pps_units(100));
1596 }
1597
pps_init_registers(struct intel_dp * intel_dp,bool force_disable_vdd)1598 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd)
1599 {
1600 struct intel_display *display = to_intel_display(intel_dp);
1601 struct drm_i915_private *dev_priv = to_i915(display->drm);
1602 u32 pp_on, pp_off, port_sel = 0;
1603 int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000;
1604 struct pps_registers regs;
1605 enum port port = dp_to_dig_port(intel_dp)->base.port;
1606 const struct intel_pps_delays *seq = &intel_dp->pps.pps_delays;
1607
1608 lockdep_assert_held(&display->pps.mutex);
1609
1610 intel_pps_get_registers(intel_dp, ®s);
1611
1612 /*
1613 * On some VLV machines the BIOS can leave the VDD
1614 * enabled even on power sequencers which aren't
1615 * hooked up to any port. This would mess up the
1616 * power domain tracking the first time we pick
1617 * one of these power sequencers for use since
1618 * intel_pps_vdd_on_unlocked() would notice that the VDD was
1619 * already on and therefore wouldn't grab the power
1620 * domain reference. Disable VDD first to avoid this.
1621 * This also avoids spuriously turning the VDD on as
1622 * soon as the new power sequencer gets initialized.
1623 */
1624 if (force_disable_vdd) {
1625 u32 pp = ilk_get_pp_control(intel_dp);
1626
1627 drm_WARN(display->drm, pp & PANEL_POWER_ON,
1628 "Panel power already on\n");
1629
1630 if (pp & EDP_FORCE_VDD)
1631 drm_dbg_kms(display->drm,
1632 "VDD already on, disabling first\n");
1633
1634 pp &= ~EDP_FORCE_VDD;
1635
1636 intel_de_write(display, regs.pp_ctrl, pp);
1637 }
1638
1639 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->power_up) |
1640 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->backlight_on);
1641 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->backlight_off) |
1642 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->power_down);
1643
1644 /* Haswell doesn't have any port selection bits for the panel
1645 * power sequencer any more. */
1646 if (display->platform.valleyview || display->platform.cherryview) {
1647 port_sel = PANEL_PORT_SELECT_VLV(port);
1648 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
1649 switch (port) {
1650 case PORT_A:
1651 port_sel = PANEL_PORT_SELECT_DPA;
1652 break;
1653 case PORT_C:
1654 port_sel = PANEL_PORT_SELECT_DPC;
1655 break;
1656 case PORT_D:
1657 port_sel = PANEL_PORT_SELECT_DPD;
1658 break;
1659 default:
1660 MISSING_CASE(port);
1661 break;
1662 }
1663 }
1664
1665 pp_on |= port_sel;
1666
1667 intel_de_write(display, regs.pp_on, pp_on);
1668 intel_de_write(display, regs.pp_off, pp_off);
1669
1670 /*
1671 * Compute the divisor for the pp clock, simply match the Bspec formula.
1672 */
1673 if (i915_mmio_reg_valid(regs.pp_div))
1674 intel_de_write(display, regs.pp_div,
1675 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK,
1676 (100 * div) / 2 - 1) |
1677 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK,
1678 DIV_ROUND_UP(seq->power_cycle, 1000) + 1));
1679 else
1680 intel_de_rmw(display, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK,
1681 REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK,
1682 DIV_ROUND_UP(seq->power_cycle, 1000) + 1));
1683
1684 drm_dbg_kms(display->drm,
1685 "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
1686 intel_de_read(display, regs.pp_on),
1687 intel_de_read(display, regs.pp_off),
1688 i915_mmio_reg_valid(regs.pp_div) ?
1689 intel_de_read(display, regs.pp_div) :
1690 (intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
1691 }
1692
intel_pps_encoder_reset(struct intel_dp * intel_dp)1693 void intel_pps_encoder_reset(struct intel_dp *intel_dp)
1694 {
1695 struct intel_display *display = to_intel_display(intel_dp);
1696 intel_wakeref_t wakeref;
1697
1698 if (!intel_dp_is_edp(intel_dp))
1699 return;
1700
1701 with_intel_pps_lock(intel_dp, wakeref) {
1702 /*
1703 * Reinit the power sequencer also on the resume path, in case
1704 * BIOS did something nasty with it.
1705 */
1706 if (display->platform.valleyview || display->platform.cherryview)
1707 vlv_initial_power_sequencer_setup(intel_dp);
1708
1709 pps_init_delays(intel_dp);
1710 pps_init_registers(intel_dp, false);
1711 pps_vdd_init(intel_dp);
1712
1713 if (edp_have_panel_vdd(intel_dp))
1714 edp_panel_vdd_schedule_off(intel_dp);
1715 }
1716 }
1717
intel_pps_init(struct intel_dp * intel_dp)1718 bool intel_pps_init(struct intel_dp *intel_dp)
1719 {
1720 intel_wakeref_t wakeref;
1721 bool ret;
1722
1723 intel_dp->pps.initializing = true;
1724 INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
1725
1726 pps_init_timestamps(intel_dp);
1727
1728 with_intel_pps_lock(intel_dp, wakeref) {
1729 ret = pps_initial_setup(intel_dp);
1730
1731 pps_init_delays(intel_dp);
1732 pps_init_registers(intel_dp, false);
1733 pps_vdd_init(intel_dp);
1734 }
1735
1736 return ret;
1737 }
1738
pps_init_late(struct intel_dp * intel_dp)1739 static void pps_init_late(struct intel_dp *intel_dp)
1740 {
1741 struct intel_display *display = to_intel_display(intel_dp);
1742 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1743 struct intel_connector *connector = intel_dp->attached_connector;
1744
1745 if (display->platform.valleyview || display->platform.cherryview)
1746 return;
1747
1748 if (intel_num_pps(display) < 2)
1749 return;
1750
1751 drm_WARN(display->drm,
1752 connector->panel.vbt.backlight.controller >= 0 &&
1753 intel_dp->pps.pps_idx != connector->panel.vbt.backlight.controller,
1754 "[ENCODER:%d:%s] power sequencer mismatch: %d (initial) vs. %d (VBT)\n",
1755 encoder->base.base.id, encoder->base.name,
1756 intel_dp->pps.pps_idx, connector->panel.vbt.backlight.controller);
1757
1758 if (connector->panel.vbt.backlight.controller >= 0)
1759 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;
1760 }
1761
intel_pps_init_late(struct intel_dp * intel_dp)1762 void intel_pps_init_late(struct intel_dp *intel_dp)
1763 {
1764 intel_wakeref_t wakeref;
1765
1766 with_intel_pps_lock(intel_dp, wakeref) {
1767 /* Reinit delays after per-panel info has been parsed from VBT */
1768 pps_init_late(intel_dp);
1769
1770 memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays));
1771 pps_init_delays(intel_dp);
1772 pps_init_registers(intel_dp, false);
1773
1774 intel_dp->pps.initializing = false;
1775
1776 if (edp_have_panel_vdd(intel_dp))
1777 edp_panel_vdd_schedule_off(intel_dp);
1778 }
1779 }
1780
intel_pps_unlock_regs_wa(struct intel_display * display)1781 void intel_pps_unlock_regs_wa(struct intel_display *display)
1782 {
1783 int pps_num;
1784 int pps_idx;
1785
1786 if (!HAS_DISPLAY(display) || HAS_DDI(display))
1787 return;
1788 /*
1789 * This w/a is needed at least on CPT/PPT, but to be sure apply it
1790 * everywhere where registers can be write protected.
1791 */
1792 pps_num = intel_num_pps(display);
1793
1794 for (pps_idx = 0; pps_idx < pps_num; pps_idx++)
1795 intel_de_rmw(display, PP_CONTROL(display, pps_idx),
1796 PANEL_UNLOCK_MASK, PANEL_UNLOCK_REGS);
1797 }
1798
intel_pps_setup(struct intel_display * display)1799 void intel_pps_setup(struct intel_display *display)
1800 {
1801 struct drm_i915_private *i915 = to_i915(display->drm);
1802
1803 if (HAS_PCH_SPLIT(i915) || display->platform.geminilake || display->platform.broxton)
1804 display->pps.mmio_base = PCH_PPS_BASE;
1805 else if (display->platform.valleyview || display->platform.cherryview)
1806 display->pps.mmio_base = VLV_PPS_BASE;
1807 else
1808 display->pps.mmio_base = PPS_BASE;
1809 }
1810
intel_pps_show(struct seq_file * m,void * data)1811 static int intel_pps_show(struct seq_file *m, void *data)
1812 {
1813 struct intel_connector *connector = m->private;
1814 struct intel_dp *intel_dp = intel_attached_dp(connector);
1815
1816 if (connector->base.status != connector_status_connected)
1817 return -ENODEV;
1818
1819 seq_printf(m, "Panel power up delay: %d\n",
1820 intel_dp->pps.panel_power_up_delay);
1821 seq_printf(m, "Panel power down delay: %d\n",
1822 intel_dp->pps.panel_power_down_delay);
1823 seq_printf(m, "Panel power cycle delay: %d\n",
1824 intel_dp->pps.panel_power_cycle_delay);
1825 seq_printf(m, "Backlight on delay: %d\n",
1826 intel_dp->pps.backlight_on_delay);
1827 seq_printf(m, "Backlight off delay: %d\n",
1828 intel_dp->pps.backlight_off_delay);
1829
1830 return 0;
1831 }
1832 DEFINE_SHOW_ATTRIBUTE(intel_pps);
1833
intel_pps_connector_debugfs_add(struct intel_connector * connector)1834 void intel_pps_connector_debugfs_add(struct intel_connector *connector)
1835 {
1836 struct dentry *root = connector->base.debugfs_entry;
1837 int connector_type = connector->base.connector_type;
1838
1839 if (connector_type == DRM_MODE_CONNECTOR_eDP)
1840 debugfs_create_file("i915_panel_timings", 0444, root,
1841 connector, &intel_pps_fops);
1842 }
1843
assert_pps_unlocked(struct intel_display * display,enum pipe pipe)1844 void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)
1845 {
1846 struct drm_i915_private *dev_priv = to_i915(display->drm);
1847 i915_reg_t pp_reg;
1848 u32 val;
1849 enum pipe panel_pipe = INVALID_PIPE;
1850 bool locked = true;
1851
1852 if (drm_WARN_ON(display->drm, HAS_DDI(display)))
1853 return;
1854
1855 if (HAS_PCH_SPLIT(dev_priv)) {
1856 u32 port_sel;
1857
1858 pp_reg = PP_CONTROL(display, 0);
1859 port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &
1860 PANEL_PORT_SELECT_MASK;
1861
1862 switch (port_sel) {
1863 case PANEL_PORT_SELECT_LVDS:
1864 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1865 break;
1866 case PANEL_PORT_SELECT_DPA:
1867 g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1868 break;
1869 case PANEL_PORT_SELECT_DPC:
1870 g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1871 break;
1872 case PANEL_PORT_SELECT_DPD:
1873 g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1874 break;
1875 default:
1876 MISSING_CASE(port_sel);
1877 break;
1878 }
1879 } else if (display->platform.valleyview || display->platform.cherryview) {
1880 /* presumably write lock depends on pipe, not port select */
1881 pp_reg = PP_CONTROL(display, pipe);
1882 panel_pipe = pipe;
1883 } else {
1884 u32 port_sel;
1885
1886 pp_reg = PP_CONTROL(display, 0);
1887 port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &
1888 PANEL_PORT_SELECT_MASK;
1889
1890 drm_WARN_ON(display->drm,
1891 port_sel != PANEL_PORT_SELECT_LVDS);
1892 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1893 }
1894
1895 val = intel_de_read(display, pp_reg);
1896 if (!(val & PANEL_POWER_ON) ||
1897 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1898 locked = false;
1899
1900 INTEL_DISPLAY_STATE_WARN(display, panel_pipe == pipe && locked,
1901 "panel assertion failure, pipe %c regs locked\n",
1902 pipe_name(pipe));
1903 }
1904