1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright 2016 Nexenta Systems, Inc. 24 * Copyright (c) 2017 by Delphix. All rights reserved. 25 */ 26 /* 27 * Copyright (c) 2010, Intel Corporation. 28 * All rights reserved. 29 */ 30 31 /* 32 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 33 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 34 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 35 * PSMI 1.5 extensions are supported in Solaris Nevada. 36 * PSMI 1.6 extensions are supported in Solaris Nevada. 37 * PSMI 1.7 extensions are supported in Solaris Nevada. 38 */ 39 #define PSMI_1_7 40 41 #include <sys/processor.h> 42 #include <sys/time.h> 43 #include <sys/psm.h> 44 #include <sys/smp_impldefs.h> 45 #include <sys/cram.h> 46 #include <sys/acpi/acpi.h> 47 #include <sys/acpica.h> 48 #include <sys/psm_common.h> 49 #include <sys/apic.h> 50 #include <sys/apic_timer.h> 51 #include <sys/pit.h> 52 #include <sys/ddi.h> 53 #include <sys/sunddi.h> 54 #include <sys/ddi_impldefs.h> 55 #include <sys/pci.h> 56 #include <sys/promif.h> 57 #include <sys/x86_archext.h> 58 #include <sys/cpc_impl.h> 59 #include <sys/uadmin.h> 60 #include <sys/panic.h> 61 #include <sys/debug.h> 62 #include <sys/archsystm.h> 63 #include <sys/trap.h> 64 #include <sys/machsystm.h> 65 #include <sys/cpuvar.h> 66 #include <sys/rm_platter.h> 67 #include <sys/privregs.h> 68 #include <sys/cyclic.h> 69 #include <sys/note.h> 70 #include <sys/pci_intr_lib.h> 71 #include <sys/sunndi.h> 72 #if !defined(__xpv) 73 #include <sys/hpet.h> 74 #include <sys/clock.h> 75 #endif 76 77 /* 78 * Local Function Prototypes 79 */ 80 static int apic_handle_defconf(); 81 static int apic_parse_mpct(caddr_t mpct, int bypass); 82 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size); 83 static int apic_checksum(caddr_t bptr, int len); 84 static int apic_find_bus_type(char *bus); 85 static int apic_find_bus(int busid); 86 static struct apic_io_intr *apic_find_io_intr(int irqno); 87 static int apic_find_free_irq(int start, int end); 88 struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid); 89 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp); 90 static void apic_free_apic_cpus(void); 91 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr); 92 static int apic_acpi_enter_apicmode(void); 93 94 int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, 95 int child_ipin, struct apic_io_intr **intrp); 96 int apic_find_bus_id(int bustype); 97 int apic_find_intin(uchar_t ioapic, uchar_t intin); 98 void apic_record_rdt_entry(apic_irq_t *irqptr, int irq); 99 100 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */ 101 102 /* ACPI SCI interrupt configuration; -1 if SCI not used */ 103 int apic_sci_vect = -1; 104 iflag_t apic_sci_flags; 105 106 #if !defined(__xpv) 107 /* ACPI HPET interrupt configuration; -1 if HPET not used */ 108 int apic_hpet_vect = -1; 109 iflag_t apic_hpet_flags; 110 #endif 111 112 /* 113 * psm name pointer 114 */ 115 char *psm_name; 116 117 /* ACPI support routines */ 118 static int acpi_probe(char *); 119 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 120 int *pci_irqp, iflag_t *intr_flagp); 121 122 int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 123 int ipin, int *pci_irqp, iflag_t *intr_flagp); 124 uchar_t acpi_find_ioapic(int irq); 125 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2); 126 127 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */ 128 int apic_max_reps_clear_pending = 1000; 129 130 int apic_intr_policy = INTR_ROUND_ROBIN; 131 132 int apic_next_bind_cpu = 1; /* For round robin assignment */ 133 /* start with cpu 1 */ 134 135 /* 136 * If enabled, the distribution works as follows: 137 * On every interrupt entry, the current ipl for the CPU is set in cpu_info 138 * and the irq corresponding to the ipl is also set in the aci_current array. 139 * interrupt exit and setspl (due to soft interrupts) will cause the current 140 * ipl to be be changed. This is cache friendly as these frequently used 141 * paths write into a per cpu structure. 142 * 143 * Sampling is done by checking the structures for all CPUs and incrementing 144 * the busy field of the irq (if any) executing on each CPU and the busy field 145 * of the corresponding CPU. 146 * In periodic mode this is done on every clock interrupt. 147 * In one-shot mode, this is done thru a cyclic with an interval of 148 * apic_redistribute_sample_interval (default 10 milli sec). 149 * 150 * Every apic_sample_factor_redistribution times we sample, we do computations 151 * to decide which interrupt needs to be migrated (see comments 152 * before apic_intr_redistribute(). 153 */ 154 155 /* 156 * Following 3 variables start as % and can be patched or set using an 157 * API to be defined in future. They will be scaled to 158 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic 159 * mode), or 101 in one-shot mode to stagger it away from one sec processing 160 */ 161 162 int apic_int_busy_mark = 60; 163 int apic_int_free_mark = 20; 164 int apic_diff_for_redistribution = 10; 165 166 /* sampling interval for interrupt redistribution for dynamic migration */ 167 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */ 168 169 /* 170 * number of times we sample before deciding to redistribute interrupts 171 * for dynamic migration 172 */ 173 int apic_sample_factor_redistribution = 101; 174 175 int apic_redist_cpu_skip = 0; 176 int apic_num_imbalance = 0; 177 int apic_num_rebind = 0; 178 179 /* 180 * Maximum number of APIC CPUs in the system, -1 indicates that dynamic 181 * allocation of CPU ids is disabled. 182 */ 183 int apic_max_nproc = -1; 184 int apic_nproc = 0; 185 size_t apic_cpus_size = 0; 186 int apic_defconf = 0; 187 int apic_irq_translate = 0; 188 int apic_spec_rev = 0; 189 int apic_imcrp = 0; 190 191 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */ 192 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */ 193 194 /* 195 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource 196 * will be assigned (via _SRS). If it is not set, use the current 197 * irq setting (via _CRS), but only if that irq is in the set of possible 198 * irqs (returned by _PRS) for the device. 199 */ 200 int apic_unconditional_srs = 1; 201 202 /* 203 * For interrupt link devices, if apic_prefer_crs is set when we are 204 * assigning an IRQ resource to a device, prefer the current IRQ setting 205 * over other possible irq settings under same conditions. 206 */ 207 208 int apic_prefer_crs = 1; 209 210 uchar_t apic_io_id[MAX_IO_APIC]; 211 volatile uint32_t *apicioadr[MAX_IO_APIC]; 212 uchar_t apic_io_ver[MAX_IO_APIC]; 213 uchar_t apic_io_vectbase[MAX_IO_APIC]; 214 uchar_t apic_io_vectend[MAX_IO_APIC]; 215 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1]; 216 uint32_t apic_physaddr[MAX_IO_APIC]; 217 218 boolean_t ioapic_mask_workaround[MAX_IO_APIC]; 219 220 /* 221 * First available slot to be used as IRQ index into the apic_irq_table 222 * for those interrupts (like MSI/X) that don't have a physical IRQ. 223 */ 224 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ; 225 226 /* 227 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound 228 * and bound elements of cpus_info and the temp_cpu element of irq_struct 229 */ 230 lock_t apic_ioapic_lock; 231 232 int apic_io_max = 0; /* no. of i/o apics enabled */ 233 234 struct apic_io_intr *apic_io_intrp = NULL; 235 static struct apic_bus *apic_busp; 236 237 uchar_t apic_resv_vector[MAXIPL+1]; 238 239 char apic_level_intr[APIC_MAX_VECTOR+1]; 240 241 uint32_t eisa_level_intr_mask = 0; 242 /* At least MSB will be set if EISA bus */ 243 244 int apic_pci_bus_total = 0; 245 uchar_t apic_single_pci_busid = 0; 246 247 /* 248 * airq_mutex protects additions to the apic_irq_table - the first 249 * pointer and any airq_nexts off of that one. It also protects 250 * apic_max_device_irq & apic_min_device_irq. It also guarantees 251 * that share_id is unique as new ids are generated only when new 252 * irq_t structs are linked in. Once linked in the structs are never 253 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed 254 * or allocated. Note that there is a slight gap between allocating in 255 * apic_introp_xlate and programming in addspl. 256 */ 257 kmutex_t airq_mutex; 258 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 259 int apic_max_device_irq = 0; 260 int apic_min_device_irq = APIC_MAX_VECTOR; 261 262 typedef struct prs_irq_list_ent { 263 int list_prio; 264 int32_t irq; 265 iflag_t intrflags; 266 acpi_prs_private_t prsprv; 267 struct prs_irq_list_ent *next; 268 } prs_irq_list_t; 269 270 271 /* 272 * ACPI variables 273 */ 274 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */ 275 int apic_enable_acpi = 0; 276 277 /* ACPI Multiple APIC Description Table ptr */ 278 static ACPI_TABLE_MADT *acpi_mapic_dtp = NULL; 279 280 /* ACPI Interrupt Source Override Structure ptr */ 281 ACPI_MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL; 282 int acpi_iso_cnt = 0; 283 284 /* ACPI Non-maskable Interrupt Sources ptr */ 285 static ACPI_MADT_NMI_SOURCE *acpi_nmi_sp = NULL; 286 static int acpi_nmi_scnt = 0; 287 static ACPI_MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL; 288 static int acpi_nmi_ccnt = 0; 289 290 static boolean_t acpi_found_smp_config = B_FALSE; 291 292 /* 293 * The following added to identify a software poweroff method if available. 294 */ 295 296 static struct { 297 int poweroff_method; 298 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */ 299 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */ 300 } apic_mps_ids[] = { 301 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */ 302 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */ 303 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */ 304 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */ 305 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */ 306 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */ 307 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */ 308 }; 309 310 int apic_poweroff_method = APIC_POWEROFF_NONE; 311 312 /* 313 * Auto-configuration routines 314 */ 315 316 /* 317 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here 318 * May work with 1.1 - but not guaranteed. 319 * According to the MP Spec, the MP floating pointer structure 320 * will be searched in the order described below: 321 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA) 322 * 2. Within the last kilobyte of system base memory 323 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh 324 * Once we find the right signature with proper checksum, we call 325 * either handle_defconf or parse_mpct to get all info necessary for 326 * subsequent operations. 327 */ 328 int 329 apic_probe_common(char *modname) 330 { 331 uint32_t mpct_addr, ebda_start = 0, base_mem_end; 332 caddr_t biosdatap; 333 caddr_t mpct = 0; 334 caddr_t fptr; 335 int i, mpct_size, mapsize, retval = PSM_FAILURE; 336 ushort_t ebda_seg, base_mem_size; 337 struct apic_mpfps_hdr *fpsp; 338 struct apic_mp_cnf_hdr *hdrp; 339 int bypass_cpu_and_ioapics_in_mptables; 340 int acpi_user_options; 341 342 if (apic_forceload < 0) 343 return (retval); 344 345 /* 346 * Remember who we are 347 */ 348 psm_name = modname; 349 350 /* Allow override for MADT-only mode */ 351 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0, 352 "acpi-user-options", 0); 353 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0); 354 355 /* Allow apic_use_acpi to override MADT-only mode */ 356 if (!apic_use_acpi) 357 apic_use_acpi_madt_only = 0; 358 359 retval = acpi_probe(modname); 360 361 /* 362 * mapin the bios data area 40:0 363 * 40:13h - two-byte location reports the base memory size 364 * 40:0Eh - two-byte location for the exact starting address of 365 * the EBDA segment for EISA 366 */ 367 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ); 368 if (!biosdatap) 369 goto apic_ret; 370 fpsp = (struct apic_mpfps_hdr *)NULL; 371 mapsize = MPFPS_RAM_WIN_LEN; 372 /*LINTED: pointer cast may result in improper alignment */ 373 ebda_seg = *((ushort_t *)(biosdatap+0xe)); 374 /* check the 1k of EBDA */ 375 if (ebda_seg) { 376 ebda_start = ((uint32_t)ebda_seg) << 4; 377 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ); 378 if (fptr) { 379 if (!(fpsp = 380 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN))) 381 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 382 } 383 } 384 /* If not in EBDA, check the last k of system base memory */ 385 if (!fpsp) { 386 /*LINTED: pointer cast may result in improper alignment */ 387 base_mem_size = *((ushort_t *)(biosdatap + 0x13)); 388 389 if (base_mem_size > 512) 390 base_mem_end = 639 * 1024; 391 else 392 base_mem_end = 511 * 1024; 393 /* if ebda == last k of base mem, skip to check BIOS ROM */ 394 if (base_mem_end != ebda_start) { 395 396 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN, 397 PROT_READ); 398 399 if (fptr) { 400 if (!(fpsp = apic_find_fps_sig(fptr, 401 MPFPS_RAM_WIN_LEN))) 402 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 403 } 404 } 405 } 406 psm_unmap_phys(biosdatap, 0x20); 407 408 /* If still cannot find it, check the BIOS ROM space */ 409 if (!fpsp) { 410 mapsize = MPFPS_ROM_WIN_LEN; 411 fptr = psm_map_phys(MPFPS_ROM_WIN_START, 412 MPFPS_ROM_WIN_LEN, PROT_READ); 413 if (fptr) { 414 if (!(fpsp = 415 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) { 416 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 417 goto apic_ret; 418 } 419 } 420 } 421 422 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) { 423 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 424 goto apic_ret; 425 } 426 427 apic_spec_rev = fpsp->mpfps_spec_rev; 428 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) { 429 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 430 goto apic_ret; 431 } 432 433 /* check IMCR is present or not */ 434 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP; 435 436 /* check default configuration (dual CPUs) */ 437 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) { 438 psm_unmap_phys(fptr, mapsize); 439 if ((retval = apic_handle_defconf()) != PSM_SUCCESS) 440 return (retval); 441 442 goto apic_ret; 443 } 444 445 /* MP Configuration Table */ 446 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr); 447 448 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */ 449 450 /* 451 * Map in enough memory for the MP Configuration Table Header. 452 * Use this table to read the total length of the BIOS data and 453 * map in all the info 454 */ 455 /*LINTED: pointer cast may result in improper alignment */ 456 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr, 457 sizeof (struct apic_mp_cnf_hdr), PROT_READ); 458 if (!hdrp) 459 goto apic_ret; 460 461 /* check mp configuration table signature PCMP */ 462 if (hdrp->mpcnf_sig != 0x504d4350) { 463 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 464 goto apic_ret; 465 } 466 mpct_size = (int)hdrp->mpcnf_tbl_length; 467 468 apic_set_pwroff_method_from_mpcnfhdr(hdrp); 469 470 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 471 472 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) { 473 /* This is an ACPI machine No need for further checks */ 474 goto apic_ret; 475 } 476 477 /* 478 * Map in the entries for this machine, ie. Processor 479 * Entry Tables, Bus Entry Tables, etc. 480 * They are in fixed order following one another 481 */ 482 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ); 483 if (!mpct) 484 goto apic_ret; 485 486 if (apic_checksum(mpct, mpct_size) != 0) 487 goto apic_fail1; 488 489 /*LINTED: pointer cast may result in improper alignment */ 490 hdrp = (struct apic_mp_cnf_hdr *)mpct; 491 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic, 492 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 493 if (!apicadr) 494 goto apic_fail1; 495 496 /* Parse all information in the tables */ 497 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS); 498 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) == 499 PSM_SUCCESS) { 500 retval = PSM_SUCCESS; 501 goto apic_ret; 502 } 503 504 apic_fail1: 505 psm_unmap_phys(mpct, mpct_size); 506 mpct = NULL; 507 508 apic_ret: 509 if (retval == PSM_SUCCESS) { 510 extern int apic_ioapic_method_probe(); 511 512 if ((retval = apic_ioapic_method_probe()) == PSM_SUCCESS) 513 return (PSM_SUCCESS); 514 } 515 516 for (i = 0; i < apic_io_max; i++) 517 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 518 if (apic_cpus) { 519 kmem_free(apic_cpus, apic_cpus_size); 520 apic_cpus = NULL; 521 } 522 if (apicadr) { 523 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 524 apicadr = NULL; 525 } 526 if (mpct) 527 psm_unmap_phys(mpct, mpct_size); 528 529 return (retval); 530 } 531 532 static void 533 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp) 534 { 535 int i; 536 537 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0])); 538 i++) { 539 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id, 540 strlen(apic_mps_ids[i].oem_id)) == 0) && 541 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id, 542 strlen(apic_mps_ids[i].prod_id)) == 0)) { 543 544 apic_poweroff_method = apic_mps_ids[i].poweroff_method; 545 break; 546 } 547 } 548 549 if (apic_debug_mps_id != 0) { 550 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'" 551 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n", 552 psm_name, 553 hdrp->mpcnf_oem_str[0], 554 hdrp->mpcnf_oem_str[1], 555 hdrp->mpcnf_oem_str[2], 556 hdrp->mpcnf_oem_str[3], 557 hdrp->mpcnf_oem_str[4], 558 hdrp->mpcnf_oem_str[5], 559 hdrp->mpcnf_oem_str[6], 560 hdrp->mpcnf_oem_str[7], 561 hdrp->mpcnf_prod_str[0], 562 hdrp->mpcnf_prod_str[1], 563 hdrp->mpcnf_prod_str[2], 564 hdrp->mpcnf_prod_str[3], 565 hdrp->mpcnf_prod_str[4], 566 hdrp->mpcnf_prod_str[5], 567 hdrp->mpcnf_prod_str[6], 568 hdrp->mpcnf_prod_str[7], 569 hdrp->mpcnf_prod_str[8], 570 hdrp->mpcnf_prod_str[9], 571 hdrp->mpcnf_prod_str[10], 572 hdrp->mpcnf_prod_str[11]); 573 } 574 } 575 576 static void 577 apic_free_apic_cpus(void) 578 { 579 if (apic_cpus != NULL) { 580 kmem_free(apic_cpus, apic_cpus_size); 581 apic_cpus = NULL; 582 apic_cpus_size = 0; 583 } 584 } 585 586 static int 587 acpi_probe(char *modname) 588 { 589 int i, intmax, index; 590 uint32_t id, ver; 591 int acpi_verboseflags = 0; 592 int madt_seen, madt_size; 593 ACPI_SUBTABLE_HEADER *ap; 594 ACPI_MADT_LOCAL_APIC *mpa; 595 ACPI_MADT_LOCAL_X2APIC *mpx2a; 596 ACPI_MADT_IO_APIC *mia; 597 ACPI_MADT_IO_SAPIC *misa; 598 ACPI_MADT_INTERRUPT_OVERRIDE *mio; 599 ACPI_MADT_NMI_SOURCE *mns; 600 ACPI_MADT_INTERRUPT_SOURCE *mis; 601 ACPI_MADT_LOCAL_APIC_NMI *mlan; 602 ACPI_MADT_LOCAL_X2APIC_NMI *mx2alan; 603 ACPI_MADT_LOCAL_APIC_OVERRIDE *mao; 604 int sci; 605 iflag_t sci_flags; 606 volatile uint32_t *ioapic; 607 int ioapic_ix; 608 uint32_t *local_ids; 609 uint32_t *proc_ids; 610 uchar_t hid; 611 int warned = 0; 612 613 if (!apic_use_acpi) 614 return (PSM_FAILURE); 615 616 if (AcpiGetTable(ACPI_SIG_MADT, 1, 617 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) { 618 cmn_err(CE_WARN, "!acpi_probe: No MADT found!"); 619 return (PSM_FAILURE); 620 } 621 622 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->Address, 623 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 624 if (!apicadr) 625 return (PSM_FAILURE); 626 627 if ((local_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t), 628 KM_NOSLEEP)) == NULL) 629 return (PSM_FAILURE); 630 631 if ((proc_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t), 632 KM_NOSLEEP)) == NULL) { 633 kmem_free(local_ids, NCPU * sizeof (uint32_t)); 634 return (PSM_FAILURE); 635 } 636 637 id = apic_reg_ops->apic_read(APIC_LID_REG); 638 local_ids[0] = (uchar_t)(id >> 24); 639 apic_nproc = index = 1; 640 apic_io_max = 0; 641 642 ap = (ACPI_SUBTABLE_HEADER *) (acpi_mapic_dtp + 1); 643 madt_size = acpi_mapic_dtp->Header.Length; 644 madt_seen = sizeof (*acpi_mapic_dtp); 645 646 while (madt_seen < madt_size) { 647 switch (ap->Type) { 648 case ACPI_MADT_TYPE_LOCAL_APIC: 649 mpa = (ACPI_MADT_LOCAL_APIC *) ap; 650 if (mpa->LapicFlags & ACPI_MADT_ENABLED) { 651 if (mpa->Id == 255) { 652 cmn_err(CE_WARN, "!%s: encountered " 653 "invalid entry in MADT: CPU %d " 654 "has Local APIC Id equal to 255 ", 655 psm_name, mpa->ProcessorId); 656 } 657 if (mpa->Id == local_ids[0]) { 658 ASSERT(index == 1); 659 proc_ids[0] = mpa->ProcessorId; 660 } else if (apic_nproc < NCPU && use_mp && 661 apic_nproc < boot_ncpus) { 662 local_ids[index] = mpa->Id; 663 proc_ids[index] = mpa->ProcessorId; 664 index++; 665 apic_nproc++; 666 } else if (apic_nproc == NCPU && !warned) { 667 cmn_err(CE_WARN, "%s: CPU limit " 668 "exceeded" 669 #if !defined(__amd64) 670 " for 32-bit mode" 671 #endif 672 "; Solaris will use %d CPUs.", 673 psm_name, NCPU); 674 warned = 1; 675 } 676 } 677 break; 678 679 case ACPI_MADT_TYPE_IO_APIC: 680 mia = (ACPI_MADT_IO_APIC *) ap; 681 if (apic_io_max < MAX_IO_APIC) { 682 ioapic_ix = apic_io_max; 683 apic_io_id[apic_io_max] = mia->Id; 684 apic_io_vectbase[apic_io_max] = 685 mia->GlobalIrqBase; 686 apic_physaddr[apic_io_max] = 687 (uint32_t)mia->Address; 688 ioapic = apicioadr[apic_io_max] = 689 mapin_ioapic((uint32_t)mia->Address, 690 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 691 if (!ioapic) 692 goto cleanup; 693 ioapic_mask_workaround[apic_io_max] = 694 apic_is_ioapic_AMD_813x(mia->Address); 695 apic_io_max++; 696 } 697 break; 698 699 case ACPI_MADT_TYPE_INTERRUPT_OVERRIDE: 700 mio = (ACPI_MADT_INTERRUPT_OVERRIDE *) ap; 701 if (acpi_isop == NULL) 702 acpi_isop = mio; 703 acpi_iso_cnt++; 704 break; 705 706 case ACPI_MADT_TYPE_NMI_SOURCE: 707 /* UNIMPLEMENTED */ 708 mns = (ACPI_MADT_NMI_SOURCE *) ap; 709 if (acpi_nmi_sp == NULL) 710 acpi_nmi_sp = mns; 711 acpi_nmi_scnt++; 712 713 cmn_err(CE_NOTE, "!apic: nmi source: %d 0x%x\n", 714 mns->GlobalIrq, mns->IntiFlags); 715 break; 716 717 case ACPI_MADT_TYPE_LOCAL_APIC_NMI: 718 /* UNIMPLEMENTED */ 719 mlan = (ACPI_MADT_LOCAL_APIC_NMI *) ap; 720 if (acpi_nmi_cp == NULL) 721 acpi_nmi_cp = mlan; 722 acpi_nmi_ccnt++; 723 724 cmn_err(CE_NOTE, "!apic: local nmi: %d 0x%x %d\n", 725 mlan->ProcessorId, mlan->IntiFlags, 726 mlan->Lint); 727 break; 728 729 case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE: 730 /* UNIMPLEMENTED */ 731 mao = (ACPI_MADT_LOCAL_APIC_OVERRIDE *) ap; 732 cmn_err(CE_NOTE, "!apic: address override: %lx\n", 733 (long)mao->Address); 734 break; 735 736 case ACPI_MADT_TYPE_IO_SAPIC: 737 /* UNIMPLEMENTED */ 738 misa = (ACPI_MADT_IO_SAPIC *) ap; 739 740 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n", 741 misa->Id, misa->GlobalIrqBase, 742 (long)misa->Address); 743 break; 744 745 case ACPI_MADT_TYPE_INTERRUPT_SOURCE: 746 /* UNIMPLEMENTED */ 747 mis = (ACPI_MADT_INTERRUPT_SOURCE *) ap; 748 749 cmn_err(CE_NOTE, 750 "!apic: irq source: %d %d %d 0x%x %d %d\n", 751 mis->Id, mis->Eid, mis->GlobalIrq, 752 mis->IntiFlags, mis->Type, 753 mis->IoSapicVector); 754 break; 755 756 case ACPI_MADT_TYPE_LOCAL_X2APIC: 757 mpx2a = (ACPI_MADT_LOCAL_X2APIC *) ap; 758 759 if (mpx2a->LapicFlags & ACPI_MADT_ENABLED) { 760 if (mpx2a->LocalApicId == local_ids[0]) { 761 ASSERT(index == 1); 762 proc_ids[0] = mpx2a->Uid; 763 } else if (apic_nproc < NCPU && use_mp && 764 apic_nproc < boot_ncpus) { 765 local_ids[index] = mpx2a->LocalApicId; 766 proc_ids[index] = mpx2a->Uid; 767 index++; 768 apic_nproc++; 769 } else if (apic_nproc == NCPU && !warned) { 770 cmn_err(CE_WARN, "%s: CPU limit " 771 "exceeded" 772 #if !defined(__amd64) 773 " for 32-bit mode" 774 #endif 775 "; Solaris will use %d CPUs.", 776 psm_name, NCPU); 777 warned = 1; 778 } 779 } 780 781 break; 782 783 case ACPI_MADT_TYPE_LOCAL_X2APIC_NMI: 784 /* UNIMPLEMENTED */ 785 mx2alan = (ACPI_MADT_LOCAL_X2APIC_NMI *) ap; 786 if (mx2alan->Uid >> 8) 787 acpi_nmi_ccnt++; 788 789 #ifdef DEBUG 790 cmn_err(CE_NOTE, 791 "!apic: local x2apic nmi: %d 0x%x %d\n", 792 mx2alan->Uid, mx2alan->IntiFlags, mx2alan->Lint); 793 #endif 794 795 break; 796 797 case ACPI_MADT_TYPE_RESERVED: 798 default: 799 break; 800 } 801 802 /* advance to next entry */ 803 madt_seen += ap->Length; 804 ap = (ACPI_SUBTABLE_HEADER *)(((char *)ap) + ap->Length); 805 } 806 807 /* We found multiple enabled cpus via MADT */ 808 if ((apic_nproc > 1) && (apic_io_max > 0)) { 809 acpi_found_smp_config = B_TRUE; 810 cmn_err(CE_NOTE, 811 "!apic: Using ACPI (MADT) for SMP configuration"); 812 } 813 814 /* 815 * allocate enough space for possible hot-adding of CPUs. 816 * max_ncpus may be less than apic_nproc if it's set by user. 817 */ 818 if (plat_dr_support_cpu()) { 819 apic_max_nproc = max_ncpus; 820 } 821 apic_cpus_size = max(apic_nproc, max_ncpus) * sizeof (*apic_cpus); 822 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL) 823 goto cleanup; 824 825 /* 826 * ACPI doesn't provide the local apic ver, get it directly from the 827 * local apic 828 */ 829 ver = apic_reg_ops->apic_read(APIC_VERS_REG); 830 for (i = 0; i < apic_nproc; i++) { 831 apic_cpus[i].aci_local_id = local_ids[i]; 832 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF); 833 apic_cpus[i].aci_processor_id = proc_ids[i]; 834 /* Only build mapping info for CPUs present at boot. */ 835 if (i < boot_ncpus) 836 (void) acpica_map_cpu(i, proc_ids[i]); 837 } 838 839 /* 840 * To support CPU dynamic reconfiguration, the apic CPU info structure 841 * for each possible CPU will be pre-allocated at boot time. 842 * The state for each apic CPU info structure will be assigned according 843 * to the following rules: 844 * Rule 1: 845 * Slot index range: [0, min(apic_nproc, boot_ncpus)) 846 * State flags: 0 847 * Note: cpu exists and will be configured/enabled at boot time 848 * Rule 2: 849 * Slot index range: [boot_ncpus, apic_nproc) 850 * State flags: APIC_CPU_FREE | APIC_CPU_DIRTY 851 * Note: cpu exists but won't be configured/enabled at boot time 852 * Rule 3: 853 * Slot index range: [apic_nproc, boot_ncpus) 854 * State flags: APIC_CPU_FREE 855 * Note: cpu doesn't exist at boot time 856 * Rule 4: 857 * Slot index range: [max(apic_nproc, boot_ncpus), max_ncpus) 858 * State flags: APIC_CPU_FREE 859 * Note: cpu doesn't exist at boot time 860 */ 861 CPUSET_ZERO(apic_cpumask); 862 for (i = 0; i < min(boot_ncpus, apic_nproc); i++) { 863 CPUSET_ADD(apic_cpumask, i); 864 apic_cpus[i].aci_status = 0; 865 } 866 for (i = boot_ncpus; i < apic_nproc; i++) { 867 apic_cpus[i].aci_status = APIC_CPU_FREE | APIC_CPU_DIRTY; 868 } 869 for (i = apic_nproc; i < boot_ncpus; i++) { 870 apic_cpus[i].aci_status = APIC_CPU_FREE; 871 } 872 for (i = max(boot_ncpus, apic_nproc); i < max_ncpus; i++) { 873 apic_cpus[i].aci_status = APIC_CPU_FREE; 874 } 875 876 for (i = 0; i < apic_io_max; i++) { 877 ioapic_ix = i; 878 879 /* 880 * need to check Sitka on the following acpi problem 881 * On the Sitka, the ioapic's apic_id field isn't reporting 882 * the actual io apic id. We have reported this problem 883 * to Intel. Until they fix the problem, we will get the 884 * actual id directly from the ioapic. 885 */ 886 id = ioapic_read(ioapic_ix, APIC_ID_CMD); 887 hid = (uchar_t)(id >> 24); 888 889 if (hid != apic_io_id[i]) { 890 if (apic_io_id[i] == 0) 891 apic_io_id[i] = hid; 892 else { /* set ioapic id to whatever reported by ACPI */ 893 id = ((uint32_t)apic_io_id[i]) << 24; 894 ioapic_write(ioapic_ix, APIC_ID_CMD, id); 895 } 896 } 897 ver = ioapic_read(ioapic_ix, APIC_VERS_CMD); 898 apic_io_ver[i] = (uchar_t)(ver & 0xff); 899 intmax = (ver >> 16) & 0xff; 900 apic_io_vectend[i] = apic_io_vectbase[i] + intmax; 901 if (apic_first_avail_irq <= apic_io_vectend[i]) 902 apic_first_avail_irq = apic_io_vectend[i] + 1; 903 } 904 905 906 /* 907 * Process SCI configuration here 908 * An error may be returned here if 909 * acpi-user-options specifies legacy mode 910 * (no SCI, no ACPI mode) 911 */ 912 if (acpica_get_sci(&sci, &sci_flags) != AE_OK) 913 sci = -1; 914 915 /* 916 * Now call acpi_init() to generate namespaces 917 * If this fails, we don't attempt to use ACPI 918 * even if we were able to get a MADT above 919 */ 920 if (acpica_init() != AE_OK) { 921 cmn_err(CE_WARN, "!apic: Failed to initialize acpica!"); 922 goto cleanup; 923 } 924 925 /* 926 * Call acpica_build_processor_map() now that we have 927 * ACPI namesspace access 928 */ 929 (void) acpica_build_processor_map(); 930 931 /* 932 * Squirrel away the SCI and flags for later on 933 * in apic_picinit() when we're ready 934 */ 935 apic_sci_vect = sci; 936 apic_sci_flags = sci_flags; 937 938 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) 939 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG; 940 941 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) 942 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG; 943 944 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG) 945 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG; 946 947 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE) 948 goto cleanup; 949 950 /* Enable ACPI APIC interrupt routing */ 951 if (apic_acpi_enter_apicmode() != PSM_FAILURE) { 952 cmn_err(CE_NOTE, "!apic: Using APIC interrupt routing mode"); 953 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist); 954 apic_enable_acpi = 1; 955 if (apic_sci_vect > 0) { 956 acpica_set_core_feature(ACPI_FEATURE_SCI_EVENT); 957 } 958 if (apic_use_acpi_madt_only) { 959 cmn_err(CE_CONT, 960 "?Using ACPI for CPU/IOAPIC information ONLY\n"); 961 } 962 963 #if !defined(__xpv) 964 /* 965 * probe ACPI for hpet information here which is used later 966 * in apic_picinit(). 967 */ 968 if (hpet_acpi_init(&apic_hpet_vect, &apic_hpet_flags) < 0) { 969 cmn_err(CE_NOTE, "!ACPI HPET table query failed\n"); 970 } 971 #endif 972 973 kmem_free(local_ids, NCPU * sizeof (uint32_t)); 974 kmem_free(proc_ids, NCPU * sizeof (uint32_t)); 975 return (PSM_SUCCESS); 976 } 977 /* if setting APIC mode failed above, we fall through to cleanup */ 978 979 cleanup: 980 cmn_err(CE_WARN, "!apic: Failed acpi_probe, SMP config was %s", 981 acpi_found_smp_config ? "found" : "not found"); 982 apic_free_apic_cpus(); 983 if (apicadr != NULL) { 984 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 985 apicadr = NULL; 986 } 987 apic_max_nproc = -1; 988 apic_nproc = 0; 989 for (i = 0; i < apic_io_max; i++) { 990 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 991 apicioadr[i] = NULL; 992 } 993 apic_io_max = 0; 994 acpi_isop = NULL; 995 acpi_iso_cnt = 0; 996 acpi_nmi_sp = NULL; 997 acpi_nmi_scnt = 0; 998 acpi_nmi_cp = NULL; 999 acpi_nmi_ccnt = 0; 1000 acpi_found_smp_config = B_FALSE; 1001 kmem_free(local_ids, NCPU * sizeof (uint32_t)); 1002 kmem_free(proc_ids, NCPU * sizeof (uint32_t)); 1003 return (PSM_FAILURE); 1004 } 1005 1006 /* 1007 * Handle default configuration. Fill in reqd global variables & tables 1008 * Fill all details as MP table does not give any more info 1009 */ 1010 static int 1011 apic_handle_defconf() 1012 { 1013 uint_t lid; 1014 1015 /* Failed to probe ACPI MADT tables, disable CPU DR. */ 1016 apic_max_nproc = -1; 1017 apic_free_apic_cpus(); 1018 plat_dr_disable_cpu(); 1019 1020 apicioadr[0] = (void *)mapin_ioapic(APIC_IO_ADDR, 1021 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 1022 apicadr = (void *)psm_map_phys(APIC_LOCAL_ADDR, 1023 APIC_LOCAL_MEMLEN, PROT_READ); 1024 apic_cpus_size = 2 * sizeof (*apic_cpus); 1025 apic_cpus = (apic_cpus_info_t *) 1026 kmem_zalloc(apic_cpus_size, KM_NOSLEEP); 1027 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus)) 1028 goto apic_handle_defconf_fail; 1029 CPUSET_ONLY(apic_cpumask, 0); 1030 CPUSET_ADD(apic_cpumask, 1); 1031 apic_nproc = 2; 1032 lid = apic_reg_ops->apic_read(APIC_LID_REG); 1033 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET); 1034 /* 1035 * According to the PC+MP spec 1.1, the local ids 1036 * for the default configuration has to be 0 or 1 1037 */ 1038 if (apic_cpus[0].aci_local_id == 1) 1039 apic_cpus[1].aci_local_id = 0; 1040 else if (apic_cpus[0].aci_local_id == 0) 1041 apic_cpus[1].aci_local_id = 1; 1042 else 1043 goto apic_handle_defconf_fail; 1044 1045 apic_io_id[0] = 2; 1046 apic_io_max = 1; 1047 if (apic_defconf >= 5) { 1048 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS; 1049 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS; 1050 apic_io_ver[0] = APIC_INTEGRATED_VERS; 1051 } else { 1052 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */ 1053 apic_cpus[1].aci_local_ver = 0; 1054 apic_io_ver[0] = 0; 1055 } 1056 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6) 1057 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 1058 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 1059 return (PSM_SUCCESS); 1060 1061 apic_handle_defconf_fail: 1062 if (apicadr) 1063 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 1064 if (apicioadr[0]) 1065 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN); 1066 return (PSM_FAILURE); 1067 } 1068 1069 /* Parse the entries in MP configuration table and collect info that we need */ 1070 static int 1071 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics) 1072 { 1073 struct apic_procent *procp; 1074 struct apic_bus *busp; 1075 struct apic_io_entry *ioapicp; 1076 struct apic_io_intr *intrp; 1077 int ioapic_ix; 1078 uint_t lid; 1079 uint32_t id; 1080 uchar_t hid; 1081 int warned = 0; 1082 1083 /*LINTED: pointer cast may result in improper alignment */ 1084 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 1085 1086 /* No need to count cpu entries if we won't use them */ 1087 if (!bypass_cpus_and_ioapics) { 1088 1089 /* Find max # of CPUS and allocate structure accordingly */ 1090 apic_nproc = 0; 1091 CPUSET_ZERO(apic_cpumask); 1092 while (procp->proc_entry == APIC_CPU_ENTRY) { 1093 if (procp->proc_cpuflags & CPUFLAGS_EN) { 1094 if (apic_nproc < NCPU && use_mp && 1095 apic_nproc < boot_ncpus) { 1096 CPUSET_ADD(apic_cpumask, apic_nproc); 1097 apic_nproc++; 1098 } else if (apic_nproc == NCPU && !warned) { 1099 cmn_err(CE_WARN, "%s: CPU limit " 1100 "exceeded" 1101 #if !defined(__amd64) 1102 " for 32-bit mode" 1103 #endif 1104 "; Solaris will use %d CPUs.", 1105 psm_name, NCPU); 1106 warned = 1; 1107 } 1108 1109 } 1110 procp++; 1111 } 1112 apic_cpus_size = apic_nproc * sizeof (*apic_cpus); 1113 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *) 1114 kmem_zalloc(apic_cpus_size, KM_NOSLEEP))) 1115 return (PSM_FAILURE); 1116 } 1117 1118 /*LINTED: pointer cast may result in improper alignment */ 1119 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 1120 1121 /* 1122 * start with index 1 as 0 needs to be filled in with Boot CPU, but 1123 * if we're bypassing this information, it has already been filled 1124 * in by acpi_probe(), so don't overwrite it. 1125 */ 1126 if (!bypass_cpus_and_ioapics) 1127 apic_nproc = 1; 1128 1129 while (procp->proc_entry == APIC_CPU_ENTRY) { 1130 /* check whether the cpu exists or not */ 1131 if (!bypass_cpus_and_ioapics && 1132 procp->proc_cpuflags & CPUFLAGS_EN) { 1133 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */ 1134 lid = apic_reg_ops->apic_read(APIC_LID_REG); 1135 apic_cpus[0].aci_local_id = procp->proc_apicid; 1136 if (apic_cpus[0].aci_local_id != 1137 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) { 1138 return (PSM_FAILURE); 1139 } 1140 apic_cpus[0].aci_local_ver = 1141 procp->proc_version; 1142 } else if (apic_nproc < NCPU && use_mp && 1143 apic_nproc < boot_ncpus) { 1144 apic_cpus[apic_nproc].aci_local_id = 1145 procp->proc_apicid; 1146 1147 apic_cpus[apic_nproc].aci_local_ver = 1148 procp->proc_version; 1149 apic_nproc++; 1150 1151 } 1152 } 1153 procp++; 1154 } 1155 1156 /* 1157 * Save start of bus entries for later use. 1158 * Get EISA level cntrl if EISA bus is present. 1159 * Also get the CPI bus id for single CPI bus case 1160 */ 1161 apic_busp = busp = (struct apic_bus *)procp; 1162 while (busp->bus_entry == APIC_BUS_ENTRY) { 1163 lid = apic_find_bus_type((char *)&busp->bus_str1); 1164 if (lid == BUS_EISA) { 1165 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 1166 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 1167 } else if (lid == BUS_PCI) { 1168 /* 1169 * apic_single_pci_busid will be used only if 1170 * apic_pic_bus_total is equal to 1 1171 */ 1172 apic_pci_bus_total++; 1173 apic_single_pci_busid = busp->bus_id; 1174 } 1175 busp++; 1176 } 1177 1178 ioapicp = (struct apic_io_entry *)busp; 1179 1180 if (!bypass_cpus_and_ioapics) 1181 apic_io_max = 0; 1182 do { 1183 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) { 1184 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) { 1185 apic_io_id[apic_io_max] = ioapicp->io_apicid; 1186 apic_io_ver[apic_io_max] = ioapicp->io_version; 1187 apicioadr[apic_io_max] = 1188 (void *)mapin_ioapic( 1189 (uint32_t)ioapicp->io_apic_addr, 1190 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 1191 1192 if (!apicioadr[apic_io_max]) 1193 return (PSM_FAILURE); 1194 1195 ioapic_mask_workaround[apic_io_max] = 1196 apic_is_ioapic_AMD_813x( 1197 ioapicp->io_apic_addr); 1198 1199 ioapic_ix = apic_io_max; 1200 id = ioapic_read(ioapic_ix, APIC_ID_CMD); 1201 hid = (uchar_t)(id >> 24); 1202 1203 if (hid != apic_io_id[apic_io_max]) { 1204 if (apic_io_id[apic_io_max] == 0) 1205 apic_io_id[apic_io_max] = hid; 1206 else { 1207 /* 1208 * set ioapic id to whatever 1209 * reported by MPS 1210 * 1211 * may not need to set index 1212 * again ??? 1213 * take it out and try 1214 */ 1215 1216 id = ((uint32_t) 1217 apic_io_id[apic_io_max]) << 1218 24; 1219 1220 ioapic_write(ioapic_ix, 1221 APIC_ID_CMD, id); 1222 } 1223 } 1224 apic_io_max++; 1225 } 1226 } 1227 ioapicp++; 1228 } while (ioapicp->io_entry == APIC_IO_ENTRY); 1229 1230 apic_io_intrp = (struct apic_io_intr *)ioapicp; 1231 1232 intrp = apic_io_intrp; 1233 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1234 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) || 1235 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) { 1236 apic_irq_translate = 1; 1237 break; 1238 } 1239 intrp++; 1240 } 1241 1242 return (PSM_SUCCESS); 1243 } 1244 1245 boolean_t 1246 apic_cpu_in_range(int cpu) 1247 { 1248 cpu &= ~IRQ_USER_BOUND; 1249 /* Check whether cpu id is in valid range. */ 1250 if (cpu < 0 || cpu >= apic_nproc) { 1251 return (B_FALSE); 1252 } else if (apic_max_nproc != -1 && cpu >= apic_max_nproc) { 1253 /* 1254 * Check whether cpuid is in valid range if CPU DR is enabled. 1255 */ 1256 return (B_FALSE); 1257 } else if (!CPU_IN_SET(apic_cpumask, cpu)) { 1258 return (B_FALSE); 1259 } 1260 1261 return (B_TRUE); 1262 } 1263 1264 processorid_t 1265 apic_get_next_bind_cpu(void) 1266 { 1267 int i, count; 1268 processorid_t cpuid = 0; 1269 1270 for (count = 0; count < apic_nproc; count++) { 1271 if (apic_next_bind_cpu >= apic_nproc) { 1272 apic_next_bind_cpu = 0; 1273 } 1274 i = apic_next_bind_cpu++; 1275 if (apic_cpu_in_range(i)) { 1276 cpuid = i; 1277 break; 1278 } 1279 } 1280 1281 return (cpuid); 1282 } 1283 1284 uint16_t 1285 apic_get_apic_version() 1286 { 1287 int i; 1288 uchar_t min_io_apic_ver = 0; 1289 static uint16_t version; /* Cache as value is constant */ 1290 static boolean_t found = B_FALSE; /* Accomodate zero version */ 1291 1292 if (found == B_FALSE) { 1293 found = B_TRUE; 1294 1295 /* 1296 * Don't assume all IO APICs in the system are the same. 1297 * 1298 * Set to the minimum version. 1299 */ 1300 for (i = 0; i < apic_io_max; i++) { 1301 if ((apic_io_ver[i] != 0) && 1302 ((min_io_apic_ver == 0) || 1303 (min_io_apic_ver >= apic_io_ver[i]))) 1304 min_io_apic_ver = apic_io_ver[i]; 1305 } 1306 1307 /* Assume all local APICs are of the same version. */ 1308 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver; 1309 } 1310 return (version); 1311 } 1312 1313 static struct apic_mpfps_hdr * 1314 apic_find_fps_sig(caddr_t cptr, int len) 1315 { 1316 int i; 1317 1318 /* Look for the pattern "_MP_" */ 1319 for (i = 0; i < len; i += 16) { 1320 if ((*(cptr+i) == '_') && 1321 (*(cptr+i+1) == 'M') && 1322 (*(cptr+i+2) == 'P') && 1323 (*(cptr+i+3) == '_')) 1324 /*LINTED: pointer cast may result in improper alignment */ 1325 return ((struct apic_mpfps_hdr *)(cptr + i)); 1326 } 1327 return (NULL); 1328 } 1329 1330 static int 1331 apic_checksum(caddr_t bptr, int len) 1332 { 1333 int i; 1334 uchar_t cksum; 1335 1336 cksum = 0; 1337 for (i = 0; i < len; i++) 1338 cksum += *bptr++; 1339 return ((int)cksum); 1340 } 1341 1342 /* 1343 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge 1344 * needs special handling. We may need to chase up the device tree, 1345 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions", 1346 * to find the IPIN at the root bus that relates to the IPIN on the 1347 * subsidiary bus (for ACPI or MP). We may, however, have an entry 1348 * in the MP table or the ACPI namespace for this device itself. 1349 * We handle both cases in the search below. 1350 */ 1351 /* this is the non-acpi version */ 1352 int 1353 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin, 1354 struct apic_io_intr **intrp) 1355 { 1356 dev_info_t *dipp, *dip; 1357 int pci_irq; 1358 ddi_acc_handle_t cfg_handle; 1359 int bridge_devno, bridge_bus; 1360 int ipin; 1361 1362 dip = idip; 1363 1364 /*CONSTCOND*/ 1365 while (1) { 1366 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) || 1367 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS)) 1368 return (-1); 1369 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) == 1370 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle, 1371 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) { 1372 pci_config_teardown(&cfg_handle); 1373 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno, 1374 NULL) != 0) 1375 return (-1); 1376 /* 1377 * This is the rotating scheme documented in the 1378 * PCI-to-PCI spec. If the PCI-to-PCI bridge is 1379 * behind another PCI-to-PCI bridge, then it needs 1380 * to keep ascending until an interrupt entry is 1381 * found or the root is reached. 1382 */ 1383 ipin = (child_devno + child_ipin) % PCI_INTD; 1384 if (bridge_bus == 0 && apic_pci_bus_total == 1) 1385 bridge_bus = (int)apic_single_pci_busid; 1386 pci_irq = ((bridge_devno & 0x1f) << 2) | 1387 (ipin & 0x3); 1388 if ((*intrp = apic_find_io_intr_w_busid(pci_irq, 1389 bridge_bus)) != NULL) { 1390 return (pci_irq); 1391 } 1392 dip = dipp; 1393 child_devno = bridge_devno; 1394 child_ipin = ipin; 1395 } else { 1396 pci_config_teardown(&cfg_handle); 1397 return (-1); 1398 } 1399 } 1400 /*LINTED: function will not fall off the bottom */ 1401 } 1402 1403 uchar_t 1404 acpi_find_ioapic(int irq) 1405 { 1406 int i; 1407 1408 for (i = 0; i < apic_io_max; i++) { 1409 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i]) 1410 return ((uchar_t)i); 1411 } 1412 return (0xFF); /* shouldn't happen */ 1413 } 1414 1415 /* 1416 * See if two irqs are compatible for sharing a vector. 1417 * Currently we only support sharing of PCI devices. 1418 */ 1419 static int 1420 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2) 1421 { 1422 uint_t level1, po1; 1423 uint_t level2, po2; 1424 1425 /* Assume active high by default */ 1426 po1 = 0; 1427 po2 = 0; 1428 1429 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI) 1430 return (0); 1431 1432 if (iflag1.intr_el == INTR_EL_CONFORM) 1433 level1 = AV_LEVEL; 1434 else 1435 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1436 1437 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) || 1438 (iflag1.intr_po == INTR_PO_CONFORM))) 1439 po1 = AV_ACTIVE_LOW; 1440 1441 if (iflag2.intr_el == INTR_EL_CONFORM) 1442 level2 = AV_LEVEL; 1443 else 1444 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1445 1446 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) || 1447 (iflag2.intr_po == INTR_PO_CONFORM))) 1448 po2 = AV_ACTIVE_LOW; 1449 1450 if ((level1 == level2) && (po1 == po2)) 1451 return (1); 1452 1453 return (0); 1454 } 1455 1456 struct apic_io_intr * 1457 apic_find_io_intr_w_busid(int irqno, int busid) 1458 { 1459 struct apic_io_intr *intrp; 1460 1461 /* 1462 * It can have more than 1 entry with same source bus IRQ, 1463 * but unique with the source bus id 1464 */ 1465 intrp = apic_io_intrp; 1466 if (intrp != NULL) { 1467 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1468 if (intrp->intr_irq == irqno && 1469 intrp->intr_busid == busid && 1470 intrp->intr_type == IO_INTR_INT) 1471 return (intrp); 1472 intrp++; 1473 } 1474 } 1475 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:" 1476 "busid %x:%x\n", irqno, busid)); 1477 return ((struct apic_io_intr *)NULL); 1478 } 1479 1480 1481 struct mps_bus_info { 1482 char *bus_name; 1483 int bus_id; 1484 } bus_info_array[] = { 1485 "ISA ", BUS_ISA, 1486 "PCI ", BUS_PCI, 1487 "EISA ", BUS_EISA, 1488 "XPRESS", BUS_XPRESS, 1489 "PCMCIA", BUS_PCMCIA, 1490 "VL ", BUS_VL, 1491 "CBUS ", BUS_CBUS, 1492 "CBUSII", BUS_CBUSII, 1493 "FUTURE", BUS_FUTURE, 1494 "INTERN", BUS_INTERN, 1495 "MBI ", BUS_MBI, 1496 "MBII ", BUS_MBII, 1497 "MPI ", BUS_MPI, 1498 "MPSA ", BUS_MPSA, 1499 "NUBUS ", BUS_NUBUS, 1500 "TC ", BUS_TC, 1501 "VME ", BUS_VME, 1502 "PCI-E ", BUS_PCIE 1503 }; 1504 1505 static int 1506 apic_find_bus_type(char *bus) 1507 { 1508 int i = 0; 1509 1510 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++) 1511 if (strncmp(bus, bus_info_array[i].bus_name, 1512 strlen(bus_info_array[i].bus_name)) == 0) 1513 return (bus_info_array[i].bus_id); 1514 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus)); 1515 return (0); 1516 } 1517 1518 static int 1519 apic_find_bus(int busid) 1520 { 1521 struct apic_bus *busp; 1522 1523 busp = apic_busp; 1524 while (busp->bus_entry == APIC_BUS_ENTRY) { 1525 if (busp->bus_id == busid) 1526 return (apic_find_bus_type((char *)&busp->bus_str1)); 1527 busp++; 1528 } 1529 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid)); 1530 return (0); 1531 } 1532 1533 int 1534 apic_find_bus_id(int bustype) 1535 { 1536 struct apic_bus *busp; 1537 1538 busp = apic_busp; 1539 while (busp->bus_entry == APIC_BUS_ENTRY) { 1540 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype) 1541 return (busp->bus_id); 1542 busp++; 1543 } 1544 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x", 1545 bustype)); 1546 return (-1); 1547 } 1548 1549 /* 1550 * Check if a particular irq need to be reserved for any io_intr 1551 */ 1552 static struct apic_io_intr * 1553 apic_find_io_intr(int irqno) 1554 { 1555 struct apic_io_intr *intrp; 1556 1557 intrp = apic_io_intrp; 1558 if (intrp != NULL) { 1559 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1560 if (intrp->intr_irq == irqno && 1561 intrp->intr_type == IO_INTR_INT) 1562 return (intrp); 1563 intrp++; 1564 } 1565 } 1566 return ((struct apic_io_intr *)NULL); 1567 } 1568 1569 /* 1570 * Check if the given ioapicindex intin combination has already been assigned 1571 * an irq. If so return irqno. Else -1 1572 */ 1573 int 1574 apic_find_intin(uchar_t ioapic, uchar_t intin) 1575 { 1576 apic_irq_t *irqptr; 1577 int i; 1578 1579 /* find ioapic and intin in the apic_irq_table[] and return the index */ 1580 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 1581 irqptr = apic_irq_table[i]; 1582 while (irqptr) { 1583 if ((irqptr->airq_mps_intr_index >= 0) && 1584 (irqptr->airq_intin_no == intin) && 1585 (irqptr->airq_ioapicindex == ioapic)) { 1586 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq " 1587 "entry for ioapic:intin %x:%x " 1588 "shared interrupts ?", ioapic, intin)); 1589 return (i); 1590 } 1591 irqptr = irqptr->airq_next; 1592 } 1593 } 1594 return (-1); 1595 } 1596 1597 int 1598 apic_allocate_irq(int irq) 1599 { 1600 int freeirq, i; 1601 1602 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1) 1603 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ, 1604 (irq - 1))) == -1) { 1605 /* 1606 * if BIOS really defines every single irq in the mps 1607 * table, then don't worry about conflicting with 1608 * them, just use any free slot in apic_irq_table 1609 */ 1610 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 1611 if ((apic_irq_table[i] == NULL) || 1612 apic_irq_table[i]->airq_mps_intr_index == 1613 FREE_INDEX) { 1614 freeirq = i; 1615 break; 1616 } 1617 } 1618 if (freeirq == -1) { 1619 /* This shouldn't happen, but just in case */ 1620 cmn_err(CE_WARN, "%s: NO available IRQ", psm_name); 1621 return (-1); 1622 } 1623 } 1624 if (apic_irq_table[freeirq] == NULL) { 1625 apic_irq_table[freeirq] = 1626 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP); 1627 if (apic_irq_table[freeirq] == NULL) { 1628 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ", 1629 psm_name); 1630 return (-1); 1631 } 1632 apic_irq_table[freeirq]->airq_temp_cpu = IRQ_UNINIT; 1633 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX; 1634 } 1635 return (freeirq); 1636 } 1637 1638 static int 1639 apic_find_free_irq(int start, int end) 1640 { 1641 int i; 1642 1643 for (i = start; i <= end; i++) 1644 /* Check if any I/O entry needs this IRQ */ 1645 if (apic_find_io_intr(i) == NULL) { 1646 /* Then see if it is free */ 1647 if ((apic_irq_table[i] == NULL) || 1648 (apic_irq_table[i]->airq_mps_intr_index == 1649 FREE_INDEX)) { 1650 return (i); 1651 } 1652 } 1653 return (-1); 1654 } 1655 1656 /* 1657 * compute the polarity, trigger mode and vector for programming into 1658 * the I/O apic and record in airq_rdt_entry. 1659 */ 1660 void 1661 apic_record_rdt_entry(apic_irq_t *irqptr, int irq) 1662 { 1663 int ioapicindex, bus_type, vector; 1664 short intr_index; 1665 uint_t level, po, io_po; 1666 struct apic_io_intr *iointrp; 1667 1668 intr_index = irqptr->airq_mps_intr_index; 1669 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d " 1670 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq, 1671 (void *)irqptr->airq_dip, irqptr->airq_vector)); 1672 1673 if (intr_index == RESERVE_INDEX) { 1674 apic_error |= APIC_ERR_INVALID_INDEX; 1675 return; 1676 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) { 1677 return; 1678 } 1679 1680 vector = irqptr->airq_vector; 1681 ioapicindex = irqptr->airq_ioapicindex; 1682 /* Assume edge triggered by default */ 1683 level = 0; 1684 /* Assume active high by default */ 1685 po = 0; 1686 1687 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) { 1688 ASSERT(irq < 16); 1689 if (eisa_level_intr_mask & (1 << irq)) 1690 level = AV_LEVEL; 1691 if (intr_index == FREE_INDEX && apic_defconf == 0) 1692 apic_error |= APIC_ERR_INVALID_INDEX; 1693 } else if (intr_index == ACPI_INDEX) { 1694 bus_type = irqptr->airq_iflag.bustype; 1695 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) { 1696 if (bus_type == BUS_PCI) 1697 level = AV_LEVEL; 1698 } else 1699 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ? 1700 AV_LEVEL : 0; 1701 if (level && 1702 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) || 1703 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM && 1704 bus_type == BUS_PCI))) 1705 po = AV_ACTIVE_LOW; 1706 } else { 1707 iointrp = apic_io_intrp + intr_index; 1708 bus_type = apic_find_bus(iointrp->intr_busid); 1709 if (iointrp->intr_el == INTR_EL_CONFORM) { 1710 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq))) 1711 level = AV_LEVEL; 1712 else if (bus_type == BUS_PCI) 1713 level = AV_LEVEL; 1714 } else 1715 level = (iointrp->intr_el == INTR_EL_LEVEL) ? 1716 AV_LEVEL : 0; 1717 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) || 1718 (iointrp->intr_po == INTR_PO_CONFORM && 1719 bus_type == BUS_PCI))) 1720 po = AV_ACTIVE_LOW; 1721 } 1722 if (level) 1723 apic_level_intr[irq] = 1; 1724 /* 1725 * The 82489DX External APIC cannot do active low polarity interrupts. 1726 */ 1727 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX)) 1728 io_po = po; 1729 else 1730 io_po = 0; 1731 1732 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) 1733 prom_printf("setio: ioapic=0x%x intin=0x%x level=0x%x po=0x%x " 1734 "vector=0x%x cpu=0x%x\n\n", ioapicindex, 1735 irqptr->airq_intin_no, level, io_po, vector, 1736 irqptr->airq_cpu); 1737 1738 irqptr->airq_rdt_entry = level|io_po|vector; 1739 } 1740 1741 int 1742 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 1743 int ipin, int *pci_irqp, iflag_t *intr_flagp) 1744 { 1745 1746 int status; 1747 acpi_psm_lnk_t acpipsmlnk; 1748 1749 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp, 1750 intr_flagp)) == ACPI_PSM_SUCCESS) { 1751 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d " 1752 "from cache for device %s, instance #%d\n", psm_name, 1753 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 1754 return (status); 1755 } 1756 1757 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t)); 1758 1759 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp, 1760 &acpipsmlnk)) == ACPI_PSM_FAILURE) { 1761 APIC_VERBOSE_IRQ((CE_WARN, "%s: " 1762 " acpi_translate_pci_irq failed for device %s, instance" 1763 " #%d", psm_name, ddi_get_name(dip), 1764 ddi_get_instance(dip))); 1765 return (status); 1766 } 1767 1768 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) { 1769 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp, 1770 intr_flagp); 1771 if (status != ACPI_PSM_SUCCESS) { 1772 status = acpi_get_current_irq_resource(&acpipsmlnk, 1773 pci_irqp, intr_flagp); 1774 } 1775 } 1776 1777 if (status == ACPI_PSM_SUCCESS) { 1778 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp, 1779 intr_flagp, &acpipsmlnk); 1780 1781 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] " 1782 "new irq %d for device %s, instance #%d\n", psm_name, 1783 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 1784 } 1785 1786 return (status); 1787 } 1788 1789 /* 1790 * Adds an entry to the irq list passed in, and returns the new list. 1791 * Entries are added in priority order (lower numerical priorities are 1792 * placed closer to the head of the list) 1793 */ 1794 static prs_irq_list_t * 1795 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq, 1796 iflag_t *iflagp, acpi_prs_private_t *prsprvp) 1797 { 1798 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp; 1799 1800 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP); 1801 1802 newent->list_prio = priority; 1803 newent->irq = irq; 1804 newent->intrflags = *iflagp; 1805 newent->prsprv = *prsprvp; 1806 /* ->next is NULL from kmem_zalloc */ 1807 1808 /* 1809 * New list -- return the new entry as the list. 1810 */ 1811 if (listp == NULL) 1812 return (newent); 1813 1814 /* 1815 * Save original list pointer for return (since we're not modifying 1816 * the head) 1817 */ 1818 origlistp = listp; 1819 1820 /* 1821 * Insertion sort, with entries with identical keys stored AFTER 1822 * existing entries (the less-than-or-equal test of priority does 1823 * this for us). 1824 */ 1825 while (listp != NULL && listp->list_prio <= priority) { 1826 prevp = listp; 1827 listp = listp->next; 1828 } 1829 1830 newent->next = listp; 1831 1832 if (prevp == NULL) { /* Add at head of list (newent is the new head) */ 1833 return (newent); 1834 } else { 1835 prevp->next = newent; 1836 return (origlistp); 1837 } 1838 } 1839 1840 /* 1841 * Frees the list passed in, deallocating all memory and leaving *listpp 1842 * set to NULL. 1843 */ 1844 static void 1845 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp) 1846 { 1847 struct prs_irq_list_ent *nextp; 1848 1849 ASSERT(listpp != NULL); 1850 1851 while (*listpp != NULL) { 1852 nextp = (*listpp)->next; 1853 kmem_free(*listpp, sizeof (struct prs_irq_list_ent)); 1854 *listpp = nextp; 1855 } 1856 } 1857 1858 /* 1859 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of 1860 * irqs returned by the link device's _PRS method. The irqs are chosen 1861 * to minimize contention in situations where the interrupt link device 1862 * can be programmed to steer interrupts to different interrupt controller 1863 * inputs (some of which may already be in use). The list is sorted in order 1864 * of irqs to use, with the highest priority given to interrupt controller 1865 * inputs that are not shared. When an interrupt controller input 1866 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the 1867 * returned list in the order that minimizes sharing (thereby ensuring lowest 1868 * possible latency from interrupt trigger time to ISR execution time). 1869 */ 1870 static prs_irq_list_t * 1871 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip, 1872 int crs_irq) 1873 { 1874 int32_t irq; 1875 int i; 1876 prs_irq_list_t *prsirqlistp = NULL; 1877 iflag_t iflags; 1878 1879 while (irqlistent != NULL) { 1880 irqlistent->intr_flags.bustype = BUS_PCI; 1881 1882 for (i = 0; i < irqlistent->num_irqs; i++) { 1883 1884 irq = irqlistent->irqs[i]; 1885 1886 if (irq <= 0) { 1887 /* invalid irq number */ 1888 continue; 1889 } 1890 1891 if ((irq < 16) && (apic_reserved_irqlist[irq])) 1892 continue; 1893 1894 if ((apic_irq_table[irq] == NULL) || 1895 (apic_irq_table[irq]->airq_dip == dip)) { 1896 1897 prsirqlistp = acpi_insert_prs_irq_ent( 1898 prsirqlistp, 0 /* Highest priority */, irq, 1899 &irqlistent->intr_flags, 1900 &irqlistent->acpi_prs_prv); 1901 1902 /* 1903 * If we do not prefer the current irq from _CRS 1904 * or if we do and this irq is the same as the 1905 * current irq from _CRS, this is the one 1906 * to pick. 1907 */ 1908 if (!(apic_prefer_crs) || (irq == crs_irq)) { 1909 return (prsirqlistp); 1910 } 1911 continue; 1912 } 1913 1914 /* 1915 * Edge-triggered interrupts cannot be shared 1916 */ 1917 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE) 1918 continue; 1919 1920 /* 1921 * To work around BIOSes that contain incorrect 1922 * interrupt polarity information in interrupt 1923 * descriptors returned by _PRS, we assume that 1924 * the polarity of the other device sharing this 1925 * interrupt controller input is compatible. 1926 * If it's not, the caller will catch it when 1927 * the caller invokes the link device's _CRS method 1928 * (after invoking its _SRS method). 1929 */ 1930 iflags = irqlistent->intr_flags; 1931 iflags.intr_po = 1932 apic_irq_table[irq]->airq_iflag.intr_po; 1933 1934 if (!acpi_intr_compatible(iflags, 1935 apic_irq_table[irq]->airq_iflag)) { 1936 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d " 1937 "not compatible [%x:%x:%x !~ %x:%x:%x]", 1938 psm_name, irq, 1939 iflags.intr_po, 1940 iflags.intr_el, 1941 iflags.bustype, 1942 apic_irq_table[irq]->airq_iflag.intr_po, 1943 apic_irq_table[irq]->airq_iflag.intr_el, 1944 apic_irq_table[irq]->airq_iflag.bustype)); 1945 continue; 1946 } 1947 1948 /* 1949 * If we prefer the irq from _CRS, no need 1950 * to search any further (and make sure 1951 * to add this irq with the highest priority 1952 * so it's tried first). 1953 */ 1954 if (crs_irq == irq && apic_prefer_crs) { 1955 1956 return (acpi_insert_prs_irq_ent( 1957 prsirqlistp, 1958 0 /* Highest priority */, 1959 irq, &iflags, 1960 &irqlistent->acpi_prs_prv)); 1961 } 1962 1963 /* 1964 * Priority is equal to the share count (lower 1965 * share count is higher priority). Note that 1966 * the intr flags passed in here are the ones we 1967 * changed above -- if incorrect, it will be 1968 * caught by the caller's _CRS flags comparison. 1969 */ 1970 prsirqlistp = acpi_insert_prs_irq_ent( 1971 prsirqlistp, 1972 apic_irq_table[irq]->airq_share, irq, 1973 &iflags, &irqlistent->acpi_prs_prv); 1974 } 1975 1976 /* Go to the next irqlist entry */ 1977 irqlistent = irqlistent->next; 1978 } 1979 1980 return (prsirqlistp); 1981 } 1982 1983 /* 1984 * Configures the irq for the interrupt link device identified by 1985 * acpipsmlnkp. 1986 * 1987 * Gets the current and the list of possible irq settings for the 1988 * device. If apic_unconditional_srs is not set, and the current 1989 * resource setting is in the list of possible irq settings, 1990 * current irq resource setting is passed to the caller. 1991 * 1992 * Otherwise, picks an irq number from the list of possible irq 1993 * settings, and sets the irq of the device to this value. 1994 * If prefer_crs is set, among a set of irq numbers in the list that have 1995 * the least number of devices sharing the interrupt, we pick current irq 1996 * resource setting if it is a member of this set. 1997 * 1998 * Passes the irq number in the value pointed to by pci_irqp, and 1999 * polarity and sensitivity in the structure pointed to by dipintrflagp 2000 * to the caller. 2001 * 2002 * Note that if setting the irq resource failed, but successfuly obtained 2003 * the current irq resource settings, passes the current irq resources 2004 * and considers it a success. 2005 * 2006 * Returns: 2007 * ACPI_PSM_SUCCESS on success. 2008 * 2009 * ACPI_PSM_FAILURE if an error occured during the configuration or 2010 * if a suitable irq was not found for this device, or if setting the 2011 * irq resource and obtaining the current resource fails. 2012 * 2013 */ 2014 static int 2015 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 2016 int *pci_irqp, iflag_t *dipintr_flagp) 2017 { 2018 int32_t irq; 2019 int cur_irq = -1; 2020 acpi_irqlist_t *irqlistp; 2021 prs_irq_list_t *prs_irq_listp, *prs_irq_entp; 2022 boolean_t found_irq = B_FALSE; 2023 2024 dipintr_flagp->bustype = BUS_PCI; 2025 2026 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp)) 2027 == ACPI_PSM_FAILURE) { 2028 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine " 2029 "or assign IRQ for device %s, instance #%d: The system was " 2030 "unable to get the list of potential IRQs from ACPI.", 2031 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 2032 2033 return (ACPI_PSM_FAILURE); 2034 } 2035 2036 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 2037 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) && 2038 (cur_irq > 0)) { 2039 /* 2040 * If an IRQ is set in CRS and that IRQ exists in the set 2041 * returned from _PRS, return that IRQ, otherwise print 2042 * a warning 2043 */ 2044 2045 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL) 2046 == ACPI_PSM_SUCCESS) { 2047 2048 ASSERT(pci_irqp != NULL); 2049 *pci_irqp = cur_irq; 2050 acpi_free_irqlist(irqlistp); 2051 return (ACPI_PSM_SUCCESS); 2052 } 2053 2054 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the " 2055 "current irq %d for device %s, instance #%d in ACPI's " 2056 "list of possible irqs for this device. Picking one from " 2057 " the latter list.", psm_name, cur_irq, ddi_get_name(dip), 2058 ddi_get_instance(dip))); 2059 } 2060 2061 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip, 2062 cur_irq)) == NULL) { 2063 2064 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a " 2065 "suitable irq from the list of possible irqs for device " 2066 "%s, instance #%d in ACPI's list of possible irqs", 2067 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 2068 2069 acpi_free_irqlist(irqlistp); 2070 return (ACPI_PSM_FAILURE); 2071 } 2072 2073 acpi_free_irqlist(irqlistp); 2074 2075 for (prs_irq_entp = prs_irq_listp; 2076 prs_irq_entp != NULL && found_irq == B_FALSE; 2077 prs_irq_entp = prs_irq_entp->next) { 2078 2079 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv; 2080 irq = prs_irq_entp->irq; 2081 2082 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for " 2083 "device %s instance #%d\n", psm_name, irq, 2084 ddi_get_name(dip), ddi_get_instance(dip))); 2085 2086 if ((acpi_set_irq_resource(acpipsmlnkp, irq)) 2087 == ACPI_PSM_SUCCESS) { 2088 /* 2089 * setting irq was successful, check to make sure CRS 2090 * reflects that. If CRS does not agree with what we 2091 * set, return the irq that was set. 2092 */ 2093 2094 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 2095 dipintr_flagp) == ACPI_PSM_SUCCESS) { 2096 2097 if (cur_irq != irq) 2098 APIC_VERBOSE_IRQ((CE_WARN, 2099 "!%s: IRQ resource set " 2100 "(irqno %d) for device %s " 2101 "instance #%d, differs from " 2102 "current setting irqno %d", 2103 psm_name, irq, ddi_get_name(dip), 2104 ddi_get_instance(dip), cur_irq)); 2105 } else { 2106 /* 2107 * On at least one system, there was a bug in 2108 * a DSDT method called by _STA, causing _STA to 2109 * indicate that the link device was disabled 2110 * (when, in fact, it was enabled). Since _SRS 2111 * succeeded, assume that _CRS is lying and use 2112 * the iflags from this _PRS interrupt choice. 2113 * If we're wrong about the flags, the polarity 2114 * will be incorrect and we may get an interrupt 2115 * storm, but there's not much else we can do 2116 * at this point. 2117 */ 2118 *dipintr_flagp = prs_irq_entp->intrflags; 2119 } 2120 2121 /* 2122 * Return the irq that was set, and not what _CRS 2123 * reports, since _CRS has been seen to return 2124 * different IRQs than what was passed to _SRS on some 2125 * systems (and just not return successfully on others). 2126 */ 2127 cur_irq = irq; 2128 found_irq = B_TRUE; 2129 } else { 2130 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource " 2131 "irq %d failed for device %s instance #%d", 2132 psm_name, irq, ddi_get_name(dip), 2133 ddi_get_instance(dip))); 2134 2135 if (cur_irq == -1) { 2136 acpi_destroy_prs_irq_list(&prs_irq_listp); 2137 return (ACPI_PSM_FAILURE); 2138 } 2139 } 2140 } 2141 2142 acpi_destroy_prs_irq_list(&prs_irq_listp); 2143 2144 if (!found_irq) 2145 return (ACPI_PSM_FAILURE); 2146 2147 ASSERT(pci_irqp != NULL); 2148 *pci_irqp = cur_irq; 2149 return (ACPI_PSM_SUCCESS); 2150 } 2151 2152 void 2153 ioapic_disable_redirection() 2154 { 2155 int ioapic_ix; 2156 int intin_max; 2157 int intin_ix; 2158 2159 /* Disable the I/O APIC redirection entries */ 2160 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) { 2161 2162 /* Bits 23-16 define the maximum redirection entries */ 2163 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16) 2164 & 0xff; 2165 2166 for (intin_ix = 0; intin_ix <= intin_max; intin_ix++) { 2167 /* 2168 * The assumption here is that this is safe, even for 2169 * systems with IOAPICs that suffer from the hardware 2170 * erratum because all devices have been quiesced before 2171 * this function is called from apic_shutdown() 2172 * (or equivalent). If that assumption turns out to be 2173 * false, this mask operation can induce the same 2174 * erratum result we're trying to avoid. 2175 */ 2176 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix, 2177 AV_MASK); 2178 } 2179 } 2180 } 2181 2182 /* 2183 * Looks for an IOAPIC with the specified physical address in the /ioapics 2184 * node in the device tree (created by the PCI enumerator). 2185 */ 2186 static boolean_t 2187 apic_is_ioapic_AMD_813x(uint32_t physaddr) 2188 { 2189 /* 2190 * Look in /ioapics, for the ioapic with 2191 * the physical address given 2192 */ 2193 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0); 2194 dev_info_t *ioapic_child; 2195 boolean_t rv = B_FALSE; 2196 int vid, did; 2197 uint64_t ioapic_paddr; 2198 boolean_t done = B_FALSE; 2199 2200 if (ioapicsnode == NULL) 2201 return (B_FALSE); 2202 2203 /* Load first child: */ 2204 ioapic_child = ddi_get_child(ioapicsnode); 2205 while (!done && ioapic_child != 0) { /* Iterate over children */ 2206 2207 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY, 2208 ioapic_child, DDI_PROP_DONTPASS, "reg", 0)) 2209 != 0 && physaddr == ioapic_paddr) { 2210 2211 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child, 2212 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0); 2213 2214 if (vid == VENID_AMD) { 2215 2216 did = ddi_prop_get_int(DDI_DEV_T_ANY, 2217 ioapic_child, DDI_PROP_DONTPASS, 2218 IOAPICS_PROP_DEVID, 0); 2219 2220 if (did == DEVID_8131_IOAPIC || 2221 did == DEVID_8132_IOAPIC) { 2222 rv = B_TRUE; 2223 done = B_TRUE; 2224 } 2225 } 2226 } 2227 2228 if (!done) 2229 ioapic_child = ddi_get_next_sibling(ioapic_child); 2230 } 2231 2232 /* The ioapics node was held by ddi_find_devinfo, so release it */ 2233 ndi_rele_devi(ioapicsnode); 2234 return (rv); 2235 } 2236 2237 struct apic_state { 2238 int32_t as_task_reg; 2239 int32_t as_dest_reg; 2240 int32_t as_format_reg; 2241 int32_t as_local_timer; 2242 int32_t as_pcint_vect; 2243 int32_t as_int_vect0; 2244 int32_t as_int_vect1; 2245 int32_t as_err_vect; 2246 int32_t as_init_count; 2247 int32_t as_divide_reg; 2248 int32_t as_spur_int_reg; 2249 uint32_t as_ioapic_ids[MAX_IO_APIC]; 2250 }; 2251 2252 2253 static int 2254 apic_acpi_enter_apicmode(void) 2255 { 2256 ACPI_OBJECT_LIST arglist; 2257 ACPI_OBJECT arg; 2258 ACPI_STATUS status; 2259 2260 /* Setup parameter object */ 2261 arglist.Count = 1; 2262 arglist.Pointer = &arg; 2263 arg.Type = ACPI_TYPE_INTEGER; 2264 arg.Integer.Value = ACPI_APIC_MODE; 2265 2266 status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL); 2267 /* 2268 * Per ACPI spec - section 5.8.1 _PIC Method 2269 * calling the \_PIC control method is optional for the OS 2270 * and might not be found. It's ok to not fail in such cases. 2271 * This is the case on linux KVM and qemu (status AE_NOT_FOUND) 2272 */ 2273 if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) { 2274 cmn_err(CE_NOTE, 2275 "!apic: Reporting APIC mode failed (via _PIC), err: 0x%x", 2276 ACPI_FAILURE(status)); 2277 return (PSM_FAILURE); 2278 } else { 2279 return (PSM_SUCCESS); 2280 } 2281 } 2282 2283 2284 static void 2285 apic_save_state(struct apic_state *sp) 2286 { 2287 int i, cpuid; 2288 ulong_t iflag; 2289 2290 PMD(PMD_SX, ("apic_save_state %p\n", (void *)sp)) 2291 /* 2292 * First the local APIC. 2293 */ 2294 sp->as_task_reg = apic_reg_ops->apic_get_pri(); 2295 sp->as_dest_reg = apic_reg_ops->apic_read(APIC_DEST_REG); 2296 if (apic_mode == LOCAL_APIC) 2297 sp->as_format_reg = apic_reg_ops->apic_read(APIC_FORMAT_REG); 2298 sp->as_local_timer = apic_reg_ops->apic_read(APIC_LOCAL_TIMER); 2299 sp->as_pcint_vect = apic_reg_ops->apic_read(APIC_PCINT_VECT); 2300 sp->as_int_vect0 = apic_reg_ops->apic_read(APIC_INT_VECT0); 2301 sp->as_int_vect1 = apic_reg_ops->apic_read(APIC_INT_VECT1); 2302 sp->as_err_vect = apic_reg_ops->apic_read(APIC_ERR_VECT); 2303 sp->as_init_count = apic_reg_ops->apic_read(APIC_INIT_COUNT); 2304 sp->as_divide_reg = apic_reg_ops->apic_read(APIC_DIVIDE_REG); 2305 sp->as_spur_int_reg = apic_reg_ops->apic_read(APIC_SPUR_INT_REG); 2306 2307 /* 2308 * If on the boot processor then save the IOAPICs' IDs 2309 */ 2310 if ((cpuid = psm_get_cpu_id()) == 0) { 2311 2312 iflag = intr_clear(); 2313 lock_set(&apic_ioapic_lock); 2314 2315 for (i = 0; i < apic_io_max; i++) 2316 sp->as_ioapic_ids[i] = ioapic_read(i, APIC_ID_CMD); 2317 2318 lock_clear(&apic_ioapic_lock); 2319 intr_restore(iflag); 2320 } 2321 2322 /* apic_state() is currently invoked only in Suspend/Resume */ 2323 apic_cpus[cpuid].aci_status |= APIC_CPU_SUSPEND; 2324 } 2325 2326 static void 2327 apic_restore_state(struct apic_state *sp) 2328 { 2329 int i; 2330 ulong_t iflag; 2331 2332 /* 2333 * First the local APIC. 2334 */ 2335 apic_reg_ops->apic_write_task_reg(sp->as_task_reg); 2336 if (apic_mode == LOCAL_APIC) { 2337 apic_reg_ops->apic_write(APIC_DEST_REG, sp->as_dest_reg); 2338 apic_reg_ops->apic_write(APIC_FORMAT_REG, sp->as_format_reg); 2339 } 2340 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, sp->as_local_timer); 2341 apic_reg_ops->apic_write(APIC_PCINT_VECT, sp->as_pcint_vect); 2342 apic_reg_ops->apic_write(APIC_INT_VECT0, sp->as_int_vect0); 2343 apic_reg_ops->apic_write(APIC_INT_VECT1, sp->as_int_vect1); 2344 apic_reg_ops->apic_write(APIC_ERR_VECT, sp->as_err_vect); 2345 apic_reg_ops->apic_write(APIC_INIT_COUNT, sp->as_init_count); 2346 apic_reg_ops->apic_write(APIC_DIVIDE_REG, sp->as_divide_reg); 2347 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, sp->as_spur_int_reg); 2348 2349 /* 2350 * the following only needs to be done once, so we do it on the 2351 * boot processor, since we know that we only have one of those 2352 */ 2353 if (psm_get_cpu_id() == 0) { 2354 2355 iflag = intr_clear(); 2356 lock_set(&apic_ioapic_lock); 2357 2358 /* Restore IOAPICs' APIC IDs */ 2359 for (i = 0; i < apic_io_max; i++) { 2360 ioapic_write(i, APIC_ID_CMD, sp->as_ioapic_ids[i]); 2361 } 2362 2363 lock_clear(&apic_ioapic_lock); 2364 intr_restore(iflag); 2365 2366 /* 2367 * Reenter APIC mode before restoring LNK devices 2368 */ 2369 (void) apic_acpi_enter_apicmode(); 2370 2371 /* 2372 * restore acpi link device mappings 2373 */ 2374 acpi_restore_link_devices(); 2375 } 2376 } 2377 2378 /* 2379 * Returns 0 on success 2380 */ 2381 int 2382 apic_state(psm_state_request_t *rp) 2383 { 2384 PMD(PMD_SX, ("apic_state ")) 2385 switch (rp->psr_cmd) { 2386 case PSM_STATE_ALLOC: 2387 rp->req.psm_state_req.psr_state = 2388 kmem_zalloc(sizeof (struct apic_state), KM_NOSLEEP); 2389 if (rp->req.psm_state_req.psr_state == NULL) 2390 return (ENOMEM); 2391 rp->req.psm_state_req.psr_state_size = 2392 sizeof (struct apic_state); 2393 PMD(PMD_SX, (":STATE_ALLOC: state %p, size %lx\n", 2394 rp->req.psm_state_req.psr_state, 2395 rp->req.psm_state_req.psr_state_size)) 2396 return (0); 2397 2398 case PSM_STATE_FREE: 2399 kmem_free(rp->req.psm_state_req.psr_state, 2400 rp->req.psm_state_req.psr_state_size); 2401 PMD(PMD_SX, (" STATE_FREE: state %p, size %lx\n", 2402 rp->req.psm_state_req.psr_state, 2403 rp->req.psm_state_req.psr_state_size)) 2404 return (0); 2405 2406 case PSM_STATE_SAVE: 2407 PMD(PMD_SX, (" STATE_SAVE: state %p, size %lx\n", 2408 rp->req.psm_state_req.psr_state, 2409 rp->req.psm_state_req.psr_state_size)) 2410 apic_save_state(rp->req.psm_state_req.psr_state); 2411 return (0); 2412 2413 case PSM_STATE_RESTORE: 2414 apic_restore_state(rp->req.psm_state_req.psr_state); 2415 PMD(PMD_SX, (" STATE_RESTORE: state %p, size %lx\n", 2416 rp->req.psm_state_req.psr_state, 2417 rp->req.psm_state_req.psr_state_size)) 2418 return (0); 2419 2420 default: 2421 return (EINVAL); 2422 } 2423 } 2424