1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright © 2019 Intel Corporation
4 */
5
6 #ifndef __INTEL_DISPLAY_POWER_H__
7 #define __INTEL_DISPLAY_POWER_H__
8
9 #include <linux/mutex.h>
10 #include <linux/workqueue.h>
11
12 #include "intel_wakeref.h"
13
14 enum aux_ch;
15 enum port;
16 struct drm_i915_private;
17 struct i915_power_well;
18 struct intel_display;
19 struct intel_encoder;
20 struct seq_file;
21
22 /*
23 * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances
24 * consecutive, so that the pipe,transcoder,port -> power domain macros
25 * work correctly.
26 */
27 enum intel_display_power_domain {
28 POWER_DOMAIN_DISPLAY_CORE,
29 POWER_DOMAIN_PIPE_A,
30 POWER_DOMAIN_PIPE_B,
31 POWER_DOMAIN_PIPE_C,
32 POWER_DOMAIN_PIPE_D,
33 POWER_DOMAIN_PIPE_PANEL_FITTER_A,
34 POWER_DOMAIN_PIPE_PANEL_FITTER_B,
35 POWER_DOMAIN_PIPE_PANEL_FITTER_C,
36 POWER_DOMAIN_PIPE_PANEL_FITTER_D,
37 POWER_DOMAIN_TRANSCODER_A,
38 POWER_DOMAIN_TRANSCODER_B,
39 POWER_DOMAIN_TRANSCODER_C,
40 POWER_DOMAIN_TRANSCODER_D,
41 POWER_DOMAIN_TRANSCODER_EDP,
42 POWER_DOMAIN_TRANSCODER_DSI_A,
43 POWER_DOMAIN_TRANSCODER_DSI_C,
44
45 /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
46 POWER_DOMAIN_TRANSCODER_VDSC_PW2,
47
48 POWER_DOMAIN_PORT_DDI_LANES_A,
49 POWER_DOMAIN_PORT_DDI_LANES_B,
50 POWER_DOMAIN_PORT_DDI_LANES_C,
51 POWER_DOMAIN_PORT_DDI_LANES_D,
52 POWER_DOMAIN_PORT_DDI_LANES_E,
53 POWER_DOMAIN_PORT_DDI_LANES_F,
54
55 POWER_DOMAIN_PORT_DDI_LANES_TC1,
56 POWER_DOMAIN_PORT_DDI_LANES_TC2,
57 POWER_DOMAIN_PORT_DDI_LANES_TC3,
58 POWER_DOMAIN_PORT_DDI_LANES_TC4,
59 POWER_DOMAIN_PORT_DDI_LANES_TC5,
60 POWER_DOMAIN_PORT_DDI_LANES_TC6,
61
62 POWER_DOMAIN_PORT_DDI_IO_A,
63 POWER_DOMAIN_PORT_DDI_IO_B,
64 POWER_DOMAIN_PORT_DDI_IO_C,
65 POWER_DOMAIN_PORT_DDI_IO_D,
66 POWER_DOMAIN_PORT_DDI_IO_E,
67 POWER_DOMAIN_PORT_DDI_IO_F,
68
69 POWER_DOMAIN_PORT_DDI_IO_TC1,
70 POWER_DOMAIN_PORT_DDI_IO_TC2,
71 POWER_DOMAIN_PORT_DDI_IO_TC3,
72 POWER_DOMAIN_PORT_DDI_IO_TC4,
73 POWER_DOMAIN_PORT_DDI_IO_TC5,
74 POWER_DOMAIN_PORT_DDI_IO_TC6,
75
76 POWER_DOMAIN_PORT_DSI,
77 POWER_DOMAIN_PORT_CRT,
78 POWER_DOMAIN_PORT_OTHER,
79 POWER_DOMAIN_VGA,
80 POWER_DOMAIN_AUDIO_MMIO,
81 POWER_DOMAIN_AUDIO_PLAYBACK,
82
83 POWER_DOMAIN_AUX_IO_A,
84 POWER_DOMAIN_AUX_IO_B,
85 POWER_DOMAIN_AUX_IO_C,
86 POWER_DOMAIN_AUX_IO_D,
87 POWER_DOMAIN_AUX_IO_E,
88 POWER_DOMAIN_AUX_IO_F,
89
90 POWER_DOMAIN_AUX_A,
91 POWER_DOMAIN_AUX_B,
92 POWER_DOMAIN_AUX_C,
93 POWER_DOMAIN_AUX_D,
94 POWER_DOMAIN_AUX_E,
95 POWER_DOMAIN_AUX_F,
96
97 POWER_DOMAIN_AUX_USBC1,
98 POWER_DOMAIN_AUX_USBC2,
99 POWER_DOMAIN_AUX_USBC3,
100 POWER_DOMAIN_AUX_USBC4,
101 POWER_DOMAIN_AUX_USBC5,
102 POWER_DOMAIN_AUX_USBC6,
103
104 POWER_DOMAIN_AUX_TBT1,
105 POWER_DOMAIN_AUX_TBT2,
106 POWER_DOMAIN_AUX_TBT3,
107 POWER_DOMAIN_AUX_TBT4,
108 POWER_DOMAIN_AUX_TBT5,
109 POWER_DOMAIN_AUX_TBT6,
110
111 POWER_DOMAIN_GMBUS,
112 POWER_DOMAIN_GT_IRQ,
113 POWER_DOMAIN_DC_OFF,
114 POWER_DOMAIN_TC_COLD_OFF,
115 POWER_DOMAIN_INIT,
116
117 POWER_DOMAIN_NUM,
118 POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM,
119 };
120
121 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
122 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
123 ((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A)
124 #define POWER_DOMAIN_TRANSCODER(tran) \
125 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
126 (tran) + POWER_DOMAIN_TRANSCODER_A)
127
128 struct intel_power_domain_mask {
129 DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
130 };
131
132 struct i915_power_domains {
133 /*
134 * Power wells needed for initialization at driver init and suspend
135 * time are on. They are kept on until after the first modeset.
136 */
137 bool initializing;
138 bool display_core_suspended;
139 int power_well_count;
140
141 u32 dc_state;
142 u32 target_dc_state;
143 u32 allowed_dc_mask;
144
145 intel_wakeref_t init_wakeref;
146 intel_wakeref_t disable_wakeref;
147
148 struct mutex lock;
149 int domain_use_count[POWER_DOMAIN_NUM];
150
151 struct delayed_work async_put_work;
152 intel_wakeref_t async_put_wakeref;
153 struct intel_power_domain_mask async_put_domains[2];
154 int async_put_next_delay;
155
156 struct i915_power_well *power_wells;
157 };
158
159 struct intel_display_power_domain_set {
160 struct intel_power_domain_mask mask;
161 #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
162 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
163 #endif
164 };
165
166 #define for_each_power_domain(__domain, __mask) \
167 for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \
168 for_each_if(test_bit((__domain), (__mask)->bits))
169
170 int intel_power_domains_init(struct intel_display *display);
171 void intel_power_domains_cleanup(struct intel_display *display);
172 void intel_power_domains_init_hw(struct intel_display *display, bool resume);
173 void intel_power_domains_driver_remove(struct intel_display *display);
174 void intel_power_domains_enable(struct intel_display *display);
175 void intel_power_domains_disable(struct intel_display *display);
176 void intel_power_domains_suspend(struct intel_display *display, bool s2idle);
177 void intel_power_domains_resume(struct intel_display *display);
178 void intel_power_domains_sanitize_state(struct intel_display *display);
179
180 void intel_display_power_suspend_late(struct intel_display *display, bool s2idle);
181 void intel_display_power_resume_early(struct intel_display *display);
182 void intel_display_power_suspend(struct intel_display *display);
183 void intel_display_power_resume(struct intel_display *display);
184 void intel_display_power_set_target_dc_state(struct intel_display *display,
185 u32 state);
186
187 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
188 enum intel_display_power_domain domain);
189 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
190 enum intel_display_power_domain domain);
191 intel_wakeref_t
192 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
193 enum intel_display_power_domain domain);
194 void __intel_display_power_put_async(struct drm_i915_private *i915,
195 enum intel_display_power_domain domain,
196 intel_wakeref_t wakeref,
197 int delay_ms);
198 void intel_display_power_flush_work(struct drm_i915_private *i915);
199 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
200 void intel_display_power_put(struct drm_i915_private *dev_priv,
201 enum intel_display_power_domain domain,
202 intel_wakeref_t wakeref);
203 static inline void
intel_display_power_put_async(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref)204 intel_display_power_put_async(struct drm_i915_private *i915,
205 enum intel_display_power_domain domain,
206 intel_wakeref_t wakeref)
207 {
208 __intel_display_power_put_async(i915, domain, wakeref, -1);
209 }
210
211 static inline void
intel_display_power_put_async_delay(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref,int delay_ms)212 intel_display_power_put_async_delay(struct drm_i915_private *i915,
213 enum intel_display_power_domain domain,
214 intel_wakeref_t wakeref,
215 int delay_ms)
216 {
217 __intel_display_power_put_async(i915, domain, wakeref, delay_ms);
218 }
219 #else
220 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
221 enum intel_display_power_domain domain);
222
223 static inline void
intel_display_power_put(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref)224 intel_display_power_put(struct drm_i915_private *i915,
225 enum intel_display_power_domain domain,
226 intel_wakeref_t wakeref)
227 {
228 intel_display_power_put_unchecked(i915, domain);
229 }
230
231 static inline void
intel_display_power_put_async(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref)232 intel_display_power_put_async(struct drm_i915_private *i915,
233 enum intel_display_power_domain domain,
234 intel_wakeref_t wakeref)
235 {
236 __intel_display_power_put_async(i915, domain, INTEL_WAKEREF_DEF, -1);
237 }
238
239 static inline void
intel_display_power_put_async_delay(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref,int delay_ms)240 intel_display_power_put_async_delay(struct drm_i915_private *i915,
241 enum intel_display_power_domain domain,
242 intel_wakeref_t wakeref,
243 int delay_ms)
244 {
245 __intel_display_power_put_async(i915, domain, INTEL_WAKEREF_DEF, delay_ms);
246 }
247 #endif
248
249 void
250 intel_display_power_get_in_set(struct drm_i915_private *i915,
251 struct intel_display_power_domain_set *power_domain_set,
252 enum intel_display_power_domain domain);
253
254 bool
255 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
256 struct intel_display_power_domain_set *power_domain_set,
257 enum intel_display_power_domain domain);
258
259 void
260 intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
261 struct intel_display_power_domain_set *power_domain_set,
262 struct intel_power_domain_mask *mask);
263
264 static inline void
intel_display_power_put_all_in_set(struct drm_i915_private * i915,struct intel_display_power_domain_set * power_domain_set)265 intel_display_power_put_all_in_set(struct drm_i915_private *i915,
266 struct intel_display_power_domain_set *power_domain_set)
267 {
268 intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
269 }
270
271 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
272
273 enum intel_display_power_domain
274 intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port);
275 enum intel_display_power_domain
276 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
277 enum intel_display_power_domain
278 intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
279 enum intel_display_power_domain
280 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
281 enum intel_display_power_domain
282 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
283
284 /*
285 * FIXME: We should probably switch this to a 0-based scheme to be consistent
286 * with how we now name/number DBUF_CTL instances.
287 */
288 enum dbuf_slice {
289 DBUF_S1,
290 DBUF_S2,
291 DBUF_S3,
292 DBUF_S4,
293 I915_MAX_DBUF_SLICES
294 };
295
296 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
297 u8 req_slices);
298
299 #define with_intel_display_power(i915, domain, wf) \
300 for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
301 intel_display_power_put_async((i915), (domain), (wf)), (wf) = NULL)
302
303 #define with_intel_display_power_if_enabled(i915, domain, wf) \
304 for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \
305 intel_display_power_put_async((i915), (domain), (wf)), (wf) = NULL)
306
307 #endif /* __INTEL_DISPLAY_POWER_H__ */
308