1 /******************************************************************************
2
3 � 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
4 All rights reserved.
5
6 This is proprietary source code of Freescale Semiconductor Inc.,
7 and its use is subject to the NetComm Device Drivers EULA.
8 The copyright notice above does not evidence any actual or intended
9 publication of such source code.
10
11 ALTERNATIVELY, redistribution and use in source and binary forms, with
12 or without modification, are permitted provided that the following
13 conditions are met:
14 * Redistributions of source code must retain the above copyright
15 notice, this list of conditions and the following disclaimer.
16 * Redistributions in binary form must reproduce the above copyright
17 notice, this list of conditions and the following disclaimer in the
18 documentation and/or other materials provided with the distribution.
19 * Neither the name of Freescale Semiconductor nor the
20 names of its contributors may be used to endorse or promote products
21 derived from this software without specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34
35 **************************************************************************/
36 /******************************************************************************
37 @File qm.h
38
39 @Description QM header
40 *//***************************************************************************/
41 #ifndef __QM_H
42 #define __QM_H
43
44 #include "std_ext.h"
45 #include "list_ext.h"
46 #include "qm_ext.h"
47 #include "qman_private.h"
48 #include "qm_ipc.h"
49
50
51 #define __ERR_MODULE__ MODULE_QM
52
53 #define QM_NUM_OF_SWP 10
54 #define QM_NUM_OF_DCP 5
55
56 #define CACHELINE_SIZE 64
57 #define QM_CONTEXTA_MAX_STASH_SIZE (3 * CACHELINE_SIZE)
58
59 /**************************************************************************//**
60 @Description Exceptions
61 *//***************************************************************************/
62 #define QM_EX_CORENET_INITIATOR_DATA 0x20000000
63 #define QM_EX_CORENET_TARGET_DATA 0x10000000
64 #define QM_EX_CORENET_INVALID_TARGET_TRANSACTION 0x08000000
65 #define QM_EX_PFDR_THRESHOLD 0x04000000
66 #define QM_EX_MULTI_ECC 0x02000000
67 #define QM_EX_SINGLE_ECC 0x01000000
68 #define QM_EX_PFDR_ENQUEUE_BLOCKED 0x00800000
69 #define QM_EX_INVALID_COMMAND 0x00010000
70 #define QM_EX_DEQUEUE_DCP 0x00000800
71 #define QM_EX_DEQUEUE_FQ 0x00000400
72 #define QM_EX_DEQUEUE_SOURCE 0x00000200
73 #define QM_EX_DEQUEUE_QUEUE 0x00000100
74 #define QM_EX_ENQUEUE_OVERFLOW 0x00000008
75 #define QM_EX_ENQUEUE_STATE 0x00000004
76 #define QM_EX_ENQUEUE_CHANNEL 0x00000002
77 #define QM_EX_ENQUEUE_QUEUE 0x00000001
78
79 #define GET_EXCEPTION_FLAG(bitMask, exception) switch(exception){ \
80 case e_QM_EX_CORENET_INITIATOR_DATA: \
81 bitMask = QM_EX_CORENET_INITIATOR_DATA; break; \
82 case e_QM_EX_CORENET_TARGET_DATA: \
83 bitMask = QM_EX_CORENET_TARGET_DATA; break; \
84 case e_QM_EX_CORENET_INVALID_TARGET_TRANSACTION: \
85 bitMask = QM_EX_CORENET_INVALID_TARGET_TRANSACTION; break; \
86 case e_QM_EX_PFDR_THRESHOLD: \
87 bitMask = QM_EX_PFDR_THRESHOLD; break; \
88 case e_QM_EX_PFDR_ENQUEUE_BLOCKED: \
89 bitMask = QM_EX_PFDR_ENQUEUE_BLOCKED; break; \
90 case e_QM_EX_SINGLE_ECC: \
91 bitMask = QM_EX_SINGLE_ECC; break; \
92 case e_QM_EX_MULTI_ECC: \
93 bitMask = QM_EX_MULTI_ECC; break; \
94 case e_QM_EX_INVALID_COMMAND: \
95 bitMask = QM_EX_INVALID_COMMAND; break; \
96 case e_QM_EX_DEQUEUE_DCP: \
97 bitMask = QM_EX_DEQUEUE_DCP; break; \
98 case e_QM_EX_DEQUEUE_FQ: \
99 bitMask = QM_EX_DEQUEUE_FQ; break; \
100 case e_QM_EX_DEQUEUE_SOURCE: \
101 bitMask = QM_EX_DEQUEUE_SOURCE; break; \
102 case e_QM_EX_DEQUEUE_QUEUE: \
103 bitMask = QM_EX_DEQUEUE_QUEUE; break; \
104 case e_QM_EX_ENQUEUE_OVERFLOW: \
105 bitMask = QM_EX_ENQUEUE_OVERFLOW; break; \
106 case e_QM_EX_ENQUEUE_STATE: \
107 bitMask = QM_EX_ENQUEUE_STATE; break; \
108 case e_QM_EX_ENQUEUE_CHANNEL: \
109 bitMask = QM_EX_ENQUEUE_CHANNEL; break; \
110 case e_QM_EX_ENQUEUE_QUEUE: \
111 bitMask = QM_EX_ENQUEUE_QUEUE; break; \
112 default: bitMask = 0;break;}
113
114 /**************************************************************************//**
115 @Description defaults
116 *//***************************************************************************/
117 /* QM defaults */
118 #define DEFAULT_exceptions ((uint32_t)(QM_EX_CORENET_INITIATOR_DATA | \
119 QM_EX_CORENET_TARGET_DATA | \
120 QM_EX_CORENET_INVALID_TARGET_TRANSACTION | \
121 QM_EX_PFDR_THRESHOLD | \
122 QM_EX_SINGLE_ECC | \
123 QM_EX_MULTI_ECC | \
124 QM_EX_PFDR_ENQUEUE_BLOCKED | \
125 QM_EX_INVALID_COMMAND | \
126 QM_EX_DEQUEUE_DCP | \
127 QM_EX_DEQUEUE_FQ | \
128 QM_EX_DEQUEUE_SOURCE | \
129 QM_EX_DEQUEUE_QUEUE | \
130 QM_EX_ENQUEUE_OVERFLOW | \
131 QM_EX_ENQUEUE_STATE | \
132 QM_EX_ENQUEUE_CHANNEL | \
133 QM_EX_ENQUEUE_QUEUE ))
134 #define DEFAULT_rtFramesDepth 30000
135 #define DEFAULT_pfdrThreshold 0
136 #define DEFAULT_sfdrThreshold 0
137 #define DEFAULT_pfdrBaseConstant 64
138 /* Corenet initiator settings. Stash request queues are 4-deep to match cores'
139 ability to snart. Stash priority is 3, other priorities are 2. */
140 #define DEFAULT_initiatorSrcciv 0
141 #define DEFAULT_initiatorSrqW 3
142 #define DEFAULT_initiatorRwW 2
143 #define DEFAULT_initiatorBmanW 2
144
145
146 /* QM-Portal defaults */
147 #define DEFAULT_dequeueDcaMode FALSE
148 #define DEFAULT_dequeueUpToThreeFrames TRUE
149 #define DEFAULT_dequeueCommandType e_QM_PORTAL_PRIORITY_PRECEDENCE_INTRA_CLASS_SCHEDULING
150 #define DEFAULT_dequeueUserToken 0xab
151 #define DEFAULT_dequeueSpecifiedWq FALSE
152 #define DEFAULT_dequeueDedicatedChannel TRUE
153 #define DEFAULT_dequeuePoolChannelId 0
154 #define DEFAULT_dequeueWqId 0
155 #define DEFAULT_dequeueDedicatedChannelHasPrecedenceOverPoolChannels TRUE
156 #define DEFAULT_dqrrSize DQRR_MAXFILL
157 #define DEFAULT_pullMode FALSE
158 #define DEFAULT_portalExceptions ((uint32_t)(QM_PIRQ_EQCI | \
159 QM_PIRQ_EQRI | \
160 QM_PIRQ_DQRI | \
161 QM_PIRQ_MRI | \
162 QM_PIRQ_CSCI))
163
164 /**************************************************************************//**
165 @Description Memory Mapped Registers
166 *//***************************************************************************/
167
168 #if defined(__MWERKS__) && !defined(__GNUC__)
169 #pragma pack(push,1)
170 #endif /* defined(__MWERKS__) && ... */
171 #define MEM_MAP_START
172
173 typedef _Packed struct
174 {
175 /* QMan Software Portal Configuration Registers */
176 _Packed struct {
177 volatile uint32_t lio_cfg; /**< QMan Software Portal LIO Configuration */
178 volatile uint32_t io_cfg; /**< QMan Software Portal 0 IO Configuration */
179 volatile uint8_t res1[4]; /**< reserved */
180 volatile uint32_t dd_cfg; /**< Software Portal Dynamic Debug Configuration */
181 } _PackedType swpConfRegs[QM_NUM_OF_SWP];
182 volatile uint8_t res1[352]; /**< reserved */
183
184 /* Dynamic Debug (DD) Configuration Registers */
185 volatile uint32_t qman_dd_cfg; /**< QMan Dynamic Debug (DD) Configuration */
186 volatile uint8_t res2[12]; /**< reserved */
187 volatile uint32_t qcsp_dd_ihrsr; /**< Software Portal DD Internal Halt Request Status */
188 volatile uint32_t qcsp_dd_ihrfr; /**< Software Portal DD Internal Halt Request Force */
189 volatile uint32_t qcsp_dd_hasr; /**< Software Portal DD Halt Acknowledge Status */
190 volatile uint8_t res3[4]; /**< reserved */
191 volatile uint32_t dcp_dd_ihrsr; /**< DCP DD Internal Halt Request Status */
192 volatile uint32_t dcp_dd_ihrfr; /**< DCP DD Internal Halt Request Force */
193 volatile uint32_t dcp_dd_hasr; /**< DCP DD Halt Acknowledge Status */
194 volatile uint8_t res4[212]; /**< reserved */
195
196 /* Direct Connect Portal (DCP) Configuration Registers */
197 _Packed struct {
198 volatile uint32_t cfg; /**< DCP Configuration */
199 volatile uint32_t dd_cfg; /**< DCP Dynamic Debug Configuration */
200 volatile uint32_t dlm_cfg; /**< DCP Dequeue Latency Monitor Configuration */
201 volatile uint32_t dlm_avg; /**< DCP Dequeue Latency Monitor Average */
202 } _PackedType dcpConfRegs[QM_NUM_OF_DCP];
203 volatile uint8_t res5[176]; /**< reserved */
204
205 /* Packed Frame Descriptor Record (PFDR) Manager Query Registers */
206 volatile uint32_t pfdr_fpc; /**< PFDR Free Pool Count */
207 volatile uint32_t pfdr_fp_head; /**< PFDR Free Pool Head Pointer */
208 volatile uint32_t pfdr_fp_tail; /**< PFDR Free Pool Tail Pointer */
209 volatile uint8_t res6[4]; /**< reserved */
210 volatile uint32_t pfdr_fp_lwit; /**< PFDR Free Pool Low Watermark Interrupt Threshold */
211 volatile uint32_t pfdr_cfg; /**< PFDR Configuration */
212 volatile uint8_t res7[232]; /**< reserved */
213
214 /* Single Frame Descriptor Record (SFDR) Manager Registers */
215 volatile uint32_t sfdr_cfg; /**< SFDR Configuration */
216 volatile uint32_t sfdr_in_use; /**< SFDR In Use Register */
217 volatile uint8_t res8[248]; /**< reserved */
218
219 /* Work Queue Semaphore and Context Manager Registers */
220 volatile uint32_t wq_cs_cfg[6]; /**< Work Queue Class Scheduler Configuration */
221 volatile uint8_t res9[24]; /**< reserved */
222 volatile uint32_t wq_def_enq_wqid; /**< Work Queue Default Enqueue WQID */
223 volatile uint8_t res10[12]; /**< reserved */
224 volatile uint32_t wq_sc_dd_cfg[5]; /**< WQ S/W Channel Dynamic Debug Config */
225 volatile uint8_t res11[44]; /**< reserved */
226 volatile uint32_t wq_pc_dd_cs_cfg[8]; /**< WQ Pool Channel Dynamic Debug Config */
227 volatile uint8_t res12[32]; /**< reserved */
228 volatile uint32_t wq_dc0_dd_cs_cfg[6]; /**< WQ DCP0 Chan. Dynamic Debug Config */
229 volatile uint8_t res13[40]; /**< reserved */
230 volatile uint32_t wq_dc1_dd_cs_cfg[6]; /**< WQ DCP1 Chan. Dynamic Debug Config */
231 volatile uint8_t res14[40]; /**< reserved */
232 volatile uint32_t wq_dc2_dd_cs_cfg; /**< WQ DCP2 Chan. Dynamic Debug Config */
233 volatile uint8_t res15[60]; /**< reserved */
234 volatile uint32_t wq_dc3_dd_cs_cfg; /**< WQ DCP3 Chan. Dynamic Debug Config */
235 volatile uint8_t res16[124]; /**< reserved */
236
237 /* Congestion Manager (CM) Registers */
238 volatile uint32_t cm_cfg; /**< CM Configuration Register */
239 volatile uint8_t res17[508]; /**< reserved */
240
241 /* QMan Error Capture Registers */
242 volatile uint32_t ecsr; /**< QMan Error Capture Status Register */
243 volatile uint32_t ecir; /**< QMan Error Capture Information Register */
244 volatile uint32_t eadr; /**< QMan Error Capture Address Register */
245 volatile uint8_t res18[4]; /**< reserved */
246 volatile uint32_t edata[16]; /**< QMan ECC Error Data Register */
247 volatile uint8_t res19[32]; /**< reserved */
248 volatile uint32_t sbet; /**< QMan Single Bit ECC Error Threshold Register */
249 volatile uint8_t res20[12]; /**< reserved */
250 volatile uint32_t sbec[7]; /**< QMan Single Bit ECC Error Count Register */
251 volatile uint8_t res21[100]; /**< reserved */
252
253 /* QMan Initialization and Debug Control Registers */
254 volatile uint32_t mcr; /**< QMan Management Command/Result Register */
255 volatile uint32_t mcp0; /**< QMan Management Command Parameter 0 Register */
256 volatile uint32_t mcp1; /**< QMan Management Command Parameter 1 Register */
257 volatile uint8_t res22[20]; /**< reserved */
258 volatile uint32_t mr[16]; /**< QMan Management Return Register */
259 volatile uint8_t res23[148]; /**< reserved */
260 volatile uint32_t idle_stat; /**< QMan Idle Status Register */
261
262 /* QMan ID/Revision Registers */
263 volatile uint32_t ip_rev_1; /**< QMan IP Block Revision 1 register */
264 volatile uint32_t ip_rev_2; /**< QMan IP Block Revision 2 register */
265
266 /* QMan Initiator Interface Memory Window Configuration Registers */
267 volatile uint32_t fqd_bare; /**< FQD Extended Base Address Register */
268 volatile uint32_t fqd_bar; /**< Frame Queue Descriptor (FQD) Base Address Register */
269 volatile uint8_t res24[8]; /**< reserved */
270 volatile uint32_t fqd_ar; /**< FQD Attributes Register */
271 volatile uint8_t res25[12]; /**< reserved */
272 volatile uint32_t pfdr_bare; /**< PFDR Extended Base Address Register */
273 volatile uint32_t pfdr_bar; /**< Packed Frame Descriptor Record (PFDR) Base Addr */
274 volatile uint8_t res26[8]; /**< reserved */
275 volatile uint32_t pfdr_ar; /**< PFDR Attributes Register */
276 volatile uint8_t res27[76]; /**< reserved */
277 volatile uint32_t qcsp_bare; /**< QCSP Extended Base Address */
278 volatile uint32_t qcsp_bar; /**< QMan Software Portal Base Address */
279 volatile uint8_t res28[120]; /**< reserved */
280 volatile uint32_t ci_sched_cfg; /**< Initiator Scheduling Configuration */
281 volatile uint32_t srcidr; /**< QMan Source ID Register */
282 volatile uint32_t liodnr; /**< QMan Logical I/O Device Number Register */
283 volatile uint8_t res29[4]; /**< reserved */
284 volatile uint32_t ci_rlm_cfg; /**< Initiator Read Latency Monitor Configuration */
285 volatile uint32_t ci_rlm_avg; /**< Initiator Read Latency Monitor Average */
286 volatile uint8_t res30[232]; /**< reserved */
287
288 /* QMan Interrupt and Error Registers */
289 volatile uint32_t err_isr; /**< QMan Error Interrupt Status Register */
290 volatile uint32_t err_ier; /**< QMan Error Interrupt Enable Register */
291 volatile uint32_t err_isdr; /**< QMan Error Interrupt Status Disable Register */
292 volatile uint32_t err_iir; /**< QMan Error Interrupt Inhibit Register */
293 volatile uint8_t res31[4]; /**< reserved */
294 volatile uint32_t err_her; /**< QMan Error Halt Enable Register */
295
296 } _PackedType t_QmRegs;
297
298 #define MEM_MAP_END
299 #if defined(__MWERKS__) && !defined(__GNUC__)
300 #pragma pack(pop)
301 #endif /* defined(__MWERKS__) && ... */
302
303
304 /**************************************************************************//**
305 @Description General defines
306 *//***************************************************************************/
307
308 #define MODULE_NAME_SIZE 30
309
310 #define PORTALS_OFFSET_CE(portal) (0x4000 * portal)
311 #define PORTALS_OFFSET_CI(portal) (0x1000 * portal)
312
313 #define PFDR_ENTRY_SIZE 64 /* 64 bytes */
314 #define FQD_ENTRY_SIZE 64 /* 64 bytes */
315
316 /* Compilation constants */
317 #define DQRR_MAXFILL 15
318 #define EQCR_THRESH 1 /* reread h/w CI when running out of space */
319
320 /**************************************************************************//**
321 @Description Register defines
322 *//***************************************************************************/
323
324 /* Assists for QMAN_MCR */
325 #define MCR_INIT_PFDR 0x01000000
326 #define MCR_get_rslt(v) (uint8_t)((v) >> 24)
327 #define MCR_rslt_idle(r) (!rslt || (rslt >= 0xf0))
328 #define MCR_rslt_ok(r) (rslt == 0xf0)
329 #define MCR_rslt_eaccess(r) (rslt == 0xf8)
330 #define MCR_rslt_inval(r) (rslt == 0xff)
331
332 /* masks */
333 #define REV1_MAJOR_MASK 0x0000FF00
334 #define REV1_MINOR_MASK 0x000000FF
335
336 #define REV2_INTEG_MASK 0x00FF0000
337 #define REV2_ERR_MASK 0x0000FF00
338 #define REV2_CFG_MASK 0x000000FF
339
340 #define AR_ENABLE 0x80000000
341 #define AR_PRIORITY 0x40000000
342 #define AR_STASH 0x20000000
343 #define AR_SIZE_MASK 0x0000003f
344
345 #define ECIR_PORTAL_TYPE 0x20000000
346 #define ECIR_PORTAL_MASK 0x1f000000
347 #define ECIR_FQID_MASK 0x00ffffff
348
349 #define CI_SCHED_CFG_EN 0x80000000
350 /* shifts */
351 #define REV1_MAJOR_SHIFT 8
352 #define REV1_MINOR_SHIFT 0
353
354 #define REV2_INTEG_SHIFT 16
355 #define REV2_ERR_SHIFT 8
356 #define REV2_CFG_SHIFT 0
357
358 #define AR_SIZE_SHIFT 0
359
360 #define ECIR_PORTAL_SHIFT 24
361 #define ECIR_FQID_SHIFT 0
362
363 #define CI_SCHED_CFG_SRCCIV_SHIFT 24
364 #define CI_SCHED_CFG_SRQ_W_SHIFT 8
365 #define CI_SCHED_CFG_RW_W_SHIFT 4
366 #define CI_SCHED_CFG_BMAN_W_SHIFT 0
367
368
369 /********* CGR ******************************/
370 #define QM_CGR_TARG_FIRST_SWPORTAL 0x80000000
371 #define QM_CGR_TARG_FIRST_DCPORTAL 0x00200000
372 #define QM_CGR_TARGET_SWP(portlaId) (QM_CGR_TARG_FIRST_SWPORTAL >> portlaId)
373 #define QM_CGR_TARGET_DCP(portlaId) (QM_CGR_TARG_FIRST_DCPORTAL >> portlaId)
374
375
376 #define QM_DCP_CFG_ED 0x00000100
377 /*
378 #define CGR_VALID 0x80
379 #define CGR_VERB_INIT 0x50
380 #define CGR_VERB_MODIFY 0x51
381 #define CGR_WRITE_ALL 0x07FF
382 #define CGR_WRITE_ENABLE_CSCN 0x0010
383 #define CGR_WRITE_ENABLE_GREEN_MODIFY 0x0380
384 #define CGR_WRITE_ENABLE_YELLOW_MODIFY 0x0240
385 #define CGR_WRITE_ENABLE_RED_MODIFY 0x0120
386
387
388 #define CGR_MODE_BYTE 0x00
389 #define CGR_MODE_FRAME 0x01
390 #define GCR_ENABLE_WRED 0x01
391 #define GCR_ENABLE_TD 0x01
392 #define GCR_ENABLE_CSCN 0x01
393 */
394
395
396 /* Lock/unlock frame queues, subject to the "UNLOCKED" flag. This is about
397 * inter-processor locking only. */
398 #define FQLOCK(fq) \
399 do { \
400 if (fq->flags & QMAN_FQ_FLAG_LOCKED) \
401 XX_LockSpinlock(&fq->fqlock); \
402 } while(0)
403 #define FQUNLOCK(fq) \
404 do { \
405 if (fq->flags & QMAN_FQ_FLAG_LOCKED) \
406 XX_UnlockSpinlock(&fq->fqlock); \
407 } while(0)
408
409 /* Lock/unlock portals, subject to "UNLOCKED" flag. This is about disabling
410 * interrupts/preemption and, if FLAG_UNLOCKED isn't defined, inter-processor
411 * locking as well. */
412 #define NCSW_PLOCK(p) ((t_QmPortal*)(p))->irq_flags = XX_DisableAllIntr()
413 #define PUNLOCK(p) XX_RestoreAllIntr(((t_QmPortal*)(p))->irq_flags)
414
415
416 typedef void (t_QmLoopDequeueRing)(t_Handle h_QmPortal);
417
418 /* Follows WQ_CS_CFG0-5 */
419 typedef enum {
420 e_QM_WQ_SW_PORTALS = 0,
421 e_QM_WQ_POOLS,
422 e_QM_WQ_DCP0,
423 e_QM_WQ_DCP1,
424 e_QM_WQ_DCP2,
425 e_QM_WQ_DCP3
426 } e_QmWqClass;
427
428 typedef enum {
429 e_QM_PORTAL_NO_DEQUEUES = 0,
430 e_QM_PORTAL_PRIORITY_PRECEDENCE_INTRA_CLASS_SCHEDULING,
431 e_QM_PORTAL_ACTIVE_FQ_PRECEDENCE_INTRA_CLASS_SCHEDULING,
432 e_QM_PORTAL_ACTIVE_FQ_PRECEDENCE_OVERRIDE_INTRA_CLASS_SCHEDULING
433 } e_QmPortalDequeueCommandType;
434
435 typedef enum e_QmInterModuleCounters {
436 e_QM_IM_COUNTERS_SFDR_IN_USE = 0,
437 e_QM_IM_COUNTERS_PFDR_IN_USE,
438 e_QM_IM_COUNTERS_PFDR_FREE_POOL
439 } e_QmInterModuleCounters;
440
441 typedef struct t_QmInterModulePortalInitParams {
442 uint8_t portalId;
443 uint8_t stashDestQueue;
444 uint16_t liodn;
445 uint16_t dqrrLiodn;
446 uint16_t fdFqLiodn;
447 } t_QmInterModulePortalInitParams;
448
449 typedef struct t_QmCg {
450 t_Handle h_Qm;
451 t_Handle h_QmPortal;
452 t_QmExceptionsCallback *f_Exception;
453 t_Handle h_App;
454 uint8_t id;
455 } t_QmCg;
456
457 typedef struct {
458 uintptr_t swPortalsBaseAddress; /**< QM Software Portals Base Address (virtual) */
459 uint32_t partFqidBase;
460 uint32_t partNumOfFqids;
461 uint32_t totalNumOfFqids;
462 uint32_t rtFramesDepth;
463 uint32_t fqdMemPartitionId;
464 uint32_t pfdrMemPartitionId;
465 uint32_t pfdrThreshold;
466 uint32_t sfdrThreshold;
467 uint32_t pfdrBaseConstant;
468 uint16_t liodn;
469 t_QmDcPortalParams dcPortalsParams[DPAA_MAX_NUM_OF_DC_PORTALS];
470 } t_QmDriverParams;
471
472 typedef struct {
473 uint8_t guestId;
474 t_Handle h_RsrvFqidMm;
475 t_Handle h_FqidMm;
476 t_Handle h_Session;
477 char moduleName[MODULE_NAME_SIZE];
478 t_Handle h_Portals[DPAA_MAX_NUM_OF_SW_PORTALS];
479 t_QmRegs *p_QmRegs;
480 uint32_t *p_FqdBase;
481 uint32_t *p_PfdrBase;
482 uint32_t exceptions;
483 t_QmExceptionsCallback *f_Exception;
484 t_Handle h_App;
485 uintptr_t errIrq; /**< error interrupt line; NO_IRQ if interrupts not used */
486 uint32_t numOfPfdr;
487 uint16_t partNumOfCgs;
488 uint16_t partCgsBase;
489 uint8_t cgsUsed[QM_MAX_NUM_OF_CGS];
490 t_Handle lock;
491 t_QmDriverParams *p_QmDriverParams;
492 } t_Qm;
493
494 typedef struct {
495 uint32_t hwExtStructsMemAttr;
496 uint8_t dqrrSize;
497 bool pullMode;
498 bool dequeueDcaMode;
499 bool dequeueUpToThreeFrames;
500 e_QmPortalDequeueCommandType commandType;
501 uint8_t userToken;
502 bool specifiedWq;
503 bool dedicatedChannel;
504 bool dedicatedChannelHasPrecedenceOverPoolChannels;
505 uint8_t poolChannels[QM_MAX_NUM_OF_POOL_CHANNELS];
506 uint8_t poolChannelId;
507 uint8_t wqId;
508 uint16_t fdLiodnOffset;
509 uint8_t stashDestQueue;
510 uint8_t eqcr;
511 bool eqcrHighPri;
512 bool dqrr;
513 uint16_t dqrrLiodn;
514 bool dqrrHighPri;
515 bool fdFq;
516 uint16_t fdFqLiodn;
517 bool fdFqHighPri;
518 bool fdFqDrop;
519 } t_QmPortalDriverParams;
520
521 /*typedef struct t_QmPortalCgs{
522 uint32_t cgsMask[QM_MAX_NUM_OF_CGS/32];
523 }t_QmPortalCgs;
524 */
525 typedef struct t_QmPortal {
526 t_Handle h_Qm;
527 struct qm_portal *p_LowQmPortal;
528 uint32_t bits; /* PORTAL_BITS_*** - dynamic, strictly internal */
529 t_Handle h_App;
530 t_QmLoopDequeueRing *f_LoopDequeueRingCB;
531 bool pullMode;
532 /* To avoid overloading the term "flags", we use these 2; */
533 uint32_t options; /* QMAN_PORTAL_FLAG_*** - static, caller-provided */
534 uint32_t irq_flags;
535 /* The wrap-around eq_[prod|cons] counters are used to support
536 * QMAN_ENQUEUE_FLAG_WAIT_SYNC. */
537 uint32_t eqProd;
538 volatile int disable_count;
539 struct qman_cgrs cgrs[2]; /* 2-element array. cgrs[0] is mask, cgrs[1] is previous snapshot. */
540 /* If we receive a DQRR or MR ring entry for a "null" FQ, ie. for which
541 * FQD::contextB is NULL rather than pointing to a FQ object, we use
542 * these handlers. (This is not considered a fast-path mechanism.) */
543 t_Handle cgsHandles[QM_MAX_NUM_OF_CGS];
544 struct qman_fq_cb *p_NullCB;
545 t_QmReceivedFrameCallback *f_DfltFrame;
546 t_QmRejectedFrameCallback *f_RejectedFrame;
547 t_QmPortalDriverParams *p_QmPortalDriverParams;
548 } t_QmPortal;
549
550 struct qman_fq {
551 struct qman_fq_cb cb;
552 t_Handle h_App;
553 t_Handle h_QmFqr;
554 t_Handle fqlock;
555 uint32_t fqid;
556 uint32_t fqidOffset;
557 uint32_t flags;
558 /* s/w-visible states. Ie. tentatively scheduled + truly scheduled +
559 * active + held-active + held-suspended are just "sched". Things like
560 * 'retired' will not be assumed until it is complete (ie.
561 * QMAN_FQ_STATE_CHANGING is set until then, to indicate it's completing
562 * and to gate attempts to retry the retire command). Note, park
563 * commands do not set QMAN_FQ_STATE_CHANGING because it's technically
564 * impossible in the case of enqueue DCAs (which refer to DQRR ring
565 * index rather than the FQ that ring entry corresponds to), so repeated
566 * park commands are allowed (if you're silly enough to try) but won't
567 * change FQ state, and the resulting park notifications move FQs from
568 * 'sched' to 'parked'. */
569 enum qman_fq_state state;
570 int cgr_groupid;
571 };
572
573 typedef struct {
574 t_Handle h_Qm;
575 t_Handle h_QmPortal;
576 e_QmFQChannel channel;
577 uint8_t workQueue;
578 bool shadowMode;
579 uint32_t fqidBase;
580 uint32_t numOfFqids;
581 t_QmFqrDrainedCompletionCB *f_CompletionCB;
582 t_Handle h_App;
583 uint32_t numOfDrainedFqids;
584 bool *p_DrainedFqs;
585 struct qman_fq **p_Fqs;
586 } t_QmFqr;
587
588
589 /****************************************/
590 /* Inter-Module functions */
591 /****************************************/
592 uint32_t QmGetCounter(t_Handle h_Qm, e_QmInterModuleCounters counter);
593 t_Error QmGetRevision(t_Handle h_Qm, t_QmRevisionInfo *p_QmRevisionInfo);
594 t_Error QmGetSetPortalParams(t_Handle h_Qm, t_QmInterModulePortalInitParams *p_PortalParams);
595 t_Error QmFreeDcPortal(t_Handle h_Qm, e_DpaaDcPortal dcPortalId);
596 uint32_t QmFqidGet(t_Qm *p_Qm, uint32_t size, uint32_t alignment, bool force, uint32_t base);
597 t_Error QmFqidPut(t_Qm *p_Qm, uint32_t base);
598 t_Error QmGetCgId(t_Handle h_Qm, uint8_t *p_CgId);
599 t_Error QmFreeCgId(t_Handle h_Qm, uint8_t cgId);
600
601
QmSetPortalHandle(t_Handle h_Qm,t_Handle h_Portal,e_DpaaSwPortal portalId)602 static __inline__ void QmSetPortalHandle(t_Handle h_Qm, t_Handle h_Portal, e_DpaaSwPortal portalId)
603 {
604 ASSERT_COND(!((t_Qm*)h_Qm)->h_Portals[portalId] || !h_Portal);
605 ((t_Qm*)h_Qm)->h_Portals[portalId] = h_Portal;
606 }
607
QmGetPortalHandle(t_Handle h_Qm)608 static __inline__ t_Handle QmGetPortalHandle(t_Handle h_Qm)
609 {
610 t_Qm *p_Qm = (t_Qm*)h_Qm;
611
612 ASSERT_COND(p_Qm);
613 return p_Qm->h_Portals[CORE_GetId()];
614 }
615
GenerateCgrThresh(uint64_t val,int roundup)616 static __inline__ uint32_t GenerateCgrThresh(uint64_t val, int roundup)
617 {
618 uint32_t e = 0; /* co-efficient, exponent */
619 uint32_t oddbit = 0;
620 while(val > 0xff) {
621 oddbit = (uint32_t)val & 1;
622 val >>= 1;
623 e++;
624 if(roundup && oddbit)
625 val++;
626 }
627 return (uint32_t)((val << 5) | e);
628 }
629
SetException(t_Qm * p_Qm,e_QmExceptions exception,bool enable)630 static __inline__ t_Error SetException(t_Qm *p_Qm, e_QmExceptions exception, bool enable)
631 {
632 uint32_t bitMask = 0;
633
634 ASSERT_COND(p_Qm);
635
636 GET_EXCEPTION_FLAG(bitMask, exception);
637 if(bitMask)
638 {
639 if (enable)
640 p_Qm->exceptions |= bitMask;
641 else
642 p_Qm->exceptions &= ~bitMask;
643 }
644 else
645 RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
646
647 return E_OK;
648 }
649
650
651 #endif /* __QM_H */
652