1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 */
5
6 #include <linux/string_helpers.h>
7
8 #include "i915_drv.h"
9 #include "i915_reg.h"
10 #include "intel_dram.h"
11 #include "intel_mchbar_regs.h"
12 #include "intel_pcode.h"
13 #include "vlv_sideband.h"
14
15 struct dram_dimm_info {
16 u16 size;
17 u8 width, ranks;
18 };
19
20 struct dram_channel_info {
21 struct dram_dimm_info dimm_l, dimm_s;
22 u8 ranks;
23 bool is_16gb_dimm;
24 };
25
26 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
27
intel_dram_type_str(enum intel_dram_type type)28 static const char *intel_dram_type_str(enum intel_dram_type type)
29 {
30 static const char * const str[] = {
31 DRAM_TYPE_STR(UNKNOWN),
32 DRAM_TYPE_STR(DDR3),
33 DRAM_TYPE_STR(DDR4),
34 DRAM_TYPE_STR(LPDDR3),
35 DRAM_TYPE_STR(LPDDR4),
36 DRAM_TYPE_STR(DDR5),
37 DRAM_TYPE_STR(LPDDR5),
38 DRAM_TYPE_STR(GDDR),
39 DRAM_TYPE_STR(GDDR_ECC),
40 };
41
42 BUILD_BUG_ON(ARRAY_SIZE(str) != __INTEL_DRAM_TYPE_MAX);
43
44 if (type >= ARRAY_SIZE(str))
45 type = INTEL_DRAM_UNKNOWN;
46
47 return str[type];
48 }
49
50 #undef DRAM_TYPE_STR
51
pnv_is_ddr3(struct drm_i915_private * i915)52 static bool pnv_is_ddr3(struct drm_i915_private *i915)
53 {
54 return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3;
55 }
56
pnv_mem_freq(struct drm_i915_private * dev_priv)57 static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv)
58 {
59 u32 tmp;
60
61 tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
62
63 switch (tmp & CLKCFG_MEM_MASK) {
64 case CLKCFG_MEM_533:
65 return 533333;
66 case CLKCFG_MEM_667:
67 return 666667;
68 case CLKCFG_MEM_800:
69 return 800000;
70 }
71
72 return 0;
73 }
74
ilk_mem_freq(struct drm_i915_private * dev_priv)75 static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv)
76 {
77 u16 ddrpll;
78
79 ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
80 switch (ddrpll & 0xff) {
81 case 0xc:
82 return 800000;
83 case 0x10:
84 return 1066667;
85 case 0x14:
86 return 1333333;
87 case 0x18:
88 return 1600000;
89 default:
90 drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
91 ddrpll & 0xff);
92 return 0;
93 }
94 }
95
chv_mem_freq(struct drm_i915_private * i915)96 static unsigned int chv_mem_freq(struct drm_i915_private *i915)
97 {
98 u32 val;
99
100 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
101 val = vlv_cck_read(i915, CCK_FUSE_REG);
102 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
103
104 switch ((val >> 2) & 0x7) {
105 case 3:
106 return 2000000;
107 default:
108 return 1600000;
109 }
110 }
111
vlv_mem_freq(struct drm_i915_private * i915)112 static unsigned int vlv_mem_freq(struct drm_i915_private *i915)
113 {
114 u32 val;
115
116 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
117 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
118 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
119
120 switch ((val >> 6) & 3) {
121 case 0:
122 case 1:
123 return 800000;
124 case 2:
125 return 1066667;
126 case 3:
127 return 1333333;
128 }
129
130 return 0;
131 }
132
detect_mem_freq(struct drm_i915_private * i915)133 static void detect_mem_freq(struct drm_i915_private *i915)
134 {
135 if (IS_PINEVIEW(i915))
136 i915->mem_freq = pnv_mem_freq(i915);
137 else if (GRAPHICS_VER(i915) == 5)
138 i915->mem_freq = ilk_mem_freq(i915);
139 else if (IS_CHERRYVIEW(i915))
140 i915->mem_freq = chv_mem_freq(i915);
141 else if (IS_VALLEYVIEW(i915))
142 i915->mem_freq = vlv_mem_freq(i915);
143
144 if (IS_PINEVIEW(i915))
145 i915->is_ddr3 = pnv_is_ddr3(i915);
146
147 if (i915->mem_freq)
148 drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
149 }
150
i9xx_fsb_freq(struct drm_i915_private * i915)151 unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
152 {
153 u32 fsb;
154
155 /*
156 * Note that this only reads the state of the FSB
157 * straps, not the actual FSB frequency. Some BIOSen
158 * let you configure each independently. Ideally we'd
159 * read out the actual FSB frequency but sadly we
160 * don't know which registers have that information,
161 * and all the relevant docs have gone to bit heaven :(
162 */
163 fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
164
165 if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
166 switch (fsb) {
167 case CLKCFG_FSB_400:
168 return 400000;
169 case CLKCFG_FSB_533:
170 return 533333;
171 case CLKCFG_FSB_667:
172 return 666667;
173 case CLKCFG_FSB_800:
174 return 800000;
175 case CLKCFG_FSB_1067:
176 return 1066667;
177 case CLKCFG_FSB_1333:
178 return 1333333;
179 default:
180 MISSING_CASE(fsb);
181 return 1333333;
182 }
183 } else {
184 switch (fsb) {
185 case CLKCFG_FSB_400_ALT:
186 return 400000;
187 case CLKCFG_FSB_533:
188 return 533333;
189 case CLKCFG_FSB_667:
190 return 666667;
191 case CLKCFG_FSB_800:
192 return 800000;
193 case CLKCFG_FSB_1067_ALT:
194 return 1066667;
195 case CLKCFG_FSB_1333_ALT:
196 return 1333333;
197 case CLKCFG_FSB_1600_ALT:
198 return 1600000;
199 default:
200 MISSING_CASE(fsb);
201 return 1333333;
202 }
203 }
204 }
205
ilk_fsb_freq(struct drm_i915_private * dev_priv)206 static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
207 {
208 u16 fsb;
209
210 fsb = intel_uncore_read16(&dev_priv->uncore, CSIPLL0) & 0x3ff;
211
212 switch (fsb) {
213 case 0x00c:
214 return 3200000;
215 case 0x00e:
216 return 3733333;
217 case 0x010:
218 return 4266667;
219 case 0x012:
220 return 4800000;
221 case 0x014:
222 return 5333333;
223 case 0x016:
224 return 5866667;
225 case 0x018:
226 return 6400000;
227 default:
228 drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb);
229 return 0;
230 }
231 }
232
detect_fsb_freq(struct drm_i915_private * i915)233 static void detect_fsb_freq(struct drm_i915_private *i915)
234 {
235 if (GRAPHICS_VER(i915) == 5)
236 i915->fsb_freq = ilk_fsb_freq(i915);
237 else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
238 i915->fsb_freq = i9xx_fsb_freq(i915);
239
240 if (i915->fsb_freq)
241 drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
242 }
243
intel_dimm_num_devices(const struct dram_dimm_info * dimm)244 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
245 {
246 return dimm->ranks * 64 / (dimm->width ?: 1);
247 }
248
249 /* Returns total Gb for the whole DIMM */
skl_get_dimm_size(u16 val)250 static int skl_get_dimm_size(u16 val)
251 {
252 return (val & SKL_DRAM_SIZE_MASK) * 8;
253 }
254
skl_get_dimm_width(u16 val)255 static int skl_get_dimm_width(u16 val)
256 {
257 if (skl_get_dimm_size(val) == 0)
258 return 0;
259
260 switch (val & SKL_DRAM_WIDTH_MASK) {
261 case SKL_DRAM_WIDTH_X8:
262 case SKL_DRAM_WIDTH_X16:
263 case SKL_DRAM_WIDTH_X32:
264 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
265 return 8 << val;
266 default:
267 MISSING_CASE(val);
268 return 0;
269 }
270 }
271
skl_get_dimm_ranks(u16 val)272 static int skl_get_dimm_ranks(u16 val)
273 {
274 if (skl_get_dimm_size(val) == 0)
275 return 0;
276
277 val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
278
279 return val + 1;
280 }
281
282 /* Returns total Gb for the whole DIMM */
icl_get_dimm_size(u16 val)283 static int icl_get_dimm_size(u16 val)
284 {
285 return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
286 }
287
icl_get_dimm_width(u16 val)288 static int icl_get_dimm_width(u16 val)
289 {
290 if (icl_get_dimm_size(val) == 0)
291 return 0;
292
293 switch (val & ICL_DRAM_WIDTH_MASK) {
294 case ICL_DRAM_WIDTH_X8:
295 case ICL_DRAM_WIDTH_X16:
296 case ICL_DRAM_WIDTH_X32:
297 val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
298 return 8 << val;
299 default:
300 MISSING_CASE(val);
301 return 0;
302 }
303 }
304
icl_get_dimm_ranks(u16 val)305 static int icl_get_dimm_ranks(u16 val)
306 {
307 if (icl_get_dimm_size(val) == 0)
308 return 0;
309
310 val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
311
312 return val + 1;
313 }
314
315 static bool
skl_is_16gb_dimm(const struct dram_dimm_info * dimm)316 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
317 {
318 /* Convert total Gb to Gb per DRAM device */
319 return dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
320 }
321
322 static void
skl_dram_get_dimm_info(struct drm_i915_private * i915,struct dram_dimm_info * dimm,int channel,char dimm_name,u16 val)323 skl_dram_get_dimm_info(struct drm_i915_private *i915,
324 struct dram_dimm_info *dimm,
325 int channel, char dimm_name, u16 val)
326 {
327 if (GRAPHICS_VER(i915) >= 11) {
328 dimm->size = icl_get_dimm_size(val);
329 dimm->width = icl_get_dimm_width(val);
330 dimm->ranks = icl_get_dimm_ranks(val);
331 } else {
332 dimm->size = skl_get_dimm_size(val);
333 dimm->width = skl_get_dimm_width(val);
334 dimm->ranks = skl_get_dimm_ranks(val);
335 }
336
337 drm_dbg_kms(&i915->drm,
338 "CH%u DIMM %c size: %u Gb, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
339 channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
340 str_yes_no(skl_is_16gb_dimm(dimm)));
341 }
342
343 static int
skl_dram_get_channel_info(struct drm_i915_private * i915,struct dram_channel_info * ch,int channel,u32 val)344 skl_dram_get_channel_info(struct drm_i915_private *i915,
345 struct dram_channel_info *ch,
346 int channel, u32 val)
347 {
348 skl_dram_get_dimm_info(i915, &ch->dimm_l,
349 channel, 'L', val & 0xffff);
350 skl_dram_get_dimm_info(i915, &ch->dimm_s,
351 channel, 'S', val >> 16);
352
353 if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
354 drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel);
355 return -EINVAL;
356 }
357
358 if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
359 ch->ranks = 2;
360 else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
361 ch->ranks = 2;
362 else
363 ch->ranks = 1;
364
365 ch->is_16gb_dimm = skl_is_16gb_dimm(&ch->dimm_l) ||
366 skl_is_16gb_dimm(&ch->dimm_s);
367
368 drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb DIMMs: %s\n",
369 channel, ch->ranks, str_yes_no(ch->is_16gb_dimm));
370
371 return 0;
372 }
373
374 static bool
intel_is_dram_symmetric(const struct dram_channel_info * ch0,const struct dram_channel_info * ch1)375 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
376 const struct dram_channel_info *ch1)
377 {
378 return !memcmp(ch0, ch1, sizeof(*ch0)) &&
379 (ch0->dimm_s.size == 0 ||
380 !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
381 }
382
383 static int
skl_dram_get_channels_info(struct drm_i915_private * i915)384 skl_dram_get_channels_info(struct drm_i915_private *i915)
385 {
386 struct dram_info *dram_info = &i915->dram_info;
387 struct dram_channel_info ch0 = {}, ch1 = {};
388 u32 val;
389 int ret;
390
391 val = intel_uncore_read(&i915->uncore,
392 SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
393 ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
394 if (ret == 0)
395 dram_info->num_channels++;
396
397 val = intel_uncore_read(&i915->uncore,
398 SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
399 ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
400 if (ret == 0)
401 dram_info->num_channels++;
402
403 if (dram_info->num_channels == 0) {
404 drm_info(&i915->drm, "Number of memory channels is zero\n");
405 return -EINVAL;
406 }
407
408 if (ch0.ranks == 0 && ch1.ranks == 0) {
409 drm_info(&i915->drm, "couldn't get memory rank information\n");
410 return -EINVAL;
411 }
412
413 dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
414
415 dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
416
417 drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n",
418 str_yes_no(dram_info->symmetric_memory));
419
420 return 0;
421 }
422
423 static enum intel_dram_type
skl_get_dram_type(struct drm_i915_private * i915)424 skl_get_dram_type(struct drm_i915_private *i915)
425 {
426 u32 val;
427
428 val = intel_uncore_read(&i915->uncore,
429 SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
430
431 switch (val & SKL_DRAM_DDR_TYPE_MASK) {
432 case SKL_DRAM_DDR_TYPE_DDR3:
433 return INTEL_DRAM_DDR3;
434 case SKL_DRAM_DDR_TYPE_DDR4:
435 return INTEL_DRAM_DDR4;
436 case SKL_DRAM_DDR_TYPE_LPDDR3:
437 return INTEL_DRAM_LPDDR3;
438 case SKL_DRAM_DDR_TYPE_LPDDR4:
439 return INTEL_DRAM_LPDDR4;
440 default:
441 MISSING_CASE(val);
442 return INTEL_DRAM_UNKNOWN;
443 }
444 }
445
446 static int
skl_get_dram_info(struct drm_i915_private * i915)447 skl_get_dram_info(struct drm_i915_private *i915)
448 {
449 struct dram_info *dram_info = &i915->dram_info;
450 int ret;
451
452 dram_info->type = skl_get_dram_type(i915);
453
454 ret = skl_dram_get_channels_info(i915);
455 if (ret)
456 return ret;
457
458 return 0;
459 }
460
461 /* Returns Gb per DRAM device */
bxt_get_dimm_size(u32 val)462 static int bxt_get_dimm_size(u32 val)
463 {
464 switch (val & BXT_DRAM_SIZE_MASK) {
465 case BXT_DRAM_SIZE_4GBIT:
466 return 4;
467 case BXT_DRAM_SIZE_6GBIT:
468 return 6;
469 case BXT_DRAM_SIZE_8GBIT:
470 return 8;
471 case BXT_DRAM_SIZE_12GBIT:
472 return 12;
473 case BXT_DRAM_SIZE_16GBIT:
474 return 16;
475 default:
476 MISSING_CASE(val);
477 return 0;
478 }
479 }
480
bxt_get_dimm_width(u32 val)481 static int bxt_get_dimm_width(u32 val)
482 {
483 if (!bxt_get_dimm_size(val))
484 return 0;
485
486 val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
487
488 return 8 << val;
489 }
490
bxt_get_dimm_ranks(u32 val)491 static int bxt_get_dimm_ranks(u32 val)
492 {
493 if (!bxt_get_dimm_size(val))
494 return 0;
495
496 switch (val & BXT_DRAM_RANK_MASK) {
497 case BXT_DRAM_RANK_SINGLE:
498 return 1;
499 case BXT_DRAM_RANK_DUAL:
500 return 2;
501 default:
502 MISSING_CASE(val);
503 return 0;
504 }
505 }
506
bxt_get_dimm_type(u32 val)507 static enum intel_dram_type bxt_get_dimm_type(u32 val)
508 {
509 if (!bxt_get_dimm_size(val))
510 return INTEL_DRAM_UNKNOWN;
511
512 switch (val & BXT_DRAM_TYPE_MASK) {
513 case BXT_DRAM_TYPE_DDR3:
514 return INTEL_DRAM_DDR3;
515 case BXT_DRAM_TYPE_LPDDR3:
516 return INTEL_DRAM_LPDDR3;
517 case BXT_DRAM_TYPE_DDR4:
518 return INTEL_DRAM_DDR4;
519 case BXT_DRAM_TYPE_LPDDR4:
520 return INTEL_DRAM_LPDDR4;
521 default:
522 MISSING_CASE(val);
523 return INTEL_DRAM_UNKNOWN;
524 }
525 }
526
bxt_get_dimm_info(struct dram_dimm_info * dimm,u32 val)527 static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val)
528 {
529 dimm->width = bxt_get_dimm_width(val);
530 dimm->ranks = bxt_get_dimm_ranks(val);
531
532 /*
533 * Size in register is Gb per DRAM device. Convert to total
534 * Gb to match the way we report this for non-LP platforms.
535 */
536 dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm);
537 }
538
bxt_get_dram_info(struct drm_i915_private * i915)539 static int bxt_get_dram_info(struct drm_i915_private *i915)
540 {
541 struct dram_info *dram_info = &i915->dram_info;
542 u32 val;
543 u8 valid_ranks = 0;
544 int i;
545
546 /*
547 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
548 */
549 for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
550 struct dram_dimm_info dimm;
551 enum intel_dram_type type;
552
553 val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i));
554 if (val == 0xFFFFFFFF)
555 continue;
556
557 dram_info->num_channels++;
558
559 bxt_get_dimm_info(&dimm, val);
560 type = bxt_get_dimm_type(val);
561
562 drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN &&
563 dram_info->type != INTEL_DRAM_UNKNOWN &&
564 dram_info->type != type);
565
566 drm_dbg_kms(&i915->drm,
567 "CH%u DIMM size: %u Gb, width: X%u, ranks: %u\n",
568 i - BXT_D_CR_DRP0_DUNIT_START,
569 dimm.size, dimm.width, dimm.ranks);
570
571 if (valid_ranks == 0)
572 valid_ranks = dimm.ranks;
573
574 if (type != INTEL_DRAM_UNKNOWN)
575 dram_info->type = type;
576 }
577
578 if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) {
579 drm_info(&i915->drm, "couldn't get memory information\n");
580 return -EINVAL;
581 }
582
583 return 0;
584 }
585
icl_pcode_read_mem_global_info(struct drm_i915_private * dev_priv)586 static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
587 {
588 struct dram_info *dram_info = &dev_priv->dram_info;
589 u32 val = 0;
590 int ret;
591
592 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
593 ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
594 if (ret)
595 return ret;
596
597 if (GRAPHICS_VER(dev_priv) == 12) {
598 switch (val & 0xf) {
599 case 0:
600 dram_info->type = INTEL_DRAM_DDR4;
601 break;
602 case 1:
603 dram_info->type = INTEL_DRAM_DDR5;
604 break;
605 case 2:
606 dram_info->type = INTEL_DRAM_LPDDR5;
607 break;
608 case 3:
609 dram_info->type = INTEL_DRAM_LPDDR4;
610 break;
611 case 4:
612 dram_info->type = INTEL_DRAM_DDR3;
613 break;
614 case 5:
615 dram_info->type = INTEL_DRAM_LPDDR3;
616 break;
617 default:
618 MISSING_CASE(val & 0xf);
619 return -EINVAL;
620 }
621 } else {
622 switch (val & 0xf) {
623 case 0:
624 dram_info->type = INTEL_DRAM_DDR4;
625 break;
626 case 1:
627 dram_info->type = INTEL_DRAM_DDR3;
628 break;
629 case 2:
630 dram_info->type = INTEL_DRAM_LPDDR3;
631 break;
632 case 3:
633 dram_info->type = INTEL_DRAM_LPDDR4;
634 break;
635 default:
636 MISSING_CASE(val & 0xf);
637 return -EINVAL;
638 }
639 }
640
641 dram_info->num_channels = (val & 0xf0) >> 4;
642 dram_info->num_qgv_points = (val & 0xf00) >> 8;
643 dram_info->num_psf_gv_points = (val & 0x3000) >> 12;
644
645 return 0;
646 }
647
gen11_get_dram_info(struct drm_i915_private * i915)648 static int gen11_get_dram_info(struct drm_i915_private *i915)
649 {
650 int ret = skl_get_dram_info(i915);
651
652 if (ret)
653 return ret;
654
655 return icl_pcode_read_mem_global_info(i915);
656 }
657
gen12_get_dram_info(struct drm_i915_private * i915)658 static int gen12_get_dram_info(struct drm_i915_private *i915)
659 {
660 i915->dram_info.wm_lv_0_adjust_needed = false;
661
662 return icl_pcode_read_mem_global_info(i915);
663 }
664
xelpdp_get_dram_info(struct drm_i915_private * i915)665 static int xelpdp_get_dram_info(struct drm_i915_private *i915)
666 {
667 u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
668 struct dram_info *dram_info = &i915->dram_info;
669
670 switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
671 case 0:
672 dram_info->type = INTEL_DRAM_DDR4;
673 break;
674 case 1:
675 dram_info->type = INTEL_DRAM_DDR5;
676 break;
677 case 2:
678 dram_info->type = INTEL_DRAM_LPDDR5;
679 break;
680 case 3:
681 dram_info->type = INTEL_DRAM_LPDDR4;
682 break;
683 case 4:
684 dram_info->type = INTEL_DRAM_DDR3;
685 break;
686 case 5:
687 dram_info->type = INTEL_DRAM_LPDDR3;
688 break;
689 case 8:
690 drm_WARN_ON(&i915->drm, !IS_DGFX(i915));
691 dram_info->type = INTEL_DRAM_GDDR;
692 break;
693 case 9:
694 drm_WARN_ON(&i915->drm, !IS_DGFX(i915));
695 dram_info->type = INTEL_DRAM_GDDR_ECC;
696 break;
697 default:
698 MISSING_CASE(val);
699 return -EINVAL;
700 }
701
702 dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val);
703 dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
704 /* PSF GV points not supported in D14+ */
705
706 return 0;
707 }
708
intel_dram_detect(struct drm_i915_private * i915)709 void intel_dram_detect(struct drm_i915_private *i915)
710 {
711 struct dram_info *dram_info = &i915->dram_info;
712 int ret;
713
714 detect_fsb_freq(i915);
715 detect_mem_freq(i915);
716
717 if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))
718 return;
719
720 /*
721 * Assume level 0 watermark latency adjustment is needed until proven
722 * otherwise, this w/a is not needed by bxt/glk.
723 */
724 dram_info->wm_lv_0_adjust_needed = !IS_BROXTON(i915) && !IS_GEMINILAKE(i915);
725
726 if (DISPLAY_VER(i915) >= 14)
727 ret = xelpdp_get_dram_info(i915);
728 else if (GRAPHICS_VER(i915) >= 12)
729 ret = gen12_get_dram_info(i915);
730 else if (GRAPHICS_VER(i915) >= 11)
731 ret = gen11_get_dram_info(i915);
732 else if (IS_BROXTON(i915) || IS_GEMINILAKE(i915))
733 ret = bxt_get_dram_info(i915);
734 else
735 ret = skl_get_dram_info(i915);
736
737 drm_dbg_kms(&i915->drm, "DRAM type: %s\n",
738 intel_dram_type_str(dram_info->type));
739
740 if (ret)
741 return;
742
743 drm_dbg_kms(&i915->drm, "Num qgv points %u\n", dram_info->num_qgv_points);
744
745 drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);
746
747 drm_dbg_kms(&i915->drm, "Watermark level 0 adjustment needed: %s\n",
748 str_yes_no(dram_info->wm_lv_0_adjust_needed));
749 }
750
gen9_edram_size_mb(struct drm_i915_private * i915,u32 cap)751 static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
752 {
753 static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
754 static const u8 sets[4] = { 1, 1, 2, 2 };
755
756 return EDRAM_NUM_BANKS(cap) *
757 ways[EDRAM_WAYS_IDX(cap)] *
758 sets[EDRAM_SETS_IDX(cap)];
759 }
760
intel_dram_edram_detect(struct drm_i915_private * i915)761 void intel_dram_edram_detect(struct drm_i915_private *i915)
762 {
763 u32 edram_cap = 0;
764
765 if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9))
766 return;
767
768 edram_cap = intel_uncore_read_fw(&i915->uncore, HSW_EDRAM_CAP);
769
770 /* NB: We can't write IDICR yet because we don't have gt funcs set up */
771
772 if (!(edram_cap & EDRAM_ENABLED))
773 return;
774
775 /*
776 * The needed capability bits for size calculation are not there with
777 * pre gen9 so return 128MB always.
778 */
779 if (GRAPHICS_VER(i915) < 9)
780 i915->edram_size_mb = 128;
781 else
782 i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);
783
784 drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb);
785 }
786