1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
5 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
6 * Copyright (c) 2000 BSDi
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39
40 #include <dev/pci/pcivar.h>
41 #include <dev/pci/pcireg.h>
42
43 /*
44 * Chipset fixups.
45 *
46 * These routines are invoked during the probe phase for devices which
47 * typically don't have specific device drivers, but which require
48 * some cleaning up.
49 */
50
51 static int fixup_pci_probe(device_t dev);
52 static void fixwsc_natoma(device_t dev);
53 static void fixc1_nforce2(device_t dev);
54
55 static device_method_t fixup_pci_methods[] = {
56 /* Device interface */
57 DEVMETHOD(device_probe, fixup_pci_probe),
58 { 0, 0 }
59 };
60
61 static driver_t fixup_pci_driver = {
62 "fixup_pci",
63 fixup_pci_methods,
64 0,
65 };
66
67 DRIVER_MODULE(fixup_pci, pci, fixup_pci_driver, 0, 0);
68
69 static int
fixup_pci_probe(device_t dev)70 fixup_pci_probe(device_t dev)
71 {
72 switch (pci_get_devid(dev)) {
73 case 0x12378086: /* Intel 82440FX (Natoma) */
74 fixwsc_natoma(dev);
75 break;
76 case 0x01e010de: /* nVidia nForce2 */
77 fixc1_nforce2(dev);
78 break;
79 }
80 return(ENXIO);
81 }
82
83 static void
fixwsc_natoma(device_t dev)84 fixwsc_natoma(device_t dev)
85 {
86 int pmccfg;
87
88 pmccfg = pci_read_config(dev, 0x50, 2);
89 #if defined(SMP)
90 if (pmccfg & 0x8000) {
91 device_printf(dev, "correcting Natoma config for SMP\n");
92 pmccfg &= ~0x8000;
93 pci_write_config(dev, 0x50, pmccfg, 2);
94 }
95 #else
96 if ((pmccfg & 0x8000) == 0) {
97 device_printf(dev, "correcting Natoma config for non-SMP\n");
98 pmccfg |= 0x8000;
99 pci_write_config(dev, 0x50, pmccfg, 2);
100 }
101 #endif
102 }
103
104 /*
105 * Set the SYSTEM_IDLE_TIMEOUT to 80 ns on nForce2 systems to work
106 * around a hang that is triggered when the CPU generates a very fast
107 * CONNECT/HALT cycle sequence. Specifically, the hang can result in
108 * the lapic timer being stopped.
109 *
110 * This requires changing the value for config register at offset 0x6c
111 * for the Host-PCI bridge at bus/dev/function 0/0/0:
112 *
113 * Chip Current Value New Value
114 * ---- ---------- ----------
115 * C17 0x1F0FFF01 0x1F01FF01
116 * C18D 0x9F0FFF01 0x9F01FF01
117 *
118 * We do this by always clearing the bits in 0x000e0000.
119 *
120 * See also: http://lkml.org/lkml/2004/5/3/157
121 */
122 static void
fixc1_nforce2(device_t dev)123 fixc1_nforce2(device_t dev)
124 {
125 uint32_t val;
126
127 if (pci_get_bus(dev) == 0 && pci_get_slot(dev) == 0 &&
128 pci_get_function(dev) == 0) {
129 val = pci_read_config(dev, 0x6c, 4);
130 if (val & 0x000e0000) {
131 device_printf(dev,
132 "correcting nForce2 C1 CPU disconnect hangs\n");
133 val &= ~0x000e0000;
134 pci_write_config(dev, 0x6c, val, 4);
135 }
136 }
137 }
138