1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause
3 *
4 * Copyright (c) 1991 Regents of the University of California.
5 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
7 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
8 * Copyright (c) 2014-2016 Svatopluk Kraus <skra@FreeBSD.org>
9 * Copyright (c) 2014-2016 Michal Meloun <mmel@FreeBSD.org>
10 * All rights reserved.
11 *
12 * This code is derived from software contributed to Berkeley by
13 * the Systems Programming Group of the University of Utah Computer
14 * Science Department and William Jolitz of UUNET Technologies Inc.
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
18 * are met:
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 * 3. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 */
40 /*-
41 * Copyright (c) 2003 Networks Associates Technology, Inc.
42 * All rights reserved.
43 *
44 * This software was developed for the FreeBSD Project by Jake Burkholder,
45 * Safeport Network Services, and Network Associates Laboratories, the
46 * Security Research Division of Network Associates, Inc. under
47 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
48 * CHATS research program.
49 *
50 * Redistribution and use in source and binary forms, with or without
51 * modification, are permitted provided that the following conditions
52 * are met:
53 * 1. Redistributions of source code must retain the above copyright
54 * notice, this list of conditions and the following disclaimer.
55 * 2. Redistributions in binary form must reproduce the above copyright
56 * notice, this list of conditions and the following disclaimer in the
57 * documentation and/or other materials provided with the distribution.
58 *
59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
62 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 * SUCH DAMAGE.
70 */
71
72 #include <sys/cdefs.h>
73 /*
74 * Manages physical address maps.
75 *
76 * Since the information managed by this module is
77 * also stored by the logical address mapping module,
78 * this module may throw away valid virtual-to-physical
79 * mappings at almost any time. However, invalidations
80 * of virtual-to-physical mappings must be done as
81 * requested.
82 *
83 * In order to cope with hardware architectures which
84 * make virtual-to-physical map invalidates expensive,
85 * this module may delay invalidate or reduced protection
86 * operations until such time as they are actually
87 * necessary. This module is given full information as
88 * to which processors are currently using which maps,
89 * and to when physical maps must be made correct.
90 */
91
92 #include "opt_vm.h"
93 #include "opt_pmap.h"
94 #include "opt_ddb.h"
95
96 #include <sys/param.h>
97 #include <sys/systm.h>
98 #include <sys/kernel.h>
99 #include <sys/ktr.h>
100 #include <sys/lock.h>
101 #include <sys/proc.h>
102 #include <sys/rwlock.h>
103 #include <sys/malloc.h>
104 #include <sys/vmmeter.h>
105 #include <sys/malloc.h>
106 #include <sys/mman.h>
107 #include <sys/sf_buf.h>
108 #include <sys/smp.h>
109 #include <sys/sched.h>
110 #include <sys/sysctl.h>
111
112 #ifdef DDB
113 #include <ddb/ddb.h>
114 #endif
115
116 #include <vm/vm.h>
117 #include <vm/uma.h>
118 #include <vm/pmap.h>
119 #include <vm/vm_param.h>
120 #include <vm/vm_kern.h>
121 #include <vm/vm_object.h>
122 #include <vm/vm_map.h>
123 #include <vm/vm_page.h>
124 #include <vm/vm_pageout.h>
125 #include <vm/vm_phys.h>
126 #include <vm/vm_extern.h>
127 #include <vm/vm_reserv.h>
128 #include <sys/lock.h>
129 #include <sys/mutex.h>
130
131 #include <machine/md_var.h>
132 #include <machine/pmap_var.h>
133 #include <machine/cpu.h>
134 #include <machine/pcb.h>
135 #include <machine/sf_buf.h>
136 #ifdef SMP
137 #include <machine/smp.h>
138 #endif
139 #ifndef PMAP_SHPGPERPROC
140 #define PMAP_SHPGPERPROC 200
141 #endif
142
143 #ifndef DIAGNOSTIC
144 #define PMAP_INLINE __inline
145 #else
146 #define PMAP_INLINE
147 #endif
148
149 #ifdef PMAP_DEBUG
150 static void pmap_zero_page_check(vm_page_t m);
151 void pmap_debug(int level);
152 int pmap_pid_dump(int pid);
153
154 #define PDEBUG(_lev_,_stat_) \
155 if (pmap_debug_level >= (_lev_)) \
156 ((_stat_))
157 #define dprintf printf
158 int pmap_debug_level = 1;
159 #else /* PMAP_DEBUG */
160 #define PDEBUG(_lev_,_stat_) /* Nothing */
161 #define dprintf(x, arg...)
162 #endif /* PMAP_DEBUG */
163
164 /*
165 * Level 2 page tables map definion ('max' is excluded).
166 */
167
168 #define PT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
169 #define PT2V_MAX_ADDRESS ((vm_offset_t)PT2MAP + PT2MAP_SIZE)
170
171 #define UPT2V_MIN_ADDRESS ((vm_offset_t)PT2MAP)
172 #define UPT2V_MAX_ADDRESS \
173 ((vm_offset_t)(PT2MAP + (KERNBASE >> PT2MAP_SHIFT)))
174
175 /*
176 * Promotion to a 1MB (PTE1) page mapping requires that the corresponding
177 * 4KB (PTE2) page mappings have identical settings for the following fields:
178 */
179 #define PTE2_PROMOTE (PTE2_V | PTE2_A | PTE2_NM | PTE2_S | PTE2_NG | \
180 PTE2_NX | PTE2_RO | PTE2_U | PTE2_W | \
181 PTE2_ATTR_MASK)
182
183 #define PTE1_PROMOTE (PTE1_V | PTE1_A | PTE1_NM | PTE1_S | PTE1_NG | \
184 PTE1_NX | PTE1_RO | PTE1_U | PTE1_W | \
185 PTE1_ATTR_MASK)
186
187 #define ATTR_TO_L1(l2_attr) ((((l2_attr) & L2_TEX0) ? L1_S_TEX0 : 0) | \
188 (((l2_attr) & L2_C) ? L1_S_C : 0) | \
189 (((l2_attr) & L2_B) ? L1_S_B : 0) | \
190 (((l2_attr) & PTE2_A) ? PTE1_A : 0) | \
191 (((l2_attr) & PTE2_NM) ? PTE1_NM : 0) | \
192 (((l2_attr) & PTE2_S) ? PTE1_S : 0) | \
193 (((l2_attr) & PTE2_NG) ? PTE1_NG : 0) | \
194 (((l2_attr) & PTE2_NX) ? PTE1_NX : 0) | \
195 (((l2_attr) & PTE2_RO) ? PTE1_RO : 0) | \
196 (((l2_attr) & PTE2_U) ? PTE1_U : 0) | \
197 (((l2_attr) & PTE2_W) ? PTE1_W : 0))
198
199 #define ATTR_TO_L2(l1_attr) ((((l1_attr) & L1_S_TEX0) ? L2_TEX0 : 0) | \
200 (((l1_attr) & L1_S_C) ? L2_C : 0) | \
201 (((l1_attr) & L1_S_B) ? L2_B : 0) | \
202 (((l1_attr) & PTE1_A) ? PTE2_A : 0) | \
203 (((l1_attr) & PTE1_NM) ? PTE2_NM : 0) | \
204 (((l1_attr) & PTE1_S) ? PTE2_S : 0) | \
205 (((l1_attr) & PTE1_NG) ? PTE2_NG : 0) | \
206 (((l1_attr) & PTE1_NX) ? PTE2_NX : 0) | \
207 (((l1_attr) & PTE1_RO) ? PTE2_RO : 0) | \
208 (((l1_attr) & PTE1_U) ? PTE2_U : 0) | \
209 (((l1_attr) & PTE1_W) ? PTE2_W : 0))
210
211 /*
212 * PTE2 descriptors creation macros.
213 */
214 #define PTE2_ATTR_DEFAULT vm_memattr_to_pte2(VM_MEMATTR_DEFAULT)
215 #define PTE2_ATTR_PT vm_memattr_to_pte2(pt_memattr)
216
217 #define PTE2_KPT(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
218 #define PTE2_KPT_NG(pa) PTE2_KERN_NG(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
219
220 #define PTE2_KRW(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT)
221 #define PTE2_KRO(pa) PTE2_KERN(pa, PTE2_AP_KR, PTE2_ATTR_DEFAULT)
222
223 #define PV_STATS
224 #ifdef PV_STATS
225 #define PV_STAT(x) do { x ; } while (0)
226 #else
227 #define PV_STAT(x) do { } while (0)
228 #endif
229
230 /*
231 * The boot_pt1 is used temporary in very early boot stage as L1 page table.
232 * We can init many things with no memory allocation thanks to its static
233 * allocation and this brings two main advantages:
234 * (1) other cores can be started very simply,
235 * (2) various boot loaders can be supported as its arguments can be processed
236 * in virtual address space and can be moved to safe location before
237 * first allocation happened.
238 * Only disadvantage is that boot_pt1 is used only in very early boot stage.
239 * However, the table is uninitialized and so lays in bss. Therefore kernel
240 * image size is not influenced.
241 *
242 * QQQ: In the future, maybe, boot_pt1 can be used for soft reset and
243 * CPU suspend/resume game.
244 */
245 extern pt1_entry_t boot_pt1[];
246
247 vm_paddr_t base_pt1;
248 pt1_entry_t *kern_pt1;
249 pt2_entry_t *kern_pt2tab;
250 pt2_entry_t *PT2MAP;
251
252 static uint32_t ttb_flags;
253 static vm_memattr_t pt_memattr;
254 ttb_entry_t pmap_kern_ttb;
255
256 struct pmap kernel_pmap_store;
257 LIST_HEAD(pmaplist, pmap);
258 static struct pmaplist allpmaps;
259 static struct mtx allpmaps_lock;
260
261 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
262 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
263
264 static vm_offset_t kernel_vm_end_new;
265 vm_offset_t kernel_vm_end = KERNBASE + NKPT2PG * NPT2_IN_PG * PTE1_SIZE;
266 vm_offset_t vm_max_kernel_address;
267 vm_paddr_t kernel_l1pa;
268
269 static struct rwlock __aligned(CACHE_LINE_SIZE) pvh_global_lock;
270
271 /*
272 * Data for the pv entry allocation mechanism
273 */
274 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
275 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
276 static struct md_page *pv_table; /* XXX: Is it used only the list in md_page? */
277 static int shpgperproc = PMAP_SHPGPERPROC;
278
279 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
280 int pv_maxchunks; /* How many chunks we have KVA for */
281 vm_offset_t pv_vafree; /* freelist stored in the PTE */
282
283 vm_paddr_t first_managed_pa;
284 #define pa_to_pvh(pa) (&pv_table[pte1_index(pa - first_managed_pa)])
285
286 /*
287 * All those kernel PT submaps that BSD is so fond of
288 */
289 caddr_t _tmppt = 0;
290
291 /*
292 * Crashdump maps.
293 */
294 static caddr_t crashdumpmap;
295
296 static pt2_entry_t *PMAP1 = NULL, *PMAP2;
297 static pt2_entry_t *PADDR1 = NULL, *PADDR2;
298 #ifdef DDB
299 static pt2_entry_t *PMAP3;
300 static pt2_entry_t *PADDR3;
301 static int PMAP3cpu __unused; /* for SMP only */
302 #endif
303 #ifdef SMP
304 static int PMAP1cpu;
305 static int PMAP1changedcpu;
306 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
307 &PMAP1changedcpu, 0,
308 "Number of times pmap_pte2_quick changed CPU with same PMAP1");
309 #endif
310 static int PMAP1changed;
311 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
312 &PMAP1changed, 0,
313 "Number of times pmap_pte2_quick changed PMAP1");
314 static int PMAP1unchanged;
315 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
316 &PMAP1unchanged, 0,
317 "Number of times pmap_pte2_quick didn't change PMAP1");
318 static struct mtx PMAP2mutex;
319
320 /*
321 * Internal flags for pmap_enter()'s helper functions.
322 */
323 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
324 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
325
326 static __inline void pt2_wirecount_init(vm_page_t m);
327 static bool pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p,
328 vm_offset_t va);
329 static int pmap_enter_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t pte1,
330 u_int flags, vm_page_t m);
331 void cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size);
332
333 /*
334 * Function to set the debug level of the pmap code.
335 */
336 #ifdef PMAP_DEBUG
337 void
pmap_debug(int level)338 pmap_debug(int level)
339 {
340
341 pmap_debug_level = level;
342 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
343 }
344 #endif /* PMAP_DEBUG */
345
346 /*
347 * This table must corespond with memory attribute configuration in vm.h.
348 * First entry is used for normal system mapping.
349 *
350 * Device memory is always marked as shared.
351 * Normal memory is shared only in SMP .
352 * Not outer shareable bits are not used yet.
353 * Class 6 cannot be used on ARM11.
354 */
355 #define TEXDEF_TYPE_SHIFT 0
356 #define TEXDEF_TYPE_MASK 0x3
357 #define TEXDEF_INNER_SHIFT 2
358 #define TEXDEF_INNER_MASK 0x3
359 #define TEXDEF_OUTER_SHIFT 4
360 #define TEXDEF_OUTER_MASK 0x3
361 #define TEXDEF_NOS_SHIFT 6
362 #define TEXDEF_NOS_MASK 0x1
363
364 #define TEX(t, i, o, s) \
365 ((t) << TEXDEF_TYPE_SHIFT) | \
366 ((i) << TEXDEF_INNER_SHIFT) | \
367 ((o) << TEXDEF_OUTER_SHIFT | \
368 ((s) << TEXDEF_NOS_SHIFT))
369
370 static uint32_t tex_class[8] = {
371 /* type inner cache outer cache */
372 TEX(PRRR_MEM, NMRR_WB_WA, NMRR_WB_WA, 0), /* 0 - ATTR_WB_WA */
373 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 1 - ATTR_NOCACHE */
374 TEX(PRRR_DEV, NMRR_NC, NMRR_NC, 0), /* 2 - ATTR_DEVICE */
375 TEX(PRRR_SO, NMRR_NC, NMRR_NC, 0), /* 3 - ATTR_SO */
376 TEX(PRRR_MEM, NMRR_WT, NMRR_WT, 0), /* 4 - ATTR_WT */
377 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 5 - NOT USED YET */
378 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 6 - NOT USED YET */
379 TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 7 - NOT USED YET */
380 };
381 #undef TEX
382
383 static uint32_t pte2_attr_tab[8] = {
384 PTE2_ATTR_WB_WA, /* 0 - VM_MEMATTR_WB_WA */
385 PTE2_ATTR_NOCACHE, /* 1 - VM_MEMATTR_NOCACHE */
386 PTE2_ATTR_DEVICE, /* 2 - VM_MEMATTR_DEVICE */
387 PTE2_ATTR_SO, /* 3 - VM_MEMATTR_SO */
388 PTE2_ATTR_WT, /* 4 - VM_MEMATTR_WRITE_THROUGH */
389 0, /* 5 - NOT USED YET */
390 0, /* 6 - NOT USED YET */
391 0 /* 7 - NOT USED YET */
392 };
393 CTASSERT(VM_MEMATTR_WB_WA == 0);
394 CTASSERT(VM_MEMATTR_NOCACHE == 1);
395 CTASSERT(VM_MEMATTR_DEVICE == 2);
396 CTASSERT(VM_MEMATTR_SO == 3);
397 CTASSERT(VM_MEMATTR_WRITE_THROUGH == 4);
398 #define VM_MEMATTR_END (VM_MEMATTR_WRITE_THROUGH + 1)
399
400 bool
pmap_is_valid_memattr(pmap_t pmap __unused,vm_memattr_t mode)401 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
402 {
403
404 return (mode >= 0 && mode < VM_MEMATTR_END);
405 }
406
407 static inline uint32_t
vm_memattr_to_pte2(vm_memattr_t ma)408 vm_memattr_to_pte2(vm_memattr_t ma)
409 {
410
411 KASSERT((u_int)ma < VM_MEMATTR_END,
412 ("%s: bad vm_memattr_t %d", __func__, ma));
413 return (pte2_attr_tab[(u_int)ma]);
414 }
415
416 static inline uint32_t
vm_page_pte2_attr(vm_page_t m)417 vm_page_pte2_attr(vm_page_t m)
418 {
419
420 return (vm_memattr_to_pte2(m->md.pat_mode));
421 }
422
423 /*
424 * Convert TEX definition entry to TTB flags.
425 */
426 static uint32_t
encode_ttb_flags(int idx)427 encode_ttb_flags(int idx)
428 {
429 uint32_t inner, outer, nos, reg;
430
431 inner = (tex_class[idx] >> TEXDEF_INNER_SHIFT) &
432 TEXDEF_INNER_MASK;
433 outer = (tex_class[idx] >> TEXDEF_OUTER_SHIFT) &
434 TEXDEF_OUTER_MASK;
435 nos = (tex_class[idx] >> TEXDEF_NOS_SHIFT) &
436 TEXDEF_NOS_MASK;
437
438 reg = nos << 5;
439 reg |= outer << 3;
440 if (cpuinfo.coherent_walk)
441 reg |= (inner & 0x1) << 6;
442 reg |= (inner & 0x2) >> 1;
443 #ifdef SMP
444 ARM_SMP_UP(
445 reg |= 1 << 1,
446 );
447 #endif
448 return reg;
449 }
450
451 /*
452 * Set TEX remapping registers in current CPU.
453 */
454 void
pmap_set_tex(void)455 pmap_set_tex(void)
456 {
457 uint32_t prrr, nmrr;
458 uint32_t type, inner, outer, nos;
459 int i;
460
461 #ifdef PMAP_PTE_NOCACHE
462 /* XXX fixme */
463 if (cpuinfo.coherent_walk) {
464 pt_memattr = VM_MEMATTR_WB_WA;
465 ttb_flags = encode_ttb_flags(0);
466 }
467 else {
468 pt_memattr = VM_MEMATTR_NOCACHE;
469 ttb_flags = encode_ttb_flags(1);
470 }
471 #else
472 pt_memattr = VM_MEMATTR_WB_WA;
473 ttb_flags = encode_ttb_flags(0);
474 #endif
475
476 prrr = 0;
477 nmrr = 0;
478
479 /* Build remapping register from TEX classes. */
480 for (i = 0; i < 8; i++) {
481 type = (tex_class[i] >> TEXDEF_TYPE_SHIFT) &
482 TEXDEF_TYPE_MASK;
483 inner = (tex_class[i] >> TEXDEF_INNER_SHIFT) &
484 TEXDEF_INNER_MASK;
485 outer = (tex_class[i] >> TEXDEF_OUTER_SHIFT) &
486 TEXDEF_OUTER_MASK;
487 nos = (tex_class[i] >> TEXDEF_NOS_SHIFT) &
488 TEXDEF_NOS_MASK;
489
490 prrr |= type << (i * 2);
491 prrr |= nos << (i + 24);
492 nmrr |= inner << (i * 2);
493 nmrr |= outer << (i * 2 + 16);
494 }
495 /* Add shareable bits for device memory. */
496 prrr |= PRRR_DS0 | PRRR_DS1;
497
498 /* Add shareable bits for normal memory in SMP case. */
499 #ifdef SMP
500 ARM_SMP_UP(
501 prrr |= PRRR_NS1,
502 );
503 #endif
504 cp15_prrr_set(prrr);
505 cp15_nmrr_set(nmrr);
506
507 /* Caches are disabled, so full TLB flush should be enough. */
508 tlb_flush_all_local();
509 }
510
511 /*
512 * Remap one vm_meattr class to another one. This can be useful as
513 * workaround for SOC errata, e.g. if devices must be accessed using
514 * SO memory class.
515 *
516 * !!! Please note that this function is absolutely last resort thing.
517 * It should not be used under normal circumstances. !!!
518 *
519 * Usage rules:
520 * - it shall be called after pmap_bootstrap_prepare() and before
521 * cpu_mp_start() (thus only on boot CPU). In practice, it's expected
522 * to be called from platform_attach() or platform_late_init().
523 *
524 * - if remapping doesn't change caching mode, or until uncached class
525 * is remapped to any kind of cached one, then no other restriction exists.
526 *
527 * - if pmap_remap_vm_attr() changes caching mode, but both (original and
528 * remapped) remain cached, then caller is resposible for calling
529 * of dcache_wbinv_poc_all().
530 *
531 * - remapping of any kind of cached class to uncached is not permitted.
532 */
533 void
pmap_remap_vm_attr(vm_memattr_t old_attr,vm_memattr_t new_attr)534 pmap_remap_vm_attr(vm_memattr_t old_attr, vm_memattr_t new_attr)
535 {
536 int old_idx, new_idx;
537
538 /* Map VM memattrs to indexes to tex_class table. */
539 old_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)old_attr]);
540 new_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)new_attr]);
541
542 /* Replace TEX attribute and apply it. */
543 tex_class[old_idx] = tex_class[new_idx];
544 pmap_set_tex();
545 }
546
547 /*
548 * KERNBASE must be multiple of NPT2_IN_PG * PTE1_SIZE. In other words,
549 * KERNBASE is mapped by first L2 page table in L2 page table page. It
550 * meets same constrain due to PT2MAP being placed just under KERNBASE.
551 */
552 CTASSERT((KERNBASE & (NPT2_IN_PG * PTE1_SIZE - 1)) == 0);
553 CTASSERT((KERNBASE - VM_MAXUSER_ADDRESS) >= PT2MAP_SIZE);
554
555 /*
556 * In crazy dreams, PAGE_SIZE could be a multiple of PTE2_SIZE in general.
557 * For now, anyhow, the following check must be fulfilled.
558 */
559 CTASSERT(PAGE_SIZE == PTE2_SIZE);
560 /*
561 * We don't want to mess up MI code with all MMU and PMAP definitions,
562 * so some things, which depend on other ones, are defined independently.
563 * Now, it is time to check that we don't screw up something.
564 */
565 CTASSERT(PDRSHIFT == PTE1_SHIFT);
566 /*
567 * Check L1 and L2 page table entries definitions consistency.
568 */
569 CTASSERT(NB_IN_PT1 == (sizeof(pt1_entry_t) * NPTE1_IN_PT1));
570 CTASSERT(NB_IN_PT2 == (sizeof(pt2_entry_t) * NPTE2_IN_PT2));
571 /*
572 * Check L2 page tables page consistency.
573 */
574 CTASSERT(PAGE_SIZE == (NPT2_IN_PG * NB_IN_PT2));
575 CTASSERT((1 << PT2PG_SHIFT) == NPT2_IN_PG);
576 /*
577 * Check PT2TAB consistency.
578 * PT2TAB_ENTRIES is defined as a division of NPTE1_IN_PT1 by NPT2_IN_PG.
579 * This should be done without remainder.
580 */
581 CTASSERT(NPTE1_IN_PT1 == (PT2TAB_ENTRIES * NPT2_IN_PG));
582
583 /*
584 * A PT2MAP magic.
585 *
586 * All level 2 page tables (PT2s) are mapped continuously and accordingly
587 * into PT2MAP address space. As PT2 size is less than PAGE_SIZE, this can
588 * be done only if PAGE_SIZE is a multiple of PT2 size. All PT2s in one page
589 * must be used together, but not necessary at once. The first PT2 in a page
590 * must map things on correctly aligned address and the others must follow
591 * in right order.
592 */
593 #define NB_IN_PT2TAB (PT2TAB_ENTRIES * sizeof(pt2_entry_t))
594 #define NPT2_IN_PT2TAB (NB_IN_PT2TAB / NB_IN_PT2)
595 #define NPG_IN_PT2TAB (NB_IN_PT2TAB / PAGE_SIZE)
596
597 /*
598 * Check PT2TAB consistency.
599 * NPT2_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by NB_IN_PT2.
600 * NPG_IN_PT2TAB is defined as a division of NB_IN_PT2TAB by PAGE_SIZE.
601 * The both should be done without remainder.
602 */
603 CTASSERT(NB_IN_PT2TAB == (NPT2_IN_PT2TAB * NB_IN_PT2));
604 CTASSERT(NB_IN_PT2TAB == (NPG_IN_PT2TAB * PAGE_SIZE));
605 /*
606 * The implementation was made general, however, with the assumption
607 * bellow in mind. In case of another value of NPG_IN_PT2TAB,
608 * the code should be once more rechecked.
609 */
610 CTASSERT(NPG_IN_PT2TAB == 1);
611
612 /*
613 * Get offset of PT2 in a page
614 * associated with given PT1 index.
615 */
616 static __inline u_int
page_pt2off(u_int pt1_idx)617 page_pt2off(u_int pt1_idx)
618 {
619
620 return ((pt1_idx & PT2PG_MASK) * NB_IN_PT2);
621 }
622
623 /*
624 * Get physical address of PT2
625 * associated with given PT2s page and PT1 index.
626 */
627 static __inline vm_paddr_t
page_pt2pa(vm_paddr_t pgpa,u_int pt1_idx)628 page_pt2pa(vm_paddr_t pgpa, u_int pt1_idx)
629 {
630
631 return (pgpa + page_pt2off(pt1_idx));
632 }
633
634 /*
635 * Get first entry of PT2
636 * associated with given PT2s page and PT1 index.
637 */
638 static __inline pt2_entry_t *
page_pt2(vm_offset_t pgva,u_int pt1_idx)639 page_pt2(vm_offset_t pgva, u_int pt1_idx)
640 {
641
642 return ((pt2_entry_t *)(pgva + page_pt2off(pt1_idx)));
643 }
644
645 /*
646 * Get virtual address of PT2s page (mapped in PT2MAP)
647 * which holds PT2 which holds entry which maps given virtual address.
648 */
649 static __inline vm_offset_t
pt2map_pt2pg(vm_offset_t va)650 pt2map_pt2pg(vm_offset_t va)
651 {
652
653 va &= ~(NPT2_IN_PG * PTE1_SIZE - 1);
654 return ((vm_offset_t)pt2map_entry(va));
655 }
656
657 /*****************************************************************************
658 *
659 * THREE pmap initialization milestones exist:
660 *
661 * locore.S
662 * -> fundamental init (including MMU) in ASM
663 *
664 * initarm()
665 * -> fundamental init continues in C
666 * -> first available physical address is known
667 *
668 * pmap_bootstrap_prepare() -> FIRST PMAP MILESTONE (first epoch begins)
669 * -> basic (safe) interface for physical address allocation is made
670 * -> basic (safe) interface for virtual mapping is made
671 * -> limited not SMP coherent work is possible
672 *
673 * -> more fundamental init continues in C
674 * -> locks and some more things are available
675 * -> all fundamental allocations and mappings are done
676 *
677 * pmap_bootstrap() -> SECOND PMAP MILESTONE (second epoch begins)
678 * -> phys_avail[] and virtual_avail is set
679 * -> control is passed to vm subsystem
680 * -> physical and virtual address allocation are off limit
681 * -> low level mapping functions, some SMP coherent,
682 * are available, which cannot be used before vm subsystem
683 * is being inited
684 *
685 * mi_startup()
686 * -> vm subsystem is being inited
687 *
688 * pmap_init() -> THIRD PMAP MILESTONE (third epoch begins)
689 * -> pmap is fully inited
690 *
691 *****************************************************************************/
692
693 /*****************************************************************************
694 *
695 * PMAP first stage initialization and utility functions
696 * for pre-bootstrap epoch.
697 *
698 * After pmap_bootstrap_prepare() is called, the following functions
699 * can be used:
700 *
701 * (1) strictly only for this stage functions for physical page allocations,
702 * virtual space allocations, and mappings:
703 *
704 * vm_paddr_t pmap_preboot_get_pages(u_int num);
705 * void pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num);
706 * vm_offset_t pmap_preboot_reserve_pages(u_int num);
707 * vm_offset_t pmap_preboot_get_vpages(u_int num);
708 * void pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
709 * vm_prot_t prot, vm_memattr_t attr);
710 *
711 * (2) for all stages:
712 *
713 * vm_paddr_t pmap_kextract(vm_offset_t va);
714 *
715 * NOTE: This is not SMP coherent stage.
716 *
717 *****************************************************************************/
718
719 #define KERNEL_P2V(pa) \
720 ((vm_offset_t)((pa) - arm_physmem_kernaddr + KERNVIRTADDR))
721 #define KERNEL_V2P(va) \
722 ((vm_paddr_t)((va) - KERNVIRTADDR + arm_physmem_kernaddr))
723
724 static vm_paddr_t last_paddr;
725
726 /*
727 * Pre-bootstrap epoch page allocator.
728 */
729 vm_paddr_t
pmap_preboot_get_pages(u_int num)730 pmap_preboot_get_pages(u_int num)
731 {
732 vm_paddr_t ret;
733
734 ret = last_paddr;
735 last_paddr += num * PAGE_SIZE;
736
737 return (ret);
738 }
739
740 /*
741 * The fundamental initialization of PMAP stuff.
742 *
743 * Some things already happened in locore.S and some things could happen
744 * before pmap_bootstrap_prepare() is called, so let's recall what is done:
745 * 1. Caches are disabled.
746 * 2. We are running on virtual addresses already with 'boot_pt1'
747 * as L1 page table.
748 * 3. So far, all virtual addresses can be converted to physical ones and
749 * vice versa by the following macros:
750 * KERNEL_P2V(pa) .... physical to virtual ones,
751 * KERNEL_V2P(va) .... virtual to physical ones.
752 *
753 * What is done herein:
754 * 1. The 'boot_pt1' is replaced by real kernel L1 page table 'kern_pt1'.
755 * 2. PT2MAP magic is brought to live.
756 * 3. Basic preboot functions for page allocations and mappings can be used.
757 * 4. Everything is prepared for L1 cache enabling.
758 *
759 * Variations:
760 * 1. To use second TTB register, so kernel and users page tables will be
761 * separated. This way process forking - pmap_pinit() - could be faster,
762 * it saves physical pages and KVA per a process, and it's simple change.
763 * However, it will lead, due to hardware matter, to the following:
764 * (a) 2G space for kernel and 2G space for users.
765 * (b) 1G space for kernel in low addresses and 3G for users above it.
766 * A question is: Is the case (b) really an option? Note that case (b)
767 * does save neither physical memory and KVA.
768 */
769 void
pmap_bootstrap_prepare(vm_paddr_t last)770 pmap_bootstrap_prepare(vm_paddr_t last)
771 {
772 vm_paddr_t pt2pg_pa, pt2tab_pa, pa, size;
773 vm_offset_t pt2pg_va;
774 pt1_entry_t *pte1p;
775 pt2_entry_t *pte2p;
776 u_int i;
777 uint32_t l1_attr;
778
779 /*
780 * Now, we are going to make real kernel mapping. Note that we are
781 * already running on some mapping made in locore.S and we expect
782 * that it's large enough to ensure nofault access to physical memory
783 * allocated herein before switch.
784 *
785 * As kernel image and everything needed before are and will be mapped
786 * by section mappings, we align last physical address to PTE1_SIZE.
787 */
788 last_paddr = pte1_roundup(last);
789
790 /*
791 * Allocate and zero page(s) for kernel L1 page table.
792 *
793 * Note that it's first allocation on space which was PTE1_SIZE
794 * aligned and as such base_pt1 is aligned to NB_IN_PT1 too.
795 */
796 base_pt1 = pmap_preboot_get_pages(NPG_IN_PT1);
797 kern_pt1 = (pt1_entry_t *)KERNEL_P2V(base_pt1);
798 bzero((void*)kern_pt1, NB_IN_PT1);
799 pte1_sync_range(kern_pt1, NB_IN_PT1);
800
801 /* Allocate and zero page(s) for kernel PT2TAB. */
802 pt2tab_pa = pmap_preboot_get_pages(NPG_IN_PT2TAB);
803 kern_pt2tab = (pt2_entry_t *)KERNEL_P2V(pt2tab_pa);
804 bzero(kern_pt2tab, NB_IN_PT2TAB);
805 pte2_sync_range(kern_pt2tab, NB_IN_PT2TAB);
806
807 /* Allocate and zero page(s) for kernel L2 page tables. */
808 pt2pg_pa = pmap_preboot_get_pages(NKPT2PG);
809 pt2pg_va = KERNEL_P2V(pt2pg_pa);
810 size = NKPT2PG * PAGE_SIZE;
811 bzero((void*)pt2pg_va, size);
812 pte2_sync_range((pt2_entry_t *)pt2pg_va, size);
813
814 /*
815 * Add a physical memory segment (vm_phys_seg) corresponding to the
816 * preallocated pages for kernel L2 page tables so that vm_page
817 * structures representing these pages will be created. The vm_page
818 * structures are required for promotion of the corresponding kernel
819 * virtual addresses to section mappings.
820 */
821 vm_phys_add_seg(pt2tab_pa, pmap_preboot_get_pages(0));
822
823 /*
824 * Insert allocated L2 page table pages to PT2TAB and make
825 * link to all PT2s in L1 page table. See how kernel_vm_end
826 * is initialized.
827 *
828 * We play simple and safe. So every KVA will have underlaying
829 * L2 page table, even kernel image mapped by sections.
830 */
831 pte2p = kern_pt2tab_entry(KERNBASE);
832 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += PTE2_SIZE)
833 pt2tab_store(pte2p++, PTE2_KPT(pa));
834
835 pte1p = kern_pte1(KERNBASE);
836 for (pa = pt2pg_pa; pa < pt2pg_pa + size; pa += NB_IN_PT2)
837 pte1_store(pte1p++, PTE1_LINK(pa));
838
839 /* Make section mappings for kernel. */
840 l1_attr = ATTR_TO_L1(PTE2_ATTR_DEFAULT);
841 pte1p = kern_pte1(KERNBASE);
842 for (pa = KERNEL_V2P(KERNBASE); pa < last; pa += PTE1_SIZE)
843 pte1_store(pte1p++, PTE1_KERN(pa, PTE1_AP_KRW, l1_attr));
844
845 /*
846 * Get free and aligned space for PT2MAP and make L1 page table links
847 * to L2 page tables held in PT2TAB.
848 *
849 * Note that pages holding PT2s are stored in PT2TAB as pt2_entry_t
850 * descriptors and PT2TAB page(s) itself is(are) used as PT2s. Thus
851 * each entry in PT2TAB maps all PT2s in a page. This implies that
852 * virtual address of PT2MAP must be aligned to NPT2_IN_PG * PTE1_SIZE.
853 */
854 PT2MAP = (pt2_entry_t *)(KERNBASE - PT2MAP_SIZE);
855 pte1p = kern_pte1((vm_offset_t)PT2MAP);
856 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
857 pte1_store(pte1p++, PTE1_LINK(pa));
858 }
859
860 /*
861 * Store PT2TAB in PT2TAB itself, i.e. self reference mapping.
862 * Each pmap will hold own PT2TAB, so the mapping should be not global.
863 */
864 pte2p = kern_pt2tab_entry((vm_offset_t)PT2MAP);
865 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
866 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
867 }
868
869 /*
870 * Choose correct L2 page table and make mappings for allocations
871 * made herein which replaces temporary locore.S mappings after a while.
872 * Note that PT2MAP cannot be used until we switch to kern_pt1.
873 *
874 * Note, that these allocations started aligned on 1M section and
875 * kernel PT1 was allocated first. Making of mappings must follow
876 * order of physical allocations as we've used KERNEL_P2V() macro
877 * for virtual addresses resolution.
878 */
879 pte2p = kern_pt2tab_entry((vm_offset_t)kern_pt1);
880 pt2pg_va = KERNEL_P2V(pte2_pa(pte2_load(pte2p)));
881
882 pte2p = page_pt2(pt2pg_va, pte1_index((vm_offset_t)kern_pt1));
883
884 /* Make mapping for kernel L1 page table. */
885 for (pa = base_pt1, i = 0; i < NPG_IN_PT1; i++, pa += PTE2_SIZE)
886 pte2_store(pte2p++, PTE2_KPT(pa));
887
888 /* Make mapping for kernel PT2TAB. */
889 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE)
890 pte2_store(pte2p++, PTE2_KPT(pa));
891
892 /* Finally, switch from 'boot_pt1' to 'kern_pt1'. */
893 pmap_kern_ttb = base_pt1 | ttb_flags;
894 cpuinfo_reinit_mmu(pmap_kern_ttb);
895 /*
896 * Initialize the first available KVA. As kernel image is mapped by
897 * sections, we are leaving some gap behind.
898 */
899 virtual_avail = (vm_offset_t)kern_pt2tab + NPG_IN_PT2TAB * PAGE_SIZE;
900 }
901
902 /*
903 * Setup L2 page table page for given KVA.
904 * Used in pre-bootstrap epoch.
905 *
906 * Note that we have allocated NKPT2PG pages for L2 page tables in advance
907 * and used them for mapping KVA starting from KERNBASE. However, this is not
908 * enough. Vectors and devices need L2 page tables too. Note that they are
909 * even above VM_MAX_KERNEL_ADDRESS.
910 */
911 static __inline vm_paddr_t
pmap_preboot_pt2pg_setup(vm_offset_t va)912 pmap_preboot_pt2pg_setup(vm_offset_t va)
913 {
914 pt2_entry_t *pte2p, pte2;
915 vm_paddr_t pt2pg_pa;
916
917 /* Get associated entry in PT2TAB. */
918 pte2p = kern_pt2tab_entry(va);
919
920 /* Just return, if PT2s page exists already. */
921 pte2 = pt2tab_load(pte2p);
922 if (pte2_is_valid(pte2))
923 return (pte2_pa(pte2));
924
925 KASSERT(va >= VM_MAX_KERNEL_ADDRESS,
926 ("%s: NKPT2PG too small", __func__));
927
928 /*
929 * Allocate page for PT2s and insert it to PT2TAB.
930 * In other words, map it into PT2MAP space.
931 */
932 pt2pg_pa = pmap_preboot_get_pages(1);
933 pt2tab_store(pte2p, PTE2_KPT(pt2pg_pa));
934
935 /* Zero all PT2s in allocated page. */
936 bzero((void*)pt2map_pt2pg(va), PAGE_SIZE);
937 pte2_sync_range((pt2_entry_t *)pt2map_pt2pg(va), PAGE_SIZE);
938
939 return (pt2pg_pa);
940 }
941
942 /*
943 * Setup L2 page table for given KVA.
944 * Used in pre-bootstrap epoch.
945 */
946 static void
pmap_preboot_pt2_setup(vm_offset_t va)947 pmap_preboot_pt2_setup(vm_offset_t va)
948 {
949 pt1_entry_t *pte1p;
950 vm_paddr_t pt2pg_pa, pt2_pa;
951
952 /* Setup PT2's page. */
953 pt2pg_pa = pmap_preboot_pt2pg_setup(va);
954 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(va));
955
956 /* Insert PT2 to PT1. */
957 pte1p = kern_pte1(va);
958 pte1_store(pte1p, PTE1_LINK(pt2_pa));
959 }
960
961 /*
962 * Get L2 page entry associated with given KVA.
963 * Used in pre-bootstrap epoch.
964 */
965 static __inline pt2_entry_t*
pmap_preboot_vtopte2(vm_offset_t va)966 pmap_preboot_vtopte2(vm_offset_t va)
967 {
968 pt1_entry_t *pte1p;
969
970 /* Setup PT2 if needed. */
971 pte1p = kern_pte1(va);
972 if (!pte1_is_valid(pte1_load(pte1p))) /* XXX - sections ?! */
973 pmap_preboot_pt2_setup(va);
974
975 return (pt2map_entry(va));
976 }
977
978 /*
979 * Pre-bootstrap epoch page(s) mapping(s).
980 */
981 void
pmap_preboot_map_pages(vm_paddr_t pa,vm_offset_t va,u_int num)982 pmap_preboot_map_pages(vm_paddr_t pa, vm_offset_t va, u_int num)
983 {
984 u_int i;
985 pt2_entry_t *pte2p;
986
987 /* Map all the pages. */
988 for (i = 0; i < num; i++) {
989 pte2p = pmap_preboot_vtopte2(va);
990 pte2_store(pte2p, PTE2_KRW(pa));
991 va += PAGE_SIZE;
992 pa += PAGE_SIZE;
993 }
994 }
995
996 /*
997 * Pre-bootstrap epoch virtual space alocator.
998 */
999 vm_offset_t
pmap_preboot_reserve_pages(u_int num)1000 pmap_preboot_reserve_pages(u_int num)
1001 {
1002 u_int i;
1003 vm_offset_t start, va;
1004 pt2_entry_t *pte2p;
1005
1006 /* Allocate virtual space. */
1007 start = va = virtual_avail;
1008 virtual_avail += num * PAGE_SIZE;
1009
1010 /* Zero the mapping. */
1011 for (i = 0; i < num; i++) {
1012 pte2p = pmap_preboot_vtopte2(va);
1013 pte2_store(pte2p, 0);
1014 va += PAGE_SIZE;
1015 }
1016
1017 return (start);
1018 }
1019
1020 /*
1021 * Pre-bootstrap epoch page(s) allocation and mapping(s).
1022 */
1023 vm_offset_t
pmap_preboot_get_vpages(u_int num)1024 pmap_preboot_get_vpages(u_int num)
1025 {
1026 vm_paddr_t pa;
1027 vm_offset_t va;
1028
1029 /* Allocate physical page(s). */
1030 pa = pmap_preboot_get_pages(num);
1031
1032 /* Allocate virtual space. */
1033 va = virtual_avail;
1034 virtual_avail += num * PAGE_SIZE;
1035
1036 /* Map and zero all. */
1037 pmap_preboot_map_pages(pa, va, num);
1038 bzero((void *)va, num * PAGE_SIZE);
1039
1040 return (va);
1041 }
1042
1043 /*
1044 * Pre-bootstrap epoch page mapping(s) with attributes.
1045 */
1046 void
pmap_preboot_map_attr(vm_paddr_t pa,vm_offset_t va,vm_size_t size,vm_prot_t prot,vm_memattr_t attr)1047 pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
1048 vm_prot_t prot, vm_memattr_t attr)
1049 {
1050 u_int num;
1051 u_int l1_attr, l1_prot, l2_prot, l2_attr;
1052 pt1_entry_t *pte1p;
1053 pt2_entry_t *pte2p;
1054
1055 l2_prot = prot & VM_PROT_WRITE ? PTE2_AP_KRW : PTE2_AP_KR;
1056 l2_prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1057 l2_attr = vm_memattr_to_pte2(attr);
1058 l1_prot = ATTR_TO_L1(l2_prot);
1059 l1_attr = ATTR_TO_L1(l2_attr);
1060
1061 /* Map all the pages. */
1062 num = round_page(size);
1063 while (num > 0) {
1064 if ((((va | pa) & PTE1_OFFSET) == 0) && (num >= PTE1_SIZE)) {
1065 pte1p = kern_pte1(va);
1066 pte1_store(pte1p, PTE1_KERN(pa, l1_prot, l1_attr));
1067 va += PTE1_SIZE;
1068 pa += PTE1_SIZE;
1069 num -= PTE1_SIZE;
1070 } else {
1071 pte2p = pmap_preboot_vtopte2(va);
1072 pte2_store(pte2p, PTE2_KERN(pa, l2_prot, l2_attr));
1073 va += PAGE_SIZE;
1074 pa += PAGE_SIZE;
1075 num -= PAGE_SIZE;
1076 }
1077 }
1078 }
1079
1080 /*
1081 * Extract from the kernel page table the physical address
1082 * that is mapped by the given virtual address "va".
1083 */
1084 vm_paddr_t
pmap_kextract(vm_offset_t va)1085 pmap_kextract(vm_offset_t va)
1086 {
1087 vm_paddr_t pa;
1088 pt1_entry_t pte1;
1089 pt2_entry_t pte2;
1090
1091 pte1 = pte1_load(kern_pte1(va));
1092 if (pte1_is_section(pte1)) {
1093 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1094 } else if (pte1_is_link(pte1)) {
1095 /*
1096 * We should beware of concurrent promotion that changes
1097 * pte1 at this point. However, it's not a problem as PT2
1098 * page is preserved by promotion in PT2TAB. So even if
1099 * it happens, using of PT2MAP is still safe.
1100 *
1101 * QQQ: However, concurrent removing is a problem which
1102 * ends in abort on PT2MAP space. Locking must be used
1103 * to deal with this.
1104 */
1105 pte2 = pte2_load(pt2map_entry(va));
1106 pa = pte2_pa(pte2) | (va & PTE2_OFFSET);
1107 }
1108 else {
1109 panic("%s: va %#x pte1 %#x", __func__, va, pte1);
1110 }
1111 return (pa);
1112 }
1113
1114 /*
1115 * Extract from the kernel page table the physical address
1116 * that is mapped by the given virtual address "va". Also
1117 * return L2 page table entry which maps the address.
1118 *
1119 * This is only intended to be used for panic dumps.
1120 */
1121 vm_paddr_t
pmap_dump_kextract(vm_offset_t va,pt2_entry_t * pte2p)1122 pmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p)
1123 {
1124 vm_paddr_t pa;
1125 pt1_entry_t pte1;
1126 pt2_entry_t pte2;
1127
1128 pte1 = pte1_load(kern_pte1(va));
1129 if (pte1_is_section(pte1)) {
1130 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1131 pte2 = pa | ATTR_TO_L2(pte1) | PTE2_V;
1132 } else if (pte1_is_link(pte1)) {
1133 pte2 = pte2_load(pt2map_entry(va));
1134 pa = pte2_pa(pte2);
1135 } else {
1136 pte2 = 0;
1137 pa = 0;
1138 }
1139 if (pte2p != NULL)
1140 *pte2p = pte2;
1141 return (pa);
1142 }
1143
1144 /*****************************************************************************
1145 *
1146 * PMAP second stage initialization and utility functions
1147 * for bootstrap epoch.
1148 *
1149 * After pmap_bootstrap() is called, the following functions for
1150 * mappings can be used:
1151 *
1152 * void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
1153 * void pmap_kremove(vm_offset_t va);
1154 * vm_offset_t pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1155 * int prot);
1156 *
1157 * NOTE: This is not SMP coherent stage. And physical page allocation is not
1158 * allowed during this stage.
1159 *
1160 *****************************************************************************/
1161
1162 /*
1163 * Initialize kernel PMAP locks and lists, kernel_pmap itself, and
1164 * reserve various virtual spaces for temporary mappings.
1165 */
1166 void
pmap_bootstrap(vm_offset_t firstaddr)1167 pmap_bootstrap(vm_offset_t firstaddr)
1168 {
1169 pt2_entry_t *unused __unused;
1170 struct pcpu *pc;
1171
1172 /*
1173 * Initialize the kernel pmap (which is statically allocated).
1174 */
1175 PMAP_LOCK_INIT(kernel_pmap);
1176 kernel_l1pa = (vm_paddr_t)kern_pt1; /* for libkvm */
1177 kernel_pmap->pm_pt1 = kern_pt1;
1178 kernel_pmap->pm_pt2tab = kern_pt2tab;
1179 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1180 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1181
1182 /*
1183 * Initialize the global pv list lock.
1184 */
1185 rw_init(&pvh_global_lock, "pmap pv global");
1186
1187 LIST_INIT(&allpmaps);
1188
1189 /*
1190 * Request a spin mutex so that changes to allpmaps cannot be
1191 * preempted by smp_rendezvous_cpus().
1192 */
1193 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
1194 mtx_lock_spin(&allpmaps_lock);
1195 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
1196 mtx_unlock_spin(&allpmaps_lock);
1197
1198 /*
1199 * Reserve some special page table entries/VA space for temporary
1200 * mapping of pages.
1201 */
1202 #define SYSMAP(c, p, v, n) do { \
1203 v = (c)pmap_preboot_reserve_pages(n); \
1204 p = pt2map_entry((vm_offset_t)v); \
1205 } while (0)
1206
1207 /*
1208 * Local CMAP1/CMAP2 are used for zeroing and copying pages.
1209 * Local CMAP2 is also used for data cache cleaning.
1210 */
1211 pc = get_pcpu();
1212 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1213 SYSMAP(caddr_t, pc->pc_cmap1_pte2p, pc->pc_cmap1_addr, 1);
1214 SYSMAP(caddr_t, pc->pc_cmap2_pte2p, pc->pc_cmap2_addr, 1);
1215 SYSMAP(vm_offset_t, pc->pc_qmap_pte2p, pc->pc_qmap_addr, 1);
1216
1217 /*
1218 * Crashdump maps.
1219 */
1220 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS);
1221
1222 /*
1223 * _tmppt is used for reading arbitrary physical pages via /dev/mem.
1224 */
1225 SYSMAP(caddr_t, unused, _tmppt, 1);
1226
1227 /*
1228 * PADDR1 and PADDR2 are used by pmap_pte2_quick() and pmap_pte2(),
1229 * respectively. PADDR3 is used by pmap_pte2_ddb().
1230 */
1231 SYSMAP(pt2_entry_t *, PMAP1, PADDR1, 1);
1232 SYSMAP(pt2_entry_t *, PMAP2, PADDR2, 1);
1233 #ifdef DDB
1234 SYSMAP(pt2_entry_t *, PMAP3, PADDR3, 1);
1235 #endif
1236 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
1237
1238 /*
1239 * Note that in very short time in initarm(), we are going to
1240 * initialize phys_avail[] array and no further page allocation
1241 * can happen after that until vm subsystem will be initialized.
1242 */
1243 kernel_vm_end_new = kernel_vm_end;
1244 virtual_end = vm_max_kernel_address;
1245 }
1246
1247 static void
pmap_init_reserved_pages(void)1248 pmap_init_reserved_pages(void)
1249 {
1250 struct pcpu *pc;
1251 vm_offset_t pages;
1252 int i;
1253
1254 CPU_FOREACH(i) {
1255 pc = pcpu_find(i);
1256 /*
1257 * Skip if the mapping has already been initialized,
1258 * i.e. this is the BSP.
1259 */
1260 if (pc->pc_cmap1_addr != 0)
1261 continue;
1262 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
1263 pages = kva_alloc(PAGE_SIZE * 3);
1264 if (pages == 0)
1265 panic("%s: unable to allocate KVA", __func__);
1266 pc->pc_cmap1_pte2p = pt2map_entry(pages);
1267 pc->pc_cmap2_pte2p = pt2map_entry(pages + PAGE_SIZE);
1268 pc->pc_qmap_pte2p = pt2map_entry(pages + (PAGE_SIZE * 2));
1269 pc->pc_cmap1_addr = (caddr_t)pages;
1270 pc->pc_cmap2_addr = (caddr_t)(pages + PAGE_SIZE);
1271 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
1272 }
1273 }
1274 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
1275
1276 /*
1277 * The function can already be use in second initialization stage.
1278 * As such, the function DOES NOT call pmap_growkernel() where PT2
1279 * allocation can happen. So if used, be sure that PT2 for given
1280 * virtual address is allocated already!
1281 *
1282 * Add a wired page to the kva.
1283 * Note: not SMP coherent.
1284 */
1285 static __inline void
pmap_kenter_prot_attr(vm_offset_t va,vm_paddr_t pa,uint32_t prot,uint32_t attr)1286 pmap_kenter_prot_attr(vm_offset_t va, vm_paddr_t pa, uint32_t prot,
1287 uint32_t attr)
1288 {
1289 pt1_entry_t *pte1p;
1290 pt2_entry_t *pte2p;
1291
1292 pte1p = kern_pte1(va);
1293 if (!pte1_is_valid(pte1_load(pte1p))) { /* XXX - sections ?! */
1294 /*
1295 * This is a very low level function, so PT2 and particularly
1296 * PT2PG associated with given virtual address must be already
1297 * allocated. It's a pain mainly during pmap initialization
1298 * stage. However, called after pmap initialization with
1299 * virtual address not under kernel_vm_end will lead to
1300 * the same misery.
1301 */
1302 if (!pte2_is_valid(pte2_load(kern_pt2tab_entry(va))))
1303 panic("%s: kernel PT2 not allocated!", __func__);
1304 }
1305
1306 pte2p = pt2map_entry(va);
1307 pte2_store(pte2p, PTE2_KERN(pa, prot, attr));
1308 }
1309
1310 PMAP_INLINE void
pmap_kenter(vm_offset_t va,vm_paddr_t pa)1311 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1312 {
1313
1314 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT);
1315 }
1316
1317 /*
1318 * Remove a page from the kernel pagetables.
1319 * Note: not SMP coherent.
1320 */
1321 PMAP_INLINE void
pmap_kremove(vm_offset_t va)1322 pmap_kremove(vm_offset_t va)
1323 {
1324 pt1_entry_t *pte1p;
1325 pt2_entry_t *pte2p;
1326
1327 pte1p = kern_pte1(va);
1328 if (pte1_is_section(pte1_load(pte1p))) {
1329 pte1_clear(pte1p);
1330 } else {
1331 pte2p = pt2map_entry(va);
1332 pte2_clear(pte2p);
1333 }
1334 }
1335
1336 /*
1337 * Share new kernel PT2PG with all pmaps.
1338 * The caller is responsible for maintaining TLB consistency.
1339 */
1340 static void
pmap_kenter_pt2tab(vm_offset_t va,pt2_entry_t npte2)1341 pmap_kenter_pt2tab(vm_offset_t va, pt2_entry_t npte2)
1342 {
1343 pmap_t pmap;
1344 pt2_entry_t *pte2p;
1345
1346 mtx_lock_spin(&allpmaps_lock);
1347 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1348 pte2p = pmap_pt2tab_entry(pmap, va);
1349 pt2tab_store(pte2p, npte2);
1350 }
1351 mtx_unlock_spin(&allpmaps_lock);
1352 }
1353
1354 /*
1355 * Share new kernel PTE1 with all pmaps.
1356 * The caller is responsible for maintaining TLB consistency.
1357 */
1358 static void
pmap_kenter_pte1(vm_offset_t va,pt1_entry_t npte1)1359 pmap_kenter_pte1(vm_offset_t va, pt1_entry_t npte1)
1360 {
1361 pmap_t pmap;
1362 pt1_entry_t *pte1p;
1363
1364 mtx_lock_spin(&allpmaps_lock);
1365 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1366 pte1p = pmap_pte1(pmap, va);
1367 pte1_store(pte1p, npte1);
1368 }
1369 mtx_unlock_spin(&allpmaps_lock);
1370 }
1371
1372 /*
1373 * Used to map a range of physical addresses into kernel
1374 * virtual address space.
1375 *
1376 * The value passed in '*virt' is a suggested virtual address for
1377 * the mapping. Architectures which can support a direct-mapped
1378 * physical to virtual region can return the appropriate address
1379 * within that region, leaving '*virt' unchanged. Other
1380 * architectures should map the pages starting at '*virt' and
1381 * update '*virt' with the first usable address after the mapped
1382 * region.
1383 *
1384 * NOTE: Read the comments above pmap_kenter_prot_attr() as
1385 * the function is used herein!
1386 */
1387 vm_offset_t
pmap_map(vm_offset_t * virt,vm_paddr_t start,vm_paddr_t end,int prot)1388 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1389 {
1390 vm_offset_t va, sva;
1391 vm_paddr_t pte1_offset;
1392 pt1_entry_t npte1;
1393 uint32_t l1prot, l2prot;
1394 uint32_t l1attr, l2attr;
1395
1396 PDEBUG(1, printf("%s: virt = %#x, start = %#x, end = %#x (size = %#x),"
1397 " prot = %d\n", __func__, *virt, start, end, end - start, prot));
1398
1399 l2prot = (prot & VM_PROT_WRITE) ? PTE2_AP_KRW : PTE2_AP_KR;
1400 l2prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
1401 l1prot = ATTR_TO_L1(l2prot);
1402
1403 l2attr = PTE2_ATTR_DEFAULT;
1404 l1attr = ATTR_TO_L1(l2attr);
1405
1406 va = *virt;
1407 /*
1408 * Does the physical address range's size and alignment permit at
1409 * least one section mapping to be created?
1410 */
1411 pte1_offset = start & PTE1_OFFSET;
1412 if ((end - start) - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) >=
1413 PTE1_SIZE) {
1414 /*
1415 * Increase the starting virtual address so that its alignment
1416 * does not preclude the use of section mappings.
1417 */
1418 if ((va & PTE1_OFFSET) < pte1_offset)
1419 va = pte1_trunc(va) + pte1_offset;
1420 else if ((va & PTE1_OFFSET) > pte1_offset)
1421 va = pte1_roundup(va) + pte1_offset;
1422 }
1423 sva = va;
1424 while (start < end) {
1425 if ((start & PTE1_OFFSET) == 0 && end - start >= PTE1_SIZE) {
1426 KASSERT((va & PTE1_OFFSET) == 0,
1427 ("%s: misaligned va %#x", __func__, va));
1428 npte1 = PTE1_KERN(start, l1prot, l1attr);
1429 pmap_kenter_pte1(va, npte1);
1430 va += PTE1_SIZE;
1431 start += PTE1_SIZE;
1432 } else {
1433 pmap_kenter_prot_attr(va, start, l2prot, l2attr);
1434 va += PAGE_SIZE;
1435 start += PAGE_SIZE;
1436 }
1437 }
1438 tlb_flush_range(sva, va - sva);
1439 *virt = va;
1440 return (sva);
1441 }
1442
1443 /*
1444 * Make a temporary mapping for a physical address.
1445 * This is only intended to be used for panic dumps.
1446 */
1447 void *
pmap_kenter_temporary(vm_paddr_t pa,int i)1448 pmap_kenter_temporary(vm_paddr_t pa, int i)
1449 {
1450 vm_offset_t va;
1451
1452 /* QQQ: 'i' should be less or equal to MAXDUMPPGS. */
1453
1454 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
1455 pmap_kenter(va, pa);
1456 tlb_flush_local(va);
1457 return ((void *)crashdumpmap);
1458 }
1459
1460 /*************************************
1461 *
1462 * TLB & cache maintenance routines.
1463 *
1464 *************************************/
1465
1466 /*
1467 * We inline these within pmap.c for speed.
1468 */
1469 PMAP_INLINE void
pmap_tlb_flush(pmap_t pmap,vm_offset_t va)1470 pmap_tlb_flush(pmap_t pmap, vm_offset_t va)
1471 {
1472
1473 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1474 tlb_flush(va);
1475 }
1476
1477 PMAP_INLINE void
pmap_tlb_flush_range(pmap_t pmap,vm_offset_t sva,vm_size_t size)1478 pmap_tlb_flush_range(pmap_t pmap, vm_offset_t sva, vm_size_t size)
1479 {
1480
1481 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1482 tlb_flush_range(sva, size);
1483 }
1484
1485 /*
1486 * Abuse the pte2 nodes for unmapped kva to thread a kva freelist through.
1487 * Requirements:
1488 * - Must deal with pages in order to ensure that none of the PTE2_* bits
1489 * are ever set, PTE2_V in particular.
1490 * - Assumes we can write to pte2s without pte2_store() atomic ops.
1491 * - Assumes nothing will ever test these addresses for 0 to indicate
1492 * no mapping instead of correctly checking PTE2_V.
1493 * - Assumes a vm_offset_t will fit in a pte2 (true for arm).
1494 * Because PTE2_V is never set, there can be no mappings to invalidate.
1495 */
1496 static vm_offset_t
pmap_pte2list_alloc(vm_offset_t * head)1497 pmap_pte2list_alloc(vm_offset_t *head)
1498 {
1499 pt2_entry_t *pte2p;
1500 vm_offset_t va;
1501
1502 va = *head;
1503 if (va == 0)
1504 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
1505 pte2p = pt2map_entry(va);
1506 *head = *pte2p;
1507 if (*head & PTE2_V)
1508 panic("%s: va with PTE2_V set!", __func__);
1509 *pte2p = 0;
1510 return (va);
1511 }
1512
1513 static void
pmap_pte2list_free(vm_offset_t * head,vm_offset_t va)1514 pmap_pte2list_free(vm_offset_t *head, vm_offset_t va)
1515 {
1516 pt2_entry_t *pte2p;
1517
1518 if (va & PTE2_V)
1519 panic("%s: freeing va with PTE2_V set!", __func__);
1520 pte2p = pt2map_entry(va);
1521 *pte2p = *head; /* virtual! PTE2_V is 0 though */
1522 *head = va;
1523 }
1524
1525 static void
pmap_pte2list_init(vm_offset_t * head,void * base,int npages)1526 pmap_pte2list_init(vm_offset_t *head, void *base, int npages)
1527 {
1528 int i;
1529 vm_offset_t va;
1530
1531 *head = 0;
1532 for (i = npages - 1; i >= 0; i--) {
1533 va = (vm_offset_t)base + i * PAGE_SIZE;
1534 pmap_pte2list_free(head, va);
1535 }
1536 }
1537
1538 /*****************************************************************************
1539 *
1540 * PMAP third and final stage initialization.
1541 *
1542 * After pmap_init() is called, PMAP subsystem is fully initialized.
1543 *
1544 *****************************************************************************/
1545
1546 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1547 "VM/pmap parameters");
1548
1549 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
1550 "Max number of PV entries");
1551 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
1552 "Page share factor per proc");
1553
1554 static u_long nkpt2pg = NKPT2PG;
1555 SYSCTL_ULONG(_vm_pmap, OID_AUTO, nkpt2pg, CTLFLAG_RD,
1556 &nkpt2pg, 0, "Pre-allocated pages for kernel PT2s");
1557
1558 static int sp_enabled = 1;
1559 SYSCTL_INT(_vm_pmap, OID_AUTO, sp_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
1560 &sp_enabled, 0, "Are large page mappings enabled?");
1561
1562 bool
pmap_ps_enabled(pmap_t pmap __unused)1563 pmap_ps_enabled(pmap_t pmap __unused)
1564 {
1565
1566 return (sp_enabled != 0);
1567 }
1568
1569 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pte1, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1570 "1MB page mapping counters");
1571
1572 static u_long pmap_pte1_demotions;
1573 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, demotions, CTLFLAG_RD,
1574 &pmap_pte1_demotions, 0, "1MB page demotions");
1575
1576 static u_long pmap_pte1_mappings;
1577 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, mappings, CTLFLAG_RD,
1578 &pmap_pte1_mappings, 0, "1MB page mappings");
1579
1580 static u_long pmap_pte1_p_failures;
1581 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, p_failures, CTLFLAG_RD,
1582 &pmap_pte1_p_failures, 0, "1MB page promotion failures");
1583
1584 static u_long pmap_pte1_promotions;
1585 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, promotions, CTLFLAG_RD,
1586 &pmap_pte1_promotions, 0, "1MB page promotions");
1587
1588 static u_long pmap_pte1_kern_demotions;
1589 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_demotions, CTLFLAG_RD,
1590 &pmap_pte1_kern_demotions, 0, "1MB page kernel demotions");
1591
1592 static u_long pmap_pte1_kern_promotions;
1593 SYSCTL_ULONG(_vm_pmap_pte1, OID_AUTO, kern_promotions, CTLFLAG_RD,
1594 &pmap_pte1_kern_promotions, 0, "1MB page kernel promotions");
1595
1596 static __inline ttb_entry_t
pmap_ttb_get(pmap_t pmap)1597 pmap_ttb_get(pmap_t pmap)
1598 {
1599
1600 return (vtophys(pmap->pm_pt1) | ttb_flags);
1601 }
1602
1603 /*
1604 * Initialize a vm_page's machine-dependent fields.
1605 *
1606 * Variations:
1607 * 1. Pages for L2 page tables are always not managed. So, pv_list and
1608 * pt2_wirecount can share same physical space. However, proper
1609 * initialization on a page alloc for page tables and reinitialization
1610 * on the page free must be ensured.
1611 */
1612 void
pmap_page_init(vm_page_t m)1613 pmap_page_init(vm_page_t m)
1614 {
1615
1616 TAILQ_INIT(&m->md.pv_list);
1617 pt2_wirecount_init(m);
1618 m->md.pat_mode = VM_MEMATTR_DEFAULT;
1619 }
1620
1621 /*
1622 * Virtualization for faster way how to zero whole page.
1623 */
1624 static __inline void
pagezero(void * page)1625 pagezero(void *page)
1626 {
1627
1628 bzero(page, PAGE_SIZE);
1629 }
1630
1631 /*
1632 * Zero L2 page table page.
1633 * Use same KVA as in pmap_zero_page().
1634 */
1635 static __inline vm_paddr_t
pmap_pt2pg_zero(vm_page_t m)1636 pmap_pt2pg_zero(vm_page_t m)
1637 {
1638 pt2_entry_t *cmap2_pte2p;
1639 vm_paddr_t pa;
1640 struct pcpu *pc;
1641
1642 pa = VM_PAGE_TO_PHYS(m);
1643
1644 /*
1645 * XXX: For now, we map whole page even if it's already zero,
1646 * to sync it even if the sync is only DSB.
1647 */
1648 sched_pin();
1649 pc = get_pcpu();
1650 cmap2_pte2p = pc->pc_cmap2_pte2p;
1651 mtx_lock(&pc->pc_cmap_lock);
1652 if (pte2_load(cmap2_pte2p) != 0)
1653 panic("%s: CMAP2 busy", __func__);
1654 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
1655 vm_page_pte2_attr(m)));
1656 /* Even VM_ALLOC_ZERO request is only advisory. */
1657 if ((m->flags & PG_ZERO) == 0)
1658 pagezero(pc->pc_cmap2_addr);
1659 pte2_sync_range((pt2_entry_t *)pc->pc_cmap2_addr, PAGE_SIZE);
1660 pte2_clear(cmap2_pte2p);
1661 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
1662
1663 /*
1664 * Unpin the thread before releasing the lock. Otherwise the thread
1665 * could be rescheduled while still bound to the current CPU, only
1666 * to unpin itself immediately upon resuming execution.
1667 */
1668 sched_unpin();
1669 mtx_unlock(&pc->pc_cmap_lock);
1670
1671 return (pa);
1672 }
1673
1674 /*
1675 * Init just allocated page as L2 page table(s) holder
1676 * and return its physical address.
1677 */
1678 static __inline vm_paddr_t
pmap_pt2pg_init(pmap_t pmap,vm_offset_t va,vm_page_t m)1679 pmap_pt2pg_init(pmap_t pmap, vm_offset_t va, vm_page_t m)
1680 {
1681 vm_paddr_t pa;
1682 pt2_entry_t *pte2p;
1683
1684 /* Check page attributes. */
1685 if (m->md.pat_mode != pt_memattr)
1686 pmap_page_set_memattr(m, pt_memattr);
1687
1688 /* Zero page and init wire counts. */
1689 pa = pmap_pt2pg_zero(m);
1690 pt2_wirecount_init(m);
1691
1692 /*
1693 * Map page to PT2MAP address space for given pmap.
1694 * Note that PT2MAP space is shared with all pmaps.
1695 */
1696 if (pmap == kernel_pmap)
1697 pmap_kenter_pt2tab(va, PTE2_KPT(pa));
1698 else {
1699 pte2p = pmap_pt2tab_entry(pmap, va);
1700 pt2tab_store(pte2p, PTE2_KPT_NG(pa));
1701 }
1702
1703 return (pa);
1704 }
1705
1706 /*
1707 * Initialize the pmap module.
1708 *
1709 * Called by vm_mem_init(), to initialize any structures that the pmap system
1710 * needs to map virtual memory.
1711 */
1712 void
pmap_init(void)1713 pmap_init(void)
1714 {
1715 vm_size_t s;
1716 pt2_entry_t *pte2p, pte2;
1717 u_int i, pte1_idx, pv_npg;
1718
1719 /*
1720 * Initialize the vm page array entries for kernel pmap's
1721 * L2 page table pages allocated in advance.
1722 */
1723 pte1_idx = pte1_index(KERNBASE - PT2MAP_SIZE);
1724 pte2p = kern_pt2tab_entry(KERNBASE - PT2MAP_SIZE);
1725 for (i = 0; i < nkpt2pg + NPG_IN_PT2TAB; i++, pte2p++) {
1726 vm_paddr_t pa;
1727 vm_page_t m;
1728
1729 pte2 = pte2_load(pte2p);
1730 KASSERT(pte2_is_valid(pte2), ("%s: no valid entry", __func__));
1731
1732 pa = pte2_pa(pte2);
1733 m = PHYS_TO_VM_PAGE(pa);
1734 KASSERT(m >= vm_page_array &&
1735 m < &vm_page_array[vm_page_array_size],
1736 ("%s: L2 page table page is out of range", __func__));
1737
1738 m->pindex = pte1_idx;
1739 m->phys_addr = pa;
1740 pte1_idx += NPT2_IN_PG;
1741 }
1742
1743 /*
1744 * Initialize the address space (zone) for the pv entries. Set a
1745 * high water mark so that the system can recover from excessive
1746 * numbers of pv entries.
1747 */
1748 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1749 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1750 TUNABLE_INT_FETCH("vm.pmap.pv_entry_max", &pv_entry_max);
1751 pv_entry_max = roundup(pv_entry_max, _NPCPV);
1752 pv_entry_high_water = 9 * (pv_entry_max / 10);
1753
1754 /*
1755 * Are large page mappings enabled?
1756 */
1757 TUNABLE_INT_FETCH("vm.pmap.sp_enabled", &sp_enabled);
1758 if (sp_enabled) {
1759 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1760 ("%s: can't assign to pagesizes[1]", __func__));
1761 pagesizes[1] = PTE1_SIZE;
1762 }
1763
1764 /*
1765 * Calculate the size of the pv head table for sections.
1766 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1767 * Note that the table is only for sections which could be promoted.
1768 */
1769 first_managed_pa = pte1_trunc(vm_phys_segs[0].start);
1770 pv_npg = (pte1_trunc(vm_phys_segs[vm_phys_nsegs - 1].end - PAGE_SIZE)
1771 - first_managed_pa) / PTE1_SIZE + 1;
1772
1773 /*
1774 * Allocate memory for the pv head table for sections.
1775 */
1776 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1777 s = round_page(s);
1778 pv_table = kmem_malloc(s, M_WAITOK | M_ZERO);
1779 for (i = 0; i < pv_npg; i++)
1780 TAILQ_INIT(&pv_table[i].pv_list);
1781
1782 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1783 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1784 if (pv_chunkbase == NULL)
1785 panic("%s: not enough kvm for pv chunks", __func__);
1786 pmap_pte2list_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1787 }
1788
1789 /*
1790 * Add a list of wired pages to the kva
1791 * this routine is only used for temporary
1792 * kernel mappings that do not need to have
1793 * page modification or references recorded.
1794 * Note that old mappings are simply written
1795 * over. The page *must* be wired.
1796 * Note: SMP coherent. Uses a ranged shootdown IPI.
1797 */
1798 void
pmap_qenter(vm_offset_t sva,vm_page_t * ma,int count)1799 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1800 {
1801 u_int anychanged;
1802 pt2_entry_t *epte2p, *pte2p, pte2;
1803 vm_page_t m;
1804 vm_paddr_t pa;
1805
1806 anychanged = 0;
1807 pte2p = pt2map_entry(sva);
1808 epte2p = pte2p + count;
1809 while (pte2p < epte2p) {
1810 m = *ma++;
1811 pa = VM_PAGE_TO_PHYS(m);
1812 pte2 = pte2_load(pte2p);
1813 if ((pte2_pa(pte2) != pa) ||
1814 (pte2_attr(pte2) != vm_page_pte2_attr(m))) {
1815 anychanged++;
1816 pte2_store(pte2p, PTE2_KERN(pa, PTE2_AP_KRW,
1817 vm_page_pte2_attr(m)));
1818 }
1819 pte2p++;
1820 }
1821 if (__predict_false(anychanged))
1822 tlb_flush_range(sva, count * PAGE_SIZE);
1823 }
1824
1825 /*
1826 * This routine tears out page mappings from the
1827 * kernel -- it is meant only for temporary mappings.
1828 * Note: SMP coherent. Uses a ranged shootdown IPI.
1829 */
1830 void
pmap_qremove(vm_offset_t sva,int count)1831 pmap_qremove(vm_offset_t sva, int count)
1832 {
1833 vm_offset_t va;
1834
1835 va = sva;
1836 while (count-- > 0) {
1837 pmap_kremove(va);
1838 va += PAGE_SIZE;
1839 }
1840 tlb_flush_range(sva, va - sva);
1841 }
1842
1843 /*
1844 * Are we current address space or kernel?
1845 */
1846 static __inline int
pmap_is_current(pmap_t pmap)1847 pmap_is_current(pmap_t pmap)
1848 {
1849
1850 return (pmap == kernel_pmap ||
1851 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace)));
1852 }
1853
1854 /*
1855 * If the given pmap is not the current or kernel pmap, the returned
1856 * pte2 must be released by passing it to pmap_pte2_release().
1857 */
1858 static pt2_entry_t *
pmap_pte2(pmap_t pmap,vm_offset_t va)1859 pmap_pte2(pmap_t pmap, vm_offset_t va)
1860 {
1861 pt1_entry_t pte1;
1862 vm_paddr_t pt2pg_pa;
1863
1864 pte1 = pte1_load(pmap_pte1(pmap, va));
1865 if (pte1_is_section(pte1))
1866 panic("%s: attempt to map PTE1", __func__);
1867 if (pte1_is_link(pte1)) {
1868 /* Are we current address space or kernel? */
1869 if (pmap_is_current(pmap))
1870 return (pt2map_entry(va));
1871 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1872 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1873 mtx_lock(&PMAP2mutex);
1874 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
1875 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
1876 tlb_flush((vm_offset_t)PADDR2);
1877 }
1878 return (PADDR2 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1879 }
1880 return (NULL);
1881 }
1882
1883 /*
1884 * Releases a pte2 that was obtained from pmap_pte2().
1885 * Be prepared for the pte2p being NULL.
1886 */
1887 static __inline void
pmap_pte2_release(pt2_entry_t * pte2p)1888 pmap_pte2_release(pt2_entry_t *pte2p)
1889 {
1890
1891 if ((pt2_entry_t *)(trunc_page((vm_offset_t)pte2p)) == PADDR2) {
1892 mtx_unlock(&PMAP2mutex);
1893 }
1894 }
1895
1896 /*
1897 * Super fast pmap_pte2 routine best used when scanning
1898 * the pv lists. This eliminates many coarse-grained
1899 * invltlb calls. Note that many of the pv list
1900 * scans are across different pmaps. It is very wasteful
1901 * to do an entire tlb flush for checking a single mapping.
1902 *
1903 * If the given pmap is not the current pmap, pvh_global_lock
1904 * must be held and curthread pinned to a CPU.
1905 */
1906 static pt2_entry_t *
pmap_pte2_quick(pmap_t pmap,vm_offset_t va)1907 pmap_pte2_quick(pmap_t pmap, vm_offset_t va)
1908 {
1909 pt1_entry_t pte1;
1910 vm_paddr_t pt2pg_pa;
1911
1912 pte1 = pte1_load(pmap_pte1(pmap, va));
1913 if (pte1_is_section(pte1))
1914 panic("%s: attempt to map PTE1", __func__);
1915 if (pte1_is_link(pte1)) {
1916 /* Are we current address space or kernel? */
1917 if (pmap_is_current(pmap))
1918 return (pt2map_entry(va));
1919 rw_assert(&pvh_global_lock, RA_WLOCKED);
1920 KASSERT(curthread->td_pinned > 0,
1921 ("%s: curthread not pinned", __func__));
1922 /* Note that L2 page table size is not equal to PAGE_SIZE. */
1923 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
1924 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
1925 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
1926 #ifdef SMP
1927 PMAP1cpu = PCPU_GET(cpuid);
1928 #endif
1929 tlb_flush_local((vm_offset_t)PADDR1);
1930 PMAP1changed++;
1931 } else
1932 #ifdef SMP
1933 if (PMAP1cpu != PCPU_GET(cpuid)) {
1934 PMAP1cpu = PCPU_GET(cpuid);
1935 tlb_flush_local((vm_offset_t)PADDR1);
1936 PMAP1changedcpu++;
1937 } else
1938 #endif
1939 PMAP1unchanged++;
1940 return (PADDR1 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
1941 }
1942 return (NULL);
1943 }
1944
1945 /*
1946 * Routine: pmap_extract
1947 * Function:
1948 * Extract the physical page address associated
1949 * with the given map/virtual_address pair.
1950 */
1951 vm_paddr_t
pmap_extract(pmap_t pmap,vm_offset_t va)1952 pmap_extract(pmap_t pmap, vm_offset_t va)
1953 {
1954 vm_paddr_t pa;
1955 pt1_entry_t pte1;
1956 pt2_entry_t *pte2p;
1957
1958 PMAP_LOCK(pmap);
1959 pte1 = pte1_load(pmap_pte1(pmap, va));
1960 if (pte1_is_section(pte1))
1961 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1962 else if (pte1_is_link(pte1)) {
1963 pte2p = pmap_pte2(pmap, va);
1964 pa = pte2_pa(pte2_load(pte2p)) | (va & PTE2_OFFSET);
1965 pmap_pte2_release(pte2p);
1966 } else
1967 pa = 0;
1968 PMAP_UNLOCK(pmap);
1969 return (pa);
1970 }
1971
1972 /*
1973 * Routine: pmap_extract_and_hold
1974 * Function:
1975 * Atomically extract and hold the physical page
1976 * with the given pmap and virtual address pair
1977 * if that mapping permits the given protection.
1978 */
1979 vm_page_t
pmap_extract_and_hold(pmap_t pmap,vm_offset_t va,vm_prot_t prot)1980 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1981 {
1982 vm_paddr_t pa;
1983 pt1_entry_t pte1;
1984 pt2_entry_t pte2, *pte2p;
1985 vm_page_t m;
1986
1987 m = NULL;
1988 PMAP_LOCK(pmap);
1989 pte1 = pte1_load(pmap_pte1(pmap, va));
1990 if (pte1_is_section(pte1)) {
1991 if (!(pte1 & PTE1_RO) || !(prot & VM_PROT_WRITE)) {
1992 pa = pte1_pa(pte1) | (va & PTE1_OFFSET);
1993 m = PHYS_TO_VM_PAGE(pa);
1994 if (!vm_page_wire_mapped(m))
1995 m = NULL;
1996 }
1997 } else if (pte1_is_link(pte1)) {
1998 pte2p = pmap_pte2(pmap, va);
1999 pte2 = pte2_load(pte2p);
2000 pmap_pte2_release(pte2p);
2001 if (pte2_is_valid(pte2) &&
2002 (!(pte2 & PTE2_RO) || !(prot & VM_PROT_WRITE))) {
2003 pa = pte2_pa(pte2);
2004 m = PHYS_TO_VM_PAGE(pa);
2005 if (!vm_page_wire_mapped(m))
2006 m = NULL;
2007 }
2008 }
2009 PMAP_UNLOCK(pmap);
2010 return (m);
2011 }
2012
2013 /*
2014 * Grow the number of kernel L2 page table entries, if needed.
2015 */
2016 void
pmap_growkernel(vm_offset_t addr)2017 pmap_growkernel(vm_offset_t addr)
2018 {
2019 vm_page_t m;
2020 vm_paddr_t pt2pg_pa, pt2_pa;
2021 pt1_entry_t pte1;
2022 pt2_entry_t pte2;
2023
2024 PDEBUG(1, printf("%s: addr = %#x\n", __func__, addr));
2025 /*
2026 * All the time kernel_vm_end is first KVA for which underlying
2027 * L2 page table is either not allocated or linked from L1 page table
2028 * (not considering sections). Except for two possible cases:
2029 *
2030 * (1) in the very beginning as long as pmap_growkernel() was
2031 * not called, it could be first unused KVA (which is not
2032 * rounded up to PTE1_SIZE),
2033 *
2034 * (2) when all KVA space is mapped and vm_map_max(kernel_map)
2035 * address is not rounded up to PTE1_SIZE. (For example,
2036 * it could be 0xFFFFFFFF.)
2037 */
2038 kernel_vm_end = pte1_roundup(kernel_vm_end);
2039 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2040 addr = roundup2(addr, PTE1_SIZE);
2041 if (addr - 1 >= vm_map_max(kernel_map))
2042 addr = vm_map_max(kernel_map);
2043 while (kernel_vm_end < addr) {
2044 pte1 = pte1_load(kern_pte1(kernel_vm_end));
2045 if (pte1_is_valid(pte1)) {
2046 kernel_vm_end += PTE1_SIZE;
2047 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2048 kernel_vm_end = vm_map_max(kernel_map);
2049 break;
2050 }
2051 continue;
2052 }
2053
2054 /*
2055 * kernel_vm_end_new is used in pmap_pinit() when kernel
2056 * mappings are entered to new pmap all at once to avoid race
2057 * between pmap_kenter_pte1() and kernel_vm_end increase.
2058 * The same aplies to pmap_kenter_pt2tab().
2059 */
2060 kernel_vm_end_new = kernel_vm_end + PTE1_SIZE;
2061
2062 pte2 = pt2tab_load(kern_pt2tab_entry(kernel_vm_end));
2063 if (!pte2_is_valid(pte2)) {
2064 /*
2065 * Install new PT2s page into kernel PT2TAB.
2066 */
2067 m = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT |
2068 VM_ALLOC_NOFREE | VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2069 if (m == NULL)
2070 panic("%s: no memory to grow kernel", __func__);
2071 m->pindex = pte1_index(kernel_vm_end) & ~PT2PG_MASK;
2072
2073 /*
2074 * QQQ: To link all new L2 page tables from L1 page
2075 * table now and so pmap_kenter_pte1() them
2076 * at once together with pmap_kenter_pt2tab()
2077 * could be nice speed up. However,
2078 * pmap_growkernel() does not happen so often...
2079 * QQQ: The other TTBR is another option.
2080 */
2081 pt2pg_pa = pmap_pt2pg_init(kernel_pmap, kernel_vm_end,
2082 m);
2083 } else
2084 pt2pg_pa = pte2_pa(pte2);
2085
2086 pt2_pa = page_pt2pa(pt2pg_pa, pte1_index(kernel_vm_end));
2087 pmap_kenter_pte1(kernel_vm_end, PTE1_LINK(pt2_pa));
2088
2089 kernel_vm_end = kernel_vm_end_new;
2090 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2091 kernel_vm_end = vm_map_max(kernel_map);
2092 break;
2093 }
2094 }
2095 }
2096
2097 static int
kvm_size(SYSCTL_HANDLER_ARGS)2098 kvm_size(SYSCTL_HANDLER_ARGS)
2099 {
2100 unsigned long ksize = vm_max_kernel_address - KERNBASE;
2101
2102 return (sysctl_handle_long(oidp, &ksize, 0, req));
2103 }
2104 SYSCTL_PROC(_vm, OID_AUTO, kvm_size,
2105 CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 0, 0, kvm_size, "IU",
2106 "Size of KVM");
2107
2108 static int
kvm_free(SYSCTL_HANDLER_ARGS)2109 kvm_free(SYSCTL_HANDLER_ARGS)
2110 {
2111 unsigned long kfree = vm_max_kernel_address - kernel_vm_end;
2112
2113 return (sysctl_handle_long(oidp, &kfree, 0, req));
2114 }
2115 SYSCTL_PROC(_vm, OID_AUTO, kvm_free,
2116 CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 0, 0, kvm_free, "IU",
2117 "Amount of KVM free");
2118
2119 /***********************************************
2120 *
2121 * Pmap allocation/deallocation routines.
2122 *
2123 ***********************************************/
2124
2125 /*
2126 * Initialize the pmap for the swapper process.
2127 */
2128 void
pmap_pinit0(pmap_t pmap)2129 pmap_pinit0(pmap_t pmap)
2130 {
2131 PDEBUG(1, printf("%s: pmap = %p\n", __func__, pmap));
2132
2133 PMAP_LOCK_INIT(pmap);
2134
2135 /*
2136 * Kernel page table directory and pmap stuff around is already
2137 * initialized, we are using it right now and here. So, finish
2138 * only PMAP structures initialization for process0 ...
2139 *
2140 * Since the L1 page table and PT2TAB is shared with the kernel pmap,
2141 * which is already included in the list "allpmaps", this pmap does
2142 * not need to be inserted into that list.
2143 */
2144 pmap->pm_pt1 = kern_pt1;
2145 pmap->pm_pt2tab = kern_pt2tab;
2146 CPU_ZERO(&pmap->pm_active);
2147 PCPU_SET(curpmap, pmap);
2148 TAILQ_INIT(&pmap->pm_pvchunk);
2149 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2150 CPU_SET(0, &pmap->pm_active);
2151 }
2152
2153 static __inline void
pte1_copy_nosync(pt1_entry_t * spte1p,pt1_entry_t * dpte1p,vm_offset_t sva,vm_offset_t eva)2154 pte1_copy_nosync(pt1_entry_t *spte1p, pt1_entry_t *dpte1p, vm_offset_t sva,
2155 vm_offset_t eva)
2156 {
2157 u_int idx, count;
2158
2159 idx = pte1_index(sva);
2160 count = (pte1_index(eva) - idx + 1) * sizeof(pt1_entry_t);
2161 bcopy(spte1p + idx, dpte1p + idx, count);
2162 }
2163
2164 static __inline void
pt2tab_copy_nosync(pt2_entry_t * spte2p,pt2_entry_t * dpte2p,vm_offset_t sva,vm_offset_t eva)2165 pt2tab_copy_nosync(pt2_entry_t *spte2p, pt2_entry_t *dpte2p, vm_offset_t sva,
2166 vm_offset_t eva)
2167 {
2168 u_int idx, count;
2169
2170 idx = pt2tab_index(sva);
2171 count = (pt2tab_index(eva) - idx + 1) * sizeof(pt2_entry_t);
2172 bcopy(spte2p + idx, dpte2p + idx, count);
2173 }
2174
2175 /*
2176 * Initialize a preallocated and zeroed pmap structure,
2177 * such as one in a vmspace structure.
2178 */
2179 int
pmap_pinit(pmap_t pmap)2180 pmap_pinit(pmap_t pmap)
2181 {
2182 pt1_entry_t *pte1p;
2183 pt2_entry_t *pte2p;
2184 vm_paddr_t pa, pt2tab_pa;
2185 u_int i;
2186
2187 PDEBUG(6, printf("%s: pmap = %p, pm_pt1 = %p\n", __func__, pmap,
2188 pmap->pm_pt1));
2189
2190 /*
2191 * No need to allocate L2 page table space yet but we do need
2192 * a valid L1 page table and PT2TAB table.
2193 *
2194 * Install shared kernel mappings to these tables. It's a little
2195 * tricky as some parts of KVA are reserved for vectors, devices,
2196 * and whatever else. These parts are supposed to be above
2197 * vm_max_kernel_address. Thus two regions should be installed:
2198 *
2199 * (1) <KERNBASE, kernel_vm_end),
2200 * (2) <vm_max_kernel_address, 0xFFFFFFFF>.
2201 *
2202 * QQQ: The second region should be stable enough to be installed
2203 * only once in time when the tables are allocated.
2204 * QQQ: Maybe copy of both regions at once could be faster ...
2205 * QQQ: Maybe the other TTBR is an option.
2206 *
2207 * Finally, install own PT2TAB table to these tables.
2208 */
2209
2210 if (pmap->pm_pt1 == NULL) {
2211 pmap->pm_pt1 = kmem_alloc_contig(NB_IN_PT1,
2212 M_NOWAIT | M_ZERO, 0, -1UL, NB_IN_PT1, 0, pt_memattr);
2213 if (pmap->pm_pt1 == NULL)
2214 return (0);
2215 }
2216 if (pmap->pm_pt2tab == NULL) {
2217 /*
2218 * QQQ: (1) PT2TAB must be contiguous. If PT2TAB is one page
2219 * only, what should be the only size for 32 bit systems,
2220 * then we could allocate it with vm_page_alloc() and all
2221 * the stuff needed as other L2 page table pages.
2222 * (2) Note that a process PT2TAB is special L2 page table
2223 * page. Its mapping in kernel_arena is permanent and can
2224 * be used no matter which process is current. Its mapping
2225 * in PT2MAP can be used only for current process.
2226 */
2227 pmap->pm_pt2tab = kmem_alloc_attr(NB_IN_PT2TAB,
2228 M_NOWAIT | M_ZERO, 0, -1UL, pt_memattr);
2229 if (pmap->pm_pt2tab == NULL) {
2230 /*
2231 * QQQ: As struct pmap is allocated from UMA with
2232 * UMA_ZONE_NOFREE flag, it's important to leave
2233 * no allocation in pmap if initialization failed.
2234 */
2235 kmem_free(pmap->pm_pt1, NB_IN_PT1);
2236 pmap->pm_pt1 = NULL;
2237 return (0);
2238 }
2239 /*
2240 * QQQ: Each L2 page table page vm_page_t has pindex set to
2241 * pte1 index of virtual address mapped by this page.
2242 * It's not valid for non kernel PT2TABs themselves.
2243 * The pindex of these pages can not be altered because
2244 * of the way how they are allocated now. However, it
2245 * should not be a problem.
2246 */
2247 }
2248
2249 mtx_lock_spin(&allpmaps_lock);
2250 /*
2251 * To avoid race with pmap_kenter_pte1() and pmap_kenter_pt2tab(),
2252 * kernel_vm_end_new is used here instead of kernel_vm_end.
2253 */
2254 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, KERNBASE,
2255 kernel_vm_end_new - 1);
2256 pte1_copy_nosync(kern_pt1, pmap->pm_pt1, vm_max_kernel_address,
2257 0xFFFFFFFF);
2258 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, KERNBASE,
2259 kernel_vm_end_new - 1);
2260 pt2tab_copy_nosync(kern_pt2tab, pmap->pm_pt2tab, vm_max_kernel_address,
2261 0xFFFFFFFF);
2262 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
2263 mtx_unlock_spin(&allpmaps_lock);
2264
2265 /*
2266 * Store PT2MAP PT2 pages (a.k.a. PT2TAB) in PT2TAB itself.
2267 * I.e. self reference mapping. The PT2TAB is private, however mapped
2268 * into shared PT2MAP space, so the mapping should be not global.
2269 */
2270 pt2tab_pa = vtophys(pmap->pm_pt2tab);
2271 pte2p = pmap_pt2tab_entry(pmap, (vm_offset_t)PT2MAP);
2272 for (pa = pt2tab_pa, i = 0; i < NPG_IN_PT2TAB; i++, pa += PTE2_SIZE) {
2273 pt2tab_store(pte2p++, PTE2_KPT_NG(pa));
2274 }
2275
2276 /* Insert PT2MAP PT2s into pmap PT1. */
2277 pte1p = pmap_pte1(pmap, (vm_offset_t)PT2MAP);
2278 for (pa = pt2tab_pa, i = 0; i < NPT2_IN_PT2TAB; i++, pa += NB_IN_PT2) {
2279 pte1_store(pte1p++, PTE1_LINK(pa));
2280 }
2281
2282 /*
2283 * Now synchronize new mapping which was made above.
2284 */
2285 pte1_sync_range(pmap->pm_pt1, NB_IN_PT1);
2286 pte2_sync_range(pmap->pm_pt2tab, NB_IN_PT2TAB);
2287
2288 CPU_ZERO(&pmap->pm_active);
2289 TAILQ_INIT(&pmap->pm_pvchunk);
2290 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2291
2292 return (1);
2293 }
2294
2295 #ifdef INVARIANTS
2296 static bool
pt2tab_user_is_empty(pt2_entry_t * tab)2297 pt2tab_user_is_empty(pt2_entry_t *tab)
2298 {
2299 u_int i, end;
2300
2301 end = pt2tab_index(VM_MAXUSER_ADDRESS);
2302 for (i = 0; i < end; i++)
2303 if (tab[i] != 0) return (false);
2304 return (true);
2305 }
2306 #endif
2307 /*
2308 * Release any resources held by the given physical map.
2309 * Called when a pmap initialized by pmap_pinit is being released.
2310 * Should only be called if the map contains no valid mappings.
2311 */
2312 void
pmap_release(pmap_t pmap)2313 pmap_release(pmap_t pmap)
2314 {
2315 #ifdef INVARIANTS
2316 vm_offset_t start, end;
2317 #endif
2318 KASSERT(pmap->pm_stats.resident_count == 0,
2319 ("%s: pmap resident count %ld != 0", __func__,
2320 pmap->pm_stats.resident_count));
2321 KASSERT(pt2tab_user_is_empty(pmap->pm_pt2tab),
2322 ("%s: has allocated user PT2(s)", __func__));
2323 KASSERT(CPU_EMPTY(&pmap->pm_active),
2324 ("%s: pmap %p is active on some CPU(s)", __func__, pmap));
2325
2326 mtx_lock_spin(&allpmaps_lock);
2327 LIST_REMOVE(pmap, pm_list);
2328 mtx_unlock_spin(&allpmaps_lock);
2329
2330 #ifdef INVARIANTS
2331 start = pte1_index(KERNBASE) * sizeof(pt1_entry_t);
2332 end = (pte1_index(0xFFFFFFFF) + 1) * sizeof(pt1_entry_t);
2333 bzero((char *)pmap->pm_pt1 + start, end - start);
2334
2335 start = pt2tab_index(KERNBASE) * sizeof(pt2_entry_t);
2336 end = (pt2tab_index(0xFFFFFFFF) + 1) * sizeof(pt2_entry_t);
2337 bzero((char *)pmap->pm_pt2tab + start, end - start);
2338 #endif
2339 /*
2340 * We are leaving PT1 and PT2TAB allocated on released pmap,
2341 * so hopefully UMA vmspace_zone will always be inited with
2342 * UMA_ZONE_NOFREE flag.
2343 */
2344 }
2345
2346 /*********************************************************
2347 *
2348 * L2 table pages and their pages management routines.
2349 *
2350 *********************************************************/
2351
2352 /*
2353 * Virtual interface for L2 page table wire counting.
2354 *
2355 * Each L2 page table in a page has own counter which counts a number of
2356 * valid mappings in a table. Global page counter counts mappings in all
2357 * tables in a page plus a single itself mapping in PT2TAB.
2358 *
2359 * During a promotion we leave the associated L2 page table counter
2360 * untouched, so the table (strictly speaking a page which holds it)
2361 * is never freed if promoted.
2362 *
2363 * If a page m->ref_count == 1 then no valid mappings exist in any L2 page
2364 * table in the page and the page itself is only mapped in PT2TAB.
2365 */
2366
2367 static __inline void
pt2_wirecount_init(vm_page_t m)2368 pt2_wirecount_init(vm_page_t m)
2369 {
2370 u_int i;
2371
2372 /*
2373 * Note: A page m is allocated with VM_ALLOC_WIRED flag and
2374 * m->ref_count should be already set correctly.
2375 * So, there is no need to set it again herein.
2376 */
2377 for (i = 0; i < NPT2_IN_PG; i++)
2378 m->md.pt2_wirecount[i] = 0;
2379 }
2380
2381 static __inline void
pt2_wirecount_inc(vm_page_t m,uint32_t pte1_idx)2382 pt2_wirecount_inc(vm_page_t m, uint32_t pte1_idx)
2383 {
2384
2385 /*
2386 * Note: A just modificated pte2 (i.e. already allocated)
2387 * is acquiring one extra reference which must be
2388 * explicitly cleared. It influences the KASSERTs herein.
2389 * All L2 page tables in a page always belong to the same
2390 * pmap, so we allow only one extra reference for the page.
2391 */
2392 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] < (NPTE2_IN_PT2 + 1),
2393 ("%s: PT2 is overflowing ...", __func__));
2394 KASSERT(m->ref_count <= (NPTE2_IN_PG + 1),
2395 ("%s: PT2PG is overflowing ...", __func__));
2396
2397 m->ref_count++;
2398 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]++;
2399 }
2400
2401 static __inline void
pt2_wirecount_dec(vm_page_t m,uint32_t pte1_idx)2402 pt2_wirecount_dec(vm_page_t m, uint32_t pte1_idx)
2403 {
2404
2405 KASSERT(m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] != 0,
2406 ("%s: PT2 is underflowing ...", __func__));
2407 KASSERT(m->ref_count > 1,
2408 ("%s: PT2PG is underflowing ...", __func__));
2409
2410 m->ref_count--;
2411 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]--;
2412 }
2413
2414 static __inline void
pt2_wirecount_set(vm_page_t m,uint32_t pte1_idx,uint16_t count)2415 pt2_wirecount_set(vm_page_t m, uint32_t pte1_idx, uint16_t count)
2416 {
2417
2418 KASSERT(count <= NPTE2_IN_PT2,
2419 ("%s: invalid count %u", __func__, count));
2420 KASSERT(m->ref_count > m->md.pt2_wirecount[pte1_idx & PT2PG_MASK],
2421 ("%s: PT2PG corrupting (%u, %u) ...", __func__, m->ref_count,
2422 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]));
2423
2424 m->ref_count -= m->md.pt2_wirecount[pte1_idx & PT2PG_MASK];
2425 m->ref_count += count;
2426 m->md.pt2_wirecount[pte1_idx & PT2PG_MASK] = count;
2427
2428 KASSERT(m->ref_count <= (NPTE2_IN_PG + 1),
2429 ("%s: PT2PG is overflowed (%u) ...", __func__, m->ref_count));
2430 }
2431
2432 static __inline uint32_t
pt2_wirecount_get(vm_page_t m,uint32_t pte1_idx)2433 pt2_wirecount_get(vm_page_t m, uint32_t pte1_idx)
2434 {
2435
2436 return (m->md.pt2_wirecount[pte1_idx & PT2PG_MASK]);
2437 }
2438
2439 static __inline bool
pt2_is_empty(vm_page_t m,vm_offset_t va)2440 pt2_is_empty(vm_page_t m, vm_offset_t va)
2441 {
2442
2443 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] == 0);
2444 }
2445
2446 static __inline bool
pt2_is_full(vm_page_t m,vm_offset_t va)2447 pt2_is_full(vm_page_t m, vm_offset_t va)
2448 {
2449
2450 return (m->md.pt2_wirecount[pte1_index(va) & PT2PG_MASK] ==
2451 NPTE2_IN_PT2);
2452 }
2453
2454 static __inline bool
pt2pg_is_empty(vm_page_t m)2455 pt2pg_is_empty(vm_page_t m)
2456 {
2457
2458 return (m->ref_count == 1);
2459 }
2460
2461 /*
2462 * This routine is called if the L2 page table
2463 * is not mapped correctly.
2464 */
2465 static vm_page_t
_pmap_allocpte2(pmap_t pmap,vm_offset_t va,u_int flags)2466 _pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2467 {
2468 uint32_t pte1_idx;
2469 pt1_entry_t *pte1p;
2470 pt2_entry_t pte2;
2471 vm_page_t m;
2472 vm_paddr_t pt2pg_pa, pt2_pa;
2473
2474 pte1_idx = pte1_index(va);
2475 pte1p = pmap->pm_pt1 + pte1_idx;
2476
2477 KASSERT(pte1_load(pte1p) == 0,
2478 ("%s: pm_pt1[%#x] is not zero: %#x", __func__, pte1_idx,
2479 pte1_load(pte1p)));
2480
2481 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, va));
2482 if (!pte2_is_valid(pte2)) {
2483 /*
2484 * Install new PT2s page into pmap PT2TAB.
2485 */
2486 m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2487 if (m == NULL) {
2488 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2489 PMAP_UNLOCK(pmap);
2490 rw_wunlock(&pvh_global_lock);
2491 vm_wait(NULL);
2492 rw_wlock(&pvh_global_lock);
2493 PMAP_LOCK(pmap);
2494 }
2495
2496 /*
2497 * Indicate the need to retry. While waiting,
2498 * the L2 page table page may have been allocated.
2499 */
2500 return (NULL);
2501 }
2502 m->pindex = pte1_idx & ~PT2PG_MASK;
2503 pmap->pm_stats.resident_count++;
2504 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
2505 } else {
2506 pt2pg_pa = pte2_pa(pte2);
2507 m = PHYS_TO_VM_PAGE(pt2pg_pa);
2508 }
2509
2510 pt2_wirecount_inc(m, pte1_idx);
2511 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
2512 pte1_store(pte1p, PTE1_LINK(pt2_pa));
2513
2514 return (m);
2515 }
2516
2517 static vm_page_t
pmap_allocpte2(pmap_t pmap,vm_offset_t va,u_int flags)2518 pmap_allocpte2(pmap_t pmap, vm_offset_t va, u_int flags)
2519 {
2520 u_int pte1_idx;
2521 pt1_entry_t *pte1p, pte1;
2522 vm_page_t m;
2523
2524 pte1_idx = pte1_index(va);
2525 retry:
2526 pte1p = pmap->pm_pt1 + pte1_idx;
2527 pte1 = pte1_load(pte1p);
2528
2529 /*
2530 * This supports switching from a 1MB page to a
2531 * normal 4K page.
2532 */
2533 if (pte1_is_section(pte1)) {
2534 (void)pmap_demote_pte1(pmap, pte1p, va);
2535 /*
2536 * Reload pte1 after demotion.
2537 *
2538 * Note: Demotion can even fail as either PT2 is not find for
2539 * the virtual address or PT2PG can not be allocated.
2540 */
2541 pte1 = pte1_load(pte1p);
2542 }
2543
2544 /*
2545 * If the L2 page table page is mapped, we just increment the
2546 * hold count, and activate it.
2547 */
2548 if (pte1_is_link(pte1)) {
2549 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2550 pt2_wirecount_inc(m, pte1_idx);
2551 } else {
2552 /*
2553 * Here if the PT2 isn't mapped, or if it has
2554 * been deallocated.
2555 */
2556 m = _pmap_allocpte2(pmap, va, flags);
2557 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2558 goto retry;
2559 }
2560
2561 return (m);
2562 }
2563
2564 /*
2565 * Schedule the specified unused L2 page table page to be freed. Specifically,
2566 * add the page to the specified list of pages that will be released to the
2567 * physical memory manager after the TLB has been updated.
2568 */
2569 static __inline void
pmap_add_delayed_free_list(vm_page_t m,struct spglist * free)2570 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free)
2571 {
2572
2573 /*
2574 * Put page on a list so that it is released after
2575 * *ALL* TLB shootdown is done
2576 */
2577 #ifdef PMAP_DEBUG
2578 pmap_zero_page_check(m);
2579 #endif
2580 m->flags |= PG_ZERO;
2581 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2582 }
2583
2584 /*
2585 * Unwire L2 page tables page.
2586 */
2587 static void
pmap_unwire_pt2pg(pmap_t pmap,vm_offset_t va,vm_page_t m)2588 pmap_unwire_pt2pg(pmap_t pmap, vm_offset_t va, vm_page_t m)
2589 {
2590 pt1_entry_t *pte1p, opte1 __unused;
2591 pt2_entry_t *pte2p;
2592 uint32_t i;
2593
2594 KASSERT(pt2pg_is_empty(m),
2595 ("%s: pmap %p PT2PG %p wired", __func__, pmap, m));
2596
2597 /*
2598 * Unmap all L2 page tables in the page from L1 page table.
2599 *
2600 * QQQ: Individual L2 page tables (except the last one) can be unmapped
2601 * earlier. However, we are doing that this way.
2602 */
2603 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
2604 ("%s: pmap %p va %#x PT2PG %p bad index", __func__, pmap, va, m));
2605 pte1p = pmap->pm_pt1 + m->pindex;
2606 for (i = 0; i < NPT2_IN_PG; i++, pte1p++) {
2607 KASSERT(m->md.pt2_wirecount[i] == 0,
2608 ("%s: pmap %p PT2 %u (PG %p) wired", __func__, pmap, i, m));
2609 opte1 = pte1_load(pte1p);
2610 if (pte1_is_link(opte1)) {
2611 pte1_clear(pte1p);
2612 /*
2613 * Flush intermediate TLB cache.
2614 */
2615 pmap_tlb_flush(pmap, (m->pindex + i) << PTE1_SHIFT);
2616 }
2617 #ifdef INVARIANTS
2618 else
2619 KASSERT((opte1 == 0) || pte1_is_section(opte1),
2620 ("%s: pmap %p va %#x bad pte1 %x at %u", __func__,
2621 pmap, va, opte1, i));
2622 #endif
2623 }
2624
2625 /*
2626 * Unmap the page from PT2TAB.
2627 */
2628 pte2p = pmap_pt2tab_entry(pmap, va);
2629 (void)pt2tab_load_clear(pte2p);
2630 pmap_tlb_flush(pmap, pt2map_pt2pg(va));
2631
2632 m->ref_count = 0;
2633 pmap->pm_stats.resident_count--;
2634
2635 /*
2636 * This barrier is so that the ordinary store unmapping
2637 * the L2 page table page is globally performed before TLB shoot-
2638 * down is begun.
2639 */
2640 wmb();
2641 vm_wire_sub(1);
2642 }
2643
2644 /*
2645 * Decrements a L2 page table page's wire count, which is used to record the
2646 * number of valid page table entries within the page. If the wire count
2647 * drops to zero, then the page table page is unmapped. Returns true if the
2648 * page table page was unmapped and false otherwise.
2649 */
2650 static __inline bool
pmap_unwire_pt2(pmap_t pmap,vm_offset_t va,vm_page_t m,struct spglist * free)2651 pmap_unwire_pt2(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2652 {
2653 pt2_wirecount_dec(m, pte1_index(va));
2654 if (pt2pg_is_empty(m)) {
2655 /*
2656 * QQQ: Wire count is zero, so whole page should be zero and
2657 * we can set PG_ZERO flag to it.
2658 * Note that when promotion is enabled, it takes some
2659 * more efforts. See pmap_unwire_pt2_all() below.
2660 */
2661 pmap_unwire_pt2pg(pmap, va, m);
2662 pmap_add_delayed_free_list(m, free);
2663 return (true);
2664 } else
2665 return (false);
2666 }
2667
2668 /*
2669 * Drop a L2 page table page's wire count at once, which is used to record
2670 * the number of valid L2 page table entries within the page. If the wire
2671 * count drops to zero, then the L2 page table page is unmapped.
2672 */
2673 static __inline void
pmap_unwire_pt2_all(pmap_t pmap,vm_offset_t va,vm_page_t m,struct spglist * free)2674 pmap_unwire_pt2_all(pmap_t pmap, vm_offset_t va, vm_page_t m,
2675 struct spglist *free)
2676 {
2677 u_int pte1_idx = pte1_index(va);
2678
2679 KASSERT(m->pindex == (pte1_idx & ~PT2PG_MASK),
2680 ("%s: PT2 page's pindex is wrong", __func__));
2681 KASSERT(m->ref_count > pt2_wirecount_get(m, pte1_idx),
2682 ("%s: bad pt2 wire count %u > %u", __func__, m->ref_count,
2683 pt2_wirecount_get(m, pte1_idx)));
2684
2685 /*
2686 * It's possible that the L2 page table was never used.
2687 * It happened in case that a section was created without promotion.
2688 */
2689 if (pt2_is_full(m, va)) {
2690 pt2_wirecount_set(m, pte1_idx, 0);
2691
2692 /*
2693 * QQQ: We clear L2 page table now, so when L2 page table page
2694 * is going to be freed, we can set it PG_ZERO flag ...
2695 * This function is called only on section mappings, so
2696 * hopefully it's not to big overload.
2697 *
2698 * XXX: If pmap is current, existing PT2MAP mapping could be
2699 * used for zeroing.
2700 */
2701 pmap_zero_page_area(m, page_pt2off(pte1_idx), NB_IN_PT2);
2702 }
2703 #ifdef INVARIANTS
2704 else
2705 KASSERT(pt2_is_empty(m, va), ("%s: PT2 is not empty (%u)",
2706 __func__, pt2_wirecount_get(m, pte1_idx)));
2707 #endif
2708 if (pt2pg_is_empty(m)) {
2709 pmap_unwire_pt2pg(pmap, va, m);
2710 pmap_add_delayed_free_list(m, free);
2711 }
2712 }
2713
2714 /*
2715 * After removing a L2 page table entry, this routine is used to
2716 * conditionally free the page, and manage the hold/wire counts.
2717 */
2718 static bool
pmap_unuse_pt2(pmap_t pmap,vm_offset_t va,struct spglist * free)2719 pmap_unuse_pt2(pmap_t pmap, vm_offset_t va, struct spglist *free)
2720 {
2721 pt1_entry_t pte1;
2722 vm_page_t mpte;
2723
2724 if (va >= VM_MAXUSER_ADDRESS)
2725 return (false);
2726 pte1 = pte1_load(pmap_pte1(pmap, va));
2727 mpte = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
2728 return (pmap_unwire_pt2(pmap, va, mpte, free));
2729 }
2730
2731 /*************************************
2732 *
2733 * Page management routines.
2734 *
2735 *************************************/
2736
2737 static const uint32_t pc_freemask[_NPCM] = {
2738 [0 ... _NPCM - 2] = PC_FREEN,
2739 [_NPCM - 1] = PC_FREEL
2740 };
2741
2742 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2743 "Current number of pv entries");
2744
2745 #ifdef PV_STATS
2746 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2747
2748 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2749 "Current number of pv entry chunks");
2750 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2751 "Current number of pv entry chunks allocated");
2752 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2753 "Current number of pv entry chunks frees");
2754 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail,
2755 0, "Number of times tried to get a chunk page but failed.");
2756
2757 static long pv_entry_frees, pv_entry_allocs;
2758 static int pv_entry_spare;
2759
2760 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2761 "Current number of pv entry frees");
2762 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs,
2763 0, "Current number of pv entry allocs");
2764 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2765 "Current number of spare pv entries");
2766 #endif
2767
2768 /*
2769 * Is given page managed?
2770 */
2771 static __inline bool
is_managed(vm_paddr_t pa)2772 is_managed(vm_paddr_t pa)
2773 {
2774 vm_page_t m;
2775
2776 m = PHYS_TO_VM_PAGE(pa);
2777 if (m == NULL)
2778 return (false);
2779 return ((m->oflags & VPO_UNMANAGED) == 0);
2780 }
2781
2782 static __inline bool
pte1_is_managed(pt1_entry_t pte1)2783 pte1_is_managed(pt1_entry_t pte1)
2784 {
2785
2786 return (is_managed(pte1_pa(pte1)));
2787 }
2788
2789 static __inline bool
pte2_is_managed(pt2_entry_t pte2)2790 pte2_is_managed(pt2_entry_t pte2)
2791 {
2792
2793 return (is_managed(pte2_pa(pte2)));
2794 }
2795
2796 /*
2797 * We are in a serious low memory condition. Resort to
2798 * drastic measures to free some pages so we can allocate
2799 * another pv entry chunk.
2800 */
2801 static vm_page_t
pmap_pv_reclaim(pmap_t locked_pmap)2802 pmap_pv_reclaim(pmap_t locked_pmap)
2803 {
2804 struct pch newtail;
2805 struct pv_chunk *pc;
2806 struct md_page *pvh;
2807 pt1_entry_t *pte1p;
2808 pmap_t pmap;
2809 pt2_entry_t *pte2p, tpte2;
2810 pv_entry_t pv;
2811 vm_offset_t va;
2812 vm_page_t m, m_pc;
2813 struct spglist free;
2814 uint32_t inuse;
2815 int bit, field, freed;
2816
2817 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2818 pmap = NULL;
2819 m_pc = NULL;
2820 SLIST_INIT(&free);
2821 TAILQ_INIT(&newtail);
2822 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2823 SLIST_EMPTY(&free))) {
2824 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2825 if (pmap != pc->pc_pmap) {
2826 if (pmap != NULL) {
2827 if (pmap != locked_pmap)
2828 PMAP_UNLOCK(pmap);
2829 }
2830 pmap = pc->pc_pmap;
2831 /* Avoid deadlock and lock recursion. */
2832 if (pmap > locked_pmap)
2833 PMAP_LOCK(pmap);
2834 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2835 pmap = NULL;
2836 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2837 continue;
2838 }
2839 }
2840
2841 /*
2842 * Destroy every non-wired, 4 KB page mapping in the chunk.
2843 */
2844 freed = 0;
2845 for (field = 0; field < _NPCM; field++) {
2846 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2847 inuse != 0; inuse &= ~(1UL << bit)) {
2848 bit = ffs(inuse) - 1;
2849 pv = &pc->pc_pventry[field * 32 + bit];
2850 va = pv->pv_va;
2851 pte1p = pmap_pte1(pmap, va);
2852 if (pte1_is_section(pte1_load(pte1p)))
2853 continue;
2854 pte2p = pmap_pte2(pmap, va);
2855 tpte2 = pte2_load(pte2p);
2856 if ((tpte2 & PTE2_W) == 0)
2857 tpte2 = pte2_load_clear(pte2p);
2858 pmap_pte2_release(pte2p);
2859 if ((tpte2 & PTE2_W) != 0)
2860 continue;
2861 KASSERT(tpte2 != 0,
2862 ("pmap_pv_reclaim: pmap %p va %#x zero pte",
2863 pmap, va));
2864 pmap_tlb_flush(pmap, va);
2865 m = PHYS_TO_VM_PAGE(pte2_pa(tpte2));
2866 if (pte2_is_dirty(tpte2))
2867 vm_page_dirty(m);
2868 if ((tpte2 & PTE2_A) != 0)
2869 vm_page_aflag_set(m, PGA_REFERENCED);
2870 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2871 if (TAILQ_EMPTY(&m->md.pv_list) &&
2872 (m->flags & PG_FICTITIOUS) == 0) {
2873 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2874 if (TAILQ_EMPTY(&pvh->pv_list)) {
2875 vm_page_aflag_clear(m,
2876 PGA_WRITEABLE);
2877 }
2878 }
2879 pc->pc_map[field] |= 1UL << bit;
2880 pmap_unuse_pt2(pmap, va, &free);
2881 freed++;
2882 }
2883 }
2884 if (freed == 0) {
2885 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2886 continue;
2887 }
2888 /* Every freed mapping is for a 4 KB page. */
2889 pmap->pm_stats.resident_count -= freed;
2890 PV_STAT(pv_entry_frees += freed);
2891 PV_STAT(pv_entry_spare += freed);
2892 pv_entry_count -= freed;
2893 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2894 for (field = 0; field < _NPCM; field++)
2895 if (pc->pc_map[field] != pc_freemask[field]) {
2896 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2897 pc_list);
2898 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2899
2900 /*
2901 * One freed pv entry in locked_pmap is
2902 * sufficient.
2903 */
2904 if (pmap == locked_pmap)
2905 goto out;
2906 break;
2907 }
2908 if (field == _NPCM) {
2909 PV_STAT(pv_entry_spare -= _NPCPV);
2910 PV_STAT(pc_chunk_count--);
2911 PV_STAT(pc_chunk_frees++);
2912 /* Entire chunk is free; return it. */
2913 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2914 pmap_qremove((vm_offset_t)pc, 1);
2915 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2916 break;
2917 }
2918 }
2919 out:
2920 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2921 if (pmap != NULL) {
2922 if (pmap != locked_pmap)
2923 PMAP_UNLOCK(pmap);
2924 }
2925 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2926 m_pc = SLIST_FIRST(&free);
2927 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2928 /* Recycle a freed page table page. */
2929 m_pc->ref_count = 1;
2930 vm_wire_add(1);
2931 }
2932 vm_page_free_pages_toq(&free, false);
2933 return (m_pc);
2934 }
2935
2936 static void
free_pv_chunk(struct pv_chunk * pc)2937 free_pv_chunk(struct pv_chunk *pc)
2938 {
2939 vm_page_t m;
2940
2941 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2942 PV_STAT(pv_entry_spare -= _NPCPV);
2943 PV_STAT(pc_chunk_count--);
2944 PV_STAT(pc_chunk_frees++);
2945 /* entire chunk is free, return it */
2946 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2947 pmap_qremove((vm_offset_t)pc, 1);
2948 vm_page_unwire_noq(m);
2949 vm_page_free(m);
2950 pmap_pte2list_free(&pv_vafree, (vm_offset_t)pc);
2951 }
2952
2953 /*
2954 * Free the pv_entry back to the free list.
2955 */
2956 static void
free_pv_entry(pmap_t pmap,pv_entry_t pv)2957 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2958 {
2959 struct pv_chunk *pc;
2960 int idx, field, bit;
2961
2962 rw_assert(&pvh_global_lock, RA_WLOCKED);
2963 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2964 PV_STAT(pv_entry_frees++);
2965 PV_STAT(pv_entry_spare++);
2966 pv_entry_count--;
2967 pc = pv_to_chunk(pv);
2968 idx = pv - &pc->pc_pventry[0];
2969 field = idx / 32;
2970 bit = idx % 32;
2971 pc->pc_map[field] |= 1ul << bit;
2972 for (idx = 0; idx < _NPCM; idx++)
2973 if (pc->pc_map[idx] != pc_freemask[idx]) {
2974 /*
2975 * 98% of the time, pc is already at the head of the
2976 * list. If it isn't already, move it to the head.
2977 */
2978 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2979 pc)) {
2980 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2981 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2982 pc_list);
2983 }
2984 return;
2985 }
2986 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2987 free_pv_chunk(pc);
2988 }
2989
2990 /*
2991 * Get a new pv_entry, allocating a block from the system
2992 * when needed.
2993 */
2994 static pv_entry_t
get_pv_entry(pmap_t pmap,bool try)2995 get_pv_entry(pmap_t pmap, bool try)
2996 {
2997 static const struct timeval printinterval = { 60, 0 };
2998 static struct timeval lastprint;
2999 int bit, field;
3000 pv_entry_t pv;
3001 struct pv_chunk *pc;
3002 vm_page_t m;
3003
3004 rw_assert(&pvh_global_lock, RA_WLOCKED);
3005 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3006 PV_STAT(pv_entry_allocs++);
3007 pv_entry_count++;
3008 if (pv_entry_count > pv_entry_high_water)
3009 if (ratecheck(&lastprint, &printinterval))
3010 printf("Approaching the limit on PV entries, consider "
3011 "increasing either the vm.pmap.shpgperproc or the "
3012 "vm.pmap.pv_entry_max tunable.\n");
3013 retry:
3014 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3015 if (pc != NULL) {
3016 for (field = 0; field < _NPCM; field++) {
3017 if (pc->pc_map[field]) {
3018 bit = ffs(pc->pc_map[field]) - 1;
3019 break;
3020 }
3021 }
3022 if (field < _NPCM) {
3023 pv = &pc->pc_pventry[field * 32 + bit];
3024 pc->pc_map[field] &= ~(1ul << bit);
3025 /* If this was the last item, move it to tail */
3026 for (field = 0; field < _NPCM; field++)
3027 if (pc->pc_map[field] != 0) {
3028 PV_STAT(pv_entry_spare--);
3029 return (pv); /* not full, return */
3030 }
3031 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3032 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3033 PV_STAT(pv_entry_spare--);
3034 return (pv);
3035 }
3036 }
3037 /*
3038 * Access to the pte2list "pv_vafree" is synchronized by the pvh
3039 * global lock. If "pv_vafree" is currently non-empty, it will
3040 * remain non-empty until pmap_pte2list_alloc() completes.
3041 */
3042 if (pv_vafree == 0 ||
3043 (m = vm_page_alloc_noobj(VM_ALLOC_WIRED)) == NULL) {
3044 if (try) {
3045 pv_entry_count--;
3046 PV_STAT(pc_chunk_tryfail++);
3047 return (NULL);
3048 }
3049 m = pmap_pv_reclaim(pmap);
3050 if (m == NULL)
3051 goto retry;
3052 }
3053 PV_STAT(pc_chunk_count++);
3054 PV_STAT(pc_chunk_allocs++);
3055 pc = (struct pv_chunk *)pmap_pte2list_alloc(&pv_vafree);
3056 pmap_qenter((vm_offset_t)pc, &m, 1);
3057 pc->pc_pmap = pmap;
3058 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
3059 for (field = 1; field < _NPCM; field++)
3060 pc->pc_map[field] = pc_freemask[field];
3061 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3062 pv = &pc->pc_pventry[0];
3063 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3064 PV_STAT(pv_entry_spare += _NPCPV - 1);
3065 return (pv);
3066 }
3067
3068 /*
3069 * Create a pv entry for page at pa for
3070 * (pmap, va).
3071 */
3072 static void
pmap_insert_entry(pmap_t pmap,vm_offset_t va,vm_page_t m)3073 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3074 {
3075 pv_entry_t pv;
3076
3077 rw_assert(&pvh_global_lock, RA_WLOCKED);
3078 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3079 pv = get_pv_entry(pmap, false);
3080 pv->pv_va = va;
3081 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3082 }
3083
3084 static __inline pv_entry_t
pmap_pvh_remove(struct md_page * pvh,pmap_t pmap,vm_offset_t va)3085 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3086 {
3087 pv_entry_t pv;
3088
3089 rw_assert(&pvh_global_lock, RA_WLOCKED);
3090 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3091 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3092 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3093 break;
3094 }
3095 }
3096 return (pv);
3097 }
3098
3099 static void
pmap_pvh_free(struct md_page * pvh,pmap_t pmap,vm_offset_t va)3100 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3101 {
3102 pv_entry_t pv;
3103
3104 pv = pmap_pvh_remove(pvh, pmap, va);
3105 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3106 free_pv_entry(pmap, pv);
3107 }
3108
3109 static void
pmap_remove_entry(pmap_t pmap,vm_page_t m,vm_offset_t va)3110 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
3111 {
3112 struct md_page *pvh;
3113
3114 rw_assert(&pvh_global_lock, RA_WLOCKED);
3115 pmap_pvh_free(&m->md, pmap, va);
3116 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
3117 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3118 if (TAILQ_EMPTY(&pvh->pv_list))
3119 vm_page_aflag_clear(m, PGA_WRITEABLE);
3120 }
3121 }
3122
3123 static void
pmap_pv_demote_pte1(pmap_t pmap,vm_offset_t va,vm_paddr_t pa)3124 pmap_pv_demote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3125 {
3126 struct md_page *pvh;
3127 pv_entry_t pv;
3128 vm_offset_t va_last;
3129 vm_page_t m;
3130
3131 rw_assert(&pvh_global_lock, RA_WLOCKED);
3132 KASSERT((pa & PTE1_OFFSET) == 0,
3133 ("pmap_pv_demote_pte1: pa is not 1mpage aligned"));
3134
3135 /*
3136 * Transfer the 1mpage's pv entry for this mapping to the first
3137 * page's pv list.
3138 */
3139 pvh = pa_to_pvh(pa);
3140 va = pte1_trunc(va);
3141 pv = pmap_pvh_remove(pvh, pmap, va);
3142 KASSERT(pv != NULL, ("pmap_pv_demote_pte1: pv not found"));
3143 m = PHYS_TO_VM_PAGE(pa);
3144 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3145 /* Instantiate the remaining NPTE2_IN_PT2 - 1 pv entries. */
3146 va_last = va + PTE1_SIZE - PAGE_SIZE;
3147 do {
3148 m++;
3149 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3150 ("pmap_pv_demote_pte1: page %p is not managed", m));
3151 va += PAGE_SIZE;
3152 pmap_insert_entry(pmap, va, m);
3153 } while (va < va_last);
3154 }
3155
3156 #if VM_NRESERVLEVEL > 0
3157 static void
pmap_pv_promote_pte1(pmap_t pmap,vm_offset_t va,vm_paddr_t pa)3158 pmap_pv_promote_pte1(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
3159 {
3160 struct md_page *pvh;
3161 pv_entry_t pv;
3162 vm_offset_t va_last;
3163 vm_page_t m;
3164
3165 rw_assert(&pvh_global_lock, RA_WLOCKED);
3166 KASSERT((pa & PTE1_OFFSET) == 0,
3167 ("pmap_pv_promote_pte1: pa is not 1mpage aligned"));
3168
3169 /*
3170 * Transfer the first page's pv entry for this mapping to the
3171 * 1mpage's pv list. Aside from avoiding the cost of a call
3172 * to get_pv_entry(), a transfer avoids the possibility that
3173 * get_pv_entry() calls pmap_pv_reclaim() and that pmap_pv_reclaim()
3174 * removes one of the mappings that is being promoted.
3175 */
3176 m = PHYS_TO_VM_PAGE(pa);
3177 va = pte1_trunc(va);
3178 pv = pmap_pvh_remove(&m->md, pmap, va);
3179 KASSERT(pv != NULL, ("pmap_pv_promote_pte1: pv not found"));
3180 pvh = pa_to_pvh(pa);
3181 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3182 /* Free the remaining NPTE2_IN_PT2 - 1 pv entries. */
3183 va_last = va + PTE1_SIZE - PAGE_SIZE;
3184 do {
3185 m++;
3186 va += PAGE_SIZE;
3187 pmap_pvh_free(&m->md, pmap, va);
3188 } while (va < va_last);
3189 }
3190 #endif
3191
3192 /*
3193 * Conditionally create a pv entry.
3194 */
3195 static bool
pmap_try_insert_pv_entry(pmap_t pmap,vm_offset_t va,vm_page_t m)3196 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
3197 {
3198 pv_entry_t pv;
3199
3200 rw_assert(&pvh_global_lock, RA_WLOCKED);
3201 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3202 if (pv_entry_count < pv_entry_high_water &&
3203 (pv = get_pv_entry(pmap, true)) != NULL) {
3204 pv->pv_va = va;
3205 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3206 return (true);
3207 } else
3208 return (false);
3209 }
3210
3211 /*
3212 * Create the pv entries for each of the pages within a section.
3213 */
3214 static bool
pmap_pv_insert_pte1(pmap_t pmap,vm_offset_t va,pt1_entry_t pte1,u_int flags)3215 pmap_pv_insert_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t pte1, u_int flags)
3216 {
3217 struct md_page *pvh;
3218 pv_entry_t pv;
3219 bool noreclaim;
3220
3221 rw_assert(&pvh_global_lock, RA_WLOCKED);
3222 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
3223 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
3224 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
3225 return (false);
3226 pv->pv_va = va;
3227 pvh = pa_to_pvh(pte1_pa(pte1));
3228 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3229 return (true);
3230 }
3231
3232 static inline void
pmap_tlb_flush_pte1(pmap_t pmap,vm_offset_t va,pt1_entry_t npte1)3233 pmap_tlb_flush_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t npte1)
3234 {
3235
3236 /* Kill all the small mappings or the big one only. */
3237 if (pte1_is_section(npte1))
3238 pmap_tlb_flush_range(pmap, pte1_trunc(va), PTE1_SIZE);
3239 else
3240 pmap_tlb_flush(pmap, pte1_trunc(va));
3241 }
3242
3243 /*
3244 * Update kernel pte1 on all pmaps.
3245 *
3246 * The following function is called only on one cpu with disabled interrupts.
3247 * In SMP case, smp_rendezvous_cpus() is used to stop other cpus. This way
3248 * nobody can invoke explicit hardware table walk during the update of pte1.
3249 * Unsolicited hardware table walk can still happen, invoked by speculative
3250 * data or instruction prefetch or even by speculative hardware table walk.
3251 *
3252 * The break-before-make approach should be implemented here. However, it's
3253 * not so easy to do that for kernel mappings as it would be unhappy to unmap
3254 * itself unexpectedly but voluntarily.
3255 */
3256 static void
pmap_update_pte1_kernel(vm_offset_t va,pt1_entry_t npte1)3257 pmap_update_pte1_kernel(vm_offset_t va, pt1_entry_t npte1)
3258 {
3259 pmap_t pmap;
3260 pt1_entry_t *pte1p;
3261
3262 /*
3263 * Get current pmap. Interrupts should be disabled here
3264 * so PCPU_GET() is done atomically.
3265 */
3266 pmap = PCPU_GET(curpmap);
3267 if (pmap == NULL)
3268 pmap = kernel_pmap;
3269
3270 /*
3271 * (1) Change pte1 on current pmap.
3272 * (2) Flush all obsolete TLB entries on current CPU.
3273 * (3) Change pte1 on all pmaps.
3274 * (4) Flush all obsolete TLB entries on all CPUs in SMP case.
3275 */
3276
3277 pte1p = pmap_pte1(pmap, va);
3278 pte1_store(pte1p, npte1);
3279
3280 /* Kill all the small mappings or the big one only. */
3281 if (pte1_is_section(npte1)) {
3282 pmap_pte1_kern_promotions++;
3283 tlb_flush_range_local(pte1_trunc(va), PTE1_SIZE);
3284 } else {
3285 pmap_pte1_kern_demotions++;
3286 tlb_flush_local(pte1_trunc(va));
3287 }
3288
3289 /*
3290 * In SMP case, this function is called when all cpus are at smp
3291 * rendezvous, so there is no need to use 'allpmaps_lock' lock here.
3292 * In UP case, the function is called with this lock locked.
3293 */
3294 LIST_FOREACH(pmap, &allpmaps, pm_list) {
3295 pte1p = pmap_pte1(pmap, va);
3296 pte1_store(pte1p, npte1);
3297 }
3298
3299 #ifdef SMP
3300 /* Kill all the small mappings or the big one only. */
3301 if (pte1_is_section(npte1))
3302 tlb_flush_range(pte1_trunc(va), PTE1_SIZE);
3303 else
3304 tlb_flush(pte1_trunc(va));
3305 #endif
3306 }
3307
3308 #ifdef SMP
3309 struct pte1_action {
3310 vm_offset_t va;
3311 pt1_entry_t npte1;
3312 u_int update; /* CPU that updates the PTE1 */
3313 };
3314
3315 static void
pmap_update_pte1_action(void * arg)3316 pmap_update_pte1_action(void *arg)
3317 {
3318 struct pte1_action *act = arg;
3319
3320 if (act->update == PCPU_GET(cpuid))
3321 pmap_update_pte1_kernel(act->va, act->npte1);
3322 }
3323
3324 /*
3325 * Change pte1 on current pmap.
3326 * Note that kernel pte1 must be changed on all pmaps.
3327 *
3328 * According to the architecture reference manual published by ARM,
3329 * the behaviour is UNPREDICTABLE when two or more TLB entries map the same VA.
3330 * According to this manual, UNPREDICTABLE behaviours must never happen in
3331 * a viable system. In contrast, on x86 processors, it is not specified which
3332 * TLB entry mapping the virtual address will be used, but the MMU doesn't
3333 * generate a bogus translation the way it does on Cortex-A8 rev 2 (Beaglebone
3334 * Black).
3335 *
3336 * It's a problem when either promotion or demotion is being done. The pte1
3337 * update and appropriate TLB flush must be done atomically in general.
3338 */
3339 static void
pmap_change_pte1(pmap_t pmap,pt1_entry_t * pte1p,vm_offset_t va,pt1_entry_t npte1)3340 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3341 pt1_entry_t npte1)
3342 {
3343
3344 if (pmap == kernel_pmap) {
3345 struct pte1_action act;
3346
3347 sched_pin();
3348 act.va = va;
3349 act.npte1 = npte1;
3350 act.update = PCPU_GET(cpuid);
3351 smp_rendezvous_cpus(all_cpus, smp_no_rendezvous_barrier,
3352 pmap_update_pte1_action, NULL, &act);
3353 sched_unpin();
3354 } else {
3355 register_t cspr;
3356
3357 /*
3358 * Use break-before-make approach for changing userland
3359 * mappings. It can cause L1 translation aborts on other
3360 * cores in SMP case. So, special treatment is implemented
3361 * in pmap_fault(). To reduce the likelihood that another core
3362 * will be affected by the broken mapping, disable interrupts
3363 * until the mapping change is completed.
3364 */
3365 cspr = disable_interrupts(PSR_I);
3366 pte1_clear(pte1p);
3367 pmap_tlb_flush_pte1(pmap, va, npte1);
3368 pte1_store(pte1p, npte1);
3369 restore_interrupts(cspr);
3370 }
3371 }
3372 #else
3373 static void
pmap_change_pte1(pmap_t pmap,pt1_entry_t * pte1p,vm_offset_t va,pt1_entry_t npte1)3374 pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
3375 pt1_entry_t npte1)
3376 {
3377
3378 if (pmap == kernel_pmap) {
3379 mtx_lock_spin(&allpmaps_lock);
3380 pmap_update_pte1_kernel(va, npte1);
3381 mtx_unlock_spin(&allpmaps_lock);
3382 } else {
3383 register_t cspr;
3384
3385 /*
3386 * Use break-before-make approach for changing userland
3387 * mappings. It's absolutely safe in UP case when interrupts
3388 * are disabled.
3389 */
3390 cspr = disable_interrupts(PSR_I);
3391 pte1_clear(pte1p);
3392 pmap_tlb_flush_pte1(pmap, va, npte1);
3393 pte1_store(pte1p, npte1);
3394 restore_interrupts(cspr);
3395 }
3396 }
3397 #endif
3398
3399 #if VM_NRESERVLEVEL > 0
3400 /*
3401 * Tries to promote the NPTE2_IN_PT2, contiguous 4KB page mappings that are
3402 * within a single page table page (PT2) to a single 1MB page mapping.
3403 * For promotion to occur, two conditions must be met: (1) the 4KB page
3404 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3405 * mappings must have identical characteristics.
3406 *
3407 * Managed (PG_MANAGED) mappings within the kernel address space are not
3408 * promoted. The reason is that kernel PTE1s are replicated in each pmap but
3409 * pmap_remove_write(), pmap_clear_modify(), and pmap_clear_reference() only
3410 * read the PTE1 from the kernel pmap.
3411 */
3412 static void
pmap_promote_pte1(pmap_t pmap,pt1_entry_t * pte1p,vm_offset_t va)3413 pmap_promote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3414 {
3415 pt1_entry_t npte1;
3416 pt2_entry_t *fpte2p, fpte2, fpte2_fav;
3417 pt2_entry_t *pte2p, pte2;
3418 vm_offset_t pteva __unused;
3419 vm_page_t m __unused;
3420
3421 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3422 pmap, va, pte1_load(pte1p), pte1p));
3423
3424 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3425
3426 /*
3427 * Examine the first PTE2 in the specified PT2. Abort if this PTE2 is
3428 * either invalid, unused, or does not map the first 4KB physical page
3429 * within a 1MB page.
3430 */
3431 fpte2p = pmap_pte2_quick(pmap, pte1_trunc(va));
3432 fpte2 = pte2_load(fpte2p);
3433 if ((fpte2 & ((PTE2_FRAME & PTE1_OFFSET) | PTE2_A | PTE2_V)) !=
3434 (PTE2_A | PTE2_V)) {
3435 pmap_pte1_p_failures++;
3436 CTR3(KTR_PMAP, "%s: failure(1) for va %#x in pmap %p",
3437 __func__, va, pmap);
3438 return;
3439 }
3440 if (pte2_is_managed(fpte2) && pmap == kernel_pmap) {
3441 pmap_pte1_p_failures++;
3442 CTR3(KTR_PMAP, "%s: failure(2) for va %#x in pmap %p",
3443 __func__, va, pmap);
3444 return;
3445 }
3446 if ((fpte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3447 /*
3448 * When page is not modified, PTE2_RO can be set without
3449 * a TLB invalidation.
3450 */
3451 fpte2 |= PTE2_RO;
3452 pte2_store(fpte2p, fpte2);
3453 }
3454
3455 /*
3456 * Examine each of the other PTE2s in the specified PT2. Abort if this
3457 * PTE2 maps an unexpected 4KB physical page or does not have identical
3458 * characteristics to the first PTE2.
3459 */
3460 fpte2_fav = (fpte2 & (PTE2_FRAME | PTE2_A | PTE2_V));
3461 fpte2_fav += PTE1_SIZE - PTE2_SIZE; /* examine from the end */
3462 for (pte2p = fpte2p + NPTE2_IN_PT2 - 1; pte2p > fpte2p; pte2p--) {
3463 pte2 = pte2_load(pte2p);
3464 if ((pte2 & (PTE2_FRAME | PTE2_A | PTE2_V)) != fpte2_fav) {
3465 pmap_pte1_p_failures++;
3466 CTR3(KTR_PMAP, "%s: failure(3) for va %#x in pmap %p",
3467 __func__, va, pmap);
3468 return;
3469 }
3470 if ((pte2 & (PTE2_NM | PTE2_RO)) == PTE2_NM) {
3471 /*
3472 * When page is not modified, PTE2_RO can be set
3473 * without a TLB invalidation. See note above.
3474 */
3475 pte2 |= PTE2_RO;
3476 pte2_store(pte2p, pte2);
3477 pteva = pte1_trunc(va) | (pte2 & PTE1_OFFSET &
3478 PTE2_FRAME);
3479 CTR3(KTR_PMAP, "%s: protect for va %#x in pmap %p",
3480 __func__, pteva, pmap);
3481 }
3482 if ((pte2 & PTE2_PROMOTE) != (fpte2 & PTE2_PROMOTE)) {
3483 pmap_pte1_p_failures++;
3484 CTR3(KTR_PMAP, "%s: failure(4) for va %#x in pmap %p",
3485 __func__, va, pmap);
3486 return;
3487 }
3488
3489 fpte2_fav -= PTE2_SIZE;
3490 }
3491 /*
3492 * The page table page in its current state will stay in PT2TAB
3493 * until the PTE1 mapping the section is demoted by pmap_demote_pte1()
3494 * or destroyed by pmap_remove_pte1().
3495 *
3496 * Note that L2 page table size is not equal to PAGE_SIZE.
3497 */
3498 m = PHYS_TO_VM_PAGE(trunc_page(pte1_link_pa(pte1_load(pte1p))));
3499 KASSERT(m >= vm_page_array && m < &vm_page_array[vm_page_array_size],
3500 ("%s: PT2 page is out of range", __func__));
3501 KASSERT(m->pindex == (pte1_index(va) & ~PT2PG_MASK),
3502 ("%s: PT2 page's pindex is wrong", __func__));
3503
3504 /*
3505 * Get pte1 from pte2 format.
3506 */
3507 npte1 = (fpte2 & PTE1_FRAME) | ATTR_TO_L1(fpte2) | PTE1_V;
3508
3509 /*
3510 * Promote the pv entries.
3511 */
3512 if (pte2_is_managed(fpte2))
3513 pmap_pv_promote_pte1(pmap, va, pte1_pa(npte1));
3514
3515 /*
3516 * Promote the mappings.
3517 */
3518 pmap_change_pte1(pmap, pte1p, va, npte1);
3519
3520 pmap_pte1_promotions++;
3521 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3522 __func__, va, pmap);
3523
3524 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3525 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3526 }
3527 #endif /* VM_NRESERVLEVEL > 0 */
3528
3529 /*
3530 * Zero L2 page table page.
3531 */
3532 static __inline void
pmap_clear_pt2(pt2_entry_t * fpte2p)3533 pmap_clear_pt2(pt2_entry_t *fpte2p)
3534 {
3535 pt2_entry_t *pte2p;
3536
3537 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++)
3538 pte2_clear(pte2p);
3539
3540 }
3541
3542 /*
3543 * Removes a 1MB page mapping from the kernel pmap.
3544 */
3545 static void
pmap_remove_kernel_pte1(pmap_t pmap,pt1_entry_t * pte1p,vm_offset_t va)3546 pmap_remove_kernel_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3547 {
3548 vm_page_t m;
3549 uint32_t pte1_idx;
3550 pt2_entry_t *fpte2p;
3551 vm_paddr_t pt2_pa;
3552
3553 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3554 m = pmap_pt2_page(pmap, va);
3555 if (m == NULL)
3556 /*
3557 * QQQ: Is this function called only on promoted pte1?
3558 * We certainly do section mappings directly
3559 * (without promotion) in kernel !!!
3560 */
3561 panic("%s: missing pt2 page", __func__);
3562
3563 pte1_idx = pte1_index(va);
3564
3565 /*
3566 * Initialize the L2 page table.
3567 */
3568 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3569 pmap_clear_pt2(fpte2p);
3570
3571 /*
3572 * Remove the mapping.
3573 */
3574 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(m), pte1_idx);
3575 pmap_kenter_pte1(va, PTE1_LINK(pt2_pa));
3576
3577 /*
3578 * QQQ: We do not need to invalidate PT2MAP mapping
3579 * as we did not change it. I.e. the L2 page table page
3580 * was and still is mapped the same way.
3581 */
3582 }
3583
3584 /*
3585 * Do the things to unmap a section in a process
3586 */
3587 static void
pmap_remove_pte1(pmap_t pmap,pt1_entry_t * pte1p,vm_offset_t sva,struct spglist * free)3588 pmap_remove_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
3589 struct spglist *free)
3590 {
3591 pt1_entry_t opte1;
3592 struct md_page *pvh;
3593 vm_offset_t eva, va;
3594 vm_page_t m;
3595
3596 PDEBUG(6, printf("%s(%p): va %#x pte1 %#x at %p\n", __func__, pmap, sva,
3597 pte1_load(pte1p), pte1p));
3598
3599 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3600 KASSERT((sva & PTE1_OFFSET) == 0,
3601 ("%s: sva is not 1mpage aligned", __func__));
3602
3603 /*
3604 * Clear and invalidate the mapping. It should occupy one and only TLB
3605 * entry. So, pmap_tlb_flush() called with aligned address should be
3606 * sufficient.
3607 */
3608 opte1 = pte1_load_clear(pte1p);
3609 pmap_tlb_flush(pmap, sva);
3610
3611 if (pte1_is_wired(opte1))
3612 pmap->pm_stats.wired_count -= PTE1_SIZE / PAGE_SIZE;
3613 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
3614 if (pte1_is_managed(opte1)) {
3615 pvh = pa_to_pvh(pte1_pa(opte1));
3616 pmap_pvh_free(pvh, pmap, sva);
3617 eva = sva + PTE1_SIZE;
3618 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
3619 va < eva; va += PAGE_SIZE, m++) {
3620 if (pte1_is_dirty(opte1))
3621 vm_page_dirty(m);
3622 if (opte1 & PTE1_A)
3623 vm_page_aflag_set(m, PGA_REFERENCED);
3624 if (TAILQ_EMPTY(&m->md.pv_list) &&
3625 TAILQ_EMPTY(&pvh->pv_list))
3626 vm_page_aflag_clear(m, PGA_WRITEABLE);
3627 }
3628 }
3629 if (pmap == kernel_pmap) {
3630 /*
3631 * L2 page table(s) can't be removed from kernel map as
3632 * kernel counts on it (stuff around pmap_growkernel()).
3633 */
3634 pmap_remove_kernel_pte1(pmap, pte1p, sva);
3635 } else {
3636 /*
3637 * Get associated L2 page table page.
3638 * It's possible that the page was never allocated.
3639 */
3640 m = pmap_pt2_page(pmap, sva);
3641 if (m != NULL)
3642 pmap_unwire_pt2_all(pmap, sva, m, free);
3643 }
3644 }
3645
3646 /*
3647 * Fills L2 page table page with mappings to consecutive physical pages.
3648 */
3649 static __inline void
pmap_fill_pt2(pt2_entry_t * fpte2p,pt2_entry_t npte2)3650 pmap_fill_pt2(pt2_entry_t *fpte2p, pt2_entry_t npte2)
3651 {
3652 pt2_entry_t *pte2p;
3653
3654 for (pte2p = fpte2p; pte2p < fpte2p + NPTE2_IN_PT2; pte2p++) {
3655 pte2_store(pte2p, npte2);
3656 npte2 += PTE2_SIZE;
3657 }
3658 }
3659
3660 /*
3661 * Tries to demote a 1MB page mapping. If demotion fails, the
3662 * 1MB page mapping is invalidated.
3663 */
3664 static bool
pmap_demote_pte1(pmap_t pmap,pt1_entry_t * pte1p,vm_offset_t va)3665 pmap_demote_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va)
3666 {
3667 pt1_entry_t opte1, npte1;
3668 pt2_entry_t *fpte2p, npte2;
3669 vm_paddr_t pt2pg_pa, pt2_pa;
3670 vm_page_t m;
3671 struct spglist free;
3672 uint32_t pte1_idx, isnew = 0;
3673
3674 PDEBUG(6, printf("%s(%p): try for va %#x pte1 %#x at %p\n", __func__,
3675 pmap, va, pte1_load(pte1p), pte1p));
3676
3677 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3678
3679 opte1 = pte1_load(pte1p);
3680 KASSERT(pte1_is_section(opte1), ("%s: opte1 not a section", __func__));
3681
3682 if ((opte1 & PTE1_A) == 0 || (m = pmap_pt2_page(pmap, va)) == NULL) {
3683 KASSERT(!pte1_is_wired(opte1),
3684 ("%s: PT2 page for a wired mapping is missing", __func__));
3685
3686 /*
3687 * Invalidate the 1MB page mapping and return
3688 * "failure" if the mapping was never accessed or the
3689 * allocation of the new page table page fails.
3690 */
3691 if ((opte1 & PTE1_A) == 0 ||
3692 (m = vm_page_alloc_noobj(VM_ALLOC_WIRED)) == NULL) {
3693 SLIST_INIT(&free);
3694 pmap_remove_pte1(pmap, pte1p, pte1_trunc(va), &free);
3695 vm_page_free_pages_toq(&free, false);
3696 CTR3(KTR_PMAP, "%s: failure for va %#x in pmap %p",
3697 __func__, va, pmap);
3698 return (false);
3699 }
3700 m->pindex = pte1_index(va) & ~PT2PG_MASK;
3701 if (va < VM_MAXUSER_ADDRESS)
3702 pmap->pm_stats.resident_count++;
3703
3704 isnew = 1;
3705
3706 /*
3707 * We init all L2 page tables in the page even if
3708 * we are going to change everything for one L2 page
3709 * table in a while.
3710 */
3711 pt2pg_pa = pmap_pt2pg_init(pmap, va, m);
3712 } else {
3713 if (va < VM_MAXUSER_ADDRESS) {
3714 if (pt2_is_empty(m, va))
3715 isnew = 1; /* Demoting section w/o promotion. */
3716 #ifdef INVARIANTS
3717 else
3718 KASSERT(pt2_is_full(m, va), ("%s: bad PT2 wire"
3719 " count %u", __func__,
3720 pt2_wirecount_get(m, pte1_index(va))));
3721 #endif
3722 }
3723 }
3724
3725 pt2pg_pa = VM_PAGE_TO_PHYS(m);
3726 pte1_idx = pte1_index(va);
3727 /*
3728 * If the pmap is current, then the PT2MAP can provide access to
3729 * the page table page (promoted L2 page tables are not unmapped).
3730 * Otherwise, temporarily map the L2 page table page (m) into
3731 * the kernel's address space at either PADDR1 or PADDR2.
3732 *
3733 * Note that L2 page table size is not equal to PAGE_SIZE.
3734 */
3735 if (pmap_is_current(pmap))
3736 fpte2p = page_pt2(pt2map_pt2pg(va), pte1_idx);
3737 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
3738 if (pte2_pa(pte2_load(PMAP1)) != pt2pg_pa) {
3739 pte2_store(PMAP1, PTE2_KPT(pt2pg_pa));
3740 #ifdef SMP
3741 PMAP1cpu = PCPU_GET(cpuid);
3742 #endif
3743 tlb_flush_local((vm_offset_t)PADDR1);
3744 PMAP1changed++;
3745 } else
3746 #ifdef SMP
3747 if (PMAP1cpu != PCPU_GET(cpuid)) {
3748 PMAP1cpu = PCPU_GET(cpuid);
3749 tlb_flush_local((vm_offset_t)PADDR1);
3750 PMAP1changedcpu++;
3751 } else
3752 #endif
3753 PMAP1unchanged++;
3754 fpte2p = page_pt2((vm_offset_t)PADDR1, pte1_idx);
3755 } else {
3756 mtx_lock(&PMAP2mutex);
3757 if (pte2_pa(pte2_load(PMAP2)) != pt2pg_pa) {
3758 pte2_store(PMAP2, PTE2_KPT(pt2pg_pa));
3759 tlb_flush((vm_offset_t)PADDR2);
3760 }
3761 fpte2p = page_pt2((vm_offset_t)PADDR2, pte1_idx);
3762 }
3763 pt2_pa = page_pt2pa(pt2pg_pa, pte1_idx);
3764 npte1 = PTE1_LINK(pt2_pa);
3765
3766 KASSERT((opte1 & PTE1_A) != 0,
3767 ("%s: opte1 is missing PTE1_A", __func__));
3768 KASSERT((opte1 & (PTE1_NM | PTE1_RO)) != PTE1_NM,
3769 ("%s: opte1 has PTE1_NM", __func__));
3770
3771 /*
3772 * Get pte2 from pte1 format.
3773 */
3774 npte2 = pte1_pa(opte1) | ATTR_TO_L2(opte1) | PTE2_V;
3775
3776 /*
3777 * If the L2 page table page is new, initialize it. If the mapping
3778 * has changed attributes, update the page table entries.
3779 */
3780 if (isnew != 0) {
3781 pt2_wirecount_set(m, pte1_idx, NPTE2_IN_PT2);
3782 pmap_fill_pt2(fpte2p, npte2);
3783 } else if ((pte2_load(fpte2p) & PTE2_PROMOTE) !=
3784 (npte2 & PTE2_PROMOTE))
3785 pmap_fill_pt2(fpte2p, npte2);
3786
3787 KASSERT(pte2_pa(pte2_load(fpte2p)) == pte2_pa(npte2),
3788 ("%s: fpte2p and npte2 map different physical addresses",
3789 __func__));
3790
3791 if (fpte2p == PADDR2)
3792 mtx_unlock(&PMAP2mutex);
3793
3794 /*
3795 * Demote the mapping. This pmap is locked. The old PTE1 has
3796 * PTE1_A set. If the old PTE1 has not PTE1_RO set, it also
3797 * has not PTE1_NM set. Thus, there is no danger of a race with
3798 * another processor changing the setting of PTE1_A and/or PTE1_NM
3799 * between the read above and the store below.
3800 */
3801 pmap_change_pte1(pmap, pte1p, va, npte1);
3802
3803 /*
3804 * Demote the pv entry. This depends on the earlier demotion
3805 * of the mapping. Specifically, the (re)creation of a per-
3806 * page pv entry might trigger the execution of pmap_pv_reclaim(),
3807 * which might reclaim a newly (re)created per-page pv entry
3808 * and destroy the associated mapping. In order to destroy
3809 * the mapping, the PTE1 must have already changed from mapping
3810 * the 1mpage to referencing the page table page.
3811 */
3812 if (pte1_is_managed(opte1))
3813 pmap_pv_demote_pte1(pmap, va, pte1_pa(opte1));
3814
3815 pmap_pte1_demotions++;
3816 CTR3(KTR_PMAP, "%s: success for va %#x in pmap %p",
3817 __func__, va, pmap);
3818
3819 PDEBUG(6, printf("%s(%p): success for va %#x pte1 %#x(%#x) at %p\n",
3820 __func__, pmap, va, npte1, pte1_load(pte1p), pte1p));
3821 return (true);
3822 }
3823
3824 /*
3825 * Insert the given physical page (p) at
3826 * the specified virtual address (v) in the
3827 * target physical map with the protection requested.
3828 *
3829 * If specified, the page will be wired down, meaning
3830 * that the related pte can not be reclaimed.
3831 *
3832 * NB: This is the only routine which MAY NOT lazy-evaluate
3833 * or lose information. That is, this routine must actually
3834 * insert this page into the given map NOW.
3835 */
3836 int
pmap_enter(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,u_int flags,int8_t psind)3837 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3838 u_int flags, int8_t psind)
3839 {
3840 pt1_entry_t *pte1p;
3841 pt2_entry_t *pte2p;
3842 pt2_entry_t npte2, opte2;
3843 pv_entry_t pv;
3844 vm_paddr_t opa, pa;
3845 vm_page_t mpte2, om;
3846 int rv;
3847
3848 va = trunc_page(va);
3849 KASSERT(va <= vm_max_kernel_address, ("%s: toobig", __func__));
3850 KASSERT(va < UPT2V_MIN_ADDRESS || va >= UPT2V_MAX_ADDRESS,
3851 ("%s: invalid to pmap_enter page table pages (va: 0x%x)", __func__,
3852 va));
3853 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || !VA_IS_CLEANMAP(va),
3854 ("%s: managed mapping within the clean submap", __func__));
3855 if ((m->oflags & VPO_UNMANAGED) == 0)
3856 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3857 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3858 ("%s: flags %u has reserved bits set", __func__, flags));
3859 pa = VM_PAGE_TO_PHYS(m);
3860 npte2 = PTE2(pa, PTE2_A, vm_page_pte2_attr(m));
3861 if ((flags & VM_PROT_WRITE) == 0)
3862 npte2 |= PTE2_NM;
3863 if ((prot & VM_PROT_WRITE) == 0)
3864 npte2 |= PTE2_RO;
3865 KASSERT((npte2 & (PTE2_NM | PTE2_RO)) != PTE2_RO,
3866 ("%s: flags includes VM_PROT_WRITE but prot doesn't", __func__));
3867 if ((prot & VM_PROT_EXECUTE) == 0)
3868 npte2 |= PTE2_NX;
3869 if ((flags & PMAP_ENTER_WIRED) != 0)
3870 npte2 |= PTE2_W;
3871 if (va < VM_MAXUSER_ADDRESS)
3872 npte2 |= PTE2_U;
3873 if (pmap != kernel_pmap)
3874 npte2 |= PTE2_NG;
3875
3876 rw_wlock(&pvh_global_lock);
3877 PMAP_LOCK(pmap);
3878 sched_pin();
3879 if (psind == 1) {
3880 /* Assert the required virtual and physical alignment. */
3881 KASSERT((va & PTE1_OFFSET) == 0,
3882 ("%s: va unaligned", __func__));
3883 KASSERT(m->psind > 0, ("%s: m->psind < psind", __func__));
3884 rv = pmap_enter_pte1(pmap, va, PTE1_PA(pa) | ATTR_TO_L1(npte2) |
3885 PTE1_V, flags, m);
3886 goto out;
3887 }
3888
3889 /*
3890 * In the case that a page table page is not
3891 * resident, we are creating it here.
3892 */
3893 if (va < VM_MAXUSER_ADDRESS) {
3894 mpte2 = pmap_allocpte2(pmap, va, flags);
3895 if (mpte2 == NULL) {
3896 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3897 ("pmap_allocpte2 failed with sleep allowed"));
3898 rv = KERN_RESOURCE_SHORTAGE;
3899 goto out;
3900 }
3901 } else
3902 mpte2 = NULL;
3903 pte1p = pmap_pte1(pmap, va);
3904 if (pte1_is_section(pte1_load(pte1p)))
3905 panic("%s: attempted on 1MB page", __func__);
3906 pte2p = pmap_pte2_quick(pmap, va);
3907 if (pte2p == NULL)
3908 panic("%s: invalid L1 page table entry va=%#x", __func__, va);
3909
3910 om = NULL;
3911 opte2 = pte2_load(pte2p);
3912 opa = pte2_pa(opte2);
3913 /*
3914 * Mapping has not changed, must be protection or wiring change.
3915 */
3916 if (pte2_is_valid(opte2) && (opa == pa)) {
3917 /*
3918 * Wiring change, just update stats. We don't worry about
3919 * wiring PT2 pages as they remain resident as long as there
3920 * are valid mappings in them. Hence, if a user page is wired,
3921 * the PT2 page will be also.
3922 */
3923 if (pte2_is_wired(npte2) && !pte2_is_wired(opte2))
3924 pmap->pm_stats.wired_count++;
3925 else if (!pte2_is_wired(npte2) && pte2_is_wired(opte2))
3926 pmap->pm_stats.wired_count--;
3927
3928 /*
3929 * Remove extra pte2 reference
3930 */
3931 if (mpte2)
3932 pt2_wirecount_dec(mpte2, pte1_index(va));
3933 if ((m->oflags & VPO_UNMANAGED) == 0)
3934 om = m;
3935 goto validate;
3936 }
3937
3938 /*
3939 * QQQ: We think that changing physical address on writeable mapping
3940 * is not safe. Well, maybe on kernel address space with correct
3941 * locking, it can make a sense. However, we have no idea why
3942 * anyone should do that on user address space. Are we wrong?
3943 */
3944 KASSERT((opa == 0) || (opa == pa) ||
3945 !pte2_is_valid(opte2) || ((opte2 & PTE2_RO) != 0),
3946 ("%s: pmap %p va %#x(%#x) opa %#x pa %#x - gotcha %#x %#x!",
3947 __func__, pmap, va, opte2, opa, pa, flags, prot));
3948
3949 pv = NULL;
3950
3951 /*
3952 * Mapping has changed, invalidate old range and fall through to
3953 * handle validating new mapping.
3954 */
3955 if (opa) {
3956 if (pte2_is_wired(opte2))
3957 pmap->pm_stats.wired_count--;
3958 om = PHYS_TO_VM_PAGE(opa);
3959 if (om != NULL && (om->oflags & VPO_UNMANAGED) != 0)
3960 om = NULL;
3961 if (om != NULL)
3962 pv = pmap_pvh_remove(&om->md, pmap, va);
3963
3964 /*
3965 * Remove extra pte2 reference
3966 */
3967 if (mpte2 != NULL)
3968 pt2_wirecount_dec(mpte2, va >> PTE1_SHIFT);
3969 } else
3970 pmap->pm_stats.resident_count++;
3971
3972 /*
3973 * Enter on the PV list if part of our managed memory.
3974 */
3975 if ((m->oflags & VPO_UNMANAGED) == 0) {
3976 if (pv == NULL) {
3977 pv = get_pv_entry(pmap, false);
3978 pv->pv_va = va;
3979 }
3980 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3981 } else if (pv != NULL)
3982 free_pv_entry(pmap, pv);
3983
3984 /*
3985 * Increment counters
3986 */
3987 if (pte2_is_wired(npte2))
3988 pmap->pm_stats.wired_count++;
3989
3990 validate:
3991 /*
3992 * Now validate mapping with desired protection/wiring.
3993 */
3994 if (prot & VM_PROT_WRITE) {
3995 if ((m->oflags & VPO_UNMANAGED) == 0)
3996 vm_page_aflag_set(m, PGA_WRITEABLE);
3997 }
3998
3999 /*
4000 * If the mapping or permission bits are different, we need
4001 * to update the pte2.
4002 *
4003 * QQQ: Think again and again what to do
4004 * if the mapping is going to be changed!
4005 */
4006 if ((opte2 & ~(PTE2_NM | PTE2_A)) != (npte2 & ~(PTE2_NM | PTE2_A))) {
4007 /*
4008 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4009 * is set. Do it now, before the mapping is stored and made
4010 * valid for hardware table walk. If done later, there is a race
4011 * for other threads of current process in lazy loading case.
4012 * Don't do it for kernel memory which is mapped with exec
4013 * permission even if the memory isn't going to hold executable
4014 * code. The only time when icache sync is needed is after
4015 * kernel module is loaded and the relocation info is processed.
4016 * And it's done in elf_cpu_load_file().
4017 *
4018 * QQQ: (1) Does it exist any better way where
4019 * or how to sync icache?
4020 * (2) Now, we do it on a page basis.
4021 */
4022 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4023 m->md.pat_mode == VM_MEMATTR_WB_WA &&
4024 (opa != pa || (opte2 & PTE2_NX)))
4025 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4026
4027 if (opte2 & PTE2_V) {
4028 /* Change mapping with break-before-make approach. */
4029 opte2 = pte2_load_clear(pte2p);
4030 pmap_tlb_flush(pmap, va);
4031 pte2_store(pte2p, npte2);
4032 if (om != NULL) {
4033 KASSERT((om->oflags & VPO_UNMANAGED) == 0,
4034 ("%s: om %p unmanaged", __func__, om));
4035 if ((opte2 & PTE2_A) != 0)
4036 vm_page_aflag_set(om, PGA_REFERENCED);
4037 if (pte2_is_dirty(opte2))
4038 vm_page_dirty(om);
4039 if (TAILQ_EMPTY(&om->md.pv_list) &&
4040 ((om->flags & PG_FICTITIOUS) != 0 ||
4041 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4042 vm_page_aflag_clear(om, PGA_WRITEABLE);
4043 }
4044 } else
4045 pte2_store(pte2p, npte2);
4046 }
4047 #if 0
4048 else {
4049 /*
4050 * QQQ: In time when both access and not mofified bits are
4051 * emulated by software, this should not happen. Some
4052 * analysis is need, if this really happen. Missing
4053 * tlb flush somewhere could be the reason.
4054 */
4055 panic("%s: pmap %p va %#x opte2 %x npte2 %x !!", __func__, pmap,
4056 va, opte2, npte2);
4057 }
4058 #endif
4059
4060 #if VM_NRESERVLEVEL > 0
4061 /*
4062 * If both the L2 page table page and the reservation are fully
4063 * populated, then attempt promotion.
4064 */
4065 if ((mpte2 == NULL || pt2_is_full(mpte2, va)) &&
4066 sp_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
4067 vm_reserv_level_iffullpop(m) == 0)
4068 pmap_promote_pte1(pmap, pte1p, va);
4069 #endif
4070
4071 rv = KERN_SUCCESS;
4072 out:
4073 sched_unpin();
4074 rw_wunlock(&pvh_global_lock);
4075 PMAP_UNLOCK(pmap);
4076 return (rv);
4077 }
4078
4079 /*
4080 * Do the things to unmap a page in a process.
4081 */
4082 static int
pmap_remove_pte2(pmap_t pmap,pt2_entry_t * pte2p,vm_offset_t va,struct spglist * free)4083 pmap_remove_pte2(pmap_t pmap, pt2_entry_t *pte2p, vm_offset_t va,
4084 struct spglist *free)
4085 {
4086 pt2_entry_t opte2;
4087 vm_page_t m;
4088
4089 rw_assert(&pvh_global_lock, RA_WLOCKED);
4090 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4091
4092 /* Clear and invalidate the mapping. */
4093 opte2 = pte2_load_clear(pte2p);
4094 pmap_tlb_flush(pmap, va);
4095
4096 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %#x not link pte2 %#x",
4097 __func__, pmap, va, opte2));
4098
4099 if (opte2 & PTE2_W)
4100 pmap->pm_stats.wired_count -= 1;
4101 pmap->pm_stats.resident_count -= 1;
4102 if (pte2_is_managed(opte2)) {
4103 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
4104 if (pte2_is_dirty(opte2))
4105 vm_page_dirty(m);
4106 if (opte2 & PTE2_A)
4107 vm_page_aflag_set(m, PGA_REFERENCED);
4108 pmap_remove_entry(pmap, m, va);
4109 }
4110 return (pmap_unuse_pt2(pmap, va, free));
4111 }
4112
4113 /*
4114 * Remove a single page from a process address space.
4115 */
4116 static void
pmap_remove_page(pmap_t pmap,vm_offset_t va,struct spglist * free)4117 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
4118 {
4119 pt2_entry_t *pte2p;
4120
4121 rw_assert(&pvh_global_lock, RA_WLOCKED);
4122 KASSERT(curthread->td_pinned > 0,
4123 ("%s: curthread not pinned", __func__));
4124 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4125 if ((pte2p = pmap_pte2_quick(pmap, va)) == NULL ||
4126 !pte2_is_valid(pte2_load(pte2p)))
4127 return;
4128 pmap_remove_pte2(pmap, pte2p, va, free);
4129 }
4130
4131 /*
4132 * Remove the given range of addresses from the specified map.
4133 *
4134 * It is assumed that the start and end are properly
4135 * rounded to the page size.
4136 */
4137 void
pmap_remove(pmap_t pmap,vm_offset_t sva,vm_offset_t eva)4138 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4139 {
4140 vm_offset_t nextva;
4141 pt1_entry_t *pte1p, pte1;
4142 pt2_entry_t *pte2p, pte2;
4143 struct spglist free;
4144
4145 /*
4146 * Perform an unsynchronized read. This is, however, safe.
4147 */
4148 if (pmap->pm_stats.resident_count == 0)
4149 return;
4150
4151 SLIST_INIT(&free);
4152
4153 rw_wlock(&pvh_global_lock);
4154 sched_pin();
4155 PMAP_LOCK(pmap);
4156
4157 /*
4158 * Special handling of removing one page. A very common
4159 * operation and easy to short circuit some code.
4160 */
4161 if (sva + PAGE_SIZE == eva) {
4162 pte1 = pte1_load(pmap_pte1(pmap, sva));
4163 if (pte1_is_link(pte1)) {
4164 pmap_remove_page(pmap, sva, &free);
4165 goto out;
4166 }
4167 }
4168
4169 for (; sva < eva; sva = nextva) {
4170 /*
4171 * Calculate address for next L2 page table.
4172 */
4173 nextva = pte1_trunc(sva + PTE1_SIZE);
4174 if (nextva < sva)
4175 nextva = eva;
4176 if (pmap->pm_stats.resident_count == 0)
4177 break;
4178
4179 pte1p = pmap_pte1(pmap, sva);
4180 pte1 = pte1_load(pte1p);
4181
4182 /*
4183 * Weed out invalid mappings. Note: we assume that the L1 page
4184 * table is always allocated, and in kernel virtual.
4185 */
4186 if (pte1 == 0)
4187 continue;
4188
4189 if (pte1_is_section(pte1)) {
4190 /*
4191 * Are we removing the entire large page? If not,
4192 * demote the mapping and fall through.
4193 */
4194 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4195 pmap_remove_pte1(pmap, pte1p, sva, &free);
4196 continue;
4197 } else if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4198 /* The large page mapping was destroyed. */
4199 continue;
4200 }
4201 #ifdef INVARIANTS
4202 else {
4203 /* Update pte1 after demotion. */
4204 pte1 = pte1_load(pte1p);
4205 }
4206 #endif
4207 }
4208
4209 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
4210 " is not link", __func__, pmap, sva, pte1, pte1p));
4211
4212 /*
4213 * Limit our scan to either the end of the va represented
4214 * by the current L2 page table page, or to the end of the
4215 * range being removed.
4216 */
4217 if (nextva > eva)
4218 nextva = eva;
4219
4220 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva;
4221 pte2p++, sva += PAGE_SIZE) {
4222 pte2 = pte2_load(pte2p);
4223 if (!pte2_is_valid(pte2))
4224 continue;
4225 if (pmap_remove_pte2(pmap, pte2p, sva, &free))
4226 break;
4227 }
4228 }
4229 out:
4230 sched_unpin();
4231 rw_wunlock(&pvh_global_lock);
4232 PMAP_UNLOCK(pmap);
4233 vm_page_free_pages_toq(&free, false);
4234 }
4235
4236 /*
4237 * Routine: pmap_remove_all
4238 * Function:
4239 * Removes this physical page from
4240 * all physical maps in which it resides.
4241 * Reflects back modify bits to the pager.
4242 *
4243 * Notes:
4244 * Original versions of this routine were very
4245 * inefficient because they iteratively called
4246 * pmap_remove (slow...)
4247 */
4248
4249 void
pmap_remove_all(vm_page_t m)4250 pmap_remove_all(vm_page_t m)
4251 {
4252 struct md_page *pvh;
4253 pv_entry_t pv;
4254 pmap_t pmap;
4255 pt2_entry_t *pte2p, opte2;
4256 pt1_entry_t *pte1p;
4257 vm_offset_t va;
4258 struct spglist free;
4259
4260 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4261 ("%s: page %p is not managed", __func__, m));
4262 SLIST_INIT(&free);
4263 rw_wlock(&pvh_global_lock);
4264 sched_pin();
4265 if ((m->flags & PG_FICTITIOUS) != 0)
4266 goto small_mappings;
4267 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4268 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4269 va = pv->pv_va;
4270 pmap = PV_PMAP(pv);
4271 PMAP_LOCK(pmap);
4272 pte1p = pmap_pte1(pmap, va);
4273 (void)pmap_demote_pte1(pmap, pte1p, va);
4274 PMAP_UNLOCK(pmap);
4275 }
4276 small_mappings:
4277 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4278 pmap = PV_PMAP(pv);
4279 PMAP_LOCK(pmap);
4280 pmap->pm_stats.resident_count--;
4281 pte1p = pmap_pte1(pmap, pv->pv_va);
4282 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found "
4283 "a 1mpage in page %p's pv list", __func__, m));
4284 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
4285 opte2 = pte2_load_clear(pte2p);
4286 pmap_tlb_flush(pmap, pv->pv_va);
4287 KASSERT(pte2_is_valid(opte2), ("%s: pmap %p va %x zero pte2",
4288 __func__, pmap, pv->pv_va));
4289 if (pte2_is_wired(opte2))
4290 pmap->pm_stats.wired_count--;
4291 if (opte2 & PTE2_A)
4292 vm_page_aflag_set(m, PGA_REFERENCED);
4293
4294 /*
4295 * Update the vm_page_t clean and reference bits.
4296 */
4297 if (pte2_is_dirty(opte2))
4298 vm_page_dirty(m);
4299 pmap_unuse_pt2(pmap, pv->pv_va, &free);
4300 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4301 free_pv_entry(pmap, pv);
4302 PMAP_UNLOCK(pmap);
4303 }
4304 vm_page_aflag_clear(m, PGA_WRITEABLE);
4305 sched_unpin();
4306 rw_wunlock(&pvh_global_lock);
4307 vm_page_free_pages_toq(&free, false);
4308 }
4309
4310 /*
4311 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4312 * good coding style, a.k.a. 80 character line width limit hell.
4313 */
4314 static __inline void
pmap_remove_pte1_quick(pmap_t pmap,pt1_entry_t pte1,pv_entry_t pv,struct spglist * free)4315 pmap_remove_pte1_quick(pmap_t pmap, pt1_entry_t pte1, pv_entry_t pv,
4316 struct spglist *free)
4317 {
4318 vm_paddr_t pa;
4319 vm_page_t m, mt, mpt2pg;
4320 struct md_page *pvh;
4321
4322 pa = pte1_pa(pte1);
4323 m = PHYS_TO_VM_PAGE(pa);
4324
4325 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4326 __func__, m, m->phys_addr, pa));
4327 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4328 m < &vm_page_array[vm_page_array_size],
4329 ("%s: bad pte1 %#x", __func__, pte1));
4330
4331 if (pte1_is_dirty(pte1)) {
4332 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4333 vm_page_dirty(mt);
4334 }
4335
4336 pmap->pm_stats.resident_count -= PTE1_SIZE / PAGE_SIZE;
4337 pvh = pa_to_pvh(pa);
4338 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4339 if (TAILQ_EMPTY(&pvh->pv_list)) {
4340 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4341 if (TAILQ_EMPTY(&mt->md.pv_list))
4342 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4343 }
4344 mpt2pg = pmap_pt2_page(pmap, pv->pv_va);
4345 if (mpt2pg != NULL)
4346 pmap_unwire_pt2_all(pmap, pv->pv_va, mpt2pg, free);
4347 }
4348
4349 /*
4350 * Just subroutine for pmap_remove_pages() to reasonably satisfy
4351 * good coding style, a.k.a. 80 character line width limit hell.
4352 */
4353 static __inline void
pmap_remove_pte2_quick(pmap_t pmap,pt2_entry_t pte2,pv_entry_t pv,struct spglist * free)4354 pmap_remove_pte2_quick(pmap_t pmap, pt2_entry_t pte2, pv_entry_t pv,
4355 struct spglist *free)
4356 {
4357 vm_paddr_t pa;
4358 vm_page_t m;
4359 struct md_page *pvh;
4360
4361 pa = pte2_pa(pte2);
4362 m = PHYS_TO_VM_PAGE(pa);
4363
4364 KASSERT(m->phys_addr == pa, ("%s: vm_page_t %p addr mismatch %#x %#x",
4365 __func__, m, m->phys_addr, pa));
4366 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4367 m < &vm_page_array[vm_page_array_size],
4368 ("%s: bad pte2 %#x", __func__, pte2));
4369
4370 if (pte2_is_dirty(pte2))
4371 vm_page_dirty(m);
4372
4373 pmap->pm_stats.resident_count--;
4374 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4375 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
4376 pvh = pa_to_pvh(pa);
4377 if (TAILQ_EMPTY(&pvh->pv_list))
4378 vm_page_aflag_clear(m, PGA_WRITEABLE);
4379 }
4380 pmap_unuse_pt2(pmap, pv->pv_va, free);
4381 }
4382
4383 /*
4384 * Remove all pages from specified address space this aids process
4385 * exit speeds. Also, this code is special cased for current process
4386 * only, but can have the more generic (and slightly slower) mode enabled.
4387 * This is much faster than pmap_remove in the case of running down
4388 * an entire address space.
4389 */
4390 void
pmap_remove_pages(pmap_t pmap)4391 pmap_remove_pages(pmap_t pmap)
4392 {
4393 pt1_entry_t *pte1p, pte1;
4394 pt2_entry_t *pte2p, pte2;
4395 pv_entry_t pv;
4396 struct pv_chunk *pc, *npc;
4397 struct spglist free;
4398 int field, idx;
4399 int32_t bit;
4400 uint32_t inuse, bitmask;
4401 bool allfree;
4402
4403 /*
4404 * Assert that the given pmap is only active on the current
4405 * CPU. Unfortunately, we cannot block another CPU from
4406 * activating the pmap while this function is executing.
4407 */
4408 KASSERT(pmap == vmspace_pmap(curthread->td_proc->p_vmspace),
4409 ("%s: non-current pmap %p", __func__, pmap));
4410 #if defined(SMP) && defined(INVARIANTS)
4411 {
4412 cpuset_t other_cpus;
4413
4414 sched_pin();
4415 other_cpus = pmap->pm_active;
4416 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
4417 sched_unpin();
4418 KASSERT(CPU_EMPTY(&other_cpus),
4419 ("%s: pmap %p active on other cpus", __func__, pmap));
4420 }
4421 #endif
4422 SLIST_INIT(&free);
4423 rw_wlock(&pvh_global_lock);
4424 PMAP_LOCK(pmap);
4425 sched_pin();
4426 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4427 KASSERT(pc->pc_pmap == pmap, ("%s: wrong pmap %p %p",
4428 __func__, pmap, pc->pc_pmap));
4429 allfree = true;
4430 for (field = 0; field < _NPCM; field++) {
4431 inuse = (~(pc->pc_map[field])) & pc_freemask[field];
4432 while (inuse != 0) {
4433 bit = ffs(inuse) - 1;
4434 bitmask = 1UL << bit;
4435 idx = field * 32 + bit;
4436 pv = &pc->pc_pventry[idx];
4437 inuse &= ~bitmask;
4438
4439 /*
4440 * Note that we cannot remove wired pages
4441 * from a process' mapping at this time
4442 */
4443 pte1p = pmap_pte1(pmap, pv->pv_va);
4444 pte1 = pte1_load(pte1p);
4445 if (pte1_is_section(pte1)) {
4446 if (pte1_is_wired(pte1)) {
4447 allfree = false;
4448 continue;
4449 }
4450 pte1_clear(pte1p);
4451 pmap_remove_pte1_quick(pmap, pte1, pv,
4452 &free);
4453 }
4454 else if (pte1_is_link(pte1)) {
4455 pte2p = pt2map_entry(pv->pv_va);
4456 pte2 = pte2_load(pte2p);
4457
4458 if (!pte2_is_valid(pte2)) {
4459 printf("%s: pmap %p va %#x "
4460 "pte2 %#x\n", __func__,
4461 pmap, pv->pv_va, pte2);
4462 panic("bad pte2");
4463 }
4464
4465 if (pte2_is_wired(pte2)) {
4466 allfree = false;
4467 continue;
4468 }
4469 pte2_clear(pte2p);
4470 pmap_remove_pte2_quick(pmap, pte2, pv,
4471 &free);
4472 } else {
4473 printf("%s: pmap %p va %#x pte1 %#x\n",
4474 __func__, pmap, pv->pv_va, pte1);
4475 panic("bad pte1");
4476 }
4477
4478 /* Mark free */
4479 PV_STAT(pv_entry_frees++);
4480 PV_STAT(pv_entry_spare++);
4481 pv_entry_count--;
4482 pc->pc_map[field] |= bitmask;
4483 }
4484 }
4485 if (allfree) {
4486 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4487 free_pv_chunk(pc);
4488 }
4489 }
4490 tlb_flush_all_ng_local();
4491 sched_unpin();
4492 rw_wunlock(&pvh_global_lock);
4493 PMAP_UNLOCK(pmap);
4494 vm_page_free_pages_toq(&free, false);
4495 }
4496
4497 /*
4498 * This code makes some *MAJOR* assumptions:
4499 * 1. Current pmap & pmap exists.
4500 * 2. Not wired.
4501 * 3. Read access.
4502 * 4. No L2 page table pages.
4503 * but is *MUCH* faster than pmap_enter...
4504 */
4505 static vm_page_t
pmap_enter_quick_locked(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,vm_page_t mpt2pg)4506 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4507 vm_prot_t prot, vm_page_t mpt2pg)
4508 {
4509 pt2_entry_t *pte2p, pte2;
4510 vm_paddr_t pa;
4511 struct spglist free;
4512 uint32_t l2prot;
4513
4514 KASSERT(!VA_IS_CLEANMAP(va) ||
4515 (m->oflags & VPO_UNMANAGED) != 0,
4516 ("%s: managed mapping within the clean submap", __func__));
4517 rw_assert(&pvh_global_lock, RA_WLOCKED);
4518 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4519
4520 /*
4521 * In the case that a L2 page table page is not
4522 * resident, we are creating it here.
4523 */
4524 if (va < VM_MAXUSER_ADDRESS) {
4525 u_int pte1_idx;
4526 pt1_entry_t pte1, *pte1p;
4527 vm_paddr_t pt2_pa;
4528
4529 /*
4530 * Get L1 page table things.
4531 */
4532 pte1_idx = pte1_index(va);
4533 pte1p = pmap_pte1(pmap, va);
4534 pte1 = pte1_load(pte1p);
4535
4536 if (mpt2pg && (mpt2pg->pindex == (pte1_idx & ~PT2PG_MASK))) {
4537 /*
4538 * Each of NPT2_IN_PG L2 page tables on the page can
4539 * come here. Make sure that associated L1 page table
4540 * link is established.
4541 *
4542 * QQQ: It comes that we don't establish all links to
4543 * L2 page tables for newly allocated L2 page
4544 * tables page.
4545 */
4546 KASSERT(!pte1_is_section(pte1),
4547 ("%s: pte1 %#x is section", __func__, pte1));
4548 if (!pte1_is_link(pte1)) {
4549 pt2_pa = page_pt2pa(VM_PAGE_TO_PHYS(mpt2pg),
4550 pte1_idx);
4551 pte1_store(pte1p, PTE1_LINK(pt2_pa));
4552 }
4553 pt2_wirecount_inc(mpt2pg, pte1_idx);
4554 } else {
4555 /*
4556 * If the L2 page table page is mapped, we just
4557 * increment the hold count, and activate it.
4558 */
4559 if (pte1_is_section(pte1)) {
4560 return (NULL);
4561 } else if (pte1_is_link(pte1)) {
4562 mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
4563 pt2_wirecount_inc(mpt2pg, pte1_idx);
4564 } else {
4565 mpt2pg = _pmap_allocpte2(pmap, va,
4566 PMAP_ENTER_NOSLEEP);
4567 if (mpt2pg == NULL)
4568 return (NULL);
4569 }
4570 }
4571 } else {
4572 mpt2pg = NULL;
4573 }
4574
4575 /*
4576 * This call to pt2map_entry() makes the assumption that we are
4577 * entering the page into the current pmap. In order to support
4578 * quick entry into any pmap, one would likely use pmap_pte2_quick().
4579 * But that isn't as quick as pt2map_entry().
4580 */
4581 pte2p = pt2map_entry(va);
4582 pte2 = pte2_load(pte2p);
4583 if (pte2_is_valid(pte2)) {
4584 if (mpt2pg != NULL) {
4585 /*
4586 * Remove extra pte2 reference
4587 */
4588 pt2_wirecount_dec(mpt2pg, pte1_index(va));
4589 mpt2pg = NULL;
4590 }
4591 return (NULL);
4592 }
4593
4594 /*
4595 * Enter on the PV list if part of our managed memory.
4596 */
4597 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4598 !pmap_try_insert_pv_entry(pmap, va, m)) {
4599 if (mpt2pg != NULL) {
4600 SLIST_INIT(&free);
4601 if (pmap_unwire_pt2(pmap, va, mpt2pg, &free)) {
4602 pmap_tlb_flush(pmap, va);
4603 vm_page_free_pages_toq(&free, false);
4604 }
4605
4606 mpt2pg = NULL;
4607 }
4608 return (NULL);
4609 }
4610
4611 /*
4612 * Increment counters
4613 */
4614 pmap->pm_stats.resident_count++;
4615
4616 /*
4617 * Now validate mapping with RO protection
4618 */
4619 pa = VM_PAGE_TO_PHYS(m);
4620 l2prot = PTE2_RO | PTE2_NM;
4621 if (va < VM_MAXUSER_ADDRESS)
4622 l2prot |= PTE2_U | PTE2_NG;
4623 if ((prot & VM_PROT_EXECUTE) == 0)
4624 l2prot |= PTE2_NX;
4625 else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
4626 /*
4627 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4628 * is set. QQQ: For more info, see comments in pmap_enter().
4629 */
4630 cache_icache_sync_fresh(va, pa, PAGE_SIZE);
4631 }
4632 pte2_store(pte2p, PTE2(pa, l2prot, vm_page_pte2_attr(m)));
4633
4634 return (mpt2pg);
4635 }
4636
4637 void
pmap_enter_quick(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot)4638 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4639 {
4640
4641 rw_wlock(&pvh_global_lock);
4642 PMAP_LOCK(pmap);
4643 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4644 rw_wunlock(&pvh_global_lock);
4645 PMAP_UNLOCK(pmap);
4646 }
4647
4648 /*
4649 * Tries to create a read- and/or execute-only 1 MB page mapping. Returns
4650 * true if successful. Returns false if (1) a mapping already exists at the
4651 * specified virtual address or (2) a PV entry cannot be allocated without
4652 * reclaiming another PV entry.
4653 */
4654 static bool
pmap_enter_1mpage(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot)4655 pmap_enter_1mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4656 {
4657 pt1_entry_t pte1;
4658 vm_paddr_t pa;
4659
4660 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4661 pa = VM_PAGE_TO_PHYS(m);
4662 pte1 = PTE1(pa, PTE1_NM | PTE1_RO, ATTR_TO_L1(vm_page_pte2_attr(m)));
4663 if ((prot & VM_PROT_EXECUTE) == 0)
4664 pte1 |= PTE1_NX;
4665 if (va < VM_MAXUSER_ADDRESS)
4666 pte1 |= PTE1_U;
4667 if (pmap != kernel_pmap)
4668 pte1 |= PTE1_NG;
4669 return (pmap_enter_pte1(pmap, va, pte1, PMAP_ENTER_NOSLEEP |
4670 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, m) == KERN_SUCCESS);
4671 }
4672
4673 /*
4674 * Tries to create the specified 1 MB page mapping. Returns KERN_SUCCESS if
4675 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
4676 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
4677 * a mapping already exists at the specified virtual address. Returns
4678 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NORECLAIM was specified and PV entry
4679 * allocation failed.
4680 */
4681 static int
pmap_enter_pte1(pmap_t pmap,vm_offset_t va,pt1_entry_t pte1,u_int flags,vm_page_t m)4682 pmap_enter_pte1(pmap_t pmap, vm_offset_t va, pt1_entry_t pte1, u_int flags,
4683 vm_page_t m)
4684 {
4685 struct spglist free;
4686 pt1_entry_t opte1, *pte1p;
4687 pt2_entry_t pte2, *pte2p;
4688 vm_offset_t cur, end;
4689 vm_page_t mt;
4690
4691 rw_assert(&pvh_global_lock, RA_WLOCKED);
4692 KASSERT((pte1 & (PTE1_NM | PTE1_RO)) == 0 ||
4693 (pte1 & (PTE1_NM | PTE1_RO)) == (PTE1_NM | PTE1_RO),
4694 ("%s: pte1 has inconsistent NM and RO attributes", __func__));
4695 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4696 pte1p = pmap_pte1(pmap, va);
4697 opte1 = pte1_load(pte1p);
4698 if (pte1_is_valid(opte1)) {
4699 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
4700 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p",
4701 __func__, va, pmap);
4702 return (KERN_FAILURE);
4703 }
4704 /* Break the existing mapping(s). */
4705 SLIST_INIT(&free);
4706 if (pte1_is_section(opte1)) {
4707 /*
4708 * If the section resulted from a promotion, then a
4709 * reserved PT page could be freed.
4710 */
4711 pmap_remove_pte1(pmap, pte1p, va, &free);
4712 } else {
4713 sched_pin();
4714 end = va + PTE1_SIZE;
4715 for (cur = va, pte2p = pmap_pte2_quick(pmap, va);
4716 cur != end; cur += PAGE_SIZE, pte2p++) {
4717 pte2 = pte2_load(pte2p);
4718 if (!pte2_is_valid(pte2))
4719 continue;
4720 if (pmap_remove_pte2(pmap, pte2p, cur, &free))
4721 break;
4722 }
4723 sched_unpin();
4724 }
4725 vm_page_free_pages_toq(&free, false);
4726 }
4727 if ((m->oflags & VPO_UNMANAGED) == 0) {
4728 /*
4729 * Abort this mapping if its PV entry could not be created.
4730 */
4731 if (!pmap_pv_insert_pte1(pmap, va, pte1, flags)) {
4732 CTR3(KTR_PMAP, "%s: failure for va %#lx in pmap %p",
4733 __func__, va, pmap);
4734 return (KERN_RESOURCE_SHORTAGE);
4735 }
4736 if ((pte1 & PTE1_RO) == 0) {
4737 for (mt = m; mt < &m[PTE1_SIZE / PAGE_SIZE]; mt++)
4738 vm_page_aflag_set(mt, PGA_WRITEABLE);
4739 }
4740 }
4741
4742 /*
4743 * Increment counters.
4744 */
4745 if (pte1_is_wired(pte1))
4746 pmap->pm_stats.wired_count += PTE1_SIZE / PAGE_SIZE;
4747 pmap->pm_stats.resident_count += PTE1_SIZE / PAGE_SIZE;
4748
4749 /*
4750 * Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
4751 * is set. QQQ: For more info, see comments in pmap_enter().
4752 */
4753 if ((pte1 & PTE1_NX) == 0 && m->md.pat_mode == VM_MEMATTR_WB_WA &&
4754 pmap != kernel_pmap && (!pte1_is_section(opte1) ||
4755 pte1_pa(opte1) != VM_PAGE_TO_PHYS(m) || (opte1 & PTE2_NX) != 0))
4756 cache_icache_sync_fresh(va, VM_PAGE_TO_PHYS(m), PTE1_SIZE);
4757
4758 /*
4759 * Map the section.
4760 */
4761 pte1_store(pte1p, pte1);
4762
4763 pmap_pte1_mappings++;
4764 CTR3(KTR_PMAP, "%s: success for va %#lx in pmap %p", __func__, va,
4765 pmap);
4766 return (KERN_SUCCESS);
4767 }
4768
4769 /*
4770 * Maps a sequence of resident pages belonging to the same object.
4771 * The sequence begins with the given page m_start. This page is
4772 * mapped at the given virtual address start. Each subsequent page is
4773 * mapped at a virtual address that is offset from start by the same
4774 * amount as the page is offset from m_start within the object. The
4775 * last page in the sequence is the page with the largest offset from
4776 * m_start that can be mapped at a virtual address less than the given
4777 * virtual address end. Not every virtual page between start and end
4778 * is mapped; only those for which a resident page exists with the
4779 * corresponding offset from m_start are mapped.
4780 */
4781 void
pmap_enter_object(pmap_t pmap,vm_offset_t start,vm_offset_t end,vm_page_t m_start,vm_prot_t prot)4782 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4783 vm_page_t m_start, vm_prot_t prot)
4784 {
4785 vm_offset_t va;
4786 vm_page_t m, mpt2pg;
4787 vm_pindex_t diff, psize;
4788
4789 PDEBUG(6, printf("%s: pmap %p start %#x end %#x m %p prot %#x\n",
4790 __func__, pmap, start, end, m_start, prot));
4791
4792 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4793 psize = atop(end - start);
4794 mpt2pg = NULL;
4795 m = m_start;
4796 rw_wlock(&pvh_global_lock);
4797 PMAP_LOCK(pmap);
4798 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4799 va = start + ptoa(diff);
4800 if ((va & PTE1_OFFSET) == 0 && va + PTE1_SIZE <= end &&
4801 m->psind == 1 && sp_enabled &&
4802 pmap_enter_1mpage(pmap, va, m, prot))
4803 m = &m[PTE1_SIZE / PAGE_SIZE - 1];
4804 else
4805 mpt2pg = pmap_enter_quick_locked(pmap, va, m, prot,
4806 mpt2pg);
4807 m = TAILQ_NEXT(m, listq);
4808 }
4809 rw_wunlock(&pvh_global_lock);
4810 PMAP_UNLOCK(pmap);
4811 }
4812
4813 /*
4814 * This code maps large physical mmap regions into the
4815 * processor address space. Note that some shortcuts
4816 * are taken, but the code works.
4817 */
4818 void
pmap_object_init_pt(pmap_t pmap,vm_offset_t addr,vm_object_t object,vm_pindex_t pindex,vm_size_t size)4819 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4820 vm_pindex_t pindex, vm_size_t size)
4821 {
4822 pt1_entry_t *pte1p;
4823 vm_paddr_t pa, pte2_pa;
4824 vm_page_t p;
4825 vm_memattr_t pat_mode;
4826 u_int l1attr, l1prot;
4827
4828 VM_OBJECT_ASSERT_WLOCKED(object);
4829 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4830 ("%s: non-device object", __func__));
4831 if ((addr & PTE1_OFFSET) == 0 && (size & PTE1_OFFSET) == 0) {
4832 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4833 return;
4834 p = vm_page_lookup(object, pindex);
4835 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4836 ("%s: invalid page %p", __func__, p));
4837 pat_mode = p->md.pat_mode;
4838
4839 /*
4840 * Abort the mapping if the first page is not physically
4841 * aligned to a 1MB page boundary.
4842 */
4843 pte2_pa = VM_PAGE_TO_PHYS(p);
4844 if (pte2_pa & PTE1_OFFSET)
4845 return;
4846
4847 /*
4848 * Skip the first page. Abort the mapping if the rest of
4849 * the pages are not physically contiguous or have differing
4850 * memory attributes.
4851 */
4852 p = TAILQ_NEXT(p, listq);
4853 for (pa = pte2_pa + PAGE_SIZE; pa < pte2_pa + size;
4854 pa += PAGE_SIZE) {
4855 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4856 ("%s: invalid page %p", __func__, p));
4857 if (pa != VM_PAGE_TO_PHYS(p) ||
4858 pat_mode != p->md.pat_mode)
4859 return;
4860 p = TAILQ_NEXT(p, listq);
4861 }
4862
4863 /*
4864 * Map using 1MB pages.
4865 *
4866 * QQQ: Well, we are mapping a section, so same condition must
4867 * be hold like during promotion. It looks that only RW mapping
4868 * is done here, so readonly mapping must be done elsewhere.
4869 */
4870 l1prot = PTE1_U | PTE1_NG | PTE1_RW | PTE1_M | PTE1_A;
4871 l1attr = ATTR_TO_L1(vm_memattr_to_pte2(pat_mode));
4872 PMAP_LOCK(pmap);
4873 for (pa = pte2_pa; pa < pte2_pa + size; pa += PTE1_SIZE) {
4874 pte1p = pmap_pte1(pmap, addr);
4875 if (!pte1_is_valid(pte1_load(pte1p))) {
4876 pte1_store(pte1p, PTE1(pa, l1prot, l1attr));
4877 pmap->pm_stats.resident_count += PTE1_SIZE /
4878 PAGE_SIZE;
4879 pmap_pte1_mappings++;
4880 }
4881 /* Else continue on if the PTE1 is already valid. */
4882 addr += PTE1_SIZE;
4883 }
4884 PMAP_UNLOCK(pmap);
4885 }
4886 }
4887
4888 /*
4889 * Do the things to protect a 1mpage in a process.
4890 */
4891 static void
pmap_protect_pte1(pmap_t pmap,pt1_entry_t * pte1p,vm_offset_t sva,vm_prot_t prot)4892 pmap_protect_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva,
4893 vm_prot_t prot)
4894 {
4895 pt1_entry_t npte1, opte1;
4896 vm_offset_t eva, va;
4897 vm_page_t m;
4898
4899 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4900 KASSERT((sva & PTE1_OFFSET) == 0,
4901 ("%s: sva is not 1mpage aligned", __func__));
4902
4903 opte1 = npte1 = pte1_load(pte1p);
4904 if (pte1_is_managed(opte1) && pte1_is_dirty(opte1)) {
4905 eva = sva + PTE1_SIZE;
4906 for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1));
4907 va < eva; va += PAGE_SIZE, m++)
4908 vm_page_dirty(m);
4909 }
4910 if ((prot & VM_PROT_WRITE) == 0)
4911 npte1 |= PTE1_RO | PTE1_NM;
4912 if ((prot & VM_PROT_EXECUTE) == 0)
4913 npte1 |= PTE1_NX;
4914
4915 /*
4916 * QQQ: Herein, execute permission is never set.
4917 * It only can be cleared. So, no icache
4918 * syncing is needed.
4919 */
4920
4921 if (npte1 != opte1) {
4922 pte1_store(pte1p, npte1);
4923 pmap_tlb_flush(pmap, sva);
4924 }
4925 }
4926
4927 /*
4928 * Set the physical protection on the
4929 * specified range of this map as requested.
4930 */
4931 void
pmap_protect(pmap_t pmap,vm_offset_t sva,vm_offset_t eva,vm_prot_t prot)4932 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4933 {
4934 bool pv_lists_locked;
4935 vm_offset_t nextva;
4936 pt1_entry_t *pte1p, pte1;
4937 pt2_entry_t *pte2p, opte2, npte2;
4938
4939 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4940 if (prot == VM_PROT_NONE) {
4941 pmap_remove(pmap, sva, eva);
4942 return;
4943 }
4944
4945 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
4946 (VM_PROT_WRITE | VM_PROT_EXECUTE))
4947 return;
4948
4949 if (pmap_is_current(pmap))
4950 pv_lists_locked = false;
4951 else {
4952 pv_lists_locked = true;
4953 resume:
4954 rw_wlock(&pvh_global_lock);
4955 sched_pin();
4956 }
4957
4958 PMAP_LOCK(pmap);
4959 for (; sva < eva; sva = nextva) {
4960 /*
4961 * Calculate address for next L2 page table.
4962 */
4963 nextva = pte1_trunc(sva + PTE1_SIZE);
4964 if (nextva < sva)
4965 nextva = eva;
4966
4967 pte1p = pmap_pte1(pmap, sva);
4968 pte1 = pte1_load(pte1p);
4969
4970 /*
4971 * Weed out invalid mappings. Note: we assume that L1 page
4972 * page table is always allocated, and in kernel virtual.
4973 */
4974 if (pte1 == 0)
4975 continue;
4976
4977 if (pte1_is_section(pte1)) {
4978 /*
4979 * Are we protecting the entire large page? If not,
4980 * demote the mapping and fall through.
4981 */
4982 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
4983 pmap_protect_pte1(pmap, pte1p, sva, prot);
4984 continue;
4985 } else {
4986 if (!pv_lists_locked) {
4987 pv_lists_locked = true;
4988 if (!rw_try_wlock(&pvh_global_lock)) {
4989 PMAP_UNLOCK(pmap);
4990 goto resume;
4991 }
4992 sched_pin();
4993 }
4994 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
4995 /*
4996 * The large page mapping
4997 * was destroyed.
4998 */
4999 continue;
5000 }
5001 #ifdef INVARIANTS
5002 else {
5003 /* Update pte1 after demotion */
5004 pte1 = pte1_load(pte1p);
5005 }
5006 #endif
5007 }
5008 }
5009
5010 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
5011 " is not link", __func__, pmap, sva, pte1, pte1p));
5012
5013 /*
5014 * Limit our scan to either the end of the va represented
5015 * by the current L2 page table page, or to the end of the
5016 * range being protected.
5017 */
5018 if (nextva > eva)
5019 nextva = eva;
5020
5021 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
5022 sva += PAGE_SIZE) {
5023 vm_page_t m;
5024
5025 opte2 = npte2 = pte2_load(pte2p);
5026 if (!pte2_is_valid(opte2))
5027 continue;
5028
5029 if ((prot & VM_PROT_WRITE) == 0) {
5030 if (pte2_is_managed(opte2) &&
5031 pte2_is_dirty(opte2)) {
5032 m = PHYS_TO_VM_PAGE(pte2_pa(opte2));
5033 vm_page_dirty(m);
5034 }
5035 npte2 |= PTE2_RO | PTE2_NM;
5036 }
5037
5038 if ((prot & VM_PROT_EXECUTE) == 0)
5039 npte2 |= PTE2_NX;
5040
5041 /*
5042 * QQQ: Herein, execute permission is never set.
5043 * It only can be cleared. So, no icache
5044 * syncing is needed.
5045 */
5046
5047 if (npte2 != opte2) {
5048 pte2_store(pte2p, npte2);
5049 pmap_tlb_flush(pmap, sva);
5050 }
5051 }
5052 }
5053 if (pv_lists_locked) {
5054 sched_unpin();
5055 rw_wunlock(&pvh_global_lock);
5056 }
5057 PMAP_UNLOCK(pmap);
5058 }
5059
5060 /*
5061 * pmap_pvh_wired_mappings:
5062 *
5063 * Return the updated number "count" of managed mappings that are wired.
5064 */
5065 static int
pmap_pvh_wired_mappings(struct md_page * pvh,int count)5066 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
5067 {
5068 pmap_t pmap;
5069 pt1_entry_t pte1;
5070 pt2_entry_t pte2;
5071 pv_entry_t pv;
5072
5073 rw_assert(&pvh_global_lock, RA_WLOCKED);
5074 sched_pin();
5075 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5076 pmap = PV_PMAP(pv);
5077 PMAP_LOCK(pmap);
5078 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5079 if (pte1_is_section(pte1)) {
5080 if (pte1_is_wired(pte1))
5081 count++;
5082 } else {
5083 KASSERT(pte1_is_link(pte1),
5084 ("%s: pte1 %#x is not link", __func__, pte1));
5085 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5086 if (pte2_is_wired(pte2))
5087 count++;
5088 }
5089 PMAP_UNLOCK(pmap);
5090 }
5091 sched_unpin();
5092 return (count);
5093 }
5094
5095 /*
5096 * pmap_page_wired_mappings:
5097 *
5098 * Return the number of managed mappings to the given physical page
5099 * that are wired.
5100 */
5101 int
pmap_page_wired_mappings(vm_page_t m)5102 pmap_page_wired_mappings(vm_page_t m)
5103 {
5104 int count;
5105
5106 count = 0;
5107 if ((m->oflags & VPO_UNMANAGED) != 0)
5108 return (count);
5109 rw_wlock(&pvh_global_lock);
5110 count = pmap_pvh_wired_mappings(&m->md, count);
5111 if ((m->flags & PG_FICTITIOUS) == 0) {
5112 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
5113 count);
5114 }
5115 rw_wunlock(&pvh_global_lock);
5116 return (count);
5117 }
5118
5119 /*
5120 * Returns true if any of the given mappings were used to modify
5121 * physical memory. Otherwise, returns false. Both page and 1mpage
5122 * mappings are supported.
5123 */
5124 static bool
pmap_is_modified_pvh(struct md_page * pvh)5125 pmap_is_modified_pvh(struct md_page *pvh)
5126 {
5127 pv_entry_t pv;
5128 pt1_entry_t pte1;
5129 pt2_entry_t pte2;
5130 pmap_t pmap;
5131 bool rv;
5132
5133 rw_assert(&pvh_global_lock, RA_WLOCKED);
5134 rv = false;
5135 sched_pin();
5136 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5137 pmap = PV_PMAP(pv);
5138 PMAP_LOCK(pmap);
5139 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5140 if (pte1_is_section(pte1)) {
5141 rv = pte1_is_dirty(pte1);
5142 } else {
5143 KASSERT(pte1_is_link(pte1),
5144 ("%s: pte1 %#x is not link", __func__, pte1));
5145 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5146 rv = pte2_is_dirty(pte2);
5147 }
5148 PMAP_UNLOCK(pmap);
5149 if (rv)
5150 break;
5151 }
5152 sched_unpin();
5153 return (rv);
5154 }
5155
5156 /*
5157 * pmap_is_modified:
5158 *
5159 * Return whether or not the specified physical page was modified
5160 * in any physical maps.
5161 */
5162 bool
pmap_is_modified(vm_page_t m)5163 pmap_is_modified(vm_page_t m)
5164 {
5165 bool rv;
5166
5167 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5168 ("%s: page %p is not managed", __func__, m));
5169
5170 /*
5171 * If the page is not busied then this check is racy.
5172 */
5173 if (!pmap_page_is_write_mapped(m))
5174 return (false);
5175 rw_wlock(&pvh_global_lock);
5176 rv = pmap_is_modified_pvh(&m->md) ||
5177 ((m->flags & PG_FICTITIOUS) == 0 &&
5178 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5179 rw_wunlock(&pvh_global_lock);
5180 return (rv);
5181 }
5182
5183 /*
5184 * pmap_is_prefaultable:
5185 *
5186 * Return whether or not the specified virtual address is eligible
5187 * for prefault.
5188 */
5189 bool
pmap_is_prefaultable(pmap_t pmap,vm_offset_t addr)5190 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5191 {
5192 pt1_entry_t pte1;
5193 pt2_entry_t pte2;
5194 bool rv;
5195
5196 rv = false;
5197 PMAP_LOCK(pmap);
5198 pte1 = pte1_load(pmap_pte1(pmap, addr));
5199 if (pte1_is_link(pte1)) {
5200 pte2 = pte2_load(pt2map_entry(addr));
5201 rv = !pte2_is_valid(pte2) ;
5202 }
5203 PMAP_UNLOCK(pmap);
5204 return (rv);
5205 }
5206
5207 /*
5208 * Returns true if any of the given mappings were referenced and false
5209 * otherwise. Both page and 1mpage mappings are supported.
5210 */
5211 static bool
pmap_is_referenced_pvh(struct md_page * pvh)5212 pmap_is_referenced_pvh(struct md_page *pvh)
5213 {
5214
5215 pv_entry_t pv;
5216 pt1_entry_t pte1;
5217 pt2_entry_t pte2;
5218 pmap_t pmap;
5219 bool rv;
5220
5221 rw_assert(&pvh_global_lock, RA_WLOCKED);
5222 rv = false;
5223 sched_pin();
5224 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5225 pmap = PV_PMAP(pv);
5226 PMAP_LOCK(pmap);
5227 pte1 = pte1_load(pmap_pte1(pmap, pv->pv_va));
5228 if (pte1_is_section(pte1)) {
5229 rv = (pte1 & (PTE1_A | PTE1_V)) == (PTE1_A | PTE1_V);
5230 } else {
5231 pte2 = pte2_load(pmap_pte2_quick(pmap, pv->pv_va));
5232 rv = (pte2 & (PTE2_A | PTE2_V)) == (PTE2_A | PTE2_V);
5233 }
5234 PMAP_UNLOCK(pmap);
5235 if (rv)
5236 break;
5237 }
5238 sched_unpin();
5239 return (rv);
5240 }
5241
5242 /*
5243 * pmap_is_referenced:
5244 *
5245 * Return whether or not the specified physical page was referenced
5246 * in any physical maps.
5247 */
5248 bool
pmap_is_referenced(vm_page_t m)5249 pmap_is_referenced(vm_page_t m)
5250 {
5251 bool rv;
5252
5253 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5254 ("%s: page %p is not managed", __func__, m));
5255 rw_wlock(&pvh_global_lock);
5256 rv = pmap_is_referenced_pvh(&m->md) ||
5257 ((m->flags & PG_FICTITIOUS) == 0 &&
5258 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5259 rw_wunlock(&pvh_global_lock);
5260 return (rv);
5261 }
5262
5263 /*
5264 * pmap_ts_referenced:
5265 *
5266 * Return a count of reference bits for a page, clearing those bits.
5267 * It is not necessary for every reference bit to be cleared, but it
5268 * is necessary that 0 only be returned when there are truly no
5269 * reference bits set.
5270 *
5271 * As an optimization, update the page's dirty field if a modified bit is
5272 * found while counting reference bits. This opportunistic update can be
5273 * performed at low cost and can eliminate the need for some future calls
5274 * to pmap_is_modified(). However, since this function stops after
5275 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5276 * dirty pages. Those dirty pages will only be detected by a future call
5277 * to pmap_is_modified().
5278 */
5279 int
pmap_ts_referenced(vm_page_t m)5280 pmap_ts_referenced(vm_page_t m)
5281 {
5282 struct md_page *pvh;
5283 pv_entry_t pv, pvf;
5284 pmap_t pmap;
5285 pt1_entry_t *pte1p, opte1;
5286 pt2_entry_t *pte2p, opte2;
5287 vm_paddr_t pa;
5288 int rtval = 0;
5289
5290 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5291 ("%s: page %p is not managed", __func__, m));
5292 pa = VM_PAGE_TO_PHYS(m);
5293 pvh = pa_to_pvh(pa);
5294 rw_wlock(&pvh_global_lock);
5295 sched_pin();
5296 if ((m->flags & PG_FICTITIOUS) != 0 ||
5297 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5298 goto small_mappings;
5299 pv = pvf;
5300 do {
5301 pmap = PV_PMAP(pv);
5302 PMAP_LOCK(pmap);
5303 pte1p = pmap_pte1(pmap, pv->pv_va);
5304 opte1 = pte1_load(pte1p);
5305 if (pte1_is_dirty(opte1)) {
5306 /*
5307 * Although "opte1" is mapping a 1MB page, because
5308 * this function is called at a 4KB page granularity,
5309 * we only update the 4KB page under test.
5310 */
5311 vm_page_dirty(m);
5312 }
5313 if ((opte1 & PTE1_A) != 0) {
5314 /*
5315 * Since this reference bit is shared by 256 4KB pages,
5316 * it should not be cleared every time it is tested.
5317 * Apply a simple "hash" function on the physical page
5318 * number, the virtual section number, and the pmap
5319 * address to select one 4KB page out of the 256
5320 * on which testing the reference bit will result
5321 * in clearing that bit. This function is designed
5322 * to avoid the selection of the same 4KB page
5323 * for every 1MB page mapping.
5324 *
5325 * On demotion, a mapping that hasn't been referenced
5326 * is simply destroyed. To avoid the possibility of a
5327 * subsequent page fault on a demoted wired mapping,
5328 * always leave its reference bit set. Moreover,
5329 * since the section is wired, the current state of
5330 * its reference bit won't affect page replacement.
5331 */
5332 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PTE1_SHIFT) ^
5333 (uintptr_t)pmap) & (NPTE2_IN_PG - 1)) == 0 &&
5334 !pte1_is_wired(opte1)) {
5335 pte1_clear_bit(pte1p, PTE1_A);
5336 pmap_tlb_flush(pmap, pv->pv_va);
5337 }
5338 rtval++;
5339 }
5340 PMAP_UNLOCK(pmap);
5341 /* Rotate the PV list if it has more than one entry. */
5342 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5343 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5344 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5345 }
5346 if (rtval >= PMAP_TS_REFERENCED_MAX)
5347 goto out;
5348 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5349 small_mappings:
5350 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5351 goto out;
5352 pv = pvf;
5353 do {
5354 pmap = PV_PMAP(pv);
5355 PMAP_LOCK(pmap);
5356 pte1p = pmap_pte1(pmap, pv->pv_va);
5357 KASSERT(pte1_is_link(pte1_load(pte1p)),
5358 ("%s: not found a link in page %p's pv list", __func__, m));
5359
5360 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5361 opte2 = pte2_load(pte2p);
5362 if (pte2_is_dirty(opte2))
5363 vm_page_dirty(m);
5364 if ((opte2 & PTE2_A) != 0) {
5365 pte2_clear_bit(pte2p, PTE2_A);
5366 pmap_tlb_flush(pmap, pv->pv_va);
5367 rtval++;
5368 }
5369 PMAP_UNLOCK(pmap);
5370 /* Rotate the PV list if it has more than one entry. */
5371 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5372 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5373 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5374 }
5375 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5376 PMAP_TS_REFERENCED_MAX);
5377 out:
5378 sched_unpin();
5379 rw_wunlock(&pvh_global_lock);
5380 return (rtval);
5381 }
5382
5383 /*
5384 * Clear the wired attribute from the mappings for the specified range of
5385 * addresses in the given pmap. Every valid mapping within that range
5386 * must have the wired attribute set. In contrast, invalid mappings
5387 * cannot have the wired attribute set, so they are ignored.
5388 *
5389 * The wired attribute of the page table entry is not a hardware feature,
5390 * so there is no need to invalidate any TLB entries.
5391 */
5392 void
pmap_unwire(pmap_t pmap,vm_offset_t sva,vm_offset_t eva)5393 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5394 {
5395 vm_offset_t nextva;
5396 pt1_entry_t *pte1p, pte1;
5397 pt2_entry_t *pte2p, pte2;
5398 bool pv_lists_locked;
5399
5400 if (pmap_is_current(pmap))
5401 pv_lists_locked = false;
5402 else {
5403 pv_lists_locked = true;
5404 resume:
5405 rw_wlock(&pvh_global_lock);
5406 sched_pin();
5407 }
5408 PMAP_LOCK(pmap);
5409 for (; sva < eva; sva = nextva) {
5410 nextva = pte1_trunc(sva + PTE1_SIZE);
5411 if (nextva < sva)
5412 nextva = eva;
5413
5414 pte1p = pmap_pte1(pmap, sva);
5415 pte1 = pte1_load(pte1p);
5416
5417 /*
5418 * Weed out invalid mappings. Note: we assume that L1 page
5419 * page table is always allocated, and in kernel virtual.
5420 */
5421 if (pte1 == 0)
5422 continue;
5423
5424 if (pte1_is_section(pte1)) {
5425 if (!pte1_is_wired(pte1))
5426 panic("%s: pte1 %#x not wired", __func__, pte1);
5427
5428 /*
5429 * Are we unwiring the entire large page? If not,
5430 * demote the mapping and fall through.
5431 */
5432 if (sva + PTE1_SIZE == nextva && eva >= nextva) {
5433 pte1_clear_bit(pte1p, PTE1_W);
5434 pmap->pm_stats.wired_count -= PTE1_SIZE /
5435 PAGE_SIZE;
5436 continue;
5437 } else {
5438 if (!pv_lists_locked) {
5439 pv_lists_locked = true;
5440 if (!rw_try_wlock(&pvh_global_lock)) {
5441 PMAP_UNLOCK(pmap);
5442 /* Repeat sva. */
5443 goto resume;
5444 }
5445 sched_pin();
5446 }
5447 if (!pmap_demote_pte1(pmap, pte1p, sva))
5448 panic("%s: demotion failed", __func__);
5449 #ifdef INVARIANTS
5450 else {
5451 /* Update pte1 after demotion */
5452 pte1 = pte1_load(pte1p);
5453 }
5454 #endif
5455 }
5456 }
5457
5458 KASSERT(pte1_is_link(pte1), ("%s: pmap %p va %#x pte1 %#x at %p"
5459 " is not link", __func__, pmap, sva, pte1, pte1p));
5460
5461 /*
5462 * Limit our scan to either the end of the va represented
5463 * by the current L2 page table page, or to the end of the
5464 * range being protected.
5465 */
5466 if (nextva > eva)
5467 nextva = eva;
5468
5469 for (pte2p = pmap_pte2_quick(pmap, sva); sva != nextva; pte2p++,
5470 sva += PAGE_SIZE) {
5471 pte2 = pte2_load(pte2p);
5472 if (!pte2_is_valid(pte2))
5473 continue;
5474 if (!pte2_is_wired(pte2))
5475 panic("%s: pte2 %#x is missing PTE2_W",
5476 __func__, pte2);
5477
5478 /*
5479 * PTE2_W must be cleared atomically. Although the pmap
5480 * lock synchronizes access to PTE2_W, another processor
5481 * could be changing PTE2_NM and/or PTE2_A concurrently.
5482 */
5483 pte2_clear_bit(pte2p, PTE2_W);
5484 pmap->pm_stats.wired_count--;
5485 }
5486 }
5487 if (pv_lists_locked) {
5488 sched_unpin();
5489 rw_wunlock(&pvh_global_lock);
5490 }
5491 PMAP_UNLOCK(pmap);
5492 }
5493
5494 /*
5495 * Clear the write and modified bits in each of the given page's mappings.
5496 */
5497 void
pmap_remove_write(vm_page_t m)5498 pmap_remove_write(vm_page_t m)
5499 {
5500 struct md_page *pvh;
5501 pv_entry_t next_pv, pv;
5502 pmap_t pmap;
5503 pt1_entry_t *pte1p;
5504 pt2_entry_t *pte2p, opte2;
5505 vm_offset_t va;
5506
5507 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5508 ("%s: page %p is not managed", __func__, m));
5509 vm_page_assert_busied(m);
5510
5511 if (!pmap_page_is_write_mapped(m))
5512 return;
5513 rw_wlock(&pvh_global_lock);
5514 sched_pin();
5515 if ((m->flags & PG_FICTITIOUS) != 0)
5516 goto small_mappings;
5517 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5518 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5519 va = pv->pv_va;
5520 pmap = PV_PMAP(pv);
5521 PMAP_LOCK(pmap);
5522 pte1p = pmap_pte1(pmap, va);
5523 if (!(pte1_load(pte1p) & PTE1_RO))
5524 (void)pmap_demote_pte1(pmap, pte1p, va);
5525 PMAP_UNLOCK(pmap);
5526 }
5527 small_mappings:
5528 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5529 pmap = PV_PMAP(pv);
5530 PMAP_LOCK(pmap);
5531 pte1p = pmap_pte1(pmap, pv->pv_va);
5532 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5533 " a section in page %p's pv list", __func__, m));
5534 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5535 opte2 = pte2_load(pte2p);
5536 if (!(opte2 & PTE2_RO)) {
5537 pte2_store(pte2p, opte2 | PTE2_RO | PTE2_NM);
5538 if (pte2_is_dirty(opte2))
5539 vm_page_dirty(m);
5540 pmap_tlb_flush(pmap, pv->pv_va);
5541 }
5542 PMAP_UNLOCK(pmap);
5543 }
5544 vm_page_aflag_clear(m, PGA_WRITEABLE);
5545 sched_unpin();
5546 rw_wunlock(&pvh_global_lock);
5547 }
5548
5549 /*
5550 * Apply the given advice to the specified range of addresses within the
5551 * given pmap. Depending on the advice, clear the referenced and/or
5552 * modified flags in each mapping and set the mapped page's dirty field.
5553 */
5554 void
pmap_advise(pmap_t pmap,vm_offset_t sva,vm_offset_t eva,int advice)5555 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5556 {
5557 pt1_entry_t *pte1p, opte1;
5558 pt2_entry_t *pte2p, pte2;
5559 vm_offset_t pdnxt;
5560 vm_page_t m;
5561 bool pv_lists_locked;
5562
5563 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5564 return;
5565 if (pmap_is_current(pmap))
5566 pv_lists_locked = false;
5567 else {
5568 pv_lists_locked = true;
5569 resume:
5570 rw_wlock(&pvh_global_lock);
5571 sched_pin();
5572 }
5573 PMAP_LOCK(pmap);
5574 for (; sva < eva; sva = pdnxt) {
5575 pdnxt = pte1_trunc(sva + PTE1_SIZE);
5576 if (pdnxt < sva)
5577 pdnxt = eva;
5578 pte1p = pmap_pte1(pmap, sva);
5579 opte1 = pte1_load(pte1p);
5580 if (!pte1_is_valid(opte1)) /* XXX */
5581 continue;
5582 else if (pte1_is_section(opte1)) {
5583 if (!pte1_is_managed(opte1))
5584 continue;
5585 if (!pv_lists_locked) {
5586 pv_lists_locked = true;
5587 if (!rw_try_wlock(&pvh_global_lock)) {
5588 PMAP_UNLOCK(pmap);
5589 goto resume;
5590 }
5591 sched_pin();
5592 }
5593 if (!pmap_demote_pte1(pmap, pte1p, sva)) {
5594 /*
5595 * The large page mapping was destroyed.
5596 */
5597 continue;
5598 }
5599
5600 /*
5601 * Unless the page mappings are wired, remove the
5602 * mapping to a single page so that a subsequent
5603 * access may repromote. Since the underlying L2 page
5604 * table is fully populated, this removal never
5605 * frees a L2 page table page.
5606 */
5607 if (!pte1_is_wired(opte1)) {
5608 pte2p = pmap_pte2_quick(pmap, sva);
5609 KASSERT(pte2_is_valid(pte2_load(pte2p)),
5610 ("%s: invalid PTE2", __func__));
5611 pmap_remove_pte2(pmap, pte2p, sva, NULL);
5612 }
5613 }
5614 if (pdnxt > eva)
5615 pdnxt = eva;
5616 for (pte2p = pmap_pte2_quick(pmap, sva); sva != pdnxt; pte2p++,
5617 sva += PAGE_SIZE) {
5618 pte2 = pte2_load(pte2p);
5619 if (!pte2_is_valid(pte2) || !pte2_is_managed(pte2))
5620 continue;
5621 else if (pte2_is_dirty(pte2)) {
5622 if (advice == MADV_DONTNEED) {
5623 /*
5624 * Future calls to pmap_is_modified()
5625 * can be avoided by making the page
5626 * dirty now.
5627 */
5628 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
5629 vm_page_dirty(m);
5630 }
5631 pte2_set_bit(pte2p, PTE2_NM);
5632 pte2_clear_bit(pte2p, PTE2_A);
5633 } else if ((pte2 & PTE2_A) != 0)
5634 pte2_clear_bit(pte2p, PTE2_A);
5635 else
5636 continue;
5637 pmap_tlb_flush(pmap, sva);
5638 }
5639 }
5640 if (pv_lists_locked) {
5641 sched_unpin();
5642 rw_wunlock(&pvh_global_lock);
5643 }
5644 PMAP_UNLOCK(pmap);
5645 }
5646
5647 /*
5648 * Clear the modify bits on the specified physical page.
5649 */
5650 void
pmap_clear_modify(vm_page_t m)5651 pmap_clear_modify(vm_page_t m)
5652 {
5653 struct md_page *pvh;
5654 pv_entry_t next_pv, pv;
5655 pmap_t pmap;
5656 pt1_entry_t *pte1p, opte1;
5657 pt2_entry_t *pte2p, opte2;
5658 vm_offset_t va;
5659
5660 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5661 ("%s: page %p is not managed", __func__, m));
5662 vm_page_assert_busied(m);
5663
5664 if (!pmap_page_is_write_mapped(m))
5665 return;
5666 rw_wlock(&pvh_global_lock);
5667 sched_pin();
5668 if ((m->flags & PG_FICTITIOUS) != 0)
5669 goto small_mappings;
5670 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5671 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5672 va = pv->pv_va;
5673 pmap = PV_PMAP(pv);
5674 PMAP_LOCK(pmap);
5675 pte1p = pmap_pte1(pmap, va);
5676 opte1 = pte1_load(pte1p);
5677 if (!(opte1 & PTE1_RO)) {
5678 if (pmap_demote_pte1(pmap, pte1p, va) &&
5679 !pte1_is_wired(opte1)) {
5680 /*
5681 * Write protect the mapping to a
5682 * single page so that a subsequent
5683 * write access may repromote.
5684 */
5685 va += VM_PAGE_TO_PHYS(m) - pte1_pa(opte1);
5686 pte2p = pmap_pte2_quick(pmap, va);
5687 opte2 = pte2_load(pte2p);
5688 if ((opte2 & PTE2_V)) {
5689 pte2_set_bit(pte2p, PTE2_NM | PTE2_RO);
5690 vm_page_dirty(m);
5691 pmap_tlb_flush(pmap, va);
5692 }
5693 }
5694 }
5695 PMAP_UNLOCK(pmap);
5696 }
5697 small_mappings:
5698 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5699 pmap = PV_PMAP(pv);
5700 PMAP_LOCK(pmap);
5701 pte1p = pmap_pte1(pmap, pv->pv_va);
5702 KASSERT(!pte1_is_section(pte1_load(pte1p)), ("%s: found"
5703 " a section in page %p's pv list", __func__, m));
5704 pte2p = pmap_pte2_quick(pmap, pv->pv_va);
5705 if (pte2_is_dirty(pte2_load(pte2p))) {
5706 pte2_set_bit(pte2p, PTE2_NM);
5707 pmap_tlb_flush(pmap, pv->pv_va);
5708 }
5709 PMAP_UNLOCK(pmap);
5710 }
5711 sched_unpin();
5712 rw_wunlock(&pvh_global_lock);
5713 }
5714
5715 /*
5716 * Sets the memory attribute for the specified page.
5717 */
5718 void
pmap_page_set_memattr(vm_page_t m,vm_memattr_t ma)5719 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5720 {
5721 pt2_entry_t *cmap2_pte2p;
5722 vm_memattr_t oma;
5723 vm_paddr_t pa;
5724 struct pcpu *pc;
5725
5726 oma = m->md.pat_mode;
5727 m->md.pat_mode = ma;
5728
5729 CTR5(KTR_PMAP, "%s: page %p - 0x%08X oma: %d, ma: %d", __func__, m,
5730 VM_PAGE_TO_PHYS(m), oma, ma);
5731 if ((m->flags & PG_FICTITIOUS) != 0)
5732 return;
5733 #if 0
5734 /*
5735 * If "m" is a normal page, flush it from the cache.
5736 *
5737 * First, try to find an existing mapping of the page by sf
5738 * buffer. sf_buf_invalidate_cache() modifies mapping and
5739 * flushes the cache.
5740 */
5741 if (sf_buf_invalidate_cache(m, oma))
5742 return;
5743 #endif
5744 /*
5745 * If page is not mapped by sf buffer, map the page
5746 * transient and do invalidation.
5747 */
5748 if (ma != oma) {
5749 pa = VM_PAGE_TO_PHYS(m);
5750 sched_pin();
5751 pc = get_pcpu();
5752 cmap2_pte2p = pc->pc_cmap2_pte2p;
5753 mtx_lock(&pc->pc_cmap_lock);
5754 if (pte2_load(cmap2_pte2p) != 0)
5755 panic("%s: CMAP2 busy", __func__);
5756 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW,
5757 vm_memattr_to_pte2(ma)));
5758 dcache_wbinv_poc((vm_offset_t)pc->pc_cmap2_addr, pa, PAGE_SIZE);
5759 pte2_clear(cmap2_pte2p);
5760 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5761 sched_unpin();
5762 mtx_unlock(&pc->pc_cmap_lock);
5763 }
5764 }
5765
5766 /*
5767 * Miscellaneous support routines follow
5768 */
5769
5770 /*
5771 * Returns true if the given page is mapped individually or as part of
5772 * a 1mpage. Otherwise, returns false.
5773 */
5774 bool
pmap_page_is_mapped(vm_page_t m)5775 pmap_page_is_mapped(vm_page_t m)
5776 {
5777 bool rv;
5778
5779 if ((m->oflags & VPO_UNMANAGED) != 0)
5780 return (false);
5781 rw_wlock(&pvh_global_lock);
5782 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5783 ((m->flags & PG_FICTITIOUS) == 0 &&
5784 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5785 rw_wunlock(&pvh_global_lock);
5786 return (rv);
5787 }
5788
5789 /*
5790 * Returns true if the pmap's pv is one of the first
5791 * 16 pvs linked to from this page. This count may
5792 * be changed upwards or downwards in the future; it
5793 * is only necessary that true be returned for a small
5794 * subset of pmaps for proper page aging.
5795 */
5796 bool
pmap_page_exists_quick(pmap_t pmap,vm_page_t m)5797 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5798 {
5799 struct md_page *pvh;
5800 pv_entry_t pv;
5801 int loops = 0;
5802 bool rv;
5803
5804 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5805 ("%s: page %p is not managed", __func__, m));
5806 rv = false;
5807 rw_wlock(&pvh_global_lock);
5808 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5809 if (PV_PMAP(pv) == pmap) {
5810 rv = true;
5811 break;
5812 }
5813 loops++;
5814 if (loops >= 16)
5815 break;
5816 }
5817 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5818 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5819 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5820 if (PV_PMAP(pv) == pmap) {
5821 rv = true;
5822 break;
5823 }
5824 loops++;
5825 if (loops >= 16)
5826 break;
5827 }
5828 }
5829 rw_wunlock(&pvh_global_lock);
5830 return (rv);
5831 }
5832
5833 /*
5834 * pmap_zero_page zeros the specified hardware page by mapping
5835 * the page into KVM and using bzero to clear its contents.
5836 */
5837 void
pmap_zero_page(vm_page_t m)5838 pmap_zero_page(vm_page_t m)
5839 {
5840 pt2_entry_t *cmap2_pte2p;
5841 struct pcpu *pc;
5842
5843 sched_pin();
5844 pc = get_pcpu();
5845 cmap2_pte2p = pc->pc_cmap2_pte2p;
5846 mtx_lock(&pc->pc_cmap_lock);
5847 if (pte2_load(cmap2_pte2p) != 0)
5848 panic("%s: CMAP2 busy", __func__);
5849 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5850 vm_page_pte2_attr(m)));
5851 pagezero(pc->pc_cmap2_addr);
5852 pte2_clear(cmap2_pte2p);
5853 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5854 sched_unpin();
5855 mtx_unlock(&pc->pc_cmap_lock);
5856 }
5857
5858 /*
5859 * pmap_zero_page_area zeros the specified hardware page by mapping
5860 * the page into KVM and using bzero to clear its contents.
5861 *
5862 * off and size may not cover an area beyond a single hardware page.
5863 */
5864 void
pmap_zero_page_area(vm_page_t m,int off,int size)5865 pmap_zero_page_area(vm_page_t m, int off, int size)
5866 {
5867 pt2_entry_t *cmap2_pte2p;
5868 struct pcpu *pc;
5869
5870 sched_pin();
5871 pc = get_pcpu();
5872 cmap2_pte2p = pc->pc_cmap2_pte2p;
5873 mtx_lock(&pc->pc_cmap_lock);
5874 if (pte2_load(cmap2_pte2p) != 0)
5875 panic("%s: CMAP2 busy", __func__);
5876 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5877 vm_page_pte2_attr(m)));
5878 if (off == 0 && size == PAGE_SIZE)
5879 pagezero(pc->pc_cmap2_addr);
5880 else
5881 bzero(pc->pc_cmap2_addr + off, size);
5882 pte2_clear(cmap2_pte2p);
5883 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5884 sched_unpin();
5885 mtx_unlock(&pc->pc_cmap_lock);
5886 }
5887
5888 /*
5889 * pmap_copy_page copies the specified (machine independent)
5890 * page by mapping the page into virtual memory and using
5891 * bcopy to copy the page, one machine dependent page at a
5892 * time.
5893 */
5894 void
pmap_copy_page(vm_page_t src,vm_page_t dst)5895 pmap_copy_page(vm_page_t src, vm_page_t dst)
5896 {
5897 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5898 struct pcpu *pc;
5899
5900 sched_pin();
5901 pc = get_pcpu();
5902 cmap1_pte2p = pc->pc_cmap1_pte2p;
5903 cmap2_pte2p = pc->pc_cmap2_pte2p;
5904 mtx_lock(&pc->pc_cmap_lock);
5905 if (pte2_load(cmap1_pte2p) != 0)
5906 panic("%s: CMAP1 busy", __func__);
5907 if (pte2_load(cmap2_pte2p) != 0)
5908 panic("%s: CMAP2 busy", __func__);
5909 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(src),
5910 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(src)));
5911 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(dst),
5912 PTE2_AP_KRW, vm_page_pte2_attr(dst)));
5913 bcopy(pc->pc_cmap1_addr, pc->pc_cmap2_addr, PAGE_SIZE);
5914 pte2_clear(cmap1_pte2p);
5915 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
5916 pte2_clear(cmap2_pte2p);
5917 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5918 sched_unpin();
5919 mtx_unlock(&pc->pc_cmap_lock);
5920 }
5921
5922 int unmapped_buf_allowed = 1;
5923
5924 void
pmap_copy_pages(vm_page_t ma[],vm_offset_t a_offset,vm_page_t mb[],vm_offset_t b_offset,int xfersize)5925 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5926 vm_offset_t b_offset, int xfersize)
5927 {
5928 pt2_entry_t *cmap1_pte2p, *cmap2_pte2p;
5929 vm_page_t a_pg, b_pg;
5930 char *a_cp, *b_cp;
5931 vm_offset_t a_pg_offset, b_pg_offset;
5932 struct pcpu *pc;
5933 int cnt;
5934
5935 sched_pin();
5936 pc = get_pcpu();
5937 cmap1_pte2p = pc->pc_cmap1_pte2p;
5938 cmap2_pte2p = pc->pc_cmap2_pte2p;
5939 mtx_lock(&pc->pc_cmap_lock);
5940 if (pte2_load(cmap1_pte2p) != 0)
5941 panic("pmap_copy_pages: CMAP1 busy");
5942 if (pte2_load(cmap2_pte2p) != 0)
5943 panic("pmap_copy_pages: CMAP2 busy");
5944 while (xfersize > 0) {
5945 a_pg = ma[a_offset >> PAGE_SHIFT];
5946 a_pg_offset = a_offset & PAGE_MASK;
5947 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5948 b_pg = mb[b_offset >> PAGE_SHIFT];
5949 b_pg_offset = b_offset & PAGE_MASK;
5950 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5951 pte2_store(cmap1_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(a_pg),
5952 PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(a_pg)));
5953 tlb_flush_local((vm_offset_t)pc->pc_cmap1_addr);
5954 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(b_pg),
5955 PTE2_AP_KRW, vm_page_pte2_attr(b_pg)));
5956 tlb_flush_local((vm_offset_t)pc->pc_cmap2_addr);
5957 a_cp = pc->pc_cmap1_addr + a_pg_offset;
5958 b_cp = pc->pc_cmap2_addr + b_pg_offset;
5959 bcopy(a_cp, b_cp, cnt);
5960 a_offset += cnt;
5961 b_offset += cnt;
5962 xfersize -= cnt;
5963 }
5964 pte2_clear(cmap1_pte2p);
5965 tlb_flush((vm_offset_t)pc->pc_cmap1_addr);
5966 pte2_clear(cmap2_pte2p);
5967 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
5968 sched_unpin();
5969 mtx_unlock(&pc->pc_cmap_lock);
5970 }
5971
5972 vm_offset_t
pmap_quick_enter_page(vm_page_t m)5973 pmap_quick_enter_page(vm_page_t m)
5974 {
5975 struct pcpu *pc;
5976 pt2_entry_t *pte2p;
5977
5978 critical_enter();
5979 pc = get_pcpu();
5980 pte2p = pc->pc_qmap_pte2p;
5981
5982 KASSERT(pte2_load(pte2p) == 0, ("%s: PTE2 busy", __func__));
5983
5984 pte2_store(pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
5985 vm_page_pte2_attr(m)));
5986 return (pc->pc_qmap_addr);
5987 }
5988
5989 void
pmap_quick_remove_page(vm_offset_t addr)5990 pmap_quick_remove_page(vm_offset_t addr)
5991 {
5992 struct pcpu *pc;
5993 pt2_entry_t *pte2p;
5994
5995 pc = get_pcpu();
5996 pte2p = pc->pc_qmap_pte2p;
5997
5998 KASSERT(addr == pc->pc_qmap_addr, ("%s: invalid address", __func__));
5999 KASSERT(pte2_load(pte2p) != 0, ("%s: PTE2 not in use", __func__));
6000
6001 pte2_clear(pte2p);
6002 tlb_flush(pc->pc_qmap_addr);
6003 critical_exit();
6004 }
6005
6006 /*
6007 * Copy the range specified by src_addr/len
6008 * from the source map to the range dst_addr/len
6009 * in the destination map.
6010 *
6011 * This routine is only advisory and need not do anything.
6012 */
6013 void
pmap_copy(pmap_t dst_pmap,pmap_t src_pmap,vm_offset_t dst_addr,vm_size_t len,vm_offset_t src_addr)6014 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6015 vm_offset_t src_addr)
6016 {
6017 struct spglist free;
6018 vm_offset_t addr;
6019 vm_offset_t end_addr = src_addr + len;
6020 vm_offset_t nextva;
6021
6022 if (dst_addr != src_addr)
6023 return;
6024
6025 if (!pmap_is_current(src_pmap))
6026 return;
6027
6028 rw_wlock(&pvh_global_lock);
6029 if (dst_pmap < src_pmap) {
6030 PMAP_LOCK(dst_pmap);
6031 PMAP_LOCK(src_pmap);
6032 } else {
6033 PMAP_LOCK(src_pmap);
6034 PMAP_LOCK(dst_pmap);
6035 }
6036 sched_pin();
6037 for (addr = src_addr; addr < end_addr; addr = nextva) {
6038 pt2_entry_t *src_pte2p, *dst_pte2p;
6039 vm_page_t dst_mpt2pg, src_mpt2pg;
6040 pt1_entry_t src_pte1;
6041 u_int pte1_idx;
6042
6043 KASSERT(addr < VM_MAXUSER_ADDRESS,
6044 ("%s: invalid to pmap_copy page tables", __func__));
6045
6046 nextva = pte1_trunc(addr + PTE1_SIZE);
6047 if (nextva < addr)
6048 nextva = end_addr;
6049
6050 pte1_idx = pte1_index(addr);
6051 src_pte1 = src_pmap->pm_pt1[pte1_idx];
6052 if (pte1_is_section(src_pte1)) {
6053 if ((addr & PTE1_OFFSET) != 0 ||
6054 (addr + PTE1_SIZE) > end_addr)
6055 continue;
6056 if (dst_pmap->pm_pt1[pte1_idx] == 0 &&
6057 (!pte1_is_managed(src_pte1) ||
6058 pmap_pv_insert_pte1(dst_pmap, addr, src_pte1,
6059 PMAP_ENTER_NORECLAIM))) {
6060 dst_pmap->pm_pt1[pte1_idx] = src_pte1 &
6061 ~PTE1_W;
6062 dst_pmap->pm_stats.resident_count +=
6063 PTE1_SIZE / PAGE_SIZE;
6064 pmap_pte1_mappings++;
6065 }
6066 continue;
6067 } else if (!pte1_is_link(src_pte1))
6068 continue;
6069
6070 src_mpt2pg = PHYS_TO_VM_PAGE(pte1_link_pa(src_pte1));
6071
6072 /*
6073 * We leave PT2s to be linked from PT1 even if they are not
6074 * referenced until all PT2s in a page are without reference.
6075 *
6076 * QQQ: It could be changed ...
6077 */
6078 #if 0 /* single_pt2_link_is_cleared */
6079 KASSERT(pt2_wirecount_get(src_mpt2pg, pte1_idx) > 0,
6080 ("%s: source page table page is unused", __func__));
6081 #else
6082 if (pt2_wirecount_get(src_mpt2pg, pte1_idx) == 0)
6083 continue;
6084 #endif
6085 if (nextva > end_addr)
6086 nextva = end_addr;
6087
6088 src_pte2p = pt2map_entry(addr);
6089 while (addr < nextva) {
6090 pt2_entry_t temp_pte2;
6091 temp_pte2 = pte2_load(src_pte2p);
6092 /*
6093 * we only virtual copy managed pages
6094 */
6095 if (pte2_is_managed(temp_pte2)) {
6096 dst_mpt2pg = pmap_allocpte2(dst_pmap, addr,
6097 PMAP_ENTER_NOSLEEP);
6098 if (dst_mpt2pg == NULL)
6099 goto out;
6100 dst_pte2p = pmap_pte2_quick(dst_pmap, addr);
6101 if (!pte2_is_valid(pte2_load(dst_pte2p)) &&
6102 pmap_try_insert_pv_entry(dst_pmap, addr,
6103 PHYS_TO_VM_PAGE(pte2_pa(temp_pte2)))) {
6104 /*
6105 * Clear the wired, modified, and
6106 * accessed (referenced) bits
6107 * during the copy.
6108 */
6109 temp_pte2 &= ~(PTE2_W | PTE2_A);
6110 temp_pte2 |= PTE2_NM;
6111 pte2_store(dst_pte2p, temp_pte2);
6112 dst_pmap->pm_stats.resident_count++;
6113 } else {
6114 SLIST_INIT(&free);
6115 if (pmap_unwire_pt2(dst_pmap, addr,
6116 dst_mpt2pg, &free)) {
6117 pmap_tlb_flush(dst_pmap, addr);
6118 vm_page_free_pages_toq(&free,
6119 false);
6120 }
6121 goto out;
6122 }
6123 if (pt2_wirecount_get(dst_mpt2pg, pte1_idx) >=
6124 pt2_wirecount_get(src_mpt2pg, pte1_idx))
6125 break;
6126 }
6127 addr += PAGE_SIZE;
6128 src_pte2p++;
6129 }
6130 }
6131 out:
6132 sched_unpin();
6133 rw_wunlock(&pvh_global_lock);
6134 PMAP_UNLOCK(src_pmap);
6135 PMAP_UNLOCK(dst_pmap);
6136 }
6137
6138 /*
6139 * Increase the starting virtual address of the given mapping if a
6140 * different alignment might result in more section mappings.
6141 */
6142 void
pmap_align_superpage(vm_object_t object,vm_ooffset_t offset,vm_offset_t * addr,vm_size_t size)6143 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6144 vm_offset_t *addr, vm_size_t size)
6145 {
6146 vm_offset_t pte1_offset;
6147
6148 if (size < PTE1_SIZE)
6149 return;
6150 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6151 offset += ptoa(object->pg_color);
6152 pte1_offset = offset & PTE1_OFFSET;
6153 if (size - ((PTE1_SIZE - pte1_offset) & PTE1_OFFSET) < PTE1_SIZE ||
6154 (*addr & PTE1_OFFSET) == pte1_offset)
6155 return;
6156 if ((*addr & PTE1_OFFSET) < pte1_offset)
6157 *addr = pte1_trunc(*addr) + pte1_offset;
6158 else
6159 *addr = pte1_roundup(*addr) + pte1_offset;
6160 }
6161
6162 void
pmap_activate(struct thread * td)6163 pmap_activate(struct thread *td)
6164 {
6165 pmap_t pmap, oldpmap;
6166 u_int cpuid, ttb;
6167
6168 PDEBUG(9, printf("%s: td = %08x\n", __func__, (uint32_t)td));
6169
6170 critical_enter();
6171 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6172 oldpmap = PCPU_GET(curpmap);
6173 cpuid = PCPU_GET(cpuid);
6174
6175 #if defined(SMP)
6176 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6177 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6178 #else
6179 CPU_CLR(cpuid, &oldpmap->pm_active);
6180 CPU_SET(cpuid, &pmap->pm_active);
6181 #endif
6182
6183 ttb = pmap_ttb_get(pmap);
6184
6185 /*
6186 * pmap_activate is for the current thread on the current cpu
6187 */
6188 td->td_pcb->pcb_pagedir = ttb;
6189 cp15_ttbr_set(ttb);
6190 PCPU_SET(curpmap, pmap);
6191 critical_exit();
6192 }
6193
6194 void
pmap_active_cpus(pmap_t pmap,cpuset_t * res)6195 pmap_active_cpus(pmap_t pmap, cpuset_t *res)
6196 {
6197 *res = pmap->pm_active;
6198 }
6199
6200 /*
6201 * Perform the pmap work for mincore(2). If the page is not both referenced and
6202 * modified by this pmap, returns its physical address so that the caller can
6203 * find other mappings.
6204 */
6205 int
pmap_mincore(pmap_t pmap,vm_offset_t addr,vm_paddr_t * pap)6206 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
6207 {
6208 pt1_entry_t *pte1p, pte1;
6209 pt2_entry_t *pte2p, pte2;
6210 vm_paddr_t pa;
6211 bool managed;
6212 int val;
6213
6214 PMAP_LOCK(pmap);
6215 pte1p = pmap_pte1(pmap, addr);
6216 pte1 = pte1_load(pte1p);
6217 if (pte1_is_section(pte1)) {
6218 pa = trunc_page(pte1_pa(pte1) | (addr & PTE1_OFFSET));
6219 managed = pte1_is_managed(pte1);
6220 val = MINCORE_PSIND(1) | MINCORE_INCORE;
6221 if (pte1_is_dirty(pte1))
6222 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6223 if (pte1 & PTE1_A)
6224 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6225 } else if (pte1_is_link(pte1)) {
6226 pte2p = pmap_pte2(pmap, addr);
6227 pte2 = pte2_load(pte2p);
6228 pmap_pte2_release(pte2p);
6229 pa = pte2_pa(pte2);
6230 managed = pte2_is_managed(pte2);
6231 val = MINCORE_INCORE;
6232 if (pte2_is_dirty(pte2))
6233 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6234 if (pte2 & PTE2_A)
6235 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6236 } else {
6237 managed = false;
6238 val = 0;
6239 }
6240 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6241 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
6242 *pap = pa;
6243 }
6244 PMAP_UNLOCK(pmap);
6245 return (val);
6246 }
6247
6248 void
pmap_kenter_device(vm_offset_t va,vm_size_t size,vm_paddr_t pa)6249 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
6250 {
6251 vm_offset_t sva;
6252 uint32_t l2attr;
6253
6254 KASSERT((size & PAGE_MASK) == 0,
6255 ("%s: device mapping not page-sized", __func__));
6256
6257 sva = va;
6258 l2attr = vm_memattr_to_pte2(VM_MEMATTR_DEVICE);
6259 while (size != 0) {
6260 pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, l2attr);
6261 va += PAGE_SIZE;
6262 pa += PAGE_SIZE;
6263 size -= PAGE_SIZE;
6264 }
6265 tlb_flush_range(sva, va - sva);
6266 }
6267
6268 void
pmap_kremove_device(vm_offset_t va,vm_size_t size)6269 pmap_kremove_device(vm_offset_t va, vm_size_t size)
6270 {
6271 vm_offset_t sva;
6272
6273 KASSERT((size & PAGE_MASK) == 0,
6274 ("%s: device mapping not page-sized", __func__));
6275
6276 sva = va;
6277 while (size != 0) {
6278 pmap_kremove(va);
6279 va += PAGE_SIZE;
6280 size -= PAGE_SIZE;
6281 }
6282 tlb_flush_range(sva, va - sva);
6283 }
6284
6285 void
pmap_set_pcb_pagedir(pmap_t pmap,struct pcb * pcb)6286 pmap_set_pcb_pagedir(pmap_t pmap, struct pcb *pcb)
6287 {
6288
6289 pcb->pcb_pagedir = pmap_ttb_get(pmap);
6290 }
6291
6292 /*
6293 * Clean L1 data cache range by physical address.
6294 * The range must be within a single page.
6295 */
6296 static void
pmap_dcache_wb_pou(vm_paddr_t pa,vm_size_t size,uint32_t attr)6297 pmap_dcache_wb_pou(vm_paddr_t pa, vm_size_t size, uint32_t attr)
6298 {
6299 pt2_entry_t *cmap2_pte2p;
6300 struct pcpu *pc;
6301
6302 KASSERT(((pa & PAGE_MASK) + size) <= PAGE_SIZE,
6303 ("%s: not on single page", __func__));
6304
6305 sched_pin();
6306 pc = get_pcpu();
6307 cmap2_pte2p = pc->pc_cmap2_pte2p;
6308 mtx_lock(&pc->pc_cmap_lock);
6309 if (pte2_load(cmap2_pte2p) != 0)
6310 panic("%s: CMAP2 busy", __func__);
6311 pte2_store(cmap2_pte2p, PTE2_KERN_NG(pa, PTE2_AP_KRW, attr));
6312 dcache_wb_pou((vm_offset_t)pc->pc_cmap2_addr + (pa & PAGE_MASK), size);
6313 pte2_clear(cmap2_pte2p);
6314 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6315 sched_unpin();
6316 mtx_unlock(&pc->pc_cmap_lock);
6317 }
6318
6319 /*
6320 * Sync instruction cache range which is not mapped yet.
6321 */
6322 void
cache_icache_sync_fresh(vm_offset_t va,vm_paddr_t pa,vm_size_t size)6323 cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
6324 {
6325 uint32_t len, offset;
6326 vm_page_t m;
6327
6328 /* Write back d-cache on given address range. */
6329 offset = pa & PAGE_MASK;
6330 for ( ; size != 0; size -= len, pa += len, offset = 0) {
6331 len = min(PAGE_SIZE - offset, size);
6332 m = PHYS_TO_VM_PAGE(pa);
6333 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6334 __func__, pa));
6335 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6336 }
6337 /*
6338 * I-cache is VIPT. Only way how to flush all virtual mappings
6339 * on given physical address is to invalidate all i-cache.
6340 */
6341 icache_inv_all();
6342 }
6343
6344 void
pmap_sync_icache(pmap_t pmap,vm_offset_t va,vm_size_t size)6345 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t size)
6346 {
6347
6348 /* Write back d-cache on given address range. */
6349 if (va >= VM_MIN_KERNEL_ADDRESS) {
6350 dcache_wb_pou(va, size);
6351 } else {
6352 uint32_t len, offset;
6353 vm_paddr_t pa;
6354 vm_page_t m;
6355
6356 offset = va & PAGE_MASK;
6357 for ( ; size != 0; size -= len, va += len, offset = 0) {
6358 pa = pmap_extract(pmap, va); /* offset is preserved */
6359 len = min(PAGE_SIZE - offset, size);
6360 m = PHYS_TO_VM_PAGE(pa);
6361 KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
6362 __func__, pa));
6363 pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
6364 }
6365 }
6366 /*
6367 * I-cache is VIPT. Only way how to flush all virtual mappings
6368 * on given physical address is to invalidate all i-cache.
6369 */
6370 icache_inv_all();
6371 }
6372
6373 /*
6374 * The implementation of pmap_fault() uses IN_RANGE2() macro which
6375 * depends on the fact that given range size is a power of 2.
6376 */
6377 CTASSERT(powerof2(NB_IN_PT1));
6378 CTASSERT(powerof2(PT2MAP_SIZE));
6379
6380 #define IN_RANGE2(addr, start, size) \
6381 ((vm_offset_t)(start) == ((vm_offset_t)(addr) & ~((size) - 1)))
6382
6383 /*
6384 * Handle access and R/W emulation faults.
6385 */
6386 int
pmap_fault(pmap_t pmap,vm_offset_t far,uint32_t fsr,int idx,bool usermode)6387 pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
6388 {
6389 pt1_entry_t *pte1p, pte1;
6390 pt2_entry_t *pte2p, pte2;
6391
6392 if (pmap == NULL)
6393 pmap = kernel_pmap;
6394
6395 /*
6396 * In kernel, we should never get abort with FAR which is in range of
6397 * pmap->pm_pt1 or PT2MAP address spaces. If it happens, stop here
6398 * and print out a useful abort message and even get to the debugger
6399 * otherwise it likely ends with never ending loop of aborts.
6400 */
6401 if (__predict_false(IN_RANGE2(far, pmap->pm_pt1, NB_IN_PT1))) {
6402 /*
6403 * All L1 tables should always be mapped and present.
6404 * However, we check only current one herein. For user mode,
6405 * only permission abort from malicious user is not fatal.
6406 * And alignment abort as it may have higher priority.
6407 */
6408 if (!usermode || (idx != FAULT_ALIGN && idx != FAULT_PERM_L2)) {
6409 CTR4(KTR_PMAP, "%s: pmap %#x pm_pt1 %#x far %#x",
6410 __func__, pmap, pmap->pm_pt1, far);
6411 panic("%s: pm_pt1 abort", __func__);
6412 }
6413 return (KERN_INVALID_ADDRESS);
6414 }
6415 if (__predict_false(IN_RANGE2(far, PT2MAP, PT2MAP_SIZE))) {
6416 /*
6417 * PT2MAP should be always mapped and present in current
6418 * L1 table. However, only existing L2 tables are mapped
6419 * in PT2MAP. For user mode, only L2 translation abort and
6420 * permission abort from malicious user is not fatal.
6421 * And alignment abort as it may have higher priority.
6422 */
6423 if (!usermode || (idx != FAULT_ALIGN &&
6424 idx != FAULT_TRAN_L2 && idx != FAULT_PERM_L2)) {
6425 CTR4(KTR_PMAP, "%s: pmap %#x PT2MAP %#x far %#x",
6426 __func__, pmap, PT2MAP, far);
6427 panic("%s: PT2MAP abort", __func__);
6428 }
6429 return (KERN_INVALID_ADDRESS);
6430 }
6431
6432 /*
6433 * A pmap lock is used below for handling of access and R/W emulation
6434 * aborts. They were handled by atomic operations before so some
6435 * analysis of new situation is needed to answer the following question:
6436 * Is it safe to use the lock even for these aborts?
6437 *
6438 * There may happen two cases in general:
6439 *
6440 * (1) Aborts while the pmap lock is locked already - this should not
6441 * happen as pmap lock is not recursive. However, under pmap lock only
6442 * internal kernel data should be accessed and such data should be
6443 * mapped with A bit set and NM bit cleared. If double abort happens,
6444 * then a mapping of data which has caused it must be fixed. Further,
6445 * all new mappings are always made with A bit set and the bit can be
6446 * cleared only on managed mappings.
6447 *
6448 * (2) Aborts while another lock(s) is/are locked - this already can
6449 * happen. However, there is no difference here if it's either access or
6450 * R/W emulation abort, or if it's some other abort.
6451 */
6452
6453 PMAP_LOCK(pmap);
6454 #ifdef INVARIANTS
6455 pte1 = pte1_load(pmap_pte1(pmap, far));
6456 if (pte1_is_link(pte1)) {
6457 /*
6458 * Check in advance that associated L2 page table is mapped into
6459 * PT2MAP space. Note that faulty access to not mapped L2 page
6460 * table is caught in more general check above where "far" is
6461 * checked that it does not lay in PT2MAP space. Note also that
6462 * L1 page table and PT2TAB always exist and are mapped.
6463 */
6464 pte2 = pt2tab_load(pmap_pt2tab_entry(pmap, far));
6465 if (!pte2_is_valid(pte2))
6466 panic("%s: missing L2 page table (%p, %#x)",
6467 __func__, pmap, far);
6468 }
6469 #endif
6470 #ifdef SMP
6471 /*
6472 * Special treatment is due to break-before-make approach done when
6473 * pte1 is updated for userland mapping during section promotion or
6474 * demotion. If not caught here, pmap_enter() can find a section
6475 * mapping on faulting address. That is not allowed.
6476 */
6477 if (idx == FAULT_TRAN_L1 && usermode && cp15_ats1cur_check(far) == 0) {
6478 PMAP_UNLOCK(pmap);
6479 return (KERN_SUCCESS);
6480 }
6481 #endif
6482 /*
6483 * Access bits for page and section. Note that the entry
6484 * is not in TLB yet, so TLB flush is not necessary.
6485 *
6486 * QQQ: This is hardware emulation, we do not call userret()
6487 * for aborts from user mode.
6488 */
6489 if (idx == FAULT_ACCESS_L2) {
6490 pte1 = pte1_load(pmap_pte1(pmap, far));
6491 if (pte1_is_link(pte1)) {
6492 /* L2 page table should exist and be mapped. */
6493 pte2p = pt2map_entry(far);
6494 pte2 = pte2_load(pte2p);
6495 if (pte2_is_valid(pte2)) {
6496 pte2_store(pte2p, pte2 | PTE2_A);
6497 PMAP_UNLOCK(pmap);
6498 return (KERN_SUCCESS);
6499 }
6500 } else {
6501 /*
6502 * We got L2 access fault but PTE1 is not a link.
6503 * Probably some race happened, do nothing.
6504 */
6505 CTR3(KTR_PMAP, "%s: FAULT_ACCESS_L2 - pmap %#x far %#x",
6506 __func__, pmap, far);
6507 PMAP_UNLOCK(pmap);
6508 return (KERN_SUCCESS);
6509 }
6510 }
6511 if (idx == FAULT_ACCESS_L1) {
6512 pte1p = pmap_pte1(pmap, far);
6513 pte1 = pte1_load(pte1p);
6514 if (pte1_is_section(pte1)) {
6515 pte1_store(pte1p, pte1 | PTE1_A);
6516 PMAP_UNLOCK(pmap);
6517 return (KERN_SUCCESS);
6518 } else {
6519 /*
6520 * We got L1 access fault but PTE1 is not section
6521 * mapping. Probably some race happened, do nothing.
6522 */
6523 CTR3(KTR_PMAP, "%s: FAULT_ACCESS_L1 - pmap %#x far %#x",
6524 __func__, pmap, far);
6525 PMAP_UNLOCK(pmap);
6526 return (KERN_SUCCESS);
6527 }
6528 }
6529
6530 /*
6531 * Handle modify bits for page and section. Note that the modify
6532 * bit is emulated by software. So PTEx_RO is software read only
6533 * bit and PTEx_NM flag is real hardware read only bit.
6534 *
6535 * QQQ: This is hardware emulation, we do not call userret()
6536 * for aborts from user mode.
6537 */
6538 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L2)) {
6539 pte1 = pte1_load(pmap_pte1(pmap, far));
6540 if (pte1_is_link(pte1)) {
6541 /* L2 page table should exist and be mapped. */
6542 pte2p = pt2map_entry(far);
6543 pte2 = pte2_load(pte2p);
6544 if (pte2_is_valid(pte2) && !(pte2 & PTE2_RO) &&
6545 (pte2 & PTE2_NM)) {
6546 pte2_store(pte2p, pte2 & ~PTE2_NM);
6547 tlb_flush(trunc_page(far));
6548 PMAP_UNLOCK(pmap);
6549 return (KERN_SUCCESS);
6550 }
6551 } else {
6552 /*
6553 * We got L2 permission fault but PTE1 is not a link.
6554 * Probably some race happened, do nothing.
6555 */
6556 CTR3(KTR_PMAP, "%s: FAULT_PERM_L2 - pmap %#x far %#x",
6557 __func__, pmap, far);
6558 PMAP_UNLOCK(pmap);
6559 return (KERN_SUCCESS);
6560 }
6561 }
6562 if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L1)) {
6563 pte1p = pmap_pte1(pmap, far);
6564 pte1 = pte1_load(pte1p);
6565 if (pte1_is_section(pte1)) {
6566 if (!(pte1 & PTE1_RO) && (pte1 & PTE1_NM)) {
6567 pte1_store(pte1p, pte1 & ~PTE1_NM);
6568 tlb_flush(pte1_trunc(far));
6569 PMAP_UNLOCK(pmap);
6570 return (KERN_SUCCESS);
6571 }
6572 } else {
6573 /*
6574 * We got L1 permission fault but PTE1 is not section
6575 * mapping. Probably some race happened, do nothing.
6576 */
6577 CTR3(KTR_PMAP, "%s: FAULT_PERM_L1 - pmap %#x far %#x",
6578 __func__, pmap, far);
6579 PMAP_UNLOCK(pmap);
6580 return (KERN_SUCCESS);
6581 }
6582 }
6583
6584 /*
6585 * QQQ: The previous code, mainly fast handling of access and
6586 * modify bits aborts, could be moved to ASM. Now we are
6587 * starting to deal with not fast aborts.
6588 */
6589 PMAP_UNLOCK(pmap);
6590 return (KERN_FAILURE);
6591 }
6592
6593 #if defined(PMAP_DEBUG)
6594 /*
6595 * Reusing of KVA used in pmap_zero_page function !!!
6596 */
6597 static void
pmap_zero_page_check(vm_page_t m)6598 pmap_zero_page_check(vm_page_t m)
6599 {
6600 pt2_entry_t *cmap2_pte2p;
6601 uint32_t *p, *end;
6602 struct pcpu *pc;
6603
6604 sched_pin();
6605 pc = get_pcpu();
6606 cmap2_pte2p = pc->pc_cmap2_pte2p;
6607 mtx_lock(&pc->pc_cmap_lock);
6608 if (pte2_load(cmap2_pte2p) != 0)
6609 panic("%s: CMAP2 busy", __func__);
6610 pte2_store(cmap2_pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
6611 vm_page_pte2_attr(m)));
6612 end = (uint32_t*)(pc->pc_cmap2_addr + PAGE_SIZE);
6613 for (p = (uint32_t*)pc->pc_cmap2_addr; p < end; p++)
6614 if (*p != 0)
6615 panic("%s: page %p not zero, va: %p", __func__, m,
6616 pc->pc_cmap2_addr);
6617 pte2_clear(cmap2_pte2p);
6618 tlb_flush((vm_offset_t)pc->pc_cmap2_addr);
6619 sched_unpin();
6620 mtx_unlock(&pc->pc_cmap_lock);
6621 }
6622
6623 int
pmap_pid_dump(int pid)6624 pmap_pid_dump(int pid)
6625 {
6626 pmap_t pmap;
6627 struct proc *p;
6628 int npte2 = 0;
6629 int i, j, index;
6630
6631 sx_slock(&allproc_lock);
6632 FOREACH_PROC_IN_SYSTEM(p) {
6633 if (p->p_pid != pid || p->p_vmspace == NULL)
6634 continue;
6635 index = 0;
6636 pmap = vmspace_pmap(p->p_vmspace);
6637 for (i = 0; i < NPTE1_IN_PT1; i++) {
6638 pt1_entry_t pte1;
6639 pt2_entry_t *pte2p, pte2;
6640 vm_offset_t base, va;
6641 vm_paddr_t pa;
6642 vm_page_t m;
6643
6644 base = i << PTE1_SHIFT;
6645 pte1 = pte1_load(&pmap->pm_pt1[i]);
6646
6647 if (pte1_is_section(pte1)) {
6648 /*
6649 * QQQ: Do something here!
6650 */
6651 } else if (pte1_is_link(pte1)) {
6652 for (j = 0; j < NPTE2_IN_PT2; j++) {
6653 va = base + (j << PAGE_SHIFT);
6654 if (va >= VM_MIN_KERNEL_ADDRESS) {
6655 if (index) {
6656 index = 0;
6657 printf("\n");
6658 }
6659 sx_sunlock(&allproc_lock);
6660 return (npte2);
6661 }
6662 pte2p = pmap_pte2(pmap, va);
6663 pte2 = pte2_load(pte2p);
6664 pmap_pte2_release(pte2p);
6665 if (!pte2_is_valid(pte2))
6666 continue;
6667
6668 pa = pte2_pa(pte2);
6669 m = PHYS_TO_VM_PAGE(pa);
6670 printf("va: 0x%x, pa: 0x%x, w: %d, "
6671 "f: 0x%x", va, pa,
6672 m->ref_count, m->flags);
6673 npte2++;
6674 index++;
6675 if (index >= 2) {
6676 index = 0;
6677 printf("\n");
6678 } else {
6679 printf(" ");
6680 }
6681 }
6682 }
6683 }
6684 }
6685 sx_sunlock(&allproc_lock);
6686 return (npte2);
6687 }
6688
6689 #endif
6690
6691 #ifdef DDB
6692 static pt2_entry_t *
pmap_pte2_ddb(pmap_t pmap,vm_offset_t va)6693 pmap_pte2_ddb(pmap_t pmap, vm_offset_t va)
6694 {
6695 pt1_entry_t pte1;
6696 vm_paddr_t pt2pg_pa;
6697
6698 pte1 = pte1_load(pmap_pte1(pmap, va));
6699 if (!pte1_is_link(pte1))
6700 return (NULL);
6701
6702 if (pmap_is_current(pmap))
6703 return (pt2map_entry(va));
6704
6705 /* Note that L2 page table size is not equal to PAGE_SIZE. */
6706 pt2pg_pa = trunc_page(pte1_link_pa(pte1));
6707 if (pte2_pa(pte2_load(PMAP3)) != pt2pg_pa) {
6708 pte2_store(PMAP3, PTE2_KPT(pt2pg_pa));
6709 #ifdef SMP
6710 PMAP3cpu = PCPU_GET(cpuid);
6711 #endif
6712 tlb_flush_local((vm_offset_t)PADDR3);
6713 }
6714 #ifdef SMP
6715 else if (PMAP3cpu != PCPU_GET(cpuid)) {
6716 PMAP3cpu = PCPU_GET(cpuid);
6717 tlb_flush_local((vm_offset_t)PADDR3);
6718 }
6719 #endif
6720 return (PADDR3 + (arm32_btop(va) & (NPTE2_IN_PG - 1)));
6721 }
6722
6723 static void
dump_pmap(pmap_t pmap)6724 dump_pmap(pmap_t pmap)
6725 {
6726
6727 printf("pmap %p\n", pmap);
6728 printf(" pm_pt1: %p\n", pmap->pm_pt1);
6729 printf(" pm_pt2tab: %p\n", pmap->pm_pt2tab);
6730 printf(" pm_active: 0x%08lX\n", pmap->pm_active.__bits[0]);
6731 }
6732
DB_SHOW_COMMAND(pmaps,pmap_list_pmaps)6733 DB_SHOW_COMMAND(pmaps, pmap_list_pmaps)
6734 {
6735
6736 pmap_t pmap;
6737 LIST_FOREACH(pmap, &allpmaps, pm_list) {
6738 dump_pmap(pmap);
6739 }
6740 }
6741
6742 static int
pte2_class(pt2_entry_t pte2)6743 pte2_class(pt2_entry_t pte2)
6744 {
6745 int cls;
6746
6747 cls = (pte2 >> 2) & 0x03;
6748 cls |= (pte2 >> 4) & 0x04;
6749 return (cls);
6750 }
6751
6752 static void
dump_section(pmap_t pmap,uint32_t pte1_idx)6753 dump_section(pmap_t pmap, uint32_t pte1_idx)
6754 {
6755 }
6756
6757 static void
dump_link(pmap_t pmap,uint32_t pte1_idx,bool invalid_ok)6758 dump_link(pmap_t pmap, uint32_t pte1_idx, bool invalid_ok)
6759 {
6760 uint32_t i;
6761 vm_offset_t va;
6762 pt2_entry_t *pte2p, pte2;
6763 vm_page_t m;
6764
6765 va = pte1_idx << PTE1_SHIFT;
6766 pte2p = pmap_pte2_ddb(pmap, va);
6767 for (i = 0; i < NPTE2_IN_PT2; i++, pte2p++, va += PAGE_SIZE) {
6768 pte2 = pte2_load(pte2p);
6769 if (pte2 == 0)
6770 continue;
6771 if (!pte2_is_valid(pte2)) {
6772 printf(" 0x%08X: 0x%08X", va, pte2);
6773 if (!invalid_ok)
6774 printf(" - not valid !!!");
6775 printf("\n");
6776 continue;
6777 }
6778 m = PHYS_TO_VM_PAGE(pte2_pa(pte2));
6779 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, g:%d, m:%p", va , pte2,
6780 pte2_class(pte2), !!(pte2 & PTE2_S), !(pte2 & PTE2_NG), m);
6781 if (m != NULL) {
6782 printf(" v:%d w:%d f:0x%04X\n", m->valid,
6783 m->ref_count, m->flags);
6784 } else {
6785 printf("\n");
6786 }
6787 }
6788 }
6789
6790 static __inline bool
is_pv_chunk_space(vm_offset_t va)6791 is_pv_chunk_space(vm_offset_t va)
6792 {
6793
6794 if ((((vm_offset_t)pv_chunkbase) <= va) &&
6795 (va < ((vm_offset_t)pv_chunkbase + PAGE_SIZE * pv_maxchunks)))
6796 return (true);
6797 return (false);
6798 }
6799
DB_SHOW_COMMAND(pmap,pmap_pmap_print)6800 DB_SHOW_COMMAND(pmap, pmap_pmap_print)
6801 {
6802 /* XXX convert args. */
6803 pmap_t pmap = (pmap_t)addr;
6804 pt1_entry_t pte1;
6805 pt2_entry_t pte2;
6806 vm_offset_t va, eva;
6807 vm_page_t m;
6808 uint32_t i;
6809 bool invalid_ok, dump_link_ok, dump_pv_chunk;
6810
6811 if (have_addr) {
6812 pmap_t pm;
6813
6814 LIST_FOREACH(pm, &allpmaps, pm_list)
6815 if (pm == pmap) break;
6816 if (pm == NULL) {
6817 printf("given pmap %p is not in allpmaps list\n", pmap);
6818 return;
6819 }
6820 } else
6821 pmap = PCPU_GET(curpmap);
6822
6823 eva = (modif[0] == 'u') ? VM_MAXUSER_ADDRESS : 0xFFFFFFFF;
6824 dump_pv_chunk = false; /* XXX evaluate from modif[] */
6825
6826 printf("pmap: 0x%08X\n", (uint32_t)pmap);
6827 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6828 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6829
6830 for(i = 0; i < NPTE1_IN_PT1; i++) {
6831 pte1 = pte1_load(&pmap->pm_pt1[i]);
6832 if (pte1 == 0)
6833 continue;
6834 va = i << PTE1_SHIFT;
6835 if (va >= eva)
6836 break;
6837
6838 if (pte1_is_section(pte1)) {
6839 printf("0x%08X: Section 0x%08X, s:%d g:%d\n", va, pte1,
6840 !!(pte1 & PTE1_S), !(pte1 & PTE1_NG));
6841 dump_section(pmap, i);
6842 } else if (pte1_is_link(pte1)) {
6843 dump_link_ok = true;
6844 invalid_ok = false;
6845 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6846 m = PHYS_TO_VM_PAGE(pte1_link_pa(pte1));
6847 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X m: %p",
6848 va, pte1, pte2, m);
6849 if (is_pv_chunk_space(va)) {
6850 printf(" - pv_chunk space");
6851 if (dump_pv_chunk)
6852 invalid_ok = true;
6853 else
6854 dump_link_ok = false;
6855 }
6856 else if (m != NULL)
6857 printf(" w:%d w2:%u", m->ref_count,
6858 pt2_wirecount_get(m, pte1_index(va)));
6859 if (pte2 == 0)
6860 printf(" !!! pt2tab entry is ZERO");
6861 else if (pte2_pa(pte1) != pte2_pa(pte2))
6862 printf(" !!! pt2tab entry is DIFFERENT - m: %p",
6863 PHYS_TO_VM_PAGE(pte2_pa(pte2)));
6864 printf("\n");
6865 if (dump_link_ok)
6866 dump_link(pmap, i, invalid_ok);
6867 } else
6868 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);
6869 }
6870 }
6871
6872 static void
dump_pt2tab(pmap_t pmap)6873 dump_pt2tab(pmap_t pmap)
6874 {
6875 uint32_t i;
6876 pt2_entry_t pte2;
6877 vm_offset_t va;
6878 vm_paddr_t pa;
6879 vm_page_t m;
6880
6881 printf("PT2TAB:\n");
6882 for (i = 0; i < PT2TAB_ENTRIES; i++) {
6883 pte2 = pte2_load(&pmap->pm_pt2tab[i]);
6884 if (!pte2_is_valid(pte2))
6885 continue;
6886 va = i << PT2TAB_SHIFT;
6887 pa = pte2_pa(pte2);
6888 m = PHYS_TO_VM_PAGE(pa);
6889 printf(" 0x%08X: 0x%08X, TEX%d, s:%d, m:%p", va, pte2,
6890 pte2_class(pte2), !!(pte2 & PTE2_S), m);
6891 if (m != NULL)
6892 printf(" , w: %d, f: 0x%04X pidx: %lld",
6893 m->ref_count, m->flags, m->pindex);
6894 printf("\n");
6895 }
6896 }
6897
DB_SHOW_COMMAND(pmap_pt2tab,pmap_pt2tab_print)6898 DB_SHOW_COMMAND(pmap_pt2tab, pmap_pt2tab_print)
6899 {
6900 /* XXX convert args. */
6901 pmap_t pmap = (pmap_t)addr;
6902 pt1_entry_t pte1;
6903 pt2_entry_t pte2;
6904 vm_offset_t va;
6905 uint32_t i, start;
6906
6907 if (have_addr) {
6908 printf("supported only on current pmap\n");
6909 return;
6910 }
6911
6912 pmap = PCPU_GET(curpmap);
6913 printf("curpmap: 0x%08X\n", (uint32_t)pmap);
6914 printf("PT2MAP: 0x%08X\n", (uint32_t)PT2MAP);
6915 printf("pt2tab: 0x%08X\n", (uint32_t)pmap->pm_pt2tab);
6916
6917 start = pte1_index((vm_offset_t)PT2MAP);
6918 for (i = start; i < (start + NPT2_IN_PT2TAB); i++) {
6919 pte1 = pte1_load(&pmap->pm_pt1[i]);
6920 if (pte1 == 0)
6921 continue;
6922 va = i << PTE1_SHIFT;
6923 if (pte1_is_section(pte1)) {
6924 printf("0x%08X: Section 0x%08X, s:%d\n", va, pte1,
6925 !!(pte1 & PTE1_S));
6926 dump_section(pmap, i);
6927 } else if (pte1_is_link(pte1)) {
6928 pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
6929 printf("0x%08X: Link 0x%08X, pt2tab: 0x%08X\n", va,
6930 pte1, pte2);
6931 if (pte2 == 0)
6932 printf(" !!! pt2tab entry is ZERO\n");
6933 } else
6934 printf("0x%08X: Invalid entry 0x%08X\n", va, pte1);
6935 }
6936 dump_pt2tab(pmap);
6937 }
6938 #endif
6939